From 645202c5d29e05d206b1998d9743816481bec4bf Mon Sep 17 00:00:00 2001 From: "guoping.liu" Date: Wed, 30 Sep 2026 17:50:30 +0800 Subject: [PATCH 1/9] feat(wifi): Update the W155S1 WiFi driver to v1.8.3.3 Replace the vendored Amlogic W1 driver in jethome-0004, v1.6.3_20240426 -> v1.8.3.3_20260310 (driver:888ce88b817c15e731df70f+612585+643887+589776). The BT sdio driver is unchanged; the aml_sdio exports it links against and the shared w1_sdio.h structures are identical. Local changes carried over from the 1.6.3 tree: - in-tree kbuild include paths ($(src)) in vmac/Makefile - WIFIMAC_PATH and WIFI_CONF_PATH under /usr/lib/firmware/w1 - rssi/reg dump paths under /lib/firmware/w1 - pairwise key dump in vm_cfg80211_add_key() commented out; it sits in the default AML_DEBUG_CFG80211 mask and would log the key - sha256_* renamed to sha256_*_i, crc32() prototype dropped (clash with kernel exports) - static print_version.c (create_version_file.pl is not run in-tree) New for 1.8.3.3: - include only if present (vendor kernels only) - drop the opt_all.h block that remapped every pr_debug() to pr_info(); its #ifndef was malformed and it made ~1000 debug prints unconditional Drop jethome-0010: 1.8.3.3 fixes the RSN-parse failure path itself. 1.6.3 did memcmp(se, oldse) with oldse == NULL on new entries, which is the wifi_mac_scan_rx+0x59c Oops seen in the field right after "RSN mcast/akm cipher wrong"; the vendor now frees new entries directly and unlinks listed ones under the caller's st_lock before freeing. RF txt files are installed from packages/bsp and are not touched. Build-tested on v6.6.129 (Image, modules, dtbs; all module symbols resolve). Not yet boot tested on hardware. --- ...home-0004-Add-Amlogic-W155S1-drivers.patch | 40872 ++++++++-------- ...fix-scan-rx-uaf-on-rsn-parse-failure.patch | 99 - 2 files changed, 21484 insertions(+), 19487 deletions(-) delete mode 100644 patch/kernel/archive/meson64-6.6/jethome-0010-wifi-fix-scan-rx-uaf-on-rsn-parse-failure.patch diff --git a/patch/kernel/archive/meson64-6.6/jethome-0004-Add-Amlogic-W155S1-drivers.patch b/patch/kernel/archive/meson64-6.6/jethome-0004-Add-Amlogic-W155S1-drivers.patch index 6ec1e9096..48a835069 100644 --- a/patch/kernel/archive/meson64-6.6/jethome-0004-Add-Amlogic-W155S1-drivers.patch +++ b/patch/kernel/archive/meson64-6.6/jethome-0004-Add-Amlogic-W155S1-drivers.patch @@ -3,447 +3,256 @@ From: "guoping.liu" Date: Thu, 15 Jan 2026 18:35:41 +0800 Subject: [PATCH 11/11] Add Amlogic W155S1 drivers +WiFi: Amlogic W1 v1.8.3.3_20260310-w1 + driver:888ce88b817c15e731df70f+612585+643887+589776 +BT: Amlogic sdio_driver_bt (unchanged) + +Local changes on top of the vendor drop: + + vmac/Makefile in-tree kbuild include paths ($(src)), + WIFIMAC_PATH=/usr/lib/firmware/w1/wifimac.txt + vmac/wifi_hal_cmd.c WIFI_CONF_PATH=/usr/lib/firmware/w1 + vmac/wifi_cfg80211.c rssi/reg dump paths under /lib/firmware/w1; + do not dump the pairwise key (AML_DEBUG_CFG80211 + is in the default debug mask); include + only if present + vmac/crypto/sha256* rename sha256_* to sha256_*_i, clashes with + exports + vmac/crypto/aml_crypto_wrap.h drop the crc32() prototype, clashes with + + vmac/opt_all.h drop the block that remapped every pr_debug() + to pr_info() (the #ifndef was malformed and it + made ~1000 debug prints unconditional) + vmac/print_version.c static copy; create_version_file.pl is not run + by in-tree kbuild + +The scan-rx RSN-parse UAF that jethome-0010 fixed on 1.6.3 is fixed by the +vendor in this drop (unlink under st_lock, then free), so 0010 is removed. --- - drivers/bluetooth/Kconfig | 1 + - drivers/bluetooth/Makefile | 1 + - drivers/bluetooth/aml_bt/Kconfig | 11 + - drivers/bluetooth/aml_bt/Makefile | 2 + - .../bluetooth/aml_bt/sdio_driver_bt/Makefile | 39 + - .../aml_bt/sdio_driver_bt/bt_hal_plateform.c | 670 ++ - .../aml_bt/sdio_driver_bt/bt_hal_plateform.h | 139 + - .../aml_bt/sdio_driver_bt/chip_intf_reg.h | 544 ++ - .../aml_bt/sdio_driver_bt/chip_pmu_reg.h | 406 + - .../aml_bt/sdio_driver_bt/rf_d_top_reg.h | 790 ++ - .../bluetooth/aml_bt/sdio_driver_bt/w1_sdio.c | 1397 ++++ - .../bluetooth/aml_bt/sdio_driver_bt/w1_sdio.h | 185 + - .../aml_bt/sdio_driver_bt/wifi_coex_addr.h | 34 + - .../aml_bt/sdio_driver_bt/wifi_drv_reg_ops.h | 41 + - .../aml_bt/sdio_driver_bt/wifi_intf_addr.h | 26 + - drivers/net/wireless/Kconfig | 1 + - drivers/net/wireless/Makefile | 1 + - drivers/net/wireless/w1/Kconfig | 13 + - drivers/net/wireless/w1/Makefile | 2 + - drivers/net/wireless/w1/common/chip_ana_reg.h | 826 ++ - .../net/wireless/w1/common/chip_bt_pmu_reg.h | 406 + - .../net/wireless/w1/common/chip_efuse_reg.h | 136 + - .../net/wireless/w1/common/chip_intf_reg.h | 544 ++ - .../wireless/w1/common/chip_pmic_i2c_reg.h | 135 + - drivers/net/wireless/w1/common/chip_pmu_reg.h | 406 + - drivers/net/wireless/w1/common/fi_cmd.h | 491 ++ - drivers/net/wireless/w1/common/fi_sdio.h | 1069 +++ - drivers/net/wireless/w1/common/fucode_em4.h | 6665 ++++++++++++++++ - drivers/net/wireless/w1/common/patch_fi_cmd.h | 159 + - .../wireless/w1/common/rf_d_adda_core_reg.h | 164 + - .../wireless/w1/common/rf_d_adda_esti_reg.h | 1390 ++++ - .../wireless/w1/common/rf_d_adda_recv_reg.h | 419 + - .../wireless/w1/common/rf_d_adda_xmit_reg.h | 1583 ++++ - drivers/net/wireless/w1/common/rf_d_rx_reg.h | 2486 ++++++ - drivers/net/wireless/w1/common/rf_d_sx_reg.h | 1093 +++ - drivers/net/wireless/w1/common/rf_d_top_reg.h | 790 ++ - drivers/net/wireless/w1/common/rf_d_tx_reg.h | 430 + - .../net/wireless/w1/common/rf_d_xosc_reg.h | 121 + - drivers/net/wireless/w1/common/wf_register.h | 21 + - .../net/wireless/w1/common/wifi_adda_addr.h | 10 + - .../net/wireless/w1/common/wifi_agc_addr.h | 110 + - .../net/wireless/w1/common/wifi_aon_addr.h | 24 + - .../net/wireless/w1/common/wifi_coex_addr.h | 34 + - .../net/wireless/w1/common/wifi_i2c_addr.h | 14 + - .../net/wireless/w1/common/wifi_intf_addr.h | 26 + - .../net/wireless/w1/common/wifi_mac_addr.h | 109 + - .../wireless/w1/common/wifi_mac_main_reg.h | 1085 +++ - .../net/wireless/w1/common/wifi_mac_rx_reg.h | 313 + - .../wireless/w1/common/wifi_mac_timer_reg.h | 565 ++ - .../net/wireless/w1/common/wifi_mac_tx_reg.h | 1341 ++++ - .../net/wireless/w1/common/wifi_ofdm_addr.h | 8 + - .../net/wireless/w1/common/wifi_phy_addr.h | 15 + - .../wireless/w1/common/wifi_sdio_cfg_addr.h | 37 + - .../wireless/w1/common/wifi_sdio_if_addr.h | 10 + - .../net/wireless/w1/common/wifi_sys_addr.h | 21 + - .../net/wireless/w1/common/wifi_top_addr.h | 27 + - .../net/wireless/w1/common/wifi_uart_addr.h | 41 + - drivers/net/wireless/w1/vmac/Makefile | 248 + - drivers/net/wireless/w1/vmac/aml_static_buf.c | 80 + - .../wireless/w1/vmac/aml_wifi_drv_cfg_0.conf | 5 + - drivers/net/wireless/w1/vmac/aml_wifi_rf.txt | 42 + - .../net/wireless/w1/vmac/aml_wifi_rf_0125.txt | 35 + - .../net/wireless/w1/vmac/aml_wifi_rf_0133.txt | 35 + - .../net/wireless/w1/vmac/aml_wifi_rf_0211.txt | 36 + - .../net/wireless/w1/vmac/aml_wifi_rf_0231.txt | 37 + - .../net/wireless/w1/vmac/aml_wifi_rf_0321.txt | 35 + - .../net/wireless/w1/vmac/aml_wifi_rf_0331.txt | 35 + - .../net/wireless/w1/vmac/aml_wifi_rf_0333.txt | 35 + - .../net/wireless/w1/vmac/aml_wifi_rf_0531.txt | 35 + - .../net/wireless/w1/vmac/aml_wifi_rf_0631.txt | 35 + - .../net/wireless/w1/vmac/aml_wifi_rf_0632.txt | 35 + - .../net/wireless/w1/vmac/aml_wifi_rf_0633.txt | 35 + - .../net/wireless/w1/vmac/aml_wifi_rf_0731.txt | 35 + - .../net/wireless/w1/vmac/aml_wifi_rf_0a11.txt | 35 + - .../net/wireless/w1/vmac/aml_wifi_rf_0a31.txt | 35 + - .../wireless/w1/vmac/aml_wifi_rf_ampak.txt | 38 + - .../wireless/w1/vmac/aml_wifi_rf_fn_link.txt | 38 + - .../net/wireless/w1/vmac/aml_wifi_rf_iton.txt | 38 + - .../wireless/w1/vmac/create_version_file.pl | 45 + - drivers/net/wireless/w1/vmac/crypto/aes-ccm.c | 211 + - drivers/net/wireless/w1/vmac/crypto/aes-ctr.c | 70 + - drivers/net/wireless/w1/vmac/crypto/aes-gcm.c | 326 + - .../w1/vmac/crypto/aes-internal-enc.c | 129 + - .../wireless/w1/vmac/crypto/aes-internal.c | 843 ++ - .../net/wireless/w1/vmac/crypto/aes-omac1.c | 172 + - drivers/net/wireless/w1/vmac/crypto/aes-siv.c | 207 + - drivers/net/wireless/w1/vmac/crypto/aes.h | 21 + - drivers/net/wireless/w1/vmac/crypto/aes_i.h | 125 + - drivers/net/wireless/w1/vmac/crypto/aes_siv.h | 21 + - .../net/wireless/w1/vmac/crypto/aes_wrap.h | 75 + - .../wireless/w1/vmac/crypto/aml_crypto_wrap.c | 67 + - .../wireless/w1/vmac/crypto/aml_crypto_wrap.h | 117 + - drivers/net/wireless/w1/vmac/crypto/ccmp.c | 383 + - .../wireless/w1/vmac/crypto/sha256-internal.c | 230 + - .../net/wireless/w1/vmac/crypto/sha256-prf.c | 109 + - drivers/net/wireless/w1/vmac/crypto/sha256.c | 104 + - drivers/net/wireless/w1/vmac/crypto/sha256.h | 30 + - .../net/wireless/w1/vmac/crypto/sha256_i.h | 25 + - .../wireless/w1/vmac/crypto/wlancrypto_wrap.h | 37 + - .../net/wireless/w1/vmac/dpd_memory_packet.h | 71 + - drivers/net/wireless/w1/vmac/opt_all.h | 268 + - drivers/net/wireless/w1/vmac/osdep.h | 300 + - drivers/net/wireless/w1/vmac/print_version.c | 6 + - .../net/wireless/w1/vmac/rc80211_minstrel.c | 870 ++ - .../net/wireless/w1/vmac/rc80211_minstrel.h | 233 + - .../wireless/w1/vmac/rc80211_minstrel_ht.c | 1348 ++++ - .../wireless/w1/vmac/rc80211_minstrel_ht.h | 284 + - .../wireless/w1/vmac/rc80211_minstrel_init.c | 907 +++ - .../wireless/w1/vmac/rc80211_minstrel_init.h | 110 + - drivers/net/wireless/w1/vmac/version.h | 1 + - .../net/wireless/w1/vmac/w1_sdio/w1_sdio.c | 1412 ++++ - .../net/wireless/w1/vmac/w1_sdio/w1_sdio.h | 185 + - drivers/net/wireless/w1/vmac/wifi_android.c | 491 ++ - drivers/net/wireless/w1/vmac/wifi_android.h | 78 + - drivers/net/wireless/w1/vmac/wifi_cfg80211.c | 7104 +++++++++++++++++ - drivers/net/wireless/w1/vmac/wifi_cfg80211.h | 381 + - .../net/wireless/w1/vmac/wifi_clock_measure.c | 267 + - .../net/wireless/w1/vmac/wifi_clock_measure.h | 60 + - drivers/net/wireless/w1/vmac/wifi_cmd_func.c | 2057 +++++ - drivers/net/wireless/w1/vmac/wifi_cmd_func.h | 138 + - drivers/net/wireless/w1/vmac/wifi_common.c | 380 + - drivers/net/wireless/w1/vmac/wifi_common.h | 32 + - drivers/net/wireless/w1/vmac/wifi_csi.h | 51 + - drivers/net/wireless/w1/vmac/wifi_debug.c | 192 + - drivers/net/wireless/w1/vmac/wifi_debug.h | 230 + - .../net/wireless/w1/vmac/wifi_drv_capture.c | 593 ++ - .../net/wireless/w1/vmac/wifi_drv_capture.h | 22 + - .../net/wireless/w1/vmac/wifi_drv_config.c | 449 ++ - .../net/wireless/w1/vmac/wifi_drv_config.h | 169 + - drivers/net/wireless/w1/vmac/wifi_drv_if.c | 446 ++ - drivers/net/wireless/w1/vmac/wifi_drv_if.h | 528 ++ - drivers/net/wireless/w1/vmac/wifi_drv_main.c | 2483 ++++++ - drivers/net/wireless/w1/vmac/wifi_drv_main.h | 616 ++ - drivers/net/wireless/w1/vmac/wifi_drv_power.c | 195 + - drivers/net/wireless/w1/vmac/wifi_drv_power.h | 51 + - drivers/net/wireless/w1/vmac/wifi_drv_recv.c | 576 ++ - drivers/net/wireless/w1/vmac/wifi_drv_recv.h | 24 + - .../net/wireless/w1/vmac/wifi_drv_reg_ops.c | 525 ++ - .../net/wireless/w1/vmac/wifi_drv_reg_ops.h | 41 + - .../net/wireless/w1/vmac/wifi_drv_statistic.c | 1259 +++ - .../net/wireless/w1/vmac/wifi_drv_statistic.h | 366 + - drivers/net/wireless/w1/vmac/wifi_drv_timer.c | 180 + - drivers/net/wireless/w1/vmac/wifi_drv_timer.h | 73 + - drivers/net/wireless/w1/vmac/wifi_drv_uapsd.c | 611 ++ - drivers/net/wireless/w1/vmac/wifi_drv_uapsd.h | 32 + - drivers/net/wireless/w1/vmac/wifi_drv_xmit.c | 3243 ++++++++ - drivers/net/wireless/w1/vmac/wifi_drv_xmit.h | 101 + - drivers/net/wireless/w1/vmac/wifi_hal.c | 3540 ++++++++ - drivers/net/wireless/w1/vmac/wifi_hal.h | 123 + - drivers/net/wireless/w1/vmac/wifi_hal_cmd.c | 2225 ++++++ - drivers/net/wireless/w1/vmac/wifi_hal_cmd.h | 91 + - drivers/net/wireless/w1/vmac/wifi_hal_com.h | 1372 ++++ - .../net/wireless/w1/vmac/wifi_hal_platform.c | 1083 +++ - .../net/wireless/w1/vmac/wifi_hal_platform.h | 53 + - .../net/wireless/w1/vmac/wifi_hal_txdesc.c | 1129 +++ - .../net/wireless/w1/vmac/wifi_hal_txdesc.h | 25 + - drivers/net/wireless/w1/vmac/wifi_hif.c | 1860 +++++ - drivers/net/wireless/w1/vmac/wifi_hif.h | 196 + - .../net/wireless/w1/vmac/wifi_iwpriv_cmd.c | 2001 +++++ - .../net/wireless/w1/vmac/wifi_iwpriv_cmd.h | 88 + - drivers/net/wireless/w1/vmac/wifi_mac.h | 1660 ++++ - drivers/net/wireless/w1/vmac/wifi_mac_acl.c | 253 + - drivers/net/wireless/w1/vmac/wifi_mac_acl.h | 10 + - .../net/wireless/w1/vmac/wifi_mac_action.c | 164 + - .../net/wireless/w1/vmac/wifi_mac_action.h | 320 + - drivers/net/wireless/w1/vmac/wifi_mac_amsdu.c | 689 ++ - drivers/net/wireless/w1/vmac/wifi_mac_amsdu.h | 84 + - drivers/net/wireless/w1/vmac/wifi_mac_arp.h | 62 + - .../net/wireless/w1/vmac/wifi_mac_beacon.c | 917 +++ - .../net/wireless/w1/vmac/wifi_mac_beacon.h | 30 + - drivers/net/wireless/w1/vmac/wifi_mac_chan.c | 1493 ++++ - drivers/net/wireless/w1/vmac/wifi_mac_chan.h | 39 + - drivers/net/wireless/w1/vmac/wifi_mac_com.h | 91 + - .../wireless/w1/vmac/wifi_mac_concurrent.c | 263 + - .../wireless/w1/vmac/wifi_mac_concurrent.h | 59 + - .../net/wireless/w1/vmac/wifi_mac_encrypt.c | 1032 +++ - .../net/wireless/w1/vmac/wifi_mac_encrypt.h | 161 + - drivers/net/wireless/w1/vmac/wifi_mac_if.c | 4444 +++++++++++ - drivers/net/wireless/w1/vmac/wifi_mac_if.h | 386 + - .../net/wireless/w1/vmac/wifi_mac_monitor.c | 448 ++ - .../net/wireless/w1/vmac/wifi_mac_monitor.h | 32 + - drivers/net/wireless/w1/vmac/wifi_mac_p2p.c | 2647 ++++++ - drivers/net/wireless/w1/vmac/wifi_mac_p2p.h | 510 ++ - drivers/net/wireless/w1/vmac/wifi_mac_pmf.c | 676 ++ - drivers/net/wireless/w1/vmac/wifi_mac_pmf.h | 91 + - drivers/net/wireless/w1/vmac/wifi_mac_power.c | 1861 +++++ - drivers/net/wireless/w1/vmac/wifi_mac_power.h | 252 + - drivers/net/wireless/w1/vmac/wifi_mac_rate.c | 914 +++ - drivers/net/wireless/w1/vmac/wifi_mac_rate.h | 57 + - drivers/net/wireless/w1/vmac/wifi_mac_recv.c | 5041 ++++++++++++ - drivers/net/wireless/w1/vmac/wifi_mac_recv.h | 93 + - .../net/wireless/w1/vmac/wifi_mac_rx_status.h | 22 + - drivers/net/wireless/w1/vmac/wifi_mac_sae.c | 198 + - drivers/net/wireless/w1/vmac/wifi_mac_sae.h | 47 + - drivers/net/wireless/w1/vmac/wifi_mac_scan.c | 2290 ++++++ - drivers/net/wireless/w1/vmac/wifi_mac_scan.h | 304 + - drivers/net/wireless/w1/vmac/wifi_mac_sta.c | 2330 ++++++ - drivers/net/wireless/w1/vmac/wifi_mac_sta.h | 587 ++ - drivers/net/wireless/w1/vmac/wifi_mac_var.h | 973 +++ - drivers/net/wireless/w1/vmac/wifi_mac_xmit.c | 3747 +++++++++ - drivers/net/wireless/w1/vmac/wifi_mac_xmit.h | 80 + - drivers/net/wireless/w1/vmac/wifi_phy.c | 346 + - drivers/net/wireless/w1/vmac/wifi_phy.h | 15 + - drivers/net/wireless/w1/vmac/wifi_pkt_desc.c | 92 + - drivers/net/wireless/w1/vmac/wifi_pkt_desc.h | 148 + - drivers/net/wireless/w1/vmac/wifi_pt_conf.h | 59 + - drivers/net/wireless/w1/vmac/wifi_pt_if.c | 361 + - drivers/net/wireless/w1/vmac/wifi_pt_if.h | 470 ++ - drivers/net/wireless/w1/vmac/wifi_pt_init.c | 1041 +++ - drivers/net/wireless/w1/vmac/wifi_pt_init.h | 249 + - .../net/wireless/w1/vmac/wifi_pt_network.c | 508 ++ - .../net/wireless/w1/vmac/wifi_pt_network.h | 90 + - drivers/net/wireless/w1/vmac/wifi_rate_ctrl.c | 78 + - drivers/net/wireless/w1/vmac/wifi_rate_ctrl.h | 127 + - drivers/net/wireless/w1/vmac/wifi_sdio.c | 2137 +++++ - drivers/net/wireless/w1/vmac/wifi_sdio.h | 194 + - .../net/wireless/w1/vmac/wifi_share_fifo.c | 517 ++ - .../net/wireless/w1/vmac/wifi_share_fifo.h | 160 + - drivers/net/wireless/w1/vmac/wifi_skbbuf.c | 9 + - drivers/net/wireless/w1/vmac/wifi_skbbuf.h | 50 + - 220 files changed, 117589 insertions(+) - create mode 100644 drivers/bluetooth/aml_bt/Kconfig - create mode 100644 drivers/bluetooth/aml_bt/Makefile - create mode 100644 drivers/bluetooth/aml_bt/sdio_driver_bt/Makefile - create mode 100644 drivers/bluetooth/aml_bt/sdio_driver_bt/bt_hal_plateform.c - create mode 100644 drivers/bluetooth/aml_bt/sdio_driver_bt/bt_hal_plateform.h - create mode 100644 drivers/bluetooth/aml_bt/sdio_driver_bt/chip_intf_reg.h - create mode 100644 drivers/bluetooth/aml_bt/sdio_driver_bt/chip_pmu_reg.h - create mode 100644 drivers/bluetooth/aml_bt/sdio_driver_bt/rf_d_top_reg.h - create mode 100644 drivers/bluetooth/aml_bt/sdio_driver_bt/w1_sdio.c - create mode 100644 drivers/bluetooth/aml_bt/sdio_driver_bt/w1_sdio.h - create mode 100644 drivers/bluetooth/aml_bt/sdio_driver_bt/wifi_coex_addr.h - create mode 100644 drivers/bluetooth/aml_bt/sdio_driver_bt/wifi_drv_reg_ops.h - create mode 100644 drivers/bluetooth/aml_bt/sdio_driver_bt/wifi_intf_addr.h - create mode 100644 drivers/net/wireless/w1/Kconfig - create mode 100755 drivers/net/wireless/w1/Makefile - create mode 100644 drivers/net/wireless/w1/common/chip_ana_reg.h - create mode 100644 drivers/net/wireless/w1/common/chip_bt_pmu_reg.h - create mode 100644 drivers/net/wireless/w1/common/chip_efuse_reg.h - create mode 100644 drivers/net/wireless/w1/common/chip_intf_reg.h - create mode 100644 drivers/net/wireless/w1/common/chip_pmic_i2c_reg.h - create mode 100644 drivers/net/wireless/w1/common/chip_pmu_reg.h - create mode 100644 drivers/net/wireless/w1/common/fi_cmd.h - create mode 100644 drivers/net/wireless/w1/common/fi_sdio.h - create mode 100644 drivers/net/wireless/w1/common/fucode_em4.h - create mode 100644 drivers/net/wireless/w1/common/patch_fi_cmd.h - create mode 100644 drivers/net/wireless/w1/common/rf_d_adda_core_reg.h - create mode 100644 drivers/net/wireless/w1/common/rf_d_adda_esti_reg.h - create mode 100644 drivers/net/wireless/w1/common/rf_d_adda_recv_reg.h - create mode 100644 drivers/net/wireless/w1/common/rf_d_adda_xmit_reg.h - create mode 100644 drivers/net/wireless/w1/common/rf_d_rx_reg.h - create mode 100644 drivers/net/wireless/w1/common/rf_d_sx_reg.h - create mode 100644 drivers/net/wireless/w1/common/rf_d_top_reg.h - create mode 100644 drivers/net/wireless/w1/common/rf_d_tx_reg.h - create mode 100644 drivers/net/wireless/w1/common/rf_d_xosc_reg.h - create mode 100644 drivers/net/wireless/w1/common/wf_register.h - create mode 100644 drivers/net/wireless/w1/common/wifi_adda_addr.h - create mode 100644 drivers/net/wireless/w1/common/wifi_agc_addr.h - create mode 100644 drivers/net/wireless/w1/common/wifi_aon_addr.h - create mode 100644 drivers/net/wireless/w1/common/wifi_coex_addr.h - create mode 100644 drivers/net/wireless/w1/common/wifi_i2c_addr.h - create mode 100644 drivers/net/wireless/w1/common/wifi_intf_addr.h - create mode 100644 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drivers/net/wireless/w1/vmac/aml_wifi_rf_0a11.txt | 35 + + drivers/net/wireless/w1/vmac/aml_wifi_rf_0a31.txt | 35 + + drivers/net/wireless/w1/vmac/aml_wifi_rf_ampak.txt | 38 + + .../net/wireless/w1/vmac/aml_wifi_rf_fn_link.txt | 38 + + drivers/net/wireless/w1/vmac/aml_wifi_rf_iton.txt | 38 + + .../net/wireless/w1/vmac/create_version_file.pl | 45 + + drivers/net/wireless/w1/vmac/crypto/aes-ccm.c | 211 + + drivers/net/wireless/w1/vmac/crypto/aes-ctr.c | 72 + + drivers/net/wireless/w1/vmac/crypto/aes-gcm.c | 326 + + .../net/wireless/w1/vmac/crypto/aes-internal-enc.c | 129 + + drivers/net/wireless/w1/vmac/crypto/aes-internal.c | 843 +++ + drivers/net/wireless/w1/vmac/crypto/aes-omac1.c | 172 + + drivers/net/wireless/w1/vmac/crypto/aes-siv.c | 207 + + drivers/net/wireless/w1/vmac/crypto/aes.h | 21 + + drivers/net/wireless/w1/vmac/crypto/aes_i.h | 125 + + drivers/net/wireless/w1/vmac/crypto/aes_siv.h | 21 + + drivers/net/wireless/w1/vmac/crypto/aes_wrap.h | 75 + + .../net/wireless/w1/vmac/crypto/aml_crypto_wrap.c | 67 + + .../net/wireless/w1/vmac/crypto/aml_crypto_wrap.h | 117 + + drivers/net/wireless/w1/vmac/crypto/ccmp.c | 383 + + .../net/wireless/w1/vmac/crypto/sha256-internal.c | 230 + + drivers/net/wireless/w1/vmac/crypto/sha256-prf.c | 109 + + drivers/net/wireless/w1/vmac/crypto/sha256.c | 104 + + drivers/net/wireless/w1/vmac/crypto/sha256.h | 30 + + drivers/net/wireless/w1/vmac/crypto/sha256_i.h | 25 + + .../net/wireless/w1/vmac/crypto/wlancrypto_wrap.h | 37 + + drivers/net/wireless/w1/vmac/dpd_memory_packet.h | 71 + + drivers/net/wireless/w1/vmac/opt_all.h | 273 + + drivers/net/wireless/w1/vmac/osdep.h | 300 + + drivers/net/wireless/w1/vmac/print_version.c | 5 + + drivers/net/wireless/w1/vmac/rc80211_minstrel.c | 877 +++ + drivers/net/wireless/w1/vmac/rc80211_minstrel.h | 233 + + drivers/net/wireless/w1/vmac/rc80211_minstrel_ht.c | 1357 ++++ + drivers/net/wireless/w1/vmac/rc80211_minstrel_ht.h | 284 + + .../net/wireless/w1/vmac/rc80211_minstrel_init.c | 907 +++ + .../net/wireless/w1/vmac/rc80211_minstrel_init.h | 110 + + drivers/net/wireless/w1/vmac/version.h | 1 + + drivers/net/wireless/w1/vmac/w1_sdio/w1_sdio.c | 1435 ++++ + drivers/net/wireless/w1/vmac/w1_sdio/w1_sdio.h | 188 + + drivers/net/wireless/w1/vmac/wifi_android.c | 491 ++ + drivers/net/wireless/w1/vmac/wifi_android.h | 78 + + drivers/net/wireless/w1/vmac/wifi_cfg80211.c | 7435 ++++++++++++++++++++ + drivers/net/wireless/w1/vmac/wifi_cfg80211.h | 393 ++ + drivers/net/wireless/w1/vmac/wifi_clock_measure.c | 267 + + drivers/net/wireless/w1/vmac/wifi_clock_measure.h | 60 + + drivers/net/wireless/w1/vmac/wifi_cmd_func.c | 2189 ++++++ + drivers/net/wireless/w1/vmac/wifi_cmd_func.h | 140 + + drivers/net/wireless/w1/vmac/wifi_common.c | 380 + + drivers/net/wireless/w1/vmac/wifi_common.h | 32 + + drivers/net/wireless/w1/vmac/wifi_csi.h | 51 + + drivers/net/wireless/w1/vmac/wifi_debug.c | 192 + + drivers/net/wireless/w1/vmac/wifi_debug.h | 230 + + drivers/net/wireless/w1/vmac/wifi_drv_capture.c | 591 ++ + drivers/net/wireless/w1/vmac/wifi_drv_capture.h | 22 + + drivers/net/wireless/w1/vmac/wifi_drv_config.c | 449 ++ + drivers/net/wireless/w1/vmac/wifi_drv_config.h | 169 + + drivers/net/wireless/w1/vmac/wifi_drv_if.c | 451 ++ + drivers/net/wireless/w1/vmac/wifi_drv_if.h | 528 ++ + drivers/net/wireless/w1/vmac/wifi_drv_main.c | 2544 +++++++ + drivers/net/wireless/w1/vmac/wifi_drv_main.h | 624 ++ + drivers/net/wireless/w1/vmac/wifi_drv_power.c | 195 + + drivers/net/wireless/w1/vmac/wifi_drv_power.h | 51 + + drivers/net/wireless/w1/vmac/wifi_drv_recv.c | 575 ++ + drivers/net/wireless/w1/vmac/wifi_drv_recv.h | 24 + + drivers/net/wireless/w1/vmac/wifi_drv_reg_ops.c | 525 ++ + drivers/net/wireless/w1/vmac/wifi_drv_reg_ops.h | 41 + + drivers/net/wireless/w1/vmac/wifi_drv_statistic.c | 1259 ++++ + drivers/net/wireless/w1/vmac/wifi_drv_statistic.h | 366 + + drivers/net/wireless/w1/vmac/wifi_drv_timer.c | 180 + + drivers/net/wireless/w1/vmac/wifi_drv_timer.h | 73 + + drivers/net/wireless/w1/vmac/wifi_drv_uapsd.c | 611 ++ + drivers/net/wireless/w1/vmac/wifi_drv_uapsd.h | 32 + + drivers/net/wireless/w1/vmac/wifi_drv_xmit.c | 3326 +++++++++ + drivers/net/wireless/w1/vmac/wifi_drv_xmit.h | 101 + + drivers/net/wireless/w1/vmac/wifi_hal.c | 3590 ++++++++++ + drivers/net/wireless/w1/vmac/wifi_hal.h | 123 + + drivers/net/wireless/w1/vmac/wifi_hal_cmd.c | 2223 ++++++ + drivers/net/wireless/w1/vmac/wifi_hal_cmd.h | 93 + + drivers/net/wireless/w1/vmac/wifi_hal_com.h | 1376 ++++ + drivers/net/wireless/w1/vmac/wifi_hal_platform.c | 1111 +++ + drivers/net/wireless/w1/vmac/wifi_hal_platform.h | 53 + + drivers/net/wireless/w1/vmac/wifi_hal_txdesc.c | 1130 +++ + drivers/net/wireless/w1/vmac/wifi_hal_txdesc.h | 25 + + drivers/net/wireless/w1/vmac/wifi_hif.c | 1944 +++++ + drivers/net/wireless/w1/vmac/wifi_hif.h | 196 + + drivers/net/wireless/w1/vmac/wifi_iwpriv_cmd.c | 2014 ++++++ + drivers/net/wireless/w1/vmac/wifi_iwpriv_cmd.h | 102 + + drivers/net/wireless/w1/vmac/wifi_mac.h | 1689 +++++ + drivers/net/wireless/w1/vmac/wifi_mac_acl.c | 253 + + drivers/net/wireless/w1/vmac/wifi_mac_acl.h | 10 + + drivers/net/wireless/w1/vmac/wifi_mac_action.c | 164 + + drivers/net/wireless/w1/vmac/wifi_mac_action.h | 335 + + drivers/net/wireless/w1/vmac/wifi_mac_amsdu.c | 689 ++ + drivers/net/wireless/w1/vmac/wifi_mac_amsdu.h | 84 + + drivers/net/wireless/w1/vmac/wifi_mac_arp.h | 62 + + drivers/net/wireless/w1/vmac/wifi_mac_beacon.c | 1112 +++ + drivers/net/wireless/w1/vmac/wifi_mac_beacon.h | 33 + + drivers/net/wireless/w1/vmac/wifi_mac_chan.c | 1697 +++++ + drivers/net/wireless/w1/vmac/wifi_mac_chan.h | 43 + + drivers/net/wireless/w1/vmac/wifi_mac_com.h | 91 + + drivers/net/wireless/w1/vmac/wifi_mac_concurrent.c | 387 + + drivers/net/wireless/w1/vmac/wifi_mac_concurrent.h | 60 + + drivers/net/wireless/w1/vmac/wifi_mac_encrypt.c | 1032 +++ + drivers/net/wireless/w1/vmac/wifi_mac_encrypt.h | 161 + + drivers/net/wireless/w1/vmac/wifi_mac_if.c | 4603 ++++++++++++ + drivers/net/wireless/w1/vmac/wifi_mac_if.h | 390 + + drivers/net/wireless/w1/vmac/wifi_mac_monitor.c | 448 ++ + drivers/net/wireless/w1/vmac/wifi_mac_monitor.h | 32 + + drivers/net/wireless/w1/vmac/wifi_mac_p2p.c | 2650 +++++++ + drivers/net/wireless/w1/vmac/wifi_mac_p2p.h | 512 ++ + drivers/net/wireless/w1/vmac/wifi_mac_pmf.c | 676 ++ + drivers/net/wireless/w1/vmac/wifi_mac_pmf.h | 91 + + drivers/net/wireless/w1/vmac/wifi_mac_power.c | 1903 +++++ + drivers/net/wireless/w1/vmac/wifi_mac_power.h | 253 + + drivers/net/wireless/w1/vmac/wifi_mac_rate.c | 929 +++ + drivers/net/wireless/w1/vmac/wifi_mac_rate.h | 57 + + drivers/net/wireless/w1/vmac/wifi_mac_recv.c | 5180 ++++++++++++++ + drivers/net/wireless/w1/vmac/wifi_mac_recv.h | 97 + + drivers/net/wireless/w1/vmac/wifi_mac_rx_status.h | 22 + + drivers/net/wireless/w1/vmac/wifi_mac_sae.c | 198 + + drivers/net/wireless/w1/vmac/wifi_mac_sae.h | 47 + + drivers/net/wireless/w1/vmac/wifi_mac_scan.c | 2353 +++++++ + drivers/net/wireless/w1/vmac/wifi_mac_scan.h | 305 + + drivers/net/wireless/w1/vmac/wifi_mac_sta.c | 2460 +++++++ + drivers/net/wireless/w1/vmac/wifi_mac_sta.h | 594 ++ + drivers/net/wireless/w1/vmac/wifi_mac_var.h | 1016 +++ + drivers/net/wireless/w1/vmac/wifi_mac_xmit.c | 3956 +++++++++++ + drivers/net/wireless/w1/vmac/wifi_mac_xmit.h | 100 + + drivers/net/wireless/w1/vmac/wifi_phy.c | 346 + + drivers/net/wireless/w1/vmac/wifi_phy.h | 15 + + drivers/net/wireless/w1/vmac/wifi_pkt_desc.c | 92 + + drivers/net/wireless/w1/vmac/wifi_pkt_desc.h | 151 + + drivers/net/wireless/w1/vmac/wifi_pt_conf.h | 59 + + drivers/net/wireless/w1/vmac/wifi_pt_if.c | 367 + + drivers/net/wireless/w1/vmac/wifi_pt_if.h | 470 ++ + drivers/net/wireless/w1/vmac/wifi_pt_init.c | 1040 +++ + drivers/net/wireless/w1/vmac/wifi_pt_init.h | 249 + + drivers/net/wireless/w1/vmac/wifi_pt_network.c | 508 ++ + drivers/net/wireless/w1/vmac/wifi_pt_network.h | 90 + + drivers/net/wireless/w1/vmac/wifi_rate_ctrl.c | 78 + + drivers/net/wireless/w1/vmac/wifi_rate_ctrl.h | 127 + + drivers/net/wireless/w1/vmac/wifi_sdio.c | 2137 ++++++ + drivers/net/wireless/w1/vmac/wifi_sdio.h | 193 + + drivers/net/wireless/w1/vmac/wifi_share_fifo.c | 517 ++ + drivers/net/wireless/w1/vmac/wifi_share_fifo.h | 160 + + drivers/net/wireless/w1/vmac/wifi_skbbuf.c | 9 + + drivers/net/wireless/w1/vmac/wifi_skbbuf.h | 50 + + 220 files changed, 119892 insertions(+) diff --git a/drivers/bluetooth/Kconfig b/drivers/bluetooth/Kconfig -index bc211c324206..9845c6782bfb 100644 +index bc211c324206b9231cba018104bfefaf1ad8ad32..9845c6782bfbc14c156a41443573442ea3325858 100644 --- a/drivers/bluetooth/Kconfig +++ b/drivers/bluetooth/Kconfig @@ -478,5 +478,6 @@ config BT_NXPUART @@ -454,7 +263,7 @@ index bc211c324206..9845c6782bfb 100644 endmenu diff --git a/drivers/bluetooth/Makefile b/drivers/bluetooth/Makefile -index 7a5967e9ac48..7f02599b24c1 100644 +index 7a5967e9ac4826b39f159ff141358147d8168bf6..7f02599b24c1d402d1ae7af525460921f1205736 100644 --- a/drivers/bluetooth/Makefile +++ b/drivers/bluetooth/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_BT_MTK) += btmtk.o @@ -467,7 +276,7 @@ index 7a5967e9ac48..7f02599b24c1 100644 diff --git a/drivers/bluetooth/aml_bt/Kconfig b/drivers/bluetooth/aml_bt/Kconfig new file mode 100644 -index 000000000000..1e32a1a600ac +index 0000000000000000000000000000000000000000..1e32a1a600ac5ae15da23b9ebca098e6f90a4dc5 --- /dev/null +++ b/drivers/bluetooth/aml_bt/Kconfig @@ -0,0 +1,11 @@ @@ -484,7 +293,7 @@ index 000000000000..1e32a1a600ac + sdio_bt. If unsure, say N. diff --git a/drivers/bluetooth/aml_bt/Makefile b/drivers/bluetooth/aml_bt/Makefile new file mode 100644 -index 000000000000..24f2766f44a5 +index 0000000000000000000000000000000000000000..24f2766f44a5b42ae805c45a3da2f7d2289a4321 --- /dev/null +++ b/drivers/bluetooth/aml_bt/Makefile @@ -0,0 +1,2 @@ @@ -492,7 +301,7 @@ index 000000000000..24f2766f44a5 +obj-$(CONFIG_AMLOGIC_BT_W1) += sdio_driver_bt/ diff --git a/drivers/bluetooth/aml_bt/sdio_driver_bt/Makefile b/drivers/bluetooth/aml_bt/sdio_driver_bt/Makefile new file mode 100644 -index 000000000000..ca50bef24625 +index 0000000000000000000000000000000000000000..ca50bef246251ac79ac090b8b3e901c8fb3dfe67 --- /dev/null +++ b/drivers/bluetooth/aml_bt/sdio_driver_bt/Makefile @@ -0,0 +1,39 @@ @@ -537,7 +346,7 @@ index 000000000000..ca50bef24625 + diff --git a/drivers/bluetooth/aml_bt/sdio_driver_bt/bt_hal_plateform.c b/drivers/bluetooth/aml_bt/sdio_driver_bt/bt_hal_plateform.c new file mode 100644 -index 000000000000..7ca5a64dc215 +index 0000000000000000000000000000000000000000..d7a318f213276bfe7adfae2d48a829e59256bf38 --- /dev/null +++ b/drivers/bluetooth/aml_bt/sdio_driver_bt/bt_hal_plateform.c @@ -0,0 +1,686 @@ @@ -1229,7 +1038,7 @@ index 000000000000..7ca5a64dc215 +MODULE_LICENSE("GPL"); diff --git a/drivers/bluetooth/aml_bt/sdio_driver_bt/bt_hal_plateform.h b/drivers/bluetooth/aml_bt/sdio_driver_bt/bt_hal_plateform.h new file mode 100644 -index 000000000000..ac7e86ea759e +index 0000000000000000000000000000000000000000..ac7e86ea759edef276e825c7a6b792d9e8449342 --- /dev/null +++ b/drivers/bluetooth/aml_bt/sdio_driver_bt/bt_hal_plateform.h @@ -0,0 +1,139 @@ @@ -1374,7 +1183,7 @@ index 000000000000..ac7e86ea759e +}; diff --git a/drivers/bluetooth/aml_bt/sdio_driver_bt/chip_intf_reg.h b/drivers/bluetooth/aml_bt/sdio_driver_bt/chip_intf_reg.h new file mode 100644 -index 000000000000..56e79b748d61 +index 0000000000000000000000000000000000000000..56e79b748d61bd907508536bc49550711b7ff778 --- /dev/null +++ b/drivers/bluetooth/aml_bt/sdio_driver_bt/chip_intf_reg.h @@ -0,0 +1,544 @@ @@ -1924,7 +1733,7 @@ index 000000000000..56e79b748d61 + diff --git a/drivers/bluetooth/aml_bt/sdio_driver_bt/chip_pmu_reg.h b/drivers/bluetooth/aml_bt/sdio_driver_bt/chip_pmu_reg.h new file mode 100644 -index 000000000000..2088eb55476d +index 0000000000000000000000000000000000000000..2088eb55476d4afe2c26ca6d82ecf89892129dac --- /dev/null +++ b/drivers/bluetooth/aml_bt/sdio_driver_bt/chip_pmu_reg.h @@ -0,0 +1,406 @@ @@ -2336,7 +2145,7 @@ index 000000000000..2088eb55476d + diff --git a/drivers/bluetooth/aml_bt/sdio_driver_bt/rf_d_top_reg.h b/drivers/bluetooth/aml_bt/sdio_driver_bt/rf_d_top_reg.h new file mode 100644 -index 000000000000..6448f506bab5 +index 0000000000000000000000000000000000000000..6448f506bab5a4413438cda30d4fc2e69271fa5e --- /dev/null +++ b/drivers/bluetooth/aml_bt/sdio_driver_bt/rf_d_top_reg.h @@ -0,0 +1,790 @@ @@ -3132,7 +2941,7 @@ index 000000000000..6448f506bab5 + diff --git a/drivers/bluetooth/aml_bt/sdio_driver_bt/w1_sdio.c b/drivers/bluetooth/aml_bt/sdio_driver_bt/w1_sdio.c new file mode 100644 -index 000000000000..8fdd9a901429 +index 0000000000000000000000000000000000000000..8fdd9a901429ebc96348c5616a30e147a4d6e2ef --- /dev/null +++ b/drivers/bluetooth/aml_bt/sdio_driver_bt/w1_sdio.c @@ -0,0 +1,1397 @@ @@ -4535,7 +4344,7 @@ index 000000000000..8fdd9a901429 +MODULE_LICENSE("GPL"); diff --git a/drivers/bluetooth/aml_bt/sdio_driver_bt/w1_sdio.h b/drivers/bluetooth/aml_bt/sdio_driver_bt/w1_sdio.h new file mode 100644 -index 000000000000..a625a427286e +index 0000000000000000000000000000000000000000..a625a427286e39331f2141c383a98e2c4fdf6ed0 --- /dev/null +++ b/drivers/bluetooth/aml_bt/sdio_driver_bt/w1_sdio.h @@ -0,0 +1,185 @@ @@ -4726,7 +4535,7 @@ index 000000000000..a625a427286e + diff --git a/drivers/bluetooth/aml_bt/sdio_driver_bt/wifi_coex_addr.h b/drivers/bluetooth/aml_bt/sdio_driver_bt/wifi_coex_addr.h new file mode 100644 -index 000000000000..68be97d11a79 +index 0000000000000000000000000000000000000000..68be97d11a79ae26359c722a1b05889fa087cfb0 --- /dev/null +++ b/drivers/bluetooth/aml_bt/sdio_driver_bt/wifi_coex_addr.h @@ -0,0 +1,34 @@ @@ -4766,7 +4575,7 @@ index 000000000000..68be97d11a79 + diff --git a/drivers/bluetooth/aml_bt/sdio_driver_bt/wifi_drv_reg_ops.h b/drivers/bluetooth/aml_bt/sdio_driver_bt/wifi_drv_reg_ops.h new file mode 100644 -index 000000000000..b2b12665c2eb +index 0000000000000000000000000000000000000000..b2b12665c2eb040e9ddb24b575dee9251c8bad22 --- /dev/null +++ b/drivers/bluetooth/aml_bt/sdio_driver_bt/wifi_drv_reg_ops.h @@ -0,0 +1,41 @@ @@ -4813,7 +4622,7 @@ index 000000000000..b2b12665c2eb +#endif diff --git a/drivers/bluetooth/aml_bt/sdio_driver_bt/wifi_intf_addr.h b/drivers/bluetooth/aml_bt/sdio_driver_bt/wifi_intf_addr.h new file mode 100644 -index 000000000000..7ec21d85f4a1 +index 0000000000000000000000000000000000000000..7ec21d85f4a191e947fc6ccbd048a16c61b173fd --- /dev/null +++ b/drivers/bluetooth/aml_bt/sdio_driver_bt/wifi_intf_addr.h @@ -0,0 +1,26 @@ @@ -4844,7 +4653,7 @@ index 000000000000..7ec21d85f4a1 + +#endif diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig -index 7555af5195ec..868feacebc38 100644 +index 7555af5195ec3f55ff83edbcdfe8f58072133295..868feacebc3885573ad9874f5eacf6b0ff7ac6b3 100644 --- a/drivers/net/wireless/Kconfig +++ b/drivers/net/wireless/Kconfig @@ -35,6 +35,7 @@ source "drivers/net/wireless/rsi/Kconfig" @@ -4856,7 +4665,7 @@ index 7555af5195ec..868feacebc38 100644 source "drivers/net/wireless/quantenna/Kconfig" diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile -index 4d7374d567d1..038a6c84df49 100644 +index 4d7374d567d18c708e6396ed8870af7543a6c3d4..038a6c84df49216d73cf60236cc2954cb99ee43f 100644 --- a/drivers/net/wireless/Makefile +++ b/drivers/net/wireless/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_WLAN_VENDOR_RSI) += rsi/ @@ -4869,7 +4678,7 @@ index 4d7374d567d1..038a6c84df49 100644 obj-$(CONFIG_WLAN) += legacy/ diff --git a/drivers/net/wireless/w1/Kconfig b/drivers/net/wireless/w1/Kconfig new file mode 100644 -index 000000000000..66fbdad58440 +index 0000000000000000000000000000000000000000..66fbdad5844086450151538b77fe068540bf9cc9 --- /dev/null +++ b/drivers/net/wireless/w1/Kconfig @@ -0,0 +1,13 @@ @@ -4888,7 +4697,7 @@ index 000000000000..66fbdad58440 + vlsicomm. If unsure, say N. diff --git a/drivers/net/wireless/w1/Makefile b/drivers/net/wireless/w1/Makefile new file mode 100755 -index 000000000000..bcf75ace3557 +index 0000000000000000000000000000000000000000..bcf75ace3557e25845ae2bed94f1e819f0078399 --- /dev/null +++ b/drivers/net/wireless/w1/Makefile @@ -0,0 +1,2 @@ @@ -4896,7 +4705,7 @@ index 000000000000..bcf75ace3557 +obj-$(CONFIG_AMLOGIC_WIFI_W1) += vmac/ diff --git a/drivers/net/wireless/w1/common/chip_ana_reg.h b/drivers/net/wireless/w1/common/chip_ana_reg.h new file mode 100644 -index 000000000000..8560cf7154e5 +index 0000000000000000000000000000000000000000..8560cf7154e5ef96829d0f9827ea6a52689fc96e --- /dev/null +++ b/drivers/net/wireless/w1/common/chip_ana_reg.h @@ -0,0 +1,826 @@ @@ -5728,7 +5537,7 @@ index 000000000000..8560cf7154e5 + diff --git a/drivers/net/wireless/w1/common/chip_bt_pmu_reg.h b/drivers/net/wireless/w1/common/chip_bt_pmu_reg.h new file mode 100644 -index 000000000000..19ca0884dfa9 +index 0000000000000000000000000000000000000000..19ca0884dfa9bc0961b67279c70febae9d48b640 --- /dev/null +++ b/drivers/net/wireless/w1/common/chip_bt_pmu_reg.h @@ -0,0 +1,406 @@ @@ -6140,149 +5949,149 @@ index 000000000000..19ca0884dfa9 + diff --git a/drivers/net/wireless/w1/common/chip_efuse_reg.h b/drivers/net/wireless/w1/common/chip_efuse_reg.h new file mode 100644 -index 000000000000..a98ab6765e4e +index 0000000000000000000000000000000000000000..90a3c9460896f668c8cf10c5f33647ebaefb0f1f --- /dev/null +++ b/drivers/net/wireless/w1/common/chip_efuse_reg.h @@ -0,0 +1,136 @@ -+#ifdef CHIP_EFUSE_REG -+#else -+#define CHIP_EFUSE_REG -+ -+ -+#define CHIP_EFUSE_REG_BASE (0xf04000) -+ -+#define EFUSE_CNTL0 (CHIP_EFUSE_REG_BASE + 0x0) -+// Bit 7 :0 tclock_high U RW default = 'h87 -+// Bit 15 :8 tclock_low U RW default = 'h27 -+// Bit 23 :16 tps_delay U RW default = 'ha -+// Bit 31 :24 tunit_delay U RW default = 'h2 -+typedef union EFUSE_CNTL0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int Tclock_high : 8; -+ unsigned int Tclock_low : 8; -+ unsigned int Tps_delay : 8; -+ unsigned int Tunit_delay : 8; -+ } b; -+} EFUSE_CNTL0_FIELD_T; -+ -+#define EFUSE_CNTL1 (CHIP_EFUSE_REG_BASE + 0x4) -+// Bit 9 :0 byte_addr U RW default = 'h0 -+// Bit 11 byte_addr_set U RW default = 'h0 -+// Bit 12 auto_wr_enable U RW default = 'h0 -+// Bit 13 auto_wr_start U RW default = 'h0 -+// Bit 14 auto_wr_busy U RO default = 'h0 -+// Bit 23 :16 byte_wdata U RW default = 'h0 -+// Bit 24 auto_rd_enable U RW default = 'h0 -+// Bit 25 auto_rd_start U RW default = 'h0 -+// Bit 26 auto_rd_busy U RO default = 'h0 -+// Bit 27 ctrl_pd U RW default = 'h1 -+// Bit 31 sim_mask_rd_dat U RW default = 'h0 -+typedef union EFUSE_CNTL1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int byte_addr : 10; -+ unsigned int rsvd_0 : 1; -+ unsigned int byte_addr_set : 1; -+ unsigned int auto_wr_enable : 1; -+ unsigned int auto_wr_start : 1; -+ unsigned int auto_wr_busy : 1; -+ unsigned int rsvd_1 : 1; -+ unsigned int byte_wdata : 8; -+ unsigned int auto_rd_enable : 1; -+ unsigned int auto_rd_start : 1; -+ unsigned int auto_rd_busy : 1; -+ unsigned int ctrl_PD : 1; -+ unsigned int rsvd_2 : 3; -+ unsigned int sim_mask_rd_dat : 1; -+ } b; -+} EFUSE_CNTL1_FIELD_T; -+ -+#define EFUSE_CNTL2 (CHIP_EFUSE_REG_BASE + 0x8) -+// Bit 31 :0 auto_rd_rdata U RO default = 'h0 -+typedef union EFUSE_CNTL2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int auto_rd_rdata : 32; -+ } b; -+} EFUSE_CNTL2_FIELD_T; -+ -+#define EFUSE_CNTL3 (CHIP_EFUSE_REG_BASE + 0xc) -+// Bit 12 :0 manual_d_addr U RW default = 'h0 -+// Bit 13 use_gen_strobe U RW default = 'h0 -+// Bit 14 gen_strobe_clk U RW default = 'h0 -+// Bit 15 gen_strobe U RO default = 'h0 -+// Bit 23 :16 manual_rdata U RO default = 'h0 -+// Bit 26 :24 man_chip_sel U RW default = 'h0 -+// Bit 27 manual_ps U RW default = 'h0 -+// Bit 28 manual_strobe U RW default = 'h0 -+// Bit 29 manual_load U RW default = 'h1 -+// Bit 30 manual_pgenb U RW default = 'h1 -+// Bit 31 manual_csb U RW default = 'h1 -+typedef union EFUSE_CNTL3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int manual_D_ADDR : 13; -+ unsigned int use_gen_STROBE : 1; -+ unsigned int gen_strobe_clk : 1; -+ unsigned int gen_STROBE : 1; -+ unsigned int manual_rdata : 8; -+ unsigned int man_chip_sel : 3; -+ unsigned int manual_PS : 1; -+ unsigned int manual_STROBE : 1; -+ unsigned int manual_LOAD : 1; -+ unsigned int manual_PGENB : 1; -+ unsigned int manual_CSB : 1; -+ } b; -+} EFUSE_CNTL3_FIELD_T; -+ -+#define EFUSE_CNTL4 (CHIP_EFUSE_REG_BASE + 0x10) -+// Bit 7 :0 encrypt_seed U RW default = 'hbe -+// Bit 8 encrypt_fixed U RW default = 'h1 -+// Bit 9 encrypt_set_seed U RW default = 'h0 -+// Bit 10 encrypt_en U RW default = 'h1 -+// Bit 23 :16 trd_clock_high U RW default = 'ha -+// Bit 31 :24 trd_clock_low U RW default = 'ha -+typedef union EFUSE_CNTL4_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int encrypt_seed : 8; -+ unsigned int encrypt_fixed : 1; -+ unsigned int encrypt_set_seed : 1; -+ unsigned int encrypt_en : 1; -+ unsigned int rsvd_0 : 5; -+ unsigned int Trd_clock_high : 8; -+ unsigned int Trd_clock_low : 8; -+ } b; -+} EFUSE_CNTL4_FIELD_T; -+ -+#define EFUSE_CNTL5 (CHIP_EFUSE_REG_BASE + 0x14) -+// Bit 2 :0 rd_strobe_time U RW default = 'h2 -+typedef union EFUSE_CNTL5_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rd_strobe_time : 3; -+ unsigned int rsvd_0 : 29; -+ } b; -+} EFUSE_CNTL5_FIELD_T; -+ -+#endif -+ ++#ifdef CHIP_EFUSE_REG ++#else ++#define CHIP_EFUSE_REG ++ ++ ++#define CHIP_EFUSE_REG_BASE (0xf04000) ++ ++#define EFUSE_CNTL0 (CHIP_EFUSE_REG_BASE + 0x0) ++// Bit 7 :0 tclock_high U RW default = 'h87 ++// Bit 15 :8 tclock_low U RW default = 'h27 ++// Bit 23 :16 tps_delay U RW default = 'ha ++// Bit 31 :24 tunit_delay U RW default = 'h2 ++typedef union EFUSE_CNTL0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int Tclock_high : 8; ++ unsigned int Tclock_low : 8; ++ unsigned int Tps_delay : 8; ++ unsigned int Tunit_delay : 8; ++ } b; ++} EFUSE_CNTL0_FIELD_T; ++ ++#define EFUSE_CNTL1 (CHIP_EFUSE_REG_BASE + 0x4) ++// Bit 9 :0 byte_addr U RW default = 'h0 ++// Bit 11 byte_addr_set U RW default = 'h0 ++// Bit 12 auto_wr_enable U RW default = 'h0 ++// Bit 13 auto_wr_start U RW default = 'h0 ++// Bit 14 auto_wr_busy U RO default = 'h0 ++// Bit 23 :16 byte_wdata U RW default = 'h0 ++// Bit 24 auto_rd_enable U RW default = 'h0 ++// Bit 25 auto_rd_start U RW default = 'h0 ++// Bit 26 auto_rd_busy U RO default = 'h0 ++// Bit 27 ctrl_pd U RW default = 'h1 ++// Bit 31 sim_mask_rd_dat U RW default = 'h0 ++typedef union EFUSE_CNTL1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int byte_addr : 10; ++ unsigned int rsvd_0 : 1; ++ unsigned int byte_addr_set : 1; ++ unsigned int auto_wr_enable : 1; ++ unsigned int auto_wr_start : 1; ++ unsigned int auto_wr_busy : 1; ++ unsigned int rsvd_1 : 1; ++ unsigned int byte_wdata : 8; ++ unsigned int auto_rd_enable : 1; ++ unsigned int auto_rd_start : 1; ++ unsigned int auto_rd_busy : 1; ++ unsigned int ctrl_PD : 1; ++ unsigned int rsvd_2 : 3; ++ unsigned int sim_mask_rd_dat : 1; ++ } b; ++} EFUSE_CNTL1_FIELD_T; ++ ++#define EFUSE_CNTL2 (CHIP_EFUSE_REG_BASE + 0x8) ++// Bit 31 :0 auto_rd_rdata U RO default = 'h0 ++typedef union EFUSE_CNTL2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int auto_rd_rdata : 32; ++ } b; ++} EFUSE_CNTL2_FIELD_T; ++ ++#define EFUSE_CNTL3 (CHIP_EFUSE_REG_BASE + 0xc) ++// Bit 12 :0 manual_d_addr U RW default = 'h0 ++// Bit 13 use_gen_strobe U RW default = 'h0 ++// Bit 14 gen_strobe_clk U RW default = 'h0 ++// Bit 15 gen_strobe U RO default = 'h0 ++// Bit 23 :16 manual_rdata U RO default = 'h0 ++// Bit 26 :24 man_chip_sel U RW default = 'h0 ++// Bit 27 manual_ps U RW default = 'h0 ++// Bit 28 manual_strobe U RW default = 'h0 ++// Bit 29 manual_load U RW default = 'h1 ++// Bit 30 manual_pgenb U RW default = 'h1 ++// Bit 31 manual_csb U RW default = 'h1 ++typedef union EFUSE_CNTL3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int manual_D_ADDR : 13; ++ unsigned int use_gen_STROBE : 1; ++ unsigned int gen_strobe_clk : 1; ++ unsigned int gen_STROBE : 1; ++ unsigned int manual_rdata : 8; ++ unsigned int man_chip_sel : 3; ++ unsigned int manual_PS : 1; ++ unsigned int manual_STROBE : 1; ++ unsigned int manual_LOAD : 1; ++ unsigned int manual_PGENB : 1; ++ unsigned int manual_CSB : 1; ++ } b; ++} EFUSE_CNTL3_FIELD_T; ++ ++#define EFUSE_CNTL4 (CHIP_EFUSE_REG_BASE + 0x10) ++// Bit 7 :0 encrypt_seed U RW default = 'hbe ++// Bit 8 encrypt_fixed U RW default = 'h1 ++// Bit 9 encrypt_set_seed U RW default = 'h0 ++// Bit 10 encrypt_en U RW default = 'h1 ++// Bit 23 :16 trd_clock_high U RW default = 'ha ++// Bit 31 :24 trd_clock_low U RW default = 'ha ++typedef union EFUSE_CNTL4_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int encrypt_seed : 8; ++ unsigned int encrypt_fixed : 1; ++ unsigned int encrypt_set_seed : 1; ++ unsigned int encrypt_en : 1; ++ unsigned int rsvd_0 : 5; ++ unsigned int Trd_clock_high : 8; ++ unsigned int Trd_clock_low : 8; ++ } b; ++} EFUSE_CNTL4_FIELD_T; ++ ++#define EFUSE_CNTL5 (CHIP_EFUSE_REG_BASE + 0x14) ++// Bit 2 :0 rd_strobe_time U RW default = 'h2 ++typedef union EFUSE_CNTL5_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rd_strobe_time : 3; ++ unsigned int rsvd_0 : 29; ++ } b; ++} EFUSE_CNTL5_FIELD_T; ++ ++#endif ++ diff --git a/drivers/net/wireless/w1/common/chip_intf_reg.h b/drivers/net/wireless/w1/common/chip_intf_reg.h new file mode 100644 -index 000000000000..56e79b748d61 +index 0000000000000000000000000000000000000000..56e79b748d61bd907508536bc49550711b7ff778 --- /dev/null +++ b/drivers/net/wireless/w1/common/chip_intf_reg.h @@ -0,0 +1,544 @@ @@ -6832,148 +6641,148 @@ index 000000000000..56e79b748d61 + diff --git a/drivers/net/wireless/w1/common/chip_pmic_i2c_reg.h b/drivers/net/wireless/w1/common/chip_pmic_i2c_reg.h new file mode 100644 -index 000000000000..3ca77327d01b +index 0000000000000000000000000000000000000000..ca06970f4e03c949c5180c6dfbcc0e971439cb2c --- /dev/null +++ b/drivers/net/wireless/w1/common/chip_pmic_i2c_reg.h @@ -0,0 +1,135 @@ -+#ifdef CHIP_PMIC_I2C_REG -+#else -+#define CHIP_PMIC_I2C_REG -+ -+ -+#define CHIP_PMIC_I2C_REG_BASE (0xf05000) -+ -+#define PMU_I2C_M_CONTROL_REG (CHIP_PMIC_I2C_REG_BASE + 0x880) -+// Bit 0 cntl_start_bit U RW default = 'h0 -+// Bit 1 cntl_ack_ignore U RW default = 'h0 -+// Bit 2 busy U RO default = 'h0 -+// Bit 3 error U RO default = 'h0 -+// Bit 7 :4 list_index U RO default = 'h0 -+// Bit 11 :8 rdata U RO default = 'h0 -+// Bit 21 :12 cntl_qtr_clk_dly U RW default = 'h14c -+// Bit 22 cntl_manual_i2c U RW default = 'h0 -+// Bit 23 cntl_scl_level_o U RW default = 'h1 -+// Bit 24 cntl_sda_level_o U RW default = 'h1 -+// Bit 25 scl_i U RO default = 'h0 -+// Bit 26 sda_i U RO default = 'h0 -+// Bit 29 :28 cnt1_qtr_clk_dly U RW default = 'h0 -+// Bit 31 cnt1_jic U RW default = 'h0 -+typedef union PMU_I2C_M_CONTROL_REG_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int cntl_start_bit : 1; -+ unsigned int cntl_ack_ignore : 1; -+ unsigned int busy : 1; -+ unsigned int error : 1; -+ unsigned int list_index : 4; -+ unsigned int rdata : 4; -+ unsigned int cntl_qtr_clk_dly : 10; -+ unsigned int cntl_manual_i2c : 1; -+ unsigned int cntl_scl_level_o : 1; -+ unsigned int cntl_sda_level_o : 1; -+ unsigned int scl_i : 1; -+ unsigned int sda_i : 1; -+ unsigned int rsvd_0 : 1; -+ unsigned int cnt1_qtr_clk_dly : 2; -+ unsigned int rsvd_1 : 1; -+ unsigned int cnt1_jic : 1; -+ } b; -+} PMU_I2C_M_CONTROL_REG_FIELD_T; -+ -+#define PMU_I2C_M_SLAVE_ADDR (CHIP_PMIC_I2C_REG_BASE + 0x884) -+// Bit 7 :0 slave_addr U RW default = 'h0 -+// Bit 10 :8 sda_filter_sel U RW default = 'h2 -+// Bit 13 :11 scl_filter_sel U RW default = 'h2 -+// Bit 27 :16 cntl_scl_low U RW default = 'h14c -+// Bit 28 use_cntl_scl_low U RW default = 'h0 -+typedef union PMU_I2C_M_SLAVE_ADDR_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int slave_addr : 8; -+ unsigned int sda_filter_sel : 3; -+ unsigned int scl_filter_sel : 3; -+ unsigned int rsvd_0 : 2; -+ unsigned int cntl_scl_low : 12; -+ unsigned int use_cntl_scl_low : 1; -+ unsigned int rsvd_1 : 3; -+ } b; -+} PMU_I2C_M_SLAVE_ADDR_FIELD_T; -+ -+#define PMU_I2C_M_TOKEN_LIST0 (CHIP_PMIC_I2C_REG_BASE + 0x888) -+// Bit 31 :0 i2c_m_token_list0 U RW default = 'h0 -+typedef union PMU_I2C_M_TOKEN_LIST0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int i2c_m_token_list0 : 32; -+ } b; -+} PMU_I2C_M_TOKEN_LIST0_FIELD_T; -+ -+#define PMU_I2C_M_TOKEN_LIST1 (CHIP_PMIC_I2C_REG_BASE + 0x88c) -+// Bit 31 :0 i2c_m_token_list1 U RW default = 'h0 -+typedef union PMU_I2C_M_TOKEN_LIST1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int i2c_m_token_list1 : 32; -+ } b; -+} PMU_I2C_M_TOKEN_LIST1_FIELD_T; -+ -+#define PMU_I2C_M_WDATA_REG0 (CHIP_PMIC_I2C_REG_BASE + 0x890) -+// Bit 31 :0 i2c_m_wdata_reg0 U RW default = 'h0 -+typedef union PMU_I2C_M_WDATA_REG0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int i2c_m_wdata_reg0 : 32; -+ } b; -+} PMU_I2C_M_WDATA_REG0_FIELD_T; -+ -+#define PMU_I2C_M_WDATA_REG1 (CHIP_PMIC_I2C_REG_BASE + 0x894) -+// Bit 31 :0 i2c_m_wdata_reg1 U RW default = 'h0 -+typedef union PMU_I2C_M_WDATA_REG1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int i2c_m_wdata_reg1 : 32; -+ } b; -+} PMU_I2C_M_WDATA_REG1_FIELD_T; -+ -+#define PMU_I2C_M_RDATA_REG0 (CHIP_PMIC_I2C_REG_BASE + 0x898) -+// Bit 31 :0 i2c_m_rdata_reg0 U RO default = 'h0 -+typedef union PMU_I2C_M_RDATA_REG0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int i2c_m_rdata_reg0 : 32; -+ } b; -+} PMU_I2C_M_RDATA_REG0_FIELD_T; -+ -+#define PMU_I2C_M_RDATA_REG1 (CHIP_PMIC_I2C_REG_BASE + 0x89c) -+// Bit 31 :0 i2c_m_rdata_reg1 U RO default = 'h0 -+typedef union PMU_I2C_M_RDATA_REG1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int i2c_m_rdata_reg1 : 32; -+ } b; -+} PMU_I2C_M_RDATA_REG1_FIELD_T; -+ -+#endif -+ ++#ifdef CHIP_PMIC_I2C_REG ++#else ++#define CHIP_PMIC_I2C_REG ++ ++ ++#define CHIP_PMIC_I2C_REG_BASE (0xf05000) ++ ++#define PMU_I2C_M_CONTROL_REG (CHIP_PMIC_I2C_REG_BASE + 0x880) ++// Bit 0 cntl_start_bit U RW default = 'h0 ++// Bit 1 cntl_ack_ignore U RW default = 'h0 ++// Bit 2 busy U RO default = 'h0 ++// Bit 3 error U RO default = 'h0 ++// Bit 7 :4 list_index U RO default = 'h0 ++// Bit 11 :8 rdata U RO default = 'h0 ++// Bit 21 :12 cntl_qtr_clk_dly U RW default = 'h14c ++// Bit 22 cntl_manual_i2c U RW default = 'h0 ++// Bit 23 cntl_scl_level_o U RW default = 'h1 ++// Bit 24 cntl_sda_level_o U RW default = 'h1 ++// Bit 25 scl_i U RO default = 'h0 ++// Bit 26 sda_i U RO default = 'h0 ++// Bit 29 :28 cnt1_qtr_clk_dly U RW default = 'h0 ++// Bit 31 cnt1_jic U RW default = 'h0 ++typedef union PMU_I2C_M_CONTROL_REG_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int cntl_start_bit : 1; ++ unsigned int cntl_ack_ignore : 1; ++ unsigned int busy : 1; ++ unsigned int error : 1; ++ unsigned int list_index : 4; ++ unsigned int rdata : 4; ++ unsigned int cntl_qtr_clk_dly : 10; ++ unsigned int cntl_manual_i2c : 1; ++ unsigned int cntl_scl_level_o : 1; ++ unsigned int cntl_sda_level_o : 1; ++ unsigned int scl_i : 1; ++ unsigned int sda_i : 1; ++ unsigned int rsvd_0 : 1; ++ unsigned int cnt1_qtr_clk_dly : 2; ++ unsigned int rsvd_1 : 1; ++ unsigned int cnt1_jic : 1; ++ } b; ++} PMU_I2C_M_CONTROL_REG_FIELD_T; ++ ++#define PMU_I2C_M_SLAVE_ADDR (CHIP_PMIC_I2C_REG_BASE + 0x884) ++// Bit 7 :0 slave_addr U RW default = 'h0 ++// Bit 10 :8 sda_filter_sel U RW default = 'h2 ++// Bit 13 :11 scl_filter_sel U RW default = 'h2 ++// Bit 27 :16 cntl_scl_low U RW default = 'h14c ++// Bit 28 use_cntl_scl_low U RW default = 'h0 ++typedef union PMU_I2C_M_SLAVE_ADDR_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int slave_addr : 8; ++ unsigned int sda_filter_sel : 3; ++ unsigned int scl_filter_sel : 3; ++ unsigned int rsvd_0 : 2; ++ unsigned int cntl_scl_low : 12; ++ unsigned int use_cntl_scl_low : 1; ++ unsigned int rsvd_1 : 3; ++ } b; ++} PMU_I2C_M_SLAVE_ADDR_FIELD_T; ++ ++#define PMU_I2C_M_TOKEN_LIST0 (CHIP_PMIC_I2C_REG_BASE + 0x888) ++// Bit 31 :0 i2c_m_token_list0 U RW default = 'h0 ++typedef union PMU_I2C_M_TOKEN_LIST0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int i2c_m_token_list0 : 32; ++ } b; ++} PMU_I2C_M_TOKEN_LIST0_FIELD_T; ++ ++#define PMU_I2C_M_TOKEN_LIST1 (CHIP_PMIC_I2C_REG_BASE + 0x88c) ++// Bit 31 :0 i2c_m_token_list1 U RW default = 'h0 ++typedef union PMU_I2C_M_TOKEN_LIST1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int i2c_m_token_list1 : 32; ++ } b; ++} PMU_I2C_M_TOKEN_LIST1_FIELD_T; ++ ++#define PMU_I2C_M_WDATA_REG0 (CHIP_PMIC_I2C_REG_BASE + 0x890) ++// Bit 31 :0 i2c_m_wdata_reg0 U RW default = 'h0 ++typedef union PMU_I2C_M_WDATA_REG0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int i2c_m_wdata_reg0 : 32; ++ } b; ++} PMU_I2C_M_WDATA_REG0_FIELD_T; ++ ++#define PMU_I2C_M_WDATA_REG1 (CHIP_PMIC_I2C_REG_BASE + 0x894) ++// Bit 31 :0 i2c_m_wdata_reg1 U RW default = 'h0 ++typedef union PMU_I2C_M_WDATA_REG1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int i2c_m_wdata_reg1 : 32; ++ } b; ++} PMU_I2C_M_WDATA_REG1_FIELD_T; ++ ++#define PMU_I2C_M_RDATA_REG0 (CHIP_PMIC_I2C_REG_BASE + 0x898) ++// Bit 31 :0 i2c_m_rdata_reg0 U RO default = 'h0 ++typedef union PMU_I2C_M_RDATA_REG0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int i2c_m_rdata_reg0 : 32; ++ } b; ++} PMU_I2C_M_RDATA_REG0_FIELD_T; ++ ++#define PMU_I2C_M_RDATA_REG1 (CHIP_PMIC_I2C_REG_BASE + 0x89c) ++// Bit 31 :0 i2c_m_rdata_reg1 U RO default = 'h0 ++typedef union PMU_I2C_M_RDATA_REG1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int i2c_m_rdata_reg1 : 32; ++ } b; ++} PMU_I2C_M_RDATA_REG1_FIELD_T; ++ ++#endif ++ diff --git a/drivers/net/wireless/w1/common/chip_pmu_reg.h b/drivers/net/wireless/w1/common/chip_pmu_reg.h new file mode 100644 -index 000000000000..2088eb55476d +index 0000000000000000000000000000000000000000..2088eb55476d4afe2c26ca6d82ecf89892129dac --- /dev/null +++ b/drivers/net/wireless/w1/common/chip_pmu_reg.h @@ -0,0 +1,406 @@ @@ -7385,7 +7194,7 @@ index 000000000000..2088eb55476d + diff --git a/drivers/net/wireless/w1/common/fi_cmd.h b/drivers/net/wireless/w1/common/fi_cmd.h new file mode 100644 -index 000000000000..09022081a888 +index 0000000000000000000000000000000000000000..09022081a8882e22a739b8a8c2d9a5c3715a8602 --- /dev/null +++ b/drivers/net/wireless/w1/common/fi_cmd.h @@ -0,0 +1,491 @@ @@ -7882,7 +7691,7 @@ index 000000000000..09022081a888 +#endif diff --git a/drivers/net/wireless/w1/common/fi_sdio.h b/drivers/net/wireless/w1/common/fi_sdio.h new file mode 100644 -index 000000000000..e3e38d249861 +index 0000000000000000000000000000000000000000..e3e38d2498610d0c62146b1867e0ce4d4399bc30 --- /dev/null +++ b/drivers/net/wireless/w1/common/fi_sdio.h @@ -0,0 +1,1069 @@ @@ -8957,7 +8766,7 @@ index 000000000000..e3e38d249861 + diff --git a/drivers/net/wireless/w1/common/fucode_em4.h b/drivers/net/wireless/w1/common/fucode_em4.h new file mode 100644 -index 000000000000..b9661763dbcc +index 0000000000000000000000000000000000000000..142d8ba45d1bf1036a65575867c25e1d50ef4776 --- /dev/null +++ b/drivers/net/wireless/w1/common/fucode_em4.h @@ -0,0 +1,6665 @@ @@ -12037,56 +11846,56 @@ index 000000000000..b9661763dbcc +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 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++0x49,0xC4,0x63,0x06,0xDB,0x26,0xC1,0x83,0x7D,0x17,0x85,0x8B,0x65,0xFB,0x89,0x65,0x93,0x85,0x05,0x71,0x17,0xE5,0x6E,0x00,0x13,0x05,0x45,0x7A,0xEF,0xC0,0x00,0x7E, +0x83,0xA7,0x4D,0x42,0x15,0x45,0x82,0x97,0x83,0x27,0x49,0xC4,0x03,0x27,0x49,0xD6,0x03,0x26,0x89,0xD6,0x93,0x15,0x27,0x00,0xB2,0x86,0x63,0xD5,0x05,0x00,0xB7,0x05, +0x00,0xC0,0x2E,0x97,0x93,0x15,0x26,0x00,0x63,0xD5,0x05,0x00,0xB7,0x06,0x00,0xC0,0xB2,0x96,0x93,0xD9,0x87,0x00,0x13,0xF4,0xF7,0x07,0x83,0x27,0x49,0xC4,0x7D,0x1B, +0x93,0xF9,0xF9,0x07,0x86,0x07,0x85,0x83,0x23,0x22,0xF9,0xC4,0xF9,0x57,0x63,0x1A,0xFB,0x14,0x93,0x55,0x37,0x41,0x7D,0x87,0x33,0x4A,0xB7,0x00,0x13,0xD9,0x36,0x41, +0x33,0x0A,0xEA,0x40,0x23,0x20,0xBD,0x00,0x23,0x22,0x2D,0x01,0x23,0x24,0x8D,0x00,0x23,0x26,0x3D,0x01,0x39,0x47,0x63,0x49,0x47,0x01,0xFD,0x86,0xB3,0xC7,0x26,0x01, -+0xB3,0x86,0xD7,0x40,0x63,0x55,0xD7,0x02,0xC2,0x05,0xB3,0xE5,0x25,0x01,0x17,0xE5,0x6E,0x00,0x13,0x05,0xA5,0x6C,0xEF,0xC0,0x80,0x70,0x93,0x15,0x04,0x01,0xB3,0xE5, -+0x35,0x01,0x17,0xE5,0x6E,0x00,0x13,0x05,0x65,0x6B,0xEF,0xC0,0x40,0x6F,0x83,0xA7,0x8D,0x7B,0x82,0x97,0xB9,0x47,0x63,0xCE,0x47,0x19,0x13,0x57,0xF9,0x41,0x33,0x49, ++0xB3,0x86,0xD7,0x40,0x63,0x55,0xD7,0x02,0xC2,0x05,0xB3,0xE5,0x25,0x01,0x17,0xE5,0x6E,0x00,0x13,0x05,0x65,0x6F,0xEF,0xC0,0x60,0x74,0x93,0x15,0x04,0x01,0xB3,0xE5, ++0x35,0x01,0x17,0xE5,0x6E,0x00,0x13,0x05,0x25,0x6E,0xEF,0xC0,0x20,0x73,0x83,0xA7,0x8D,0x7B,0x82,0x97,0xB9,0x47,0x63,0xCE,0x47,0x19,0x13,0x57,0xF9,0x41,0x33,0x49, +0x27,0x01,0x33,0x09,0xE9,0x40,0x63,0xC6,0x27,0x19,0x17,0xB4,0x6E,0x00,0x13,0x04,0xA4,0x0F,0x63,0x82,0x0B,0x1A,0x9C,0x40,0x05,0x69,0x13,0x05,0x89,0xC0,0x82,0x97, +0x96,0x47,0x93,0x95,0x87,0x00,0xC1,0x77,0x13,0x87,0xF7,0x0F,0x79,0x8D,0x62,0x57,0x4D,0x8D,0x93,0x84,0xF7,0xFF,0x1C,0x40,0x93,0x15,0x07,0x01,0x65,0x8D,0xC9,0x8D, +0x13,0x05,0x89,0xC0,0x82,0x97,0x82,0x57,0xB7,0xF6,0xA0,0x00,0x03,0xA7,0x46,0xC4,0x93,0x95,0xF7,0x01,0xB7,0x07,0x00,0x80,0x13,0xC6,0xF7,0xFF,0x71,0x8F,0x4D,0x8F, @@ -12234,7 +12043,7 @@ index 000000000000..b9661763dbcc +0xF4,0x00,0xB3,0x99,0xF9,0x00,0xC2,0x57,0x93,0xCA,0xFA,0xFF,0x95,0xEF,0x93,0x87,0x0C,0xCB,0xE2,0x97,0x3E,0x85,0xBE,0xC6,0x02,0x97,0xB6,0x47,0x03,0x27,0x0A,0x00, +0xB3,0x75,0x55,0x01,0xC1,0x8D,0x3E,0x85,0x02,0x97,0x93,0x8C,0x8C,0xCC,0x9C,0x40,0x66,0x9C,0x62,0x85,0x82,0x97,0x83,0x27,0x0A,0x00,0xB3,0x75,0x55,0x01,0xB3,0xE5, +0x35,0x01,0x62,0x85,0x82,0x97,0xBD,0xBB,0x93,0x87,0xCC,0xCB,0xE2,0x97,0x3E,0x85,0xBE,0xC6,0x02,0x97,0xB6,0x47,0x03,0x27,0x0A,0x00,0xB3,0x75,0x55,0x01,0xC1,0x8D, -+0x3E,0x85,0x02,0x97,0x93,0x8C,0x4C,0xCD,0xD9,0xB7,0xE1,0x83,0x59,0xB3,0xE1,0x83,0x61,0xBB,0xF2,0x55,0x17,0xE5,0x6E,0x00,0x13,0x05,0x45,0x50,0xEF,0xC0,0x20,0x54, ++0x3E,0x85,0x02,0x97,0x93,0x8C,0x4C,0xCD,0xD9,0xB7,0xE1,0x83,0x59,0xB3,0xE1,0x83,0x61,0xBB,0xF2,0x55,0x17,0xE5,0x6E,0x00,0x13,0x05,0x05,0x53,0xEF,0xC0,0x00,0x58, +0xB2,0x47,0xFD,0x17,0x93,0xF7,0xF7,0x0F,0x3E,0xC6,0x85,0x47,0x3E,0xC8,0xB2,0x47,0xE3,0x8D,0x07,0xE4,0x49,0xB9,0x9C,0x40,0x05,0x69,0x13,0x05,0xC9,0xD6,0x82,0x97, +0x92,0x57,0x93,0x95,0xB7,0x00,0xFD,0x77,0x93,0x87,0xF7,0x7F,0x7D,0x8D,0x1C,0x40,0xC9,0x8D,0x13,0x05,0xC9,0xD6,0x82,0x97,0x3D,0xBD,0x51,0x71,0xA2,0xD5,0xCE,0xCF, +0xD2,0xCD,0xDA,0xC9,0xDE,0xC7,0x86,0xD7,0xA6,0xD3,0xCA,0xD1,0xD6,0xCB,0xE2,0xC5,0xE6,0xC3,0xEA,0xC1,0x6E,0xDF,0x02,0xC2,0x02,0xC4,0x02,0xC6,0x02,0xC8,0x02,0xCA, @@ -12308,7 +12117,7 @@ index 000000000000..b9661763dbcc +0xB3,0xF4,0x94,0x01,0xDD,0x8C,0x81,0x77,0x93,0x87,0x27,0x0E,0x33,0x7D,0xF5,0x00,0xC9,0x67,0x93,0x87,0x57,0x40,0x33,0x6D,0xFD,0x00,0x83,0x27,0x0C,0x00,0xEA,0x85, +0x13,0x85,0x8A,0xC0,0x82,0x97,0x83,0xA7,0x0D,0x00,0x13,0x85,0x8A,0xCE,0xB7,0x0C,0x00,0x80,0x82,0x97,0x83,0x27,0x0C,0x00,0x93,0xCC,0xFC,0xFF,0xB3,0x75,0x95,0x01, +0x13,0x5A,0xF5,0x01,0x13,0x85,0x8A,0xCE,0x82,0x97,0x83,0xA7,0x0D,0x00,0x13,0x85,0xCA,0xCE,0x7E,0x0A,0x82,0x97,0x13,0x59,0xF5,0x01,0x7E,0x09,0x83,0x27,0x0C,0x00, -+0xB3,0x75,0x95,0x01,0x01,0xBC,0x13,0x85,0x01,0x7C,0xEF,0xB0,0x50,0x41,0x35,0xBE,0x31,0x71,0x26,0xDB,0x97,0xA4,0x6E,0x00,0x93,0x84,0x44,0x63,0x9C,0x40,0x06,0xDF, ++0xB3,0x75,0x95,0x01,0x01,0xBC,0x13,0x85,0x01,0x7C,0xEF,0xB0,0x30,0x45,0x35,0xBE,0x31,0x71,0x26,0xDB,0x97,0xA4,0x6E,0x00,0x93,0x84,0x44,0x63,0x9C,0x40,0x06,0xDF, +0x22,0xDD,0x4A,0xD9,0x4E,0xD7,0x52,0xD5,0x56,0xD3,0x5A,0xD1,0x5E,0xCF,0x62,0xCD,0x66,0xCB,0x6A,0xC9,0x6E,0xC7,0xAA,0xC2,0x13,0x05,0x80,0x05,0xAE,0x8B,0x82,0x97, +0x17,0xA4,0x6E,0x00,0x13,0x04,0x44,0x60,0x93,0x77,0x15,0x00,0x3E,0xC6,0x1C,0x40,0x93,0x65,0x15,0x00,0x13,0x05,0x80,0x05,0x82,0x97,0x9C,0x40,0x13,0x05,0x00,0x09, +0x05,0x69,0x82,0x97,0x93,0x17,0x05,0x01,0xC1,0x83,0x3E,0xDE,0x93,0x65,0x85,0x23,0xC1,0x77,0x7D,0x8D,0xC2,0x05,0x1C,0x40,0xC1,0x81,0xC9,0x8D,0x13,0x05,0x00,0x09, @@ -12399,7 +12208,7 @@ index 000000000000..b9661763dbcc +0xC7,0x42,0x13,0x18,0x85,0x00,0xB3,0x76,0xF5,0x00,0xB3,0xE6,0x06,0x01,0xED,0x8E,0x13,0x18,0x05,0x01,0xB3,0xE6,0x06,0x01,0x62,0x05,0xF1,0x8E,0xC9,0x8E,0x23,0x26, +0xD7,0x42,0x03,0x45,0x04,0x1A,0x83,0x26,0x07,0x43,0x13,0x18,0x85,0x00,0xB3,0x76,0xF5,0x00,0xB3,0xE6,0x06,0x01,0xED,0x8E,0x13,0x18,0x05,0x01,0xB3,0xE6,0x06,0x01, +0x62,0x05,0xF1,0x8E,0xC9,0x8E,0x23,0x28,0xD7,0x42,0x83,0x26,0x47,0x43,0x83,0x46,0x04,0x1A,0x13,0x95,0x86,0x00,0xF5,0x8F,0xC9,0x8F,0xED,0x8F,0x13,0x95,0x06,0x01, -+0xC9,0x8F,0xE2,0x06,0xF1,0x8F,0xD5,0x8F,0x23,0x2A,0xF7,0x42,0x97,0xC6,0x6E,0x00,0x83,0xC6,0x76,0xA8,0x93,0x07,0xB0,0x02,0x17,0xC6,0x6E,0x00,0x13,0x06,0x06,0xA9, ++0xC9,0x8F,0xE2,0x06,0xF1,0x8F,0xD5,0x8F,0x23,0x2A,0xF7,0x42,0x97,0xC6,0x6E,0x00,0x83,0xC6,0x76,0xA8,0x93,0x07,0xB0,0x02,0x17,0xC6,0x6E,0x00,0x13,0x06,0x86,0xAA, +0x13,0x07,0x90,0x03,0xB3,0x85,0xC7,0x00,0x83,0xC5,0x05,0x00,0x63,0x9F,0xD5,0x2A,0xD6,0x97,0x83,0xC6,0xA7,0x0C,0x12,0x0A,0x56,0x9A,0x03,0x47,0x6A,0x00,0x93,0x07, +0x40,0x06,0x97,0xC8,0x6E,0x00,0x83,0xC8,0x88,0xA5,0x33,0x07,0xD7,0x02,0x17,0xC8,0x6E,0x00,0x03,0x48,0xD8,0xA4,0x13,0x96,0x08,0x01,0x93,0x15,0x08,0x01,0x17,0xC5, +0x6E,0x00,0x03,0x45,0xB5,0xA3,0x41,0x82,0xC1,0x81,0x33,0x47,0xF7,0x02,0x33,0x07,0x27,0x03,0x33,0x47,0xF7,0x02,0x85,0x47,0x42,0x07,0x41,0x83,0x63,0x1F,0xF5,0x00, @@ -12464,8 +12273,8 @@ index 000000000000..b9661763dbcc +0xD7,0x01,0x55,0x8F,0xB7,0x06,0x00,0x80,0x55,0x8F,0x23,0xAA,0xE7,0x4A,0x83,0xA6,0x87,0x4B,0x13,0xD3,0xC8,0x00,0x93,0x7D,0xF3,0x0F,0xC1,0x74,0x93,0xF6,0x06,0xF0, +0x93,0x8E,0xF4,0x0F,0x13,0xFE,0xF8,0x0F,0xB3,0xE6,0xB6,0x01,0x93,0xF8,0xF8,0x0F,0xA2,0x08,0xB3,0xF6,0xD6,0x01,0xB3,0xE6,0x16,0x01,0x23,0xAC,0xD7,0x4A,0x83,0x26, +0x86,0x7B,0x23,0x24,0xCB,0x01,0x23,0x20,0xBB,0x00,0x23,0x22,0xAB,0x00,0x23,0x26,0xBB,0x01,0x72,0xD2,0x2E,0xD6,0x2A,0xD4,0x82,0x96,0xB2,0x55,0x22,0x55,0x93,0xFC, -+0x8C,0x23,0xC2,0x05,0xC9,0x8D,0x13,0x85,0x81,0x7E,0xEF,0xA0,0x50,0x09,0x12,0x5E,0x17,0xB5,0x6E,0x00,0x13,0x05,0xC5,0xAA,0x05,0x6B,0x93,0x15,0x0E,0x01,0xB3,0xE5, -+0xB5,0x01,0xEF,0xA0,0xD0,0x07,0x14,0x40,0x13,0x05,0x80,0x05,0x97,0x9D,0x6E,0x00,0x93,0x8D,0x8D,0x29,0x82,0x96,0x92,0x47,0x03,0xA6,0x0D,0x00,0x93,0x75,0xE5,0xFF, ++0x8C,0x23,0xC2,0x05,0xC9,0x8D,0x13,0x85,0x81,0x7E,0xEF,0xA0,0x30,0x0D,0x12,0x5E,0x17,0xB5,0x6E,0x00,0x13,0x05,0xC5,0xAA,0x05,0x6B,0x93,0x15,0x0E,0x01,0xB3,0xE5, ++0xB5,0x01,0xEF,0xA0,0xB0,0x0B,0x14,0x40,0x13,0x05,0x80,0x05,0x97,0x9D,0x6E,0x00,0x93,0x8D,0x8D,0x29,0x82,0x96,0x92,0x47,0x03,0xA6,0x0D,0x00,0x93,0x75,0xE5,0xFF, +0xDD,0x8D,0x13,0x05,0x80,0x05,0x02,0x96,0x10,0x40,0x13,0x05,0x00,0x09,0xA2,0x09,0x02,0x96,0x93,0x75,0x75,0xDC,0xB3,0xEC,0x95,0x01,0x03,0xA6,0x0D,0x00,0xC2,0x0C, +0xB3,0x75,0x95,0x00,0x93,0xDC,0x0C,0x01,0xB3,0xE5,0x95,0x01,0x13,0x05,0x00,0x09,0x02,0x96,0x10,0x40,0x13,0x05,0x8B,0x81,0x93,0xFB,0xCB,0x01,0x02,0x96,0xB7,0x45, +0xE0,0xFF,0xDD,0x15,0x6D,0x8D,0xB7,0xC5,0x1F,0x00,0x03,0xA6,0x0D,0x00,0xA1,0x05,0xB3,0xF5,0xBA,0x00,0xC9,0x8D,0x13,0x05,0x8B,0x81,0x02,0x96,0x10,0x40,0x13,0x05, @@ -12480,7 +12289,7 @@ index 000000000000..b9661763dbcc +0xE2,0x46,0xDA,0x44,0x33,0x77,0x37,0x01,0xC2,0x06,0x55,0x8F,0x82,0x56,0x22,0x07,0x21,0x83,0xE2,0x06,0x55,0x8F,0x23,0xAC,0xE7,0x4A,0x03,0xA7,0x87,0x5B,0xF2,0x46, +0xBA,0x49,0x13,0x77,0x07,0xF0,0x55,0x8F,0x23,0xAC,0xE7,0x5A,0x83,0x27,0x88,0xC3,0x2A,0x4A,0x9A,0x4A,0xC1,0x9B,0xB3,0xE7,0x27,0x01,0x23,0x2C,0xF8,0xC2,0x4A,0x49, +0x0A,0x4B,0xF6,0x5B,0x66,0x5C,0xD6,0x5C,0x46,0x5D,0xB6,0x5D,0x0D,0x61,0x82,0x80,0x81,0x77,0x93,0x87,0xF7,0x0F,0x33,0x7A,0xF5,0x00,0xE5,0x67,0x93,0x87,0x07,0x90, -+0x03,0x27,0x0D,0x00,0x33,0x6A,0xFA,0x00,0xD2,0x85,0x13,0x85,0x84,0xC0,0x02,0x97,0x05,0xB6,0x13,0x85,0x41,0x7D,0xEF,0xA0,0x80,0x68,0x17,0xD6,0xFF,0xFF,0x13,0x06, ++0x03,0x27,0x0D,0x00,0x33,0x6A,0xFA,0x00,0xD2,0x85,0x13,0x85,0x84,0xC0,0x02,0x97,0x05,0xB6,0x13,0x85,0x41,0x7D,0xEF,0xA0,0x60,0x6C,0x17,0xD6,0xFF,0xFF,0x13,0x06, +0x66,0x88,0xB1,0xB3,0x6F,0x30,0x80,0x20,0x5D,0x71,0xA6,0xC2,0x97,0x94,0x6E,0x00,0x93,0x84,0xC4,0x09,0x9C,0x40,0x86,0xC6,0xA2,0xC4,0xCA,0xC0,0x4E,0xDE,0x52,0xDC, +0x2A,0x8A,0x13,0x05,0x80,0x05,0x17,0x94,0x6E,0x00,0x13,0x04,0xE4,0x07,0xAE,0x89,0x82,0x97,0x1C,0x40,0x93,0x75,0xE5,0xF8,0x93,0xE5,0x15,0x02,0x13,0x05,0x80,0x05, +0x82,0x97,0x9C,0x40,0x13,0x05,0x00,0x09,0x05,0x69,0x82,0x97,0x93,0x65,0x05,0x22,0xC1,0x77,0x7D,0x8D,0xC2,0x05,0x1C,0x40,0xC1,0x81,0xC9,0x8D,0x13,0x05,0x00,0x09, @@ -12514,23 +12323,23 @@ index 000000000000..b9661763dbcc +0x93,0x77,0xF5,0x0F,0x3E,0xD4,0x93,0x65,0xC5,0x01,0x1C,0x40,0x13,0x75,0x05,0xF0,0x93,0xF5,0xF5,0x0F,0xC9,0x8D,0x13,0x05,0x80,0x07,0x82,0x97,0x83,0xA7,0x0C,0x4F, +0x37,0xF9,0xA0,0x00,0x93,0xD9,0x89,0x00,0x13,0xD7,0x87,0x01,0x13,0x67,0x57,0x09,0x62,0x07,0xB3,0xF7,0xA7,0x01,0xD9,0x8F,0x23,0xA8,0xFC,0x4E,0x83,0x27,0xC9,0x82, +0x93,0xF9,0xF9,0x0F,0xEC,0x00,0xB9,0x9B,0x93,0xE7,0x07,0x01,0x23,0x26,0xF9,0x82,0x85,0x47,0xBE,0xD2,0x23,0x06,0xF1,0x06,0x97,0xC7,0xFF,0xFF,0x93,0x87,0x87,0x46, -+0x83,0xA7,0x47,0x7C,0xCE,0xD4,0xE8,0x08,0x82,0xCE,0x82,0xD0,0x82,0x97,0xB6,0x4B,0x46,0x4C,0x17,0xC5,0x6E,0x00,0x13,0x05,0xA5,0x24,0x93,0x95,0x0B,0x01,0xB3,0xE5, -+0x85,0x01,0xEF,0xA0,0xC0,0x23,0x83,0xAD,0xCC,0x40,0xB7,0x07,0x00,0x5E,0x37,0x07,0x20,0xA0,0xB3,0xF7,0xFD,0x00,0xD9,0x8F,0x23,0xA6,0xFC,0x40,0x83,0xA7,0x0C,0x41, ++0x83,0xA7,0x47,0x7C,0xCE,0xD4,0xE8,0x08,0x82,0xCE,0x82,0xD0,0x82,0x97,0xB6,0x4B,0x46,0x4C,0x17,0xC5,0x6E,0x00,0x13,0x05,0x65,0x27,0x93,0x95,0x0B,0x01,0xB3,0xE5, ++0x85,0x01,0xEF,0xA0,0xA0,0x27,0x83,0xAD,0xCC,0x40,0xB7,0x07,0x00,0x5E,0x37,0x07,0x20,0xA0,0xB3,0xF7,0xFD,0x00,0xD9,0x8F,0x23,0xA6,0xFC,0x40,0x83,0xA7,0x0C,0x41, +0xB7,0xF9,0xA0,0x00,0x13,0xF7,0x37,0x00,0xF1,0x9B,0x3A,0xC8,0x93,0xE7,0x17,0x00,0x23,0xA8,0xFC,0x40,0x83,0x27,0x09,0xD0,0x37,0x07,0x00,0xFF,0xF9,0x8F,0x93,0xE7, +0x07,0x01,0x23,0x20,0xF9,0xD0,0x83,0x27,0x49,0xD0,0x61,0x77,0xF9,0x8F,0x33,0xEB,0x67,0x01,0xB7,0x47,0x0F,0x00,0x23,0x22,0x69,0xD1,0x93,0x87,0x07,0x24,0x6A,0xD8, +0x0D,0x4B,0x01,0x47,0x13,0x09,0x40,0x03,0x37,0x0D,0x00,0x80,0x3E,0xDA,0x83,0xA7,0x8C,0x4B,0x09,0xE7,0x13,0xDA,0x07,0x01,0x13,0x7A,0x1A,0x00,0x41,0x67,0xD9,0x8F, +0x42,0x57,0x93,0x16,0x89,0x01,0x01,0x45,0x7D,0x8F,0xB3,0x67,0xD7,0x00,0x23,0xAC,0xFC,0x4A,0xEF,0xC0,0xDF,0xF8,0x83,0xA7,0x49,0xC4,0x81,0x45,0xB3,0xE7,0xA7,0x01, +0x23,0xA2,0xF9,0xC4,0x83,0xA7,0x49,0xC4,0xC1,0x83,0x85,0x8B,0x63,0x94,0x07,0x2C,0x83,0xA7,0x49,0xC4,0x52,0x57,0x85,0x05,0xC1,0x83,0x85,0x8B,0xE3,0x98,0xE5,0xFE, +0x03,0xA5,0x49,0xD6,0x83,0xA6,0x89,0xD6,0x93,0x17,0x25,0x00,0x36,0x87,0x63,0xD5,0x07,0x00,0xB7,0x07,0x00,0xC0,0x3E,0x95,0x13,0x96,0x26,0x00,0x93,0x57,0x35,0x41, -+0x63,0x55,0x06,0x00,0x37,0x07,0x00,0xC0,0x36,0x97,0x4D,0x87,0x93,0x95,0x07,0x01,0xD9,0x8D,0x17,0xC5,0x6E,0x00,0x13,0x05,0xA5,0x14,0x3E,0xDE,0x3A,0xDC,0xEF,0xA0, -+0x00,0x14,0xF2,0x57,0x62,0x57,0x33,0x85,0x77,0x41,0x33,0x07,0x87,0x41,0x33,0x07,0xE7,0x02,0x33,0x05,0xA5,0x02,0x3A,0x95,0xEF,0x30,0xC0,0x50,0x83,0xA7,0x49,0xC4, ++0x63,0x55,0x06,0x00,0x37,0x07,0x00,0xC0,0x36,0x97,0x4D,0x87,0x93,0x95,0x07,0x01,0xD9,0x8D,0x17,0xC5,0x6E,0x00,0x13,0x05,0x65,0x17,0x3E,0xDE,0x3A,0xDC,0xEF,0xA0, ++0xE0,0x17,0xF2,0x57,0x62,0x57,0x33,0x85,0x77,0x41,0x33,0x07,0x87,0x41,0x33,0x07,0xE7,0x02,0x33,0x05,0xA5,0x02,0x3A,0x95,0xEF,0x30,0xC0,0x50,0x83,0xA7,0x49,0xC4, +0x37,0x07,0x00,0x80,0x13,0x47,0xF7,0xFF,0xF9,0x8F,0x2A,0xDC,0x23,0xA2,0xF9,0xC4,0xEF,0xC0,0x3F,0xF2,0x62,0x55,0x52,0x47,0x93,0x07,0x75,0xF2,0x92,0x07,0x13,0x05, -+0x40,0x06,0xB3,0x87,0x57,0x41,0xB3,0x87,0xA7,0x02,0x17,0xA5,0x6E,0x00,0x13,0x05,0x65,0x33,0xB3,0xC7,0xE7,0x02,0xBE,0x85,0x3E,0xDC,0xEF,0xA0,0x40,0x0E,0xE2,0x57, ++0x40,0x06,0xB3,0x87,0x57,0x41,0xB3,0x87,0xA7,0x02,0x17,0xA5,0x6E,0x00,0x13,0x05,0x65,0x33,0xB3,0xC7,0xE7,0x02,0xBE,0x85,0x3E,0xDC,0xEF,0xA0,0x20,0x12,0xE2,0x57, +0x13,0x05,0x80,0x70,0xB3,0x07,0xF5,0x40,0x93,0xD6,0xF7,0x41,0x33,0xC7,0xF6,0x00,0x15,0x8F,0x93,0x06,0x20,0x03,0x63,0xDB,0xE6,0x02,0x9E,0x07,0x13,0x05,0x80,0x0C, +0x33,0xC5,0xA7,0x02,0xEF,0x30,0x80,0x57,0x93,0x07,0x00,0x40,0x33,0x45,0xF5,0x02,0x37,0x07,0x04,0x00,0x33,0x05,0x25,0x03,0x13,0x09,0xF0,0x0F,0x63,0x54,0xE5,0x00, +0x33,0x49,0xF5,0x02,0x7D,0x1B,0x05,0x47,0xE3,0x13,0x0B,0xEC,0x93,0x07,0x40,0x06,0x93,0x05,0x60,0x04,0x33,0x09,0xF9,0x02,0x85,0x67,0x93,0x87,0x77,0xE3,0x63,0xD6, +0x27,0x01,0x93,0x05,0x40,0x03,0xB3,0x45,0xB9,0x02,0x97,0xB7,0x6E,0x00,0x83,0xC7,0xB7,0xA4,0x05,0x47,0x63,0x97,0xE7,0x1A,0x97,0xB7,0x6E,0x00,0x83,0xC7,0xE7,0xA3, -+0x63,0xD3,0xB7,0x00,0xBE,0x85,0xB2,0x57,0x17,0xA5,0x6E,0x00,0x13,0x05,0x45,0x2A,0xC1,0x79,0x8C,0xC7,0xEF,0xA0,0xA0,0x04,0x9C,0x40,0x13,0x05,0x80,0x05,0x05,0x69, ++0x63,0xD3,0xB7,0x00,0xBE,0x85,0xB2,0x57,0x17,0xA5,0x6E,0x00,0x13,0x05,0x45,0x2A,0xC1,0x79,0x8C,0xC7,0xEF,0xA0,0x80,0x08,0x9C,0x40,0x13,0x05,0x80,0x05,0x05,0x69, +0x82,0x97,0x82,0x57,0x13,0x75,0xE5,0xF8,0x42,0x0A,0x93,0xF5,0x17,0x07,0x1C,0x40,0xC9,0x8D,0x13,0x05,0x80,0x05,0x82,0x97,0x9C,0x40,0x13,0x05,0x00,0x09,0x82,0x97, +0x72,0x47,0x93,0x77,0x75,0xDC,0x93,0x75,0x87,0x23,0xCD,0x8F,0x18,0x40,0xC2,0x07,0xC1,0x83,0xB3,0x75,0x35,0x01,0xDD,0x8D,0x13,0x05,0x00,0x09,0x02,0x97,0x9C,0x40, +0x13,0x05,0x49,0x81,0x82,0x97,0x82,0x47,0x93,0x95,0xA7,0x01,0xB7,0x07,0x00,0xFC,0xFD,0x17,0x7D,0x8D,0x1C,0x40,0xC9,0x8D,0x13,0x05,0x49,0x81,0x82,0x97,0x9C,0x40, @@ -12542,7 +12351,7 @@ index 000000000000..b9661763dbcc +0x80,0x07,0x82,0x97,0xA2,0x57,0x0D,0x99,0x93,0xF5,0xC7,0x01,0x1C,0x40,0xC9,0x8D,0x13,0x05,0x80,0x07,0x82,0x97,0xB7,0xE7,0xA0,0x00,0x03,0xA7,0x87,0x4B,0xB7,0x06, +0x00,0x5E,0xB3,0x79,0x37,0x01,0x33,0xEA,0x49,0x01,0x23,0xAC,0x47,0x4B,0x03,0xA7,0xC7,0x40,0x75,0x8F,0xB7,0x06,0x00,0xA2,0xFD,0x16,0xB3,0xF6,0xDD,0x00,0x55,0x8F, +0x23,0xA6,0xE7,0x40,0x03,0xA7,0x07,0x41,0xC2,0x46,0x71,0x9B,0x55,0x8F,0x23,0xA8,0xE7,0x40,0xEF,0xC0,0x1F,0xD0,0xBA,0x50,0x2A,0x54,0x9A,0x54,0x0A,0x59,0xFA,0x49, -+0x6A,0x4A,0xDA,0x4A,0x4A,0x4B,0xBA,0x4B,0x2A,0x4C,0x9A,0x4C,0x0A,0x4D,0xF6,0x5D,0x4D,0x61,0x82,0x80,0x17,0xA5,0x6E,0x00,0x13,0x05,0x85,0x0F,0xEF,0x90,0x30,0x6C, ++0x6A,0x4A,0xDA,0x4A,0x4A,0x4B,0xBA,0x4B,0x2A,0x4C,0x9A,0x4C,0x0A,0x4D,0xF6,0x5D,0x4D,0x61,0x82,0x80,0x17,0xA5,0x6E,0x00,0x13,0x05,0x85,0x0F,0xEF,0x90,0x10,0x70, +0x81,0xB3,0x93,0x07,0x40,0x06,0xE3,0xD0,0xB7,0xE6,0x97,0xA7,0x6E,0x00,0x93,0x87,0x67,0x78,0x83,0xC7,0x77,0x01,0xFD,0x17,0x93,0xF7,0xF7,0x0F,0x63,0x79,0xF7,0x00, +0x93,0x07,0xE0,0x06,0xE3,0xD1,0xB7,0xE4,0x93,0x05,0xE0,0x06,0x2D,0xBD,0x93,0x05,0x40,0x06,0x15,0xBD,0x5C,0x41,0x75,0x71,0x22,0xC5,0x26,0xC3,0x4A,0xC1,0xEA,0xD0, +0x06,0xC7,0xCE,0xDE,0xD2,0xDC,0xD6,0xDA,0xDA,0xD8,0xDE,0xD6,0xE2,0xD4,0xE6,0xD2,0xEE,0xCE,0x3E,0xD8,0x1C,0x45,0x83,0x4B,0x05,0x01,0x02,0xCA,0x02,0xCC,0x02,0xCE, @@ -12564,13 +12373,13 @@ index 000000000000..b9661763dbcc +0x98,0x40,0x56,0x85,0xBE,0xC6,0x02,0x97,0xD2,0x57,0x93,0x75,0x05,0xF8,0xB3,0xE5,0x95,0x01,0x03,0x27,0x0A,0x00,0xFD,0x8D,0xB3,0xE5,0x85,0x01,0x56,0x85,0x02,0x97, +0xB6,0x47,0xFD,0x17,0xE1,0xF3,0x83,0xA7,0x4D,0x42,0x13,0x05,0x20,0x03,0x82,0x97,0x42,0x47,0x83,0x27,0x49,0xC4,0x01,0xE7,0x13,0xD7,0xF7,0x01,0x3A,0xD0,0x37,0x07, +0x00,0x80,0xD9,0x8F,0x23,0x22,0xF9,0xC4,0x83,0x27,0x49,0xC4,0x7D,0x57,0x63,0x0F,0xEB,0x26,0xC1,0x83,0x09,0x67,0x85,0x8B,0x13,0x07,0x07,0x71,0xFD,0x56,0x95,0xE3, -+0x83,0x27,0x49,0xC4,0x63,0x06,0xDB,0x26,0xC1,0x83,0x7D,0x17,0x85,0x8B,0x65,0xFB,0x89,0x65,0x93,0x85,0x05,0x71,0x17,0xC5,0x6E,0x00,0x13,0x05,0x25,0xC3,0xEF,0x90, -+0x10,0x40,0x83,0xA7,0x4D,0x42,0x15,0x45,0x82,0x97,0x83,0x27,0x49,0xC4,0x03,0x27,0x49,0xD6,0x03,0x26,0x89,0xD6,0x93,0x15,0x27,0x00,0xB2,0x86,0x63,0xD5,0x05,0x00, ++0x83,0x27,0x49,0xC4,0x63,0x06,0xDB,0x26,0xC1,0x83,0x7D,0x17,0x85,0x8B,0x65,0xFB,0x89,0x65,0x93,0x85,0x05,0x71,0x17,0xC5,0x6E,0x00,0x13,0x05,0xE5,0xC5,0xEF,0x90, ++0xF0,0x43,0x83,0xA7,0x4D,0x42,0x15,0x45,0x82,0x97,0x83,0x27,0x49,0xC4,0x03,0x27,0x49,0xD6,0x03,0x26,0x89,0xD6,0x93,0x15,0x27,0x00,0xB2,0x86,0x63,0xD5,0x05,0x00, +0xB7,0x05,0x00,0xC0,0x2E,0x97,0x93,0x15,0x26,0x00,0x63,0xD5,0x05,0x00,0xB7,0x06,0x00,0xC0,0xB2,0x96,0x93,0xD9,0x87,0x00,0x13,0xF4,0xF7,0x07,0x83,0x27,0x49,0xC4, +0x7D,0x1B,0x93,0xF9,0xF9,0x07,0x86,0x07,0x85,0x83,0x23,0x22,0xF9,0xC4,0xF9,0x57,0x63,0x1A,0xFB,0x14,0x93,0x55,0x37,0x41,0x7D,0x87,0x33,0x4A,0xB7,0x00,0x13,0xD9, +0x36,0x41,0x33,0x0A,0xEA,0x40,0x23,0x20,0xBD,0x00,0x23,0x22,0x2D,0x01,0x23,0x24,0x8D,0x00,0x23,0x26,0x3D,0x01,0x39,0x47,0x63,0x49,0x47,0x01,0xFD,0x86,0xB3,0xC7, -+0x26,0x01,0xB3,0x86,0xD7,0x40,0x63,0x55,0xD7,0x02,0xC2,0x05,0xB3,0xE5,0x25,0x01,0x17,0xC5,0x6E,0x00,0x13,0x05,0x05,0xB8,0xEF,0x90,0x70,0x36,0x93,0x15,0x04,0x01, -+0xB3,0xE5,0x35,0x01,0x17,0xC5,0x6E,0x00,0x13,0x05,0xC5,0xB6,0xEF,0x90,0x30,0x35,0x83,0xA7,0x8D,0x7B,0x82,0x97,0xB9,0x47,0x63,0xCE,0x47,0x19,0x13,0x57,0xF9,0x41, ++0x26,0x01,0xB3,0x86,0xD7,0x40,0x63,0x55,0xD7,0x02,0xC2,0x05,0xB3,0xE5,0x25,0x01,0x17,0xC5,0x6E,0x00,0x13,0x05,0xC5,0xBA,0xEF,0x90,0x50,0x3A,0x93,0x15,0x04,0x01, ++0xB3,0xE5,0x35,0x01,0x17,0xC5,0x6E,0x00,0x13,0x05,0x85,0xB9,0xEF,0x90,0x10,0x39,0x83,0xA7,0x8D,0x7B,0x82,0x97,0xB9,0x47,0x63,0xCE,0x47,0x19,0x13,0x57,0xF9,0x41, +0x33,0x49,0x27,0x01,0x33,0x09,0xE9,0x40,0x63,0xC6,0x27,0x19,0x17,0x84,0x6E,0x00,0x13,0x04,0x84,0x55,0x63,0x82,0x0B,0x1A,0x9C,0x40,0x05,0x69,0x13,0x05,0x89,0xC0, +0x82,0x97,0x96,0x47,0x93,0x95,0x87,0x00,0xC1,0x77,0x13,0x87,0xF7,0x0F,0x79,0x8D,0x62,0x57,0x4D,0x8D,0x93,0x84,0xF7,0xFF,0x1C,0x40,0x93,0x15,0x07,0x01,0x65,0x8D, +0xC9,0x8D,0x13,0x05,0x89,0xC0,0x82,0x97,0x82,0x57,0xB7,0xF6,0xA0,0x00,0x03,0xA7,0x46,0xC4,0x93,0x95,0xF7,0x01,0xB7,0x07,0x00,0x80,0x13,0xC6,0xF7,0xFF,0x71,0x8F, @@ -12583,15 +12392,15 @@ index 000000000000..b9661763dbcc +0x33,0x14,0xF4,0x00,0xB3,0x99,0xF9,0x00,0xC2,0x57,0x93,0xCA,0xFA,0xFF,0x95,0xEF,0x93,0x87,0x0C,0xC8,0xE2,0x97,0x3E,0x85,0xBE,0xC6,0x02,0x97,0xB6,0x47,0x03,0x27, +0x0A,0x00,0xB3,0x75,0x55,0x01,0xC1,0x8D,0x3E,0x85,0x02,0x97,0x93,0x8C,0x8C,0xC9,0x9C,0x40,0x66,0x9C,0x62,0x85,0x82,0x97,0x83,0x27,0x0A,0x00,0xB3,0x75,0x55,0x01, +0xB3,0xE5,0x35,0x01,0x62,0x85,0x82,0x97,0xBD,0xBB,0x93,0x87,0xCC,0xC8,0xE2,0x97,0x3E,0x85,0xBE,0xC6,0x02,0x97,0xB6,0x47,0x03,0x27,0x0A,0x00,0xB3,0x75,0x55,0x01, -+0xC1,0x8D,0x3E,0x85,0x02,0x97,0x93,0x8C,0x4C,0xCA,0xD9,0xB7,0xE1,0x83,0x59,0xB3,0xE1,0x83,0x61,0xBB,0xF2,0x55,0x17,0xC5,0x6E,0x00,0x13,0x05,0xA5,0x9B,0xEF,0x90, -+0x10,0x1A,0xB2,0x47,0xFD,0x17,0x93,0xF7,0xF7,0x0F,0x3E,0xC6,0x85,0x47,0x3E,0xC8,0xB2,0x47,0xE3,0x8D,0x07,0xE4,0x49,0xB9,0x9C,0x40,0x05,0x69,0x13,0x05,0x89,0xC1, ++0xC1,0x8D,0x3E,0x85,0x02,0x97,0x93,0x8C,0x4C,0xCA,0xD9,0xB7,0xE1,0x83,0x59,0xB3,0xE1,0x83,0x61,0xBB,0xF2,0x55,0x17,0xC5,0x6E,0x00,0x13,0x05,0x65,0x9E,0xEF,0x90, ++0xF0,0x1D,0xB2,0x47,0xFD,0x17,0x93,0xF7,0xF7,0x0F,0x3E,0xC6,0x85,0x47,0x3E,0xC8,0xB2,0x47,0xE3,0x8D,0x07,0xE4,0x49,0xB9,0x9C,0x40,0x05,0x69,0x13,0x05,0x89,0xC1, +0x82,0x97,0x92,0x57,0x13,0x75,0xF5,0xFD,0x93,0x95,0x57,0x00,0x1C,0x40,0xC9,0x8D,0x13,0x05,0x89,0xC1,0x82,0x97,0x89,0xB5,0x01,0x11,0x22,0xCC,0x37,0xF4,0xA0,0x00, +0x83,0x27,0x84,0x80,0x37,0x07,0xF0,0xFF,0x3D,0x07,0x4A,0xC8,0x06,0xCE,0x26,0xCA,0x4E,0xC6,0xF9,0x8F,0x23,0x24,0xF4,0x80,0x83,0x27,0x44,0xD0,0x61,0x77,0x01,0x45, +0xF9,0x8F,0x11,0x67,0xD9,0x8F,0x23,0x22,0xF4,0xD0,0x83,0x27,0x04,0xD0,0x37,0x07,0x00,0xFF,0xF9,0x8F,0x93,0xE7,0x07,0x01,0x23,0x20,0xF4,0xD0,0xEF,0xC0,0x2F,0xF0, +0x83,0x27,0x44,0xC4,0x37,0x07,0x00,0x80,0xB7,0xF6,0xA0,0x00,0x13,0xD9,0xF7,0x01,0xD9,0x8F,0x23,0x22,0xF4,0xC4,0x83,0x27,0x44,0xC4,0x37,0x47,0x0F,0x00,0x13,0x07, +0x07,0x24,0xC1,0x83,0x85,0x8B,0x99,0xE7,0x83,0xA7,0x46,0xC4,0x7D,0x17,0xC1,0x83,0x85,0x8B,0x75,0xFB,0xB7,0xF7,0xA0,0x00,0x03,0xA4,0x47,0xD6,0x83,0xA7,0x87,0xD6, +0x13,0x17,0x24,0x00,0xBE,0x84,0x63,0x55,0x07,0x00,0x37,0x07,0x00,0xC0,0x3A,0x94,0x13,0x97,0x27,0x00,0x4D,0x84,0x63,0x55,0x07,0x00,0xB7,0x04,0x00,0xC0,0xBE,0x94, -+0xCD,0x84,0x93,0x15,0x04,0x01,0xC5,0x8D,0x17,0xC5,0x6E,0x00,0x13,0x05,0x45,0x8F,0xEF,0x90,0xF0,0x0A,0x63,0x52,0x04,0x08,0x33,0x04,0x80,0x40,0x63,0xD3,0x04,0x08, ++0xCD,0x84,0x93,0x15,0x04,0x01,0xC5,0x8D,0x17,0xC5,0x6E,0x00,0x13,0x05,0x05,0x92,0xEF,0x90,0xD0,0x0E,0x63,0x52,0x04,0x08,0x33,0x04,0x80,0x40,0x63,0xD3,0x04,0x08, +0xB3,0x04,0x90,0x40,0xB7,0xF9,0xA0,0x00,0x83,0xA7,0x89,0x80,0x7D,0x77,0x3D,0x07,0x13,0x74,0xF4,0x0F,0xF9,0x8F,0x12,0x04,0x5D,0x8C,0xB7,0x17,0xF0,0xFF,0xFD,0x17, +0x93,0xF4,0xF4,0x0F,0x7D,0x8C,0xB2,0x04,0xC1,0x8C,0x23,0xA4,0x99,0x80,0x83,0xA7,0x49,0xC4,0x37,0x04,0x00,0x80,0x13,0x44,0xF4,0xFF,0xE1,0x8F,0x23,0xA2,0xF9,0xC4, +0x97,0xC7,0xFF,0xFF,0x93,0x87,0x07,0xA6,0x83,0xA7,0x47,0x42,0x13,0x05,0x00,0x7D,0x82,0x97,0xEF,0xC0,0x0F,0xE6,0x83,0xA7,0x49,0xC4,0x13,0x17,0xF9,0x01,0xF2,0x40, @@ -12680,7 +12489,7 @@ index 000000000000..b9661763dbcc +0xE9,0x8D,0x22,0x04,0x93,0x77,0xD5,0x01,0x4D,0x8C,0x5D,0x8C,0x81,0x77,0x93,0x87,0x27,0x0E,0xB3,0x7C,0xF5,0x00,0xC9,0x67,0x93,0x87,0x57,0x10,0x5D,0xB4,0x89,0x47, +0xE3,0x19,0xF9,0xAA,0x83,0x27,0x0D,0x00,0x13,0x85,0x8A,0xC0,0x82,0x97,0x13,0x54,0x85,0x00,0x13,0x74,0xF4,0x0F,0xC1,0x65,0xE9,0x8D,0x22,0x04,0x93,0x77,0xD5,0x01, +0x4D,0x8C,0x5D,0x8C,0x81,0x77,0x93,0x87,0x27,0x0E,0xB3,0x7C,0xF5,0x00,0xC9,0x67,0x93,0x87,0x97,0x31,0xBD,0xB4,0x81,0x49,0x01,0x4A,0x01,0x4B,0x45,0xB4,0x17,0x95, -+0x6E,0x00,0x13,0x05,0xA5,0x1D,0xEF,0x80,0x90,0x59,0x79,0xBE,0x01,0x11,0x22,0xCC,0x26,0xCA,0x97,0x77,0x6E,0x00,0x93,0x87,0x67,0x7B,0x06,0xCE,0x4A,0xC8,0x4E,0xC6, ++0x6E,0x00,0x13,0x05,0xA5,0x1D,0xEF,0x80,0x70,0x5D,0x79,0xBE,0x01,0x11,0x22,0xCC,0x26,0xCA,0x97,0x77,0x6E,0x00,0x93,0x87,0x67,0x7B,0x06,0xCE,0x4A,0xC8,0x4E,0xC6, +0x52,0xC4,0x9C,0x43,0x13,0x74,0xF6,0x00,0x97,0x74,0x6E,0x00,0x93,0x84,0xC4,0x79,0x63,0x13,0x05,0x10,0x13,0x87,0x45,0xF7,0x13,0x0A,0x70,0x02,0xAE,0x89,0x63,0x74, +0xEA,0x0C,0x2A,0x89,0x05,0x65,0x13,0x05,0xC5,0xC1,0x82,0x97,0x93,0x07,0x30,0x0B,0x63,0xD3,0x37,0x03,0x41,0x99,0x41,0x8D,0x9C,0x40,0xAA,0x85,0x05,0x65,0x13,0x05, +0xC5,0xC1,0x82,0x97,0xF2,0x40,0x62,0x44,0x4A,0x85,0xD2,0x44,0x42,0x49,0xB2,0x49,0x22,0x4A,0x05,0x61,0x82,0x80,0xCD,0x47,0x63,0xC8,0x37,0x01,0x12,0x04,0x13,0x75, @@ -12735,10 +12544,10 @@ index 000000000000..b9661763dbcc +0xC9,0x8D,0x93,0x59,0x05,0x01,0x13,0x85,0x84,0xC0,0x82,0x97,0x1C,0x40,0x13,0x85,0x44,0xCE,0x93,0xF9,0x19,0x00,0x82,0x97,0x83,0x27,0x09,0x00,0xB7,0x05,0x00,0x80, +0xC9,0x8D,0x13,0x5A,0xF5,0x01,0x13,0x85,0x44,0xCE,0x82,0x97,0x1C,0x40,0x13,0x85,0xC4,0xCF,0x13,0x0B,0x80,0x3E,0x82,0x97,0x81,0x45,0x93,0x84,0xC4,0xCF,0x13,0x75, +0x05,0x10,0x49,0xE1,0x1C,0x40,0x26,0x85,0x2E,0xC6,0x82,0x97,0xB2,0x45,0x85,0x05,0xE3,0x97,0x65,0xFF,0x1C,0x40,0x85,0x64,0x13,0x85,0xC4,0xCF,0x82,0x97,0xAA,0x85, -+0x2A,0x8B,0x23,0xA0,0xAA,0x00,0x17,0x95,0x6E,0x00,0x13,0x05,0xA5,0xB1,0xEF,0x80,0x00,0x6B,0x1C,0x40,0x13,0x85,0x84,0xC0,0x7E,0x0A,0x82,0x97,0xC1,0x77,0xFD,0x17, ++0x2A,0x8B,0x23,0xA0,0xAA,0x00,0x17,0x95,0x6E,0x00,0x13,0x05,0xA5,0xB1,0xEF,0x80,0xE0,0x6E,0x1C,0x40,0x13,0x85,0x84,0xC0,0x7E,0x0A,0x82,0x97,0xC1,0x77,0xFD,0x17, +0x7D,0x8D,0x83,0x27,0x09,0x00,0x93,0x95,0x09,0x01,0xC9,0x8D,0x13,0x85,0x84,0xC0,0x82,0x97,0x1C,0x40,0x13,0x85,0x44,0xCE,0x82,0x97,0x93,0x15,0x15,0x00,0x83,0x27, +0x09,0x00,0x85,0x81,0x13,0x85,0x44,0xCE,0xB3,0xE5,0x45,0x01,0x82,0x97,0xB2,0x50,0x22,0x54,0x5A,0x85,0x92,0x54,0x02,0x59,0xF2,0x49,0x62,0x4A,0xD2,0x4A,0x42,0x4B, -+0x45,0x61,0x82,0x80,0x17,0x95,0x6E,0x00,0x13,0x05,0x85,0xAA,0xEF,0x80,0x20,0x65,0x51,0xB7,0x19,0x71,0xA2,0xDC,0xA6,0xDA,0x86,0xDE,0xCA,0xD8,0xCE,0xD6,0xD2,0xD4, ++0x45,0x61,0x82,0x80,0x17,0x95,0x6E,0x00,0x13,0x05,0x85,0xAA,0xEF,0x80,0x00,0x69,0x51,0xB7,0x19,0x71,0xA2,0xDC,0xA6,0xDA,0x86,0xDE,0xCA,0xD8,0xCE,0xD6,0xD2,0xD4, +0xD6,0xD2,0xDA,0xD0,0xDE,0xCE,0xE2,0xCC,0xE6,0xCA,0x85,0x47,0x2A,0x84,0xAE,0x84,0x63,0xF6,0xB7,0x4E,0x93,0x87,0xE5,0xFF,0x13,0xBA,0x17,0x00,0x01,0x49,0x93,0x07, +0x56,0x0D,0x92,0x07,0xA2,0x97,0x97,0x7C,0x6E,0x00,0x93,0x8C,0x2C,0x04,0x83,0xA9,0xC7,0x00,0x83,0xA7,0x0C,0x00,0x85,0x6A,0x13,0x85,0x8A,0xCE,0x36,0xC6,0x32,0xC4, +0x17,0x7C,0x6E,0x00,0x13,0x0C,0x4C,0x02,0x82,0x97,0x83,0x27,0x0C,0x00,0x37,0x0B,0x00,0x80,0x93,0x4B,0xFB,0xFF,0xB3,0x75,0x75,0x01,0x13,0x85,0x8A,0xCE,0x82,0x97, @@ -12791,7 +12600,7 @@ index 000000000000..b9661763dbcc +0xB3,0xE5,0x15,0x01,0x23,0xA6,0xB6,0x42,0x83,0xC8,0x07,0x19,0x83,0xA5,0x06,0x43,0x13,0x93,0x88,0x00,0xB3,0xF5,0xE8,0x00,0xB3,0xE5,0x65,0x00,0xB3,0xF5,0x05,0x01, +0x13,0x93,0x08,0x01,0xB3,0xE5,0x65,0x00,0xE2,0x08,0xE9,0x8D,0xB3,0xE5,0x15,0x01,0x23,0xA8,0xB6,0x42,0x83,0xA5,0x46,0x43,0x83,0xC5,0x07,0x19,0x93,0x98,0x85,0x00, +0x6D,0x8F,0x33,0x67,0x17,0x01,0x33,0x77,0x07,0x01,0x93,0x98,0x05,0x01,0x33,0x67,0x17,0x01,0xE2,0x05,0x69,0x8F,0x4D,0x8F,0x23,0xAA,0xE6,0x42,0x17,0x95,0x6E,0x00, -+0x03,0x45,0x55,0x8A,0x01,0x47,0x97,0x95,0x6E,0x00,0x93,0x85,0x25,0x9A,0x93,0x06,0xB0,0x02,0x33,0x08,0xB7,0x00,0x03,0x48,0x08,0x00,0x63,0x19,0xA8,0x0C,0x97,0x96, ++0x03,0x45,0x55,0x8A,0x01,0x47,0x97,0x95,0x6E,0x00,0x93,0x85,0xA5,0x9B,0x93,0x06,0xB0,0x02,0x33,0x08,0xB7,0x00,0x03,0x48,0x08,0x00,0x63,0x19,0xA8,0x0C,0x97,0x96, +0x6E,0x00,0x93,0x86,0x26,0x87,0x36,0x97,0x03,0x48,0xA7,0x0C,0x97,0x95,0x6E,0x00,0x93,0x85,0x45,0x86,0x81,0x46,0x2E,0x87,0x91,0x48,0x03,0xC3,0x65,0x0C,0x63,0x1D, +0x03,0x0A,0x85,0x06,0x85,0x05,0xE3,0x9A,0x16,0xFF,0x63,0x9F,0x04,0x2C,0xB7,0x16,0x13,0x1A,0xB7,0xE5,0xA0,0x00,0x93,0x86,0xC6,0xD0,0x23,0xAE,0xD5,0x5A,0xB7,0x26, +0x23,0x00,0x93,0x86,0xE6,0x21,0x23,0xA0,0xD5,0x5C,0x83,0xA6,0xC7,0x18,0x83,0xA7,0x87,0x18,0x97,0x98,0x6E,0x00,0x83,0xC8,0xA8,0x92,0xA2,0x06,0x17,0x93,0x6E,0x00, @@ -12834,7 +12643,7 @@ index 000000000000..b9661763dbcc +0xF9,0x75,0x9C,0x40,0x93,0x85,0xF5,0x0F,0xE9,0x8D,0xA2,0x09,0xB3,0xE5,0x35,0x01,0x13,0x05,0x00,0x40,0x82,0x97,0x1C,0x40,0x13,0x05,0x00,0x40,0x82,0x97,0x9C,0x40, +0x93,0x65,0x15,0x00,0x13,0x05,0x00,0x40,0x82,0x97,0x1C,0x40,0x13,0x05,0x80,0x40,0xB7,0x44,0x0F,0x00,0x82,0x97,0x93,0x84,0x04,0x24,0x63,0x48,0x05,0x00,0x1C,0x40, +0x13,0x05,0x80,0x40,0xFD,0x14,0x82,0x97,0xED,0xF8,0xF2,0x40,0x62,0x44,0xD2,0x44,0x42,0x49,0xB2,0x49,0x22,0x4A,0x05,0x61,0x82,0x80,0x41,0x75,0x22,0x09,0x13,0x05, -+0xF5,0x0F,0x51,0xB7,0x41,0x11,0x22,0xC4,0x06,0xC6,0x2A,0x84,0x31,0x37,0x22,0x85,0x22,0x44,0xB2,0x40,0x41,0x01,0x6F,0x80,0x00,0x64,0x35,0x71,0xE2,0xDC,0x17,0x6C, ++0xF5,0x0F,0x51,0xB7,0x41,0x11,0x22,0xC4,0x06,0xC6,0x2A,0x84,0x31,0x37,0x22,0x85,0x22,0x44,0xB2,0x40,0x41,0x01,0x6F,0x80,0x80,0x6A,0x35,0x71,0xE2,0xDC,0x17,0x6C, +0x6E,0x00,0x13,0x0C,0xAC,0x46,0x83,0x27,0x0C,0x00,0x06,0xCF,0x22,0xCD,0x26,0xCB,0x4A,0xC9,0x4E,0xC7,0x52,0xC5,0x56,0xC3,0x5A,0xC1,0xDE,0xDE,0xE6,0xDA,0xEA,0xD8, +0xEE,0xD6,0xAA,0x8B,0x71,0x45,0x32,0xC0,0x2E,0x89,0x82,0x97,0x97,0x64,0x6E,0x00,0x93,0x84,0x84,0x43,0x93,0x65,0x85,0x23,0xC1,0x77,0x93,0x1C,0x05,0x01,0xC2,0x05, +0x7D,0x8D,0x9C,0x40,0xC1,0x81,0xC9,0x8D,0x71,0x45,0x82,0x97,0x83,0x27,0x0C,0x00,0x05,0x64,0x13,0x05,0x84,0x80,0x82,0x97,0x02,0x46,0xB7,0x05,0xE4,0xFF,0x13,0x79, @@ -12865,8 +12674,8 @@ index 000000000000..b9661763dbcc +0xE6,0x01,0x33,0x66,0x66,0x00,0x37,0x03,0x00,0x80,0x33,0x66,0x66,0x00,0x23,0xAA,0xC7,0x4A,0x03,0xA6,0x87,0x4B,0x13,0x5E,0xC7,0x00,0x93,0x7D,0xFE,0x0F,0xC1,0x74, +0x13,0x76,0x06,0xF0,0x13,0x83,0xF4,0x0F,0x93,0x7E,0xF7,0x0F,0x33,0x66,0xB6,0x01,0x13,0x77,0xF7,0x0F,0x13,0x1F,0x87,0x00,0x33,0x76,0x66,0x00,0x33,0x66,0xE6,0x01, +0x83,0x26,0x88,0x7B,0x23,0xAC,0xC7,0x4A,0x23,0xA4,0xDB,0x01,0x23,0xA0,0xBB,0x00,0x23,0xA2,0xAB,0x00,0x23,0xA6,0xBB,0x01,0x76,0xD2,0x2E,0xD6,0x2A,0xD4,0x82,0x96, -+0xB2,0x55,0x22,0x55,0x93,0xFC,0x8C,0x23,0xC2,0x05,0xC9,0x8D,0x17,0x85,0x6E,0x00,0x13,0x05,0x85,0xAF,0xEF,0x70,0xA0,0x66,0x92,0x5E,0x17,0x85,0x6E,0x00,0x13,0x05, -+0xA5,0xAF,0x22,0x0A,0x93,0x95,0x0E,0x01,0xB3,0xE5,0xB5,0x01,0xEF,0x70,0x20,0x65,0x14,0x40,0x71,0x45,0x97,0x6D,0x6E,0x00,0x93,0x8D,0x0D,0x07,0x82,0x96,0x93,0x75, ++0xB2,0x55,0x22,0x55,0x93,0xFC,0x8C,0x23,0xC2,0x05,0xC9,0x8D,0x17,0x85,0x6E,0x00,0x13,0x05,0x85,0xAF,0xEF,0x70,0x80,0x6A,0x92,0x5E,0x17,0x85,0x6E,0x00,0x13,0x05, ++0xA5,0xAF,0x22,0x0A,0x93,0x95,0x0E,0x01,0xB3,0xE5,0xB5,0x01,0xEF,0x70,0x00,0x69,0x14,0x40,0x71,0x45,0x97,0x6D,0x6E,0x00,0x93,0x8D,0x0D,0x07,0x82,0x96,0x93,0x75, +0x75,0xDC,0xB3,0xEC,0x95,0x01,0x03,0xA6,0x0D,0x00,0xC2,0x0C,0xB3,0x75,0x95,0x00,0x93,0xDC,0x0C,0x01,0xB3,0xE5,0x95,0x01,0x71,0x45,0x02,0x96,0x10,0x40,0x85,0x6C, +0x13,0x85,0x8C,0x80,0x02,0x96,0xB7,0x05,0x04,0xFE,0x93,0x85,0xF5,0xF7,0x6D,0x8D,0xB7,0x05,0xFC,0x01,0x03,0xA6,0x0D,0x00,0x93,0x85,0x05,0x08,0xB3,0x75,0xBB,0x00, +0xC9,0x8D,0x13,0x85,0x8C,0x80,0x02,0x96,0x10,0x40,0x13,0x85,0x8C,0xC0,0x2A,0x09,0x02,0x96,0xC1,0x77,0x13,0x83,0xF7,0x0F,0x33,0x75,0x65,0x00,0x03,0xA7,0x0D,0x00, @@ -12881,7 +12690,7 @@ index 000000000000..b9661763dbcc +0xD9,0x8E,0x23,0xA6,0xD8,0x82,0x03,0xA7,0x87,0x4B,0xB2,0x46,0xBA,0x49,0x33,0x77,0x47,0x01,0xC2,0x06,0x55,0x8F,0xE2,0x46,0x22,0x07,0x21,0x83,0xE2,0x06,0x55,0x8F, +0x23,0xAC,0xE7,0x4A,0x03,0xA7,0x87,0x5B,0xD2,0x46,0x2A,0x4A,0x13,0x77,0x07,0xF0,0x55,0x8F,0x23,0xAC,0xE7,0x5A,0x83,0xA7,0x88,0xC3,0x42,0x47,0x9A,0x4A,0xC1,0x9B, +0xD9,0x8F,0x0A,0x4B,0xF6,0x5B,0x66,0x5C,0xD6,0x5C,0x46,0x5D,0x23,0xAC,0xF8,0xC2,0xB6,0x5D,0x0D,0x61,0x82,0x80,0x17,0x85,0x6E,0x00,0x13,0x05,0xA5,0x8F,0xEF,0x70, -+0x00,0x48,0x17,0x98,0xFF,0xFF,0x13,0x08,0xE8,0x67,0x8D,0xB3,0xB7,0xF7,0xA0,0x00,0x83,0xA7,0x87,0xD1,0x35,0x71,0x37,0x47,0x0F,0x00,0xD9,0x83,0x22,0xCF,0x26,0xCD, ++0xE0,0x4B,0x17,0x98,0xFF,0xFF,0x13,0x08,0xE8,0x67,0x8D,0xB3,0xB7,0xF7,0xA0,0x00,0x83,0xA7,0x87,0xD1,0x35,0x71,0x37,0x47,0x0F,0x00,0xD9,0x83,0x22,0xCF,0x26,0xCD, +0x4A,0xCB,0x4E,0xC9,0x52,0xC7,0x85,0x8B,0x13,0x07,0x07,0x24,0xB7,0xF6,0xA0,0x00,0x99,0xE7,0x83,0xA7,0x86,0xD1,0x7D,0x17,0xD9,0x83,0x85,0x8B,0x75,0xFB,0xB7,0xB7, +0xA0,0x00,0x23,0xA8,0x07,0x00,0x37,0x07,0x04,0x00,0x23,0xA2,0x07,0x00,0x71,0x17,0x23,0xA0,0xE7,0x1A,0x97,0x87,0x6E,0x00,0x83,0xC7,0xF7,0xD0,0x93,0xF7,0xF7,0x07, +0x17,0x87,0x6E,0x00,0xA3,0x01,0xF7,0xD0,0x99,0xE7,0xB7,0xD7,0xA0,0x00,0x13,0x07,0xF0,0x07,0x23,0xA2,0xE7,0x0E,0xB7,0xF7,0xA0,0x00,0x03,0xA7,0xC7,0xD7,0x03,0xA8, @@ -12994,14 +12803,14 @@ index 000000000000..b9661763dbcc +0x27,0x00,0x4D,0x85,0x63,0xD5,0x06,0x00,0xB7,0x07,0x00,0xC0,0xBA,0x97,0x02,0x57,0xCD,0x87,0x19,0x8D,0x12,0x57,0x33,0x05,0xA5,0x02,0x99,0x8F,0xB3,0x87,0xF7,0x02, +0x3E,0x95,0x49,0x34,0x83,0xA7,0x49,0xC4,0x37,0x07,0x00,0x80,0x13,0x47,0xF7,0xFF,0xF9,0x8F,0xAA,0xC6,0x23,0xA2,0xF9,0xC4,0xEF,0x90,0xAF,0xC9,0x36,0x45,0x72,0x47, +0x93,0x07,0x75,0xF2,0x92,0x07,0x13,0x05,0x40,0x06,0xB3,0x87,0x87,0x41,0xB3,0x87,0xA7,0x02,0x17,0x75,0x6E,0x00,0x13,0x05,0x65,0xB2,0xB3,0xC7,0xE7,0x02,0xBE,0x85, -+0xBE,0xC6,0xEF,0x60,0xC0,0x65,0xB6,0x47,0x13,0x05,0x20,0x6C,0xB3,0x07,0xF5,0x40,0x93,0xD6,0xF7,0x41,0x33,0xC7,0xF6,0x00,0x15,0x8F,0x93,0x06,0x20,0x03,0x63,0xD8, ++0xBE,0xC6,0xEF,0x60,0xA0,0x69,0xB6,0x47,0x13,0x05,0x20,0x6C,0xB3,0x07,0xF5,0x40,0x93,0xD6,0xF7,0x41,0x33,0xC7,0xF6,0x00,0x15,0x8F,0x93,0x06,0x20,0x03,0x63,0xD8, +0xE6,0x02,0x9E,0x07,0x13,0x05,0x80,0x0C,0x33,0xC5,0xA7,0x02,0xC5,0x3C,0x33,0x05,0x85,0x02,0xB7,0x07,0x00,0x10,0x13,0x04,0xF0,0x0F,0x63,0x56,0xF5,0x00,0x37,0x04, +0x10,0x00,0x33,0x44,0x85,0x02,0xFD,0x1C,0x85,0x46,0xE3,0x9A,0x0C,0xEC,0x93,0x07,0x40,0x06,0x18,0x09,0x33,0x04,0xF4,0x02,0x93,0x07,0xA0,0x03,0x33,0x44,0xF4,0x02, +0xF2,0x57,0x8A,0x07,0xBA,0x97,0x83,0xA7,0xC7,0xFC,0x63,0x73,0xF4,0x00,0x3E,0x84,0x97,0x76,0x6E,0x00,0x83,0xC6,0x56,0xFC,0x05,0x47,0x63,0x91,0xE6,0x02,0x97,0x77, -+0x6E,0x00,0x83,0xC7,0x97,0xFB,0x63,0xDF,0x87,0x00,0x3E,0x84,0x21,0xA8,0x17,0x75,0x6E,0x00,0x13,0x05,0x65,0xA7,0xEF,0x60,0x80,0x5C,0xF5,0xB5,0x93,0x87,0xC7,0x03, -+0xE3,0xE5,0x87,0xFE,0xA2,0x85,0x17,0x75,0x6E,0x00,0x13,0x05,0xE5,0xA7,0xEF,0x60,0x00,0x5B,0x96,0x47,0xA8,0x08,0x83,0xA7,0x87,0x42,0x82,0x97,0xE6,0x47,0x13,0x07, ++0x6E,0x00,0x83,0xC7,0x97,0xFB,0x63,0xDF,0x87,0x00,0x3E,0x84,0x21,0xA8,0x17,0x75,0x6E,0x00,0x13,0x05,0x65,0xA7,0xEF,0x60,0x60,0x60,0xF5,0xB5,0x93,0x87,0xC7,0x03, ++0xE3,0xE5,0x87,0xFE,0xA2,0x85,0x17,0x75,0x6E,0x00,0x13,0x05,0xE5,0xA7,0xEF,0x60,0xE0,0x5E,0x96,0x47,0xA8,0x08,0x83,0xA7,0x87,0x42,0x82,0x97,0xE6,0x47,0x13,0x07, +0xF0,0x02,0x93,0x86,0x07,0xFB,0x63,0x63,0xD7,0x1A,0x0E,0x04,0xA9,0x47,0x33,0x44,0xF4,0x02,0xE2,0x57,0xA2,0x85,0x17,0x75,0x6E,0x00,0x13,0x05,0xE5,0xA4,0x80,0xC7, -+0xEF,0x60,0xE0,0x57,0x83,0x27,0x09,0x00,0x71,0x45,0xC1,0x79,0x82,0x97,0x62,0x47,0x93,0x77,0x75,0xDC,0x05,0x64,0x93,0x75,0x87,0x23,0xCD,0x8F,0x98,0x40,0xC2,0x07, ++0xEF,0x60,0xC0,0x5B,0x83,0x27,0x09,0x00,0x71,0x45,0xC1,0x79,0x82,0x97,0x62,0x47,0x93,0x77,0x75,0xDC,0x05,0x64,0x93,0x75,0x87,0x23,0xCD,0x8F,0x98,0x40,0xC2,0x07, +0xC1,0x83,0xB3,0x75,0x35,0x01,0xDD,0x8D,0x71,0x45,0x02,0x97,0x83,0x27,0x09,0x00,0x13,0x05,0x80,0x05,0x62,0x0B,0x82,0x97,0xB2,0x57,0x13,0x75,0xE5,0xF8,0xFE,0x0A, +0x93,0xF5,0x17,0x07,0x9C,0x40,0xC9,0x8D,0x13,0x05,0x80,0x05,0x82,0x97,0x83,0x27,0x09,0x00,0x13,0x05,0x84,0x80,0x82,0x97,0xB7,0x05,0x04,0xFE,0xF9,0x15,0x6D,0x8D, +0xB7,0x05,0xFC,0x01,0x9C,0x40,0x85,0x05,0xB3,0xF5,0xBB,0x00,0xC9,0x8D,0x13,0x05,0x84,0x80,0x82,0x97,0x83,0x27,0x09,0x00,0x13,0x05,0x84,0xC0,0x82,0x97,0xA2,0x57, @@ -13068,13 +12877,13 @@ index 000000000000..b9661763dbcc +0x93,0xC5,0xF7,0xC3,0x03,0x27,0x09,0x00,0x93,0x87,0x07,0x08,0xE9,0x8D,0xDD,0x8D,0xAA,0x89,0x13,0x85,0x44,0xCE,0x02,0x97,0x1C,0x40,0x13,0x85,0xC4,0xCF,0x13,0x7B, +0x1B,0x00,0x82,0x97,0x81,0x45,0x93,0x84,0xC4,0xCF,0x13,0x0C,0x80,0x3E,0x13,0x75,0x05,0x10,0x7D,0xE1,0x1C,0x40,0x26,0x85,0x2E,0xC6,0x82,0x97,0xB2,0x45,0x85,0x05, +0xE3,0x97,0x85,0xFF,0x1C,0x40,0x85,0x64,0x13,0x85,0xC4,0xCF,0x82,0x97,0x2A,0x8C,0xAA,0x85,0x23,0xA2,0xAA,0x00,0x17,0x65,0x6E,0x00,0x13,0x05,0xE5,0x20,0xEF,0x50, -+0x10,0x52,0x1C,0x40,0x13,0x85,0x84,0xCE,0xB7,0x0A,0x10,0xF8,0x82,0x97,0xFD,0x1A,0x83,0x27,0x09,0x00,0x93,0x7C,0xFC,0x07,0xD2,0x0C,0xB3,0x75,0x55,0x01,0xB3,0xE5, ++0xF0,0x55,0x1C,0x40,0x13,0x85,0x84,0xCE,0xB7,0x0A,0x10,0xF8,0x82,0x97,0xFD,0x1A,0x83,0x27,0x09,0x00,0x93,0x7C,0xFC,0x07,0xD2,0x0C,0xB3,0x75,0x55,0x01,0xB3,0xE5, +0x95,0x01,0x13,0x85,0x84,0xCE,0x82,0x97,0x1C,0x40,0x13,0x85,0xC4,0xCE,0xA2,0x0B,0x82,0x97,0x83,0x27,0x09,0x00,0xB3,0x75,0x55,0x01,0xB3,0xE5,0x95,0x01,0x13,0x85, +0xC4,0xCE,0x82,0x97,0x1C,0x40,0x13,0x85,0x84,0xC0,0x42,0x0B,0x82,0x97,0x41,0x77,0x93,0x07,0xF7,0x0F,0xE9,0x8F,0xB3,0xE7,0x77,0x01,0x7D,0x17,0xF9,0x8F,0xB3,0xE7, +0x67,0x01,0x03,0x27,0x09,0x00,0x89,0x9B,0x93,0x75,0xDA,0x01,0xDD,0x8D,0x13,0x85,0x84,0xC0,0x02,0x97,0x1C,0x40,0x13,0x85,0x44,0xCE,0x82,0x97,0xB7,0x07,0x00,0x80, +0x93,0xC5,0xF7,0xC3,0x93,0x87,0x07,0x3C,0xB3,0xF9,0xF9,0x00,0x83,0x27,0x09,0x00,0xE9,0x8D,0xB3,0xE5,0x35,0x01,0x13,0x85,0x44,0xCE,0x82,0x97,0xF2,0x50,0x62,0x54, +0x62,0x85,0xD2,0x54,0x42,0x59,0xB2,0x59,0x22,0x5A,0x92,0x5A,0x02,0x5B,0xF2,0x4B,0x62,0x4C,0xD2,0x4C,0x21,0x61,0x82,0x80,0x17,0x65,0x6E,0x00,0x13,0x05,0x85,0x13, -+0xEF,0x50,0xF0,0x45,0x05,0xB7,0x01,0x11,0x22,0xCC,0x2A,0x84,0x11,0x45,0x2E,0xC6,0x06,0xCE,0xEF,0x30,0x7E,0x9A,0xB2,0x45,0x85,0x47,0x63,0x9C,0xF5,0x0A,0x93,0x77, ++0xEF,0x50,0xD0,0x49,0x05,0xB7,0x01,0x11,0x22,0xCC,0x2A,0x84,0x11,0x45,0x2E,0xC6,0x06,0xCE,0xEF,0x30,0x7E,0x9A,0xB2,0x45,0x85,0x47,0x63,0x9C,0xF5,0x0A,0x93,0x77, +0x85,0x00,0xD1,0xCF,0x97,0x66,0x6E,0x00,0x93,0x86,0xC6,0x50,0x83,0xC7,0x66,0x06,0x37,0x16,0xF0,0x00,0x83,0xC6,0x76,0x06,0x58,0x52,0xB6,0x97,0x93,0x56,0x85,0x01, +0xB6,0x97,0xFD,0x76,0x93,0xF7,0xF7,0x0F,0xBD,0x06,0x92,0x07,0x75,0x8F,0xD9,0x8F,0x5C,0xD2,0x85,0x47,0x63,0x11,0xF4,0x06,0x93,0x77,0x45,0x00,0xD5,0xC3,0xB7,0x16, +0xF0,0x00,0xDC,0x5A,0x13,0x57,0x05,0x01,0x37,0x86,0xC0,0xFF,0x7D,0x16,0x13,0x77,0xF7,0x07,0x3E,0x07,0xF1,0x8F,0xD9,0x8F,0xDC,0xDA,0x98,0x52,0x93,0x57,0x25,0x01, @@ -13121,10 +12930,10 @@ index 000000000000..b9661763dbcc +0x03,0xA6,0x0A,0x01,0x83,0x27,0x4A,0x4E,0x83,0xA6,0x8A,0x00,0x03,0x27,0x04,0x43,0x91,0x8F,0x9A,0x07,0x99,0x83,0xB6,0x97,0x97,0x66,0x6E,0x00,0x23,0xA2,0xF6,0xBC, +0x01,0x45,0x02,0x97,0x97,0x47,0x6E,0x00,0x23,0xA0,0x07,0xE0,0x83,0x27,0xCA,0x54,0x97,0x46,0x6E,0x00,0x93,0x86,0x06,0x8B,0x03,0x27,0x04,0x46,0xB6,0x97,0x23,0x84, +0x07,0x50,0x35,0x45,0x02,0x97,0x93,0xE9,0x29,0x00,0x91,0xB7,0x83,0x27,0x84,0x57,0x82,0x97,0x83,0x27,0x04,0x46,0x17,0x47,0x6E,0x00,0xA3,0x0F,0x07,0xD4,0xBD,0xB7, -+0x83,0xA5,0x4A,0x00,0x17,0x75,0x6E,0x00,0x13,0x05,0x85,0x6C,0xEF,0x50,0x20,0x67,0x83,0xA7,0x8A,0x00,0xB7,0x05,0x00,0x80,0x01,0x46,0xDD,0x8D,0x17,0x75,0x6E,0x00, -+0x13,0x05,0x05,0x6B,0xEF,0x50,0xA0,0x65,0x97,0x67,0x6E,0x00,0x23,0x86,0x07,0xB4,0x97,0x67,0x6E,0x00,0x23,0xA4,0x07,0xB4,0x97,0x67,0x6E,0x00,0x23,0xA2,0x07,0xB4, -+0x45,0xBB,0xAA,0x85,0x17,0x75,0x6E,0x00,0x13,0x05,0x05,0x69,0xEF,0x50,0x20,0x63,0x31,0xBD,0x83,0x27,0xC4,0x57,0x82,0x97,0xF9,0xB5,0xDE,0x85,0x17,0x75,0x6E,0x00, -+0x13,0x05,0x05,0x68,0xEF,0x50,0xA0,0x61,0xB1,0xB5,0x97,0x46,0x6E,0x00,0x83,0xC6,0x36,0xCE,0x97,0x05,0x6E,0x00,0x93,0x85,0xE5,0x80,0x96,0x06,0xB3,0x87,0xD5,0x00, ++0x83,0xA5,0x4A,0x00,0x17,0x75,0x6E,0x00,0x13,0x05,0x45,0x6F,0xEF,0x50,0x00,0x6B,0x83,0xA7,0x8A,0x00,0xB7,0x05,0x00,0x80,0x01,0x46,0xDD,0x8D,0x17,0x75,0x6E,0x00, ++0x13,0x05,0xC5,0x6D,0xEF,0x50,0x80,0x69,0x97,0x67,0x6E,0x00,0x23,0x86,0x07,0xB4,0x97,0x67,0x6E,0x00,0x23,0xA4,0x07,0xB4,0x97,0x67,0x6E,0x00,0x23,0xA2,0x07,0xB4, ++0x45,0xBB,0xAA,0x85,0x17,0x75,0x6E,0x00,0x13,0x05,0xC5,0x6B,0xEF,0x50,0x00,0x67,0x31,0xBD,0x83,0x27,0xC4,0x57,0x82,0x97,0xF9,0xB5,0xDE,0x85,0x17,0x75,0x6E,0x00, ++0x13,0x05,0xC5,0x6A,0xEF,0x50,0x80,0x65,0xB1,0xB5,0x97,0x46,0x6E,0x00,0x83,0xC6,0x36,0xCE,0x97,0x05,0x6E,0x00,0x93,0x85,0xE5,0x80,0x96,0x06,0xB3,0x87,0xD5,0x00, +0x11,0x67,0x3E,0x97,0x03,0x26,0x07,0x49,0x83,0x27,0x47,0x49,0x03,0x27,0xC7,0x47,0x61,0x82,0x93,0xF7,0xF7,0x0F,0xA2,0x07,0x0D,0x8B,0x0D,0x48,0xD1,0x8F,0x63,0x03, +0x07,0x01,0x82,0x80,0x13,0x87,0x17,0x00,0x05,0x66,0x41,0x11,0x63,0x77,0xC7,0x0A,0xAE,0x96,0x91,0x65,0xAE,0x96,0x93,0x17,0x07,0x01,0xC1,0x83,0x03,0xC7,0x36,0x49, +0x13,0xF6,0xF7,0x0F,0xA3,0x89,0xC6,0x48,0x13,0xD7,0x87,0x00,0x03,0xC6,0x46,0x49,0x23,0x8A,0xE6,0x48,0x17,0x37,0x6E,0x00,0x13,0x07,0xC7,0x7A,0x83,0x25,0xC7,0x4B, @@ -13182,7 +12991,7 @@ index 000000000000..b9661763dbcc +0xB3,0x87,0xE4,0x00,0x11,0x67,0x3E,0x97,0x4A,0xC0,0x06,0xC6,0x83,0x47,0x87,0x50,0x17,0x79,0xFF,0xFF,0x13,0x09,0x09,0x13,0x85,0x07,0x93,0xF7,0xF7,0x0F,0x23,0x04, +0xF7,0x50,0x83,0x27,0x44,0x54,0x85,0x07,0x17,0x37,0x6E,0x00,0x23,0x2E,0xF7,0x64,0x03,0x27,0x44,0x54,0x83,0x27,0x84,0x54,0x63,0xF7,0xE7,0x04,0x83,0x27,0x09,0x43, +0x01,0x45,0x82,0x97,0x83,0x27,0x89,0x57,0x82,0x97,0x83,0x27,0x09,0x46,0x17,0x37,0x6E,0x00,0xA3,0x03,0x07,0x5C,0x35,0x45,0x17,0x37,0x6E,0x00,0x23,0x00,0x07,0x64, -+0x82,0x97,0xB7,0x67,0xF0,0x00,0x23,0xA4,0x07,0x20,0x17,0x75,0x6E,0x00,0x13,0x05,0xE5,0xF3,0x97,0x37,0x6E,0x00,0x23,0xA9,0x07,0x60,0xEF,0x40,0x70,0x6B,0x83,0x27, ++0x82,0x97,0xB7,0x67,0xF0,0x00,0x23,0xA4,0x07,0x20,0x17,0x75,0x6E,0x00,0x13,0x05,0xA5,0xF6,0x97,0x37,0x6E,0x00,0x23,0xA9,0x07,0x60,0xEF,0x40,0x50,0x6F,0x83,0x27, +0x09,0x55,0x82,0x97,0x3D,0xC5,0xB7,0x67,0xF0,0x00,0x83,0xA7,0x87,0x20,0x03,0x27,0xC4,0x54,0x9D,0x46,0x63,0x08,0xD7,0x04,0x89,0x66,0x93,0x86,0x06,0x27,0x36,0x97, +0x06,0x07,0x03,0x46,0x04,0x55,0xBA,0x94,0x83,0xC6,0x14,0x01,0x13,0x97,0x07,0x01,0x41,0x83,0x32,0x97,0x41,0x76,0xF1,0x8F,0x63,0xF6,0xE6,0x00,0x03,0xC7,0x14,0x01, +0x13,0x77,0xF7,0x0F,0xD9,0x8F,0x37,0x67,0xF0,0x00,0x23,0x24,0xF7,0x20,0x83,0x25,0x44,0x55,0x22,0x44,0x03,0x23,0xC9,0x45,0xB2,0x40,0x92,0x44,0x02,0x49,0x35,0x45, @@ -13268,11 +13077,11 @@ index 000000000000..b9661763dbcc +0x03,0x47,0x07,0x00,0x0D,0x8B,0x16,0x07,0x11,0x07,0xBA,0x97,0x23,0x82,0x07,0x00,0xA3,0x82,0x07,0x00,0x23,0x83,0x07,0x00,0xA3,0x83,0x07,0x00,0xA3,0x81,0x07,0x00, +0x23,0x80,0xD7,0x00,0xA3,0x80,0x07,0x00,0x23,0x81,0xD7,0x00,0x83,0x26,0x84,0x4C,0x03,0xC7,0x06,0x00,0x05,0x07,0x23,0x80,0xE6,0x00,0x03,0xA7,0xC4,0x18,0x23,0x82, +0x57,0x01,0xA3,0x82,0x07,0x00,0x23,0x83,0x07,0x00,0xA3,0x83,0x07,0x00,0x02,0x97,0x97,0x57,0x6E,0x00,0xA3,0x84,0x57,0xD3,0xF1,0xBD,0x83,0x45,0xF1,0x00,0xF9,0x34, -+0x97,0x57,0x6E,0x00,0xA3,0x89,0x47,0xD1,0xBD,0xB5,0x42,0x0A,0xB3,0x65,0xBA,0x00,0x17,0x65,0x6E,0x00,0x13,0x05,0x05,0x49,0xEF,0x40,0x60,0x40,0x83,0x47,0x01,0x01, ++0x97,0x57,0x6E,0x00,0xA3,0x89,0x47,0xD1,0xBD,0xB5,0x42,0x0A,0xB3,0x65,0xBA,0x00,0x17,0x65,0x6E,0x00,0x13,0x05,0xC5,0x4B,0xEF,0x40,0x40,0x44,0x83,0x47,0x01,0x01, +0x17,0x57,0x6E,0x00,0xA3,0x0A,0xF7,0x90,0xC9,0xB5,0x97,0x64,0xFF,0xFF,0x93,0x84,0x64,0x5F,0x83,0xA7,0x04,0x55,0x82,0x97,0x63,0x15,0x05,0x10,0x83,0xA7,0xC4,0x4B, -+0x17,0x65,0x6E,0x00,0x13,0x05,0x45,0x45,0x82,0x97,0x83,0xA7,0x84,0x4B,0x97,0x55,0x6E,0x00,0x83,0xC5,0x05,0xCC,0x11,0x45,0x82,0x97,0x83,0xA7,0x84,0x4A,0x29,0x45, ++0x17,0x65,0x6E,0x00,0x13,0x05,0x05,0x48,0x82,0x97,0x83,0xA7,0x84,0x4B,0x97,0x55,0x6E,0x00,0x83,0xC5,0x05,0xCC,0x11,0x45,0x82,0x97,0x83,0xA7,0x84,0x4A,0x29,0x45, +0x82,0x97,0xE9,0xBD,0xB7,0x07,0xA0,0x00,0x83,0xA5,0x07,0x13,0x03,0xA5,0xC9,0x00,0x83,0xA7,0x04,0x58,0x9A,0x05,0x99,0x81,0x82,0x97,0xAA,0x85,0x17,0x65,0x6E,0x00, -+0x13,0x05,0x05,0x43,0xEF,0x40,0xA0,0x39,0x83,0xA7,0x84,0x57,0x89,0x49,0x82,0x97,0x83,0xA7,0x04,0x46,0x17,0x37,0x6E,0x00,0xA3,0x00,0x07,0xA6,0x35,0x45,0x17,0x37, ++0x13,0x05,0xC5,0x45,0xEF,0x40,0x80,0x3D,0x83,0xA7,0x84,0x57,0x89,0x49,0x82,0x97,0x83,0xA7,0x04,0x46,0x17,0x37,0x6E,0x00,0xA3,0x00,0x07,0xA6,0x35,0x45,0x17,0x37, +0x6E,0x00,0x23,0x0D,0x07,0xAC,0x82,0x97,0x83,0xA7,0x04,0x43,0x37,0x67,0xF0,0x00,0x23,0x24,0x07,0x20,0x01,0x45,0x82,0x97,0x97,0x37,0x6E,0x00,0x23,0xA6,0x07,0xAA, +0x83,0x27,0xC4,0x54,0x17,0x57,0x6E,0x00,0x03,0x47,0x57,0xC5,0x3E,0x99,0x91,0x67,0x3E,0x99,0x23,0x04,0x09,0x50,0xE3,0x00,0x37,0xE7,0x83,0x27,0x84,0x4C,0x03,0x27, +0x84,0x4C,0xA1,0x46,0x13,0x05,0x00,0x40,0x03,0x47,0x07,0x00,0x0D,0x8B,0x16,0x07,0x11,0x07,0xBA,0x97,0x23,0x82,0x07,0x00,0xA3,0x82,0x07,0x00,0x23,0x83,0x07,0x00, @@ -13297,8 +13106,8 @@ index 000000000000..b9661763dbcc +0xC7,0x69,0xBA,0x96,0x13,0x95,0x06,0x01,0x41,0x81,0xD1,0x45,0x63,0xF3,0xA5,0x02,0x93,0x87,0x57,0x68,0xBA,0x97,0xC2,0x07,0xC1,0x83,0x93,0x06,0x50,0x03,0x01,0x45, +0xE3,0xEB,0xF6,0xFC,0xB3,0x07,0xC7,0x40,0x85,0x87,0xA9,0x07,0x13,0xF5,0xF7,0x0F,0x82,0x80,0x93,0xD7,0x16,0x40,0x13,0xF5,0xF7,0x0F,0x82,0x80,0x41,0x11,0x06,0xC6, +0x22,0xC4,0x26,0xC2,0x83,0x44,0xA5,0x01,0x83,0x47,0xB5,0x01,0x03,0x47,0xD5,0x01,0x83,0x45,0xC5,0x01,0x93,0x96,0x84,0x01,0xC2,0x07,0xD5,0x8F,0xD9,0x8F,0xA2,0x05, -+0x2A,0x84,0xDD,0x8D,0x17,0x65,0x6E,0x00,0x13,0x05,0x45,0x11,0xEF,0x40,0x20,0x07,0x83,0x47,0xE4,0x01,0x03,0x47,0xF4,0x01,0x83,0x46,0x14,0x02,0x83,0x45,0x04,0x02, -+0x42,0x07,0xE2,0x07,0xD9,0x8F,0xD5,0x8F,0xA2,0x05,0xDD,0x8D,0x17,0x65,0x6E,0x00,0x13,0x05,0xC5,0x0E,0xEF,0x40,0xA0,0x04,0x85,0x47,0x63,0x86,0xF4,0x02,0x89,0x47, ++0x2A,0x84,0xDD,0x8D,0x17,0x65,0x6E,0x00,0x13,0x05,0x05,0x14,0xEF,0x40,0x00,0x0B,0x83,0x47,0xE4,0x01,0x03,0x47,0xF4,0x01,0x83,0x46,0x14,0x02,0x83,0x45,0x04,0x02, ++0x42,0x07,0xE2,0x07,0xD9,0x8F,0xD5,0x8F,0xA2,0x05,0xDD,0x8D,0x17,0x65,0x6E,0x00,0x13,0x05,0x85,0x11,0xEF,0x40,0x80,0x08,0x85,0x47,0x63,0x86,0xF4,0x02,0x89,0x47, +0x63,0x9E,0xF4,0x00,0x83,0x47,0xB4,0x01,0x17,0x57,0x6E,0x00,0xA3,0x04,0xF7,0x92,0x83,0x47,0xC4,0x01,0x17,0x57,0x6E,0x00,0x23,0x0F,0xF7,0x90,0xB2,0x40,0x22,0x44, +0x92,0x44,0x41,0x01,0x82,0x80,0x83,0x47,0xB4,0x01,0x63,0x8C,0x97,0x00,0x81,0x44,0xB2,0x40,0x22,0x44,0x97,0x57,0x6E,0x00,0xA3,0x8D,0x97,0x8E,0x92,0x44,0x41,0x01, +0x82,0x80,0x83,0x47,0xC4,0x01,0x17,0x57,0x6E,0x00,0x23,0x05,0xF7,0x8E,0xCD,0xB7,0x41,0x11,0x26,0xC2,0x06,0xC6,0x22,0xC4,0x03,0x47,0x55,0x00,0x83,0x46,0x45,0x00, @@ -13330,13 +13139,13 @@ index 000000000000..b9661763dbcc +0x64,0xEC,0x37,0x07,0xF0,0x00,0x85,0x07,0x23,0x20,0xF7,0x08,0x83,0x27,0x04,0x5B,0x01,0x45,0x82,0x97,0x03,0x23,0x44,0x54,0x22,0x44,0xB2,0x40,0x81,0x45,0x09,0x45, +0x41,0x01,0x02,0x83,0x17,0x07,0x6E,0x00,0x03,0x47,0xE7,0x29,0x89,0x47,0x63,0x04,0xF7,0x00,0x01,0x45,0x82,0x80,0x41,0x11,0x26,0xC2,0x97,0x64,0xFF,0xFF,0x93,0x84, +0x64,0xE8,0x83,0xA7,0x84,0x17,0x06,0xC6,0x22,0xC4,0x4A,0xC0,0x82,0x97,0x51,0xCD,0x17,0x09,0x6E,0x00,0x13,0x09,0x09,0xE7,0x83,0x47,0xC9,0x3B,0x29,0x47,0x63,0x76, -+0xF7,0x08,0xB7,0x27,0xF0,0x00,0xFC,0x4F,0x85,0x8B,0xC1,0xC3,0x97,0x47,0x6E,0x00,0x83,0xC7,0x77,0x52,0x17,0x65,0x6E,0x00,0x13,0x05,0x85,0xCF,0xAD,0xE7,0x97,0x47, ++0xF7,0x08,0xB7,0x27,0xF0,0x00,0xFC,0x4F,0x85,0x8B,0xC1,0xC3,0x97,0x47,0x6E,0x00,0x83,0xC7,0x77,0x52,0x17,0x65,0x6E,0x00,0x13,0x05,0x45,0xD2,0xAD,0xE7,0x97,0x47, +0x6E,0x00,0x83,0xC7,0x57,0x52,0x4A,0x84,0x91,0xC7,0x97,0x47,0x6E,0x00,0x83,0xC7,0xB7,0x51,0xA1,0xEF,0xB7,0x37,0xF0,0x00,0xFC,0x4F,0x17,0x65,0x6E,0x00,0x13,0x05, -+0x25,0xCE,0x85,0x8B,0xA9,0xE3,0xB7,0x57,0xA0,0x00,0x83,0xA7,0xC7,0xC0,0x13,0x97,0x97,0x00,0x63,0x5C,0x07,0x02,0x97,0x27,0x6E,0x00,0x93,0x87,0xA7,0xE0,0xB8,0x5F, ++0xE5,0xD0,0x85,0x8B,0xA9,0xE3,0xB7,0x57,0xA0,0x00,0x83,0xA7,0xC7,0xC0,0x13,0x97,0x97,0x00,0x63,0x5C,0x07,0x02,0x97,0x27,0x6E,0x00,0x93,0x87,0xA7,0xE0,0xB8,0x5F, +0xBC,0x5F,0x03,0x27,0x07,0x40,0x83,0xA7,0x47,0x40,0x63,0x10,0xF7,0x02,0x03,0x25,0x04,0x7D,0x83,0xA7,0x44,0x1A,0x13,0x05,0x85,0x03,0x82,0x97,0x11,0xED,0x17,0x65, -+0x6E,0x00,0x13,0x05,0xE5,0xCA,0xEF,0x30,0xB0,0x3C,0x01,0x45,0xB2,0x40,0x22,0x44,0x92,0x44,0x02,0x49,0x41,0x01,0x82,0x80,0xB7,0x07,0xA0,0x00,0x03,0xA7,0xC7,0x1F, ++0x6E,0x00,0x13,0x05,0xA5,0xCD,0xEF,0x30,0x90,0x40,0x01,0x45,0xB2,0x40,0x22,0x44,0x92,0x44,0x02,0x49,0x41,0x01,0x82,0x80,0xB7,0x07,0xA0,0x00,0x03,0xA7,0xC7,0x1F, +0x83,0xA6,0x07,0x20,0x83,0xA7,0x47,0x20,0xE3,0x11,0xD7,0xFE,0xE3,0x1F,0xF7,0xFC,0xB7,0x77,0xA0,0x00,0x83,0xA7,0x07,0x0A,0x03,0x27,0x04,0x7D,0x93,0xF7,0xF7,0x0F, -+0x78,0x4F,0x63,0x1B,0xF7,0x00,0x83,0x27,0x44,0x1E,0x63,0x47,0xF0,0x00,0x83,0x27,0x04,0x2D,0x05,0x45,0xE3,0x5C,0xF0,0xFA,0x17,0x65,0x6E,0x00,0x13,0x05,0x05,0xC6, ++0x78,0x4F,0x63,0x1B,0xF7,0x00,0x83,0x27,0x44,0x1E,0x63,0x47,0xF0,0x00,0x83,0x27,0x04,0x2D,0x05,0x45,0xE3,0x5C,0xF0,0xFA,0x17,0x65,0x6E,0x00,0x13,0x05,0xC5,0xC8, +0x5D,0xB7,0x41,0x11,0x22,0xC4,0x06,0xC6,0x26,0xC2,0x93,0x77,0x45,0x00,0x1D,0x44,0x99,0xE7,0x93,0x77,0x25,0x00,0x0D,0x44,0x99,0xE3,0x13,0x74,0x15,0x00,0x97,0x64, +0xFF,0xFF,0x93,0x84,0x24,0xD6,0x83,0xA7,0x84,0x33,0x22,0x85,0x82,0x97,0x83,0xA7,0x84,0x15,0x01,0x46,0xA2,0x85,0x05,0x45,0x82,0x97,0x83,0xA7,0x44,0x42,0x29,0x45, +0x82,0x97,0x93,0x77,0x24,0x00,0xAD,0xCB,0x97,0xE7,0x6D,0x00,0x23,0x8B,0x07,0xF8,0x97,0xE7,0x6D,0x00,0x23,0x81,0x07,0x1E,0x97,0xE7,0x6D,0x00,0x23,0x87,0x07,0x42, @@ -13350,23 +13159,23 @@ index 000000000000..b9661763dbcc +0xD2,0x4C,0x42,0x4D,0x21,0x61,0x82,0x80,0x13,0x9B,0x2B,0x00,0xDA,0x97,0x9C,0x43,0x63,0x9D,0x97,0x01,0x93,0x17,0x24,0x00,0xD2,0x97,0x9C,0x43,0xB3,0xF7,0x57,0x01, +0x23,0xA0,0xFC,0x00,0x85,0x0B,0x05,0x04,0x6D,0xBF,0x63,0x95,0x27,0x01,0x23,0x20,0x09,0x00,0xCD,0xBF,0x93,0x14,0x24,0x00,0x63,0x9D,0x37,0x01,0xB7,0x07,0x00,0xC1, +0x23,0xA0,0xF9,0x00,0x83,0x27,0x4C,0x42,0x15,0x45,0x82,0x97,0xB2,0x47,0xDA,0x97,0x9C,0x43,0xD2,0x94,0x98,0x40,0x98,0xC3,0xF1,0xB7,0xB7,0xD7,0xA0,0x00,0x83,0xA5, -+0xC7,0x0F,0x83,0xA7,0x87,0x0F,0x01,0x11,0xDA,0x05,0xA9,0x83,0xDD,0x8D,0x01,0x46,0x17,0x65,0x6E,0x00,0x13,0x05,0x45,0xAB,0x06,0xCE,0x22,0xCC,0x4A,0xC8,0x17,0x64, -+0xFF,0xFF,0x13,0x04,0x24,0xBC,0x4E,0xC6,0x26,0xCA,0xEF,0x30,0x50,0x1B,0x83,0x27,0xC4,0x1C,0x17,0x09,0x6E,0x00,0x13,0x09,0xE9,0xBA,0x82,0x97,0x83,0x27,0x04,0x32, ++0xC7,0x0F,0x83,0xA7,0x87,0x0F,0x01,0x11,0xDA,0x05,0xA9,0x83,0xDD,0x8D,0x01,0x46,0x17,0x65,0x6E,0x00,0x13,0x05,0x05,0xAE,0x06,0xCE,0x22,0xCC,0x4A,0xC8,0x17,0x64, ++0xFF,0xFF,0x13,0x04,0x24,0xBC,0x4E,0xC6,0x26,0xCA,0xEF,0x30,0x30,0x1F,0x83,0x27,0xC4,0x1C,0x17,0x09,0x6E,0x00,0x13,0x09,0xE9,0xBA,0x82,0x97,0x83,0x27,0x04,0x32, +0x82,0x97,0x83,0x27,0x44,0x11,0x82,0x97,0x37,0x07,0xF0,0x00,0x3C,0x5F,0x93,0xE7,0x17,0x00,0x3C,0xDF,0xB7,0x27,0xF0,0x00,0x83,0xA9,0xC7,0x05,0x83,0x27,0x04,0x36, +0x82,0x97,0x5D,0xC9,0x93,0xF9,0x19,0x00,0x63,0x88,0x09,0x0A,0x83,0x47,0x29,0x40,0x09,0x47,0x63,0x13,0xF7,0x0A,0x83,0x27,0x84,0x60,0xAA,0x84,0x79,0x45,0x82,0x97, -+0x83,0x27,0xC4,0x37,0x26,0x85,0x82,0x97,0x97,0x07,0x6E,0x00,0xA3,0x8F,0xA7,0xF4,0x83,0x45,0x79,0x40,0x17,0x65,0x6E,0x00,0x13,0x05,0x85,0xA3,0xF2,0x05,0xC5,0x8D, -+0xEF,0x30,0xF0,0x13,0x93,0x05,0x80,0x3E,0xB3,0x84,0xB4,0x02,0x9D,0x65,0x93,0x85,0x55,0x73,0x03,0x45,0x79,0x40,0x83,0x27,0xC4,0x35,0xB3,0xD5,0xB4,0x02,0x82,0x97, -+0xB7,0xD7,0xA0,0x00,0x83,0xA5,0xC7,0x0F,0x83,0xA7,0x87,0x0F,0x01,0x46,0xDA,0x05,0xA9,0x83,0xDD,0x8D,0x17,0x65,0x6E,0x00,0x13,0x05,0x45,0xA1,0xEF,0x30,0x30,0x10, ++0x83,0x27,0xC4,0x37,0x26,0x85,0x82,0x97,0x97,0x07,0x6E,0x00,0xA3,0x8F,0xA7,0xF4,0x83,0x45,0x79,0x40,0x17,0x65,0x6E,0x00,0x13,0x05,0x45,0xA6,0xF2,0x05,0xC5,0x8D, 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index 000000000000..b9661763dbcc +0xB7,0x36,0xF0,0xFF,0x93,0x86,0xC6,0x75,0x75,0x8F,0xB7,0xC6,0x0B,0x00,0x93,0x86,0x26,0x08,0x55,0x8F,0x98,0xDB,0xD8,0x5B,0xB7,0x06,0x00,0x80,0x55,0x8F,0xD8,0xDB, +0x13,0x07,0x00,0x02,0x98,0xD3,0x82,0x80,0xB7,0x26,0xF0,0x00,0x98,0x5A,0xFD,0x77,0x93,0x87,0xF7,0x71,0x05,0x66,0xF9,0x8F,0x13,0x06,0x06,0x82,0xD1,0x8F,0xC2,0x07, +0x41,0x76,0x71,0x8F,0xC1,0x83,0xD9,0x8F,0x9C,0xDA,0xDC,0x5A,0x37,0x07,0x00,0x80,0xD9,0x8F,0xDC,0xDA,0x82,0x80,0x41,0x11,0x22,0xC4,0x17,0x44,0x6E,0x00,0x13,0x04, -+0x64,0xDF,0x13,0x06,0x80,0x11,0x81,0x45,0x22,0x85,0x06,0xC6,0xEF,0x40,0x4E,0xDA,0x89,0x47,0x25,0x45,0x23,0x08,0xF4,0x00,0xEF,0x10,0x0E,0xA6,0x3D,0x81,0x05,0x89, ++0x64,0xDF,0x13,0x06,0x00,0x13,0x81,0x45,0x22,0x85,0x06,0xC6,0xEF,0x40,0x4E,0xDA,0x89,0x47,0x25,0x45,0x23,0x08,0xF4,0x00,0xEF,0x10,0x0E,0xA6,0x3D,0x81,0x05,0x89, +0x23,0x0F,0xA4,0x00,0xB2,0x40,0x22,0x44,0x41,0x01,0x82,0x80,0xB7,0x27,0xF0,0x00,0xBC,0x43,0x41,0x11,0x22,0xC4,0x26,0xC2,0x06,0xC6,0x85,0x8B,0x17,0x54,0xFF,0xFF, +0x13,0x04,0x44,0x6E,0x85,0x44,0xE5,0xE7,0x83,0x27,0x44,0x1B,0x82,0x97,0x65,0x37,0x83,0x27,0x44,0x4A,0x82,0x97,0x83,0x27,0xC4,0x59,0x11,0x45,0x82,0x97,0x83,0x27, +0x84,0x3F,0x82,0x97,0x83,0x27,0x04,0x45,0x82,0x97,0x83,0x27,0xC4,0x43,0x82,0x97,0xB7,0x77,0xA0,0x00,0x23,0xA0,0x07,0x08,0x83,0x27,0x44,0x3E,0x82,0x97,0x83,0x27, +0x84,0x29,0x82,0x97,0x83,0x27,0xC4,0x4D,0x82,0x97,0x1C,0x58,0x82,0x97,0x83,0x27,0x04,0x25,0x82,0x97,0x83,0x27,0x84,0x08,0x82,0x97,0x83,0x27,0x04,0x49,0x82,0x97, -+0x83,0x27,0xC4,0x49,0x82,0x97,0x83,0x27,0x44,0x1E,0x82,0x97,0x83,0x27,0x84,0x11,0x82,0x97,0x83,0x27,0x04,0x57,0x82,0x97,0xEF,0x40,0x10,0x6D,0x83,0x27,0x04,0x40, ++0x83,0x27,0xC4,0x49,0x82,0x97,0x83,0x27,0x44,0x1E,0x82,0x97,0x83,0x27,0x84,0x11,0x82,0x97,0x83,0x27,0x04,0x57,0x82,0x97,0xEF,0x40,0x90,0x73,0x83,0x27,0x04,0x40, +0x82,0x97,0x83,0x27,0x44,0x49,0x82,0x97,0x83,0x27,0x84,0x75,0x82,0x97,0x83,0x27,0x04,0x41,0x82,0x97,0xB7,0x07,0xA0,0x00,0x37,0x07,0x00,0x70,0x23,0xA8,0xE7,0x1A, +0x37,0x07,0x10,0x07,0x23,0xA8,0xE7,0x1A,0x25,0x47,0xB7,0x07,0xF0,0x00,0xF8,0xCB,0x83,0x27,0xC4,0x45,0xB7,0x95,0x98,0x00,0x93,0x85,0x05,0x68,0x09,0x45,0x82,0x97, -+0xEF,0xF0,0x2F,0xF4,0xEF,0x40,0xD0,0x16,0x83,0x27,0x44,0x18,0x82,0x97,0x97,0xF7,0x6D,0x00,0x93,0x87,0x27,0x61,0x03,0xA7,0x07,0x7D,0x85,0x47,0x1C,0xC7,0x37,0x07, ++0xEF,0xF0,0x2F,0xF4,0xEF,0x40,0x50,0x1D,0x83,0x27,0x44,0x18,0x82,0x97,0x97,0xF7,0x6D,0x00,0x93,0x87,0x27,0x61,0x03,0xA7,0x07,0x7D,0x85,0x47,0x1C,0xC7,0x37,0x07, +0xA1,0x00,0x1C,0xC7,0x1D,0xA8,0x83,0x27,0x44,0x42,0x15,0x45,0x82,0x97,0x83,0x27,0xC4,0x36,0x82,0x97,0xE3,0x19,0x95,0xFE,0x83,0x27,0x84,0x36,0x17,0x05,0x6E,0x00, +0x03,0x45,0xB5,0x9E,0x82,0x97,0x83,0x27,0x44,0x32,0x82,0x97,0x83,0x27,0xC4,0x59,0x11,0x45,0x82,0x97,0x83,0x27,0x44,0x1E,0x82,0x97,0x37,0x07,0xF0,0x00,0x3C,0x5F, +0xF9,0x9B,0x3C,0xDF,0x83,0x27,0x44,0x53,0x82,0x97,0xB2,0x40,0x22,0x44,0x92,0x44,0x01,0x45,0x41,0x01,0x82,0x80,0x41,0x11,0xB7,0x17,0x10,0x10,0x93,0x87,0x07,0x80, @@ -13440,15 +13249,15 @@ index 000000000000..b9661763dbcc +0x3A,0x95,0x0A,0x05,0x14,0xC1,0x23,0x2A,0xF5,0xE6,0xB7,0x07,0xA0,0x00,0x83,0xA7,0x07,0x13,0x9A,0x07,0x99,0x83,0x23,0x28,0xF8,0x24,0x41,0x01,0x82,0x80,0x01,0x11, +0x52,0xC4,0x37,0x0A,0xA0,0x00,0x22,0xCC,0x03,0x24,0xCA,0x00,0x26,0xCA,0x06,0xCE,0x06,0x04,0x05,0x80,0x4A,0xC8,0x4E,0xC6,0x56,0xC2,0x5A,0xC0,0x23,0x26,0x8A,0x00, +0x93,0x74,0x24,0x00,0x63,0x80,0x04,0x10,0x93,0x59,0x44,0x00,0x13,0x59,0x44,0x01,0x93,0x77,0x04,0x10,0x93,0xF9,0xF9,0x00,0x13,0x79,0xF9,0x03,0x63,0x83,0x07,0x28, -+0x83,0x25,0x0A,0x01,0x17,0x55,0x6E,0x00,0x13,0x05,0x85,0xFB,0x0A,0x09,0xEF,0x20,0x10,0x69,0x83,0x27,0x0A,0x1E,0x93,0x95,0x09,0x01,0xB3,0x65,0xB9,0x00,0xE2,0x07, -+0xDD,0x8D,0x17,0x55,0x6E,0x00,0x13,0x05,0x65,0xFA,0xEF,0x20,0x50,0x67,0x97,0x57,0xFF,0xFF,0x93,0x87,0x27,0x07,0xBC,0x47,0xCA,0x85,0x4E,0x85,0x82,0x97,0x93,0x77, ++0x83,0x25,0x0A,0x01,0x17,0x55,0x6E,0x00,0x13,0x05,0x45,0xFE,0x0A,0x09,0xEF,0x20,0xF0,0x6C,0x83,0x27,0x0A,0x1E,0x93,0x95,0x09,0x01,0xB3,0x65,0xB9,0x00,0xE2,0x07, ++0xDD,0x8D,0x17,0x55,0x6E,0x00,0x13,0x05,0x25,0xFD,0xEF,0x20,0x30,0x6B,0x97,0x57,0xFF,0xFF,0x93,0x87,0x27,0x07,0xBC,0x47,0xCA,0x85,0x4E,0x85,0x82,0x97,0x93,0x77, +0x04,0x40,0x99,0xCB,0xB7,0x07,0xA0,0x00,0x88,0x4B,0x97,0x57,0xFF,0xFF,0x93,0x87,0x67,0x05,0x83,0xA7,0xC7,0x11,0x82,0x97,0xD1,0xC4,0xB7,0x07,0xA0,0x00,0x83,0xA4, +0x07,0x25,0x23,0xA8,0x97,0x24,0x93,0x77,0x04,0x10,0xAD,0xEF,0x17,0x59,0xFF,0xFF,0x13,0x09,0x49,0x03,0xB5,0xC0,0x93,0xF7,0x14,0x00,0x89,0xC7,0x83,0x27,0x49,0x04, +0x01,0x45,0x82,0x97,0x93,0xF7,0x24,0x00,0x89,0xC7,0x83,0x27,0x49,0x04,0x05,0x45,0x82,0x97,0x93,0xF7,0x44,0x00,0x89,0xC7,0x83,0x27,0x49,0x04,0x09,0x45,0x82,0x97, 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+0x85,0x00,0x13,0xF6,0xF5,0x0F,0x93,0xF7,0xC7,0x0F,0x97,0x59,0xFF,0xFF,0x93,0x89,0x69,0xF5,0x63,0x5A,0x07,0x42,0x13,0xF7,0xF7,0x00,0x91,0x46,0x63,0x18,0xD7,0x00, +0x03,0xA7,0xC9,0x04,0xE1,0x81,0x13,0xF5,0x07,0x0F,0x02,0x97,0xB7,0x07,0xA0,0x00,0x17,0x39,0x6E,0x00,0x13,0x09,0x09,0x60,0x83,0xA7,0xC7,0x1F,0x03,0x25,0xC9,0x00, @@ -13479,614 +13288,639 @@ index 000000000000..b9661763dbcc +0xF5,0x02,0x89,0x67,0x93,0x87,0x47,0x0B,0x3E,0x95,0x83,0x27,0xC9,0x39,0x56,0x95,0x82,0x97,0x0D,0xE1,0x83,0x27,0xC9,0x39,0x83,0xA5,0x49,0x00,0x17,0x15,0x6E,0x00, +0x13,0x05,0x05,0xC9,0x82,0x97,0x19,0xE5,0x83,0x27,0x49,0x39,0x83,0xA5,0x49,0x00,0x5A,0x85,0x82,0x97,0x83,0xD7,0x89,0x23,0xF5,0x9B,0x23,0x9C,0xF9,0x22,0xC1,0xBD, +0x17,0xF7,0x6D,0x00,0x03,0x47,0xC7,0xF9,0xA9,0x47,0x17,0xD9,0x6D,0x00,0x13,0x09,0x69,0xBD,0x17,0xFA,0x6D,0x00,0x13,0x0A,0xEA,0xBC,0x63,0xED,0xE7,0x02,0x83,0x47, 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++0x4A,0xC0,0xAA,0x84,0x82,0x97,0x2A,0x89,0x26,0x85,0xEF,0x00,0x3F,0xCA,0x83,0x27,0xC4,0x2E,0xAA,0x84,0x4A,0x85,0x82,0x97,0xB2,0x40,0x22,0x44,0x26,0x85,0x02,0x49, ++0x92,0x44,0x41,0x01,0x82,0x80,0x01,0x11,0x22,0xCC,0x17,0x04,0xFF,0xFF,0x13,0x04,0x64,0x35,0x83,0x27,0x04,0x2F,0x06,0xCE,0x26,0xCA,0x4A,0xC8,0x2E,0xC6,0x2A,0x89, ++0x82,0x97,0xB2,0x45,0xAA,0x84,0x4A,0x85,0xEF,0x00,0x5F,0xC9,0x03,0x23,0xC4,0x2E,0x62,0x44,0xF2,0x40,0x42,0x49,0x26,0x85,0xD2,0x44,0x05,0x61,0x02,0x83,0x97,0x07, ++0x6E,0x00,0x93,0x87,0x67,0x0F,0x37,0xE7,0xB3,0x00,0x98,0xC3,0x37,0xF7,0xB3,0x00,0xD8,0xC3,0x82,0x80,0x41,0x11,0x06,0xC6,0x22,0xC4,0x97,0xC7,0x6D,0x00,0x93,0x87, ++0xA7,0xF6,0x17,0xC4,0x6D,0x00,0x13,0x04,0xE4,0x2F,0x3C,0xDC,0x28,0x5C,0x13,0x06,0x40,0x41,0x81,0x45,0xEF,0xF0,0xCD,0x97,0x38,0x5C,0x3C,0x5C,0xB7,0x06,0xF8,0xFF, ++0xFD,0x16,0x23,0xA0,0xE7,0x40,0x38,0x5C,0x3C,0x5C,0x23,0xA2,0xE7,0x40,0x38,0x5C,0xF1,0x67,0x93,0x87,0x07,0x20,0x23,0x26,0xF7,0x40,0x3C,0x5C,0x17,0xE7,0xFE,0xFF, ++0x13,0x07,0x87,0x8B,0x23,0xA8,0xE7,0x40,0xB7,0x57,0xA0,0x00,0x03,0xA7,0x87,0xC0,0x75,0x8F,0x23,0xA4,0xE7,0xC0,0x38,0x5C,0x03,0x27,0xC7,0x40,0x93,0x16,0x27,0x00, ++0x37,0xB7,0xC4,0x04,0x13,0x07,0x07,0x40,0x33,0x57,0xD7,0x02,0x85,0x66,0x23,0xA4,0xE7,0xC0,0x03,0xA7,0x87,0xC0,0x55,0x8F,0x23,0xA4,0xE7,0xC0,0x03,0xA7,0x87,0xC0, ++0xB7,0x06,0xC0,0x01,0x55,0x8F,0x23,0xA4,0xE7,0xC0,0x03,0xA7,0x87,0xC0,0xB7,0x06,0x40,0xFE,0xFD,0x16,0x75,0x8F,0x23,0xA4,0xE7,0xC0,0x38,0x5C,0x17,0x04,0xFF,0xFF, ++0x13,0x04,0x44,0x26,0x83,0x27,0xC4,0x4B,0x03,0x25,0x07,0x41,0x82,0x97,0x83,0x27,0x44,0x54,0x81,0x45,0x01,0x45,0x82,0x97,0x22,0x44,0xB2,0x40,0x41,0x01,0x05,0xB7, ++0x97,0xC6,0x6D,0x00,0x93,0x86,0x06,0x24,0x03,0xA7,0x86,0x4C,0x83,0xA7,0x86,0x4C,0x13,0x05,0x00,0x40,0x83,0xC7,0x07,0x00,0x8D,0x8B,0x96,0x07,0x91,0x07,0xBA,0x97, ++0x1D,0x47,0x23,0x80,0xE7,0x00,0x11,0x47,0xA3,0x80,0x07,0x00,0xA3,0x81,0x07,0x00,0x23,0x81,0xE7,0x00,0x03,0xA7,0x86,0x4C,0x83,0x47,0x07,0x00,0x85,0x07,0x23,0x00, ++0xF7,0x00,0x97,0x07,0xFF,0xFF,0x93,0x87,0xE7,0x1F,0x03,0xA3,0xC7,0x18,0x02,0x83,0x41,0x11,0x22,0xC4,0x17,0xC4,0x6D,0x00,0x13,0x04,0xC4,0x1E,0x38,0x5C,0x3C,0x5C, ++0x06,0xC6,0x03,0x27,0x07,0x40,0x83,0xA7,0x47,0x40,0x63,0x06,0xF7,0x02,0x97,0xF7,0x6D,0x00,0x83,0xC7,0x57,0x8B,0xBD,0xEF,0xB7,0x57,0xA0,0x00,0x83,0xA7,0xC7,0xC0, ++0x37,0x56,0xA0,0x00,0xA1,0x83,0x13,0xF7,0xF7,0x0F,0x93,0x07,0x00,0x08,0x99,0x8F,0x3D,0x47,0x63,0x6E,0xF7,0x02,0xB2,0x40,0x22,0x44,0x41,0x01,0x82,0x80,0x34,0x5C, ++0x03,0xA7,0x06,0x40,0x93,0x05,0x17,0x00,0x23,0xA0,0xB6,0x40,0x03,0x47,0x07,0x00,0x23,0x20,0xE6,0xC0,0x34,0x5C,0x38,0x5C,0x83,0xA6,0x06,0x40,0x13,0x07,0x07,0x40, ++0x63,0x96,0xE6,0x00,0x34,0x5C,0x38,0x5C,0x23,0x20,0xD7,0x40,0xFD,0x17,0x34,0x5C,0x38,0x5C,0x83,0xA6,0x06,0x40,0x03,0x27,0x47,0x40,0x63,0x83,0xE6,0x00,0xE1,0xF3, ++0x37,0x57,0xA0,0x00,0x83,0x27,0x87,0xC0,0xB7,0x06,0x00,0x10,0xD5,0x8F,0x23,0x24,0xF7,0xC0,0x55,0xB7,0x17,0xF7,0x6D,0x00,0x03,0x47,0x27,0x83,0x85,0x47,0x63,0x1F, ++0xF7,0x04,0x97,0xF7,0x6D,0x00,0x83,0xC7,0x37,0x82,0xB1,0xE3,0x38,0x5C,0x97,0x07,0x6E,0x00,0x93,0x87,0x67,0xF0,0xDC,0x43,0x03,0x27,0x07,0x40,0x93,0x87,0x07,0x80, ++0x63,0x77,0xF7,0x00,0x38,0x5C,0x03,0x27,0x47,0x40,0x63,0x7C,0xF7,0x00,0x38,0x5C,0x03,0x27,0x07,0x40,0x63,0x6D,0xF7,0x00,0x38,0x5C,0x03,0x27,0x47,0x40,0x63,0x78, ++0xF7,0x00,0x7D,0x3D,0x85,0x47,0x17,0xE7,0x6D,0x00,0xA3,0x0F,0xF7,0x7C,0x38,0x5C,0x3C,0x5C,0x03,0x27,0x47,0x40,0x23,0xA0,0xE7,0x40,0x35,0xBF,0x3C,0x5C,0x03,0xA7, ++0x47,0x40,0x97,0x07,0x6E,0x00,0x93,0x87,0x27,0xEB,0xD4,0x43,0x15,0x07,0x63,0xFC,0xE6,0x00,0x38,0x5C,0x03,0x27,0x47,0x40,0xD4,0x43,0x63,0x61,0xD7,0x02,0x38,0x5C, ++0x9C,0x43,0x23,0x22,0xF7,0x40,0x3C,0x5C,0x15,0x46,0x97,0x05,0x6E,0x00,0x93,0x85,0x25,0xE9,0x03,0xA5,0x47,0x40,0xEF,0xE0,0xFD,0xF1,0x55,0xBF,0x23,0x00,0x07,0x00, ++0x05,0x07,0xD9,0xBF,0x17,0xC7,0x6D,0x00,0x13,0x07,0xC7,0x09,0x3C,0x5F,0x97,0xE6,0x6D,0x00,0x83,0xC6,0x56,0x77,0x13,0xF6,0xF6,0xF7,0x83,0xA7,0x47,0x40,0x85,0x07, ++0x0D,0xE6,0x34,0x5F,0x93,0x86,0x06,0x40,0x63,0x93,0xD7,0x00,0x3C,0x5F,0x34,0x5F,0x83,0xA6,0x06,0x40,0x63,0x8A,0xF6,0x00,0x34,0x5F,0x83,0xA6,0x46,0x40,0x23,0x80, ++0xA6,0x00,0x38,0x5F,0x23,0x22,0xF7,0x40,0x82,0x80,0xE2,0x06,0xE1,0x86,0xE3,0xCD,0x06,0xFE,0x97,0x06,0x6E,0x00,0x93,0x86,0x26,0xE2,0xD0,0x42,0xE3,0x19,0xF6,0xFC, ++0x9C,0x42,0xF1,0xB7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++}; ++static unsigned char fwDCCM[] = { ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -+}; -+static unsigned char fwDCCM[] = { +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -14510,161 +14344,136 @@ index 000000000000..b9661763dbcc +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 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++0xAF,0xFF,0x13,0x07,0x27,0x3C,0x83,0x26,0x87,0x4C,0xAA,0x87,0x05,0x46,0x03,0xC8,0x06,0x02,0xBA,0x86,0x13,0x45,0xF8,0xFF,0x3E,0x95,0x13,0x75,0xF5,0x0F,0x23,0x80, ++0xA5,0x00,0x63,0x7E,0xA6,0x00,0xFD,0x17,0x93,0xF7,0xF7,0x0F,0x01,0x47,0x8D,0x48,0x63,0x98,0x07,0x01,0x85,0x47,0x63,0xF4,0xE7,0x00,0x13,0x05,0xF0,0x0F,0x82,0x80, ++0x03,0xA6,0x86,0x4C,0x93,0xF5,0x37,0x00,0x96,0x05,0x2E,0x96,0x03,0x46,0x46,0x00,0x63,0x15,0x16,0x01,0x05,0x07,0x13,0x77,0xF7,0x0F,0xFD,0x17,0x93,0xF7,0xF7,0x0F, ++0xC1,0xBF,0x79,0x71,0x06,0xD6,0x22,0xD4,0x26,0xD2,0x4A,0xD0,0x4E,0xCE,0xA3,0x07,0x01,0x00,0x97,0x97,0xAF,0xFF,0x83,0xC7,0xF7,0x74,0xB1,0xCF,0x17,0xC7,0xAF,0xFF, ++0x03,0x47,0xA7,0xB8,0x85,0x47,0x63,0x08,0xF7,0x04,0x97,0xB4,0xAF,0xFF,0x93,0x84,0x64,0x33,0x83,0xA7,0x84,0x4C,0xAA,0x89,0x93,0x05,0xF1,0x00,0x03,0xC5,0x07,0x00, ++0x17,0xF4,0x40,0xFF,0x13,0x04,0x04,0x32,0x99,0x3F,0x93,0x07,0xF0,0x0F,0x2A,0x89,0x63,0x1A,0xF5,0x02,0x83,0x27,0xC4,0x4B,0x17,0xF5,0xAF,0xFF,0x13,0x05,0x05,0x45, ++0x82,0x97,0x83,0x27,0x84,0x4B,0x83,0x45,0xF1,0x00,0x11,0x45,0x82,0x97,0x83,0x27,0x84,0x4A,0x29,0x45,0x82,0x97,0xB2,0x50,0x22,0x54,0x92,0x54,0x02,0x59,0xF2,0x49, ++0x45,0x61,0x82,0x80,0x89,0x47,0x63,0xF9,0xA7,0x02,0x83,0x27,0xC4,0x4B,0x17,0xF5,0xAF,0xFF,0x13,0x05,0x65,0x42,0x42,0x09,0x82,0x97,0x83,0xA7,0x84,0x4C,0x11,0x45, ++0x83,0xC5,0x07,0x00,0x83,0x27,0x84,0x4B,0xE2,0x05,0xB3,0xE5,0x25,0x01,0x82,0x97,0x83,0x27,0x84,0x4A,0x29,0x45,0x82,0x97,0x83,0xA7,0x84,0x4C,0x03,0xA7,0x84,0x4C, ++0x13,0x05,0x00,0x40,0x03,0x47,0x07,0x00,0x0D,0x8B,0x16,0x07,0xBA,0x97,0x0D,0x47,0x23,0x82,0xE7,0x00,0x03,0xA7,0x84,0x4C,0xA3,0x82,0x37,0x01,0x23,0x83,0x07,0x00, ++0x83,0x47,0x07,0x00,0x85,0x07,0x23,0x00,0xF7,0x00,0x83,0x27,0xC4,0x18,0x82,0x97,0x59,0xB7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -15628,7 +15437,7 @@ index 000000000000..b9661763dbcc + #endif //#define _F_BUF_H_ diff --git a/drivers/net/wireless/w1/common/patch_fi_cmd.h b/drivers/net/wireless/w1/common/patch_fi_cmd.h new file mode 100644 -index 000000000000..ee6a5369039d +index 0000000000000000000000000000000000000000..ee6a5369039d2c5b135bae3558459670eb151ba3 --- /dev/null +++ b/drivers/net/wireless/w1/common/patch_fi_cmd.h @@ -0,0 +1,159 @@ @@ -15793,12262 +15602,12262 @@ index 000000000000..ee6a5369039d +#endif diff --git a/drivers/net/wireless/w1/common/rf_d_adda_core_reg.h b/drivers/net/wireless/w1/common/rf_d_adda_core_reg.h new file mode 100644 -index 000000000000..0d7106c3b6dc +index 0000000000000000000000000000000000000000..6a0e2cc9129e01754ef1f8d68bc80e166e97e77f --- /dev/null +++ b/drivers/net/wireless/w1/common/rf_d_adda_core_reg.h @@ -0,0 +1,164 @@ -+#ifdef RF_D_ADDA_CORE_REG ++#ifdef RF_D_ADDA_CORE_REG ++#else ++#define RF_D_ADDA_CORE_REG ++ ++ ++#define RF_D_ADDA_CORE_REG_BASE (0xa0e000) ++ ++#define RG_CORE_A0 (RF_D_ADDA_CORE_REG_BASE + 0x0) ++// Bit 31 :0 rg_core_cfg0 U RW default = 'h0 ++typedef union RG_CORE_A0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_core_cfg0 : 32; ++ } b; ++} RG_CORE_A0_FIELD_T; ++ ++#define RG_CORE_A1 (RF_D_ADDA_CORE_REG_BASE + 0x4) ++// Bit 31 :0 rg_core_cfg1 U RW default = 'h0 ++typedef union RG_CORE_A1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_core_cfg1 : 32; ++ } b; ++} RG_CORE_A1_FIELD_T; ++ ++#define RG_CORE_A2 (RF_D_ADDA_CORE_REG_BASE + 0x8) ++// Bit 0 rg_core_enb_man U RW default = 'h0 ++// Bit 4 rg_core_enb_man_en U RW default = 'h0 ++// Bit 8 rg_xmit_enb_man U RW default = 'h0 ++// Bit 12 rg_xmit_enb_man_en U RW default = 'h0 ++// Bit 16 rg_recv_enb_man U RW default = 'h0 ++// Bit 20 rg_recv_enb_man_en U RW default = 'h0 ++// Bit 24 rg_esti_enb_man U RW default = 'h0 ++// Bit 28 rg_esti_enb_man_en U RW default = 'h0 ++typedef union RG_CORE_A2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_core_enb_man : 1; ++ unsigned int rsvd_0 : 3; ++ unsigned int rg_core_enb_man_en : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int rg_xmit_enb_man : 1; ++ unsigned int rsvd_2 : 3; ++ unsigned int rg_xmit_enb_man_en : 1; ++ unsigned int rsvd_3 : 3; ++ unsigned int rg_recv_enb_man : 1; ++ unsigned int rsvd_4 : 3; ++ unsigned int rg_recv_enb_man_en : 1; ++ unsigned int rsvd_5 : 3; ++ unsigned int rg_esti_enb_man : 1; ++ unsigned int rsvd_6 : 3; ++ unsigned int rg_esti_enb_man_en : 1; ++ unsigned int rsvd_7 : 3; ++ } b; ++} RG_CORE_A2_FIELD_T; ++ ++#define RG_CORE_A3 (RF_D_ADDA_CORE_REG_BASE + 0xc) ++// Bit 12 :0 rg_freq_mhz_man U RW default = 'h0 ++// Bit 15 rg_freq_mhz_man_en U RW default = 'h0 ++// Bit 24 rg_2g_5g_man U RW default = 'h0 ++// Bit 31 rg_2g_5g_man_en U RW default = 'h0 ++typedef union RG_CORE_A3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_freq_mhz_man : 13; ++ unsigned int rsvd_0 : 2; ++ unsigned int rg_freq_mhz_man_en : 1; ++ unsigned int rsvd_1 : 8; ++ unsigned int rg_2g_5g_man : 1; ++ unsigned int rsvd_2 : 6; ++ unsigned int rg_2g_5g_man_en : 1; ++ } b; ++} RG_CORE_A3_FIELD_T; ++ ++#define RG_CORE_A4 (RF_D_ADDA_CORE_REG_BASE + 0x10) ++// Bit 3 :0 rg_tx_pwrlvl_man U RW default = 'h0 ++// Bit 8 rg_tx_pwrlvl_man_en U RW default = 'h0 ++// Bit 17 :16 rg_tx_bw_man U RW default = 'h0 ++// Bit 20 rg_tx_bw_man_en U RW default = 'h0 ++// Bit 25 :24 rg_dac_fs_man U RW default = 'h0 ++// Bit 28 rg_dac_fs_man_en U RW default = 'h0 ++typedef union RG_CORE_A4_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_pwrlvl_man : 4; ++ unsigned int rsvd_0 : 4; ++ unsigned int rg_tx_pwrlvl_man_en : 1; ++ unsigned int rsvd_1 : 7; ++ unsigned int rg_tx_bw_man : 2; ++ unsigned int rsvd_2 : 2; ++ unsigned int rg_tx_bw_man_en : 1; ++ unsigned int rsvd_3 : 3; ++ unsigned int rg_dac_fs_man : 2; ++ unsigned int rsvd_4 : 2; ++ unsigned int rg_dac_fs_man_en : 1; ++ unsigned int rsvd_5 : 3; ++ } b; ++} RG_CORE_A4_FIELD_T; ++ ++#define RG_CORE_A5 (RF_D_ADDA_CORE_REG_BASE + 0x14) ++// Bit 7 :0 rg_rx_gain_man U RW default = 'h0 ++// Bit 8 rg_rx_gain_man_en U RW default = 'h0 ++// Bit 17 :16 rg_rx_bw_man U RW default = 'h0 ++// Bit 20 rg_rx_bw_man_en U RW default = 'h0 ++// Bit 25 :24 rg_adc_fs_man U RW default = 'h0 ++// Bit 28 rg_adc_fs_man_en U RW default = 'h0 ++typedef union RG_CORE_A5_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_rx_gain_man : 8; ++ unsigned int rg_rx_gain_man_en : 1; ++ unsigned int rsvd_0 : 7; ++ unsigned int rg_rx_bw_man : 2; ++ unsigned int rsvd_1 : 2; ++ unsigned int rg_rx_bw_man_en : 1; ++ unsigned int rsvd_2 : 3; ++ unsigned int rg_adc_fs_man : 2; ++ unsigned int rsvd_3 : 2; ++ unsigned int rg_adc_fs_man_en : 1; ++ unsigned int rsvd_4 : 3; ++ } b; ++} RG_CORE_A5_FIELD_T; ++ ++#define RG_CORE_A6 (RF_D_ADDA_CORE_REG_BASE + 0x18) ++// Bit 1 :0 rg_rf_mode_man U RW default = 'h0 ++// Bit 4 rg_rf_mode_man_en U RW default = 'h0 ++// Bit 11 :8 rg_cali_mode_man U RW default = 'h0 ++// Bit 16 rg_cali_mode_man_en U RW default = 'h0 ++// Bit 20 rg_tx_rx_man_en U RW default = 'h0 ++// Bit 24 rg_tx_rx_man U RW default = 'h0 ++typedef union RG_CORE_A6_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_rf_mode_man : 2; ++ unsigned int rsvd_0 : 2; ++ unsigned int rg_rf_mode_man_en : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int rg_cali_mode_man : 4; ++ unsigned int rsvd_2 : 4; ++ unsigned int rg_cali_mode_man_en : 1; ++ unsigned int rsvd_3 : 3; ++ unsigned int rg_tx_rx_man_en : 1; ++ unsigned int rsvd_4 : 3; ++ unsigned int rg_tx_rx_man : 1; ++ unsigned int rsvd_5 : 7; ++ } b; ++} RG_CORE_A6_FIELD_T; ++ ++#endif ++ +diff --git a/drivers/net/wireless/w1/common/rf_d_adda_esti_reg.h b/drivers/net/wireless/w1/common/rf_d_adda_esti_reg.h +new file mode 100644 +index 0000000000000000000000000000000000000000..e316994226fa5aa6a6542bbe0335b839f0a7225c +--- /dev/null ++++ b/drivers/net/wireless/w1/common/rf_d_adda_esti_reg.h +@@ -0,0 +1,1390 @@ ++#ifdef RF_D_ADDA_ESTI_REG ++#else ++#define RF_D_ADDA_ESTI_REG ++ ++ ++#define RF_D_ADDA_ESTI_REG_BASE (0xa0ec00) ++ ++#define RG_ESTI_A0 (RF_D_ADDA_ESTI_REG_BASE + 0x0) ++// Bit 31 :0 rg_esti_cfg0 U RW default = 'h0 ++typedef union RG_ESTI_A0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_esti_cfg0 : 32; ++ } b; ++} RG_ESTI_A0_FIELD_T; ++ ++#define RG_ESTI_A1 (RF_D_ADDA_ESTI_REG_BASE + 0x4) ++// Bit 31 :0 rg_esti_cfg1 U RW default = 'h0 ++typedef union RG_ESTI_A1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_esti_cfg1 : 32; ++ } b; ++} RG_ESTI_A1_FIELD_T; ++ ++#define RG_ESTI_A3 (RF_D_ADDA_ESTI_REG_BASE + 0xc) ++// Bit 14 :0 ro_rxirr_eup_0 U RO default = 'h0 ++// Bit 30 :16 ro_rxirr_eup_1 U RO default = 'h0 ++typedef union RG_ESTI_A3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rxirr_eup_0 : 15; ++ unsigned int rsvd_0 : 1; ++ unsigned int ro_rxirr_eup_1 : 15; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_ESTI_A3_FIELD_T; ++ ++#define RG_ESTI_A4 (RF_D_ADDA_ESTI_REG_BASE + 0x10) ++// Bit 14 :0 ro_rxirr_eup_2 U RO default = 'h0 ++// Bit 30 :16 ro_rxirr_eup_3 U RO default = 'h0 ++typedef union RG_ESTI_A4_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rxirr_eup_2 : 15; ++ unsigned int rsvd_0 : 1; ++ unsigned int ro_rxirr_eup_3 : 15; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_ESTI_A4_FIELD_T; ++ ++#define RG_ESTI_A5 (RF_D_ADDA_ESTI_REG_BASE + 0x14) ++// Bit 14 :0 ro_rxirr_pup_0 U RO default = 'h0 ++// Bit 30 :16 ro_rxirr_pup_1 U RO default = 'h0 ++typedef union RG_ESTI_A5_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rxirr_pup_0 : 15; ++ unsigned int rsvd_0 : 1; ++ unsigned int ro_rxirr_pup_1 : 15; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_ESTI_A5_FIELD_T; ++ ++#define RG_ESTI_A6 (RF_D_ADDA_ESTI_REG_BASE + 0x18) ++// Bit 14 :0 ro_rxirr_pup_2 U RO default = 'h0 ++// Bit 30 :16 ro_rxirr_pup_3 U RO default = 'h0 ++typedef union RG_ESTI_A6_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rxirr_pup_2 : 15; ++ unsigned int rsvd_0 : 1; ++ unsigned int ro_rxirr_pup_3 : 15; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_ESTI_A6_FIELD_T; ++ ++#define RG_ESTI_A7 (RF_D_ADDA_ESTI_REG_BASE + 0x1c) ++// Bit 14 :0 ro_rxirr_elow_0 U RO default = 'h0 ++// Bit 30 :16 ro_rxirr_elow_1 U RO default = 'h0 ++typedef union RG_ESTI_A7_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rxirr_elow_0 : 15; ++ unsigned int rsvd_0 : 1; ++ unsigned int ro_rxirr_elow_1 : 15; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_ESTI_A7_FIELD_T; ++ ++#define RG_ESTI_A8 (RF_D_ADDA_ESTI_REG_BASE + 0x20) ++// Bit 14 :0 ro_rxirr_elow_2 U RO default = 'h0 ++// Bit 30 :16 ro_rxirr_elow_3 U RO default = 'h0 ++typedef union RG_ESTI_A8_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rxirr_elow_2 : 15; ++ unsigned int rsvd_0 : 1; ++ unsigned int ro_rxirr_elow_3 : 15; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_ESTI_A8_FIELD_T; ++ ++#define RG_ESTI_A9 (RF_D_ADDA_ESTI_REG_BASE + 0x24) ++// Bit 14 :0 ro_rxirr_plow_0 U RO default = 'h0 ++// Bit 30 :16 ro_rxirr_plow_1 U RO default = 'h0 ++typedef union RG_ESTI_A9_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rxirr_plow_0 : 15; ++ unsigned int rsvd_0 : 1; ++ unsigned int ro_rxirr_plow_1 : 15; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_ESTI_A9_FIELD_T; ++ ++#define RG_ESTI_A10 (RF_D_ADDA_ESTI_REG_BASE + 0x28) ++// Bit 14 :0 ro_rxirr_plow_2 U RO default = 'h0 ++// Bit 30 :16 ro_rxirr_plow_3 U RO default = 'h0 ++typedef union RG_ESTI_A10_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rxirr_plow_2 : 15; ++ unsigned int rsvd_0 : 1; ++ unsigned int ro_rxirr_plow_3 : 15; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_ESTI_A10_FIELD_T; ++ ++#define RG_ESTI_A11 (RF_D_ADDA_ESTI_REG_BASE + 0x2c) ++// Bit 0 rg_iqib_enable U RW default = 'h0 ++// Bit 1 rg_iqib_hold U RW default = 'h0 ++// Bit 7 :4 rg_iqib_period U RW default = 'h0 ++// Bit 11 :8 rg_iqib_step_a U RW default = 'h1 ++// Bit 15 :12 rg_iqib_step_b U RW default = 'h1 ++// Bit 18 :16 rg_iqib_shift U RW default = 'h0 ++// Bit 20 rg_iqib_man_en U RW default = 'h0 ++// Bit 24 rg_rxirr_read_response U RW default = 'h0 ++// Bit 28 rg_rxirr_read_response_bypass U RW default = 'h0 ++// Bit 31 ro_rxirr_ready U RO default = 'h0 ++typedef union RG_ESTI_A11_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_iqib_enable : 1; ++ unsigned int rg_iqib_hold : 1; ++ unsigned int rsvd_0 : 2; ++ unsigned int rg_iqib_period : 4; ++ unsigned int rg_iqib_step_a : 4; ++ unsigned int rg_iqib_step_b : 4; ++ unsigned int rg_iqib_shift : 3; ++ unsigned int rsvd_1 : 1; ++ unsigned int rg_iqib_man_en : 1; ++ unsigned int rsvd_2 : 3; ++ unsigned int rg_rxirr_read_response : 1; ++ unsigned int rsvd_3 : 3; ++ unsigned int rg_rxirr_read_response_bypass : 1; ++ unsigned int rsvd_4 : 2; ++ unsigned int ro_rxirr_ready : 1; ++ } b; ++} RG_ESTI_A11_FIELD_T; ++ ++#define RG_ESTI_A12 (RF_D_ADDA_ESTI_REG_BASE + 0x30) ++// Bit 21 :0 rg_set_b U RW default = 'h0 ++// Bit 31 rg_set_val U RW default = 'h0 ++typedef union RG_ESTI_A12_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_set_b : 22; ++ unsigned int rsvd_0 : 9; ++ unsigned int rg_set_val : 1; ++ } b; ++} RG_ESTI_A12_FIELD_T; ++ ++#define RG_ESTI_A13 (RF_D_ADDA_ESTI_REG_BASE + 0x34) ++// Bit 18 :0 rg_set_a U RW default = 'h0 ++typedef union RG_ESTI_A13_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_set_a : 19; ++ unsigned int rsvd_0 : 13; ++ } b; ++} RG_ESTI_A13_FIELD_T; ++ ++#define RG_ESTI_A14 (RF_D_ADDA_ESTI_REG_BASE + 0x38) ++// Bit 3 :0 rg_dc_rm_leaky_factor U RW default = 'h0 ++// Bit 28 :4 rg_spectrum_ana_angle_man U RW default = 'h0 ++// Bit 31 rg_spectrum_ana_angle_man_en U RW default = 'h0 ++typedef union RG_ESTI_A14_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_dc_rm_leaky_factor : 4; ++ unsigned int rg_spectrum_ana_angle_man : 25; ++ unsigned int rsvd_0 : 2; ++ unsigned int rg_spectrum_ana_angle_man_en : 1; ++ } b; ++} RG_ESTI_A14_FIELD_T; ++ ++#define RG_ESTI_A15 (RF_D_ADDA_ESTI_REG_BASE + 0x3c) ++// Bit 31 :0 rg_esti_cfg2 U RW default = 'h0 ++typedef union RG_ESTI_A15_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_esti_cfg2 : 32; ++ } b; ++} RG_ESTI_A15_FIELD_T; ++ ++#define RG_ESTI_A16 (RF_D_ADDA_ESTI_REG_BASE + 0x40) ++// Bit 31 :0 rg_esti_cfg3 U RW default = 'h0 ++typedef union RG_ESTI_A16_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_esti_cfg3 : 32; ++ } b; ++} RG_ESTI_A16_FIELD_T; ++ ++#define RG_ESTI_A17 (RF_D_ADDA_ESTI_REG_BASE + 0x44) ++// Bit 6 :0 ro_dcoc_code_i U RO default = 'h0 ++// Bit 14 :8 ro_dcoc_code_q U RO default = 'h0 ++// Bit 16 ro_dcoc_code_ready U RO default = 'h0 ++// Bit 24 ro_dcoc_finish U RO default = 'h0 ++// Bit 28 rg_dcoc_read_response_bypass U RW default = 'h0 ++// Bit 31 rg_dcoc_read_response U RW default = 'h0 ++typedef union RG_ESTI_A17_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_dcoc_code_i : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int ro_dcoc_code_q : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int ro_dcoc_code_ready : 1; ++ unsigned int rsvd_2 : 7; ++ unsigned int ro_dcoc_finish : 1; ++ unsigned int rsvd_3 : 3; ++ unsigned int rg_dcoc_read_response_bypass : 1; ++ unsigned int rsvd_4 : 2; ++ unsigned int rg_dcoc_read_response : 1; ++ } b; ++} RG_ESTI_A17_FIELD_T; ++ ++#define RG_ESTI_A18 (RF_D_ADDA_ESTI_REG_BASE + 0x48) ++// Bit 3 :0 ro_lnatank_esti_code U RO default = 'h0 ++// Bit 8 ro_lnatank_esti_code_ready U RO default = 'h0 ++// Bit 16 ro_lnatank_esti_finish U RO default = 'h0 ++// Bit 28 rg_lnatank_read_response_bypass U RW default = 'h0 ++// Bit 31 rg_lnatank_read_response U RW default = 'h0 ++typedef union RG_ESTI_A18_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_lnatank_esti_code : 4; ++ unsigned int rsvd_0 : 4; ++ unsigned int ro_lnatank_esti_code_ready : 1; ++ unsigned int rsvd_1 : 7; ++ unsigned int ro_lnatank_esti_finish : 1; ++ unsigned int rsvd_2 : 11; ++ unsigned int rg_lnatank_read_response_bypass : 1; ++ unsigned int rsvd_3 : 2; ++ unsigned int rg_lnatank_read_response : 1; ++ } b; ++} RG_ESTI_A18_FIELD_T; ++ ++#define RG_ESTI_A19 (RF_D_ADDA_ESTI_REG_BASE + 0x4c) ++// Bit 7 :0 ro_txirr_dc_i U RO default = 'h0 ++// Bit 19 :12 ro_txirr_dc_q U RO default = 'h0 ++// Bit 24 ro_txirr_dc_ready U RO default = 'h0 ++// Bit 25 ro_txirr_code_ready U RO default = 'h0 ++// Bit 26 ro_txirr_mode_ready U RO default = 'h0 ++// Bit 28 rg_txirr_code_continue U RW default = 'h0 ++// Bit 29 rg_txirr_code_continue_bypass U RW default = 'h1 ++// Bit 30 rg_txirr_mode_continue U RW default = 'h0 ++// Bit 31 rg_txirr_mode_continue_bypass U RW default = 'h1 ++typedef union RG_ESTI_A19_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txirr_dc_i : 8; ++ unsigned int rsvd_0 : 4; ++ unsigned int ro_txirr_dc_q : 8; ++ unsigned int rsvd_1 : 4; ++ unsigned int ro_txirr_dc_ready : 1; ++ unsigned int ro_txirr_code_ready : 1; ++ unsigned int ro_txirr_mode_ready : 1; ++ unsigned int rsvd_2 : 1; ++ unsigned int rg_txirr_code_continue : 1; ++ unsigned int rg_txirr_code_continue_bypass : 1; ++ unsigned int rg_txirr_mode_continue : 1; ++ unsigned int rg_txirr_mode_continue_bypass : 1; ++ } b; ++} RG_ESTI_A19_FIELD_T; ++ ++#define RG_ESTI_A20 (RF_D_ADDA_ESTI_REG_BASE + 0x50) ++// Bit 7 :0 ro_txirr_alpha U RO default = 'h0 ++// Bit 19 :12 ro_txirr_theta U RO default = 'h0 ++// Bit 24 ro_txirr_irr_ready U RO default = 'h0 ++// Bit 28 rg_txirr_read_response_bypass U RW default = 'h0 ++// Bit 31 rg_txirr_read_response U RW default = 'h0 ++typedef union RG_ESTI_A20_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txirr_alpha : 8; ++ unsigned int rsvd_0 : 4; ++ unsigned int ro_txirr_theta : 8; ++ unsigned int rsvd_1 : 4; ++ unsigned int ro_txirr_irr_ready : 1; ++ unsigned int rsvd_2 : 3; ++ unsigned int rg_txirr_read_response_bypass : 1; ++ unsigned int rsvd_3 : 2; ++ unsigned int rg_txirr_read_response : 1; ++ } b; ++} RG_ESTI_A20_FIELD_T; ++ ++#define RG_ESTI_A21 (RF_D_ADDA_ESTI_REG_BASE + 0x54) ++// Bit 7 :0 rg_tx_dcmax_i U RW default = 'h33 ++// Bit 15 :8 rg_tx_dcmax_q U RW default = 'h33 ++// Bit 23 :16 rg_tx_alpha_max U RW default = 'h7b ++// Bit 31 :24 rg_tx_theta_max U RW default = 'h6b ++typedef union RG_ESTI_A21_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_dcmax_i : 8; ++ unsigned int rg_tx_dcmax_q : 8; ++ unsigned int rg_tx_alpha_max : 8; ++ unsigned int rg_tx_theta_max : 8; ++ } b; ++} RG_ESTI_A21_FIELD_T; ++ ++#define RG_ESTI_A22 (RF_D_ADDA_ESTI_REG_BASE + 0x58) ++// Bit 7 :0 rg_tx_dcmin_i U RW default = 'hcd ++// Bit 15 :8 rg_tx_dcmin_q U RW default = 'hcd ++// Bit 23 :16 rg_tx_alpha_min U RW default = 'h85 ++// Bit 31 :24 rg_tx_theta_min U RW default = 'h95 ++typedef union RG_ESTI_A22_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_dcmin_i : 8; ++ unsigned int rg_tx_dcmin_q : 8; ++ unsigned int rg_tx_alpha_min : 8; ++ unsigned int rg_tx_theta_min : 8; ++ } b; ++} RG_ESTI_A22_FIELD_T; ++ ++#define RG_ESTI_A23 (RF_D_ADDA_ESTI_REG_BASE + 0x5c) ++// Bit 3 :0 rg_tx_dc_i_step U RW default = 'h5 ++// Bit 7 :4 rg_tx_dc_q_step U RW default = 'h5 ++// Bit 11 :8 rg_tx_alpha_step U RW default = 'h3 ++// Bit 15 :12 rg_tx_theta_step U RW default = 'h4 ++// Bit 19 :16 rg_txirr_oper_bnd U RW default = 'h1 ++typedef union RG_ESTI_A23_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_dc_i_step : 4; ++ unsigned int rg_tx_dc_q_step : 4; ++ unsigned int rg_tx_alpha_step : 4; ++ unsigned int rg_tx_theta_step : 4; ++ unsigned int rg_txirr_oper_bnd : 4; ++ unsigned int rsvd_0 : 12; ++ } b; ++} RG_ESTI_A23_FIELD_T; ++ ++#define RG_ESTI_A24 (RF_D_ADDA_ESTI_REG_BASE + 0x60) ++// Bit 24 :0 rg_spectrum_ana_angle_dcoc U RW default = 'h0 ++typedef union RG_ESTI_A24_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_spectrum_ana_angle_dcoc : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_ESTI_A24_FIELD_T; ++ ++#define RG_ESTI_A25 (RF_D_ADDA_ESTI_REG_BASE + 0x64) ++// Bit 24 :0 rg_spectrum_ana_angle_lna U RW default = 'h1f99999 ++typedef union RG_ESTI_A25_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_spectrum_ana_angle_lna : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_ESTI_A25_FIELD_T; ++ ++#define RG_ESTI_A26 (RF_D_ADDA_ESTI_REG_BASE + 0x68) ++// Bit 24 :0 rg_spectrum_ana_angle_txirr U RW default = 'h1c00000 ++typedef union RG_ESTI_A26_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_spectrum_ana_angle_txirr : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_ESTI_A26_FIELD_T; ++ ++#define RG_ESTI_A27 (RF_D_ADDA_ESTI_REG_BASE + 0x6c) ++// Bit 24 :0 rg_spectrum_ana_angle_txdc U RW default = 'h1e00000 ++typedef union RG_ESTI_A27_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_spectrum_ana_angle_txdc : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_ESTI_A27_FIELD_T; ++ ++#define RG_ESTI_A28 (RF_D_ADDA_ESTI_REG_BASE + 0x70) ++// Bit 24 :0 rg_spectrum_ana_angle_dpd U RW default = 'h0 ++typedef union RG_ESTI_A28_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_spectrum_ana_angle_dpd : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_ESTI_A28_FIELD_T; ++ ++#define RG_ESTI_A29 (RF_D_ADDA_ESTI_REG_BASE + 0x74) ++// Bit 24 :0 rg_spectrum_ana_angle_pwc U RW default = 'h0 ++typedef union RG_ESTI_A29_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_spectrum_ana_angle_pwc : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_ESTI_A29_FIELD_T; ++ ++#define RG_ESTI_A30 (RF_D_ADDA_ESTI_REG_BASE + 0x78) ++// Bit 24 :0 rg_irr_tone_freq_0 U RW default = 'h4ccccc ++typedef union RG_ESTI_A30_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_tone_freq_0 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_ESTI_A30_FIELD_T; ++ ++#define RG_ESTI_A31 (RF_D_ADDA_ESTI_REG_BASE + 0x7c) ++// Bit 24 :0 rg_irr_tone_freq_1 U RW default = 'ha66666 ++typedef union RG_ESTI_A31_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_tone_freq_1 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_ESTI_A31_FIELD_T; ++ ++#define RG_ESTI_A32 (RF_D_ADDA_ESTI_REG_BASE + 0x80) ++// Bit 24 :0 rg_irr_tone_freq_2 U RW default = 'hd33333 ++typedef union RG_ESTI_A32_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_tone_freq_2 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_ESTI_A32_FIELD_T; ++ ++#define RG_ESTI_A33 (RF_D_ADDA_ESTI_REG_BASE + 0x84) ++// Bit 24 :0 rg_irr_tone_freq_3 U RW default = 'hf99999 ++typedef union RG_ESTI_A33_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_tone_freq_3 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_ESTI_A33_FIELD_T; ++ ++#define RG_ESTI_A34 (RF_D_ADDA_ESTI_REG_BASE + 0x88) ++// Bit 24 :0 rg_irr_tone_freq_4 U RW default = 'h1066666 ++typedef union RG_ESTI_A34_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_tone_freq_4 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_ESTI_A34_FIELD_T; ++ ++#define RG_ESTI_A35 (RF_D_ADDA_ESTI_REG_BASE + 0x8c) ++// Bit 24 :0 rg_irr_tone_freq_5 U RW default = 'h12ccccc ++typedef union RG_ESTI_A35_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_tone_freq_5 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_ESTI_A35_FIELD_T; ++ ++#define RG_ESTI_A36 (RF_D_ADDA_ESTI_REG_BASE + 0x90) ++// Bit 24 :0 rg_irr_tone_freq_6 U RW default = 'h1599999 ++typedef union RG_ESTI_A36_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_tone_freq_6 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_ESTI_A36_FIELD_T; ++ ++#define RG_ESTI_A37 (RF_D_ADDA_ESTI_REG_BASE + 0x94) ++// Bit 24 :0 rg_irr_tone_freq_7 U RW default = 'h1b33333 ++typedef union RG_ESTI_A37_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_tone_freq_7 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_ESTI_A37_FIELD_T; ++ ++#define RG_ESTI_A38 (RF_D_ADDA_ESTI_REG_BASE + 0x98) ++// Bit 15 :0 rg_irr_interp_coef_up0 U RW default = 'hf751 ++// Bit 31 :16 rg_irr_interp_coef_up1 U RW default = 'h97e ++typedef union RG_ESTI_A38_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_interp_coef_up0 : 16; ++ unsigned int rg_irr_interp_coef_up1 : 16; ++ } b; ++} RG_ESTI_A38_FIELD_T; ++ ++#define RG_ESTI_A39 (RF_D_ADDA_ESTI_REG_BASE + 0x9c) ++// Bit 15 :0 rg_irr_interp_coef_up2 U RW default = 'hfbb7 ++// Bit 31 :16 rg_irr_interp_coef_up3 U RW default = 'h292 ++typedef union RG_ESTI_A39_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_interp_coef_up2 : 16; ++ unsigned int rg_irr_interp_coef_up3 : 16; ++ } b; ++} RG_ESTI_A39_FIELD_T; ++ ++#define RG_ESTI_A40 (RF_D_ADDA_ESTI_REG_BASE + 0xa0) ++// Bit 15 :0 rg_irr_interp_coef_up4 U RW default = 'h369c ++// Bit 31 :16 rg_irr_interp_coef_up5 U RW default = 'hd196 ++typedef union RG_ESTI_A40_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_interp_coef_up4 : 16; ++ unsigned int rg_irr_interp_coef_up5 : 16; ++ } b; ++} RG_ESTI_A40_FIELD_T; ++ ++#define RG_ESTI_A41 (RF_D_ADDA_ESTI_REG_BASE + 0xa4) ++// Bit 15 :0 rg_irr_interp_coef_up6 U RW default = 'h1ae1 ++// Bit 31 :16 rg_irr_interp_coef_up7 U RW default = 'hf4d1 ++typedef union RG_ESTI_A41_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_interp_coef_up6 : 16; ++ unsigned int rg_irr_interp_coef_up7 : 16; ++ } b; ++} RG_ESTI_A41_FIELD_T; ++ ++#define RG_ESTI_A42 (RF_D_ADDA_ESTI_REG_BASE + 0xa8) ++// Bit 15 :0 rg_irr_interp_coef_up8 U RW default = 'had86 ++// Bit 31 :16 rg_irr_interp_coef_up9 U RW default = 'h4663 ++typedef union RG_ESTI_A42_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_interp_coef_up8 : 16; ++ unsigned int rg_irr_interp_coef_up9 : 16; ++ } b; ++} RG_ESTI_A42_FIELD_T; ++ ++#define RG_ESTI_A43 (RF_D_ADDA_ESTI_REG_BASE + 0xac) ++// Bit 15 :0 rg_irr_interp_coef_upa U RW default = 'hd7c6 ++// Bit 31 :16 rg_irr_interp_coef_upb U RW default = 'hdd8 ++typedef union RG_ESTI_A43_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_interp_coef_upa : 16; ++ unsigned int rg_irr_interp_coef_upb : 16; ++ } b; ++} RG_ESTI_A43_FIELD_T; ++ ++#define RG_ESTI_A44 (RF_D_ADDA_ESTI_REG_BASE + 0xb0) ++// Bit 15 :0 rg_irr_interp_coef_upc U RW default = 'h288d ++// Bit 31 :16 rg_irr_interp_coef_upd U RW default = 'hde88 ++typedef union RG_ESTI_A44_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_interp_coef_upc : 16; ++ unsigned int rg_irr_interp_coef_upd : 16; ++ } b; ++} RG_ESTI_A44_FIELD_T; ++ ++#define RG_ESTI_A45 (RF_D_ADDA_ESTI_REG_BASE + 0xb4) ++// Bit 15 :0 rg_irr_interp_coef_upe U RW default = 'h11a2 ++// Bit 31 :16 rg_irr_interp_coef_upf U RW default = 'hfac5 ++typedef union RG_ESTI_A45_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_interp_coef_upe : 16; ++ unsigned int rg_irr_interp_coef_upf : 16; ++ } b; ++} RG_ESTI_A45_FIELD_T; ++ ++#define RG_ESTI_A46 (RF_D_ADDA_ESTI_REG_BASE + 0xb8) ++// Bit 15 :0 rg_irr_interp_coef_low0 U RW default = 'h288d ++// Bit 31 :16 rg_irr_interp_coef_low1 U RW default = 'hde88 ++typedef union RG_ESTI_A46_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_interp_coef_low0 : 16; ++ unsigned int rg_irr_interp_coef_low1 : 16; ++ } b; ++} RG_ESTI_A46_FIELD_T; ++ ++#define RG_ESTI_A47 (RF_D_ADDA_ESTI_REG_BASE + 0xbc) ++// Bit 15 :0 rg_irr_interp_coef_low2 U RW default = 'h11a2 ++// Bit 31 :16 rg_irr_interp_coef_low3 U RW default = 'hfac5 ++typedef union RG_ESTI_A47_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_interp_coef_low2 : 16; ++ unsigned int rg_irr_interp_coef_low3 : 16; ++ } b; ++} RG_ESTI_A47_FIELD_T; ++ ++#define RG_ESTI_A48 (RF_D_ADDA_ESTI_REG_BASE + 0xc0) ++// Bit 15 :0 rg_irr_interp_coef_low4 U RW default = 'had86 ++// Bit 31 :16 rg_irr_interp_coef_low5 U RW default = 'h4663 ++typedef union RG_ESTI_A48_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_interp_coef_low4 : 16; ++ unsigned int rg_irr_interp_coef_low5 : 16; ++ } b; ++} RG_ESTI_A48_FIELD_T; ++ ++#define RG_ESTI_A49 (RF_D_ADDA_ESTI_REG_BASE + 0xc4) ++// Bit 15 :0 rg_irr_interp_coef_low6 U RW default = 'hd7c6 ++// Bit 31 :16 rg_irr_interp_coef_low7 U RW default = 'hdd8 ++typedef union RG_ESTI_A49_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_interp_coef_low6 : 16; ++ unsigned int rg_irr_interp_coef_low7 : 16; ++ } b; ++} RG_ESTI_A49_FIELD_T; ++ ++#define RG_ESTI_A50 (RF_D_ADDA_ESTI_REG_BASE + 0xc8) ++// Bit 15 :0 rg_irr_interp_coef_low8 U RW default = 'h369c ++// Bit 31 :16 rg_irr_interp_coef_low9 U RW default = 'hd196 ++typedef union RG_ESTI_A50_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_interp_coef_low8 : 16; ++ unsigned int rg_irr_interp_coef_low9 : 16; ++ } b; ++} RG_ESTI_A50_FIELD_T; ++ ++#define RG_ESTI_A51 (RF_D_ADDA_ESTI_REG_BASE + 0xcc) ++// Bit 15 :0 rg_irr_interp_coef_lowa U RW default = 'h1ae1 ++// Bit 31 :16 rg_irr_interp_coef_lowb U RW default = 'hf4d1 ++typedef union RG_ESTI_A51_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_interp_coef_lowa : 16; ++ unsigned int rg_irr_interp_coef_lowb : 16; ++ } b; ++} RG_ESTI_A51_FIELD_T; ++ ++#define RG_ESTI_A52 (RF_D_ADDA_ESTI_REG_BASE + 0xd0) ++// Bit 15 :0 rg_irr_interp_coef_lowc U RW default = 'hf751 ++// Bit 31 :16 rg_irr_interp_coef_lowd U RW default = 'h97e ++typedef union RG_ESTI_A52_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_interp_coef_lowc : 16; ++ unsigned int rg_irr_interp_coef_lowd : 16; ++ } b; ++} RG_ESTI_A52_FIELD_T; ++ ++#define RG_ESTI_A53 (RF_D_ADDA_ESTI_REG_BASE + 0xd4) ++// Bit 15 :0 rg_irr_interp_coef_lowe U RW default = 'hfbb7 ++// Bit 31 :16 rg_irr_interp_coef_lowf U RW default = 'h292 ++typedef union RG_ESTI_A53_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_irr_interp_coef_lowe : 16; ++ unsigned int rg_irr_interp_coef_lowf : 16; ++ } b; ++} RG_ESTI_A53_FIELD_T; ++ ++#define RG_ESTI_A54 (RF_D_ADDA_ESTI_REG_BASE + 0xd8) ++// Bit 3 :0 rg_rxirr_esti_len_avg_0 U RW default = 'h2 ++// Bit 7 :4 rg_rxirr_esti_miu_0 U RW default = 'h0 ++// Bit 15 :8 rg_rxirr_esti_navg_0 U RW default = 'h3 ++// Bit 19 :16 rg_rxirr_esti_len_avg_1 U RW default = 'h3 ++// Bit 23 :20 rg_rxirr_esti_miu_1 U RW default = 'h1 ++// Bit 31 :24 rg_rxirr_esti_navg_1 U RW default = 'h7 ++typedef union RG_ESTI_A54_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_rxirr_esti_len_avg_0 : 4; ++ unsigned int rg_rxirr_esti_miu_0 : 4; ++ unsigned int rg_rxirr_esti_navg_0 : 8; ++ unsigned int rg_rxirr_esti_len_avg_1 : 4; ++ unsigned int rg_rxirr_esti_miu_1 : 4; ++ unsigned int rg_rxirr_esti_navg_1 : 8; ++ } b; ++} RG_ESTI_A54_FIELD_T; ++ ++#define RG_ESTI_A55 (RF_D_ADDA_ESTI_REG_BASE + 0xdc) ++// Bit 3 :0 rg_rxirr_esti_len_avg_2 U RW default = 'h4 ++// Bit 7 :4 rg_rxirr_esti_miu_2 U RW default = 'h2 ++// Bit 15 :8 rg_rxirr_esti_navg_2 U RW default = 'hb ++// Bit 19 :16 rg_rxirr_esti_len_avg_3 U RW default = 'h4 ++// Bit 23 :20 rg_rxirr_esti_miu_3 U RW default = 'h3 ++// Bit 31 :24 rg_rxirr_esti_navg_3 U RW default = 'h13 ++typedef union RG_ESTI_A55_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_rxirr_esti_len_avg_2 : 4; ++ unsigned int rg_rxirr_esti_miu_2 : 4; ++ unsigned int rg_rxirr_esti_navg_2 : 8; ++ unsigned int rg_rxirr_esti_len_avg_3 : 4; ++ unsigned int rg_rxirr_esti_miu_3 : 4; ++ unsigned int rg_rxirr_esti_navg_3 : 8; ++ } b; ++} RG_ESTI_A55_FIELD_T; ++ ++#define RG_ESTI_A56 (RF_D_ADDA_ESTI_REG_BASE + 0xe0) ++// Bit 13 :0 ro_rxirr_interp_e_0 U RO default = 'h0 ++// Bit 29 :16 ro_rxirr_interp_e_1 U RO default = 'h0 ++typedef union RG_ESTI_A56_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rxirr_interp_e_0 : 14; ++ unsigned int rsvd_0 : 2; ++ unsigned int ro_rxirr_interp_e_1 : 14; ++ unsigned int rsvd_1 : 2; ++ } b; ++} RG_ESTI_A56_FIELD_T; ++ ++#define RG_ESTI_A57 (RF_D_ADDA_ESTI_REG_BASE + 0xe4) ++// Bit 13 :0 ro_rxirr_interp_e_2 U RO default = 'h0 ++// Bit 29 :16 ro_rxirr_interp_e_3 U RO default = 'h0 ++typedef union RG_ESTI_A57_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rxirr_interp_e_2 : 14; ++ unsigned int rsvd_0 : 2; ++ unsigned int ro_rxirr_interp_e_3 : 14; ++ unsigned int rsvd_1 : 2; ++ } b; ++} RG_ESTI_A57_FIELD_T; ++ ++#define RG_ESTI_A58 (RF_D_ADDA_ESTI_REG_BASE + 0xe8) ++// Bit 13 :0 ro_rxirr_interp_e_4 U RO default = 'h0 ++// Bit 29 :16 ro_rxirr_interp_e_5 U RO default = 'h0 ++typedef union RG_ESTI_A58_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rxirr_interp_e_4 : 14; ++ unsigned int rsvd_0 : 2; ++ unsigned int ro_rxirr_interp_e_5 : 14; ++ unsigned int rsvd_1 : 2; ++ } b; ++} RG_ESTI_A58_FIELD_T; ++ ++#define RG_ESTI_A59 (RF_D_ADDA_ESTI_REG_BASE + 0xec) ++// Bit 13 :0 ro_rxirr_interp_e_6 U RO default = 'h0 ++// Bit 29 :16 ro_rxirr_interp_e_7 U RO default = 'h0 ++typedef union RG_ESTI_A59_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rxirr_interp_e_6 : 14; ++ unsigned int rsvd_0 : 2; ++ unsigned int ro_rxirr_interp_e_7 : 14; ++ unsigned int rsvd_1 : 2; ++ } b; ++} RG_ESTI_A59_FIELD_T; ++ ++#define RG_ESTI_A60 (RF_D_ADDA_ESTI_REG_BASE + 0xf0) ++// Bit 13 :0 ro_rxirr_interp_p_0 U RO default = 'h0 ++// Bit 29 :16 ro_rxirr_interp_p_1 U RO default = 'h0 ++typedef union RG_ESTI_A60_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rxirr_interp_p_0 : 14; ++ unsigned int rsvd_0 : 2; ++ unsigned int ro_rxirr_interp_p_1 : 14; ++ unsigned int rsvd_1 : 2; ++ } b; ++} RG_ESTI_A60_FIELD_T; ++ ++#define RG_ESTI_A61 (RF_D_ADDA_ESTI_REG_BASE + 0xf4) ++// Bit 13 :0 ro_rxirr_interp_p_2 U RO default = 'h0 ++// Bit 29 :16 ro_rxirr_interp_p_3 U RO default = 'h0 ++typedef union RG_ESTI_A61_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rxirr_interp_p_2 : 14; ++ unsigned int rsvd_0 : 2; ++ unsigned int ro_rxirr_interp_p_3 : 14; ++ unsigned int rsvd_1 : 2; ++ } b; ++} RG_ESTI_A61_FIELD_T; ++ ++#define RG_ESTI_A62 (RF_D_ADDA_ESTI_REG_BASE + 0xf8) ++// Bit 13 :0 ro_rxirr_interp_p_4 U RO default = 'h0 ++// Bit 29 :16 ro_rxirr_interp_p_5 U RO default = 'h0 ++typedef union RG_ESTI_A62_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rxirr_interp_p_4 : 14; ++ unsigned int rsvd_0 : 2; ++ unsigned int ro_rxirr_interp_p_5 : 14; ++ unsigned int rsvd_1 : 2; ++ } b; ++} RG_ESTI_A62_FIELD_T; ++ ++#define RG_ESTI_A63 (RF_D_ADDA_ESTI_REG_BASE + 0xfc) ++// Bit 13 :0 ro_rxirr_interp_p_6 U RO default = 'h0 ++// Bit 29 :16 ro_rxirr_interp_p_7 U RO default = 'h0 ++typedef union RG_ESTI_A63_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rxirr_interp_p_6 : 14; ++ unsigned int rsvd_0 : 2; ++ unsigned int ro_rxirr_interp_p_7 : 14; ++ unsigned int rsvd_1 : 2; ++ } b; ++} RG_ESTI_A63_FIELD_T; ++ ++#define RG_ESTI_A64 (RF_D_ADDA_ESTI_REG_BASE + 0x100) ++// Bit 23 :0 rg_adda_wait_count U RW default = 'h50 ++typedef union RG_ESTI_A64_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_adda_wait_count : 24; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_ESTI_A64_FIELD_T; ++ ++#define RG_ESTI_A65 (RF_D_ADDA_ESTI_REG_BASE + 0x104) ++// Bit 14 :0 rg_adda_calc_count U RW default = 'h50 ++typedef union RG_ESTI_A65_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_adda_calc_count : 15; ++ unsigned int rsvd_0 : 17; ++ } b; ++} RG_ESTI_A65_FIELD_T; ++ ++#define RG_ESTI_A66 (RF_D_ADDA_ESTI_REG_BASE + 0x108) ++// Bit 27 :0 rg_adda_esti_count U RW default = 'h40000 ++typedef union RG_ESTI_A66_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_adda_esti_count : 28; ++ unsigned int rsvd_0 : 4; ++ } b; ++} RG_ESTI_A66_FIELD_T; ++ ++#define RG_ESTI_A67 (RF_D_ADDA_ESTI_REG_BASE + 0x10c) ++// Bit 0 rg_txpwc_read_response U RW default = 'h0 ++// Bit 4 rg_txpwc_read_response_bypass U RW default = 'h1 ++// Bit 16 :8 rg_txpwc_ph U RW default = 'h0 ++// Bit 28 :20 rg_txpwc_pl U RW default = 'h0 ++typedef union RG_ESTI_A67_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txpwc_read_response : 1; ++ unsigned int rsvd_0 : 3; ++ unsigned int rg_txpwc_read_response_bypass : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int rg_txpwc_ph : 9; ++ unsigned int rsvd_2 : 3; ++ unsigned int rg_txpwc_pl : 9; ++ unsigned int rsvd_3 : 3; ++ } b; ++} RG_ESTI_A67_FIELD_T; ++ ++#define RG_ESTI_A68 (RF_D_ADDA_ESTI_REG_BASE + 0x110) ++// Bit 7 :0 rg_txpwc_vh_amp U RW default = 'h0 ++// Bit 15 :8 rg_txpwc_vl_amp U RW default = 'h0 ++// Bit 25 :24 rg_txpwc_dc_cnt U RW default = 'h0 ++typedef union RG_ESTI_A68_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txpwc_vh_amp : 8; ++ unsigned int rg_txpwc_vl_amp : 8; ++ unsigned int rsvd_0 : 8; ++ unsigned int rg_txpwc_dc_cnt : 2; ++ unsigned int rsvd_1 : 6; ++ } b; ++} RG_ESTI_A68_FIELD_T; ++ ++#define RG_ESTI_A69 (RF_D_ADDA_ESTI_REG_BASE + 0x114) ++// Bit 8 :0 ro_txpwc_slope U RO default = 'h0 ++// Bit 26 :12 ro_txpwc_offset U RO default = 'h0 ++// Bit 31 ro_txpwc_ready U RO default = 'h0 ++typedef union RG_ESTI_A69_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txpwc_slope : 9; ++ unsigned int rsvd_0 : 3; ++ unsigned int ro_txpwc_offset : 15; ++ unsigned int rsvd_1 : 4; ++ unsigned int ro_txpwc_ready : 1; ++ } b; ++} RG_ESTI_A69_FIELD_T; ++ ++#define RG_ESTI_A70 (RF_D_ADDA_ESTI_REG_BASE + 0x118) ++// Bit 0 rg_txdpd_esti_read_response U RW default = 'h0 ++// Bit 2 rg_txdpd_esti_read_response_bypass U RW default = 'h0 ++// Bit 11 :4 rg_txdpd_esti_alpha U RW default = 'h33 ++// Bit 18 :12 rg_txdpd_esti_sync_gap U RW default = 'h20 ++// Bit 22 ro_txdpd_esti_ready U RO default = 'h0 ++// Bit 31 :24 rg_txdpd_esti_mp_pow_thresh U RW default = 'h6 ++typedef union RG_ESTI_A70_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_esti_read_response : 1; ++ unsigned int rsvd_0 : 1; ++ unsigned int rg_txdpd_esti_read_response_bypass : 1; ++ unsigned int rsvd_1 : 1; ++ unsigned int rg_txdpd_esti_alpha : 8; ++ unsigned int rg_txdpd_esti_sync_gap : 7; ++ unsigned int rsvd_2 : 3; ++ unsigned int ro_txdpd_esti_ready : 1; ++ unsigned int rsvd_3 : 1; ++ unsigned int rg_txdpd_esti_mp_pow_thresh : 8; ++ } b; ++} RG_ESTI_A70_FIELD_T; ++ ++#define RG_ESTI_A72 (RF_D_ADDA_ESTI_REG_BASE + 0x11c) ++// Bit 11 :0 ro_txdpd_esti_coef_i_0 U RO default = 'h0 ++// Bit 23 :12 ro_txdpd_esti_coef_q_0 U RO default = 'h0 ++typedef union RG_ESTI_A72_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txdpd_esti_coef_i_0 : 12; ++ unsigned int ro_txdpd_esti_coef_q_0 : 12; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_ESTI_A72_FIELD_T; ++ ++#define RG_ESTI_A73 (RF_D_ADDA_ESTI_REG_BASE + 0x120) ++// Bit 11 :0 ro_txdpd_esti_coef_i_1 U RO default = 'h0 ++// Bit 23 :12 ro_txdpd_esti_coef_q_1 U RO default = 'h0 ++typedef union RG_ESTI_A73_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txdpd_esti_coef_i_1 : 12; ++ unsigned int ro_txdpd_esti_coef_q_1 : 12; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_ESTI_A73_FIELD_T; ++ ++#define RG_ESTI_A74 (RF_D_ADDA_ESTI_REG_BASE + 0x124) ++// Bit 11 :0 ro_txdpd_esti_coef_i_2 U RO default = 'h0 ++// Bit 23 :12 ro_txdpd_esti_coef_q_2 U RO default = 'h0 ++typedef union RG_ESTI_A74_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txdpd_esti_coef_i_2 : 12; ++ unsigned int ro_txdpd_esti_coef_q_2 : 12; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_ESTI_A74_FIELD_T; ++ ++#define RG_ESTI_A75 (RF_D_ADDA_ESTI_REG_BASE + 0x128) ++// Bit 11 :0 ro_txdpd_esti_coef_i_3 U RO default = 'h0 ++// Bit 23 :12 ro_txdpd_esti_coef_q_3 U RO default = 'h0 ++typedef union RG_ESTI_A75_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txdpd_esti_coef_i_3 : 12; ++ unsigned int ro_txdpd_esti_coef_q_3 : 12; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_ESTI_A75_FIELD_T; ++ ++#define RG_ESTI_A76 (RF_D_ADDA_ESTI_REG_BASE + 0x12c) ++// Bit 11 :0 ro_txdpd_esti_coef_i_4 U RO default = 'h0 ++// Bit 23 :12 ro_txdpd_esti_coef_q_4 U RO default = 'h0 ++typedef union RG_ESTI_A76_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txdpd_esti_coef_i_4 : 12; ++ unsigned int ro_txdpd_esti_coef_q_4 : 12; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_ESTI_A76_FIELD_T; ++ ++#define RG_ESTI_A77 (RF_D_ADDA_ESTI_REG_BASE + 0x130) ++// Bit 11 :0 ro_txdpd_esti_coef_i_5 U RO default = 'h0 ++// Bit 23 :12 ro_txdpd_esti_coef_q_5 U RO default = 'h0 ++typedef union RG_ESTI_A77_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txdpd_esti_coef_i_5 : 12; ++ unsigned int ro_txdpd_esti_coef_q_5 : 12; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_ESTI_A77_FIELD_T; ++ ++#define RG_ESTI_A78 (RF_D_ADDA_ESTI_REG_BASE + 0x134) ++// Bit 11 :0 ro_txdpd_esti_coef_i_6 U RO default = 'h0 ++// Bit 23 :12 ro_txdpd_esti_coef_q_6 U RO default = 'h0 ++typedef union RG_ESTI_A78_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txdpd_esti_coef_i_6 : 12; ++ unsigned int ro_txdpd_esti_coef_q_6 : 12; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_ESTI_A78_FIELD_T; ++ ++#define RG_ESTI_A79 (RF_D_ADDA_ESTI_REG_BASE + 0x138) ++// Bit 11 :0 ro_txdpd_esti_coef_i_7 U RO default = 'h0 ++// Bit 23 :12 ro_txdpd_esti_coef_q_7 U RO default = 'h0 ++typedef union RG_ESTI_A79_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txdpd_esti_coef_i_7 : 12; ++ unsigned int ro_txdpd_esti_coef_q_7 : 12; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_ESTI_A79_FIELD_T; ++ ++#define RG_ESTI_A80 (RF_D_ADDA_ESTI_REG_BASE + 0x13c) ++// Bit 11 :0 ro_txdpd_esti_coef_i_8 U RO default = 'h0 ++// Bit 23 :12 ro_txdpd_esti_coef_q_8 U RO default = 'h0 ++typedef union RG_ESTI_A80_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txdpd_esti_coef_i_8 : 12; ++ unsigned int ro_txdpd_esti_coef_q_8 : 12; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_ESTI_A80_FIELD_T; ++ ++#define RG_ESTI_A81 (RF_D_ADDA_ESTI_REG_BASE + 0x140) ++// Bit 11 :0 ro_txdpd_esti_coef_i_9 U RO default = 'h0 ++// Bit 23 :12 ro_txdpd_esti_coef_q_9 U RO default = 'h0 ++typedef union RG_ESTI_A81_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txdpd_esti_coef_i_9 : 12; ++ unsigned int ro_txdpd_esti_coef_q_9 : 12; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_ESTI_A81_FIELD_T; ++ ++#define RG_ESTI_A82 (RF_D_ADDA_ESTI_REG_BASE + 0x144) ++// Bit 11 :0 ro_txdpd_esti_coef_i_a U RO default = 'h0 ++// Bit 23 :12 ro_txdpd_esti_coef_q_a U RO default = 'h0 ++typedef union RG_ESTI_A82_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txdpd_esti_coef_i_a : 12; ++ unsigned int ro_txdpd_esti_coef_q_a : 12; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_ESTI_A82_FIELD_T; ++ ++#define RG_ESTI_A83 (RF_D_ADDA_ESTI_REG_BASE + 0x148) ++// Bit 11 :0 ro_txdpd_esti_coef_i_b U RO default = 'h0 ++// Bit 23 :12 ro_txdpd_esti_coef_q_b U RO default = 'h0 ++typedef union RG_ESTI_A83_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txdpd_esti_coef_i_b : 12; ++ unsigned int ro_txdpd_esti_coef_q_b : 12; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_ESTI_A83_FIELD_T; ++ ++#define RG_ESTI_A84 (RF_D_ADDA_ESTI_REG_BASE + 0x14c) ++// Bit 11 :0 ro_txdpd_esti_coef_i_c U RO default = 'h0 ++// Bit 23 :12 ro_txdpd_esti_coef_q_c U RO default = 'h0 ++typedef union RG_ESTI_A84_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txdpd_esti_coef_i_c : 12; ++ unsigned int ro_txdpd_esti_coef_q_c : 12; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_ESTI_A84_FIELD_T; ++ ++#define RG_ESTI_A85 (RF_D_ADDA_ESTI_REG_BASE + 0x150) ++// Bit 11 :0 ro_txdpd_esti_coef_i_d U RO default = 'h0 ++// Bit 23 :12 ro_txdpd_esti_coef_q_d U RO default = 'h0 ++typedef union RG_ESTI_A85_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txdpd_esti_coef_i_d : 12; ++ unsigned int ro_txdpd_esti_coef_q_d : 12; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_ESTI_A85_FIELD_T; ++ ++#define RG_ESTI_A86 (RF_D_ADDA_ESTI_REG_BASE + 0x154) ++// Bit 11 :0 ro_txdpd_esti_coef_i_e U RO default = 'h0 ++// Bit 23 :12 ro_txdpd_esti_coef_q_e U RO default = 'h0 ++typedef union RG_ESTI_A86_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txdpd_esti_coef_i_e : 12; ++ unsigned int ro_txdpd_esti_coef_q_e : 12; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_ESTI_A86_FIELD_T; ++ ++#define RG_ESTI_A87 (RF_D_ADDA_ESTI_REG_BASE + 0x158) ++// Bit 0 rg_snr_esti_en U RW default = 'h1 ++// Bit 6 :4 rg_snr_esti_calctime U RW default = 'h0 ++// Bit 10 :8 rg_snr_alpha U RW default = 'h0 ++// Bit 18 :16 rg_txdpd_snr_esti_alpha U RW default = 'h0 ++typedef union RG_ESTI_A87_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_snr_esti_en : 1; ++ unsigned int rsvd_0 : 3; ++ unsigned int rg_snr_esti_calctime : 3; ++ unsigned int rsvd_1 : 1; ++ unsigned int rg_snr_alpha : 3; ++ unsigned int rsvd_2 : 5; ++ unsigned int rg_txdpd_snr_esti_alpha : 3; ++ unsigned int rsvd_3 : 13; ++ } b; ++} RG_ESTI_A87_FIELD_T; ++ ++#define RG_ESTI_A88 (RF_D_ADDA_ESTI_REG_BASE + 0x15c) ++// Bit 8 :0 ro_adda_snr_db U RO default = 'h0 ++// Bit 12 ro_adda_db_vld U RO default = 'h0 ++// Bit 24 :16 ro_adda_pwr_db U RO default = 'h0 ++typedef union RG_ESTI_A88_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_adda_snr_db : 9; ++ unsigned int rsvd_0 : 3; ++ unsigned int ro_adda_db_vld : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int ro_adda_pwr_db : 9; ++ unsigned int rsvd_2 : 7; ++ } b; ++} RG_ESTI_A88_FIELD_T; ++ ++#define RG_ESTI_A89 (RF_D_ADDA_ESTI_REG_BASE + 0x160) ++// Bit 8 :0 ro_txdpd_esti_snr_db U RO default = 'h0 ++typedef union RG_ESTI_A89_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txdpd_esti_snr_db : 9; ++ unsigned int rsvd_0 : 23; ++ } b; ++} RG_ESTI_A89_FIELD_T; ++ ++#define RG_ESTI_A90 (RF_D_ADDA_ESTI_REG_BASE + 0x164) ++// Bit 29 :0 ro_dcoc_dc_i U RO default = 'h0 ++typedef union RG_ESTI_A90_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_dcoc_dc_i : 30; ++ unsigned int rsvd_0 : 2; ++ } b; ++} RG_ESTI_A90_FIELD_T; ++ ++#define RG_ESTI_A91 (RF_D_ADDA_ESTI_REG_BASE + 0x168) ++// Bit 29 :0 ro_dcoc_dc_q U RO default = 'h0 ++typedef union RG_ESTI_A91_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_dcoc_dc_q : 30; ++ unsigned int rsvd_0 : 2; ++ } b; ++} RG_ESTI_A91_FIELD_T; ++ ++#define RG_ESTI_A92 (RF_D_ADDA_ESTI_REG_BASE + 0x16c) ++// Bit 31 :0 ro_txirr_dc_pow_low U RO default = 'h0 ++typedef union RG_ESTI_A92_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txirr_dc_pow_low : 32; ++ } b; ++} RG_ESTI_A92_FIELD_T; ++ ++#define RG_ESTI_A93 (RF_D_ADDA_ESTI_REG_BASE + 0x170) ++// Bit 22 :0 ro_txirr_dc_pow_high U RO default = 'h0 ++typedef union RG_ESTI_A93_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txirr_dc_pow_high : 23; ++ unsigned int rsvd_0 : 9; ++ } b; ++} RG_ESTI_A93_FIELD_T; ++ ++#define RG_ESTI_A94 (RF_D_ADDA_ESTI_REG_BASE + 0x174) ++// Bit 31 :0 ro_lnatank_esti_pow U RO default = 'h0 ++typedef union RG_ESTI_A94_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_lnatank_esti_pow : 32; ++ } b; ++} RG_ESTI_A94_FIELD_T; ++ ++#define RG_ESTI_A96 (RF_D_ADDA_ESTI_REG_BASE + 0x17c) ++// Bit 11 :0 ro_txdpd_gain U RO default = 'h0 ++typedef union RG_ESTI_A96_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txdpd_gain : 12; ++ unsigned int rsvd_0 : 20; ++ } b; ++} RG_ESTI_A96_FIELD_T; ++ ++#endif ++ +diff --git a/drivers/net/wireless/w1/common/rf_d_adda_recv_reg.h b/drivers/net/wireless/w1/common/rf_d_adda_recv_reg.h +new file mode 100644 +index 0000000000000000000000000000000000000000..a2059b05976e8c1fdb9d75179f61c2ee95b557f8 +--- /dev/null ++++ b/drivers/net/wireless/w1/common/rf_d_adda_recv_reg.h +@@ -0,0 +1,419 @@ ++#ifdef RF_D_ADDA_RECV_REG ++#else ++#define RF_D_ADDA_RECV_REG ++ ++ ++#define RF_D_ADDA_RECV_REG_BASE (0xa0e800) ++ ++#define RG_RECV_A0 (RF_D_ADDA_RECV_REG_BASE + 0x0) ++// Bit 31 :0 rg_recv_cfg0 U RW default = 'h0 ++typedef union RG_RECV_A0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_recv_cfg0 : 32; ++ } b; ++} RG_RECV_A0_FIELD_T; ++ ++#define RG_RECV_A1 (RF_D_ADDA_RECV_REG_BASE + 0x4) ++// Bit 31 :0 rg_recv_cfg1 U RW default = 'h0 ++typedef union RG_RECV_A1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_recv_cfg1 : 32; ++ } b; ++} RG_RECV_A1_FIELD_T; ++ ++#define RG_RECV_A2 (RF_D_ADDA_RECV_REG_BASE + 0x8) ++// Bit 0 rg_rxneg_msb U RW default = 'h0 ++// Bit 1 rg_rxiq_swap U RW default = 'h0 ++// Bit 11 :4 rg_rxi_dcoft U RW default = 'h0 ++// Bit 19 :12 rg_rxq_dcoft U RW default = 'h0 ++// Bit 20 rg_dcloop_bypass U RW default = 'h1 ++// Bit 24 rg_rx_adc_fs U RW default = 'h1 ++// Bit 28 rg_to_agc_en U RW default = 'h0 ++typedef union RG_RECV_A2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_rxneg_msb : 1; ++ unsigned int rg_rxiq_swap : 1; ++ unsigned int rsvd_0 : 2; ++ unsigned int rg_rxi_dcoft : 8; ++ unsigned int rg_rxq_dcoft : 8; ++ unsigned int rg_dcloop_bypass : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int rg_rx_adc_fs : 1; ++ unsigned int rsvd_2 : 3; ++ unsigned int rg_to_agc_en : 1; ++ unsigned int rsvd_3 : 3; ++ } b; ++} RG_RECV_A2_FIELD_T; ++ ++#define RG_RECV_A3 (RF_D_ADDA_RECV_REG_BASE + 0xc) ++// Bit 14 :0 rg_rxirr_eup_0 U RW default = 'h7f51 ++// Bit 30 :16 rg_rxirr_eup_1 U RW default = 'h46 ++typedef union RG_RECV_A3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_rxirr_eup_0 : 15; ++ unsigned int rsvd_0 : 1; ++ unsigned int rg_rxirr_eup_1 : 15; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_RECV_A3_FIELD_T; ++ ++#define RG_RECV_A4 (RF_D_ADDA_RECV_REG_BASE + 0x10) ++// Bit 14 :0 rg_rxirr_eup_2 U RW default = 'h7fb7 ++// Bit 30 :16 rg_rxirr_eup_3 U RW default = 'h17 ++typedef union RG_RECV_A4_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_rxirr_eup_2 : 15; ++ unsigned int rsvd_0 : 1; ++ unsigned int rg_rxirr_eup_3 : 15; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_RECV_A4_FIELD_T; ++ ++#define RG_RECV_A5 (RF_D_ADDA_RECV_REG_BASE + 0x14) ++// Bit 14 :0 rg_rxirr_pup_0 U RW default = 'h5a4 ++// Bit 30 :16 rg_rxirr_pup_1 U RW default = 'h7ff9 ++typedef union RG_RECV_A5_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_rxirr_pup_0 : 15; ++ unsigned int rsvd_0 : 1; ++ unsigned int rg_rxirr_pup_1 : 15; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_RECV_A5_FIELD_T; ++ ++#define RG_RECV_A6 (RF_D_ADDA_RECV_REG_BASE + 0x18) ++// Bit 14 :0 rg_rxirr_pup_2 U RW default = 'h7ff6 ++// Bit 30 :16 rg_rxirr_pup_3 U RW default = 'h7 ++typedef union RG_RECV_A6_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_rxirr_pup_2 : 15; ++ unsigned int rsvd_0 : 1; ++ unsigned int rg_rxirr_pup_3 : 15; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_RECV_A6_FIELD_T; ++ ++#define RG_RECV_A7 (RF_D_ADDA_RECV_REG_BASE + 0x1c) ++// Bit 14 :0 rg_rxirr_elow_0 U RW default = 'h7f7d ++// Bit 30 :16 rg_rxirr_elow_1 U RW default = 'h7fba ++typedef union RG_RECV_A7_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_rxirr_elow_0 : 15; ++ unsigned int rsvd_0 : 1; ++ unsigned int rg_rxirr_elow_1 : 15; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_RECV_A7_FIELD_T; ++ ++#define RG_RECV_A8 (RF_D_ADDA_RECV_REG_BASE + 0x20) ++// Bit 14 :0 rg_rxirr_elow_2 U RW default = 'h46 ++// Bit 30 :16 rg_rxirr_elow_3 U RW default = 'h7feb ++typedef union RG_RECV_A8_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_rxirr_elow_2 : 15; ++ unsigned int rsvd_0 : 1; ++ unsigned int rg_rxirr_elow_3 : 15; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_RECV_A8_FIELD_T; ++ ++#define RG_RECV_A9 (RF_D_ADDA_RECV_REG_BASE + 0x24) ++// Bit 14 :0 rg_rxirr_plow_0 U RW default = 'h5a5 ++// Bit 30 :16 rg_rxirr_plow_1 U RW default = 'h7ffa ++typedef union RG_RECV_A9_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_rxirr_plow_0 : 15; ++ unsigned int rsvd_0 : 1; ++ unsigned int rg_rxirr_plow_1 : 15; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_RECV_A9_FIELD_T; ++ ++#define RG_RECV_A10 (RF_D_ADDA_RECV_REG_BASE + 0x28) ++// Bit 14 :0 rg_rxirr_plow_2 U RW default = 'h7ff3 ++// Bit 30 :16 rg_rxirr_plow_3 U RW default = 'h8 ++typedef union RG_RECV_A10_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_rxirr_plow_2 : 15; ++ unsigned int rsvd_0 : 1; ++ unsigned int rg_rxirr_plow_3 : 15; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_RECV_A10_FIELD_T; ++ ++#define RG_RECV_A11 (RF_D_ADDA_RECV_REG_BASE + 0x2c) ++// Bit 0 rg_rxirr_man_mode U RW default = 'h1 ++// Bit 4 rg_rxirr_bypass U RW default = 'h1 ++// Bit 11 :8 rg_rx_async_wgap U RW default = 'ha ++typedef union RG_RECV_A11_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_rxirr_man_mode : 1; ++ unsigned int rsvd_0 : 3; ++ unsigned int rg_rxirr_bypass : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int rg_rx_async_wgap : 4; ++ unsigned int rsvd_2 : 20; ++ } b; ++} RG_RECV_A11_FIELD_T; ++ ++#define RG_RECV_A12 (RF_D_ADDA_RECV_REG_BASE + 0x30) ++// Bit 24 :0 rg_rxddc_angle U RW default = 'h0 ++// Bit 28 rg_rxddc_phs_reset U RW default = 'h0 ++// Bit 31 rg_rxddc_bypass U RW default = 'h1 ++typedef union RG_RECV_A12_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_rxddc_angle : 25; ++ unsigned int rsvd_0 : 3; ++ unsigned int rg_rxddc_phs_reset : 1; ++ unsigned int rsvd_1 : 2; ++ unsigned int rg_rxddc_bypass : 1; ++ } b; ++} RG_RECV_A12_FIELD_T; ++ ++#define RG_RECV_A13 (RF_D_ADDA_RECV_REG_BASE + 0x34) ++// Bit 8 :0 rg_dc_sub_thr_pow U RW default = 'h74 ++typedef union RG_RECV_A13_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_dc_sub_thr_pow : 9; ++ unsigned int rsvd_0 : 23; ++ } b; ++} RG_RECV_A13_FIELD_T; ++ ++#define RG_RECV_A14 (RF_D_ADDA_RECV_REG_BASE + 0x38) ++// Bit 8 :0 rg_hdmi_sub_thr_pow1 U RW default = 'h70 ++// Bit 20 :12 rg_hdmi_sub_thr_pow2 U RW default = 'h68 ++typedef union RG_RECV_A14_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_hdmi_sub_thr_pow1 : 9; ++ unsigned int rsvd_0 : 3; ++ unsigned int rg_hdmi_sub_thr_pow2 : 9; ++ unsigned int rsvd_1 : 11; ++ } b; ++} RG_RECV_A14_FIELD_T; ++ ++#define RG_RECV_A15 (RF_D_ADDA_RECV_REG_BASE + 0x3c) ++// Bit 8 :0 rg_cw_sub_thr_pow1 U RW default = 'h78 ++// Bit 20 :12 rg_cw_sub_thr_pow2 U RW default = 'h66 ++typedef union RG_RECV_A15_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_cw_sub_thr_pow1 : 9; ++ unsigned int rsvd_0 : 3; ++ unsigned int rg_cw_sub_thr_pow2 : 9; ++ unsigned int rsvd_1 : 11; ++ } b; ++} RG_RECV_A15_FIELD_T; ++ ++#define RG_RECV_A16 (RF_D_ADDA_RECV_REG_BASE + 0x40) ++// Bit 0 rg_cw_remove_sub_man_bypass0 U RW default = 'h0 ++// Bit 1 rg_cw_remove_sub_bypass_man_mode0 U RW default = 'h0 ++// Bit 4 rg_cw_remove_sub_man_bypass1 U RW default = 'h0 ++// Bit 5 rg_cw_remove_sub_bypass_man_mode1 U RW default = 'h0 ++// Bit 8 rg_cw_remove_sub_man_bypass2 U RW default = 'h0 ++// Bit 9 rg_cw_remove_sub_bypass_man_mode2 U RW default = 'h0 ++// Bit 12 rg_cw_remove_sub_man_bypass3 U RW default = 'h0 ++// Bit 13 rg_cw_remove_sub_bypass_man_mode3 U RW default = 'h0 ++// Bit 16 rg_cw_remove_sub_man_bypass4 U RW default = 'h0 ++// Bit 17 rg_cw_remove_sub_bypass_man_mode4 U RW default = 'h0 ++// Bit 20 rg_dc_bypass U RW default = 'h0 ++// Bit 24 rg_hdmi_bypass U RW default = 'h0 ++// Bit 28 rg_cw_bypass U RW default = 'h0 ++// Bit 30 rg_cw_remove_bypass_val U RW default = 'h1 ++// Bit 31 rg_cw_remove_bypass_man U RW default = 'h1 ++typedef union RG_RECV_A16_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_cw_remove_sub_man_bypass0 : 1; ++ unsigned int rg_cw_remove_sub_bypass_man_mode0 : 1; ++ unsigned int rsvd_0 : 2; ++ unsigned int rg_cw_remove_sub_man_bypass1 : 1; ++ unsigned int rg_cw_remove_sub_bypass_man_mode1 : 1; ++ unsigned int rsvd_1 : 2; ++ unsigned int rg_cw_remove_sub_man_bypass2 : 1; ++ unsigned int rg_cw_remove_sub_bypass_man_mode2 : 1; ++ unsigned int rsvd_2 : 2; ++ unsigned int rg_cw_remove_sub_man_bypass3 : 1; ++ unsigned int rg_cw_remove_sub_bypass_man_mode3 : 1; ++ unsigned int rsvd_3 : 2; ++ unsigned int rg_cw_remove_sub_man_bypass4 : 1; ++ unsigned int rg_cw_remove_sub_bypass_man_mode4 : 1; ++ unsigned int rsvd_4 : 2; ++ unsigned int rg_dc_bypass : 1; ++ unsigned int rsvd_5 : 3; ++ unsigned int rg_hdmi_bypass : 1; ++ unsigned int rsvd_6 : 3; ++ unsigned int rg_cw_bypass : 1; ++ unsigned int rsvd_7 : 1; ++ unsigned int rg_cw_remove_bypass_val : 1; ++ unsigned int rg_cw_remove_bypass_man : 1; ++ } b; ++} RG_RECV_A16_FIELD_T; ++ ++#define RG_RECV_A17 (RF_D_ADDA_RECV_REG_BASE + 0x44) ++// Bit 24 :0 rg_cw_remove_sub_angle_base1 U RW default = 'h1d33333 ++typedef union RG_RECV_A17_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_cw_remove_sub_angle_base1 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_RECV_A17_FIELD_T; ++ ++#define RG_RECV_A18 (RF_D_ADDA_RECV_REG_BASE + 0x48) ++// Bit 24 :0 rg_cw_remove_sub_angle_base2 U RW default = 'h800000 ++typedef union RG_RECV_A18_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_cw_remove_sub_angle_base2 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_RECV_A18_FIELD_T; ++ ++#define RG_RECV_A19 (RF_D_ADDA_RECV_REG_BASE + 0x4c) ++// Bit 24 :0 rg_cw_remove_sub_angle_base3 U RW default = 'h1e00000 ++typedef union RG_RECV_A19_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_cw_remove_sub_angle_base3 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_RECV_A19_FIELD_T; ++ ++#define RG_RECV_A20 (RF_D_ADDA_RECV_REG_BASE + 0x50) ++// Bit 24 :0 rg_cw_remove_sub_angle_base4 U RW default = 'he00000 ++typedef union RG_RECV_A20_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_cw_remove_sub_angle_base4 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_RECV_A20_FIELD_T; ++ ++#define RG_RECV_A21 (RF_D_ADDA_RECV_REG_BASE + 0x54) ++// Bit 9 :0 rg_dc_dc_remove_cnt U RW default = 'h3ff ++// Bit 25 :16 rg_hdmi_dc_remove_cnt U RW default = 'h3f ++typedef union RG_RECV_A21_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_dc_dc_remove_cnt : 10; ++ unsigned int rsvd_0 : 6; ++ unsigned int rg_hdmi_dc_remove_cnt : 10; ++ unsigned int rsvd_1 : 6; ++ } b; ++} RG_RECV_A21_FIELD_T; ++ ++#define RG_RECV_A22 (RF_D_ADDA_RECV_REG_BASE + 0x58) ++// Bit 9 :0 rg_cw_dc_remove_cnt U RW default = 'h3f ++typedef union RG_RECV_A22_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_cw_dc_remove_cnt : 10; ++ unsigned int rsvd_0 : 22; ++ } b; ++} RG_RECV_A22_FIELD_T; ++ ++#define RG_RECV_A23 (RF_D_ADDA_RECV_REG_BASE + 0x5c) ++// Bit 0 rg_cali_cw_rmv_bypass U RW default = 'h1 ++// Bit 4 rg_agc_cw_rmv_bypass U RW default = 'h1 ++typedef union RG_RECV_A23_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_cali_cw_rmv_bypass : 1; ++ unsigned int rsvd_0 : 3; ++ unsigned int rg_agc_cw_rmv_bypass : 1; ++ unsigned int rsvd_1 : 27; ++ } b; ++} RG_RECV_A23_FIELD_T; ++ ++#define RG_RECV_A24 (RF_D_ADDA_RECV_REG_BASE + 0x60) ++// Bit 8 :0 rg_cw_remove_gaindb_val U RW default = 'h84 ++// Bit 12 rg_cw_remove_gaindb_man U RW default = 'h0 ++typedef union RG_RECV_A24_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_cw_remove_gaindb_val : 9; ++ unsigned int rsvd_0 : 3; ++ unsigned int rg_cw_remove_gaindb_man : 1; ++ unsigned int rsvd_1 : 19; ++ } b; ++} RG_RECV_A24_FIELD_T; ++ ++#define RG_RECV_A25 (RF_D_ADDA_RECV_REG_BASE + 0x64) ++// Bit 0 rg_rssi_snr_est U RW default = 'h0 ++typedef union RG_RECV_A25_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_rssi_snr_est : 1; ++ unsigned int rsvd_0 : 31; ++ } b; ++} RG_RECV_A25_FIELD_T; ++ ++#endif ++ +diff --git a/drivers/net/wireless/w1/common/rf_d_adda_xmit_reg.h b/drivers/net/wireless/w1/common/rf_d_adda_xmit_reg.h +new file mode 100644 +index 0000000000000000000000000000000000000000..7788a25772f5d993d9e59a7d457396caabd31dee +--- /dev/null ++++ b/drivers/net/wireless/w1/common/rf_d_adda_xmit_reg.h +@@ -0,0 +1,1583 @@ ++#ifdef RF_D_ADDA_XMIT_REG ++#else ++#define RF_D_ADDA_XMIT_REG ++ ++ ++#define RF_D_ADDA_XMIT_REG_BASE (0xa0e400) ++ ++#define RG_XMIT_A0 (RF_D_ADDA_XMIT_REG_BASE + 0x0) ++// Bit 31 :0 rg_xmit_cfg0 U RW default = 'h0 ++typedef union RG_XMIT_A0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_xmit_cfg0 : 32; ++ } b; ++} RG_XMIT_A0_FIELD_T; ++ ++#define RG_XMIT_A1 (RF_D_ADDA_XMIT_REG_BASE + 0x4) ++// Bit 31 :0 rg_xmit_cfg1 U RW default = 'h0 ++typedef union RG_XMIT_A1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_xmit_cfg1 : 32; ++ } b; ++} RG_XMIT_A1_FIELD_T; ++ ++#define RG_XMIT_A2 (RF_D_ADDA_XMIT_REG_BASE + 0x8) ++// Bit 24 :0 rg_tg1_f_sel U RW default = 'h200000 ++// Bit 28 :25 rg_tg1_tone_gain U RW default = 'h0 ++// Bit 29 rg_tg1_enable U RW default = 'h0 ++// Bit 30 rg_tg1_tone_40 U RW default = 'h0 ++// Bit 31 rg_tg1_tone_man_en U RW default = 'h1 ++typedef union RG_XMIT_A2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tg1_f_sel : 25; ++ unsigned int rg_tg1_tone_gain : 4; ++ unsigned int rg_tg1_enable : 1; ++ unsigned int rg_tg1_tone_40 : 1; ++ unsigned int rg_tg1_tone_man_en : 1; ++ } b; ++} RG_XMIT_A2_FIELD_T; ++ ++#define RG_XMIT_A3 (RF_D_ADDA_XMIT_REG_BASE + 0xc) ++// Bit 24 :0 rg_tg2_f_sel U RW default = 'h200000 ++// Bit 28 :25 rg_tg2_tone_gain U RW default = 'h0 ++// Bit 29 rg_tg2_enable U RW default = 'h0 ++// Bit 30 rg_tg2_tone_40 U RW default = 'h0 ++// Bit 31 rg_tg2_tone_man_en U RW default = 'h1 ++typedef union RG_XMIT_A3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tg2_f_sel : 25; ++ unsigned int rg_tg2_tone_gain : 4; ++ unsigned int rg_tg2_enable : 1; ++ unsigned int rg_tg2_tone_40 : 1; ++ unsigned int rg_tg2_tone_man_en : 1; ++ } b; ++} RG_XMIT_A3_FIELD_T; ++ ++#define RG_XMIT_A4 (RF_D_ADDA_XMIT_REG_BASE + 0x10) ++// Bit 1 :0 rg_tx_signal_sel U RW default = 'h0 ++// Bit 14 :4 rg_tx_const_i U RW default = 'h0 ++// Bit 26 :16 rg_tx_const_q U RW default = 'h0 ++// Bit 31 rg_tx_const_v U RW default = 'h0 ++typedef union RG_XMIT_A4_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_signal_sel : 2; ++ unsigned int rsvd_0 : 2; ++ unsigned int rg_tx_const_i : 11; ++ unsigned int rsvd_1 : 1; ++ unsigned int rg_tx_const_q : 11; ++ unsigned int rsvd_2 : 4; ++ unsigned int rg_tx_const_v : 1; ++ } b; ++} RG_XMIT_A4_FIELD_T; ++ ++#define RG_XMIT_A5 (RF_D_ADDA_XMIT_REG_BASE + 0x14) ++// Bit 31 :0 rg_tim_ratio U RW default = 'h0 ++typedef union RG_XMIT_A5_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tim_ratio : 32; ++ } b; ++} RG_XMIT_A5_FIELD_T; ++ ++#define RG_XMIT_A6 (RF_D_ADDA_XMIT_REG_BASE + 0x18) ++// Bit 7 :0 rg_txirr_comp_theta0 U RW default = 'h0 ++// Bit 15 :8 rg_txirr_comp_theta1 U RW default = 'h0 ++// Bit 23 :16 rg_txirr_comp_theta2 U RW default = 'h0 ++// Bit 31 :24 rg_txirr_comp_theta3 U RW default = 'h0 ++typedef union RG_XMIT_A6_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txirr_comp_theta0 : 8; ++ unsigned int rg_txirr_comp_theta1 : 8; ++ unsigned int rg_txirr_comp_theta2 : 8; ++ unsigned int rg_txirr_comp_theta3 : 8; ++ } b; ++} RG_XMIT_A6_FIELD_T; ++ ++#define RG_XMIT_A7 (RF_D_ADDA_XMIT_REG_BASE + 0x1c) ++// Bit 7 :0 rg_txirr_comp_theta4 U RW default = 'h0 ++// Bit 15 :8 rg_txirr_comp_theta5 U RW default = 'h0 ++// Bit 23 :16 rg_txirr_comp_theta6 U RW default = 'h0 ++// Bit 31 :24 rg_txirr_comp_theta7 U RW default = 'h0 ++typedef union RG_XMIT_A7_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txirr_comp_theta4 : 8; ++ unsigned int rg_txirr_comp_theta5 : 8; ++ unsigned int rg_txirr_comp_theta6 : 8; ++ unsigned int rg_txirr_comp_theta7 : 8; ++ } b; ++} RG_XMIT_A7_FIELD_T; ++ ++#define RG_XMIT_A8 (RF_D_ADDA_XMIT_REG_BASE + 0x20) ++// Bit 7 :0 rg_txirr_comp_theta8 U RW default = 'h0 ++// Bit 15 :8 rg_txirr_comp_theta9 U RW default = 'h0 ++// Bit 23 :16 rg_txirr_comp_thetaa U RW default = 'h0 ++// Bit 31 :24 rg_txirr_comp_thetab U RW default = 'h0 ++typedef union RG_XMIT_A8_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txirr_comp_theta8 : 8; ++ unsigned int rg_txirr_comp_theta9 : 8; ++ unsigned int rg_txirr_comp_thetaa : 8; ++ unsigned int rg_txirr_comp_thetab : 8; ++ } b; ++} RG_XMIT_A8_FIELD_T; ++ ++#define RG_XMIT_A9 (RF_D_ADDA_XMIT_REG_BASE + 0x24) ++// Bit 7 :0 rg_txirr_comp_thetac U RW default = 'h0 ++// Bit 15 :8 rg_txirr_comp_thetad U RW default = 'h0 ++// Bit 23 :16 rg_txirr_comp_thetae U RW default = 'h0 ++// Bit 31 :24 rg_txirr_comp_thetaf U RW default = 'h0 ++typedef union RG_XMIT_A9_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txirr_comp_thetac : 8; ++ unsigned int rg_txirr_comp_thetad : 8; ++ unsigned int rg_txirr_comp_thetae : 8; ++ unsigned int rg_txirr_comp_thetaf : 8; ++ } b; ++} RG_XMIT_A9_FIELD_T; ++ ++#define RG_XMIT_A10 (RF_D_ADDA_XMIT_REG_BASE + 0x28) ++// Bit 7 :0 rg_txirr_comp_alpha0 U RW default = 'h0 ++// Bit 15 :8 rg_txirr_comp_alpha1 U RW default = 'h0 ++// Bit 23 :16 rg_txirr_comp_alpha2 U RW default = 'h0 ++// Bit 31 :24 rg_txirr_comp_alpha3 U RW default = 'h0 ++typedef union RG_XMIT_A10_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txirr_comp_alpha0 : 8; ++ unsigned int rg_txirr_comp_alpha1 : 8; ++ unsigned int rg_txirr_comp_alpha2 : 8; ++ unsigned int rg_txirr_comp_alpha3 : 8; ++ } b; ++} RG_XMIT_A10_FIELD_T; ++ ++#define RG_XMIT_A11 (RF_D_ADDA_XMIT_REG_BASE + 0x2c) ++// Bit 7 :0 rg_txirr_comp_alpha4 U RW default = 'h0 ++// Bit 15 :8 rg_txirr_comp_alpha5 U RW default = 'h0 ++// Bit 23 :16 rg_txirr_comp_alpha6 U RW default = 'h0 ++// Bit 31 :24 rg_txirr_comp_alpha7 U RW default = 'h0 ++typedef union RG_XMIT_A11_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txirr_comp_alpha4 : 8; ++ unsigned int rg_txirr_comp_alpha5 : 8; ++ unsigned int rg_txirr_comp_alpha6 : 8; ++ unsigned int rg_txirr_comp_alpha7 : 8; ++ } b; ++} RG_XMIT_A11_FIELD_T; ++ ++#define RG_XMIT_A12 (RF_D_ADDA_XMIT_REG_BASE + 0x30) ++// Bit 7 :0 rg_txirr_comp_alpha8 U RW default = 'h0 ++// Bit 15 :8 rg_txirr_comp_alpha9 U RW default = 'h0 ++// Bit 23 :16 rg_txirr_comp_alphaa U RW default = 'h0 ++// Bit 31 :24 rg_txirr_comp_alphab U RW default = 'h0 ++typedef union RG_XMIT_A12_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txirr_comp_alpha8 : 8; ++ unsigned int rg_txirr_comp_alpha9 : 8; ++ unsigned int rg_txirr_comp_alphaa : 8; ++ unsigned int rg_txirr_comp_alphab : 8; ++ } b; ++} RG_XMIT_A12_FIELD_T; ++ ++#define RG_XMIT_A13 (RF_D_ADDA_XMIT_REG_BASE + 0x34) ++// Bit 7 :0 rg_txirr_comp_alphac U RW default = 'h0 ++// Bit 15 :8 rg_txirr_comp_alphad U RW default = 'h0 ++// Bit 23 :16 rg_txirr_comp_alphae U RW default = 'h0 ++// Bit 31 :24 rg_txirr_comp_alphaf U RW default = 'h0 ++typedef union RG_XMIT_A13_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txirr_comp_alphac : 8; ++ unsigned int rg_txirr_comp_alphad : 8; ++ unsigned int rg_txirr_comp_alphae : 8; ++ unsigned int rg_txirr_comp_alphaf : 8; ++ } b; ++} RG_XMIT_A13_FIELD_T; ++ ++#define RG_XMIT_A18 (RF_D_ADDA_XMIT_REG_BASE + 0x48) ++// Bit 24 :0 rg_tx_pwrlvl0 U RW default = 'h800000 ++typedef union RG_XMIT_A18_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_pwrlvl0 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_XMIT_A18_FIELD_T; ++ ++#define RG_XMIT_A19 (RF_D_ADDA_XMIT_REG_BASE + 0x4c) ++// Bit 24 :0 rg_tx_pwrlvl1 U RW default = 'h800000 ++typedef union RG_XMIT_A19_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_pwrlvl1 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_XMIT_A19_FIELD_T; ++ ++#define RG_XMIT_A20 (RF_D_ADDA_XMIT_REG_BASE + 0x50) ++// Bit 24 :0 rg_tx_pwrlvl2 U RW default = 'h800000 ++typedef union RG_XMIT_A20_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_pwrlvl2 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_XMIT_A20_FIELD_T; ++ ++#define RG_XMIT_A21 (RF_D_ADDA_XMIT_REG_BASE + 0x54) ++// Bit 24 :0 rg_tx_pwrlvl3 U RW default = 'h800000 ++typedef union RG_XMIT_A21_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_pwrlvl3 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_XMIT_A21_FIELD_T; ++ ++#define RG_XMIT_A22 (RF_D_ADDA_XMIT_REG_BASE + 0x58) ++// Bit 24 :0 rg_tx_pwrlvl4 U RW default = 'h800000 ++typedef union RG_XMIT_A22_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_pwrlvl4 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_XMIT_A22_FIELD_T; ++ ++#define RG_XMIT_A23 (RF_D_ADDA_XMIT_REG_BASE + 0x5c) ++// Bit 24 :0 rg_tx_pwrlvl5 U RW default = 'h800000 ++typedef union RG_XMIT_A23_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_pwrlvl5 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_XMIT_A23_FIELD_T; ++ ++#define RG_XMIT_A24 (RF_D_ADDA_XMIT_REG_BASE + 0x60) ++// Bit 24 :0 rg_tx_pwrlvl6 U RW default = 'h800000 ++typedef union RG_XMIT_A24_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_pwrlvl6 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_XMIT_A24_FIELD_T; ++ ++#define RG_XMIT_A25 (RF_D_ADDA_XMIT_REG_BASE + 0x64) ++// Bit 24 :0 rg_tx_pwrlvl7 U RW default = 'h800000 ++typedef union RG_XMIT_A25_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_pwrlvl7 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_XMIT_A25_FIELD_T; ++ ++#define RG_XMIT_A26 (RF_D_ADDA_XMIT_REG_BASE + 0x68) ++// Bit 24 :0 rg_tx_pwrlvl8 U RW default = 'h800000 ++typedef union RG_XMIT_A26_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_pwrlvl8 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_XMIT_A26_FIELD_T; ++ ++#define RG_XMIT_A27 (RF_D_ADDA_XMIT_REG_BASE + 0x6c) ++// Bit 24 :0 rg_tx_pwrlvl9 U RW default = 'h800000 ++typedef union RG_XMIT_A27_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_pwrlvl9 : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_XMIT_A27_FIELD_T; ++ ++#define RG_XMIT_A28 (RF_D_ADDA_XMIT_REG_BASE + 0x70) ++// Bit 24 :0 rg_tx_pwrlvla U RW default = 'h800000 ++typedef union RG_XMIT_A28_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_pwrlvla : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_XMIT_A28_FIELD_T; ++ ++#define RG_XMIT_A29 (RF_D_ADDA_XMIT_REG_BASE + 0x74) ++// Bit 24 :0 rg_tx_pwrlvlb U RW default = 'h800000 ++typedef union RG_XMIT_A29_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_pwrlvlb : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_XMIT_A29_FIELD_T; ++ ++#define RG_XMIT_A30 (RF_D_ADDA_XMIT_REG_BASE + 0x78) ++// Bit 24 :0 rg_tx_pwrlvlc U RW default = 'h800000 ++typedef union RG_XMIT_A30_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_pwrlvlc : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_XMIT_A30_FIELD_T; ++ ++#define RG_XMIT_A31 (RF_D_ADDA_XMIT_REG_BASE + 0x7c) ++// Bit 24 :0 rg_tx_pwrlvld U RW default = 'h800000 ++typedef union RG_XMIT_A31_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_pwrlvld : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_XMIT_A31_FIELD_T; ++ ++#define RG_XMIT_A32 (RF_D_ADDA_XMIT_REG_BASE + 0x80) ++// Bit 24 :0 rg_tx_pwrlvle U RW default = 'h800000 ++typedef union RG_XMIT_A32_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_pwrlvle : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_XMIT_A32_FIELD_T; ++ ++#define RG_XMIT_A33 (RF_D_ADDA_XMIT_REG_BASE + 0x84) ++// Bit 24 :0 rg_tx_pwrlvlf U RW default = 'h800000 ++typedef union RG_XMIT_A33_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_pwrlvlf : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_XMIT_A33_FIELD_T; ++ ++#define RG_XMIT_A34 (RF_D_ADDA_XMIT_REG_BASE + 0x88) ++// Bit 0 rg_tx_iqmm_bypass U RW default = 'h1 ++// Bit 4 rg_tx_negate_msb U RW default = 'h1 ++// Bit 8 rg_tx_iq_swap U RW default = 'h0 ++// Bit 13 :12 rg_tx_dout_sel U RW default = 'h0 ++// Bit 19 :16 rg_tx_async_wgap U RW default = 'ha ++typedef union RG_XMIT_A34_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_iqmm_bypass : 1; ++ unsigned int rsvd_0 : 3; ++ unsigned int rg_tx_negate_msb : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int rg_tx_iq_swap : 1; ++ unsigned int rsvd_2 : 3; ++ unsigned int rg_tx_dout_sel : 2; ++ unsigned int rsvd_3 : 2; ++ unsigned int rg_tx_async_wgap : 4; ++ unsigned int rsvd_4 : 12; ++ } b; ++} RG_XMIT_A34_FIELD_T; ++ ++#define RG_XMIT_A45 (RF_D_ADDA_XMIT_REG_BASE + 0xb4) ++// Bit 24 :0 rg_man_tx_pwrlvl U RW default = 'h800000 ++// Bit 31 rg_tx_pwr_sel_man_en U RW default = 'h0 ++typedef union RG_XMIT_A45_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_man_tx_pwrlvl : 25; ++ unsigned int rsvd_0 : 6; ++ unsigned int rg_tx_pwr_sel_man_en : 1; ++ } b; ++} RG_XMIT_A45_FIELD_T; ++ ++#define RG_XMIT_A46 (RF_D_ADDA_XMIT_REG_BASE + 0xb8) ++// Bit 7 :0 rg_man_txirr_comp_theta U RW default = 'h0 ++// Bit 15 :8 rg_man_txirr_comp_alpha U RW default = 'h0 ++// Bit 16 rg_txpwc_comp_man_sel U RW default = 'h1 ++// Bit 31 :24 rg_txpwc_comp_man U RW default = 'h80 ++typedef union RG_XMIT_A46_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_man_txirr_comp_theta : 8; ++ unsigned int rg_man_txirr_comp_alpha : 8; ++ unsigned int rg_txpwc_comp_man_sel : 1; ++ unsigned int rsvd_0 : 7; ++ unsigned int rg_txpwc_comp_man : 8; ++ } b; ++} RG_XMIT_A46_FIELD_T; ++ ++#define RG_XMIT_A47 (RF_D_ADDA_XMIT_REG_BASE + 0xbc) ++// Bit 15 :0 rg_tx_ex_gain0 U RW default = 'h9 ++// Bit 31 :16 rg_tx_ex_gain1 U RW default = 'ha ++typedef union RG_XMIT_A47_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_ex_gain0 : 16; ++ unsigned int rg_tx_ex_gain1 : 16; ++ } b; ++} RG_XMIT_A47_FIELD_T; ++ ++#define RG_XMIT_A48 (RF_D_ADDA_XMIT_REG_BASE + 0xd0) ++// Bit 15 :0 rg_tx_ex_gain2 U RW default = 'h9 ++// Bit 31 :16 rg_tx_ex_gain3 U RW default = 'ha ++typedef union RG_XMIT_A48_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_ex_gain2 : 16; ++ unsigned int rg_tx_ex_gain3 : 16; ++ } b; ++} RG_XMIT_A48_FIELD_T; ++ ++#define RG_XMIT_A49 (RF_D_ADDA_XMIT_REG_BASE + 0xd4) ++// Bit 15 :0 rg_tx_ex_gain4 U RW default = 'h9 ++// Bit 31 :16 rg_tx_ex_gain5 U RW default = 'ha ++typedef union RG_XMIT_A49_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_ex_gain4 : 16; ++ unsigned int rg_tx_ex_gain5 : 16; ++ } b; ++} RG_XMIT_A49_FIELD_T; ++ ++#define RG_XMIT_A50 (RF_D_ADDA_XMIT_REG_BASE + 0xd8) ++// Bit 15 :0 rg_tx_ex_gain6 U RW default = 'h9 ++// Bit 31 :16 rg_tx_ex_gain7 U RW default = 'ha ++typedef union RG_XMIT_A50_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_ex_gain6 : 16; ++ unsigned int rg_tx_ex_gain7 : 16; ++ } b; ++} RG_XMIT_A50_FIELD_T; ++ ++#define RG_XMIT_A51 (RF_D_ADDA_XMIT_REG_BASE + 0xdc) ++// Bit 15 :0 rg_tx_ex_gain8 U RW default = 'h9 ++// Bit 31 :16 rg_tx_ex_gain9 U RW default = 'ha ++typedef union RG_XMIT_A51_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_ex_gain8 : 16; ++ unsigned int rg_tx_ex_gain9 : 16; ++ } b; ++} RG_XMIT_A51_FIELD_T; ++ ++#define RG_XMIT_A52 (RF_D_ADDA_XMIT_REG_BASE + 0xe0) ++// Bit 15 :0 rg_tx_ex_gaina U RW default = 'h9 ++// Bit 31 :16 rg_tx_ex_gainb U RW default = 'ha ++typedef union RG_XMIT_A52_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_ex_gaina : 16; ++ unsigned int rg_tx_ex_gainb : 16; ++ } b; ++} RG_XMIT_A52_FIELD_T; ++ ++#define RG_XMIT_A53 (RF_D_ADDA_XMIT_REG_BASE + 0xe4) ++// Bit 15 :0 rg_tx_ex_gainc U RW default = 'h9 ++// Bit 31 :16 rg_tx_ex_gaind U RW default = 'ha ++typedef union RG_XMIT_A53_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_ex_gainc : 16; ++ unsigned int rg_tx_ex_gaind : 16; ++ } b; ++} RG_XMIT_A53_FIELD_T; ++ ++#define RG_XMIT_A54 (RF_D_ADDA_XMIT_REG_BASE + 0xe8) ++// Bit 15 :0 rg_tx_ex_gaine U RW default = 'h9 ++// Bit 31 :16 rg_tx_ex_gainf U RW default = 'ha ++typedef union RG_XMIT_A54_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_ex_gaine : 16; ++ unsigned int rg_tx_ex_gainf : 16; ++ } b; ++} RG_XMIT_A54_FIELD_T; ++ ++#define RG_XMIT_A55 (RF_D_ADDA_XMIT_REG_BASE + 0xec) ++// Bit 15 :0 rg_tx_gain U RW default = 'h0 ++// Bit 16 rg_tx_set U RW default = 'h0 ++typedef union RG_XMIT_A55_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_gain : 16; ++ unsigned int rg_tx_set : 1; ++ unsigned int rsvd_0 : 15; ++ } b; ++} RG_XMIT_A55_FIELD_T; ++ ++#define RG_XMIT_A56 (RF_D_ADDA_XMIT_REG_BASE + 0xf0) ++// Bit 7 :0 rg_txdpd_comp_in_gain U RW default = 'h80 ++// Bit 18 :8 rg_txdpd_comp_out_gain U RW default = 'h80 ++// Bit 24 rg_txdpd_comp_type U RW default = 'h1 ++// Bit 26 rg_txdpd_comp_bypass U RW default = 'h1 ++// Bit 28 rg_txdpd_comp_bypass_man U RW default = 'h1 ++// Bit 31 rg_txdpd_comp_coef_man_sel U RW default = 'h0 ++typedef union RG_XMIT_A56_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_in_gain : 8; ++ unsigned int rg_txdpd_comp_out_gain : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_type : 1; ++ unsigned int rsvd_1 : 1; ++ unsigned int rg_txdpd_comp_bypass : 1; ++ unsigned int rsvd_2 : 1; ++ unsigned int rg_txdpd_comp_bypass_man : 1; ++ unsigned int rsvd_3 : 2; ++ unsigned int rg_txdpd_comp_coef_man_sel : 1; ++ } b; ++} RG_XMIT_A56_FIELD_T; ++ ++#define RG_XMIT_A57 (RF_D_ADDA_XMIT_REG_BASE + 0xf4) ++// Bit 11 :0 rg_txdpd_comp_coef_i_0_man U RW default = 'hff9 ++// Bit 27 :16 rg_txdpd_comp_coef_q_0_man U RW default = 'h46 ++typedef union RG_XMIT_A57_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_coef_i_0_man : 12; ++ unsigned int rsvd_0 : 4; ++ unsigned int rg_txdpd_comp_coef_q_0_man : 12; ++ unsigned int rsvd_1 : 4; ++ } b; ++} RG_XMIT_A57_FIELD_T; ++ ++#define RG_XMIT_A58 (RF_D_ADDA_XMIT_REG_BASE + 0xf8) ++// Bit 11 :0 rg_txdpd_comp_coef_i_1_man U RW default = 'hff8 ++// Bit 27 :16 rg_txdpd_comp_coef_q_1_man U RW default = 'h13 ++typedef union RG_XMIT_A58_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_coef_i_1_man : 12; ++ unsigned int rsvd_0 : 4; ++ unsigned int rg_txdpd_comp_coef_q_1_man : 12; ++ unsigned int rsvd_1 : 4; ++ } b; ++} RG_XMIT_A58_FIELD_T; ++ ++#define RG_XMIT_A59 (RF_D_ADDA_XMIT_REG_BASE + 0xfc) ++// Bit 11 :0 rg_txdpd_comp_coef_i_2_man U RW default = 'h10 ++// Bit 27 :16 rg_txdpd_comp_coef_q_2_man U RW default = 'h8 ++typedef union RG_XMIT_A59_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_coef_i_2_man : 12; ++ unsigned int rsvd_0 : 4; ++ unsigned int rg_txdpd_comp_coef_q_2_man : 12; ++ unsigned int rsvd_1 : 4; ++ } b; ++} RG_XMIT_A59_FIELD_T; ++ ++#define RG_XMIT_A60 (RF_D_ADDA_XMIT_REG_BASE + 0x100) ++// Bit 11 :0 rg_txdpd_comp_coef_i_3_man U RW default = 'he ++// Bit 27 :16 rg_txdpd_comp_coef_q_3_man U RW default = 'h93 ++typedef union RG_XMIT_A60_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_coef_i_3_man : 12; ++ unsigned int rsvd_0 : 4; ++ unsigned int rg_txdpd_comp_coef_q_3_man : 12; ++ unsigned int rsvd_1 : 4; ++ } b; ++} RG_XMIT_A60_FIELD_T; ++ ++#define RG_XMIT_A61 (RF_D_ADDA_XMIT_REG_BASE + 0x104) ++// Bit 11 :0 rg_txdpd_comp_coef_i_4_man U RW default = 'h16 ++// Bit 27 :16 rg_txdpd_comp_coef_q_4_man U RW default = 'h1f ++typedef union RG_XMIT_A61_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_coef_i_4_man : 12; ++ unsigned int rsvd_0 : 4; ++ unsigned int rg_txdpd_comp_coef_q_4_man : 12; ++ unsigned int rsvd_1 : 4; ++ } b; ++} RG_XMIT_A61_FIELD_T; ++ ++#define RG_XMIT_A62 (RF_D_ADDA_XMIT_REG_BASE + 0x108) ++// Bit 11 :0 rg_txdpd_comp_coef_i_5_man U RW default = 'hfe1 ++// Bit 27 :16 rg_txdpd_comp_coef_q_5_man U RW default = 'hff9 ++typedef union RG_XMIT_A62_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_coef_i_5_man : 12; ++ unsigned int rsvd_0 : 4; ++ unsigned int rg_txdpd_comp_coef_q_5_man : 12; ++ unsigned int rsvd_1 : 4; ++ } b; ++} RG_XMIT_A62_FIELD_T; ++ ++#define RG_XMIT_A63 (RF_D_ADDA_XMIT_REG_BASE + 0x10c) ++// Bit 11 :0 rg_txdpd_comp_coef_i_6_man U RW default = 'hf79 ++// Bit 27 :16 rg_txdpd_comp_coef_q_6_man U RW default = 'hc7f ++typedef union RG_XMIT_A63_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_coef_i_6_man : 12; ++ unsigned int rsvd_0 : 4; ++ unsigned int rg_txdpd_comp_coef_q_6_man : 12; ++ unsigned int rsvd_1 : 4; ++ } b; ++} RG_XMIT_A63_FIELD_T; ++ ++#define RG_XMIT_A64 (RF_D_ADDA_XMIT_REG_BASE + 0x110) ++// Bit 11 :0 rg_txdpd_comp_coef_i_7_man U RW default = 'h9 ++// Bit 27 :16 rg_txdpd_comp_coef_q_7_man U RW default = 'hf51 ++typedef union RG_XMIT_A64_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_coef_i_7_man : 12; ++ unsigned int rsvd_0 : 4; ++ unsigned int rg_txdpd_comp_coef_q_7_man : 12; ++ unsigned int rsvd_1 : 4; ++ } b; ++} RG_XMIT_A64_FIELD_T; ++ ++#define RG_XMIT_A65 (RF_D_ADDA_XMIT_REG_BASE + 0x114) ++// Bit 11 :0 rg_txdpd_comp_coef_i_8_man U RW default = 'hff1 ++// Bit 27 :16 rg_txdpd_comp_coef_q_8_man U RW default = 'h27 ++typedef union RG_XMIT_A65_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_coef_i_8_man : 12; ++ unsigned int rsvd_0 : 4; ++ unsigned int rg_txdpd_comp_coef_q_8_man : 12; ++ unsigned int rsvd_1 : 4; ++ } b; ++} RG_XMIT_A65_FIELD_T; ++ ++#define RG_XMIT_A66 (RF_D_ADDA_XMIT_REG_BASE + 0x118) ++// Bit 11 :0 rg_txdpd_comp_coef_i_9_man U RW default = 'hfeb ++// Bit 27 :16 rg_txdpd_comp_coef_q_9_man U RW default = 'hf4d ++typedef union RG_XMIT_A66_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_coef_i_9_man : 12; ++ unsigned int rsvd_0 : 4; ++ unsigned int rg_txdpd_comp_coef_q_9_man : 12; ++ unsigned int rsvd_1 : 4; ++ } b; ++} RG_XMIT_A66_FIELD_T; ++ ++#define RG_XMIT_A67 (RF_D_ADDA_XMIT_REG_BASE + 0x11c) ++// Bit 11 :0 rg_txdpd_comp_coef_i_a_man U RW default = 'h5 ++// Bit 27 :16 rg_txdpd_comp_coef_q_a_man U RW default = 'hfe4 ++typedef union RG_XMIT_A67_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_coef_i_a_man : 12; ++ unsigned int rsvd_0 : 4; ++ unsigned int rg_txdpd_comp_coef_q_a_man : 12; ++ unsigned int rsvd_1 : 4; ++ } b; ++} RG_XMIT_A67_FIELD_T; ++ ++#define RG_XMIT_A68 (RF_D_ADDA_XMIT_REG_BASE + 0x120) ++// Bit 11 :0 rg_txdpd_comp_coef_i_b_man U RW default = 'h6 ++// Bit 27 :16 rg_txdpd_comp_coef_q_b_man U RW default = 'hfee ++typedef union RG_XMIT_A68_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_coef_i_b_man : 12; ++ unsigned int rsvd_0 : 4; ++ unsigned int rg_txdpd_comp_coef_q_b_man : 12; ++ unsigned int rsvd_1 : 4; ++ } b; ++} RG_XMIT_A68_FIELD_T; ++ ++#define RG_XMIT_A69 (RF_D_ADDA_XMIT_REG_BASE + 0x124) ++// Bit 11 :0 rg_txdpd_comp_coef_i_c_man U RW default = 'h17 ++// Bit 27 :16 rg_txdpd_comp_coef_q_c_man U RW default = 'ha3 ++typedef union RG_XMIT_A69_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_coef_i_c_man : 12; ++ unsigned int rsvd_0 : 4; ++ unsigned int rg_txdpd_comp_coef_q_c_man : 12; ++ unsigned int rsvd_1 : 4; ++ } b; ++} RG_XMIT_A69_FIELD_T; ++ ++#define RG_XMIT_A70 (RF_D_ADDA_XMIT_REG_BASE + 0x128) ++// Bit 11 :0 rg_txdpd_comp_coef_i_d_man U RW default = 'hffc ++// Bit 27 :16 rg_txdpd_comp_coef_q_d_man U RW default = 'h16 ++typedef union RG_XMIT_A70_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_coef_i_d_man : 12; ++ unsigned int rsvd_0 : 4; ++ unsigned int rg_txdpd_comp_coef_q_d_man : 12; ++ unsigned int rsvd_1 : 4; ++ } b; ++} RG_XMIT_A70_FIELD_T; ++ ++#define RG_XMIT_A71 (RF_D_ADDA_XMIT_REG_BASE + 0x12c) ++// Bit 11 :0 rg_txdpd_comp_coef_i_e_man U RW default = 'hfff ++// Bit 27 :16 rg_txdpd_comp_coef_q_e_man U RW default = 'h5 ++typedef union RG_XMIT_A71_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_coef_i_e_man : 12; ++ unsigned int rsvd_0 : 4; ++ unsigned int rg_txdpd_comp_coef_q_e_man : 12; ++ unsigned int rsvd_1 : 4; ++ } b; ++} RG_XMIT_A71_FIELD_T; ++ ++#define RG_XMIT_A72 (RF_D_ADDA_XMIT_REG_BASE + 0x130) ++// Bit 12 :0 rg_txdpd_comp_low_thresh U RW default = 'hcd ++// Bit 28 :16 rg_txdpd_comp_high_thresh U RW default = 'h1000 ++typedef union RG_XMIT_A72_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_low_thresh : 13; ++ unsigned int rsvd_0 : 3; ++ unsigned int rg_txdpd_comp_high_thresh : 13; ++ unsigned int rsvd_1 : 3; ++ } b; ++} RG_XMIT_A72_FIELD_T; ++ ++#define RG_XMIT_A73 (RF_D_ADDA_XMIT_REG_BASE + 0x134) ++// Bit 10 :0 rg_txdpd_comp_lut_00_i U RW default = 'h101 ++// Bit 26 :16 rg_txdpd_comp_lut_00_q U RW default = 'h0 ++typedef union RG_XMIT_A73_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_00_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_00_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A73_FIELD_T; ++ ++#define RG_XMIT_A74 (RF_D_ADDA_XMIT_REG_BASE + 0x138) ++// Bit 10 :0 rg_txdpd_comp_lut_01_i U RW default = 'hfb ++// Bit 26 :16 rg_txdpd_comp_lut_01_q U RW default = 'h7fe ++typedef union RG_XMIT_A74_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_01_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_01_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A74_FIELD_T; ++ ++#define RG_XMIT_A75 (RF_D_ADDA_XMIT_REG_BASE + 0x13c) ++// Bit 10 :0 rg_txdpd_comp_lut_02_i U RW default = 'hf5 ++// Bit 26 :16 rg_txdpd_comp_lut_02_q U RW default = 'h7fb ++typedef union RG_XMIT_A75_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_02_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_02_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A75_FIELD_T; ++ ++#define RG_XMIT_A76 (RF_D_ADDA_XMIT_REG_BASE + 0x140) ++// Bit 10 :0 rg_txdpd_comp_lut_03_i U RW default = 'hf2 ++// Bit 26 :16 rg_txdpd_comp_lut_03_q U RW default = 'h7fb ++typedef union RG_XMIT_A76_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_03_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_03_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A76_FIELD_T; ++ ++#define RG_XMIT_A77 (RF_D_ADDA_XMIT_REG_BASE + 0x144) ++// Bit 10 :0 rg_txdpd_comp_lut_04_i U RW default = 'hf2 ++// Bit 26 :16 rg_txdpd_comp_lut_04_q U RW default = 'h7fe ++typedef union RG_XMIT_A77_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_04_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_04_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A77_FIELD_T; ++ ++#define RG_XMIT_A78 (RF_D_ADDA_XMIT_REG_BASE + 0x148) ++// Bit 10 :0 rg_txdpd_comp_lut_05_i U RW default = 'hf0 ++// Bit 26 :16 rg_txdpd_comp_lut_05_q U RW default = 'h0 ++typedef union RG_XMIT_A78_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_05_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_05_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A78_FIELD_T; ++ ++#define RG_XMIT_A79 (RF_D_ADDA_XMIT_REG_BASE + 0x14c) ++// Bit 10 :0 rg_txdpd_comp_lut_06_i U RW default = 'hee ++// Bit 26 :16 rg_txdpd_comp_lut_06_q U RW default = 'h2 ++typedef union RG_XMIT_A79_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_06_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_06_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A79_FIELD_T; ++ ++#define RG_XMIT_A80 (RF_D_ADDA_XMIT_REG_BASE + 0x150) ++// Bit 10 :0 rg_txdpd_comp_lut_07_i U RW default = 'heb ++// Bit 26 :16 rg_txdpd_comp_lut_07_q U RW default = 'h4 ++typedef union RG_XMIT_A80_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_07_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_07_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A80_FIELD_T; ++ ++#define RG_XMIT_A81 (RF_D_ADDA_XMIT_REG_BASE + 0x154) ++// Bit 10 :0 rg_txdpd_comp_lut_08_i U RW default = 'he8 ++// Bit 26 :16 rg_txdpd_comp_lut_08_q U RW default = 'h5 ++typedef union RG_XMIT_A81_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_08_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_08_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A81_FIELD_T; ++ ++#define RG_XMIT_A82 (RF_D_ADDA_XMIT_REG_BASE + 0x158) ++// Bit 10 :0 rg_txdpd_comp_lut_09_i U RW default = 'he6 ++// Bit 26 :16 rg_txdpd_comp_lut_09_q U RW default = 'h6 ++typedef union RG_XMIT_A82_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_09_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_09_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A82_FIELD_T; ++ ++#define RG_XMIT_A83 (RF_D_ADDA_XMIT_REG_BASE + 0x15c) ++// Bit 10 :0 rg_txdpd_comp_lut_10_i U RW default = 'he4 ++// Bit 26 :16 rg_txdpd_comp_lut_10_q U RW default = 'h7 ++typedef union RG_XMIT_A83_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_10_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_10_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A83_FIELD_T; ++ ++#define RG_XMIT_A84 (RF_D_ADDA_XMIT_REG_BASE + 0x160) ++// Bit 10 :0 rg_txdpd_comp_lut_11_i U RW default = 'he4 ++// Bit 26 :16 rg_txdpd_comp_lut_11_q U RW default = 'h8 ++typedef union RG_XMIT_A84_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_11_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_11_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A84_FIELD_T; ++ ++#define RG_XMIT_A85 (RF_D_ADDA_XMIT_REG_BASE + 0x164) ++// Bit 10 :0 rg_txdpd_comp_lut_12_i U RW default = 'he6 ++// Bit 26 :16 rg_txdpd_comp_lut_12_q U RW default = 'h9 ++typedef union RG_XMIT_A85_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_12_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_12_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A85_FIELD_T; ++ ++#define RG_XMIT_A86 (RF_D_ADDA_XMIT_REG_BASE + 0x168) ++// Bit 10 :0 rg_txdpd_comp_lut_13_i U RW default = 'hea ++// Bit 26 :16 rg_txdpd_comp_lut_13_q U RW default = 'h9 ++typedef union RG_XMIT_A86_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_13_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_13_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A86_FIELD_T; ++ ++#define RG_XMIT_A87 (RF_D_ADDA_XMIT_REG_BASE + 0x16c) ++// Bit 10 :0 rg_txdpd_comp_lut_14_i U RW default = 'hef ++// Bit 26 :16 rg_txdpd_comp_lut_14_q U RW default = 'h8 ++typedef union RG_XMIT_A87_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_14_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_14_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A87_FIELD_T; ++ ++#define RG_XMIT_A88 (RF_D_ADDA_XMIT_REG_BASE + 0x170) ++// Bit 10 :0 rg_txdpd_comp_lut_15_i U RW default = 'hf6 ++// Bit 26 :16 rg_txdpd_comp_lut_15_q U RW default = 'h7 ++typedef union RG_XMIT_A88_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_15_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_15_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A88_FIELD_T; ++ ++#define RG_XMIT_A89 (RF_D_ADDA_XMIT_REG_BASE + 0x174) ++// Bit 10 :0 rg_txdpd_comp_lut_16_i U RW default = 'hfe ++// Bit 26 :16 rg_txdpd_comp_lut_16_q U RW default = 'h5 ++typedef union RG_XMIT_A89_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_16_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_16_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A89_FIELD_T; ++ ++#define RG_XMIT_A90 (RF_D_ADDA_XMIT_REG_BASE + 0x178) ++// Bit 10 :0 rg_txdpd_comp_lut_17_i U RW default = 'h108 ++// Bit 26 :16 rg_txdpd_comp_lut_17_q U RW default = 'h2 ++typedef union RG_XMIT_A90_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_17_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_17_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A90_FIELD_T; ++ ++#define RG_XMIT_A91 (RF_D_ADDA_XMIT_REG_BASE + 0x17c) ++// Bit 10 :0 rg_txdpd_comp_lut_18_i U RW default = 'h113 ++// Bit 26 :16 rg_txdpd_comp_lut_18_q U RW default = 'h7ff ++typedef union RG_XMIT_A91_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_18_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_18_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A91_FIELD_T; ++ ++#define RG_XMIT_A92 (RF_D_ADDA_XMIT_REG_BASE + 0x180) ++// Bit 10 :0 rg_txdpd_comp_lut_19_i U RW default = 'h11e ++// Bit 26 :16 rg_txdpd_comp_lut_19_q U RW default = 'h7fd ++typedef union RG_XMIT_A92_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_19_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_19_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A92_FIELD_T; ++ ++#define RG_XMIT_A93 (RF_D_ADDA_XMIT_REG_BASE + 0x184) ++// Bit 10 :0 rg_txdpd_comp_lut_20_i U RW default = 'h129 ++// Bit 26 :16 rg_txdpd_comp_lut_20_q U RW default = 'h7fa ++typedef union RG_XMIT_A93_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_20_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_20_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A93_FIELD_T; ++ ++#define RG_XMIT_A94 (RF_D_ADDA_XMIT_REG_BASE + 0x188) ++// Bit 10 :0 rg_txdpd_comp_lut_21_i U RW default = 'h135 ++// Bit 26 :16 rg_txdpd_comp_lut_21_q U RW default = 'h7f7 ++typedef union RG_XMIT_A94_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_21_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_21_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A94_FIELD_T; ++ ++#define RG_XMIT_A95 (RF_D_ADDA_XMIT_REG_BASE + 0x18c) ++// Bit 10 :0 rg_txdpd_comp_lut_22_i U RW default = 'h140 ++// Bit 26 :16 rg_txdpd_comp_lut_22_q U RW default = 'h7f4 ++typedef union RG_XMIT_A95_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_22_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_22_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A95_FIELD_T; ++ ++#define RG_XMIT_A96 (RF_D_ADDA_XMIT_REG_BASE + 0x190) ++// Bit 10 :0 rg_txdpd_comp_lut_23_i U RW default = 'h14b ++// Bit 26 :16 rg_txdpd_comp_lut_23_q U RW default = 'h7f1 ++typedef union RG_XMIT_A96_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_23_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_23_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A96_FIELD_T; ++ ++#define RG_XMIT_A97 (RF_D_ADDA_XMIT_REG_BASE + 0x194) ++// Bit 10 :0 rg_txdpd_comp_lut_24_i U RW default = 'h157 ++// Bit 26 :16 rg_txdpd_comp_lut_24_q U RW default = 'h7ee ++typedef union RG_XMIT_A97_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_24_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_24_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A97_FIELD_T; ++ ++#define RG_XMIT_A98 (RF_D_ADDA_XMIT_REG_BASE + 0x198) ++// Bit 10 :0 rg_txdpd_comp_lut_25_i U RW default = 'h163 ++// Bit 26 :16 rg_txdpd_comp_lut_25_q U RW default = 'h7ec ++typedef union RG_XMIT_A98_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_25_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_25_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A98_FIELD_T; ++ ++#define RG_XMIT_A99 (RF_D_ADDA_XMIT_REG_BASE + 0x19c) ++// Bit 10 :0 rg_txdpd_comp_lut_26_i U RW default = 'h170 ++// Bit 26 :16 rg_txdpd_comp_lut_26_q U RW default = 'h7e9 ++typedef union RG_XMIT_A99_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_26_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_26_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A99_FIELD_T; ++ ++#define RG_XMIT_A100 (RF_D_ADDA_XMIT_REG_BASE + 0x1a0) ++// Bit 10 :0 rg_txdpd_comp_lut_27_i U RW default = 'h17b ++// Bit 26 :16 rg_txdpd_comp_lut_27_q U RW default = 'h7e6 ++typedef union RG_XMIT_A100_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_27_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_27_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A100_FIELD_T; ++ ++#define RG_XMIT_A101 (RF_D_ADDA_XMIT_REG_BASE + 0x1a4) ++// Bit 10 :0 rg_txdpd_comp_lut_28_i U RW default = 'h185 ++// Bit 26 :16 rg_txdpd_comp_lut_28_q U RW default = 'h7e2 ++typedef union RG_XMIT_A101_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_28_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_28_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A101_FIELD_T; ++ ++#define RG_XMIT_A102 (RF_D_ADDA_XMIT_REG_BASE + 0x1a8) ++// Bit 10 :0 rg_txdpd_comp_lut_29_i U RW default = 'h18d ++// Bit 26 :16 rg_txdpd_comp_lut_29_q U RW default = 'h7df ++typedef union RG_XMIT_A102_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_29_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_29_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A102_FIELD_T; ++ ++#define RG_XMIT_A103 (RF_D_ADDA_XMIT_REG_BASE + 0x1ac) ++// Bit 10 :0 rg_txdpd_comp_lut_30_i U RW default = 'h199 ++// Bit 26 :16 rg_txdpd_comp_lut_30_q U RW default = 'h7dc ++typedef union RG_XMIT_A103_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_30_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_30_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A103_FIELD_T; ++ ++#define RG_XMIT_A104 (RF_D_ADDA_XMIT_REG_BASE + 0x1b0) ++// Bit 10 :0 rg_txdpd_comp_lut_31_i U RW default = 'h1ad ++// Bit 26 :16 rg_txdpd_comp_lut_31_q U RW default = 'h7da ++typedef union RG_XMIT_A104_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_31_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_31_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A104_FIELD_T; ++ ++#define RG_XMIT_A105 (RF_D_ADDA_XMIT_REG_BASE + 0x1b4) ++// Bit 12 :0 rg_txdpd_comp_high_thresh_recip U RW default = 'h10d ++// Bit 30 :16 rg_txdpd_coef_update_en U RW default = 'h7fff ++typedef union RG_XMIT_A105_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_high_thresh_recip : 13; ++ unsigned int rsvd_0 : 3; ++ unsigned int rg_txdpd_coef_update_en : 15; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_XMIT_A105_FIELD_T; ++ ++#define RG_XMIT_A106 (RF_D_ADDA_XMIT_REG_BASE + 0x1b8) ++// Bit 7 :0 rg_tx_atten_factor U RW default = 'h8 ++// Bit 8 rg_tx_atten_factor_man_mode U RW default = 'h1 ++typedef union RG_XMIT_A106_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_atten_factor : 8; ++ unsigned int rg_tx_atten_factor_man_mode : 1; ++ unsigned int rsvd_0 : 23; ++ } b; ++} RG_XMIT_A106_FIELD_T; ++ ++#define RG_XMIT_A107 (RF_D_ADDA_XMIT_REG_BASE + 0x1bc) ++// Bit 7 :0 rg_tx_coeff_20m_0 U RW default = 'hfb ++// Bit 15 :8 rg_tx_coeff_20m_1 U RW default = 'hfb ++// Bit 23 :16 rg_tx_coeff_20m_2 U RW default = 'h2 ++// Bit 31 :24 rg_tx_coeff_20m_3 U RW default = 'h11 ++typedef union RG_XMIT_A107_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_coeff_20m_0 : 8; ++ unsigned int rg_tx_coeff_20m_1 : 8; ++ unsigned int rg_tx_coeff_20m_2 : 8; ++ unsigned int rg_tx_coeff_20m_3 : 8; ++ } b; ++} RG_XMIT_A107_FIELD_T; ++ ++#define RG_XMIT_A108 (RF_D_ADDA_XMIT_REG_BASE + 0x1c0) ++// Bit 7 :0 rg_tx_coeff_20m_4 U RW default = 'h25 ++// Bit 15 :8 rg_tx_coeff_20m_5 U RW default = 'h37 ++// Bit 23 :16 rg_tx_coeff_20m_6 U RW default = 'h3e ++typedef union RG_XMIT_A108_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_coeff_20m_4 : 8; ++ unsigned int rg_tx_coeff_20m_5 : 8; ++ unsigned int rg_tx_coeff_20m_6 : 8; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_XMIT_A108_FIELD_T; ++ ++#define RG_XMIT_A109 (RF_D_ADDA_XMIT_REG_BASE + 0x1c4) ++// Bit 7 :0 rg_tx_coeff_40m_0 U RW default = 'h2 ++// Bit 15 :8 rg_tx_coeff_40m_1 U RW default = 'hfc ++// Bit 23 :16 rg_tx_coeff_40m_2 U RW default = 'hf3 ++// Bit 31 :24 rg_tx_coeff_40m_3 U RW default = 'hf8 ++typedef union RG_XMIT_A109_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_coeff_40m_0 : 8; ++ unsigned int rg_tx_coeff_40m_1 : 8; ++ unsigned int rg_tx_coeff_40m_2 : 8; ++ unsigned int rg_tx_coeff_40m_3 : 8; ++ } b; ++} RG_XMIT_A109_FIELD_T; ++ ++#define RG_XMIT_A110 (RF_D_ADDA_XMIT_REG_BASE + 0x1c8) ++// Bit 7 :0 rg_tx_coeff_40m_4 U RW default = 'h1a ++// Bit 15 :8 rg_tx_coeff_40m_5 U RW default = 'h49 ++// Bit 23 :16 rg_tx_coeff_40m_6 U RW default = 'h60 ++typedef union RG_XMIT_A110_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_coeff_40m_4 : 8; ++ unsigned int rg_tx_coeff_40m_5 : 8; ++ unsigned int rg_tx_coeff_40m_6 : 8; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_XMIT_A110_FIELD_T; ++ ++#define RG_XMIT_A111 (RF_D_ADDA_XMIT_REG_BASE + 0x1cc) ++// Bit 1 :0 rg_txirr_theta_step U RW default = 'h0 ++typedef union RG_XMIT_A111_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txirr_theta_step : 2; ++ unsigned int rsvd_0 : 30; ++ } b; ++} RG_XMIT_A111_FIELD_T; ++ ++#define RG_XMIT_A112 (RF_D_ADDA_XMIT_REG_BASE + 0x1d0) ++// Bit 7 :0 rg_tx_atten_factor0 U RW default = 'h8 ++// Bit 15 :8 rg_tx_atten_factor1 U RW default = 'h8 ++// Bit 23 :16 rg_tx_atten_factor2 U RW default = 'h8 ++// Bit 31 :24 rg_tx_atten_factor3 U RW default = 'h8 ++typedef union RG_XMIT_A112_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_atten_factor0 : 8; ++ unsigned int rg_tx_atten_factor1 : 8; ++ unsigned int rg_tx_atten_factor2 : 8; ++ unsigned int rg_tx_atten_factor3 : 8; ++ } b; ++} RG_XMIT_A112_FIELD_T; ++ ++#define RG_XMIT_A113 (RF_D_ADDA_XMIT_REG_BASE + 0x1d4) ++// Bit 7 :0 rg_tx_atten_factor4 U RW default = 'h8 ++// Bit 15 :8 rg_tx_atten_factor5 U RW default = 'h8 ++// Bit 23 :16 rg_tx_atten_factor6 U RW default = 'h8 ++// Bit 31 :24 rg_tx_atten_factor7 U RW default = 'h8 ++typedef union RG_XMIT_A113_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_atten_factor4 : 8; ++ unsigned int rg_tx_atten_factor5 : 8; ++ unsigned int rg_tx_atten_factor6 : 8; ++ unsigned int rg_tx_atten_factor7 : 8; ++ } b; ++} RG_XMIT_A113_FIELD_T; ++ ++#define RG_XMIT_A114 (RF_D_ADDA_XMIT_REG_BASE + 0x1d8) ++// Bit 7 :0 rg_tx_atten_factor8 U RW default = 'h8 ++// Bit 15 :8 rg_tx_atten_factor9 U RW default = 'h8 ++// Bit 23 :16 rg_tx_atten_factora U RW default = 'h8 ++// Bit 31 :24 rg_tx_atten_factorb U RW default = 'h8 ++typedef union RG_XMIT_A114_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_atten_factor8 : 8; ++ unsigned int rg_tx_atten_factor9 : 8; ++ unsigned int rg_tx_atten_factora : 8; ++ unsigned int rg_tx_atten_factorb : 8; ++ } b; ++} RG_XMIT_A114_FIELD_T; ++ ++#define RG_XMIT_A115 (RF_D_ADDA_XMIT_REG_BASE + 0x1dc) ++// Bit 7 :0 rg_tx_atten_factorc U RW default = 'h8 ++// Bit 15 :8 rg_tx_atten_factord U RW default = 'h8 ++// Bit 23 :16 rg_tx_atten_factore U RW default = 'h8 ++// Bit 31 :24 rg_tx_atten_factorf U RW default = 'h8 ++typedef union RG_XMIT_A115_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_tx_atten_factorc : 8; ++ unsigned int rg_tx_atten_factord : 8; ++ unsigned int rg_tx_atten_factore : 8; ++ unsigned int rg_tx_atten_factorf : 8; ++ } b; ++} RG_XMIT_A115_FIELD_T; ++ ++#define RG_XMIT_A116 (RF_D_ADDA_XMIT_REG_BASE + 0x1e0) ++// Bit 10 :0 rg_txdpd_comp_lut_32_i U RW default = 'h0 ++// Bit 26 :16 rg_txdpd_comp_lut_32_q U RW default = 'h0 ++typedef union RG_XMIT_A116_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_txdpd_comp_lut_32_i : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_txdpd_comp_lut_32_q : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A116_FIELD_T; ++ ++#define RG_XMIT_A117 (RF_D_ADDA_XMIT_REG_BASE + 0x1e4) ++// Bit 10 :0 rg_trig_wave_min U RW default = 'h401 ++// Bit 26 :16 rg_trig_wave_max U RW default = 'h3ff ++typedef union RG_XMIT_A117_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_trig_wave_min : 11; ++ unsigned int rsvd_0 : 5; ++ unsigned int rg_trig_wave_max : 11; ++ unsigned int rsvd_1 : 5; ++ } b; ++} RG_XMIT_A117_FIELD_T; ++ ++#define RG_XMIT_A118 (RF_D_ADDA_XMIT_REG_BASE + 0x1e8) ++// Bit 10 :0 rg_trig_wave_step U RW default = 'h5 ++// Bit 27 :12 rg_trig_wave_length U RW default = 'h2 ++// Bit 30 rg_trig_wave_q_hold U RW default = 'h0 ++// Bit 31 rg_trig_wave_en U RW default = 'h0 ++typedef union RG_XMIT_A118_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_trig_wave_step : 11; ++ unsigned int rsvd_0 : 1; ++ unsigned int rg_trig_wave_length : 16; ++ unsigned int rsvd_1 : 2; ++ unsigned int rg_trig_wave_q_hold : 1; ++ unsigned int rg_trig_wave_en : 1; ++ } b; ++} RG_XMIT_A118_FIELD_T; ++ ++#define RG_XMIT_A119 (RF_D_ADDA_XMIT_REG_BASE + 0x1ec) ++// Bit 0 rg_const_sel U RW default = 'h0 ++typedef union RG_XMIT_A119_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_const_sel : 1; ++ unsigned int rsvd_0 : 31; ++ } b; ++} RG_XMIT_A119_FIELD_T; ++ ++#endif ++ +diff --git a/drivers/net/wireless/w1/common/rf_d_rx_reg.h b/drivers/net/wireless/w1/common/rf_d_rx_reg.h +new file mode 100644 +index 0000000000000000000000000000000000000000..f17b5c0212c7ab6c7a41ef3daf5d3d124758a163 +--- /dev/null ++++ b/drivers/net/wireless/w1/common/rf_d_rx_reg.h +@@ -0,0 +1,2486 @@ ++#ifdef RF_D_RX_REG ++#else ++#define RF_D_RX_REG ++ ++ ++#define RF_D_RX_REG_BASE (0xc00) ++ ++#define RG_RX_A0 (RF_D_RX_REG_BASE + 0x0) ++// Bit 31 :0 rg_wf_rx_dig_rsv0 U RW default = 'hffff ++typedef union RG_RX_A0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_DIG_RSV0 : 32; ++ } b; ++} RG_RX_A0_FIELD_T; ++ ++#define RG_RX_A1 (RF_D_RX_REG_BASE + 0x4) ++// Bit 31 :0 rg_wf_rx_dig_rsv1 U RW default = 'hffff ++typedef union RG_RX_A1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_DIG_RSV1 : 32; ++ } b; ++} RG_RX_A1_FIELD_T; ++ ++#define RG_RX_A2 (RF_D_RX_REG_BASE + 0x8) ++// Bit 0 rg_wf_rx_bbbm_man_mode U RW default = 'h0 ++// Bit 3 :2 rg_wf_rx_bw_sel U RW default = 'h0 ++// Bit 4 rg_wf_rx_adcfs_sel U RW default = 'h0 ++// Bit 15 :8 rg_wf_rx_gain_man U RW default = 'h9c ++// Bit 16 rg_wf_rx_gain_man_mode U RW default = 'h0 ++// Bit 23 :20 rg_wf_rx_osc_freq U RW default = 'h5 ++typedef union RG_RX_A2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_BBBM_MAN_MODE : 1; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF_RX_BW_SEL : 2; ++ unsigned int RG_WF_RX_ADCFS_SEL : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int RG_WF_RX_GAIN_MAN : 8; ++ unsigned int RG_WF_RX_GAIN_MAN_MODE : 1; ++ unsigned int rsvd_2 : 3; ++ unsigned int RG_WF_RX_OSC_FREQ : 4; ++ unsigned int rsvd_3 : 8; ++ } b; ++} RG_RX_A2_FIELD_T; ++ ++#define RG_RX_A3 (RF_D_RX_REG_BASE + 0xc) ++// Bit 0 rg_m0_wf_rx_fe_topbias_en U RW default = 'h0 ++// Bit 1 rg_m0_wf_rx_lna_bias_en U RW default = 'h0 ++// Bit 2 rg_m0_wf_rx_gm_bias_en U RW default = 'h0 ++// Bit 3 rg_m0_wf_rx_mxr_bias_en U RW default = 'h0 ++// Bit 4 rg_m0_wf5g_rx_lna_trsw_en U RW default = 'h0 ++// Bit 5 rg_m0_wf5g_rx_lna_en U RW default = 'h0 ++// Bit 6 rg_m0_wf5g_rx_gm_en U RW default = 'h0 ++// Bit 7 rg_m0_wf5g_rx_mxr_en U RW default = 'h0 ++// Bit 8 rg_m0_wf5g_rx_dpd_en U RW default = 'h0 ++// Bit 9 rg_m0_wf5g_rx_irrcal_en U RW default = 'h0 ++// Bit 10 rg_m0_wf2g_rx_lna_trsw_en U RW default = 'h0 ++// Bit 11 rg_m0_wf2g_rx_lna_en U RW default = 'h0 ++// Bit 12 rg_m0_wf2g_rx_gm_en U RW default = 'h0 ++// Bit 13 rg_m0_wf2g_rx_mxr_en U RW default = 'h0 ++// Bit 14 rg_m0_wf2g_rx_irrcal_en U RW default = 'h0 ++// Bit 15 rg_m0_wf2g_rx_dpd_en U RW default = 'h0 ++// Bit 17 rg_m0_wf_rtx_abb_topbias_en U RW default = 'h0 ++// Bit 18 rg_m0_wf_rtx_abb_rx_en U RW default = 'h0 ++// Bit 22 rg_m0_wf_rx_tia_bias_en U RW default = 'h0 ++// Bit 23 rg_m0_wf_rx_rssipga_bias_en U RW default = 'h0 ++// Bit 24 rg_m0_wf_rx_lpf_bias_en U RW default = 'h0 ++// Bit 25 rg_m0_wf_rx_tia_en U RW default = 'h0 ++// Bit 26 rg_m0_wf_rx_rssipga_en U RW default = 'h0 ++// Bit 27 rg_m0_wf_rx_lpf_en U RW default = 'h0 ++// Bit 28 rg_m0_wf_rx_lpf_i_dcoc_en U RW default = 'h0 ++// Bit 29 rg_m0_wf_rx_lpf_q_dcoc_en U RW default = 'h0 ++typedef union RG_RX_A3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M0_WF_RX_FE_TOPBIAS_EN : 1; ++ unsigned int RG_M0_WF_RX_LNA_BIAS_EN : 1; ++ unsigned int RG_M0_WF_RX_GM_BIAS_EN : 1; ++ unsigned int RG_M0_WF_RX_MXR_BIAS_EN : 1; ++ unsigned int RG_M0_WF5G_RX_LNA_TRSW_EN : 1; ++ unsigned int RG_M0_WF5G_RX_LNA_EN : 1; ++ unsigned int RG_M0_WF5G_RX_GM_EN : 1; ++ unsigned int RG_M0_WF5G_RX_MXR_EN : 1; ++ unsigned int RG_M0_WF5G_RX_DPD_EN : 1; ++ unsigned int RG_M0_WF5G_RX_IRRCAL_EN : 1; ++ unsigned int RG_M0_WF2G_RX_LNA_TRSW_EN : 1; ++ unsigned int RG_M0_WF2G_RX_LNA_EN : 1; ++ unsigned int RG_M0_WF2G_RX_GM_EN : 1; ++ unsigned int RG_M0_WF2G_RX_MXR_EN : 1; ++ unsigned int RG_M0_WF2G_RX_IRRCAL_EN : 1; ++ unsigned int RG_M0_WF2G_RX_DPD_EN : 1; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_M0_WF_RTX_ABB_TOPBIAS_EN : 1; ++ unsigned int RG_M0_WF_RTX_ABB_RX_EN : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int RG_M0_WF_RX_TIA_BIAS_EN : 1; ++ unsigned int RG_M0_WF_RX_RSSIPGA_BIAS_EN : 1; ++ unsigned int RG_M0_WF_RX_LPF_BIAS_EN : 1; ++ unsigned int RG_M0_WF_RX_TIA_EN : 1; ++ unsigned int RG_M0_WF_RX_RSSIPGA_EN : 1; ++ unsigned int RG_M0_WF_RX_LPF_EN : 1; ++ unsigned int RG_M0_WF_RX_LPF_I_DCOC_EN : 1; ++ unsigned int RG_M0_WF_RX_LPF_Q_DCOC_EN : 1; ++ unsigned int rsvd_2 : 2; ++ } b; ++} RG_RX_A3_FIELD_T; ++ ++#define RG_RX_A4 (RF_D_RX_REG_BASE + 0x10) ++// Bit 0 rg_m1_wf_rx_fe_topbias_en U RW default = 'h0 ++// Bit 1 rg_m1_wf_rx_lna_bias_en U RW default = 'h0 ++// Bit 2 rg_m1_wf_rx_gm_bias_en U RW default = 'h0 ++// Bit 3 rg_m1_wf_rx_mxr_bias_en U RW default = 'h0 ++// Bit 4 rg_m1_wf5g_rx_lna_trsw_en U RW default = 'h0 ++// Bit 5 rg_m1_wf5g_rx_lna_en U RW default = 'h0 ++// Bit 6 rg_m1_wf5g_rx_gm_en U RW default = 'h0 ++// Bit 7 rg_m1_wf5g_rx_mxr_en U RW default = 'h0 ++// Bit 8 rg_m1_wf5g_rx_dpd_en U RW default = 'h0 ++// Bit 9 rg_m1_wf5g_rx_irrcal_en U RW default = 'h0 ++// Bit 10 rg_m1_wf2g_rx_lna_trsw_en U RW default = 'h0 ++// Bit 11 rg_m1_wf2g_rx_lna_en U RW default = 'h0 ++// Bit 12 rg_m1_wf2g_rx_gm_en U RW default = 'h0 ++// Bit 13 rg_m1_wf2g_rx_mxr_en U RW default = 'h0 ++// Bit 14 rg_m1_wf2g_rx_irrcal_en U RW default = 'h0 ++// Bit 15 rg_m1_wf2g_rx_dpd_en U RW default = 'h0 ++// Bit 17 rg_m1_wf_rtx_abb_topbias_en U RW default = 'h0 ++// Bit 18 rg_m1_wf_rtx_abb_rx_en U RW default = 'h0 ++// Bit 22 rg_m1_wf_rx_tia_bias_en U RW default = 'h0 ++// Bit 23 rg_m1_wf_rx_rssipga_bias_en U RW default = 'h0 ++// Bit 24 rg_m1_wf_rx_lpf_bias_en U RW default = 'h0 ++// Bit 25 rg_m1_wf_rx_tia_en U RW default = 'h0 ++// Bit 26 rg_m1_wf_rx_rssipga_en U RW default = 'h0 ++// Bit 27 rg_m1_wf_rx_lpf_en U RW default = 'h0 ++// Bit 28 rg_m1_wf_rx_lpf_i_dcoc_en U RW default = 'h0 ++// Bit 29 rg_m1_wf_rx_lpf_q_dcoc_en U RW default = 'h0 ++typedef union RG_RX_A4_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M1_WF_RX_FE_TOPBIAS_EN : 1; ++ unsigned int RG_M1_WF_RX_LNA_BIAS_EN : 1; ++ unsigned int RG_M1_WF_RX_GM_BIAS_EN : 1; ++ unsigned int RG_M1_WF_RX_MXR_BIAS_EN : 1; ++ unsigned int RG_M1_WF5G_RX_LNA_TRSW_EN : 1; ++ unsigned int RG_M1_WF5G_RX_LNA_EN : 1; ++ unsigned int RG_M1_WF5G_RX_GM_EN : 1; ++ unsigned int RG_M1_WF5G_RX_MXR_EN : 1; ++ unsigned int RG_M1_WF5G_RX_DPD_EN : 1; ++ unsigned int RG_M1_WF5G_RX_IRRCAL_EN : 1; ++ unsigned int RG_M1_WF2G_RX_LNA_TRSW_EN : 1; ++ unsigned int RG_M1_WF2G_RX_LNA_EN : 1; ++ unsigned int RG_M1_WF2G_RX_GM_EN : 1; ++ unsigned int RG_M1_WF2G_RX_MXR_EN : 1; ++ unsigned int RG_M1_WF2G_RX_IRRCAL_EN : 1; ++ unsigned int RG_M1_WF2G_RX_DPD_EN : 1; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_M1_WF_RTX_ABB_TOPBIAS_EN : 1; ++ unsigned int RG_M1_WF_RTX_ABB_RX_EN : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int RG_M1_WF_RX_TIA_BIAS_EN : 1; ++ unsigned int RG_M1_WF_RX_RSSIPGA_BIAS_EN : 1; ++ unsigned int RG_M1_WF_RX_LPF_BIAS_EN : 1; ++ unsigned int RG_M1_WF_RX_TIA_EN : 1; ++ unsigned int RG_M1_WF_RX_RSSIPGA_EN : 1; ++ unsigned int RG_M1_WF_RX_LPF_EN : 1; ++ unsigned int RG_M1_WF_RX_LPF_I_DCOC_EN : 1; ++ unsigned int RG_M1_WF_RX_LPF_Q_DCOC_EN : 1; ++ unsigned int rsvd_2 : 2; ++ } b; ++} RG_RX_A4_FIELD_T; ++ ++#define RG_RX_A5 (RF_D_RX_REG_BASE + 0x14) ++// Bit 0 rg_m2_wf_rx_fe_topbias_en U RW default = 'h1 ++// Bit 1 rg_m2_wf_rx_lna_bias_en U RW default = 'h0 ++// Bit 2 rg_m2_wf_rx_gm_bias_en U RW default = 'h0 ++// Bit 3 rg_m2_wf_rx_mxr_bias_en U RW default = 'h0 ++// Bit 4 rg_m2_wf5g_rx_lna_trsw_en U RW default = 'h1 ++// Bit 5 rg_m2_wf5g_rx_lna_en U RW default = 'h0 ++// Bit 6 rg_m2_wf5g_rx_gm_en U RW default = 'h0 ++// Bit 7 rg_m2_wf5g_rx_mxr_en U RW default = 'h0 ++// Bit 8 rg_m2_wf5g_rx_dpd_en U RW default = 'h0 ++// Bit 9 rg_m2_wf5g_rx_irrcal_en U RW default = 'h0 ++// Bit 10 rg_m2_wf2g_rx_lna_trsw_en U RW default = 'h0 ++// Bit 11 rg_m2_wf2g_rx_lna_en U RW default = 'h0 ++// Bit 12 rg_m2_wf2g_rx_gm_en U RW default = 'h0 ++// Bit 13 rg_m2_wf2g_rx_mxr_en U RW default = 'h0 ++// Bit 14 rg_m2_wf2g_rx_irrcal_en U RW default = 'h0 ++// Bit 15 rg_m2_wf2g_rx_dpd_en U RW default = 'h0 ++// Bit 17 rg_m2_wf_rtx_abb_topbias_en U RW default = 'h1 ++// Bit 18 rg_m2_wf_rtx_abb_rx_en U RW default = 'h0 ++// Bit 22 rg_m2_wf_rx_tia_bias_en U RW default = 'h0 ++// Bit 23 rg_m2_wf_rx_rssipga_bias_en U RW default = 'h0 ++// Bit 24 rg_m2_wf_rx_lpf_bias_en U RW default = 'h0 ++// Bit 25 rg_m2_wf_rx_tia_en U RW default = 'h0 ++// Bit 26 rg_m2_wf_rx_rssipga_en U RW default = 'h0 ++// Bit 27 rg_m2_wf_rx_lpf_en U RW default = 'h0 ++// Bit 28 rg_m2_wf_rx_lpf_i_dcoc_en U RW default = 'h0 ++// Bit 29 rg_m2_wf_rx_lpf_q_dcoc_en U RW default = 'h0 ++typedef union RG_RX_A5_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M2_WF_RX_FE_TOPBIAS_EN : 1; ++ unsigned int RG_M2_WF_RX_LNA_BIAS_EN : 1; ++ unsigned int RG_M2_WF_RX_GM_BIAS_EN : 1; ++ unsigned int RG_M2_WF_RX_MXR_BIAS_EN : 1; ++ unsigned int RG_M2_WF5G_RX_LNA_TRSW_EN : 1; ++ unsigned int RG_M2_WF5G_RX_LNA_EN : 1; ++ unsigned int RG_M2_WF5G_RX_GM_EN : 1; ++ unsigned int RG_M2_WF5G_RX_MXR_EN : 1; ++ unsigned int RG_M2_WF5G_RX_DPD_EN : 1; ++ unsigned int RG_M2_WF5G_RX_IRRCAL_EN : 1; ++ unsigned int RG_M2_WF2G_RX_LNA_TRSW_EN : 1; ++ unsigned int RG_M2_WF2G_RX_LNA_EN : 1; ++ unsigned int RG_M2_WF2G_RX_GM_EN : 1; ++ unsigned int RG_M2_WF2G_RX_MXR_EN : 1; ++ unsigned int RG_M2_WF2G_RX_IRRCAL_EN : 1; ++ unsigned int RG_M2_WF2G_RX_DPD_EN : 1; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_M2_WF_RTX_ABB_TOPBIAS_EN : 1; ++ unsigned int RG_M2_WF_RTX_ABB_RX_EN : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int RG_M2_WF_RX_TIA_BIAS_EN : 1; ++ unsigned int RG_M2_WF_RX_RSSIPGA_BIAS_EN : 1; ++ unsigned int RG_M2_WF_RX_LPF_BIAS_EN : 1; ++ unsigned int RG_M2_WF_RX_TIA_EN : 1; ++ unsigned int RG_M2_WF_RX_RSSIPGA_EN : 1; ++ unsigned int RG_M2_WF_RX_LPF_EN : 1; ++ unsigned int RG_M2_WF_RX_LPF_I_DCOC_EN : 1; ++ unsigned int RG_M2_WF_RX_LPF_Q_DCOC_EN : 1; ++ unsigned int rsvd_2 : 2; ++ } b; ++} RG_RX_A5_FIELD_T; ++ ++#define RG_RX_A6 (RF_D_RX_REG_BASE + 0x18) ++// Bit 0 rg_m3_wf_rx_fe_topbias_en U RW default = 'h1 ++// Bit 1 rg_m3_wf_rx_lna_bias_en U RW default = 'h1 ++// Bit 2 rg_m3_wf_rx_gm_bias_en U RW default = 'h1 ++// Bit 3 rg_m3_wf_rx_mxr_bias_en U RW default = 'h1 ++// Bit 4 rg_m3_wf5g_rx_lna_trsw_en U RW default = 'h0 ++// Bit 5 rg_m3_wf5g_rx_lna_en U RW default = 'h1 ++// Bit 6 rg_m3_wf5g_rx_gm_en U RW default = 'h1 ++// Bit 7 rg_m3_wf5g_rx_mxr_en U RW default = 'h1 ++// Bit 8 rg_m3_wf5g_rx_dpd_en U RW default = 'h0 ++// Bit 9 rg_m3_wf5g_rx_irrcal_en U RW default = 'h0 ++// Bit 10 rg_m3_wf2g_rx_lna_trsw_en U RW default = 'h0 ++// Bit 11 rg_m3_wf2g_rx_lna_en U RW default = 'h0 ++// Bit 12 rg_m3_wf2g_rx_gm_en U RW default = 'h0 ++// Bit 13 rg_m3_wf2g_rx_mxr_en U RW default = 'h0 ++// Bit 14 rg_m3_wf2g_rx_irrcal_en U RW default = 'h0 ++// Bit 15 rg_m3_wf2g_rx_dpd_en U RW default = 'h0 ++// Bit 17 rg_m3_wf_rtx_abb_topbias_en U RW default = 'h1 ++// Bit 18 rg_m3_wf_rtx_abb_rx_en U RW default = 'h1 ++// Bit 22 rg_m3_wf_rx_tia_bias_en U RW default = 'h1 ++// Bit 23 rg_m3_wf_rx_rssipga_bias_en U RW default = 'h1 ++// Bit 24 rg_m3_wf_rx_lpf_bias_en U RW default = 'h1 ++// Bit 25 rg_m3_wf_rx_tia_en U RW default = 'h1 ++// Bit 26 rg_m3_wf_rx_rssipga_en U RW default = 'h1 ++// Bit 27 rg_m3_wf_rx_lpf_en U RW default = 'h1 ++// Bit 28 rg_m3_wf_rx_lpf_i_dcoc_en U RW default = 'h1 ++// Bit 29 rg_m3_wf_rx_lpf_q_dcoc_en U RW default = 'h1 ++typedef union RG_RX_A6_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M3_WF_RX_FE_TOPBIAS_EN : 1; ++ unsigned int RG_M3_WF_RX_LNA_BIAS_EN : 1; ++ unsigned int RG_M3_WF_RX_GM_BIAS_EN : 1; ++ unsigned int RG_M3_WF_RX_MXR_BIAS_EN : 1; ++ unsigned int RG_M3_WF5G_RX_LNA_TRSW_EN : 1; ++ unsigned int RG_M3_WF5G_RX_LNA_EN : 1; ++ unsigned int RG_M3_WF5G_RX_GM_EN : 1; ++ unsigned int RG_M3_WF5G_RX_MXR_EN : 1; ++ unsigned int RG_M3_WF5G_RX_DPD_EN : 1; ++ unsigned int RG_M3_WF5G_RX_IRRCAL_EN : 1; ++ unsigned int RG_M3_WF2G_RX_LNA_TRSW_EN : 1; ++ unsigned int RG_M3_WF2G_RX_LNA_EN : 1; ++ unsigned int RG_M3_WF2G_RX_GM_EN : 1; ++ unsigned int RG_M3_WF2G_RX_MXR_EN : 1; ++ unsigned int RG_M3_WF2G_RX_IRRCAL_EN : 1; ++ unsigned int RG_M3_WF2G_RX_DPD_EN : 1; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_M3_WF_RTX_ABB_TOPBIAS_EN : 1; ++ unsigned int RG_M3_WF_RTX_ABB_RX_EN : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int RG_M3_WF_RX_TIA_BIAS_EN : 1; ++ unsigned int RG_M3_WF_RX_RSSIPGA_BIAS_EN : 1; ++ unsigned int RG_M3_WF_RX_LPF_BIAS_EN : 1; ++ unsigned int RG_M3_WF_RX_TIA_EN : 1; ++ unsigned int RG_M3_WF_RX_RSSIPGA_EN : 1; ++ unsigned int RG_M3_WF_RX_LPF_EN : 1; ++ unsigned int RG_M3_WF_RX_LPF_I_DCOC_EN : 1; ++ unsigned int RG_M3_WF_RX_LPF_Q_DCOC_EN : 1; ++ unsigned int rsvd_2 : 2; ++ } b; ++} RG_RX_A6_FIELD_T; ++ ++#define RG_RX_A7 (RF_D_RX_REG_BASE + 0x1c) ++// Bit 3 :0 rg_wf5g_rx_lna_tank_sel_band0 U RW default = 'h9 ++// Bit 7 :4 rg_wf5g_rx_lna_tank_sel_band1 U RW default = 'h9 ++// Bit 11 :8 rg_wf5g_rx_lna_tank_sel_band2 U RW default = 'h8 ++// Bit 15 :12 rg_wf5g_rx_lna_tank_sel_band3 U RW default = 'h7 ++// Bit 19 :16 rg_wf5g_rx_lna_tank_sel_band4 U RW default = 'h6 ++// Bit 23 :20 rg_wf5g_rx_lna_tank_sel_band5 U RW default = 'h5 ++// Bit 27 :24 rg_wf5g_rx_lna_tank_sel_band6 U RW default = 'h4 ++// Bit 31 :28 rg_wf5g_rx_lna_tank_sel_band7 U RW default = 'h4 ++typedef union RG_RX_A7_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND0 : 4; ++ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND1 : 4; ++ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND2 : 4; ++ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND3 : 4; ++ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND4 : 4; ++ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND5 : 4; ++ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND6 : 4; ++ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND7 : 4; ++ } b; ++} RG_RX_A7_FIELD_T; ++ ++#define RG_RX_A8 (RF_D_RX_REG_BASE + 0x20) ++// Bit 3 :0 rg_wf5g_rx_lna_tank_sel_band8 U RW default = 'h3 ++// Bit 7 :4 rg_wf5g_rx_lna_tank_sel_band9 U RW default = 'h2 ++// Bit 11 :8 rg_wf5g_rx_lna_tank_sel_man U RW default = 'h2 ++// Bit 12 rg_wf5g_rx_lna_tank_sel_man_mode U RW default = 'h0 ++// Bit 19 :16 rg_wf2g_rx_lna_tank_sel U RW default = 'h5 ++// Bit 23 :20 rg_wf2g_rx_lna_tank_sel_man U RW default = 'h5 ++// Bit 24 rg_wf2g_rx_lna_tank_sel_man_mode U RW default = 'h0 ++typedef union RG_RX_A8_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND8 : 4; ++ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND9 : 4; ++ unsigned int RG_WF5G_RX_LNA_TANK_SEL_MAN : 4; ++ unsigned int RG_WF5G_RX_LNA_TANK_SEL_MAN_MODE : 1; ++ unsigned int rsvd_0 : 3; ++ unsigned int RG_WF2G_RX_LNA_TANK_SEL : 4; ++ unsigned int RG_WF2G_RX_LNA_TANK_SEL_MAN : 4; ++ unsigned int RG_WF2G_RX_LNA_TANK_SEL_MAN_MODE : 1; ++ unsigned int rsvd_1 : 7; ++ } b; ++} RG_RX_A8_FIELD_T; ++ ++#define RG_RX_A9 (RF_D_RX_REG_BASE + 0x24) ++// Bit 2 :0 rg_wf5g_rx_lna_tank_offset_g1 U RW default = 'h0 ++// Bit 6 :4 rg_wf5g_rx_lna_tank_offset_g2 U RW default = 'h0 ++// Bit 10 :8 rg_wf5g_rx_lna_tank_offset_g3 U RW default = 'h0 ++// Bit 14 :12 rg_wf5g_rx_lna_tank_offset_g4 U RW default = 'h2 ++// Bit 18 :16 rg_wf5g_rx_lna_tank_offset_g5 U RW default = 'h2 ++// Bit 26 :24 rg_wf5g_rx_lna_tank_offset_g6 U RW default = 'h2 ++// Bit 30 :28 rg_wf5g_rx_lna_tank_offset_g7 U RW default = 'h2 ++typedef union RG_RX_A9_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LNA_TANK_OFFSET_G1 : 3; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF5G_RX_LNA_TANK_OFFSET_G2 : 3; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF5G_RX_LNA_TANK_OFFSET_G3 : 3; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF5G_RX_LNA_TANK_OFFSET_G4 : 3; ++ unsigned int rsvd_3 : 1; ++ unsigned int RG_WF5G_RX_LNA_TANK_OFFSET_G5 : 3; ++ unsigned int rsvd_4 : 5; ++ unsigned int RG_WF5G_RX_LNA_TANK_OFFSET_G6 : 3; ++ unsigned int rsvd_5 : 1; ++ unsigned int RG_WF5G_RX_LNA_TANK_OFFSET_G7 : 3; ++ unsigned int rsvd_6 : 1; ++ } b; ++} RG_RX_A9_FIELD_T; ++ ++#define RG_RX_A10 (RF_D_RX_REG_BASE + 0x28) ++// Bit 2 :0 rg_wf2g_rx_lna_tank_offset_g1 U RW default = 'h0 ++// Bit 6 :4 rg_wf2g_rx_lna_tank_offset_g2 U RW default = 'h0 ++// Bit 10 :8 rg_wf2g_rx_lna_tank_offset_g3 U RW default = 'h0 ++// Bit 14 :12 rg_wf2g_rx_lna_tank_offset_g4 U RW default = 'h0 ++// Bit 18 :16 rg_wf2g_rx_lna_tank_offset_g5 U RW default = 'h0 ++// Bit 26 :24 rg_wf2g_rx_lna_tank_offset_g6 U RW default = 'h2 ++// Bit 30 :28 rg_wf2g_rx_lna_tank_offset_g7 U RW default = 'h3 ++typedef union RG_RX_A10_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LNA_TANK_OFFSET_G1 : 3; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF2G_RX_LNA_TANK_OFFSET_G2 : 3; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF2G_RX_LNA_TANK_OFFSET_G3 : 3; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF2G_RX_LNA_TANK_OFFSET_G4 : 3; ++ unsigned int rsvd_3 : 1; ++ unsigned int RG_WF2G_RX_LNA_TANK_OFFSET_G5 : 3; ++ unsigned int rsvd_4 : 5; ++ unsigned int RG_WF2G_RX_LNA_TANK_OFFSET_G6 : 3; ++ unsigned int rsvd_5 : 1; ++ unsigned int RG_WF2G_RX_LNA_TANK_OFFSET_G7 : 3; ++ unsigned int rsvd_6 : 1; ++ } b; ++} RG_RX_A10_FIELD_T; ++ ++#define RG_RX_A11 (RF_D_RX_REG_BASE + 0x2c) ++// Bit 6 :0 rg_wf_rxfe_gain_g1 U RW default = 'h12 ++// Bit 14 :8 rg_wf_rxfe_gain_g2 U RW default = 'h1a ++// Bit 22 :16 rg_wf_rxfe_gain_g3 U RW default = 'h32 ++// Bit 30 :24 rg_wf_rxfe_gain_g4 U RW default = 'h3a ++typedef union RG_RX_A11_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RXFE_GAIN_G1 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF_RXFE_GAIN_G2 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF_RXFE_GAIN_G3 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF_RXFE_GAIN_G4 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A11_FIELD_T; ++ ++#define RG_RX_A12 (RF_D_RX_REG_BASE + 0x30) ++// Bit 6 :0 rg_wf_rxfe_gain_g5 U RW default = 'h52 ++// Bit 14 :8 rg_wf_rxfe_gain_g6 U RW default = 'h5a ++// Bit 22 :16 rg_wf_rxfe_gain_g7 U RW default = 'h72 ++// Bit 30 :24 rg_wf_rxfe_gain_g8 U RW default = 'h7a ++typedef union RG_RX_A12_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RXFE_GAIN_G5 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF_RXFE_GAIN_G6 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF_RXFE_GAIN_G7 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF_RXFE_GAIN_G8 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A12_FIELD_T; ++ ++#define RG_RX_A13 (RF_D_RX_REG_BASE + 0x34) ++// Bit 6 :0 rg_wf_rxfe_gain_g9 U RW default = 'h7e ++// Bit 22 :8 rg_wf_rxfe_lpf_gain_man U RW default = 'h7ec ++// Bit 24 rg_wf_rxfe_lpf_gain_man_mode U RW default = 'h0 ++typedef union RG_RX_A13_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RXFE_GAIN_G9 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF_RXFE_LPF_GAIN_MAN : 15; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF_RXFE_LPF_GAIN_MAN_MODE : 1; ++ unsigned int rsvd_2 : 7; ++ } b; ++} RG_RX_A13_FIELD_T; ++ ++#define RG_RX_A14 (RF_D_RX_REG_BASE + 0x38) ++// Bit 2 :0 rg_wf5g_rx_lna_ictrl_g1 U RW default = 'h3 ++// Bit 6 :4 rg_wf5g_rx_lna_ictrl_g2 U RW default = 'h3 ++// Bit 10 :8 rg_wf5g_rx_lna_ictrl_g3 U RW default = 'h3 ++// Bit 14 :12 rg_wf5g_rx_lna_ictrl_g4 U RW default = 'h2 ++// Bit 18 :16 rg_wf5g_rx_lna_ictrl_g5 U RW default = 'h2 ++// Bit 22 :20 rg_wf5g_rx_lna_ictrl_g6 U RW default = 'h3 ++// Bit 26 :24 rg_wf5g_rx_lna_ictrl_g7 U RW default = 'h3 ++// Bit 30 :28 rg_wf5g_rx_lna_ictrl_man U RW default = 'h0 ++// Bit 31 rg_wf5g_rx_lna_ictrl_man_mode U RW default = 'h0 ++typedef union RG_RX_A14_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LNA_ICTRL_G1 : 3; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF5G_RX_LNA_ICTRL_G2 : 3; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF5G_RX_LNA_ICTRL_G3 : 3; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF5G_RX_LNA_ICTRL_G4 : 3; ++ unsigned int rsvd_3 : 1; ++ unsigned int RG_WF5G_RX_LNA_ICTRL_G5 : 3; ++ unsigned int rsvd_4 : 1; ++ unsigned int RG_WF5G_RX_LNA_ICTRL_G6 : 3; ++ unsigned int rsvd_5 : 1; ++ unsigned int RG_WF5G_RX_LNA_ICTRL_G7 : 3; ++ unsigned int rsvd_6 : 1; ++ unsigned int RG_WF5G_RX_LNA_ICTRL_MAN : 3; ++ unsigned int RG_WF5G_RX_LNA_ICTRL_MAN_MODE : 1; ++ } b; ++} RG_RX_A14_FIELD_T; ++ ++#define RG_RX_A15 (RF_D_RX_REG_BASE + 0x3c) ++// Bit 5 :0 rg_wf5g_rx_lna_slice_g1 U RW default = 'h1 ++// Bit 13 :8 rg_wf5g_rx_lna_slice_g2 U RW default = 'h1 ++// Bit 21 :16 rg_wf5g_rx_lna_slice_g3 U RW default = 'h2 ++// Bit 29 :24 rg_wf5g_rx_lna_slice_g4 U RW default = 'h4 ++typedef union RG_RX_A15_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LNA_SLICE_G1 : 6; ++ unsigned int rsvd_0 : 2; ++ unsigned int RG_WF5G_RX_LNA_SLICE_G2 : 6; ++ unsigned int rsvd_1 : 2; ++ unsigned int RG_WF5G_RX_LNA_SLICE_G3 : 6; ++ unsigned int rsvd_2 : 2; ++ unsigned int RG_WF5G_RX_LNA_SLICE_G4 : 6; ++ unsigned int rsvd_3 : 2; ++ } b; ++} RG_RX_A15_FIELD_T; ++ ++#define RG_RX_A16 (RF_D_RX_REG_BASE + 0x40) ++// Bit 5 :0 rg_wf5g_rx_lna_slice_g5 U RW default = 'hc ++// Bit 13 :8 rg_wf5g_rx_lna_slice_g6 U RW default = 'h1c ++// Bit 21 :16 rg_wf5g_rx_lna_slice_g7 U RW default = 'h3c ++// Bit 29 :24 rg_wf5g_rx_lna_slice_man U RW default = 'h0 ++// Bit 31 rg_wf5g_rx_lna_slice_man_mode U RW default = 'h0 ++typedef union RG_RX_A16_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LNA_SLICE_G5 : 6; ++ unsigned int rsvd_0 : 2; ++ unsigned int RG_WF5G_RX_LNA_SLICE_G6 : 6; ++ unsigned int rsvd_1 : 2; ++ unsigned int RG_WF5G_RX_LNA_SLICE_G7 : 6; ++ unsigned int rsvd_2 : 2; ++ unsigned int RG_WF5G_RX_LNA_SLICE_MAN : 6; ++ unsigned int rsvd_3 : 1; ++ unsigned int RG_WF5G_RX_LNA_SLICE_MAN_MODE : 1; ++ } b; ++} RG_RX_A16_FIELD_T; ++ ++#define RG_RX_A17 (RF_D_RX_REG_BASE + 0x44) ++// Bit 3 :0 rg_wf5g_rx_lna_rfb_lb_g1 U RW default = 'h5 ++// Bit 7 :4 rg_wf5g_rx_lna_rfb_lb_g2 U RW default = 'h2 ++// Bit 11 :8 rg_wf5g_rx_lna_rfb_lb_g3 U RW default = 'h4 ++// Bit 15 :12 rg_wf5g_rx_lna_rfb_lb_g4 U RW default = 'h7 ++// Bit 19 :16 rg_wf5g_rx_lna_rfb_lb_g5 U RW default = 'h7 ++// Bit 23 :20 rg_wf5g_rx_lna_rfb_lb_g6 U RW default = 'h7 ++// Bit 27 :24 rg_wf5g_rx_lna_rfb_lb_g7 U RW default = 'h0 ++// Bit 31 :28 rg_wf5g_rx_lna_rfb_hb_g1 U RW default = 'h2 ++typedef union RG_RX_A17_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LNA_RFB_LB_G1 : 4; ++ unsigned int RG_WF5G_RX_LNA_RFB_LB_G2 : 4; ++ unsigned int RG_WF5G_RX_LNA_RFB_LB_G3 : 4; ++ unsigned int RG_WF5G_RX_LNA_RFB_LB_G4 : 4; ++ unsigned int RG_WF5G_RX_LNA_RFB_LB_G5 : 4; ++ unsigned int RG_WF5G_RX_LNA_RFB_LB_G6 : 4; ++ unsigned int RG_WF5G_RX_LNA_RFB_LB_G7 : 4; ++ unsigned int RG_WF5G_RX_LNA_RFB_HB_G1 : 4; ++ } b; ++} RG_RX_A17_FIELD_T; ++ ++#define RG_RX_A18 (RF_D_RX_REG_BASE + 0x48) ++// Bit 3 :0 rg_wf5g_rx_lna_rfb_hb_g2 U RW default = 'h0 ++// Bit 7 :4 rg_wf5g_rx_lna_rfb_hb_g3 U RW default = 'h2 ++// Bit 11 :8 rg_wf5g_rx_lna_rfb_hb_g4 U RW default = 'h5 ++// Bit 15 :12 rg_wf5g_rx_lna_rfb_hb_g5 U RW default = 'h4 ++// Bit 19 :16 rg_wf5g_rx_lna_rfb_hb_g6 U RW default = 'h5 ++// Bit 23 :20 rg_wf5g_rx_lna_rfb_hb_g7 U RW default = 'h0 ++// Bit 27 :24 rg_wf5g_rx_lna_rfb_man U RW default = 'h0 ++// Bit 31 rg_wf5g_rx_lna_rfb_man_mode U RW default = 'h0 ++typedef union RG_RX_A18_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LNA_RFB_HB_G2 : 4; ++ unsigned int RG_WF5G_RX_LNA_RFB_HB_G3 : 4; ++ unsigned int RG_WF5G_RX_LNA_RFB_HB_G4 : 4; ++ unsigned int RG_WF5G_RX_LNA_RFB_HB_G5 : 4; ++ unsigned int RG_WF5G_RX_LNA_RFB_HB_G6 : 4; ++ unsigned int RG_WF5G_RX_LNA_RFB_HB_G7 : 4; ++ unsigned int RG_WF5G_RX_LNA_RFB_MAN : 4; ++ unsigned int rsvd_0 : 3; ++ unsigned int RG_WF5G_RX_LNA_RFB_MAN_MODE : 1; ++ } b; ++} RG_RX_A18_FIELD_T; ++ ++#define RG_RX_A19 (RF_D_RX_REG_BASE + 0x4c) ++// Bit 2 :0 rg_wf5g_rx_lna_rt_g1 U RW default = 'h5 ++// Bit 5 :3 rg_wf5g_rx_lna_rt_g2 U RW default = 'h7 ++// Bit 8 :6 rg_wf5g_rx_lna_rt_g3 U RW default = 'h5 ++// Bit 11 :9 rg_wf5g_rx_lna_rt_g4 U RW default = 'h5 ++// Bit 14 :12 rg_wf5g_rx_lna_rt_g5 U RW default = 'h3 ++// Bit 17 :15 rg_wf5g_rx_lna_rt_g6 U RW default = 'h1 ++// Bit 26 :24 rg_wf5g_rx_lna_rt_man U RW default = 'h0 ++// Bit 31 rg_wf5g_rx_lna_rt_man_mode U RW default = 'h0 ++typedef union RG_RX_A19_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LNA_RT_G1 : 3; ++ unsigned int RG_WF5G_RX_LNA_RT_G2 : 3; ++ unsigned int RG_WF5G_RX_LNA_RT_G3 : 3; ++ unsigned int RG_WF5G_RX_LNA_RT_G4 : 3; ++ unsigned int RG_WF5G_RX_LNA_RT_G5 : 3; ++ unsigned int RG_WF5G_RX_LNA_RT_G6 : 3; ++ unsigned int rsvd_0 : 6; ++ unsigned int RG_WF5G_RX_LNA_RT_MAN : 3; ++ unsigned int rsvd_1 : 4; ++ unsigned int RG_WF5G_RX_LNA_RT_MAN_MODE : 1; ++ } b; ++} RG_RX_A19_FIELD_T; ++ ++#define RG_RX_A20 (RF_D_RX_REG_BASE + 0x50) ++// Bit 2 :0 rg_wf5g_rx_lna_att_lb_g1 U RW default = 'h3 ++// Bit 5 :3 rg_wf5g_rx_lna_att_lb_g2 U RW default = 'h1 ++// Bit 8 :6 rg_wf5g_rx_lna_att_lb_g3 U RW default = 'h0 ++// Bit 11 :9 rg_wf5g_rx_lna_att_hb_g1 U RW default = 'h6 ++// Bit 14 :12 rg_wf5g_rx_lna_att_hb_g2 U RW default = 'h2 ++// Bit 17 :15 rg_wf5g_rx_lna_att_hb_g3 U RW default = 'h1 ++// Bit 26 :24 rg_wf5g_rx_lna_att_man U RW default = 'h0 ++// Bit 31 rg_wf5g_rx_lna_att_man_mode U RW default = 'h0 ++typedef union RG_RX_A20_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LNA_ATT_LB_G1 : 3; ++ unsigned int RG_WF5G_RX_LNA_ATT_LB_G2 : 3; ++ unsigned int RG_WF5G_RX_LNA_ATT_LB_G3 : 3; ++ unsigned int RG_WF5G_RX_LNA_ATT_HB_G1 : 3; ++ unsigned int RG_WF5G_RX_LNA_ATT_HB_G2 : 3; ++ unsigned int RG_WF5G_RX_LNA_ATT_HB_G3 : 3; ++ unsigned int rsvd_0 : 6; ++ unsigned int RG_WF5G_RX_LNA_ATT_MAN : 3; ++ unsigned int rsvd_1 : 4; ++ unsigned int RG_WF5G_RX_LNA_ATT_MAN_MODE : 1; ++ } b; ++} RG_RX_A20_FIELD_T; ++ ++#define RG_RX_A21 (RF_D_RX_REG_BASE + 0x54) ++// Bit 4 :0 rg_wf_rx_tia_cfix_sel_g1 U RW default = 'h1f ++// Bit 12 :8 rg_wf_rx_tia_cfix_sel_g2 U RW default = 'h1a ++// Bit 20 :16 rg_wf_rx_tia_cfix_sel_g3 U RW default = 'h14 ++// Bit 28 :24 rg_wf_rx_tia_cfix_sel_g4 U RW default = 'h1f ++typedef union RG_RX_A21_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_TIA_CFIX_SEL_G1 : 5; ++ unsigned int rsvd_0 : 3; ++ unsigned int RG_WF_RX_TIA_CFIX_SEL_G2 : 5; ++ unsigned int rsvd_1 : 3; ++ unsigned int RG_WF_RX_TIA_CFIX_SEL_G3 : 5; ++ unsigned int rsvd_2 : 3; ++ unsigned int RG_WF_RX_TIA_CFIX_SEL_G4 : 5; ++ unsigned int rsvd_3 : 3; ++ } b; ++} RG_RX_A21_FIELD_T; ++ ++#define RG_RX_A22 (RF_D_RX_REG_BASE + 0x58) ++// Bit 4 :0 rg_wf_rx_tia_cfix_sel_g5 U RW default = 'h1a ++// Bit 12 :8 rg_wf_rx_tia_cfix_sel_g6 U RW default = 'h14 ++// Bit 28 :24 rg_wf_rx_tia_cfix_sel_man U RW default = 'h0 ++// Bit 31 rg_wf_rx_tia_cfix_sel_man_mode U RW default = 'h0 ++typedef union RG_RX_A22_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_TIA_CFIX_SEL_G5 : 5; ++ unsigned int rsvd_0 : 3; ++ unsigned int RG_WF_RX_TIA_CFIX_SEL_G6 : 5; ++ unsigned int rsvd_1 : 11; ++ unsigned int RG_WF_RX_TIA_CFIX_SEL_MAN : 5; ++ unsigned int rsvd_2 : 2; ++ unsigned int RG_WF_RX_TIA_CFIX_SEL_MAN_MODE : 1; ++ } b; ++} RG_RX_A22_FIELD_T; ++ ++#define RG_RX_A23 (RF_D_RX_REG_BASE + 0x5c) ++// Bit 3 :0 rg_wf_rx_tia_cunit_sel_g1 U RW default = 'h5 ++// Bit 7 :4 rg_wf_rx_tia_cunit_sel_g2 U RW default = 'h3 ++// Bit 11 :8 rg_wf_rx_tia_cunit_sel_g3 U RW default = 'h3 ++// Bit 15 :12 rg_wf_rx_tia_cunit_sel_g4 U RW default = 'h2 ++// Bit 19 :16 rg_wf_rx_tia_cunit_sel_g5 U RW default = 'h1 ++// Bit 23 :20 rg_wf_rx_tia_cunit_sel_g6 U RW default = 'h1 ++// Bit 27 :24 rg_wf_rx_tia_cunit_sel_man U RW default = 'h0 ++// Bit 31 rg_wf_rx_tia_cunit_sel_man_mode U RW default = 'h0 ++typedef union RG_RX_A23_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_TIA_CUNIT_SEL_G1 : 4; ++ unsigned int RG_WF_RX_TIA_CUNIT_SEL_G2 : 4; ++ unsigned int RG_WF_RX_TIA_CUNIT_SEL_G3 : 4; ++ unsigned int RG_WF_RX_TIA_CUNIT_SEL_G4 : 4; ++ unsigned int RG_WF_RX_TIA_CUNIT_SEL_G5 : 4; ++ unsigned int RG_WF_RX_TIA_CUNIT_SEL_G6 : 4; ++ unsigned int RG_WF_RX_TIA_CUNIT_SEL_MAN : 4; ++ unsigned int rsvd_0 : 3; ++ unsigned int RG_WF_RX_TIA_CUNIT_SEL_MAN_MODE : 1; ++ } b; ++} RG_RX_A23_FIELD_T; ++ ++#define RG_RX_A24 (RF_D_RX_REG_BASE + 0x60) ++// Bit 3 :0 rg_wf_rx_lpf_sra_sel_bw20m U RW default = 'h1 ++// Bit 7 :4 rg_wf_rx_lpf_sra_sel_bw40m U RW default = 'h1 ++// Bit 11 :8 rg_wf_rx_lpf_sra_sel_bw80m U RW default = 'h3 ++// Bit 15 :12 rg_wf_rx_lpf_sra_sel_bw160m U RW default = 'h3 ++// Bit 27 :24 rg_wf_rx_lpf_sra_sel_man U RW default = 'h0 ++// Bit 31 rg_wf_rx_lpf_sra_sel_man_mode U RW default = 'h0 ++typedef union RG_RX_A24_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_LPF_SRA_SEL_BW20M : 4; ++ unsigned int RG_WF_RX_LPF_SRA_SEL_BW40M : 4; ++ unsigned int RG_WF_RX_LPF_SRA_SEL_BW80M : 4; ++ unsigned int RG_WF_RX_LPF_SRA_SEL_BW160M : 4; ++ unsigned int rsvd_0 : 8; ++ unsigned int RG_WF_RX_LPF_SRA_SEL_MAN : 4; ++ unsigned int rsvd_1 : 3; ++ unsigned int RG_WF_RX_LPF_SRA_SEL_MAN_MODE : 1; ++ } b; ++} RG_RX_A24_FIELD_T; ++ ++#define RG_RX_A25 (RF_D_RX_REG_BASE + 0x64) ++// Bit 3 :0 rg_wf_rx_lpf_sraq_sel_bw20m U RW default = 'h1 ++// Bit 7 :4 rg_wf_rx_lpf_sraq_sel_bw40m U RW default = 'h1 ++// Bit 11 :8 rg_wf_rx_lpf_sraq_sel_bw80m U RW default = 'h3 ++// Bit 15 :12 rg_wf_rx_lpf_sraq_sel_bw160m U RW default = 'h3 ++// Bit 27 :24 rg_wf_rx_lpf_sraq_sel_man U RW default = 'h0 ++// Bit 31 rg_wf_rx_lpf_sraq_sel_man_mode U RW default = 'h0 ++typedef union RG_RX_A25_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_LPF_SRAQ_SEL_BW20M : 4; ++ unsigned int RG_WF_RX_LPF_SRAQ_SEL_BW40M : 4; ++ unsigned int RG_WF_RX_LPF_SRAQ_SEL_BW80M : 4; ++ unsigned int RG_WF_RX_LPF_SRAQ_SEL_BW160M : 4; ++ unsigned int rsvd_0 : 8; ++ unsigned int RG_WF_RX_LPF_SRAQ_SEL_MAN : 4; ++ unsigned int rsvd_1 : 3; ++ unsigned int RG_WF_RX_LPF_SRAQ_SEL_MAN_MODE : 1; ++ } b; ++} RG_RX_A25_FIELD_T; ++ ++#define RG_RX_A26 (RF_D_RX_REG_BASE + 0x68) ++// Bit 4 :0 rg_wf_rx_lpf_cfix_sel_bw20m U RW default = 'h1a ++// Bit 9 :5 rg_wf_rx_lpf_cfix_sel_bw40m U RW default = 'h1a ++// Bit 14 :10 rg_wf_rx_lpf_cfix_sel_bw80m U RW default = 'h1a ++// Bit 19 :15 rg_wf_rx_lpf_cfix_sel_bw160m U RW default = 'h1a ++// Bit 24 :20 rg_wf_rx_lpf_cfix_sel_man U RW default = 'h0 ++// Bit 31 rg_wf_rx_lpf_cfix_sel_man_mode U RW default = 'h0 ++typedef union RG_RX_A26_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_LPF_CFIX_SEL_BW20M : 5; ++ unsigned int RG_WF_RX_LPF_CFIX_SEL_BW40M : 5; ++ unsigned int RG_WF_RX_LPF_CFIX_SEL_BW80M : 5; ++ unsigned int RG_WF_RX_LPF_CFIX_SEL_BW160M : 5; ++ unsigned int RG_WF_RX_LPF_CFIX_SEL_MAN : 5; ++ unsigned int rsvd_0 : 6; ++ unsigned int RG_WF_RX_LPF_CFIX_SEL_MAN_MODE : 1; ++ } b; ++} RG_RX_A26_FIELD_T; ++ ++#define RG_RX_A27 (RF_D_RX_REG_BASE + 0x6c) ++// Bit 2 :0 rg_wf_rx_lpf_c1unit_sel_bw20m U RW default = 'h5 ++// Bit 6 :4 rg_wf_rx_lpf_c1unit_sel_bw40m U RW default = 'h2 ++// Bit 10 :8 rg_wf_rx_lpf_c1unit_sel_bw80m U RW default = 'h2 ++// Bit 14 :12 rg_wf_rx_lpf_c1unit_sel_bw160m U RW default = 'h0 ++// Bit 18 :16 rg_wf_rx_lpf_c1unit_sel_man U RW default = 'h0 ++// Bit 20 rg_wf_rx_lpf_c1unit_sel_man_mode U RW default = 'h0 ++typedef union RG_RX_A27_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_LPF_C1UNIT_SEL_BW20M : 3; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF_RX_LPF_C1UNIT_SEL_BW40M : 3; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF_RX_LPF_C1UNIT_SEL_BW80M : 3; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF_RX_LPF_C1UNIT_SEL_BW160M : 3; ++ unsigned int rsvd_3 : 1; ++ unsigned int RG_WF_RX_LPF_C1UNIT_SEL_MAN : 3; ++ unsigned int rsvd_4 : 1; ++ unsigned int RG_WF_RX_LPF_C1UNIT_SEL_MAN_MODE : 1; ++ unsigned int rsvd_5 : 11; ++ } b; ++} RG_RX_A27_FIELD_T; ++ ++#define RG_RX_A28 (RF_D_RX_REG_BASE + 0x70) ++// Bit 2 :0 rg_wf_rx_lpf_c2unit_sel_bw20m U RW default = 'h5 ++// Bit 6 :4 rg_wf_rx_lpf_c2unit_sel_bw40m U RW default = 'h2 ++// Bit 10 :8 rg_wf_rx_lpf_c2unit_sel_bw80m U RW default = 'h2 ++// Bit 14 :12 rg_wf_rx_lpf_c2unit_sel_bw160m U RW default = 'h0 ++// Bit 18 :16 rg_wf_rx_lpf_c2unit_sel_man U RW default = 'h0 ++// Bit 20 rg_wf_rx_lpf_c2unit_sel_man_mode U RW default = 'h0 ++typedef union RG_RX_A28_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_LPF_C2UNIT_SEL_BW20M : 3; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF_RX_LPF_C2UNIT_SEL_BW40M : 3; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF_RX_LPF_C2UNIT_SEL_BW80M : 3; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF_RX_LPF_C2UNIT_SEL_BW160M : 3; ++ unsigned int rsvd_3 : 1; ++ unsigned int RG_WF_RX_LPF_C2UNIT_SEL_MAN : 3; ++ unsigned int rsvd_4 : 1; ++ unsigned int RG_WF_RX_LPF_C2UNIT_SEL_MAN_MODE : 1; ++ unsigned int rsvd_5 : 11; ++ } b; ++} RG_RX_A28_FIELD_T; ++ ++#define RG_RX_A29 (RF_D_RX_REG_BASE + 0x74) ++// Bit 3 :0 rg_wf_rx_lpf_rn_sel_bw20madc160m U RW default = 'h1 ++// Bit 7 :4 rg_wf_rx_lpf_rn_sel_bw40madc160m U RW default = 'h1 ++// Bit 11 :8 rg_wf_rx_lpf_rn_sel_bw80madc160m U RW default = 'h3 ++// Bit 15 :12 rg_wf_rx_lpf_rn_sel_bw80madc320m U RW default = 'h3 ++// Bit 19 :16 rg_wf_rx_lpf_rn_sel_bw160madc320m U RW default = 'h3 ++// Bit 23 :20 rg_wf_rx_lpf_rn_sel_man U RW default = 'h0 ++// Bit 31 rg_wf_rx_lpf_rn_sel_man_mode U RW default = 'h0 ++typedef union RG_RX_A29_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_LPF_RN_SEL_BW20MADC160M : 4; ++ unsigned int RG_WF_RX_LPF_RN_SEL_BW40MADC160M : 4; ++ unsigned int RG_WF_RX_LPF_RN_SEL_BW80MADC160M : 4; ++ unsigned int RG_WF_RX_LPF_RN_SEL_BW80MADC320M : 4; ++ unsigned int RG_WF_RX_LPF_RN_SEL_BW160MADC320M : 4; ++ unsigned int RG_WF_RX_LPF_RN_SEL_MAN : 4; ++ unsigned int rsvd_0 : 7; ++ unsigned int RG_WF_RX_LPF_RN_SEL_MAN_MODE : 1; ++ } b; ++} RG_RX_A29_FIELD_T; ++ ++#define RG_RX_A30 (RF_D_RX_REG_BASE + 0x78) ++// Bit 2 :0 rg_wf_rx_lpf_cn_sel_bw20madc160m U RW default = 'h3 ++// Bit 6 :4 rg_wf_rx_lpf_cn_sel_bw40madc160m U RW default = 'h3 ++// Bit 10 :8 rg_wf_rx_lpf_cn_sel_bw80madc160m U RW default = 'h3 ++// Bit 14 :12 rg_wf_rx_lpf_cn_sel_bw80madc320m U RW default = 'h1 ++// Bit 18 :16 rg_wf_rx_lpf_cn_sel_bw160madc320m U RW default = 'h0 ++// Bit 22 :20 rg_wf_rx_lpf_cn_sel_man U RW default = 'h0 ++// Bit 31 rg_wf_rx_lpf_cn_sel_man_mode U RW default = 'h0 ++typedef union RG_RX_A30_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_LPF_CN_SEL_BW20MADC160M : 3; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF_RX_LPF_CN_SEL_BW40MADC160M : 3; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF_RX_LPF_CN_SEL_BW80MADC160M : 3; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF_RX_LPF_CN_SEL_BW80MADC320M : 3; ++ unsigned int rsvd_3 : 1; ++ unsigned int RG_WF_RX_LPF_CN_SEL_BW160MADC320M : 3; ++ unsigned int rsvd_4 : 1; ++ unsigned int RG_WF_RX_LPF_CN_SEL_MAN : 3; ++ unsigned int rsvd_5 : 8; ++ unsigned int RG_WF_RX_LPF_CN_SEL_MAN_MODE : 1; ++ } b; ++} RG_RX_A30_FIELD_T; ++ ++#define RG_RX_A31 (RF_D_RX_REG_BASE + 0x7c) ++// Bit 4 :0 rg_wf_rx_lpf_cnfix_sel_bw20madc160m U RW default = 'h1a ++// Bit 9 :5 rg_wf_rx_lpf_cnfix_sel_bw40madc160m U RW default = 'h1a ++// Bit 14 :10 rg_wf_rx_lpf_cnfix_sel_bw80madc160m U RW default = 'h1a ++// Bit 19 :15 rg_wf_rx_lpf_cnfix_sel_bw80madc320m U RW default = 'h1a ++// Bit 24 :20 rg_wf_rx_lpf_cnfix_sel_bw160madc320m U RW default = 'h1a ++// Bit 29 :25 rg_wf_rx_lpf_cnfix_sel_man U RW default = 'h0 ++// Bit 31 rg_wf_rx_lpf_cnfix_sel_man_mode U RW default = 'h0 ++typedef union RG_RX_A31_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_LPF_CNFIX_SEL_BW20MADC160M : 5; ++ unsigned int RG_WF_RX_LPF_CNFIX_SEL_BW40MADC160M : 5; ++ unsigned int RG_WF_RX_LPF_CNFIX_SEL_BW80MADC160M : 5; ++ unsigned int RG_WF_RX_LPF_CNFIX_SEL_BW80MADC320M : 5; ++ unsigned int RG_WF_RX_LPF_CNFIX_SEL_BW160MADC320M : 5; ++ unsigned int RG_WF_RX_LPF_CNFIX_SEL_MAN : 5; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF_RX_LPF_CNFIX_SEL_MAN_MODE : 1; ++ } b; ++} RG_RX_A31_FIELD_T; ++ ++#define RG_RX_A32 (RF_D_RX_REG_BASE + 0x80) ++// Bit 6 :0 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg1 U RW default = 'h40 ++// Bit 14 :8 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg2 U RW default = 'h40 ++// Bit 22 :16 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg3 U RW default = 'h40 ++// Bit 30 :24 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg4 U RW default = 'h40 ++typedef union RG_RX_A32_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG1 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG2 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG3 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG4 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A32_FIELD_T; ++ ++#define RG_RX_A33 (RF_D_RX_REG_BASE + 0x84) ++// Bit 6 :0 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg5 U RW default = 'h40 ++// Bit 14 :8 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg6 U RW default = 'h40 ++// Bit 22 :16 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg7 U RW default = 'h40 ++// Bit 30 :24 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg8 U RW default = 'h40 ++typedef union RG_RX_A33_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG5 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG6 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG7 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG8 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A33_FIELD_T; ++ ++#define RG_RX_A34 (RF_D_RX_REG_BASE + 0x88) ++// Bit 6 :0 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg9 U RW default = 'h40 ++// Bit 14 :8 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg10 U RW default = 'h40 ++// Bit 22 :16 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg11 U RW default = 'h40 ++// Bit 30 :24 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg12 U RW default = 'h40 ++typedef union RG_RX_A34_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG9 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG10 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG11 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG12 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A34_FIELD_T; ++ ++#define RG_RX_A35 (RF_D_RX_REG_BASE + 0x8c) ++// Bit 6 :0 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg1 U RW default = 'h40 ++// Bit 14 :8 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg2 U RW default = 'h40 ++// Bit 22 :16 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg3 U RW default = 'h40 ++// Bit 30 :24 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg4 U RW default = 'h40 ++typedef union RG_RX_A35_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG1 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG2 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG3 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG4 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A35_FIELD_T; ++ ++#define RG_RX_A36 (RF_D_RX_REG_BASE + 0x90) ++// Bit 6 :0 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg5 U RW default = 'h40 ++// Bit 14 :8 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg6 U RW default = 'h40 ++// Bit 22 :16 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg7 U RW default = 'h40 ++// Bit 30 :24 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg8 U RW default = 'h40 ++typedef union RG_RX_A36_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG5 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG6 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG7 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG8 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A36_FIELD_T; ++ ++#define RG_RX_A37 (RF_D_RX_REG_BASE + 0x94) ++// Bit 6 :0 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg9 U RW default = 'h40 ++// Bit 14 :8 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg10 U RW default = 'h40 ++// Bit 22 :16 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg11 U RW default = 'h40 ++// Bit 30 :24 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg12 U RW default = 'h40 ++typedef union RG_RX_A37_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG9 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG10 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG11 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG12 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A37_FIELD_T; ++ ++#define RG_RX_A38 (RF_D_RX_REG_BASE + 0x98) ++// Bit 6 :0 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg1 U RW default = 'h40 ++// Bit 14 :8 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg2 U RW default = 'h40 ++// Bit 22 :16 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg3 U RW default = 'h40 ++// Bit 30 :24 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg4 U RW default = 'h40 ++typedef union RG_RX_A38_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG1 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG2 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG3 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG4 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A38_FIELD_T; ++ ++#define RG_RX_A39 (RF_D_RX_REG_BASE + 0x9c) ++// Bit 6 :0 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg5 U RW default = 'h40 ++// Bit 14 :8 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg6 U RW default = 'h40 ++// Bit 22 :16 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg7 U RW default = 'h40 ++// Bit 30 :24 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg8 U RW default = 'h40 ++typedef union RG_RX_A39_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG5 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG6 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG7 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG8 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A39_FIELD_T; ++ ++#define RG_RX_A40 (RF_D_RX_REG_BASE + 0xa0) ++// Bit 6 :0 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg9 U RW default = 'h40 ++// Bit 14 :8 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg10 U RW default = 'h40 ++// Bit 22 :16 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg11 U RW default = 'h40 ++// Bit 30 :24 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg12 U RW default = 'h40 ++typedef union RG_RX_A40_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG9 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG10 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG11 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG12 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A40_FIELD_T; ++ ++#define RG_RX_A41 (RF_D_RX_REG_BASE + 0xa4) ++// Bit 6 :0 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg1 U RW default = 'h40 ++// Bit 14 :8 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg2 U RW default = 'h40 ++// Bit 22 :16 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg3 U RW default = 'h40 ++// Bit 30 :24 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg4 U RW default = 'h40 ++typedef union RG_RX_A41_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG1 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG2 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG3 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG4 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A41_FIELD_T; ++ ++#define RG_RX_A42 (RF_D_RX_REG_BASE + 0xa8) ++// Bit 6 :0 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg5 U RW default = 'h40 ++// Bit 14 :8 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg6 U RW default = 'h40 ++// Bit 22 :16 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg7 U RW default = 'h40 ++// Bit 30 :24 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg8 U RW default = 'h40 ++typedef union RG_RX_A42_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG5 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG6 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG7 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG8 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A42_FIELD_T; ++ ++#define RG_RX_A43 (RF_D_RX_REG_BASE + 0xac) ++// Bit 6 :0 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg9 U RW default = 'h40 ++// Bit 14 :8 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg10 U RW default = 'h40 ++// Bit 22 :16 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg11 U RW default = 'h40 ++// Bit 30 :24 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg12 U RW default = 'h40 ++typedef union RG_RX_A43_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG9 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG10 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG11 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG12 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A43_FIELD_T; ++ ++#define RG_RX_A44 (RF_D_RX_REG_BASE + 0xb0) ++// Bit 6 :0 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg1 U RW default = 'h40 ++// Bit 14 :8 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg2 U RW default = 'h40 ++// Bit 22 :16 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg3 U RW default = 'h40 ++// Bit 30 :24 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg4 U RW default = 'h40 ++typedef union RG_RX_A44_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG1 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG2 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG3 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG4 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A44_FIELD_T; ++ ++#define RG_RX_A45 (RF_D_RX_REG_BASE + 0xb4) ++// Bit 6 :0 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg5 U RW default = 'h40 ++// Bit 14 :8 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg6 U RW default = 'h40 ++// Bit 22 :16 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg7 U RW default = 'h40 ++// Bit 30 :24 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg8 U RW default = 'h40 ++typedef union RG_RX_A45_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG5 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG6 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG7 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG8 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A45_FIELD_T; ++ ++#define RG_RX_A46 (RF_D_RX_REG_BASE + 0xb8) ++// Bit 6 :0 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg9 U RW default = 'h40 ++// Bit 14 :8 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg10 U RW default = 'h40 ++// Bit 22 :16 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg11 U RW default = 'h40 ++// Bit 30 :24 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg12 U RW default = 'h40 ++typedef union RG_RX_A46_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG9 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG10 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG11 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG12 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A46_FIELD_T; ++ ++#define RG_RX_A47 (RF_D_RX_REG_BASE + 0xbc) ++// Bit 6 :0 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg1 U RW default = 'h40 ++// Bit 14 :8 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg2 U RW default = 'h40 ++// Bit 22 :16 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg3 U RW default = 'h40 ++// Bit 30 :24 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg4 U RW default = 'h40 ++typedef union RG_RX_A47_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG1 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG2 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG3 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG4 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A47_FIELD_T; ++ ++#define RG_RX_A48 (RF_D_RX_REG_BASE + 0xc0) ++// Bit 6 :0 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg5 U RW default = 'h40 ++// Bit 14 :8 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg6 U RW default = 'h40 ++// Bit 22 :16 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg7 U RW default = 'h40 ++// Bit 30 :24 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg8 U RW default = 'h40 ++typedef union RG_RX_A48_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG5 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG6 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG7 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG8 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A48_FIELD_T; ++ ++#define RG_RX_A49 (RF_D_RX_REG_BASE + 0xc4) ++// Bit 6 :0 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg9 U RW default = 'h40 ++// Bit 14 :8 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg10 U RW default = 'h40 ++// Bit 22 :16 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg11 U RW default = 'h40 ++// Bit 30 :24 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg12 U RW default = 'h40 ++typedef union RG_RX_A49_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG9 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG10 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG11 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG12 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A49_FIELD_T; ++ ++#define RG_RX_A50 (RF_D_RX_REG_BASE + 0xc8) ++// Bit 6 :0 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg1 U RW default = 'h40 ++// Bit 14 :8 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg2 U RW default = 'h40 ++// Bit 22 :16 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg3 U RW default = 'h40 ++// Bit 30 :24 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg4 U RW default = 'h40 ++typedef union RG_RX_A50_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG1 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG2 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG3 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG4 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A50_FIELD_T; ++ ++#define RG_RX_A51 (RF_D_RX_REG_BASE + 0xcc) ++// Bit 6 :0 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg5 U RW default = 'h40 ++// Bit 14 :8 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg6 U RW default = 'h40 ++// Bit 22 :16 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg7 U RW default = 'h40 ++// Bit 30 :24 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg8 U RW default = 'h40 ++typedef union RG_RX_A51_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG5 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG6 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG7 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG8 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A51_FIELD_T; ++ ++#define RG_RX_A52 (RF_D_RX_REG_BASE + 0xd0) ++// Bit 6 :0 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg9 U RW default = 'h40 ++// Bit 14 :8 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg10 U RW default = 'h40 ++// Bit 22 :16 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg11 U RW default = 'h40 ++// Bit 30 :24 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg12 U RW default = 'h40 ++typedef union RG_RX_A52_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG9 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG10 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG11 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG12 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A52_FIELD_T; ++ ++#define RG_RX_A53 (RF_D_RX_REG_BASE + 0xd4) ++// Bit 6 :0 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg1 U RW default = 'h40 ++// Bit 14 :8 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg2 U RW default = 'h40 ++// Bit 22 :16 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg3 U RW default = 'h40 ++// Bit 30 :24 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg4 U RW default = 'h40 ++typedef union RG_RX_A53_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG1 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG2 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG3 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG4 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A53_FIELD_T; ++ ++#define RG_RX_A54 (RF_D_RX_REG_BASE + 0xd8) ++// Bit 6 :0 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg5 U RW default = 'h40 ++// Bit 14 :8 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg6 U RW default = 'h40 ++// Bit 22 :16 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg7 U RW default = 'h40 ++// Bit 30 :24 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg8 U RW default = 'h40 ++typedef union RG_RX_A54_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG5 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG6 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG7 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG8 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A54_FIELD_T; ++ ++#define RG_RX_A55 (RF_D_RX_REG_BASE + 0xdc) ++// Bit 6 :0 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg9 U RW default = 'h40 ++// Bit 14 :8 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg10 U RW default = 'h40 ++// Bit 22 :16 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg11 U RW default = 'h40 ++// Bit 30 :24 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg12 U RW default = 'h40 ++typedef union RG_RX_A55_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG9 : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG10 : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG11 : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG12 : 7; ++ unsigned int rsvd_3 : 1; ++ } b; ++} RG_RX_A55_FIELD_T; ++ ++#define RG_RX_A56 (RF_D_RX_REG_BASE + 0xe0) ++// Bit 6 :0 rg_wf_rx_lpf_i_dcoc_sel_man U RW default = 'h40 ++// Bit 8 rg_wf_rx_lpf_i_dcoc_sel_man_mode U RW default = 'h0 ++// Bit 22 :16 rg_wf_rx_lpf_q_dcoc_sel_man U RW default = 'h40 ++// Bit 24 rg_wf_rx_lpf_q_dcoc_sel_man_mode U RW default = 'h0 ++typedef union RG_RX_A56_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_LPF_I_DCOC_SEL_MAN : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF_RX_LPF_I_DCOC_SEL_MAN_MODE : 1; ++ unsigned int rsvd_1 : 7; ++ unsigned int RG_WF_RX_LPF_Q_DCOC_SEL_MAN : 7; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF_RX_LPF_Q_DCOC_SEL_MAN_MODE : 1; ++ unsigned int rsvd_3 : 7; ++ } b; ++} RG_RX_A56_FIELD_T; ++ ++#define RG_RX_A57 (RF_D_RX_REG_BASE + 0xe4) ++// Bit 1 :0 rg_wf_rx_rck_t1 U RW default = 'h0 ++// Bit 3 :2 rg_wf_rx_rck_t2 U RW default = 'h0 ++// Bit 5 :4 rg_wf_rx_rck_t3 U RW default = 'h0 ++// Bit 7 :6 rg_wf_rx_rck_t4 U RW default = 'h0 ++// Bit 9 :8 rg_wf_rx_rck_t5 U RW default = 'h0 ++// Bit 11 :10 rg_wf_rx_rck_t6 U RW default = 'h0 ++// Bit 22 :20 rg_wf_rx_rck_refsel_man U RW default = 'h1 ++// Bit 24 rg_wf_rx_rck_refsel_man_mode U RW default = 'h0 ++// Bit 31 rg_wf_rx_rck_cali_en U RW default = 'h0 ++typedef union RG_RX_A57_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_RCK_T1 : 2; ++ unsigned int RG_WF_RX_RCK_T2 : 2; ++ unsigned int RG_WF_RX_RCK_T3 : 2; ++ unsigned int RG_WF_RX_RCK_T4 : 2; ++ unsigned int RG_WF_RX_RCK_T5 : 2; ++ unsigned int RG_WF_RX_RCK_T6 : 2; ++ unsigned int rsvd_0 : 8; ++ unsigned int RG_WF_RX_RCK_REFSEL_MAN : 3; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF_RX_RCK_REFSEL_MAN_MODE : 1; ++ unsigned int rsvd_2 : 6; ++ unsigned int RG_WF_RX_RCK_CALI_EN : 1; ++ } b; ++} RG_RX_A57_FIELD_T; ++ ++#define RG_RX_A58 (RF_D_RX_REG_BASE + 0xe8) ++// Bit 3 :0 rg_wf_rx_lpf_rck_ioffset_bw20m U RW default = 'h0 ++// Bit 7 :4 rg_wf_rx_lpf_rck_ioffset_bw40m U RW default = 'h0 ++// Bit 11 :8 rg_wf_rx_lpf_rck_ioffset_bw80m U RW default = 'h0 ++// Bit 15 :12 rg_wf_rx_lpf_rck_ioffset_bw160m U RW default = 'h0 ++// Bit 26 :20 rg_wf_rx_lpf_ctune_isel_man U RW default = 'h0 ++// Bit 31 rg_wf_rx_lpf_ctune_isel_man_mode U RW default = 'h0 ++typedef union RG_RX_A58_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_LPF_RCK_IOFFSET_BW20M : 4; ++ unsigned int RG_WF_RX_LPF_RCK_IOFFSET_BW40M : 4; ++ unsigned int RG_WF_RX_LPF_RCK_IOFFSET_BW80M : 4; ++ unsigned int RG_WF_RX_LPF_RCK_IOFFSET_BW160M : 4; ++ unsigned int rsvd_0 : 4; ++ unsigned int RG_WF_RX_LPF_CTUNE_ISEL_MAN : 7; ++ unsigned int rsvd_1 : 4; ++ unsigned int RG_WF_RX_LPF_CTUNE_ISEL_MAN_MODE : 1; ++ } b; ++} RG_RX_A58_FIELD_T; ++ ++#define RG_RX_A59 (RF_D_RX_REG_BASE + 0xec) ++// Bit 3 :0 rg_wf_rx_lpf_rck_qoffset_bw20m U RW default = 'h0 ++// Bit 7 :4 rg_wf_rx_lpf_rck_qoffset_bw40m U RW default = 'h0 ++// Bit 11 :8 rg_wf_rx_lpf_rck_qoffset_bw80m U RW default = 'h0 ++// Bit 15 :12 rg_wf_rx_lpf_rck_qoffset_bw160m U RW default = 'h0 ++// Bit 26 :20 rg_wf_rx_lpf_ctune_qsel_man U RW default = 'h0 ++// Bit 31 rg_wf_rx_lpf_ctune_qsel_man_mode U RW default = 'h0 ++typedef union RG_RX_A59_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_LPF_RCK_QOFFSET_BW20M : 4; ++ unsigned int RG_WF_RX_LPF_RCK_QOFFSET_BW40M : 4; ++ unsigned int RG_WF_RX_LPF_RCK_QOFFSET_BW80M : 4; ++ unsigned int RG_WF_RX_LPF_RCK_QOFFSET_BW160M : 4; ++ unsigned int rsvd_0 : 4; ++ unsigned int RG_WF_RX_LPF_CTUNE_QSEL_MAN : 7; ++ unsigned int rsvd_1 : 4; ++ unsigned int RG_WF_RX_LPF_CTUNE_QSEL_MAN_MODE : 1; ++ } b; ++} RG_RX_A59_FIELD_T; ++ ++#define RG_RX_A60 (RF_D_RX_REG_BASE + 0xf0) ++// Bit 3 :0 rg_wf_rx_tia_rck_ioffset U RW default = 'h0 ++// Bit 10 :4 rg_wf_rx_tia_ctune_isel_man U RW default = 'h0 ++// Bit 15 rg_wf_rx_tia_ctune_isel_man_mode U RW default = 'h0 ++// Bit 19 :16 rg_wf_rx_tia_rck_qoffset U RW default = 'h0 ++// Bit 26 :20 rg_wf_rx_tia_ctune_qsel_man U RW default = 'h0 ++// Bit 31 rg_wf_rx_tia_ctune_qsel_man_mode U RW default = 'h0 ++typedef union RG_RX_A60_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_TIA_RCK_IOFFSET : 4; ++ unsigned int RG_WF_RX_TIA_CTUNE_ISEL_MAN : 7; ++ unsigned int rsvd_0 : 4; ++ unsigned int RG_WF_RX_TIA_CTUNE_ISEL_MAN_MODE : 1; ++ unsigned int RG_WF_RX_TIA_RCK_QOFFSET : 4; ++ unsigned int RG_WF_RX_TIA_CTUNE_QSEL_MAN : 7; ++ unsigned int rsvd_1 : 4; ++ unsigned int RG_WF_RX_TIA_CTUNE_QSEL_MAN_MODE : 1; ++ } b; ++} RG_RX_A60_FIELD_T; ++ ++#define RG_RX_A61 (RF_D_RX_REG_BASE + 0xf4) ++// Bit 3 :0 rg_wf_rx_lpf_notch_rck_offset_adc160m U RW default = 'h0 ++// Bit 10 :4 rg_wf_rx_lpf_notch_ctune_sel_man U RW default = 'h0 ++// Bit 15 rg_wf_rx_lpf_notch_ctune_sel_man_mode U RW default = 'h0 ++// Bit 19 :16 rg_wf_rx_lpf_notch_rck_offset_adc320m U RW default = 'h0 ++typedef union RG_RX_A61_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_LPF_NOTCH_RCK_OFFSET_ADC160M : 4; ++ unsigned int RG_WF_RX_LPF_NOTCH_CTUNE_SEL_MAN : 7; ++ unsigned int rsvd_0 : 4; ++ unsigned int RG_WF_RX_LPF_NOTCH_CTUNE_SEL_MAN_MODE : 1; ++ unsigned int RG_WF_RX_LPF_NOTCH_RCK_OFFSET_ADC320M : 4; ++ unsigned int rsvd_1 : 12; ++ } b; ++} RG_RX_A61_FIELD_T; ++ ++#define RG_RX_A62 (RF_D_RX_REG_BASE + 0xf8) ++// Bit 3 :0 rg_wf_rx_rssipga_rck_ioffset U RW default = 'h0 ++// Bit 10 :4 rg_wf_rx_rssipga_ctune_isel_man U RW default = 'h0 ++// Bit 15 rg_wf_rx_rssipga_ctune_isel_man_mode U RW default = 'h0 ++// Bit 19 :16 rg_wf_rx_rssipga_rck_qoffset U RW default = 'h0 ++// Bit 26 :20 rg_wf_rx_rssipga_ctune_qsel_man U RW default = 'h0 ++// Bit 31 rg_wf_rx_rssipga_ctune_qsel_man_mode U RW default = 'h0 ++typedef union RG_RX_A62_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_RSSIPGA_RCK_IOFFSET : 4; ++ unsigned int RG_WF_RX_RSSIPGA_CTUNE_ISEL_MAN : 7; ++ unsigned int rsvd_0 : 4; ++ unsigned int RG_WF_RX_RSSIPGA_CTUNE_ISEL_MAN_MODE : 1; ++ unsigned int RG_WF_RX_RSSIPGA_RCK_QOFFSET : 4; ++ unsigned int RG_WF_RX_RSSIPGA_CTUNE_QSEL_MAN : 7; ++ unsigned int rsvd_1 : 4; ++ unsigned int RG_WF_RX_RSSIPGA_CTUNE_QSEL_MAN_MODE : 1; ++ } b; ++} RG_RX_A62_FIELD_T; ++ ++#define RG_RX_A63 (RF_D_RX_REG_BASE + 0xfc) ++// Bit 6 :0 ro_wf_rx_rck U RO default = 'h0 ++// Bit 8 ro_wf_rx_rck_vld U RO default = 'h0 ++typedef union RG_RX_A63_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RO_WF_RX_RCK : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RO_WF_RX_RCK_VLD : 1; ++ unsigned int rsvd_1 : 23; ++ } b; ++} RG_RX_A63_FIELD_T; ++ ++#define RG_RX_A64 (RF_D_RX_REG_BASE + 0x100) ++// Bit 0 rg_wf_rx_rssipga_sca_en U RW default = 'h1 ++// Bit 5 :1 rg_wf_rx_rssipga_cfix_sel U RW default = 'h1a ++// Bit 8 :6 rg_wf_rx_rssipga_ictrl U RW default = 'h3 ++// Bit 11 :9 rg_wf_rx_rssipga_ictrl_agclock U RW default = 'h0 ++// Bit 15 :12 rg_wf_rx_rssipga_drvctrl U RW default = 'h3 ++// Bit 19 :16 rg_wf_rx_rssipga_drvctrl_agclock U RW default = 'h0 ++// Bit 21 :20 rg_wf_rx_rssipga_drv U RW default = 'h1 ++// Bit 23 :22 rg_wf_rx_rssipga_drv_agclock U RW default = 'h0 ++// Bit 26 :24 rg_wf_rx_rssipga_vcmsel U RW default = 'h4 ++// Bit 29 :27 rg_wf_rx_rssipga_gain U RW default = 'h0 ++typedef union RG_RX_A64_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_RSSIPGA_SCA_EN : 1; ++ unsigned int RG_WF_RX_RSSIPGA_CFIX_SEL : 5; ++ unsigned int RG_WF_RX_RSSIPGA_ICTRL : 3; ++ unsigned int RG_WF_RX_RSSIPGA_ICTRL_AGCLOCK : 3; ++ unsigned int RG_WF_RX_RSSIPGA_DRVCTRL : 4; ++ unsigned int RG_WF_RX_RSSIPGA_DRVCTRL_AGCLOCK : 4; ++ unsigned int RG_WF_RX_RSSIPGA_DRV : 2; ++ unsigned int RG_WF_RX_RSSIPGA_DRV_AGCLOCK : 2; ++ unsigned int RG_WF_RX_RSSIPGA_VCMSEL : 3; ++ unsigned int RG_WF_RX_RSSIPGA_GAIN : 3; ++ unsigned int rsvd_0 : 2; ++ } b; ++} RG_RX_A64_FIELD_T; ++ ++#define RG_RX_A65 (RF_D_RX_REG_BASE + 0x104) ++// Bit 0 rg_wf_rx_irrcalfrom_tx_en U RW default = 'h1 ++// Bit 3 :1 rg_wf5g_rx_irrcal_buf_ictrl U RW default = 'h3 ++// Bit 6 :4 rg_wf5g_rx_lna_cal_att U RW default = 'h0 ++// Bit 9 :7 rg_wf2g_rx_irrcal_buf_ictrl U RW default = 'h3 ++// Bit 12 :10 rg_wf2g_rx_lna_cal_att U RW default = 'h2 ++// Bit 15 :13 rg_wf_rx_gm_vcmsel U RW default = 'h4 ++typedef union RG_RX_A65_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_IRRCALFROM_TX_EN : 1; ++ unsigned int RG_WF5G_RX_IRRCAL_BUF_ICTRL : 3; ++ unsigned int RG_WF5G_RX_LNA_CAL_ATT : 3; ++ unsigned int RG_WF2G_RX_IRRCAL_BUF_ICTRL : 3; ++ unsigned int RG_WF2G_RX_LNA_CAL_ATT : 3; ++ unsigned int RG_WF_RX_GM_VCMSEL : 3; ++ unsigned int rsvd_0 : 16; ++ } b; ++} RG_RX_A65_FIELD_T; ++ ++#define RG_RX_A66 (RF_D_RX_REG_BASE + 0x108) ++// Bit 1 :0 rg_wf5g_rx_dpd_att_ctrl U RW default = 'h1 ++// Bit 4 :2 rg_wf5g_rx_dpd_gm_gain U RW default = 'h7 ++// Bit 7 :5 rg_wf5g_rx_dpd_gm_ictrl U RW default = 'h3 ++// Bit 11 :8 rg_wf5g_rx_dpd_mxr_lodrv_ictrl U RW default = 'h3 ++// Bit 14 :12 rg_wf5g_rx_gm_ictrl U RW default = 'h3 ++// Bit 18 :15 rg_wf5g_rx_mxr_lodrv_ictrl U RW default = 'h3 ++// Bit 22 :19 rg_wf5g_rx_mxr_vbsel U RW default = 'h2 ++// Bit 25 :23 rg_wf5g_rx_mxr_vcmsel U RW default = 'h3 ++typedef union RG_RX_A66_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_RX_DPD_ATT_CTRL : 2; ++ unsigned int RG_WF5G_RX_DPD_GM_GAIN : 3; ++ unsigned int RG_WF5G_RX_DPD_GM_ICTRL : 3; ++ unsigned int RG_WF5G_RX_DPD_MXR_LODRV_ICTRL : 4; ++ unsigned int RG_WF5G_RX_GM_ICTRL : 3; ++ unsigned int RG_WF5G_RX_MXR_LODRV_ICTRL : 4; ++ unsigned int RG_WF5G_RX_MXR_VBSEL : 4; ++ unsigned int RG_WF5G_RX_MXR_VCMSEL : 3; ++ unsigned int rsvd_0 : 6; ++ } b; ++} RG_RX_A66_FIELD_T; ++ ++#define RG_RX_A67 (RF_D_RX_REG_BASE + 0x10c) ++// Bit 1 rg_wf_rx_tia_sca_en U RW default = 'h1 ++// Bit 16 :14 rg_wf_rx_tia_ictrl U RW default = 'h3 ++// Bit 19 :17 rg_wf_rx_tia_drvctrl U RW default = 'h3 ++typedef union RG_RX_A67_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF_RX_TIA_SCA_EN : 1; ++ unsigned int rsvd_1 : 12; ++ unsigned int RG_WF_RX_TIA_ICTRL : 3; ++ unsigned int RG_WF_RX_TIA_DRVCTRL : 3; ++ unsigned int rsvd_2 : 12; ++ } b; ++} RG_RX_A67_FIELD_T; ++ ++#define RG_RX_A68 (RF_D_RX_REG_BASE + 0x110) ++// Bit 0 rg_wf_rx_lpf_sra1_en U RW default = 'h1 ++// Bit 1 rg_wf_rx_lpf_sra2_en U RW default = 'h1 ++// Bit 2 rg_wf_rx_lpf_sra3_en U RW default = 'h1 ++// Bit 3 rg_wf_rx_lpf_sra4_en U RW default = 'h1 ++// Bit 4 rg_wf_rx_lpf_sca1_en U RW default = 'h1 ++// Bit 5 rg_wf_rx_lpf_sca2_en U RW default = 'h1 ++// Bit 6 rg_wf_rx_lpf_rn1_en U RW default = 'h1 ++// Bit 7 rg_wf_rx_lpf_notch_en U RW default = 'h1 ++// Bit 8 rg_wf_rx_lpf_op1_en U RW default = 'h1 ++// Bit 9 rg_wf_rx_lpf_op2_en U RW default = 'h1 ++// Bit 10 rg_wf5g_txlpbk2tia_en U RW default = 'h0 ++// Bit 11 rg_wf2g_txlpbk2tia_en U RW default = 'h0 ++// Bit 12 rg_wf_rx_adcbuf_en U RW default = 'h0 ++// Bit 16 :13 rg_wf_rx_adcbuf_sra_sel U RW default = 'h0 ++typedef union RG_RX_A68_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_LPF_SRA1_EN : 1; ++ unsigned int RG_WF_RX_LPF_SRA2_EN : 1; ++ unsigned int RG_WF_RX_LPF_SRA3_EN : 1; ++ unsigned int RG_WF_RX_LPF_SRA4_EN : 1; ++ unsigned int RG_WF_RX_LPF_SCA1_EN : 1; ++ unsigned int RG_WF_RX_LPF_SCA2_EN : 1; ++ unsigned int RG_WF_RX_LPF_RN1_EN : 1; ++ unsigned int RG_WF_RX_LPF_NOTCH_EN : 1; ++ unsigned int RG_WF_RX_LPF_OP1_EN : 1; ++ unsigned int RG_WF_RX_LPF_OP2_EN : 1; ++ unsigned int RG_WF5G_TXLPBK2TIA_EN : 1; ++ unsigned int RG_WF2G_TXLPBK2TIA_EN : 1; ++ unsigned int RG_WF_RX_ADCBUF_EN : 1; ++ unsigned int RG_WF_RX_ADCBUF_SRA_SEL : 4; ++ unsigned int rsvd_0 : 15; ++ } b; ++} RG_RX_A68_FIELD_T; ++ ++#define RG_RX_A69 (RF_D_RX_REG_BASE + 0x114) ++// Bit 2 :0 rg_wf_rx_vcmsel U RW default = 'h4 ++// Bit 5 :3 rg_wf_rx_lpf_op1_drvctrl U RW default = 'h3 ++// Bit 9 :6 rg_wf_rx_lpf_op2_drvctrl U RW default = 'h3 ++typedef union RG_RX_A69_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_VCMSEL : 3; ++ unsigned int RG_WF_RX_LPF_OP1_DRVCTRL : 3; ++ unsigned int RG_WF_RX_LPF_OP2_DRVCTRL : 4; ++ unsigned int rsvd_0 : 22; ++ } b; ++} RG_RX_A69_FIELD_T; ++ ++#define RG_RX_A71 (RF_D_RX_REG_BASE + 0x11c) ++// Bit 0 rg_wf_rx_fe_tp_en U RW default = 'h0 ++// Bit 8 :1 rg_wf_rx_fe_tp_sel U RW default = 'h0 ++// Bit 9 rg_wf_rtx_abb_tp_en U RW default = 'h0 ++// Bit 17 :10 rg_wf_rtx_abb_tp_sel U RW default = 'h0 ++// Bit 31 :18 rg_wf_rx_reserved8 U RW default = 'h0 ++typedef union RG_RX_A71_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_FE_TP_EN : 1; ++ unsigned int RG_WF_RX_FE_TP_SEL : 8; ++ unsigned int RG_WF_RTX_ABB_TP_EN : 1; ++ unsigned int RG_WF_RTX_ABB_TP_SEL : 8; ++ unsigned int RG_WF_RX_RESERVED8 : 14; ++ } b; ++} RG_RX_A71_FIELD_T; ++ ++#define RG_RX_A72 (RF_D_RX_REG_BASE + 0x120) ++// Bit 31 :0 rg_wf_rx_rsv0 U RW default = 'h0 ++typedef union RG_RX_A72_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_RSV0 : 32; ++ } b; ++} RG_RX_A72_FIELD_T; ++ ++#define RG_RX_A73 (RF_D_RX_REG_BASE + 0x124) ++// Bit 31 :0 rg_wf_rx_rsv1 U RW default = 'h0 ++typedef union RG_RX_A73_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_RSV1 : 32; ++ } b; ++} RG_RX_A73_FIELD_T; ++ ++#define RG_RX_A74 (RF_D_RX_REG_BASE + 0x128) ++// Bit 2 :0 rg_wf_rx_lpf_dcoc_rsel_bw20m U RW default = 'h3 ++// Bit 5 :3 rg_wf_rx_lpf_dcoc_rsel_bw40m U RW default = 'h3 ++// Bit 8 :6 rg_wf_rx_lpf_dcoc_rsel_bw80m U RW default = 'h0 ++// Bit 11 :9 rg_wf_rx_lpf_dcoc_rsel_bw160m U RW default = 'h0 ++// Bit 14 :12 rg_wf_rx_lpf_dcoc_rgsel_bw20m U RW default = 'h3 ++// Bit 17 :15 rg_wf_rx_lpf_dcoc_rgsel_bw40m U RW default = 'h3 ++// Bit 20 :18 rg_wf_rx_lpf_dcoc_rgsel_bw80m U RW default = 'h0 ++// Bit 23 :21 rg_wf_rx_lpf_dcoc_rgsel_bw160m U RW default = 'h0 ++// Bit 26 :24 rg_wf_rx_lpf_dcoc_rsel_man U RW default = 'h0 ++// Bit 27 rg_wf_rx_lpf_dcoc_rsel_man_mode U RW default = 'h0 ++// Bit 30 :28 rg_wf_rx_lpf_dcoc_rgsel_man U RW default = 'h0 ++// Bit 31 rg_wf_rx_lpf_dcoc_rgsel_man_mode U RW default = 'h0 ++typedef union RG_RX_A74_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_LPF_DCOC_RSEL_BW20M : 3; ++ unsigned int RG_WF_RX_LPF_DCOC_RSEL_BW40M : 3; ++ unsigned int RG_WF_RX_LPF_DCOC_RSEL_BW80M : 3; ++ unsigned int RG_WF_RX_LPF_DCOC_RSEL_BW160M : 3; ++ unsigned int RG_WF_RX_LPF_DCOC_RGSEL_BW20M : 3; ++ unsigned int RG_WF_RX_LPF_DCOC_RGSEL_BW40M : 3; ++ unsigned int RG_WF_RX_LPF_DCOC_RGSEL_BW80M : 3; ++ unsigned int RG_WF_RX_LPF_DCOC_RGSEL_BW160M : 3; ++ unsigned int RG_WF_RX_LPF_DCOC_RSEL_MAN : 3; ++ unsigned int RG_WF_RX_LPF_DCOC_RSEL_MAN_MODE : 1; ++ unsigned int RG_WF_RX_LPF_DCOC_RGSEL_MAN : 3; ++ unsigned int RG_WF_RX_LPF_DCOC_RGSEL_MAN_MODE : 1; ++ } b; ++} RG_RX_A74_FIELD_T; ++ ++#define RG_RX_A75 (RF_D_RX_REG_BASE + 0x12c) ++// Bit 2 :0 rg_wf_rx_lpf_op1_ictrl_bw20m U RW default = 'h1 ++// Bit 5 :3 rg_wf_rx_lpf_op1_ictrl_bw40m U RW default = 'h2 ++// Bit 8 :6 rg_wf_rx_lpf_op1_ictrl_bw80m U RW default = 'h3 ++// Bit 11 :9 rg_wf_rx_lpf_op1_ictrl_bw160m U RW default = 'h4 ++// Bit 14 :12 rg_wf_rx_lpf_op1_ictrl_man U RW default = 'h0 ++// Bit 15 rg_wf_rx_lpf_op1_ictrl_man_mode U RW default = 'h0 ++// Bit 17 :16 rg_wf_rx_lpf_op1_drv_bw20m U RW default = 'h0 ++// Bit 19 :18 rg_wf_rx_lpf_op1_drv_bw40m U RW default = 'h1 ++// Bit 21 :20 rg_wf_rx_lpf_op1_drv_bw80m U RW default = 'h2 ++// Bit 23 :22 rg_wf_rx_lpf_op1_drv_bw160m U RW default = 'h3 ++// Bit 25 :24 rg_wf_rx_lpf_op1_drv_man U RW default = 'h0 ++// Bit 26 rg_wf_rx_lpf_op1_drv_man_mode U RW default = 'h0 ++typedef union RG_RX_A75_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_LPF_OP1_ICTRL_BW20M : 3; ++ unsigned int RG_WF_RX_LPF_OP1_ICTRL_BW40M : 3; ++ unsigned int RG_WF_RX_LPF_OP1_ICTRL_BW80M : 3; ++ unsigned int RG_WF_RX_LPF_OP1_ICTRL_BW160M : 3; ++ unsigned int RG_WF_RX_LPF_OP1_ICTRL_MAN : 3; ++ unsigned int RG_WF_RX_LPF_OP1_ICTRL_MAN_MODE : 1; ++ unsigned int RG_WF_RX_LPF_OP1_DRV_BW20M : 2; ++ unsigned int RG_WF_RX_LPF_OP1_DRV_BW40M : 2; ++ unsigned int RG_WF_RX_LPF_OP1_DRV_BW80M : 2; ++ unsigned int RG_WF_RX_LPF_OP1_DRV_BW160M : 2; ++ unsigned int RG_WF_RX_LPF_OP1_DRV_MAN : 2; ++ unsigned int RG_WF_RX_LPF_OP1_DRV_MAN_MODE : 1; ++ unsigned int rsvd_0 : 5; ++ } b; ++} RG_RX_A75_FIELD_T; ++ ++#define RG_RX_A76 (RF_D_RX_REG_BASE + 0x130) ++// Bit 2 :0 rg_wf_rx_lpf_op2_ictrl_bw20m U RW default = 'h1 ++// Bit 5 :3 rg_wf_rx_lpf_op2_ictrl_bw40m U RW default = 'h2 ++// Bit 8 :6 rg_wf_rx_lpf_op2_ictrl_bw80m U RW default = 'h3 ++// Bit 11 :9 rg_wf_rx_lpf_op2_ictrl_bw160m U RW default = 'h4 ++// Bit 14 :12 rg_wf_rx_lpf_op2_ictrl_man U RW default = 'h0 ++// Bit 15 rg_wf_rx_lpf_op2_ictrl_man_mode U RW default = 'h0 ++// Bit 17 :16 rg_wf_rx_lpf_op2_drv_bw20m U RW default = 'h1 ++// Bit 19 :18 rg_wf_rx_lpf_op2_drv_bw40m U RW default = 'h1 ++// Bit 21 :20 rg_wf_rx_lpf_op2_drv_bw80m U RW default = 'h1 ++// Bit 23 :22 rg_wf_rx_lpf_op2_drv_bw160m U RW default = 'h2 ++// Bit 25 :24 rg_wf_rx_lpf_op2_drv_man U RW default = 'h0 ++// Bit 26 rg_wf_rx_lpf_op2_drv_man_mode U RW default = 'h0 ++typedef union RG_RX_A76_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_LPF_OP2_ICTRL_BW20M : 3; ++ unsigned int RG_WF_RX_LPF_OP2_ICTRL_BW40M : 3; ++ unsigned int RG_WF_RX_LPF_OP2_ICTRL_BW80M : 3; ++ unsigned int RG_WF_RX_LPF_OP2_ICTRL_BW160M : 3; ++ unsigned int RG_WF_RX_LPF_OP2_ICTRL_MAN : 3; ++ unsigned int RG_WF_RX_LPF_OP2_ICTRL_MAN_MODE : 1; ++ unsigned int RG_WF_RX_LPF_OP2_DRV_BW20M : 2; ++ unsigned int RG_WF_RX_LPF_OP2_DRV_BW40M : 2; ++ unsigned int RG_WF_RX_LPF_OP2_DRV_BW80M : 2; ++ unsigned int RG_WF_RX_LPF_OP2_DRV_BW160M : 2; ++ unsigned int RG_WF_RX_LPF_OP2_DRV_MAN : 2; ++ unsigned int RG_WF_RX_LPF_OP2_DRV_MAN_MODE : 1; ++ unsigned int rsvd_0 : 5; ++ } b; ++} RG_RX_A76_FIELD_T; ++ ++#define RG_RX_A77 (RF_D_RX_REG_BASE + 0x134) ++// Bit 1 :0 rg_wf_rx_lpf_op1_rcc_lg U RW default = 'h3 ++// Bit 3 :2 rg_wf_rx_lpf_op1_rcc_mg U RW default = 'h2 ++// Bit 5 :4 rg_wf_rx_lpf_op1_rcc_hg U RW default = 'h1 ++// Bit 7 :6 rg_wf_rx_lpf_op1_rcc_man U RW default = 'h0 ++// Bit 8 rg_wf_rx_lpf_op1_rcc_man_mode U RW default = 'h0 ++// Bit 10 :9 rg_wf_rx_lpf_op1_rcm_lg U RW default = 'h1 ++// Bit 12 :11 rg_wf_rx_lpf_op1_rcm_mg U RW default = 'h2 ++// Bit 14 :13 rg_wf_rx_lpf_op1_rcm_hg U RW default = 'h3 ++// Bit 16 :15 rg_wf_rx_lpf_op1_rcm_man U RW default = 'h0 ++// Bit 17 rg_wf_rx_lpf_op1_rcm_man_mode U RW default = 'h0 ++// Bit 19 :18 rg_wf_rx_lpf_op2_rcc_bw20m U RW default = 'h3 ++// Bit 21 :20 rg_wf_rx_lpf_op2_rcc_bw40m U RW default = 'h2 ++// Bit 23 :22 rg_wf_rx_lpf_op2_rcc_bw80m U RW default = 'h1 ++// Bit 25 :24 rg_wf_rx_lpf_op2_rcc_bw160m U RW default = 'h1 ++// Bit 27 :26 rg_wf_rx_lpf_op2_rcc_man U RW default = 'h0 ++// Bit 28 rg_wf_rx_lpf_op2_rcc_man_mode U RW default = 'h0 ++typedef union RG_RX_A77_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_LPF_OP1_RCC_LG : 2; ++ unsigned int RG_WF_RX_LPF_OP1_RCC_MG : 2; ++ unsigned int RG_WF_RX_LPF_OP1_RCC_HG : 2; ++ unsigned int RG_WF_RX_LPF_OP1_RCC_MAN : 2; ++ unsigned int RG_WF_RX_LPF_OP1_RCC_MAN_MODE : 1; ++ unsigned int RG_WF_RX_LPF_OP1_RCM_LG : 2; ++ unsigned int RG_WF_RX_LPF_OP1_RCM_MG : 2; ++ unsigned int RG_WF_RX_LPF_OP1_RCM_HG : 2; ++ unsigned int RG_WF_RX_LPF_OP1_RCM_MAN : 2; ++ unsigned int RG_WF_RX_LPF_OP1_RCM_MAN_MODE : 1; ++ unsigned int RG_WF_RX_LPF_OP2_RCC_BW20M : 2; ++ unsigned int RG_WF_RX_LPF_OP2_RCC_BW40M : 2; ++ unsigned int RG_WF_RX_LPF_OP2_RCC_BW80M : 2; ++ unsigned int RG_WF_RX_LPF_OP2_RCC_BW160M : 2; ++ unsigned int RG_WF_RX_LPF_OP2_RCC_MAN : 2; ++ unsigned int RG_WF_RX_LPF_OP2_RCC_MAN_MODE : 1; ++ unsigned int rsvd_0 : 3; ++ } b; ++} RG_RX_A77_FIELD_T; ++ ++#define RG_RX_A78 (RF_D_RX_REG_BASE + 0x138) ++// Bit 10 :9 rg_wf_rx_lpf_op2_rcm_bw20m U RW default = 'h3 ++// Bit 12 :11 rg_wf_rx_lpf_op2_rcm_bw40m U RW default = 'h3 ++// Bit 14 :13 rg_wf_rx_lpf_op2_rcm_bw80m U RW default = 'h3 ++// Bit 16 :15 rg_wf_rx_lpf_op2_rcm_bw160m U RW default = 'h3 ++// Bit 18 :17 rg_wf_rx_lpf_op2_rcm_man U RW default = 'h0 ++// Bit 19 rg_wf_rx_lpf_op2_rcm_man_mode U RW default = 'h0 ++// Bit 31 rg_wf2g_rx_lna_slice_man_mode U RW default = 'h0 ++typedef union RG_RX_A78_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rsvd_0 : 9; ++ unsigned int RG_WF_RX_LPF_OP2_RCM_BW20M : 2; ++ unsigned int RG_WF_RX_LPF_OP2_RCM_BW40M : 2; ++ unsigned int RG_WF_RX_LPF_OP2_RCM_BW80M : 2; ++ unsigned int RG_WF_RX_LPF_OP2_RCM_BW160M : 2; ++ unsigned int RG_WF_RX_LPF_OP2_RCM_MAN : 2; ++ unsigned int RG_WF_RX_LPF_OP2_RCM_MAN_MODE : 1; ++ unsigned int rsvd_1 : 11; ++ unsigned int RG_WF2G_RX_LNA_SLICE_MAN_MODE : 1; ++ } b; ++} RG_RX_A78_FIELD_T; ++ ++#define RG_RX_A79 (RF_D_RX_REG_BASE + 0x13c) ++// Bit 2 :0 rg_wf2g_rx_lna_ictrl_g1 U RW default = 'h3 ++// Bit 6 :4 rg_wf2g_rx_lna_ictrl_g2 U RW default = 'h4 ++// Bit 10 :8 rg_wf2g_rx_lna_ictrl_g3 U RW default = 'h4 ++// Bit 14 :12 rg_wf2g_rx_lna_ictrl_g4 U RW default = 'h4 ++// Bit 18 :16 rg_wf2g_rx_lna_ictrl_g5 U RW default = 'h2 ++// Bit 22 :20 rg_wf2g_rx_lna_ictrl_g6 U RW default = 'h2 ++// Bit 26 :24 rg_wf2g_rx_lna_ictrl_g7 U RW default = 'h3 ++// Bit 30 :28 rg_wf2g_rx_lna_ictrl_man U RW default = 'h0 ++// Bit 31 rg_wf2g_rx_lna_ictrl_man_mode U RW default = 'h0 ++typedef union RG_RX_A79_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LNA_ICTRL_G1 : 3; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF2G_RX_LNA_ICTRL_G2 : 3; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF2G_RX_LNA_ICTRL_G3 : 3; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF2G_RX_LNA_ICTRL_G4 : 3; ++ unsigned int rsvd_3 : 1; ++ unsigned int RG_WF2G_RX_LNA_ICTRL_G5 : 3; ++ unsigned int rsvd_4 : 1; ++ unsigned int RG_WF2G_RX_LNA_ICTRL_G6 : 3; ++ unsigned int rsvd_5 : 1; ++ unsigned int RG_WF2G_RX_LNA_ICTRL_G7 : 3; ++ unsigned int rsvd_6 : 1; ++ unsigned int RG_WF2G_RX_LNA_ICTRL_MAN : 3; ++ unsigned int RG_WF2G_RX_LNA_ICTRL_MAN_MODE : 1; ++ } b; ++} RG_RX_A79_FIELD_T; ++ ++#define RG_RX_A80 (RF_D_RX_REG_BASE + 0x140) ++// Bit 7 :0 rg_wf2g_rx_lna_slice_g1 U RW default = 'h49 ++// Bit 15 :8 rg_wf2g_rx_lna_slice_g2 U RW default = 'h92 ++// Bit 23 :16 rg_wf2g_rx_lna_slice_g3 U RW default = 'h93 ++// Bit 31 :24 rg_wf2g_rx_lna_slice_g4 U RW default = 'ha ++typedef union RG_RX_A80_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LNA_SLICE_G1 : 8; ++ unsigned int RG_WF2G_RX_LNA_SLICE_G2 : 8; ++ unsigned int RG_WF2G_RX_LNA_SLICE_G3 : 8; ++ unsigned int RG_WF2G_RX_LNA_SLICE_G4 : 8; ++ } b; ++} RG_RX_A80_FIELD_T; ++ ++#define RG_RX_A81 (RF_D_RX_REG_BASE + 0x144) ++// Bit 7 :0 rg_wf2g_rx_lna_slice_g5 U RW default = 'h1a ++// Bit 15 :8 rg_wf2g_rx_lna_slice_g6 U RW default = 'h7b ++// Bit 23 :16 rg_wf2g_rx_lna_slice_g7 U RW default = 'hfa ++// Bit 31 :24 rg_wf2g_rx_lna_slice_man U RW default = 'h0 ++typedef union RG_RX_A81_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LNA_SLICE_G5 : 8; ++ unsigned int RG_WF2G_RX_LNA_SLICE_G6 : 8; ++ unsigned int RG_WF2G_RX_LNA_SLICE_G7 : 8; ++ unsigned int RG_WF2G_RX_LNA_SLICE_MAN : 8; ++ } b; ++} RG_RX_A81_FIELD_T; ++ ++#define RG_RX_A82 (RF_D_RX_REG_BASE + 0x148) ++// Bit 4 :0 rg_wf2g_rx_lna_rfb_g1 U RW default = 'h0 ++// Bit 9 :5 rg_wf2g_rx_lna_rfb_g2 U RW default = 'h0 ++// Bit 14 :10 rg_wf2g_rx_lna_rfb_g3 U RW default = 'h0 ++// Bit 19 :15 rg_wf2g_rx_lna_rfb_g4 U RW default = 'h2 ++// Bit 24 :20 rg_wf2g_rx_lna_rfb_g5 U RW default = 'h4 ++// Bit 29 :25 rg_wf2g_rx_lna_rfb_g6 U RW default = 'h8 ++typedef union RG_RX_A82_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LNA_RFB_G1 : 5; ++ unsigned int RG_WF2G_RX_LNA_RFB_G2 : 5; ++ unsigned int RG_WF2G_RX_LNA_RFB_G3 : 5; ++ unsigned int RG_WF2G_RX_LNA_RFB_G4 : 5; ++ unsigned int RG_WF2G_RX_LNA_RFB_G5 : 5; ++ unsigned int RG_WF2G_RX_LNA_RFB_G6 : 5; ++ unsigned int rsvd_0 : 2; ++ } b; ++} RG_RX_A82_FIELD_T; ++ ++#define RG_RX_A83 (RF_D_RX_REG_BASE + 0x14c) ++// Bit 4 :0 rg_wf2g_rx_lna_rfb_g7 U RW default = 'h0 ++// Bit 9 :5 rg_wf2g_rx_lna_rfb_man U RW default = 'h0 ++// Bit 10 rg_wf2g_rx_lna_rfb_man_mode U RW default = 'h0 ++typedef union RG_RX_A83_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LNA_RFB_G7 : 5; ++ unsigned int RG_WF2G_RX_LNA_RFB_MAN : 5; ++ unsigned int RG_WF2G_RX_LNA_RFB_MAN_MODE : 1; ++ unsigned int rsvd_0 : 21; ++ } b; ++} RG_RX_A83_FIELD_T; ++ ++#define RG_RX_A84 (RF_D_RX_REG_BASE + 0x150) ++// Bit 2 :0 rg_wf2g_rx_lna_rt_g1 U RW default = 'h5 ++// Bit 5 :3 rg_wf2g_rx_lna_rt_g2 U RW default = 'h5 ++// Bit 8 :6 rg_wf2g_rx_lna_rt_g3 U RW default = 'h5 ++// Bit 11 :9 rg_wf2g_rx_lna_rt_g4 U RW default = 'h5 ++// Bit 14 :12 rg_wf2g_rx_lna_rt_g5 U RW default = 'h5 ++// Bit 17 :15 rg_wf2g_rx_lna_rt_g6 U RW default = 'h0 ++// Bit 26 :24 rg_wf2g_rx_lna_rt_man U RW default = 'h0 ++// Bit 31 rg_wf2g_rx_lna_rt_man_mode U RW default = 'h0 ++typedef union RG_RX_A84_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LNA_RT_G1 : 3; ++ unsigned int RG_WF2G_RX_LNA_RT_G2 : 3; ++ unsigned int RG_WF2G_RX_LNA_RT_G3 : 3; ++ unsigned int RG_WF2G_RX_LNA_RT_G4 : 3; ++ unsigned int RG_WF2G_RX_LNA_RT_G5 : 3; ++ unsigned int RG_WF2G_RX_LNA_RT_G6 : 3; ++ unsigned int rsvd_0 : 6; ++ unsigned int RG_WF2G_RX_LNA_RT_MAN : 3; ++ unsigned int rsvd_1 : 4; ++ unsigned int RG_WF2G_RX_LNA_RT_MAN_MODE : 1; ++ } b; ++} RG_RX_A84_FIELD_T; ++ ++#define RG_RX_A85 (RF_D_RX_REG_BASE + 0x154) ++// Bit 2 :0 rg_wf2g_rx_lna_att_g1 U RW default = 'h0 ++// Bit 5 :3 rg_wf2g_rx_lna_att_g2 U RW default = 'h2 ++// Bit 8 :6 rg_wf2g_rx_lna_att_g3 U RW default = 'h3 ++// Bit 11 :9 rg_wf2g_rx_lna_att_man U RW default = 'h0 ++// Bit 12 rg_wf2g_rx_lna_att_man_mode U RW default = 'h0 ++typedef union RG_RX_A85_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LNA_ATT_G1 : 3; ++ unsigned int RG_WF2G_RX_LNA_ATT_G2 : 3; ++ unsigned int RG_WF2G_RX_LNA_ATT_G3 : 3; ++ unsigned int RG_WF2G_RX_LNA_ATT_MAN : 3; ++ unsigned int RG_WF2G_RX_LNA_ATT_MAN_MODE : 1; ++ unsigned int rsvd_0 : 19; ++ } b; ++} RG_RX_A85_FIELD_T; ++ ++#define RG_RX_A86 (RF_D_RX_REG_BASE + 0x158) ++// Bit 1 :0 rg_wf2g_rx_dpd_att_ctrl U RW default = 'h1 ++// Bit 4 :2 rg_wf2g_rx_dpd_gm_gain U RW default = 'h7 ++// Bit 7 :5 rg_wf2g_rx_dpd_gm_ictrl U RW default = 'h3 ++// Bit 11 :8 rg_wf2g_rx_dpd_mxr_lodrv_ictrl U RW default = 'h3 ++// Bit 14 :12 rg_wf2g_rx_gm_ictrl U RW default = 'h3 ++// Bit 18 :15 rg_wf2g_rx_mxr_lodrv_ictrl U RW default = 'h3 ++// Bit 22 :19 rg_wf2g_rx_mxr_vbsel U RW default = 'h2 ++// Bit 25 :23 rg_wf2g_rx_mxr_vcmsel U RW default = 'h3 ++typedef union RG_RX_A86_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_DPD_ATT_CTRL : 2; ++ unsigned int RG_WF2G_RX_DPD_GM_GAIN : 3; ++ unsigned int RG_WF2G_RX_DPD_GM_ICTRL : 3; ++ unsigned int RG_WF2G_RX_DPD_MXR_LODRV_ICTRL : 4; ++ unsigned int RG_WF2G_RX_GM_ICTRL : 3; ++ unsigned int RG_WF2G_RX_MXR_LODRV_ICTRL : 4; ++ unsigned int RG_WF2G_RX_MXR_VBSEL : 4; ++ unsigned int RG_WF2G_RX_MXR_VCMSEL : 3; ++ unsigned int rsvd_0 : 6; ++ } b; ++} RG_RX_A86_FIELD_T; ++ ++#define RG_RX_A87 (RF_D_RX_REG_BASE + 0x15c) ++// Bit 7 :0 rg_wf2g_rx_lna_priority U RW default = 'hdb ++typedef union RG_RX_A87_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LNA_PRIORITY : 8; ++ unsigned int rsvd_0 : 24; ++ } b; ++} RG_RX_A87_FIELD_T; ++ ++#define RG_RX_A88 (RF_D_RX_REG_BASE + 0x160) ++// Bit 0 rg_m4_wf_rx_fe_topbias_en U RW default = 'h1 ++// Bit 1 rg_m4_wf_rx_lna_bias_en U RW default = 'h1 ++// Bit 2 rg_m4_wf_rx_gm_bias_en U RW default = 'h1 ++// Bit 3 rg_m4_wf_rx_mxr_bias_en U RW default = 'h1 ++// Bit 4 rg_m4_wf5g_rx_lna_trsw_en U RW default = 'h1 ++// Bit 5 rg_m4_wf5g_rx_lna_en U RW default = 'h0 ++// Bit 6 rg_m4_wf5g_rx_gm_en U RW default = 'h0 ++// Bit 7 rg_m4_wf5g_rx_mxr_en U RW default = 'h0 ++// Bit 8 rg_m4_wf5g_rx_dpd_en U RW default = 'h1 ++// Bit 9 rg_m4_wf5g_rx_irrcal_en U RW default = 'h0 ++// Bit 10 rg_m4_wf2g_rx_lna_trsw_en U RW default = 'h0 ++// Bit 11 rg_m4_wf2g_rx_lna_en U RW default = 'h0 ++// Bit 12 rg_m4_wf2g_rx_gm_en U RW default = 'h0 ++// Bit 13 rg_m4_wf2g_rx_mxr_en U RW default = 'h0 ++// Bit 14 rg_m4_wf2g_rx_irrcal_en U RW default = 'h0 ++// Bit 15 rg_m4_wf2g_rx_dpd_en U RW default = 'h0 ++// Bit 17 rg_m4_wf_rtx_abb_topbias_en U RW default = 'h1 ++// Bit 18 rg_m4_wf_rtx_abb_rx_en U RW default = 'h1 ++// Bit 22 rg_m4_wf_rx_tia_bias_en U RW default = 'h1 ++// Bit 23 rg_m4_wf_rx_rssipga_bias_en U RW default = 'h1 ++// Bit 24 rg_m4_wf_rx_lpf_bias_en U RW default = 'h1 ++// Bit 25 rg_m4_wf_rx_tia_en U RW default = 'h1 ++// Bit 26 rg_m4_wf_rx_rssipga_en U RW default = 'h1 ++// Bit 27 rg_m4_wf_rx_lpf_en U RW default = 'h1 ++// Bit 28 rg_m4_wf_rx_lpf_i_dcoc_en U RW default = 'h1 ++// Bit 29 rg_m4_wf_rx_lpf_q_dcoc_en U RW default = 'h1 ++typedef union RG_RX_A88_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M4_WF_RX_FE_TOPBIAS_EN : 1; ++ unsigned int RG_M4_WF_RX_LNA_BIAS_EN : 1; ++ unsigned int RG_M4_WF_RX_GM_BIAS_EN : 1; ++ unsigned int RG_M4_WF_RX_MXR_BIAS_EN : 1; ++ unsigned int RG_M4_WF5G_RX_LNA_TRSW_EN : 1; ++ unsigned int RG_M4_WF5G_RX_LNA_EN : 1; ++ unsigned int RG_M4_WF5G_RX_GM_EN : 1; ++ unsigned int RG_M4_WF5G_RX_MXR_EN : 1; ++ unsigned int RG_M4_WF5G_RX_DPD_EN : 1; ++ unsigned int RG_M4_WF5G_RX_IRRCAL_EN : 1; ++ unsigned int RG_M4_WF2G_RX_LNA_TRSW_EN : 1; ++ unsigned int RG_M4_WF2G_RX_LNA_EN : 1; ++ unsigned int RG_M4_WF2G_RX_GM_EN : 1; ++ unsigned int RG_M4_WF2G_RX_MXR_EN : 1; ++ unsigned int RG_M4_WF2G_RX_IRRCAL_EN : 1; ++ unsigned int RG_M4_WF2G_RX_DPD_EN : 1; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_M4_WF_RTX_ABB_TOPBIAS_EN : 1; ++ unsigned int RG_M4_WF_RTX_ABB_RX_EN : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int RG_M4_WF_RX_TIA_BIAS_EN : 1; ++ unsigned int RG_M4_WF_RX_RSSIPGA_BIAS_EN : 1; ++ unsigned int RG_M4_WF_RX_LPF_BIAS_EN : 1; ++ unsigned int RG_M4_WF_RX_TIA_EN : 1; ++ unsigned int RG_M4_WF_RX_RSSIPGA_EN : 1; ++ unsigned int RG_M4_WF_RX_LPF_EN : 1; ++ unsigned int RG_M4_WF_RX_LPF_I_DCOC_EN : 1; ++ unsigned int RG_M4_WF_RX_LPF_Q_DCOC_EN : 1; ++ unsigned int rsvd_2 : 2; ++ } b; ++} RG_RX_A88_FIELD_T; ++ ++#define RG_RX_A89 (RF_D_RX_REG_BASE + 0x164) ++// Bit 0 rg_m5_wf_rx_fe_topbias_en U RW default = 'h0 ++// Bit 1 rg_m5_wf_rx_lna_bias_en U RW default = 'h0 ++// Bit 2 rg_m5_wf_rx_gm_bias_en U RW default = 'h0 ++// Bit 3 rg_m5_wf_rx_mxr_bias_en U RW default = 'h0 ++// Bit 4 rg_m5_wf5g_rx_lna_trsw_en U RW default = 'h0 ++// Bit 5 rg_m5_wf5g_rx_lna_en U RW default = 'h0 ++// Bit 6 rg_m5_wf5g_rx_gm_en U RW default = 'h0 ++// Bit 7 rg_m5_wf5g_rx_mxr_en U RW default = 'h0 ++// Bit 8 rg_m5_wf5g_rx_dpd_en U RW default = 'h0 ++// Bit 9 rg_m5_wf5g_rx_irrcal_en U RW default = 'h0 ++// Bit 10 rg_m5_wf2g_rx_lna_trsw_en U RW default = 'h0 ++// Bit 11 rg_m5_wf2g_rx_lna_en U RW default = 'h0 ++// Bit 12 rg_m5_wf2g_rx_gm_en U RW default = 'h0 ++// Bit 13 rg_m5_wf2g_rx_mxr_en U RW default = 'h0 ++// Bit 14 rg_m5_wf2g_rx_irrcal_en U RW default = 'h0 ++// Bit 15 rg_m5_wf2g_rx_dpd_en U RW default = 'h0 ++// Bit 17 rg_m5_wf_rtx_abb_topbias_en U RW default = 'h0 ++// Bit 18 rg_m5_wf_rtx_abb_rx_en U RW default = 'h0 ++// Bit 22 rg_m5_wf_rx_tia_bias_en U RW default = 'h0 ++// Bit 23 rg_m5_wf_rx_rssipga_bias_en U RW default = 'h0 ++// Bit 24 rg_m5_wf_rx_lpf_bias_en U RW default = 'h0 ++// Bit 25 rg_m5_wf_rx_tia_en U RW default = 'h0 ++// Bit 26 rg_m5_wf_rx_rssipga_en U RW default = 'h0 ++// Bit 27 rg_m5_wf_rx_lpf_en U RW default = 'h0 ++// Bit 28 rg_m5_wf_rx_lpf_i_dcoc_en U RW default = 'h0 ++// Bit 29 rg_m5_wf_rx_lpf_q_dcoc_en U RW default = 'h0 ++typedef union RG_RX_A89_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M5_WF_RX_FE_TOPBIAS_EN : 1; ++ unsigned int RG_M5_WF_RX_LNA_BIAS_EN : 1; ++ unsigned int RG_M5_WF_RX_GM_BIAS_EN : 1; ++ unsigned int RG_M5_WF_RX_MXR_BIAS_EN : 1; ++ unsigned int RG_M5_WF5G_RX_LNA_TRSW_EN : 1; ++ unsigned int RG_M5_WF5G_RX_LNA_EN : 1; ++ unsigned int RG_M5_WF5G_RX_GM_EN : 1; ++ unsigned int RG_M5_WF5G_RX_MXR_EN : 1; ++ unsigned int RG_M5_WF5G_RX_DPD_EN : 1; ++ unsigned int RG_M5_WF5G_RX_IRRCAL_EN : 1; ++ unsigned int RG_M5_WF2G_RX_LNA_TRSW_EN : 1; ++ unsigned int RG_M5_WF2G_RX_LNA_EN : 1; ++ unsigned int RG_M5_WF2G_RX_GM_EN : 1; ++ unsigned int RG_M5_WF2G_RX_MXR_EN : 1; ++ unsigned int RG_M5_WF2G_RX_IRRCAL_EN : 1; ++ unsigned int RG_M5_WF2G_RX_DPD_EN : 1; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_M5_WF_RTX_ABB_TOPBIAS_EN : 1; ++ unsigned int RG_M5_WF_RTX_ABB_RX_EN : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int RG_M5_WF_RX_TIA_BIAS_EN : 1; ++ unsigned int RG_M5_WF_RX_RSSIPGA_BIAS_EN : 1; ++ unsigned int RG_M5_WF_RX_LPF_BIAS_EN : 1; ++ unsigned int RG_M5_WF_RX_TIA_EN : 1; ++ unsigned int RG_M5_WF_RX_RSSIPGA_EN : 1; ++ unsigned int RG_M5_WF_RX_LPF_EN : 1; ++ unsigned int RG_M5_WF_RX_LPF_I_DCOC_EN : 1; ++ unsigned int RG_M5_WF_RX_LPF_Q_DCOC_EN : 1; ++ unsigned int rsvd_2 : 2; ++ } b; ++} RG_RX_A89_FIELD_T; ++ ++#define RG_RX_A90 (RF_D_RX_REG_BASE + 0x168) ++// Bit 0 rg_m6_wf_rx_fe_topbias_en U RW default = 'h1 ++// Bit 1 rg_m6_wf_rx_lna_bias_en U RW default = 'h0 ++// Bit 2 rg_m6_wf_rx_gm_bias_en U RW default = 'h0 ++// Bit 3 rg_m6_wf_rx_mxr_bias_en U RW default = 'h0 ++// Bit 4 rg_m6_wf5g_rx_lna_trsw_en U RW default = 'h0 ++// Bit 5 rg_m6_wf5g_rx_lna_en U RW default = 'h0 ++// Bit 6 rg_m6_wf5g_rx_gm_en U RW default = 'h0 ++// Bit 7 rg_m6_wf5g_rx_mxr_en U RW default = 'h0 ++// Bit 8 rg_m6_wf5g_rx_dpd_en U RW default = 'h0 ++// Bit 9 rg_m6_wf5g_rx_irrcal_en U RW default = 'h0 ++// Bit 10 rg_m6_wf2g_rx_lna_trsw_en U RW default = 'h1 ++// Bit 11 rg_m6_wf2g_rx_lna_en U RW default = 'h0 ++// Bit 12 rg_m6_wf2g_rx_gm_en U RW default = 'h0 ++// Bit 13 rg_m6_wf2g_rx_mxr_en U RW default = 'h0 ++// Bit 14 rg_m6_wf2g_rx_irrcal_en U RW default = 'h0 ++// Bit 15 rg_m6_wf2g_rx_dpd_en U RW default = 'h0 ++// Bit 17 rg_m6_wf_rtx_abb_topbias_en U RW default = 'h1 ++// Bit 18 rg_m6_wf_rtx_abb_rx_en U RW default = 'h0 ++// Bit 22 rg_m6_wf_rx_tia_bias_en U RW default = 'h0 ++// Bit 23 rg_m6_wf_rx_rssipga_bias_en U RW default = 'h0 ++// Bit 24 rg_m6_wf_rx_lpf_bias_en U RW default = 'h0 ++// Bit 25 rg_m6_wf_rx_tia_en U RW default = 'h0 ++// Bit 26 rg_m6_wf_rx_rssipga_en U RW default = 'h0 ++// Bit 27 rg_m6_wf_rx_lpf_en U RW default = 'h0 ++// Bit 28 rg_m6_wf_rx_lpf_i_dcoc_en U RW default = 'h0 ++// Bit 29 rg_m6_wf_rx_lpf_q_dcoc_en U RW default = 'h0 ++typedef union RG_RX_A90_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M6_WF_RX_FE_TOPBIAS_EN : 1; ++ unsigned int RG_M6_WF_RX_LNA_BIAS_EN : 1; ++ unsigned int RG_M6_WF_RX_GM_BIAS_EN : 1; ++ unsigned int RG_M6_WF_RX_MXR_BIAS_EN : 1; ++ unsigned int RG_M6_WF5G_RX_LNA_TRSW_EN : 1; ++ unsigned int RG_M6_WF5G_RX_LNA_EN : 1; ++ unsigned int RG_M6_WF5G_RX_GM_EN : 1; ++ unsigned int RG_M6_WF5G_RX_MXR_EN : 1; ++ unsigned int RG_M6_WF5G_RX_DPD_EN : 1; ++ unsigned int RG_M6_WF5G_RX_IRRCAL_EN : 1; ++ unsigned int RG_M6_WF2G_RX_LNA_TRSW_EN : 1; ++ unsigned int RG_M6_WF2G_RX_LNA_EN : 1; ++ unsigned int RG_M6_WF2G_RX_GM_EN : 1; ++ unsigned int RG_M6_WF2G_RX_MXR_EN : 1; ++ unsigned int RG_M6_WF2G_RX_IRRCAL_EN : 1; ++ unsigned int RG_M6_WF2G_RX_DPD_EN : 1; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_M6_WF_RTX_ABB_TOPBIAS_EN : 1; ++ unsigned int RG_M6_WF_RTX_ABB_RX_EN : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int RG_M6_WF_RX_TIA_BIAS_EN : 1; ++ unsigned int RG_M6_WF_RX_RSSIPGA_BIAS_EN : 1; ++ unsigned int RG_M6_WF_RX_LPF_BIAS_EN : 1; ++ unsigned int RG_M6_WF_RX_TIA_EN : 1; ++ unsigned int RG_M6_WF_RX_RSSIPGA_EN : 1; ++ unsigned int RG_M6_WF_RX_LPF_EN : 1; ++ unsigned int RG_M6_WF_RX_LPF_I_DCOC_EN : 1; ++ unsigned int RG_M6_WF_RX_LPF_Q_DCOC_EN : 1; ++ unsigned int rsvd_2 : 2; ++ } b; ++} RG_RX_A90_FIELD_T; ++ ++#define RG_RX_A91 (RF_D_RX_REG_BASE + 0x16c) ++// Bit 0 rg_m7_wf_rx_fe_topbias_en U RW default = 'h1 ++// Bit 1 rg_m7_wf_rx_lna_bias_en U RW default = 'h1 ++// Bit 2 rg_m7_wf_rx_gm_bias_en U RW default = 'h1 ++// Bit 3 rg_m7_wf_rx_mxr_bias_en U RW default = 'h1 ++// Bit 4 rg_m7_wf5g_rx_lna_trsw_en U RW default = 'h0 ++// Bit 5 rg_m7_wf5g_rx_lna_en U RW default = 'h0 ++// Bit 6 rg_m7_wf5g_rx_gm_en U RW default = 'h0 ++// Bit 7 rg_m7_wf5g_rx_mxr_en U RW default = 'h0 ++// Bit 8 rg_m7_wf5g_rx_dpd_en U RW default = 'h0 ++// Bit 9 rg_m7_wf5g_rx_irrcal_en U RW default = 'h0 ++// Bit 10 rg_m7_wf2g_rx_lna_trsw_en U RW default = 'h0 ++// Bit 11 rg_m7_wf2g_rx_lna_en U RW default = 'h1 ++// Bit 12 rg_m7_wf2g_rx_gm_en U RW default = 'h1 ++// Bit 13 rg_m7_wf2g_rx_mxr_en U RW default = 'h1 ++// Bit 14 rg_m7_wf2g_rx_irrcal_en U RW default = 'h0 ++// Bit 15 rg_m7_wf2g_rx_dpd_en U RW default = 'h0 ++// Bit 17 rg_m7_wf_rtx_abb_topbias_en U RW default = 'h1 ++// Bit 18 rg_m7_wf_rtx_abb_rx_en U RW default = 'h1 ++// Bit 22 rg_m7_wf_rx_tia_bias_en U RW default = 'h1 ++// Bit 23 rg_m7_wf_rx_rssipga_bias_en U RW default = 'h1 ++// Bit 24 rg_m7_wf_rx_lpf_bias_en U RW default = 'h1 ++// Bit 25 rg_m7_wf_rx_tia_en U RW default = 'h1 ++// Bit 26 rg_m7_wf_rx_rssipga_en U RW default = 'h1 ++// Bit 27 rg_m7_wf_rx_lpf_en U RW default = 'h1 ++// Bit 28 rg_m7_wf_rx_lpf_i_dcoc_en U RW default = 'h1 ++// Bit 29 rg_m7_wf_rx_lpf_q_dcoc_en U RW default = 'h1 ++typedef union RG_RX_A91_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M7_WF_RX_FE_TOPBIAS_EN : 1; ++ unsigned int RG_M7_WF_RX_LNA_BIAS_EN : 1; ++ unsigned int RG_M7_WF_RX_GM_BIAS_EN : 1; ++ unsigned int RG_M7_WF_RX_MXR_BIAS_EN : 1; ++ unsigned int RG_M7_WF5G_RX_LNA_TRSW_EN : 1; ++ unsigned int RG_M7_WF5G_RX_LNA_EN : 1; ++ unsigned int RG_M7_WF5G_RX_GM_EN : 1; ++ unsigned int RG_M7_WF5G_RX_MXR_EN : 1; ++ unsigned int RG_M7_WF5G_RX_DPD_EN : 1; ++ unsigned int RG_M7_WF5G_RX_IRRCAL_EN : 1; ++ unsigned int RG_M7_WF2G_RX_LNA_TRSW_EN : 1; ++ unsigned int RG_M7_WF2G_RX_LNA_EN : 1; ++ unsigned int RG_M7_WF2G_RX_GM_EN : 1; ++ unsigned int RG_M7_WF2G_RX_MXR_EN : 1; ++ unsigned int RG_M7_WF2G_RX_IRRCAL_EN : 1; ++ unsigned int RG_M7_WF2G_RX_DPD_EN : 1; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_M7_WF_RTX_ABB_TOPBIAS_EN : 1; ++ unsigned int RG_M7_WF_RTX_ABB_RX_EN : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int RG_M7_WF_RX_TIA_BIAS_EN : 1; ++ unsigned int RG_M7_WF_RX_RSSIPGA_BIAS_EN : 1; ++ unsigned int RG_M7_WF_RX_LPF_BIAS_EN : 1; ++ unsigned int RG_M7_WF_RX_TIA_EN : 1; ++ unsigned int RG_M7_WF_RX_RSSIPGA_EN : 1; ++ unsigned int RG_M7_WF_RX_LPF_EN : 1; ++ unsigned int RG_M7_WF_RX_LPF_I_DCOC_EN : 1; ++ unsigned int RG_M7_WF_RX_LPF_Q_DCOC_EN : 1; ++ unsigned int rsvd_2 : 2; ++ } b; ++} RG_RX_A91_FIELD_T; ++ ++#define RG_RX_A92 (RF_D_RX_REG_BASE + 0x170) ++// Bit 2 :0 rg_wf2g_rx_lna_ictrl_g67 U RW default = 'h3 ++// Bit 5 :3 rg_wf2g_rx_lna_ictrl_g57 U RW default = 'h2 ++// Bit 8 :6 rg_wf2g_rx_lna_ictrl_g47 U RW default = 'h2 ++// Bit 11 :9 rg_wf2g_rx_lna_ictrl_g37 U RW default = 'h5 ++// Bit 14 :12 rg_wf2g_rx_lna_ictrl_g56 U RW default = 'h3 ++// Bit 17 :15 rg_wf2g_rx_lna_ictrl_g46 U RW default = 'h2 ++// Bit 20 :18 rg_wf2g_rx_lna_ictrl_g36 U RW default = 'h5 ++// Bit 23 :21 rg_wf2g_rx_lna_ictrl_g45 U RW default = 'h3 ++// Bit 26 :24 rg_wf2g_rx_lna_ictrl_g35 U RW default = 'h3 ++// Bit 29 :27 rg_wf2g_rx_lna_ictrl_g34 U RW default = 'h2 ++typedef union RG_RX_A92_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LNA_ICTRL_G67 : 3; ++ unsigned int RG_WF2G_RX_LNA_ICTRL_G57 : 3; ++ unsigned int RG_WF2G_RX_LNA_ICTRL_G47 : 3; ++ unsigned int RG_WF2G_RX_LNA_ICTRL_G37 : 3; ++ unsigned int RG_WF2G_RX_LNA_ICTRL_G56 : 3; ++ unsigned int RG_WF2G_RX_LNA_ICTRL_G46 : 3; ++ unsigned int RG_WF2G_RX_LNA_ICTRL_G36 : 3; ++ unsigned int RG_WF2G_RX_LNA_ICTRL_G45 : 3; ++ unsigned int RG_WF2G_RX_LNA_ICTRL_G35 : 3; ++ unsigned int RG_WF2G_RX_LNA_ICTRL_G34 : 3; ++ unsigned int rsvd_0 : 2; ++ } b; ++} RG_RX_A92_FIELD_T; ++ ++#define RG_RX_A93 (RF_D_RX_REG_BASE + 0x174) ++// Bit 4 :0 rg_wf2g_rx_lna_rfb_g77 U RW default = 'h0 ++// Bit 9 :5 rg_wf2g_btrx_lna_rfb_g77 U RW default = 'h0 ++// Bit 11 :10 rg_wf_agc_lock_option U RW default = 'h3 ++// Bit 23 :16 rg_wf_rx_lna_en_delay_bnd U RW default = 'h14 ++// Bit 24 rg_wf_rx_lna_en_delay_bypass U RW default = 'h0 ++typedef union RG_RX_A93_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_RX_LNA_RFB_G77 : 5; ++ unsigned int RG_WF2G_BTRX_LNA_RFB_G77 : 5; ++ unsigned int RG_WF_AGC_LOCK_OPTION : 2; ++ unsigned int rsvd_0 : 4; ++ unsigned int RG_WF_RX_LNA_EN_DELAY_BND : 8; ++ unsigned int RG_WF_RX_LNA_EN_DELAY_BYPASS : 1; ++ unsigned int rsvd_1 : 7; ++ } b; ++} RG_RX_A93_FIELD_T; ++ ++#define RG_RX_A94 (RF_D_RX_REG_BASE + 0x178) ++// Bit 12 rg_wf_daclpbk2adc_en U RW default = 'h0 ++// Bit 13 rg_wf_rx_lpf_testout_en U RW default = 'h0 ++// Bit 14 rg_wf_rx_rssipga_testout_en U RW default = 'h0 ++typedef union RG_RX_A94_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rsvd_0 : 12; ++ unsigned int RG_WF_DACLPBK2ADC_EN : 1; ++ unsigned int RG_WF_RX_LPF_TESTOUT_EN : 1; ++ unsigned int RG_WF_RX_RSSIPGA_TESTOUT_EN : 1; ++ unsigned int rsvd_1 : 17; ++ } b; ++} RG_RX_A94_FIELD_T; ++ ++#endif ++ +diff --git a/drivers/net/wireless/w1/common/rf_d_sx_reg.h b/drivers/net/wireless/w1/common/rf_d_sx_reg.h +new file mode 100644 +index 0000000000000000000000000000000000000000..7019eb56ab70a661893905fc9a5eff7fcec08488 +--- /dev/null ++++ b/drivers/net/wireless/w1/common/rf_d_sx_reg.h +@@ -0,0 +1,1093 @@ ++#ifdef RF_D_SX_REG ++#else ++#define RF_D_SX_REG ++ ++ ++#define RF_D_SX_REG_BASE (0x400) ++ ++#define RG_SX_A0 (RF_D_SX_REG_BASE + 0x0) ++// Bit 0 rg_wf_sx_fcal_en U RW default = 'h0 ++// Bit 2 rg_wf_sx_cali_start_man_mode U RW default = 'h1 ++// Bit 4 rg_wf_sx_sdm_frac_en U RW default = 'h1 ++// Bit 12 :8 rg_wf_sx_fcal_mode_sel U RW default = 'h1b ++// Bit 16 rg_wf_sx_rf_osc_double U RW default = 'h0 ++// Bit 20 rg_wf_sx_dig_osc_double U RW default = 'h0 ++// Bit 31 rg_wf_sx_soft_reset U RW default = 'h0 ++typedef union RG_SX_A0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_FCAL_EN : 1; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF_SX_CALI_START_MAN_MODE : 1; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF_SX_SDM_FRAC_EN : 1; ++ unsigned int rsvd_2 : 3; ++ unsigned int RG_WF_SX_FCAL_MODE_SEL : 5; ++ unsigned int rsvd_3 : 3; ++ unsigned int RG_WF_SX_RF_OSC_DOUBLE : 1; ++ unsigned int rsvd_4 : 3; ++ unsigned int RG_WF_SX_DIG_OSC_DOUBLE : 1; ++ unsigned int rsvd_5 : 10; ++ unsigned int RG_WF_SX_SOFT_RESET : 1; ++ } b; ++} RG_SX_A0_FIELD_T; ++ ++#define RG_SX_A1 (RF_D_SX_REG_BASE + 0x4) ++// Bit 0 rg_wf_sx_fcal_sel_p U RW default = 'h0 ++// Bit 10 :4 rg_wf_sx_vcoc_p U RW default = 'h40 ++// Bit 12 rg_wf_sx_fcal_sel_t U RW default = 'h0 ++// Bit 20 :16 rg_wf_sx_vcoc_t U RW default = 'h10 ++// Bit 24 rg_wf_sx_ldo_fc_man U RW default = 'h0 ++// Bit 28 rg_wf_sx_ldo_fc U RW default = 'h0 ++typedef union RG_SX_A1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_FCAL_SEL_P : 1; ++ unsigned int rsvd_0 : 3; ++ unsigned int RG_WF_SX_VCOC_P : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF_SX_FCAL_SEL_T : 1; ++ unsigned int rsvd_2 : 3; ++ unsigned int RG_WF_SX_VCOC_T : 5; ++ unsigned int rsvd_3 : 3; ++ unsigned int RG_WF_SX_LDO_FC_MAN : 1; ++ unsigned int rsvd_4 : 3; ++ unsigned int RG_WF_SX_LDO_FC : 1; ++ unsigned int rsvd_5 : 3; ++ } b; ++} RG_SX_A1_FIELD_T; ++ ++#define RG_SX_A2 (RF_D_SX_REG_BASE + 0x8) ++// Bit 6 :0 ro_da_wf_sx_vcoc_p U RO default = 'h0 ++// Bit 20 :16 ro_da_wf_sx_vcoc_t U RO default = 'h0 ++// Bit 24 ro_wf_sx_mxrtank_cali_ready U RO default = 'h0 ++// Bit 25 ro_wf_sx_chn_map_ready U RO default = 'h0 ++// Bit 26 ro_wf_sx_p_cali_ready U RO default = 'h0 ++// Bit 27 ro_wf_sx_a_cali_ready U RO default = 'h0 ++// Bit 28 ro_wf_sx_t_cali_ready U RO default = 'h0 ++// Bit 29 ro_ad_wf_sx_ready U RO default = 'h0 ++// Bit 31 ro_cali_end_flg U RO default = 'h0 ++typedef union RG_SX_A2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RO_DA_WF_SX_VCOC_P : 7; ++ unsigned int rsvd_0 : 9; ++ unsigned int RO_DA_WF_SX_VCOC_T : 5; ++ unsigned int rsvd_1 : 3; ++ unsigned int RO_WF_SX_MXRTANK_CALI_READY : 1; ++ unsigned int RO_WF_SX_CHN_MAP_READY : 1; ++ unsigned int RO_WF_SX_P_CALI_READY : 1; ++ unsigned int RO_WF_SX_A_CALI_READY : 1; ++ unsigned int RO_WF_SX_T_CALI_READY : 1; ++ unsigned int RO_AD_WF_SX_READY : 1; ++ unsigned int rsvd_2 : 1; ++ unsigned int RO_CALI_END_FLG : 1; ++ } b; ++} RG_SX_A2_FIELD_T; ++ ++#define RG_SX_A3 (RF_D_SX_REG_BASE + 0xc) ++// Bit 1 :0 rg_wf_sx_ldo_fc_waittime U RW default = 'h2 ++// Bit 5 :4 rg_wf_sx_set_code_waittime U RW default = 'h1 ++// Bit 9 :8 rg_wf_sx_fcal_cw_waittime U RW default = 'h1 ++// Bit 13 :12 rg_wf_sx_tr_wait_waittime U RW default = 'h1 ++// Bit 17 :16 rg_wf_sx_acal_vco_waittime U RW default = 'h1 ++// Bit 21 :20 rg_wf_sx_tr_switch_bnd U RW default = 'h0 ++typedef union RG_SX_A3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_LDO_FC_WAITTIME : 2; ++ unsigned int rsvd_0 : 2; ++ unsigned int RG_WF_SX_SET_CODE_WAITTIME : 2; ++ unsigned int rsvd_1 : 2; ++ unsigned int RG_WF_SX_FCAL_CW_WAITTIME : 2; ++ unsigned int rsvd_2 : 2; ++ unsigned int RG_WF_SX_TR_WAIT_WAITTIME : 2; ++ unsigned int rsvd_3 : 2; ++ unsigned int RG_WF_SX_ACAL_VCO_WAITTIME : 2; ++ unsigned int rsvd_4 : 2; ++ unsigned int RG_WF_SX_TR_SWITCH_BND : 2; ++ unsigned int rsvd_5 : 10; ++ } b; ++} RG_SX_A3_FIELD_T; ++ ++#define RG_SX_A4 (RF_D_SX_REG_BASE + 0x10) ++// Bit 0 rg_wf_sx_vco_i_man U RW default = 'h0 ++// Bit 7 :4 rg_wf_sx_vco_i U RW default = 'h8 ++// Bit 15 :8 rg_wf_sx_pd_vctrl_sel U RW default = 'h3 ++typedef union RG_SX_A4_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_VCO_I_MAN : 1; ++ unsigned int rsvd_0 : 3; ++ unsigned int RG_WF_SX_VCO_I : 4; ++ unsigned int RG_WF_SX_PD_VCTRL_SEL : 8; ++ unsigned int rsvd_1 : 16; ++ } b; ++} RG_SX_A4_FIELD_T; ++ ++#define RG_SX_A5 (RF_D_SX_REG_BASE + 0x14) ++// Bit 3 :0 ro_wf_sx_vco_i U RO default = 'h0 ++// Bit 4 ro_da_wf_sx_vco_acfinish U RO default = 'h0 ++// Bit 8 ro_ad_wf_sx_vco_alc_out U RO default = 'h0 ++// Bit 23 :16 ro_wf_sx_pt_fsm U RO default = 'h0 ++// Bit 30 :24 ro_wf_sx_top_fsm U RO default = 'h0 ++typedef union RG_SX_A5_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RO_WF_SX_VCO_I : 4; ++ unsigned int RO_DA_WF_SX_VCO_ACFINISH : 1; ++ unsigned int rsvd_0 : 3; ++ unsigned int RO_AD_WF_SX_VCO_ALC_OUT : 1; ++ unsigned int rsvd_1 : 7; ++ unsigned int RO_WF_SX_PT_FSM : 8; ++ unsigned int RO_WF_SX_TOP_FSM : 7; ++ unsigned int rsvd_2 : 1; ++ } b; ++} RG_SX_A5_FIELD_T; ++ ++#define RG_SX_A6 (RF_D_SX_REG_BASE + 0x18) ++// Bit 0 rg_sx_pdiv_sel U RW default = 'h1 ++// Bit 7 :4 rg_sx_osc_freq U RW default = 'h3 ++// Bit 15 :8 rg_2gb_sx_channel U RW default = 'h8 ++// Bit 23 :16 rg_5gb_sx_channel U RW default = 'h64 ++// Bit 27 :24 rg_wifi_freq_mode_man U RW default = 'h0 ++// Bit 31 rg_wifi_freq_mode_man_mode U RW default = 'h0 ++typedef union RG_SX_A6_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_SX_PDIV_SEL : 1; ++ unsigned int rsvd_0 : 3; ++ unsigned int RG_SX_OSC_FREQ : 4; ++ unsigned int RG_2GB_SX_CHANNEL : 8; ++ unsigned int RG_5GB_SX_CHANNEL : 8; ++ unsigned int RG_WIFI_FREQ_MODE_MAN : 4; ++ unsigned int rsvd_1 : 3; ++ unsigned int RG_WIFI_FREQ_MODE_MAN_MODE : 1; ++ } b; ++} RG_SX_A6_FIELD_T; ++ ++#define RG_SX_A7 (RF_D_SX_REG_BASE + 0x1c) ++// Bit 0 rg_sx_rfch_man_en U RW default = 'h0 ++// Bit 14 :4 rg_wf_sx_rfctrl_int U RW default = 'h0 ++typedef union RG_SX_A7_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_SX_RFCH_MAN_EN : 1; ++ unsigned int rsvd_0 : 3; ++ unsigned int RG_WF_SX_RFCTRL_INT : 11; ++ unsigned int rsvd_1 : 17; ++ } b; ++} RG_SX_A7_FIELD_T; ++ ++#define RG_SX_A8 (RF_D_SX_REG_BASE + 0x20) ++// Bit 24 :0 rg_wf_sx_rfctrl_frac U RW default = 'h0 ++typedef union RG_SX_A8_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_RFCTRL_FRAC : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_SX_A8_FIELD_T; ++ ++#define RG_SX_A9 (RF_D_SX_REG_BASE + 0x24) ++// Bit 15 :0 rg_sx_fcal_ntargt U RW default = 'h0 ++// Bit 16 rg_sx_fcal_ntargt_man U RW default = 'h0 ++typedef union RG_SX_A9_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_SX_FCAL_NTARGT : 16; ++ unsigned int RG_SX_FCAL_NTARGT_MAN : 1; ++ unsigned int rsvd_0 : 15; ++ } b; ++} RG_SX_A9_FIELD_T; ++ ++#define RG_SX_A10 (RF_D_SX_REG_BASE + 0x28) ++// Bit 15 :0 ro_wf_sx_fcal_cnt U RO default = 'h0 ++// Bit 28 :16 ro_wf_sx_rf_freq_mhz U RO default = 'h0 ++typedef union RG_SX_A10_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RO_WF_SX_FCAL_CNT : 16; ++ unsigned int RO_WF_SX_RF_FREQ_MHZ : 13; ++ unsigned int rsvd_0 : 3; ++ } b; ++} RG_SX_A10_FIELD_T; ++ ++#define RG_SX_A11 (RF_D_SX_REG_BASE + 0x2c) ++// Bit 1 :0 rg_wf_sx_fcal_hvt U RW default = 'h1 ++// Bit 5 :4 rg_wf_sx_fcal_lvt U RW default = 'h1 ++typedef union RG_SX_A11_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_FCAL_HVT : 2; ++ unsigned int rsvd_0 : 2; ++ unsigned int RG_WF_SX_FCAL_LVT : 2; ++ unsigned int rsvd_1 : 26; ++ } b; ++} RG_SX_A11_FIELD_T; ++ ++#define RG_SX_A12 (RF_D_SX_REG_BASE + 0x30) ++// Bit 10 :0 ro_sx_rfctrl_nint U RO default = 'h0 ++typedef union RG_SX_A12_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RO_SX_RFCTRL_NINT : 11; ++ unsigned int rsvd_0 : 21; ++ } b; ++} RG_SX_A12_FIELD_T; ++ ++#define RG_SX_A13 (RF_D_SX_REG_BASE + 0x34) ++// Bit 24 :0 ro_sx_rfctrl_nfrac U RO default = 'h0 ++typedef union RG_SX_A13_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RO_SX_RFCTRL_NFRAC : 25; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_SX_A13_FIELD_T; ++ ++#define RG_SX_A14 (RF_D_SX_REG_BASE + 0x38) ++// Bit 15 :0 ro_sx_fcal_ntargt U RO default = 'h0 ++typedef union RG_SX_A14_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RO_SX_FCAL_NTARGT : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} RG_SX_A14_FIELD_T; ++ ++#define RG_SX_A15 (RF_D_SX_REG_BASE + 0x3c) ++// Bit 6 rg_tr_switch_man U RW default = 'h0 ++// Bit 7 rg_tr_switch_val U RW default = 'h0 ++typedef union RG_SX_A15_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rsvd_0 : 6; ++ unsigned int RG_TR_SWITCH_MAN : 1; ++ unsigned int RG_TR_SWITCH_VAL : 1; ++ unsigned int rsvd_1 : 24; ++ } b; ++} RG_SX_A15_FIELD_T; ++ ++#define RG_SX_A16 (RF_D_SX_REG_BASE + 0x40) ++// Bit 2 :0 rg_wf_sx_log_pdthreshold_man U RW default = 'h7 ++// Bit 4 rg_wf_sx_log_pd_man_mode U RW default = 'h0 ++// Bit 8 rg_wf_sx_log_pdtest_en U RW default = 'h0 ++typedef union RG_SX_A16_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_LOG_PDTHRESHOLD_MAN : 3; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF_SX_LOG_PD_MAN_MODE : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int RG_WF_SX_LOG_PDTEST_EN : 1; ++ unsigned int rsvd_2 : 23; ++ } b; ++} RG_SX_A16_FIELD_T; ++ ++#define RG_SX_A17 (RF_D_SX_REG_BASE + 0x44) ++// Bit 3 :0 rg_wf_sx_log5g_mxr_banksel_man0 U RW default = 'he ++// Bit 7 :4 rg_wf_sx_log5g_mxr_banksel_man1 U RW default = 'hd ++// Bit 11 :8 rg_wf_sx_log5g_mxr_banksel_man2 U RW default = 'hc ++// Bit 15 :12 rg_wf_sx_log5g_mxr_banksel_man3 U RW default = 'hb ++// Bit 19 :16 rg_wf_sx_log5g_mxr_banksel_man4 U RW default = 'ha ++// Bit 23 :20 rg_wf_sx_log5g_mxr_banksel_man5 U RW default = 'h9 ++// Bit 27 :24 rg_wf_sx_log5g_mxr_banksel_man6 U RW default = 'h8 ++// Bit 31 :28 rg_wf_sx_log5g_mxr_banksel_man7 U RW default = 'h7 ++typedef union RG_SX_A17_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN0 : 4; ++ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN1 : 4; ++ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN2 : 4; ++ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN3 : 4; ++ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN4 : 4; ++ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN5 : 4; ++ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN6 : 4; ++ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN7 : 4; ++ } b; ++} RG_SX_A17_FIELD_T; ++ ++#define RG_SX_A18 (RF_D_SX_REG_BASE + 0x48) ++// Bit 3 :0 rg_wf_sx_log5g_mxr_banksel_man8 U RW default = 'h6 ++// Bit 7 :4 rg_wf_sx_log5g_mxr_banksel_man9 U RW default = 'h4 ++// Bit 11 :8 rg_wf_sx_log2g_mxr_banksel_man U RW default = 'h6 ++typedef union RG_SX_A18_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN8 : 4; ++ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN9 : 4; ++ unsigned int RG_WF_SX_LOG2G_MXR_BANKSEL_MAN : 4; ++ unsigned int rsvd_0 : 20; ++ } b; ++} RG_SX_A18_FIELD_T; ++ ++#define RG_SX_A20 (RF_D_SX_REG_BASE + 0x50) ++// Bit 3 :0 ro_wf_sx_log5g_mxr_banksel_0 U RO default = 'h0 ++// Bit 7 :4 ro_wf_sx_log5g_mxr_banksel_1 U RO default = 'h0 ++// Bit 11 :8 ro_wf_sx_log5g_mxr_banksel_2 U RO default = 'h0 ++// Bit 15 :12 ro_wf_sx_log5g_mxr_banksel_3 U RO default = 'h0 ++// Bit 19 :16 ro_wf_sx_log5g_mxr_banksel_4 U RO default = 'h0 ++// Bit 23 :20 ro_wf_sx_log5g_mxr_banksel_5 U RO default = 'h0 ++// Bit 27 :24 ro_wf_sx_log5g_mxr_banksel_6 U RO default = 'h0 ++// Bit 31 :28 ro_wf_sx_log5g_mxr_banksel_7 U RO default = 'h0 ++typedef union RG_SX_A20_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_0 : 4; ++ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_1 : 4; ++ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_2 : 4; ++ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_3 : 4; ++ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_4 : 4; ++ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_5 : 4; ++ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_6 : 4; ++ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_7 : 4; ++ } b; ++} RG_SX_A20_FIELD_T; ++ ++#define RG_SX_A21 (RF_D_SX_REG_BASE + 0x54) ++// Bit 3 :0 ro_wf_sx_log5g_mxr_banksel_8 U RO default = 'h0 ++// Bit 7 :4 ro_wf_sx_log5g_mxr_banksel_9 U RO default = 'h0 ++// Bit 11 :8 ro_wf_sx_log2g_mxr_banksel U RO default = 'h0 ++typedef union RG_SX_A21_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_8 : 4; ++ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_9 : 4; ++ unsigned int RO_WF_SX_LOG2G_MXR_BANKSEL : 4; ++ unsigned int rsvd_0 : 20; ++ } b; ++} RG_SX_A21_FIELD_T; ++ ++#define RG_SX_A23 (RF_D_SX_REG_BASE + 0x5c) ++// Bit 0 rg_m0_wf_sx_vco_en U RW default = 'h0 ++// Bit 1 rg_m0_wf_sx_vco_acal_en U RW default = 'h0 ++// Bit 2 rg_m0_wf_sx_pfd_en U RW default = 'h0 ++// Bit 3 rg_m0_wf_sx_cp_en U RW default = 'h0 ++// Bit 4 rg_m0_wf_sx_vco_ldo_en U RW default = 'h0 ++// Bit 5 rg_m0_wf_sx_cp_ldo_en U RW default = 'h0 ++// Bit 6 rg_m0_wf_sx_lpf_comp_en U RW default = 'h0 ++// Bit 7 rg_m0_wf_sx_log5g_mxr_en U RW default = 'h0 ++// Bit 8 rg_m0_wf_sx_log5g_inv_en U RW default = 'h0 ++// Bit 9 rg_m0_wf_sx_log5g_div_en U RW default = 'h0 ++// Bit 10 rg_m0_wf_sx_log5g_iqdiv_en U RW default = 'h0 ++// Bit 11 rg_m0_wf_sx_log5g_rxlo_en U RW default = 'h0 ++// Bit 12 rg_m0_wf_sx_log5g_dpdlo_en U RW default = 'h0 ++// Bit 13 rg_m0_wf_sx_log5g_txlo_en U RW default = 'h0 ++// Bit 14 rg_m0_wf_sx_log2g_mxr_en U RW default = 'h0 ++// Bit 15 rg_m0_wf_sx_log2g_div_en U RW default = 'h0 ++// Bit 16 rg_m0_wf_sx_log2g_iqdiv_en U RW default = 'h0 ++// Bit 17 rg_m0_wf_sx_log2g_rxlo_en U RW default = 'h0 ++// Bit 18 rg_m0_wf_sx_log2g_dpdlo_en U RW default = 'h0 ++// Bit 19 rg_m0_wf_sx_log2g_txlo_en U RW default = 'h0 ++typedef union RG_SX_A23_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M0_WF_SX_VCO_EN : 1; ++ unsigned int RG_M0_WF_SX_VCO_ACAL_EN : 1; ++ unsigned int RG_M0_WF_SX_PFD_EN : 1; ++ unsigned int RG_M0_WF_SX_CP_EN : 1; ++ unsigned int RG_M0_WF_SX_VCO_LDO_EN : 1; ++ unsigned int RG_M0_WF_SX_CP_LDO_EN : 1; ++ unsigned int RG_M0_WF_SX_LPF_COMP_EN : 1; ++ unsigned int RG_M0_WF_SX_LOG5G_MXR_EN : 1; ++ unsigned int RG_M0_WF_SX_LOG5G_INV_EN : 1; ++ unsigned int RG_M0_WF_SX_LOG5G_DIV_EN : 1; ++ unsigned int RG_M0_WF_SX_LOG5G_IQDIV_EN : 1; ++ unsigned int RG_M0_WF_SX_LOG5G_RXLO_EN : 1; ++ unsigned int RG_M0_WF_SX_LOG5G_DPDLO_EN : 1; ++ unsigned int RG_M0_WF_SX_LOG5G_TXLO_EN : 1; ++ unsigned int RG_M0_WF_SX_LOG2G_MXR_EN : 1; ++ unsigned int RG_M0_WF_SX_LOG2G_DIV_EN : 1; ++ unsigned int RG_M0_WF_SX_LOG2G_IQDIV_EN : 1; ++ unsigned int RG_M0_WF_SX_LOG2G_RXLO_EN : 1; ++ unsigned int RG_M0_WF_SX_LOG2G_DPDLO_EN : 1; ++ unsigned int RG_M0_WF_SX_LOG2G_TXLO_EN : 1; ++ unsigned int rsvd_0 : 12; ++ } b; ++} RG_SX_A23_FIELD_T; ++ ++#define RG_SX_A24 (RF_D_SX_REG_BASE + 0x60) ++// Bit 0 rg_m1_wf_sx_vco_en U RW default = 'h1 ++// Bit 1 rg_m1_wf_sx_vco_acal_en U RW default = 'h1 ++// Bit 2 rg_m1_wf_sx_pfd_en U RW default = 'h1 ++// Bit 3 rg_m1_wf_sx_cp_en U RW default = 'h1 ++// Bit 4 rg_m1_wf_sx_vco_ldo_en U RW default = 'h1 ++// Bit 5 rg_m1_wf_sx_cp_ldo_en U RW default = 'h1 ++// Bit 6 rg_m1_wf_sx_lpf_comp_en U RW default = 'h1 ++// Bit 7 rg_m1_wf_sx_log5g_mxr_en U RW default = 'h1 ++// Bit 8 rg_m1_wf_sx_log5g_inv_en U RW default = 'h1 ++// Bit 9 rg_m1_wf_sx_log5g_div_en U RW default = 'h1 ++// Bit 10 rg_m1_wf_sx_log5g_iqdiv_en U RW default = 'h1 ++// Bit 11 rg_m1_wf_sx_log5g_rxlo_en U RW default = 'h0 ++// Bit 12 rg_m1_wf_sx_log5g_dpdlo_en U RW default = 'h0 ++// Bit 13 rg_m1_wf_sx_log5g_txlo_en U RW default = 'h0 ++// Bit 14 rg_m1_wf_sx_log2g_mxr_en U RW default = 'h0 ++// Bit 15 rg_m1_wf_sx_log2g_div_en U RW default = 'h0 ++// Bit 16 rg_m1_wf_sx_log2g_iqdiv_en U RW default = 'h0 ++// Bit 17 rg_m1_wf_sx_log2g_rxlo_en U RW default = 'h0 ++// Bit 18 rg_m1_wf_sx_log2g_dpdlo_en U RW default = 'h0 ++// Bit 19 rg_m1_wf_sx_log2g_txlo_en U RW default = 'h0 ++typedef union RG_SX_A24_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M1_WF_SX_VCO_EN : 1; ++ unsigned int RG_M1_WF_SX_VCO_ACAL_EN : 1; ++ unsigned int RG_M1_WF_SX_PFD_EN : 1; ++ unsigned int RG_M1_WF_SX_CP_EN : 1; ++ unsigned int RG_M1_WF_SX_VCO_LDO_EN : 1; ++ unsigned int RG_M1_WF_SX_CP_LDO_EN : 1; ++ unsigned int RG_M1_WF_SX_LPF_COMP_EN : 1; ++ unsigned int RG_M1_WF_SX_LOG5G_MXR_EN : 1; ++ unsigned int RG_M1_WF_SX_LOG5G_INV_EN : 1; ++ unsigned int RG_M1_WF_SX_LOG5G_DIV_EN : 1; ++ unsigned int RG_M1_WF_SX_LOG5G_IQDIV_EN : 1; ++ unsigned int RG_M1_WF_SX_LOG5G_RXLO_EN : 1; ++ unsigned int RG_M1_WF_SX_LOG5G_DPDLO_EN : 1; ++ unsigned int RG_M1_WF_SX_LOG5G_TXLO_EN : 1; ++ unsigned int RG_M1_WF_SX_LOG2G_MXR_EN : 1; ++ unsigned int RG_M1_WF_SX_LOG2G_DIV_EN : 1; ++ unsigned int RG_M1_WF_SX_LOG2G_IQDIV_EN : 1; ++ unsigned int RG_M1_WF_SX_LOG2G_RXLO_EN : 1; ++ unsigned int RG_M1_WF_SX_LOG2G_DPDLO_EN : 1; ++ unsigned int RG_M1_WF_SX_LOG2G_TXLO_EN : 1; ++ unsigned int rsvd_0 : 12; ++ } b; ++} RG_SX_A24_FIELD_T; ++ ++#define RG_SX_A25 (RF_D_SX_REG_BASE + 0x64) ++// Bit 0 rg_m2_wf_sx_vco_en U RW default = 'h1 ++// Bit 1 rg_m2_wf_sx_vco_acal_en U RW default = 'h1 ++// Bit 2 rg_m2_wf_sx_pfd_en U RW default = 'h1 ++// Bit 3 rg_m2_wf_sx_cp_en U RW default = 'h1 ++// Bit 4 rg_m2_wf_sx_vco_ldo_en U RW default = 'h1 ++// Bit 5 rg_m2_wf_sx_cp_ldo_en U RW default = 'h1 ++// Bit 6 rg_m2_wf_sx_lpf_comp_en U RW default = 'h1 ++// Bit 7 rg_m2_wf_sx_log5g_mxr_en U RW default = 'h1 ++// Bit 8 rg_m2_wf_sx_log5g_inv_en U RW default = 'h1 ++// Bit 9 rg_m2_wf_sx_log5g_div_en U RW default = 'h1 ++// Bit 10 rg_m2_wf_sx_log5g_iqdiv_en U RW default = 'h1 ++// Bit 11 rg_m2_wf_sx_log5g_rxlo_en U RW default = 'h0 ++// Bit 12 rg_m2_wf_sx_log5g_dpdlo_en U RW default = 'h0 ++// Bit 13 rg_m2_wf_sx_log5g_txlo_en U RW default = 'h1 ++// Bit 14 rg_m2_wf_sx_log2g_mxr_en U RW default = 'h0 ++// Bit 15 rg_m2_wf_sx_log2g_div_en U RW default = 'h0 ++// Bit 16 rg_m2_wf_sx_log2g_iqdiv_en U RW default = 'h0 ++// Bit 17 rg_m2_wf_sx_log2g_rxlo_en U RW default = 'h0 ++// Bit 18 rg_m2_wf_sx_log2g_dpdlo_en U RW default = 'h0 ++// Bit 19 rg_m2_wf_sx_log2g_txlo_en U RW default = 'h1 ++typedef union RG_SX_A25_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M2_WF_SX_VCO_EN : 1; ++ unsigned int RG_M2_WF_SX_VCO_ACAL_EN : 1; ++ unsigned int RG_M2_WF_SX_PFD_EN : 1; ++ unsigned int RG_M2_WF_SX_CP_EN : 1; ++ unsigned int RG_M2_WF_SX_VCO_LDO_EN : 1; ++ unsigned int RG_M2_WF_SX_CP_LDO_EN : 1; ++ unsigned int RG_M2_WF_SX_LPF_COMP_EN : 1; ++ unsigned int RG_M2_WF_SX_LOG5G_MXR_EN : 1; ++ unsigned int RG_M2_WF_SX_LOG5G_INV_EN : 1; ++ unsigned int RG_M2_WF_SX_LOG5G_DIV_EN : 1; ++ unsigned int RG_M2_WF_SX_LOG5G_IQDIV_EN : 1; ++ unsigned int RG_M2_WF_SX_LOG5G_RXLO_EN : 1; ++ unsigned int RG_M2_WF_SX_LOG5G_DPDLO_EN : 1; ++ unsigned int RG_M2_WF_SX_LOG5G_TXLO_EN : 1; ++ unsigned int RG_M2_WF_SX_LOG2G_MXR_EN : 1; ++ unsigned int RG_M2_WF_SX_LOG2G_DIV_EN : 1; ++ unsigned int RG_M2_WF_SX_LOG2G_IQDIV_EN : 1; ++ unsigned int RG_M2_WF_SX_LOG2G_RXLO_EN : 1; ++ unsigned int RG_M2_WF_SX_LOG2G_DPDLO_EN : 1; ++ unsigned int RG_M2_WF_SX_LOG2G_TXLO_EN : 1; ++ unsigned int rsvd_0 : 12; ++ } b; ++} RG_SX_A25_FIELD_T; ++ ++#define RG_SX_A26 (RF_D_SX_REG_BASE + 0x68) ++// Bit 0 rg_m3_wf_sx_vco_en U RW default = 'h1 ++// Bit 1 rg_m3_wf_sx_vco_acal_en U RW default = 'h1 ++// Bit 2 rg_m3_wf_sx_pfd_en U RW default = 'h1 ++// Bit 3 rg_m3_wf_sx_cp_en U RW default = 'h1 ++// Bit 4 rg_m3_wf_sx_vco_ldo_en U RW default = 'h1 ++// Bit 5 rg_m3_wf_sx_cp_ldo_en U RW default = 'h1 ++// Bit 6 rg_m3_wf_sx_lpf_comp_en U RW default = 'h1 ++// Bit 7 rg_m3_wf_sx_log5g_mxr_en U RW default = 'h1 ++// Bit 8 rg_m3_wf_sx_log5g_inv_en U RW default = 'h1 ++// Bit 9 rg_m3_wf_sx_log5g_div_en U RW default = 'h1 ++// Bit 10 rg_m3_wf_sx_log5g_iqdiv_en U RW default = 'h1 ++// Bit 11 rg_m3_wf_sx_log5g_rxlo_en U RW default = 'h1 ++// Bit 12 rg_m3_wf_sx_log5g_dpdlo_en U RW default = 'h0 ++// Bit 13 rg_m3_wf_sx_log5g_txlo_en U RW default = 'h0 ++// Bit 14 rg_m3_wf_sx_log2g_mxr_en U RW default = 'h0 ++// Bit 15 rg_m3_wf_sx_log2g_div_en U RW default = 'h0 ++// Bit 16 rg_m3_wf_sx_log2g_iqdiv_en U RW default = 'h0 ++// Bit 17 rg_m3_wf_sx_log2g_rxlo_en U RW default = 'h0 ++// Bit 18 rg_m3_wf_sx_log2g_dpdlo_en U RW default = 'h0 ++// Bit 19 rg_m3_wf_sx_log2g_txlo_en U RW default = 'h0 ++typedef union RG_SX_A26_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M3_WF_SX_VCO_EN : 1; ++ unsigned int RG_M3_WF_SX_VCO_ACAL_EN : 1; ++ unsigned int RG_M3_WF_SX_PFD_EN : 1; ++ unsigned int RG_M3_WF_SX_CP_EN : 1; ++ unsigned int RG_M3_WF_SX_VCO_LDO_EN : 1; ++ unsigned int RG_M3_WF_SX_CP_LDO_EN : 1; ++ unsigned int RG_M3_WF_SX_LPF_COMP_EN : 1; ++ unsigned int RG_M3_WF_SX_LOG5G_MXR_EN : 1; ++ unsigned int RG_M3_WF_SX_LOG5G_INV_EN : 1; ++ unsigned int RG_M3_WF_SX_LOG5G_DIV_EN : 1; ++ unsigned int RG_M3_WF_SX_LOG5G_IQDIV_EN : 1; ++ unsigned int RG_M3_WF_SX_LOG5G_RXLO_EN : 1; ++ unsigned int RG_M3_WF_SX_LOG5G_DPDLO_EN : 1; ++ unsigned int RG_M3_WF_SX_LOG5G_TXLO_EN : 1; ++ unsigned int RG_M3_WF_SX_LOG2G_MXR_EN : 1; ++ unsigned int RG_M3_WF_SX_LOG2G_DIV_EN : 1; ++ unsigned int RG_M3_WF_SX_LOG2G_IQDIV_EN : 1; ++ unsigned int RG_M3_WF_SX_LOG2G_RXLO_EN : 1; ++ unsigned int RG_M3_WF_SX_LOG2G_DPDLO_EN : 1; ++ unsigned int RG_M3_WF_SX_LOG2G_TXLO_EN : 1; ++ unsigned int rsvd_0 : 12; ++ } b; ++} RG_SX_A26_FIELD_T; ++ ++#define RG_SX_A27 (RF_D_SX_REG_BASE + 0x6c) ++// Bit 31 :0 rg_wf_sx_dig_rsv0 U RW default = 'hffff ++typedef union RG_SX_A27_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_DIG_RSV0 : 32; ++ } b; ++} RG_SX_A27_FIELD_T; ++ ++#define RG_SX_A32 (RF_D_SX_REG_BASE + 0x80) ++// Bit 2 :0 rg_wf_sx_lpf_bw U RW default = 'h7 ++// Bit 5 :4 rg_wf_sx_pfd_delay U RW default = 'h0 ++// Bit 10 :8 rg_wf_sx_cp_offset U RW default = 'h5 ++// Bit 13 :12 rg_wf_sx_stable_cnt U RW default = 'h0 ++// Bit 16 rg_wf_sx_stable_en_man_mode U RW default = 'h0 ++// Bit 20 rg_wf_sx_stable_en_man U RW default = 'h0 ++typedef union RG_SX_A32_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_LPF_BW : 3; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF_SX_PFD_DELAY : 2; ++ unsigned int rsvd_1 : 2; ++ unsigned int RG_WF_SX_CP_OFFSET : 3; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF_SX_STABLE_CNT : 2; ++ unsigned int rsvd_3 : 2; ++ unsigned int RG_WF_SX_STABLE_EN_MAN_MODE : 1; ++ unsigned int rsvd_4 : 3; ++ unsigned int RG_WF_SX_STABLE_EN_MAN : 1; ++ unsigned int rsvd_5 : 11; ++ } b; ++} RG_SX_A32_FIELD_T; ++ ++#define RG_SX_A34 (RF_D_SX_REG_BASE + 0x88) ++// Bit 8 :4 rg_wf_sx_vco_ldo_vref_adj U RW default = 'h14 ++// Bit 20 :16 rg_wf_sx_cp_ldo_vref_adj U RW default = 'h10 ++typedef union RG_SX_A34_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rsvd_0 : 4; ++ unsigned int RG_WF_SX_VCO_LDO_VREF_ADJ : 5; ++ unsigned int rsvd_1 : 7; ++ unsigned int RG_WF_SX_CP_LDO_VREF_ADJ : 5; ++ unsigned int rsvd_2 : 11; ++ } b; ++} RG_SX_A34_FIELD_T; ++ ++#define RG_SX_A35 (RF_D_SX_REG_BASE + 0x8c) ++// Bit 2 :0 rg_wf_sx_cp_i U RW default = 'h5 ++// Bit 4 :3 rg_wf_sx_pfd_lock_t U RW default = 'h0 ++// Bit 5 rg_wf_sx_pfd_ph_en U RW default = 'h1 ++// Bit 6 rg_wf_sx_pfd_sel U RW default = 'h0 ++// Bit 8 rg_wf_sx_mmd_pw_en U RW default = 'h1 ++// Bit 9 rg_wf_sx_cp_bypass_mode U RW default = 'h0 ++// Bit 10 rg_wf_sx_lpf_bypass_mode U RW default = 'h0 ++// Bit 11 rg_wf_sx_lpf_resample_mode U RW default = 'h1 ++// Bit 12 rg_wf_sx_cp_cali_ctrl U RW default = 'h0 ++// Bit 13 rg_wf_sx_lpf_cali_ctrl U RW default = 'h0 ++// Bit 14 rg_wf_sx_cp_rc_ctrl U RW default = 'h0 ++// Bit 15 rg_wf_sx_ldo_hf_rc_ctrl U RW default = 'h1 ++// Bit 16 rg_wf_sx_ldo_hf_rc_modesel U RW default = 'h0 ++// Bit 17 rg_wf_sx_ldo_lf_rc_ctrl U RW default = 'h1 ++// Bit 18 rg_wf_sx_ldo_lf_rc_modesel U RW default = 'h0 ++// Bit 19 rg_wf_sx_pll_rst_man U RW default = 'h0 ++// Bit 20 rg_wf_sx_pll_rst_man_val U RW default = 'h0 ++// Bit 22 :21 rg_wf_sx_vctrl_sel U RW default = 'h0 ++// Bit 24 :23 rg_wf_sx_vco_var_dc U RW default = 'h3 ++// Bit 25 rg_wf_sx_fcal_div U RW default = 'h1 ++// Bit 27 :26 rg_wf_sx_vco_2nd_capn U RW default = 'h1 ++// Bit 29 :28 rg_wf_sx_vco_2nd_capp U RW default = 'h1 ++// Bit 30 rg_sx_vco_lpf_testmode U RW default = 'h0 ++typedef union RG_SX_A35_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_CP_I : 3; ++ unsigned int RG_WF_SX_PFD_LOCK_T : 2; ++ unsigned int RG_WF_SX_PFD_PH_EN : 1; ++ unsigned int RG_WF_SX_PFD_SEL : 1; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF_SX_MMD_PW_EN : 1; ++ unsigned int RG_WF_SX_CP_BYPASS_MODE : 1; ++ unsigned int RG_WF_SX_LPF_BYPASS_MODE : 1; ++ unsigned int RG_WF_SX_LPF_RESAMPLE_MODE : 1; ++ unsigned int RG_WF_SX_CP_CALI_CTRL : 1; ++ unsigned int RG_WF_SX_LPF_CALI_CTRL : 1; ++ unsigned int RG_WF_SX_CP_RC_CTRL : 1; ++ unsigned int RG_WF_SX_LDO_HF_RC_CTRL : 1; ++ unsigned int RG_WF_SX_LDO_HF_RC_MODESEL : 1; ++ unsigned int RG_WF_SX_LDO_LF_RC_CTRL : 1; ++ unsigned int RG_WF_SX_LDO_LF_RC_MODESEL : 1; ++ unsigned int RG_WF_SX_PLL_RST_MAN : 1; ++ unsigned int RG_WF_SX_PLL_RST_MAN_VAL : 1; ++ unsigned int RG_WF_SX_VCTRL_SEL : 2; ++ unsigned int RG_WF_SX_VCO_VAR_DC : 2; ++ unsigned int RG_WF_SX_FCAL_DIV : 1; ++ unsigned int RG_WF_SX_VCO_2ND_CAPN : 2; ++ unsigned int RG_WF_SX_VCO_2ND_CAPP : 2; ++ unsigned int RG_SX_VCO_LPF_TESTMODE : 1; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_SX_A35_FIELD_T; ++ ++#define RG_SX_A36 (RF_D_SX_REG_BASE + 0x90) ++// Bit 0 rg_wf_sx_log5g_pd_en_man U RW default = 'h0 ++// Bit 4 rg_wf_sx_log2g_pd_en_man U RW default = 'h0 ++// Bit 11 :8 rg_wf_sx_log5g_mxr_ictrl U RW default = 'ha ++// Bit 15 :12 rg_wf_sx_log5g_div_vdd U RW default = 'h1 ++// Bit 31 rg_wf_sx_log5g_reserve1 U RW default = 'h0 ++typedef union RG_SX_A36_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_LOG5G_PD_EN_MAN : 1; ++ unsigned int rsvd_0 : 3; ++ unsigned int RG_WF_SX_LOG2G_PD_EN_MAN : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int RG_WF_SX_LOG5G_MXR_ICTRL : 4; ++ unsigned int RG_WF_SX_LOG5G_DIV_VDD : 4; ++ unsigned int rsvd_2 : 15; ++ unsigned int RG_WF_SX_LOG5G_RESERVE1 : 1; ++ } b; ++} RG_SX_A36_FIELD_T; ++ ++#define RG_SX_A37 (RF_D_SX_REG_BASE + 0x94) ++// Bit 3 :0 rg_wf_sx_log5g_rxlo_vdd U RW default = 'h7 ++// Bit 7 :4 rg_wf_sx_log5g_dpdlo_vdd U RW default = 'h7 ++// Bit 11 :8 rg_wf_sx_log5g_txlo_vdd U RW default = 'h7 ++// Bit 15 :12 rg_wf_sx_log5g_iqdiv_rctrl U RW default = 'h0 ++// Bit 20 :16 rg_wf_sx_log5g_iqdiv_ictrl U RW default = 'h6 ++typedef union RG_SX_A37_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_LOG5G_RXLO_VDD : 4; ++ unsigned int RG_WF_SX_LOG5G_DPDLO_VDD : 4; ++ unsigned int RG_WF_SX_LOG5G_TXLO_VDD : 4; ++ unsigned int RG_WF_SX_LOG5G_IQDIV_RCTRL : 4; ++ unsigned int RG_WF_SX_LOG5G_IQDIV_ICTRL : 5; ++ unsigned int rsvd_0 : 11; ++ } b; ++} RG_SX_A37_FIELD_T; ++ ++#define RG_SX_A38 (RF_D_SX_REG_BASE + 0x98) ++// Bit 3 :0 rg_wf_sx_log2g_mxr_vdd U RW default = 'hf ++// Bit 7 :4 rg_wf_sx_log2g_div_vdd U RW default = 'h1 ++// Bit 11 :8 rg_wf_sx_log2g_iqdiv_vdd U RW default = 'h1 ++// Bit 15 :12 rg_wf_sx_log2g_rxlo_vdd U RW default = 'h4 ++// Bit 19 :16 rg_wf_sx_log2g_dpdlo_vdd U RW default = 'h4 ++// Bit 23 :20 rg_wf_sx_log2g_txlo_vdd U RW default = 'h4 ++typedef union RG_SX_A38_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_LOG2G_MXR_VDD : 4; ++ unsigned int RG_WF_SX_LOG2G_DIV_VDD : 4; ++ unsigned int RG_WF_SX_LOG2G_IQDIV_VDD : 4; ++ unsigned int RG_WF_SX_LOG2G_RXLO_VDD : 4; ++ unsigned int RG_WF_SX_LOG2G_DPDLO_VDD : 4; ++ unsigned int RG_WF_SX_LOG2G_TXLO_VDD : 4; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_SX_A38_FIELD_T; ++ ++#define RG_SX_A42 (RF_D_SX_REG_BASE + 0xa8) ++// Bit 31 :0 rg_wf_sx_rsv0 U RW default = 'hfffb ++typedef union RG_SX_A42_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_RSV0 : 32; ++ } b; ++} RG_SX_A42_FIELD_T; ++ ++#define RG_SX_A43 (RF_D_SX_REG_BASE + 0xac) ++// Bit 31 :0 rg_wf_sx_rsv1 U RW default = 'hffff ++typedef union RG_SX_A43_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_RSV1 : 32; ++ } b; ++} RG_SX_A43_FIELD_T; ++ ++#define RG_SX_A44 (RF_D_SX_REG_BASE + 0xb0) ++// Bit 0 rg_wf_sx_double_edge_sel U RW default = 'h0 ++// Bit 1 rg_wf_sx_double_bypass_mode U RW default = 'h1 ++// Bit 2 rg_wf_sx_double_dig_loop_en U RW default = 'h0 ++// Bit 3 rg_wf_sx_double_ana_loop_en U RW default = 'h0 ++// Bit 4 rg_wf_sx_double_half_lsb_ctrl U RW default = 'h0 ++// Bit 5 rg_wf_sx_double_half_lsb_sel U RW default = 'h1 ++// Bit 6 rg_wf_sx_double_post_delay_en U RW default = 'h1 ++// Bit 7 rg_wf_sx_double_pre_delay_en U RW default = 'h1 ++// Bit 8 rg_wf_sx_double_op_en U RW default = 'h1 ++// Bit 11 :9 rg_wf_sx_double_vref_sel U RW default = 'h4 ++// Bit 19 :12 rg_wf_sx_double_reserved U RW default = 'h0 ++// Bit 21 rg_wf_sx_double_rst_man_mode U RW default = 'h0 ++// Bit 22 rg_wf_sx_double_rst_man U RW default = 'h0 ++// Bit 23 rg_wf_sx_double_tune_man_mode U RW default = 'h0 ++// Bit 30 :24 rg_wf_sx_double_tune_man U RW default = 'h0 ++typedef union RG_SX_A44_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_DOUBLE_EDGE_SEL : 1; ++ unsigned int RG_WF_SX_DOUBLE_BYPASS_MODE : 1; ++ unsigned int RG_WF_SX_DOUBLE_DIG_LOOP_EN : 1; ++ unsigned int RG_WF_SX_DOUBLE_ANA_LOOP_EN : 1; ++ unsigned int RG_WF_SX_DOUBLE_HALF_LSB_CTRL : 1; ++ unsigned int RG_WF_SX_DOUBLE_HALF_LSB_SEL : 1; ++ unsigned int RG_WF_SX_DOUBLE_POST_DELAY_EN : 1; ++ unsigned int RG_WF_SX_DOUBLE_PRE_DELAY_EN : 1; ++ unsigned int RG_WF_SX_DOUBLE_OP_EN : 1; ++ unsigned int RG_WF_SX_DOUBLE_VREF_SEL : 3; ++ unsigned int RG_WF_SX_DOUBLE_RESERVED : 8; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF_SX_DOUBLE_RST_MAN_MODE : 1; ++ unsigned int RG_WF_SX_DOUBLE_RST_MAN : 1; ++ unsigned int RG_WF_SX_DOUBLE_TUNE_MAN_MODE : 1; ++ unsigned int RG_WF_SX_DOUBLE_TUNE_MAN : 7; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_SX_A44_FIELD_T; ++ ++#define RG_SX_A45 (RF_D_SX_REG_BASE + 0xb4) ++// Bit 0 rg_wf_sx_open_drain_tp_en U RW default = 'h0 ++// Bit 1 rg_wf_sx_vco_vctrl_tp_sel U RW default = 'h0 ++// Bit 2 rg_wf_sx_tp_en U RW default = 'h0 ++// Bit 5 :3 rg_wf_sx_tp_sel U RW default = 'h4 ++// Bit 6 rg_wf_sx_fb_clk_edge_sel U RW default = 'h0 ++// Bit 7 rg_wf_sx_clk_edge_sel U RW default = 'h0 ++// Bit 8 rg_wf_sx_double_cali_en U RW default = 'h0 ++// Bit 9 rg_wf_sx_double_en U RW default = 'h0 ++// Bit 13 :12 rg_wf_sx_double_waittime_25u U RW default = 'h0 ++// Bit 15 :14 rg_wf_sx_double_waittime_40u U RW default = 'h0 ++// Bit 23 :16 rg_wf_sx_double_check_code_cnt U RW default = 'h80 ++// Bit 31 rg_wf_sx_double_duty_flag_sel U RW default = 'h0 ++typedef union RG_SX_A45_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_SX_OPEN_DRAIN_TP_EN : 1; ++ unsigned int RG_WF_SX_VCO_VCTRL_TP_SEL : 1; ++ unsigned int RG_WF_SX_TP_EN : 1; ++ unsigned int RG_WF_SX_TP_SEL : 3; ++ unsigned int RG_WF_SX_FB_CLK_EDGE_SEL : 1; ++ unsigned int RG_WF_SX_CLK_EDGE_SEL : 1; ++ unsigned int RG_WF_SX_DOUBLE_CALI_EN : 1; ++ unsigned int RG_WF_SX_DOUBLE_EN : 1; ++ unsigned int rsvd_0 : 2; ++ unsigned int RG_WF_SX_DOUBLE_WAITTIME_25U : 2; ++ unsigned int RG_WF_SX_DOUBLE_WAITTIME_40U : 2; ++ unsigned int RG_WF_SX_DOUBLE_CHECK_CODE_CNT : 8; ++ unsigned int rsvd_1 : 7; ++ unsigned int RG_WF_SX_DOUBLE_DUTY_FLAG_SEL : 1; ++ } b; ++} RG_SX_A45_FIELD_T; ++ ++#define RG_SX_A46 (RF_D_SX_REG_BASE + 0xb8) ++// Bit 0 rg_m4_wf_sx_vco_en U RW default = 'h1 ++// Bit 1 rg_m4_wf_sx_vco_acal_en U RW default = 'h1 ++// Bit 2 rg_m4_wf_sx_pfd_en U RW default = 'h1 ++// Bit 3 rg_m4_wf_sx_cp_en U RW default = 'h1 ++// Bit 4 rg_m4_wf_sx_vco_ldo_en U RW default = 'h1 ++// Bit 5 rg_m4_wf_sx_cp_ldo_en U RW default = 'h1 ++// Bit 6 rg_m4_wf_sx_lpf_comp_en U RW default = 'h1 ++// Bit 7 rg_m4_wf_sx_log5g_mxr_en U RW default = 'h1 ++// Bit 8 rg_m4_wf_sx_log5g_inv_en U RW default = 'h1 ++// Bit 9 rg_m4_wf_sx_log5g_div_en U RW default = 'h1 ++// Bit 10 rg_m4_wf_sx_log5g_iqdiv_en U RW default = 'h1 ++// Bit 11 rg_m4_wf_sx_log5g_rxlo_en U RW default = 'h0 ++// Bit 12 rg_m4_wf_sx_log5g_dpdlo_en U RW default = 'h1 ++// Bit 13 rg_m4_wf_sx_log5g_txlo_en U RW default = 'h1 ++// Bit 14 rg_m4_wf_sx_log2g_mxr_en U RW default = 'h0 ++// Bit 15 rg_m4_wf_sx_log2g_div_en U RW default = 'h0 ++// Bit 16 rg_m4_wf_sx_log2g_iqdiv_en U RW default = 'h0 ++// Bit 17 rg_m4_wf_sx_log2g_rxlo_en U RW default = 'h0 ++// Bit 18 rg_m4_wf_sx_log2g_dpdlo_en U RW default = 'h0 ++// Bit 19 rg_m4_wf_sx_log2g_txlo_en U RW default = 'h0 ++typedef union RG_SX_A46_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M4_WF_SX_VCO_EN : 1; ++ unsigned int RG_M4_WF_SX_VCO_ACAL_EN : 1; ++ unsigned int RG_M4_WF_SX_PFD_EN : 1; ++ unsigned int RG_M4_WF_SX_CP_EN : 1; ++ unsigned int RG_M4_WF_SX_VCO_LDO_EN : 1; ++ unsigned int RG_M4_WF_SX_CP_LDO_EN : 1; ++ unsigned int RG_M4_WF_SX_LPF_COMP_EN : 1; ++ unsigned int RG_M4_WF_SX_LOG5G_MXR_EN : 1; ++ unsigned int RG_M4_WF_SX_LOG5G_INV_EN : 1; ++ unsigned int RG_M4_WF_SX_LOG5G_DIV_EN : 1; ++ unsigned int RG_M4_WF_SX_LOG5G_IQDIV_EN : 1; ++ unsigned int RG_M4_WF_SX_LOG5G_RXLO_EN : 1; ++ unsigned int RG_M4_WF_SX_LOG5G_DPDLO_EN : 1; ++ unsigned int RG_M4_WF_SX_LOG5G_TXLO_EN : 1; ++ unsigned int RG_M4_WF_SX_LOG2G_MXR_EN : 1; ++ unsigned int RG_M4_WF_SX_LOG2G_DIV_EN : 1; ++ unsigned int RG_M4_WF_SX_LOG2G_IQDIV_EN : 1; ++ unsigned int RG_M4_WF_SX_LOG2G_RXLO_EN : 1; ++ unsigned int RG_M4_WF_SX_LOG2G_DPDLO_EN : 1; ++ unsigned int RG_M4_WF_SX_LOG2G_TXLO_EN : 1; ++ unsigned int rsvd_0 : 12; ++ } b; ++} RG_SX_A46_FIELD_T; ++ ++#define RG_SX_A47 (RF_D_SX_REG_BASE + 0xbc) ++// Bit 0 rg_m5_wf_sx_vco_en U RW default = 'h1 ++// Bit 1 rg_m5_wf_sx_vco_acal_en U RW default = 'h1 ++// Bit 2 rg_m5_wf_sx_pfd_en U RW default = 'h1 ++// Bit 3 rg_m5_wf_sx_cp_en U RW default = 'h1 ++// Bit 4 rg_m5_wf_sx_vco_ldo_en U RW default = 'h1 ++// Bit 5 rg_m5_wf_sx_cp_ldo_en U RW default = 'h1 ++// Bit 6 rg_m5_wf_sx_lpf_comp_en U RW default = 'h1 ++// Bit 7 rg_m5_wf_sx_log5g_mxr_en U RW default = 'h0 ++// Bit 8 rg_m5_wf_sx_log5g_inv_en U RW default = 'h0 ++// Bit 9 rg_m5_wf_sx_log5g_div_en U RW default = 'h0 ++// Bit 10 rg_m5_wf_sx_log5g_iqdiv_en U RW default = 'h0 ++// Bit 11 rg_m5_wf_sx_log5g_rxlo_en U RW default = 'h0 ++// Bit 12 rg_m5_wf_sx_log5g_dpdlo_en U RW default = 'h0 ++// Bit 13 rg_m5_wf_sx_log5g_txlo_en U RW default = 'h0 ++// Bit 14 rg_m5_wf_sx_log2g_mxr_en U RW default = 'h1 ++// Bit 15 rg_m5_wf_sx_log2g_div_en U RW default = 'h1 ++// Bit 16 rg_m5_wf_sx_log2g_iqdiv_en U RW default = 'h1 ++// Bit 17 rg_m5_wf_sx_log2g_rxlo_en U RW default = 'h0 ++// Bit 18 rg_m5_wf_sx_log2g_dpdlo_en U RW default = 'h0 ++// Bit 19 rg_m5_wf_sx_log2g_txlo_en U RW default = 'h0 ++typedef union RG_SX_A47_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M5_WF_SX_VCO_EN : 1; ++ unsigned int RG_M5_WF_SX_VCO_ACAL_EN : 1; ++ unsigned int RG_M5_WF_SX_PFD_EN : 1; ++ unsigned int RG_M5_WF_SX_CP_EN : 1; ++ unsigned int RG_M5_WF_SX_VCO_LDO_EN : 1; ++ unsigned int RG_M5_WF_SX_CP_LDO_EN : 1; ++ unsigned int RG_M5_WF_SX_LPF_COMP_EN : 1; ++ unsigned int RG_M5_WF_SX_LOG5G_MXR_EN : 1; ++ unsigned int RG_M5_WF_SX_LOG5G_INV_EN : 1; ++ unsigned int RG_M5_WF_SX_LOG5G_DIV_EN : 1; ++ unsigned int RG_M5_WF_SX_LOG5G_IQDIV_EN : 1; ++ unsigned int RG_M5_WF_SX_LOG5G_RXLO_EN : 1; ++ unsigned int RG_M5_WF_SX_LOG5G_DPDLO_EN : 1; ++ unsigned int RG_M5_WF_SX_LOG5G_TXLO_EN : 1; ++ unsigned int RG_M5_WF_SX_LOG2G_MXR_EN : 1; ++ unsigned int RG_M5_WF_SX_LOG2G_DIV_EN : 1; ++ unsigned int RG_M5_WF_SX_LOG2G_IQDIV_EN : 1; ++ unsigned int RG_M5_WF_SX_LOG2G_RXLO_EN : 1; ++ unsigned int RG_M5_WF_SX_LOG2G_DPDLO_EN : 1; ++ unsigned int RG_M5_WF_SX_LOG2G_TXLO_EN : 1; ++ unsigned int rsvd_0 : 12; ++ } b; ++} RG_SX_A47_FIELD_T; ++ ++#define RG_SX_A48 (RF_D_SX_REG_BASE + 0xc0) ++// Bit 0 rg_m6_wf_sx_vco_en U RW default = 'h1 ++// Bit 1 rg_m6_wf_sx_vco_acal_en U RW default = 'h1 ++// Bit 2 rg_m6_wf_sx_pfd_en U RW default = 'h1 ++// Bit 3 rg_m6_wf_sx_cp_en U RW default = 'h1 ++// Bit 4 rg_m6_wf_sx_vco_ldo_en U RW default = 'h1 ++// Bit 5 rg_m6_wf_sx_cp_ldo_en U RW default = 'h1 ++// Bit 6 rg_m6_wf_sx_lpf_comp_en U RW default = 'h1 ++// Bit 7 rg_m6_wf_sx_log5g_mxr_en U RW default = 'h0 ++// Bit 8 rg_m6_wf_sx_log5g_inv_en U RW default = 'h0 ++// Bit 9 rg_m6_wf_sx_log5g_div_en U RW default = 'h0 ++// Bit 10 rg_m6_wf_sx_log5g_iqdiv_en U RW default = 'h0 ++// Bit 11 rg_m6_wf_sx_log5g_rxlo_en U RW default = 'h0 ++// Bit 12 rg_m6_wf_sx_log5g_dpdlo_en U RW default = 'h0 ++// Bit 13 rg_m6_wf_sx_log5g_txlo_en U RW default = 'h0 ++// Bit 14 rg_m6_wf_sx_log2g_mxr_en U RW default = 'h1 ++// Bit 15 rg_m6_wf_sx_log2g_div_en U RW default = 'h1 ++// Bit 16 rg_m6_wf_sx_log2g_iqdiv_en U RW default = 'h1 ++// Bit 17 rg_m6_wf_sx_log2g_rxlo_en U RW default = 'h0 ++// Bit 18 rg_m6_wf_sx_log2g_dpdlo_en U RW default = 'h0 ++// Bit 19 rg_m6_wf_sx_log2g_txlo_en U RW default = 'h1 ++typedef union RG_SX_A48_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M6_WF_SX_VCO_EN : 1; ++ unsigned int RG_M6_WF_SX_VCO_ACAL_EN : 1; ++ unsigned int RG_M6_WF_SX_PFD_EN : 1; ++ unsigned int RG_M6_WF_SX_CP_EN : 1; ++ unsigned int RG_M6_WF_SX_VCO_LDO_EN : 1; ++ unsigned int RG_M6_WF_SX_CP_LDO_EN : 1; ++ unsigned int RG_M6_WF_SX_LPF_COMP_EN : 1; ++ unsigned int RG_M6_WF_SX_LOG5G_MXR_EN : 1; ++ unsigned int RG_M6_WF_SX_LOG5G_INV_EN : 1; ++ unsigned int RG_M6_WF_SX_LOG5G_DIV_EN : 1; ++ unsigned int RG_M6_WF_SX_LOG5G_IQDIV_EN : 1; ++ unsigned int RG_M6_WF_SX_LOG5G_RXLO_EN : 1; ++ unsigned int RG_M6_WF_SX_LOG5G_DPDLO_EN : 1; ++ unsigned int RG_M6_WF_SX_LOG5G_TXLO_EN : 1; ++ unsigned int RG_M6_WF_SX_LOG2G_MXR_EN : 1; ++ unsigned int RG_M6_WF_SX_LOG2G_DIV_EN : 1; ++ unsigned int RG_M6_WF_SX_LOG2G_IQDIV_EN : 1; ++ unsigned int RG_M6_WF_SX_LOG2G_RXLO_EN : 1; ++ unsigned int RG_M6_WF_SX_LOG2G_DPDLO_EN : 1; ++ unsigned int RG_M6_WF_SX_LOG2G_TXLO_EN : 1; ++ unsigned int rsvd_0 : 12; ++ } b; ++} RG_SX_A48_FIELD_T; ++ ++#define RG_SX_A49 (RF_D_SX_REG_BASE + 0xc4) ++// Bit 0 rg_m7_wf_sx_vco_en U RW default = 'h1 ++// Bit 1 rg_m7_wf_sx_vco_acal_en U RW default = 'h1 ++// Bit 2 rg_m7_wf_sx_pfd_en U RW default = 'h1 ++// Bit 3 rg_m7_wf_sx_cp_en U RW default = 'h1 ++// Bit 4 rg_m7_wf_sx_vco_ldo_en U RW default = 'h1 ++// Bit 5 rg_m7_wf_sx_cp_ldo_en U RW default = 'h1 ++// Bit 6 rg_m7_wf_sx_lpf_comp_en U RW default = 'h1 ++// Bit 7 rg_m7_wf_sx_log5g_mxr_en U RW default = 'h0 ++// Bit 8 rg_m7_wf_sx_log5g_inv_en U RW default = 'h0 ++// Bit 9 rg_m7_wf_sx_log5g_div_en U RW default = 'h0 ++// Bit 10 rg_m7_wf_sx_log5g_iqdiv_en U RW default = 'h0 ++// Bit 11 rg_m7_wf_sx_log5g_rxlo_en U RW default = 'h0 ++// Bit 12 rg_m7_wf_sx_log5g_dpdlo_en U RW default = 'h0 ++// Bit 13 rg_m7_wf_sx_log5g_txlo_en U RW default = 'h0 ++// Bit 14 rg_m7_wf_sx_log2g_mxr_en U RW default = 'h1 ++// Bit 15 rg_m7_wf_sx_log2g_div_en U RW default = 'h1 ++// Bit 16 rg_m7_wf_sx_log2g_iqdiv_en U RW default = 'h1 ++// Bit 17 rg_m7_wf_sx_log2g_rxlo_en U RW default = 'h1 ++// Bit 18 rg_m7_wf_sx_log2g_dpdlo_en U RW default = 'h0 ++// Bit 19 rg_m7_wf_sx_log2g_txlo_en U RW default = 'h0 ++typedef union RG_SX_A49_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M7_WF_SX_VCO_EN : 1; ++ unsigned int RG_M7_WF_SX_VCO_ACAL_EN : 1; ++ unsigned int RG_M7_WF_SX_PFD_EN : 1; ++ unsigned int RG_M7_WF_SX_CP_EN : 1; ++ unsigned int RG_M7_WF_SX_VCO_LDO_EN : 1; ++ unsigned int RG_M7_WF_SX_CP_LDO_EN : 1; ++ unsigned int RG_M7_WF_SX_LPF_COMP_EN : 1; ++ unsigned int RG_M7_WF_SX_LOG5G_MXR_EN : 1; ++ unsigned int RG_M7_WF_SX_LOG5G_INV_EN : 1; ++ unsigned int RG_M7_WF_SX_LOG5G_DIV_EN : 1; ++ unsigned int RG_M7_WF_SX_LOG5G_IQDIV_EN : 1; ++ unsigned int RG_M7_WF_SX_LOG5G_RXLO_EN : 1; ++ unsigned int RG_M7_WF_SX_LOG5G_DPDLO_EN : 1; ++ unsigned int RG_M7_WF_SX_LOG5G_TXLO_EN : 1; ++ unsigned int RG_M7_WF_SX_LOG2G_MXR_EN : 1; ++ unsigned int RG_M7_WF_SX_LOG2G_DIV_EN : 1; ++ unsigned int RG_M7_WF_SX_LOG2G_IQDIV_EN : 1; ++ unsigned int RG_M7_WF_SX_LOG2G_RXLO_EN : 1; ++ unsigned int RG_M7_WF_SX_LOG2G_DPDLO_EN : 1; ++ unsigned int RG_M7_WF_SX_LOG2G_TXLO_EN : 1; ++ unsigned int rsvd_0 : 12; ++ } b; ++} RG_SX_A49_FIELD_T; ++ ++#define RG_SX_A50 (RF_D_SX_REG_BASE + 0xc8) ++// Bit 6 :0 ro_wf_sx_double_tune U RO default = 'h0 ++// Bit 8 ro_wf_sx_double_tune_ready U RO default = 'h0 ++typedef union RG_SX_A50_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RO_WF_SX_DOUBLE_TUNE : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int RO_WF_SX_DOUBLE_TUNE_READY : 1; ++ unsigned int rsvd_1 : 23; ++ } b; ++} RG_SX_A50_FIELD_T; ++ ++#endif ++ +diff --git a/drivers/net/wireless/w1/common/rf_d_top_reg.h b/drivers/net/wireless/w1/common/rf_d_top_reg.h +new file mode 100644 +index 0000000000000000000000000000000000000000..c0419d43d9be52645268c406929dda8eeb6983c1 +--- /dev/null ++++ b/drivers/net/wireless/w1/common/rf_d_top_reg.h +@@ -0,0 +1,790 @@ ++#ifdef RF_D_TOP_REG ++#else ++#define RF_D_TOP_REG ++ ++ ++#define RF_D_TOP_REG_BASE (0x0) ++ ++#define RG_TOP_A0 (RF_D_TOP_REG_BASE + 0x0) ++// Bit 31 :0 rg_wf_rx_dig_rsv0 U RW default = 'hffff ++typedef union RG_TOP_A0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_DIG_RSV0 : 32; ++ } b; ++} RG_TOP_A0_FIELD_T; ++ ++#define RG_TOP_A1 (RF_D_TOP_REG_BASE + 0x4) ++// Bit 31 :0 rg_wf_rx_dig_rsv1 U RW default = 'hffff ++typedef union RG_TOP_A1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_RX_DIG_RSV1 : 32; ++ } b; ++} RG_TOP_A1_FIELD_T; ++ ++#define RG_TOP_A2 (RF_D_TOP_REG_BASE + 0x8) ++// Bit 2 :0 rg_wf_mode_man U RW default = 'h0 ++// Bit 4 rg_wf_mode_man_mode U RW default = 'h0 ++// Bit 7 :6 rg_wf_sleep_mode U RW default = 'h0 ++// Bit 9 :8 rg_wf5g_sx_mode U RW default = 'h1 ++// Bit 11 :10 rg_wf5g_tx_mode U RW default = 'h2 ++// Bit 13 :12 rg_wf5g_rx_mode U RW default = 'h3 ++// Bit 15 :14 rg_wf5g_dpd_mode U RW default = 'h0 ++// Bit 17 :16 rg_wf2g_sx_mode U RW default = 'h1 ++// Bit 19 :18 rg_wf2g_tx_mode U RW default = 'h2 ++// Bit 21 :20 rg_wf2g_rx_mode U RW default = 'h3 ++// Bit 24 rg_wf_rf_mode U RW default = 'h0 ++// Bit 26 rg_wf_agc_lock_man U RW default = 'h0 ++// Bit 28 rg_wf_agc_lock_man_mode U RW default = 'h0 ++// Bit 30 :29 rg_wf_trswitch_edge_mask U RW default = 'h0 ++typedef union RG_TOP_A2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_MODE_MAN : 3; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF_MODE_MAN_MODE : 1; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF_SLEEP_MODE : 2; ++ unsigned int RG_WF5G_SX_MODE : 2; ++ unsigned int RG_WF5G_TX_MODE : 2; ++ unsigned int RG_WF5G_RX_MODE : 2; ++ unsigned int RG_WF5G_DPD_MODE : 2; ++ unsigned int RG_WF2G_SX_MODE : 2; ++ unsigned int RG_WF2G_TX_MODE : 2; ++ unsigned int RG_WF2G_RX_MODE : 2; ++ unsigned int rsvd_2 : 2; ++ unsigned int RG_WF_RF_MODE : 1; ++ unsigned int rsvd_3 : 1; ++ unsigned int RG_WF_AGC_LOCK_MAN : 1; ++ unsigned int rsvd_4 : 1; ++ unsigned int RG_WF_AGC_LOCK_MAN_MODE : 1; ++ unsigned int RG_WF_TRSWITCH_EDGE_MASK : 2; ++ unsigned int rsvd_5 : 1; ++ } b; ++} RG_TOP_A2_FIELD_T; ++ ++#define RG_TOP_A3 (RF_D_TOP_REG_BASE + 0xc) ++// Bit 0 rg_wf_trx_hf_ldo_fc_sel U RW default = 'h0 ++// Bit 1 rg_wf_trx_hf_ldo_fc_en_man_mode U RW default = 'h0 ++// Bit 2 rg_wf_trx_hf_ldo_fc_en_man U RW default = 'h0 ++// Bit 7 :3 rg_wf_trx_hf_ldo_vsel U RW default = 'h10 ++// Bit 8 rg_wf_trx_hf_ldo_rc_ctrl U RW default = 'h1 ++// Bit 9 rg_wf_trx_lf_ldo_fc_sel U RW default = 'h0 ++// Bit 10 rg_wf_trx_lf_ldo_fc_en_man_mode U RW default = 'h0 ++// Bit 11 rg_wf_trx_lf_ldo_fc_en_man U RW default = 'h0 ++// Bit 16 :12 rg_wf_trx_lf_ldo_vsel U RW default = 'h10 ++// Bit 17 rg_wf_trx_lf_ldo_rc_ctrl U RW default = 'h1 ++// Bit 20 :18 rg_wf_top_dc_test_sel U RW default = 'h0 ++// Bit 23 :21 rg_wf_top_ac_test_sel U RW default = 'h0 ++// Bit 24 rg_wf_top_dc_test_en U RW default = 'h0 ++// Bit 25 rg_wf_top_ac_test_en U RW default = 'h0 ++// Bit 26 rg_wf_top_tx_test_en U RW default = 'h0 ++// Bit 27 rg_wf_top_rx_test_en U RW default = 'h0 ++// Bit 28 rg_wf_top_adc_test_en U RW default = 'h0 ++// Bit 29 rg_wf_top_rcal_test_en U RW default = 'h0 ++// Bit 30 rg_wf_top_xosc_test_en U RW default = 'h0 ++// Bit 31 rg_wf_top_bbpll_test_en U RW default = 'h0 ++typedef union RG_TOP_A3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_TRX_HF_LDO_FC_SEL : 1; ++ unsigned int RG_WF_TRX_HF_LDO_FC_EN_MAN_MODE : 1; ++ unsigned int RG_WF_TRX_HF_LDO_FC_EN_MAN : 1; ++ unsigned int RG_WF_TRX_HF_LDO_VSEL : 5; ++ unsigned int RG_WF_TRX_HF_LDO_RC_CTRL : 1; ++ unsigned int RG_WF_TRX_LF_LDO_FC_SEL : 1; ++ unsigned int RG_WF_TRX_LF_LDO_FC_EN_MAN_MODE : 1; ++ unsigned int RG_WF_TRX_LF_LDO_FC_EN_MAN : 1; ++ unsigned int RG_WF_TRX_LF_LDO_VSEL : 5; ++ unsigned int RG_WF_TRX_LF_LDO_RC_CTRL : 1; ++ unsigned int RG_WF_TOP_DC_TEST_SEL : 3; ++ unsigned int RG_WF_TOP_AC_TEST_SEL : 3; ++ unsigned int RG_WF_TOP_DC_TEST_EN : 1; ++ unsigned int RG_WF_TOP_AC_TEST_EN : 1; ++ unsigned int RG_WF_TOP_TX_TEST_EN : 1; ++ unsigned int RG_WF_TOP_RX_TEST_EN : 1; ++ unsigned int RG_WF_TOP_ADC_TEST_EN : 1; ++ unsigned int RG_WF_TOP_RCAL_TEST_EN : 1; ++ unsigned int RG_WF_TOP_XOSC_TEST_EN : 1; ++ unsigned int RG_WF_TOP_BBPLL_TEST_EN : 1; ++ } b; ++} RG_TOP_A3_FIELD_T; ++ ++#define RG_TOP_A4 (RF_D_TOP_REG_BASE + 0x10) ++// Bit 15 :0 rg_wf_top_reserved0 U RW default = 'h0 ++// Bit 31 :16 rg_wf_top_reserved1 U RW default = 'hffff ++typedef union RG_TOP_A4_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_TOP_RESERVED0 : 16; ++ unsigned int RG_WF_TOP_RESERVED1 : 16; ++ } b; ++} RG_TOP_A4_FIELD_T; ++ ++#define RG_TOP_A5 (RF_D_TOP_REG_BASE + 0x14) ++// Bit 0 rg_m0_wf_trx_hf_ldo_en U RW default = 'h0 ++// Bit 1 rg_m0_wf_trx_hf_ldo_tx1_en U RW default = 'h0 ++// Bit 2 rg_m0_wf_trx_hf_ldo_tx2_en U RW default = 'h0 ++// Bit 3 rg_m0_wf_trx_hf_ldo_rxb_en U RW default = 'h0 ++// Bit 4 rg_m0_wf_trx_hf_ldo_rx1_en U RW default = 'h0 ++// Bit 5 rg_m0_wf_trx_hf_ldo_rx2_en U RW default = 'h0 ++// Bit 6 rg_m0_wf_trx_hf_ldo_lo_en U RW default = 'h0 ++// Bit 7 rg_m0_wf_trx_lf_ldo_en U RW default = 'h0 ++// Bit 8 rg_m0_wf_trx_lf_ldo_tx_en U RW default = 'h0 ++// Bit 9 rg_m0_wf_trx_lf_ldo_rx_en U RW default = 'h0 ++typedef union RG_TOP_A5_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M0_WF_TRX_HF_LDO_EN : 1; ++ unsigned int RG_M0_WF_TRX_HF_LDO_TX1_EN : 1; ++ unsigned int RG_M0_WF_TRX_HF_LDO_TX2_EN : 1; ++ unsigned int RG_M0_WF_TRX_HF_LDO_RXB_EN : 1; ++ unsigned int RG_M0_WF_TRX_HF_LDO_RX1_EN : 1; ++ unsigned int RG_M0_WF_TRX_HF_LDO_RX2_EN : 1; ++ unsigned int RG_M0_WF_TRX_HF_LDO_LO_EN : 1; ++ unsigned int RG_M0_WF_TRX_LF_LDO_EN : 1; ++ unsigned int RG_M0_WF_TRX_LF_LDO_TX_EN : 1; ++ unsigned int RG_M0_WF_TRX_LF_LDO_RX_EN : 1; ++ unsigned int rsvd_0 : 22; ++ } b; ++} RG_TOP_A5_FIELD_T; ++ ++#define RG_TOP_A6 (RF_D_TOP_REG_BASE + 0x18) ++// Bit 0 rg_m1_wf_trx_hf_ldo_en U RW default = 'h1 ++// Bit 1 rg_m1_wf_trx_hf_ldo_tx1_en U RW default = 'h0 ++// Bit 2 rg_m1_wf_trx_hf_ldo_tx2_en U RW default = 'h0 ++// Bit 3 rg_m1_wf_trx_hf_ldo_rxb_en U RW default = 'h0 ++// Bit 4 rg_m1_wf_trx_hf_ldo_rx1_en U RW default = 'h0 ++// Bit 5 rg_m1_wf_trx_hf_ldo_rx2_en U RW default = 'h0 ++// Bit 6 rg_m1_wf_trx_hf_ldo_lo_en U RW default = 'h1 ++// Bit 7 rg_m1_wf_trx_lf_ldo_en U RW default = 'h0 ++// Bit 8 rg_m1_wf_trx_lf_ldo_tx_en U RW default = 'h0 ++// Bit 9 rg_m1_wf_trx_lf_ldo_rx_en U RW default = 'h0 ++typedef union RG_TOP_A6_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M1_WF_TRX_HF_LDO_EN : 1; ++ unsigned int RG_M1_WF_TRX_HF_LDO_TX1_EN : 1; ++ unsigned int RG_M1_WF_TRX_HF_LDO_TX2_EN : 1; ++ unsigned int RG_M1_WF_TRX_HF_LDO_RXB_EN : 1; ++ unsigned int RG_M1_WF_TRX_HF_LDO_RX1_EN : 1; ++ unsigned int RG_M1_WF_TRX_HF_LDO_RX2_EN : 1; ++ unsigned int RG_M1_WF_TRX_HF_LDO_LO_EN : 1; ++ unsigned int RG_M1_WF_TRX_LF_LDO_EN : 1; ++ unsigned int RG_M1_WF_TRX_LF_LDO_TX_EN : 1; ++ unsigned int RG_M1_WF_TRX_LF_LDO_RX_EN : 1; ++ unsigned int rsvd_0 : 22; ++ } b; ++} RG_TOP_A6_FIELD_T; ++ ++#define RG_TOP_A7 (RF_D_TOP_REG_BASE + 0x1c) ++// Bit 0 rg_m2_wf_trx_hf_ldo_en U RW default = 'h1 ++// Bit 1 rg_m2_wf_trx_hf_ldo_tx1_en U RW default = 'h1 ++// Bit 2 rg_m2_wf_trx_hf_ldo_tx2_en U RW default = 'h1 ++// Bit 3 rg_m2_wf_trx_hf_ldo_rxb_en U RW default = 'h0 ++// Bit 4 rg_m2_wf_trx_hf_ldo_rx1_en U RW default = 'h0 ++// Bit 5 rg_m2_wf_trx_hf_ldo_rx2_en U RW default = 'h0 ++// Bit 6 rg_m2_wf_trx_hf_ldo_lo_en U RW default = 'h1 ++// Bit 7 rg_m2_wf_trx_lf_ldo_en U RW default = 'h1 ++// Bit 8 rg_m2_wf_trx_lf_ldo_tx_en U RW default = 'h1 ++// Bit 9 rg_m2_wf_trx_lf_ldo_rx_en U RW default = 'h0 ++typedef union RG_TOP_A7_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M2_WF_TRX_HF_LDO_EN : 1; ++ unsigned int RG_M2_WF_TRX_HF_LDO_TX1_EN : 1; ++ unsigned int RG_M2_WF_TRX_HF_LDO_TX2_EN : 1; ++ unsigned int RG_M2_WF_TRX_HF_LDO_RXB_EN : 1; ++ unsigned int RG_M2_WF_TRX_HF_LDO_RX1_EN : 1; ++ unsigned int RG_M2_WF_TRX_HF_LDO_RX2_EN : 1; ++ unsigned int RG_M2_WF_TRX_HF_LDO_LO_EN : 1; ++ unsigned int RG_M2_WF_TRX_LF_LDO_EN : 1; ++ unsigned int RG_M2_WF_TRX_LF_LDO_TX_EN : 1; ++ unsigned int RG_M2_WF_TRX_LF_LDO_RX_EN : 1; ++ unsigned int rsvd_0 : 22; ++ } b; ++} RG_TOP_A7_FIELD_T; ++ ++#define RG_TOP_A8 (RF_D_TOP_REG_BASE + 0x20) ++// Bit 0 rg_m3_wf_trx_hf_ldo_en U RW default = 'h1 ++// Bit 1 rg_m3_wf_trx_hf_ldo_tx1_en U RW default = 'h0 ++// Bit 2 rg_m3_wf_trx_hf_ldo_tx2_en U RW default = 'h0 ++// Bit 3 rg_m3_wf_trx_hf_ldo_rxb_en U RW default = 'h1 ++// Bit 4 rg_m3_wf_trx_hf_ldo_rx1_en U RW default = 'h1 ++// Bit 5 rg_m3_wf_trx_hf_ldo_rx2_en U RW default = 'h1 ++// Bit 6 rg_m3_wf_trx_hf_ldo_lo_en U RW default = 'h1 ++// Bit 7 rg_m3_wf_trx_lf_ldo_en U RW default = 'h1 ++// Bit 8 rg_m3_wf_trx_lf_ldo_tx_en U RW default = 'h0 ++// Bit 9 rg_m3_wf_trx_lf_ldo_rx_en U RW default = 'h1 ++typedef union RG_TOP_A8_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M3_WF_TRX_HF_LDO_EN : 1; ++ unsigned int RG_M3_WF_TRX_HF_LDO_TX1_EN : 1; ++ unsigned int RG_M3_WF_TRX_HF_LDO_TX2_EN : 1; ++ unsigned int RG_M3_WF_TRX_HF_LDO_RXB_EN : 1; ++ unsigned int RG_M3_WF_TRX_HF_LDO_RX1_EN : 1; ++ unsigned int RG_M3_WF_TRX_HF_LDO_RX2_EN : 1; ++ unsigned int RG_M3_WF_TRX_HF_LDO_LO_EN : 1; ++ unsigned int RG_M3_WF_TRX_LF_LDO_EN : 1; ++ unsigned int RG_M3_WF_TRX_LF_LDO_TX_EN : 1; ++ unsigned int RG_M3_WF_TRX_LF_LDO_RX_EN : 1; ++ unsigned int rsvd_0 : 22; ++ } b; ++} RG_TOP_A8_FIELD_T; ++ ++#define RG_TOP_A9 (RF_D_TOP_REG_BASE + 0x40) ++// Bit 0 rg_wf_adda_ldo_lf_rc_ctrl U RW default = 'h0 ++// Bit 1 rg_wf_adda_ldo_rc_modelsel U RW default = 'h0 ++// Bit 6 :2 rg_wf_adda_ldo_vref_adj U RW default = 'h0 ++// Bit 7 rg_wf_adda_ldo_load_en U RW default = 'h0 ++// Bit 23 :8 rg_wf_adda_rsv U RW default = 'h0 ++// Bit 24 rg_wf_dac_bit9_inv U RW default = 'h0 ++// Bit 30 :28 rg_wf_dac_clk_delay_i U RW default = 'h1 ++typedef union RG_TOP_A9_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_wf_adda_ldo_lf_rc_ctrl : 1; ++ unsigned int rg_wf_adda_ldo_rc_modelsel : 1; ++ unsigned int rg_wf_adda_ldo_vref_adj : 5; ++ unsigned int rg_wf_adda_ldo_load_en : 1; ++ unsigned int rg_wf_adda_rsv : 16; ++ unsigned int rg_wf_dac_bit9_inv : 1; ++ unsigned int rsvd_0 : 3; ++ unsigned int rg_wf_dac_clk_delay_i : 3; ++ unsigned int rsvd_1 : 1; ++ } b; ++} RG_TOP_A9_FIELD_T; ++ ++#define RG_TOP_A11 (RF_D_TOP_REG_BASE + 0x48) ++// Bit 2 :0 rg_wf_dac_clk_delay_q U RW default = 'h1 ++// Bit 6 :3 rg_wf_dac_dcoc_i U RW default = 'h0 ++// Bit 10 :7 rg_wf_dac_dcoc_q U RW default = 'h0 ++// Bit 11 rg_wf_dac_dem_en U RW default = 'h0 ++// Bit 12 rg_wf_dac_driver_adj U RW default = 'h0 ++// Bit 16 :13 rg_wf_dac_op_drive U RW default = 'hf ++// Bit 18 :17 rg_wf_dac_op_ibias U RW default = 'h3 ++// Bit 22 :19 rg_wf_dac_ovcm U RW default = 'h0 ++// Bit 23 rg_wf_dac_fs_sel U RW default = 'h1 ++// Bit 28 :24 rg_wf_dac_rc_adj_i U RW default = 'h8 ++typedef union RG_TOP_A11_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_wf_dac_clk_delay_q : 3; ++ unsigned int rg_wf_dac_dcoc_i : 4; ++ unsigned int rg_wf_dac_dcoc_q : 4; ++ unsigned int rg_wf_dac_dem_en : 1; ++ unsigned int rg_wf_dac_driver_adj : 1; ++ unsigned int rg_wf_dac_op_drive : 4; ++ unsigned int rg_wf_dac_op_ibias : 2; ++ unsigned int rg_wf_dac_ovcm : 4; ++ unsigned int rg_wf_dac_fs_sel : 1; ++ unsigned int rg_wf_dac_rc_adj_i : 5; ++ unsigned int rsvd_0 : 3; ++ } b; ++} RG_TOP_A11_FIELD_T; ++ ++#define RG_TOP_A12 (RF_D_TOP_REG_BASE + 0x4c) ++// Bit 4 :0 rg_wf_dac_rc_adj_q U RW default = 'h8 ++// Bit 12 :5 rg_wf_dac_rsv U RW default = 'h86 ++// Bit 15 :13 rg_wf_dac_vimc_i U RW default = 'h0 ++// Bit 18 :16 rg_wf_dac_vimc_q U RW default = 'h0 ++// Bit 20 :19 rg_wf_dac_pole_sel U RW default = 'h0 ++// Bit 21 rg_wf_dac_tia_mux_sel_i U RW default = 'h0 ++// Bit 22 rg_wf_dac_tia_mux_sel_q U RW default = 'h0 ++// Bit 24 :23 rg_wf_radc_bs_sel U RW default = 'h1 ++// Bit 25 rg_wf_radc_c_adj U RW default = 'h0 ++// Bit 28 :26 rg_wf_radc_clk_delay_adj U RW default = 'h1 ++// Bit 29 rg_wf_radc_ref_adj U RW default = 'h0 ++typedef union RG_TOP_A12_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_wf_dac_rc_adj_q : 5; ++ unsigned int rg_wf_dac_rsv : 8; ++ unsigned int rg_wf_dac_vimc_i : 3; ++ unsigned int rg_wf_dac_vimc_q : 3; ++ unsigned int rg_wf_dac_pole_sel : 2; ++ unsigned int rg_wf_dac_tia_mux_sel_i : 1; ++ unsigned int rg_wf_dac_tia_mux_sel_q : 1; ++ unsigned int rg_wf_radc_bs_sel : 2; ++ unsigned int rg_wf_radc_c_adj : 1; ++ unsigned int rg_wf_radc_clk_delay_adj : 3; ++ unsigned int rg_wf_radc_ref_adj : 1; ++ unsigned int rsvd_0 : 2; ++ } b; ++} RG_TOP_A12_FIELD_T; ++ ++#define RG_TOP_A13 (RF_D_TOP_REG_BASE + 0x50) ++// Bit 7 :0 rg_wf_radc_resv U RW default = 'h3 ++// Bit 8 rg_wf_radc_skip_sel U RW default = 'h0 ++// Bit 10 :9 rg_wf_wadc_bs_sel U RW default = 'h2 ++// Bit 11 rg_wf_wadc_ch1_latch U RW default = 'h0 ++// Bit 16 :12 rg_wf_wadc_ch1_os_corr_i_man U RW default = 'h0 ++// Bit 21 :17 rg_wf_wadc_ch1_os_corr_q_man U RW default = 'h0 ++// Bit 22 rg_wf_wadc_ch2_latch U RW default = 'h0 ++// Bit 27 :23 rg_wf_wadc_ch2_os_corr_i_man U RW default = 'h0 ++// Bit 28 rg_wf_wadc_ch_os_corr_man_sel U RW default = 'h1 ++// Bit 29 rg_wf_wadc_force_ch_man_sel U RW default = 'h1 ++typedef union RG_TOP_A13_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_wf_radc_resv : 8; ++ unsigned int rg_wf_radc_skip_sel : 1; ++ unsigned int rg_wf_wadc_bs_sel : 2; ++ unsigned int rg_wf_wadc_ch1_latch : 1; ++ unsigned int rg_wf_wadc_ch1_os_corr_i_man : 5; ++ unsigned int rg_wf_wadc_ch1_os_corr_q_man : 5; ++ unsigned int rg_wf_wadc_ch2_latch : 1; ++ unsigned int rg_wf_wadc_ch2_os_corr_i_man : 5; ++ unsigned int rg_wf_wadc_ch_os_corr_man_sel : 1; ++ unsigned int rg_wf_wadc_force_ch_man_sel : 1; ++ unsigned int rsvd_0 : 2; ++ } b; ++} RG_TOP_A13_FIELD_T; ++ ++#define RG_TOP_A14 (RF_D_TOP_REG_BASE + 0x54) ++// Bit 4 :0 rg_wf_wadc_ch2_os_corr_q_man U RW default = 'h0 ++// Bit 5 rg_wf_wadc_clk_phase U RW default = 'h0 ++// Bit 7 :6 rg_wf_wadc_delay_adj U RW default = 'h0 ++// Bit 8 rg_wf_wadc_div2 U RW default = 'h1 ++// Bit 13 :9 rg_wf_wadc_divn U RW default = 'h0 ++// Bit 14 rg_wf_wadc_fs_sel U RW default = 'h0 ++// Bit 15 rg_wf_wadc_force_ch1_man U RW default = 'h1 ++// Bit 16 rg_wf_wadc_force_ch2_man U RW default = 'h0 ++// Bit 17 rg_wf_wadc_oscorr_en U RW default = 'h0 ++// Bit 18 rg_wf_wadc_clkout_phase U RW default = 'h0 ++// Bit 19 rg_wf_wadc_skip_sel U RW default = 'h0 ++// Bit 21 :20 rg_wf_wadc_waittime U RW default = 'h0 ++// Bit 23 :22 rg_wf_wadc_calctime U RW default = 'h0 ++// Bit 24 rg_wf_adda_ldo_fc U RW default = 'h0 ++typedef union RG_TOP_A14_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_wf_wadc_ch2_os_corr_q_man : 5; ++ unsigned int rg_wf_wadc_clk_phase : 1; ++ unsigned int rg_wf_wadc_delay_adj : 2; ++ unsigned int rg_wf_wadc_div2 : 1; ++ unsigned int rg_wf_wadc_divn : 5; ++ unsigned int rg_wf_wadc_fs_sel : 1; ++ unsigned int rg_wf_wadc_force_ch1_man : 1; ++ unsigned int rg_wf_wadc_force_ch2_man : 1; ++ unsigned int rg_wf_wadc_oscorr_en : 1; ++ unsigned int rg_wf_wadc_clkout_phase : 1; ++ unsigned int rg_wf_wadc_skip_sel : 1; ++ unsigned int rg_wf_wadc_waittime : 2; ++ unsigned int rg_wf_wadc_calctime : 2; ++ unsigned int rg_wf_adda_ldo_fc : 1; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_TOP_A14_FIELD_T; ++ ++#define RG_TOP_A15 (RF_D_TOP_REG_BASE + 0x58) ++// Bit 0 rg_wf_adda_man_mode U RW default = 'h1 ++// Bit 6 :4 rg_wf_dac_ampctrl_man U RW default = 'h4 ++// Bit 12 rg_wf_tx_tia_ibias_en_h U RW default = 'h1 ++// Bit 18 :16 rg_wf_tx_ibias_pata U RW default = 'h0 ++// Bit 22 :20 rg_wf_tx_ibias_zt U RW default = 'h0 ++typedef union RG_TOP_A15_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_wf_adda_man_mode : 1; ++ unsigned int rsvd_0 : 3; ++ unsigned int rg_wf_dac_ampctrl_man : 3; ++ unsigned int rsvd_1 : 5; ++ unsigned int rg_wf_tx_tia_ibias_en_h : 1; ++ unsigned int rsvd_2 : 3; ++ unsigned int rg_wf_tx_ibias_pata : 3; ++ unsigned int rsvd_3 : 1; ++ unsigned int rg_wf_tx_ibias_zt : 3; ++ unsigned int rsvd_4 : 9; ++ } b; ++} RG_TOP_A15_FIELD_T; ++ ++#define RG_TOP_A16 (RF_D_TOP_REG_BASE + 0x5c) ++// Bit 4 :0 ro_wf_wadc_ch1_os_corr_i U RO default = 'h0 ++// Bit 9 :5 ro_wf_wadc_ch1_os_corr_q U RO default = 'h0 ++// Bit 14 :10 ro_wf_wadc_ch2_os_corr_i U RO default = 'h0 ++// Bit 19 :15 ro_wf_wadc_ch2_os_corr_q U RO default = 'h0 ++typedef union RG_TOP_A16_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_wf_wadc_ch1_os_corr_i : 5; ++ unsigned int ro_wf_wadc_ch1_os_corr_q : 5; ++ unsigned int ro_wf_wadc_ch2_os_corr_i : 5; ++ unsigned int ro_wf_wadc_ch2_os_corr_q : 5; ++ unsigned int rsvd_0 : 12; ++ } b; ++} RG_TOP_A16_FIELD_T; ++ ++#define RG_TOP_A17 (RF_D_TOP_REG_BASE + 0x60) ++// Bit 0 rg_m0_wf_adda_ldo_en U RW default = 'h0 ++// Bit 1 rg_m0_wf_dac_enable U RW default = 'h0 ++// Bit 2 rg_m0_wf_radc_en U RW default = 'h0 ++// Bit 3 rg_m0_wf_wadc_enable_i U RW default = 'h0 ++// Bit 4 rg_m0_wf_wadc_enable_q U RW default = 'h0 ++typedef union RG_TOP_A17_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_m0_wf_adda_ldo_en : 1; ++ unsigned int rg_m0_wf_dac_enable : 1; ++ unsigned int rg_m0_wf_radc_en : 1; ++ unsigned int rg_m0_wf_wadc_enable_i : 1; ++ unsigned int rg_m0_wf_wadc_enable_q : 1; ++ unsigned int rsvd_0 : 27; ++ } b; ++} RG_TOP_A17_FIELD_T; ++ ++#define RG_TOP_A18 (RF_D_TOP_REG_BASE + 0x64) ++// Bit 0 rg_m1_wf_adda_ldo_en U RW default = 'h0 ++// Bit 1 rg_m1_wf_dac_enable U RW default = 'h0 ++// Bit 2 rg_m1_wf_radc_en U RW default = 'h0 ++// Bit 3 rg_m1_wf_wadc_enable_i U RW default = 'h0 ++// Bit 4 rg_m1_wf_wadc_enable_q U RW default = 'h0 ++typedef union RG_TOP_A18_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_m1_wf_adda_ldo_en : 1; ++ unsigned int rg_m1_wf_dac_enable : 1; ++ unsigned int rg_m1_wf_radc_en : 1; ++ unsigned int rg_m1_wf_wadc_enable_i : 1; ++ unsigned int rg_m1_wf_wadc_enable_q : 1; ++ unsigned int rsvd_0 : 27; ++ } b; ++} RG_TOP_A18_FIELD_T; ++ ++#define RG_TOP_A19 (RF_D_TOP_REG_BASE + 0x68) ++// Bit 0 rg_m2_wf_adda_ldo_en U RW default = 'h1 ++// Bit 1 rg_m2_wf_dac_enable U RW default = 'h1 ++// Bit 2 rg_m2_wf_radc_en U RW default = 'h0 ++// Bit 3 rg_m2_wf_wadc_enable_i U RW default = 'h0 ++// Bit 4 rg_m2_wf_wadc_enable_q U RW default = 'h0 ++typedef union RG_TOP_A19_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_m2_wf_adda_ldo_en : 1; ++ unsigned int rg_m2_wf_dac_enable : 1; ++ unsigned int rg_m2_wf_radc_en : 1; ++ unsigned int rg_m2_wf_wadc_enable_i : 1; ++ unsigned int rg_m2_wf_wadc_enable_q : 1; ++ unsigned int rsvd_0 : 27; ++ } b; ++} RG_TOP_A19_FIELD_T; ++ ++#define RG_TOP_A20 (RF_D_TOP_REG_BASE + 0x6c) ++// Bit 0 rg_m3_wf_adda_ldo_en U RW default = 'h1 ++// Bit 1 rg_m3_wf_dac_enable U RW default = 'h0 ++// Bit 2 rg_m3_wf_radc_en U RW default = 'h1 ++// Bit 3 rg_m3_wf_wadc_enable_i U RW default = 'h1 ++// Bit 4 rg_m3_wf_wadc_enable_q U RW default = 'h1 ++typedef union RG_TOP_A20_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_m3_wf_adda_ldo_en : 1; ++ unsigned int rg_m3_wf_dac_enable : 1; ++ unsigned int rg_m3_wf_radc_en : 1; ++ unsigned int rg_m3_wf_wadc_enable_i : 1; ++ unsigned int rg_m3_wf_wadc_enable_q : 1; ++ unsigned int rsvd_0 : 27; ++ } b; ++} RG_TOP_A20_FIELD_T; ++ ++#define RG_TOP_A21 (RF_D_TOP_REG_BASE + 0x70) ++// Bit 0 rg_m4_wf_adda_ldo_en U RW default = 'h1 ++// Bit 1 rg_m4_wf_dac_enable U RW default = 'h1 ++// Bit 2 rg_m4_wf_radc_en U RW default = 'h0 ++// Bit 3 rg_m4_wf_wadc_enable_i U RW default = 'h1 ++// Bit 4 rg_m4_wf_wadc_enable_q U RW default = 'h1 ++typedef union RG_TOP_A21_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_m4_wf_adda_ldo_en : 1; ++ unsigned int rg_m4_wf_dac_enable : 1; ++ unsigned int rg_m4_wf_radc_en : 1; ++ unsigned int rg_m4_wf_wadc_enable_i : 1; ++ unsigned int rg_m4_wf_wadc_enable_q : 1; ++ unsigned int rsvd_0 : 27; ++ } b; ++} RG_TOP_A21_FIELD_T; ++ ++#define RG_TOP_A22 (RF_D_TOP_REG_BASE + 0x74) ++// Bit 0 rg_m5_wf_adda_ldo_en U RW default = 'h0 ++// Bit 1 rg_m5_wf_dac_enable U RW default = 'h0 ++// Bit 2 rg_m5_wf_radc_en U RW default = 'h0 ++// Bit 3 rg_m5_wf_wadc_enable_i U RW default = 'h0 ++// Bit 4 rg_m5_wf_wadc_enable_q U RW default = 'h0 ++typedef union RG_TOP_A22_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_m5_wf_adda_ldo_en : 1; ++ unsigned int rg_m5_wf_dac_enable : 1; ++ unsigned int rg_m5_wf_radc_en : 1; ++ unsigned int rg_m5_wf_wadc_enable_i : 1; ++ unsigned int rg_m5_wf_wadc_enable_q : 1; ++ unsigned int rsvd_0 : 27; ++ } b; ++} RG_TOP_A22_FIELD_T; ++ ++#define RG_TOP_A23 (RF_D_TOP_REG_BASE + 0x78) ++// Bit 0 rg_m6_wf_adda_ldo_en U RW default = 'h1 ++// Bit 1 rg_m6_wf_dac_enable U RW default = 'h1 ++// Bit 2 rg_m6_wf_radc_en U RW default = 'h0 ++// Bit 3 rg_m6_wf_wadc_enable_i U RW default = 'h0 ++// Bit 4 rg_m6_wf_wadc_enable_q U RW default = 'h0 ++typedef union RG_TOP_A23_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_m6_wf_adda_ldo_en : 1; ++ unsigned int rg_m6_wf_dac_enable : 1; ++ unsigned int rg_m6_wf_radc_en : 1; ++ unsigned int rg_m6_wf_wadc_enable_i : 1; ++ unsigned int rg_m6_wf_wadc_enable_q : 1; ++ unsigned int rsvd_0 : 27; ++ } b; ++} RG_TOP_A23_FIELD_T; ++ ++#define RG_TOP_A24 (RF_D_TOP_REG_BASE + 0x7c) ++// Bit 0 rg_m7_wf_adda_ldo_en U RW default = 'h1 ++// Bit 1 rg_m7_wf_dac_enable U RW default = 'h0 ++// Bit 2 rg_m7_wf_radc_en U RW default = 'h1 ++// Bit 3 rg_m7_wf_wadc_enable_i U RW default = 'h1 ++// Bit 4 rg_m7_wf_wadc_enable_q U RW default = 'h1 ++typedef union RG_TOP_A24_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rg_m7_wf_adda_ldo_en : 1; ++ unsigned int rg_m7_wf_dac_enable : 1; ++ unsigned int rg_m7_wf_radc_en : 1; ++ unsigned int rg_m7_wf_wadc_enable_i : 1; ++ unsigned int rg_m7_wf_wadc_enable_q : 1; ++ unsigned int rsvd_0 : 27; ++ } b; ++} RG_TOP_A24_FIELD_T; ++ ++#define RG_TOP_A27 (RF_D_TOP_REG_BASE + 0x88) ++// Bit 0 rg_m4_wf_trx_hf_ldo_en U RW default = 'h1 ++// Bit 1 rg_m4_wf_trx_hf_ldo_tx1_en U RW default = 'h1 ++// Bit 2 rg_m4_wf_trx_hf_ldo_tx2_en U RW default = 'h1 ++// Bit 3 rg_m4_wf_trx_hf_ldo_rxb_en U RW default = 'h1 ++// Bit 4 rg_m4_wf_trx_hf_ldo_rx1_en U RW default = 'h1 ++// Bit 5 rg_m4_wf_trx_hf_ldo_rx2_en U RW default = 'h1 ++// Bit 6 rg_m4_wf_trx_hf_ldo_lo_en U RW default = 'h1 ++// Bit 7 rg_m4_wf_trx_lf_ldo_en U RW default = 'h1 ++// Bit 8 rg_m4_wf_trx_lf_ldo_tx_en U RW default = 'h1 ++// Bit 9 rg_m4_wf_trx_lf_ldo_rx_en U RW default = 'h1 ++typedef union RG_TOP_A27_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M4_WF_TRX_HF_LDO_EN : 1; ++ unsigned int RG_M4_WF_TRX_HF_LDO_TX1_EN : 1; ++ unsigned int RG_M4_WF_TRX_HF_LDO_TX2_EN : 1; ++ unsigned int RG_M4_WF_TRX_HF_LDO_RXB_EN : 1; ++ unsigned int RG_M4_WF_TRX_HF_LDO_RX1_EN : 1; ++ unsigned int RG_M4_WF_TRX_HF_LDO_RX2_EN : 1; ++ unsigned int RG_M4_WF_TRX_HF_LDO_LO_EN : 1; ++ unsigned int RG_M4_WF_TRX_LF_LDO_EN : 1; ++ unsigned int RG_M4_WF_TRX_LF_LDO_TX_EN : 1; ++ unsigned int RG_M4_WF_TRX_LF_LDO_RX_EN : 1; ++ unsigned int rsvd_0 : 22; ++ } b; ++} RG_TOP_A27_FIELD_T; ++ ++#define RG_TOP_A28 (RF_D_TOP_REG_BASE + 0x8c) ++// Bit 0 rg_m5_wf_trx_hf_ldo_en U RW default = 'h1 ++// Bit 1 rg_m5_wf_trx_hf_ldo_tx1_en U RW default = 'h0 ++// Bit 2 rg_m5_wf_trx_hf_ldo_tx2_en U RW default = 'h0 ++// Bit 3 rg_m5_wf_trx_hf_ldo_rxb_en U RW default = 'h0 ++// Bit 4 rg_m5_wf_trx_hf_ldo_rx1_en U RW default = 'h0 ++// Bit 5 rg_m5_wf_trx_hf_ldo_rx2_en U RW default = 'h0 ++// Bit 6 rg_m5_wf_trx_hf_ldo_lo_en U RW default = 'h1 ++// Bit 7 rg_m5_wf_trx_lf_ldo_en U RW default = 'h0 ++// Bit 8 rg_m5_wf_trx_lf_ldo_tx_en U RW default = 'h0 ++// Bit 9 rg_m5_wf_trx_lf_ldo_rx_en U RW default = 'h0 ++typedef union RG_TOP_A28_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M5_WF_TRX_HF_LDO_EN : 1; ++ unsigned int RG_M5_WF_TRX_HF_LDO_TX1_EN : 1; ++ unsigned int RG_M5_WF_TRX_HF_LDO_TX2_EN : 1; ++ unsigned int RG_M5_WF_TRX_HF_LDO_RXB_EN : 1; ++ unsigned int RG_M5_WF_TRX_HF_LDO_RX1_EN : 1; ++ unsigned int RG_M5_WF_TRX_HF_LDO_RX2_EN : 1; ++ unsigned int RG_M5_WF_TRX_HF_LDO_LO_EN : 1; ++ unsigned int RG_M5_WF_TRX_LF_LDO_EN : 1; ++ unsigned int RG_M5_WF_TRX_LF_LDO_TX_EN : 1; ++ unsigned int RG_M5_WF_TRX_LF_LDO_RX_EN : 1; ++ unsigned int rsvd_0 : 22; ++ } b; ++} RG_TOP_A28_FIELD_T; ++ ++#define RG_TOP_A29 (RF_D_TOP_REG_BASE + 0x90) ++// Bit 0 rg_m6_wf_trx_hf_ldo_en U RW default = 'h1 ++// Bit 1 rg_m6_wf_trx_hf_ldo_tx1_en U RW default = 'h1 ++// Bit 2 rg_m6_wf_trx_hf_ldo_tx2_en U RW default = 'h1 ++// Bit 3 rg_m6_wf_trx_hf_ldo_rxb_en U RW default = 'h0 ++// Bit 4 rg_m6_wf_trx_hf_ldo_rx1_en U RW default = 'h0 ++// Bit 5 rg_m6_wf_trx_hf_ldo_rx2_en U RW default = 'h0 ++// Bit 6 rg_m6_wf_trx_hf_ldo_lo_en U RW default = 'h1 ++// Bit 7 rg_m6_wf_trx_lf_ldo_en U RW default = 'h1 ++// Bit 8 rg_m6_wf_trx_lf_ldo_tx_en U RW default = 'h1 ++// Bit 9 rg_m6_wf_trx_lf_ldo_rx_en U RW default = 'h0 ++typedef union RG_TOP_A29_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M6_WF_TRX_HF_LDO_EN : 1; ++ unsigned int RG_M6_WF_TRX_HF_LDO_TX1_EN : 1; ++ unsigned int RG_M6_WF_TRX_HF_LDO_TX2_EN : 1; ++ unsigned int RG_M6_WF_TRX_HF_LDO_RXB_EN : 1; ++ unsigned int RG_M6_WF_TRX_HF_LDO_RX1_EN : 1; ++ unsigned int RG_M6_WF_TRX_HF_LDO_RX2_EN : 1; ++ unsigned int RG_M6_WF_TRX_HF_LDO_LO_EN : 1; ++ unsigned int RG_M6_WF_TRX_LF_LDO_EN : 1; ++ unsigned int RG_M6_WF_TRX_LF_LDO_TX_EN : 1; ++ unsigned int RG_M6_WF_TRX_LF_LDO_RX_EN : 1; ++ unsigned int rsvd_0 : 22; ++ } b; ++} RG_TOP_A29_FIELD_T; ++ ++#define RG_TOP_A30 (RF_D_TOP_REG_BASE + 0x94) ++// Bit 0 rg_m7_wf_trx_hf_ldo_en U RW default = 'h1 ++// Bit 1 rg_m7_wf_trx_hf_ldo_tx1_en U RW default = 'h0 ++// Bit 2 rg_m7_wf_trx_hf_ldo_tx2_en U RW default = 'h0 ++// Bit 3 rg_m7_wf_trx_hf_ldo_rxb_en U RW default = 'h1 ++// Bit 4 rg_m7_wf_trx_hf_ldo_rx1_en U RW default = 'h1 ++// Bit 5 rg_m7_wf_trx_hf_ldo_rx2_en U RW default = 'h1 ++// Bit 6 rg_m7_wf_trx_hf_ldo_lo_en U RW default = 'h1 ++// Bit 7 rg_m7_wf_trx_lf_ldo_en U RW default = 'h1 ++// Bit 8 rg_m7_wf_trx_lf_ldo_tx_en U RW default = 'h0 ++// Bit 9 rg_m7_wf_trx_lf_ldo_rx_en U RW default = 'h1 ++typedef union RG_TOP_A30_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M7_WF_TRX_HF_LDO_EN : 1; ++ unsigned int RG_M7_WF_TRX_HF_LDO_TX1_EN : 1; ++ unsigned int RG_M7_WF_TRX_HF_LDO_TX2_EN : 1; ++ unsigned int RG_M7_WF_TRX_HF_LDO_RXB_EN : 1; ++ unsigned int RG_M7_WF_TRX_HF_LDO_RX1_EN : 1; ++ unsigned int RG_M7_WF_TRX_HF_LDO_RX2_EN : 1; ++ unsigned int RG_M7_WF_TRX_HF_LDO_LO_EN : 1; ++ unsigned int RG_M7_WF_TRX_LF_LDO_EN : 1; ++ unsigned int RG_M7_WF_TRX_LF_LDO_TX_EN : 1; ++ unsigned int RG_M7_WF_TRX_LF_LDO_RX_EN : 1; ++ unsigned int rsvd_0 : 22; ++ } b; ++} RG_TOP_A30_FIELD_T; ++ ++#define RG_TOP_A31 (RF_D_TOP_REG_BASE + 0x98) ++// Bit 31 :0 rg_wf_ad_inv U RW default = 'h0 ++typedef union RG_TOP_A31_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_AD_INV : 32; ++ } b; ++} RG_TOP_A31_FIELD_T; ++ ++#define RG_TOP_A32 (RF_D_TOP_REG_BASE + 0x9c) ++// Bit 23 :0 ro_wf_top_ad_monitor U RO default = 'h0 ++typedef union RG_TOP_A32_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RO_WF_TOP_AD_MONITOR : 24; ++ unsigned int rsvd_0 : 8; ++ } b; ++} RG_TOP_A32_FIELD_T; ++ ++#define RG_TOP_A33 (RF_D_TOP_REG_BASE + 0xa0) ++// Bit 1 :0 rg_wf_trx_ldo_fc_cnt U RW default = 'h0 ++typedef union RG_TOP_A33_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_TRX_LDO_FC_CNT : 2; ++ unsigned int rsvd_0 : 30; ++ } b; ++} RG_TOP_A33_FIELD_T; ++ ++#define RG_TOP_A34 (RF_D_TOP_REG_BASE + 0xa4) ++// Bit 1 :0 ro_hw_wf_trx_mode U RO default = 'h0 ++// Bit 11 :4 ro_hw_wf_rx_gain U RO default = 'h0 ++// Bit 13 :12 ro_hw_wf_bw U RO default = 'h0 ++// Bit 23 :16 ro_hw_wf_tx_gain U RO default = 'h0 ++// Bit 24 ro_hw_wf_agc_lock U RO default = 'h0 ++typedef union RG_TOP_A34_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RO_HW_WF_TRX_MODE : 2; ++ unsigned int rsvd_0 : 2; ++ unsigned int RO_HW_WF_RX_GAIN : 8; ++ unsigned int RO_HW_WF_BW : 2; ++ unsigned int rsvd_1 : 2; ++ unsigned int RO_HW_WF_TX_GAIN : 8; ++ unsigned int RO_HW_WF_AGC_LOCK : 1; ++ unsigned int rsvd_2 : 7; ++ } b; ++} RG_TOP_A34_FIELD_T; ++ ++#endif ++ +diff --git a/drivers/net/wireless/w1/common/rf_d_tx_reg.h b/drivers/net/wireless/w1/common/rf_d_tx_reg.h +new file mode 100644 +index 0000000000000000000000000000000000000000..bf180978c96379f596621a11d916308053438514 +--- /dev/null ++++ b/drivers/net/wireless/w1/common/rf_d_tx_reg.h +@@ -0,0 +1,430 @@ ++#ifdef RF_D_TX_REG ++#else ++#define RF_D_TX_REG ++ ++ ++#define RF_D_TX_REG_BASE (0x800) ++ ++#define RG_TX_A0 (RF_D_TX_REG_BASE + 0x0) ++// Bit 2 :0 rg_wf5g_tx_pa_vgcg0 U RW default = 'h4 ++// Bit 6 :4 rg_wf5g_tx_mxr_vgcg1 U RW default = 'h3 ++// Bit 10 :8 rg_wf5g_tx_mxr_lo_vb U RW default = 'h3 ++// Bit 14 :12 rg_wf5g_tx_mxr_lobuf_ict U RW default = 'h4 ++typedef union RG_TX_A0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_TX_PA_VGCG0 : 3; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF5G_TX_MXR_VGCG1 : 3; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF5G_TX_MXR_LO_VB : 3; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF5G_TX_MXR_LOBUF_ICT : 3; ++ unsigned int rsvd_3 : 17; ++ } b; ++} RG_TX_A0_FIELD_T; ++ ++#define RG_TX_A1 (RF_D_TX_REG_BASE + 0x4) ++// Bit 2 :0 rg_wf5g_tx_adb_cbank U RW default = 'h7 ++// Bit 6 :3 rg_wf5g_tx_adb_dc U RW default = 'h4 ++// Bit 10 :7 rg_wf5g_tx_adb_vb_ct U RW default = 'h0 ++// Bit 11 rg_wf5g_tx_adb_en U RW default = 'h1 ++// Bit 12 rg_wf5g_tx_adb_ed_en U RW default = 'h1 ++// Bit 16 :13 rg_wf5g_tx_adb_ed_gain U RW default = 'h4 ++// Bit 19 :17 rg_wf5g_tx_adb_icgm U RW default = 'h3 ++// Bit 22 :20 rg_wf5g_tx_adb_iptat U RW default = 'h0 ++// Bit 25 :23 rg_wf5g_tx_ib_adj U RW default = 'h0 ++typedef union RG_TX_A1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_TX_ADB_CBANK : 3; ++ unsigned int RG_WF5G_TX_ADB_DC : 4; ++ unsigned int RG_WF5G_TX_ADB_VB_CT : 4; ++ unsigned int RG_WF5G_TX_ADB_EN : 1; ++ unsigned int RG_WF5G_TX_ADB_ED_EN : 1; ++ unsigned int RG_WF5G_TX_ADB_ED_GAIN : 4; ++ unsigned int RG_WF5G_TX_ADB_ICGM : 3; ++ unsigned int RG_WF5G_TX_ADB_IPTAT : 3; ++ unsigned int RG_WF5G_TX_IB_ADJ : 3; ++ unsigned int rsvd_0 : 6; ++ } b; ++} RG_TX_A1_FIELD_T; ++ ++#define RG_TX_A2 (RF_D_TX_REG_BASE + 0x8) ++// Bit 0 rg_wf5g_tx_tssi_en U RW default = 'h0 ++// Bit 3 :1 rg_wf5g_tx_tssi_attn U RW default = 'h7 ++// Bit 6 :4 rg_wf5g_tx_tssi_lo_vb U RW default = 'h3 ++// Bit 7 rg_wf5g_tx_iqcal_en U RW default = 'h0 ++// Bit 8 rg_wf5g_tx_rxiqcal_en U RW default = 'h0 ++// Bit 16 :9 rg_wf5g_tx_tp_sel U RW default = 'h0 ++// Bit 17 rg_wf5g_tx_tp_en U RW default = 'h0 ++// Bit 20 :18 rg_wf5g_tx_pa_gain_man U RW default = 'h7 ++// Bit 23 :21 rg_wf5g_tx_mxr_gain_man U RW default = 'h7 ++// Bit 24 rg_wf5g_tx_man_mode U RW default = 'h0 ++typedef union RG_TX_A2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_TX_TSSI_EN : 1; ++ unsigned int RG_WF5G_TX_TSSI_ATTN : 3; ++ unsigned int RG_WF5G_TX_TSSI_LO_VB : 3; ++ unsigned int RG_WF5G_TX_IQCAL_EN : 1; ++ unsigned int RG_WF5G_TX_RXIQCAL_EN : 1; ++ unsigned int RG_WF5G_TX_TP_SEL : 8; ++ unsigned int RG_WF5G_TX_TP_EN : 1; ++ unsigned int RG_WF5G_TX_PA_GAIN_MAN : 3; ++ unsigned int RG_WF5G_TX_MXR_GAIN_MAN : 3; ++ unsigned int RG_WF5G_TX_MAN_MODE : 1; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_TX_A2_FIELD_T; ++ ++#define RG_TX_A3 (RF_D_TX_REG_BASE + 0xc) ++// Bit 0 rg_m0_wf5g_tx_pa_en U RW default = 'h0 ++// Bit 1 rg_m0_wf5g_tx_mxr_en U RW default = 'h0 ++// Bit 2 rg_m0_wf5g_tx_ib_en U RW default = 'h0 ++// Bit 3 rg_m1_wf5g_tx_pa_en U RW default = 'h0 ++// Bit 4 rg_m1_wf5g_tx_mxr_en U RW default = 'h0 ++// Bit 5 rg_m1_wf5g_tx_ib_en U RW default = 'h0 ++// Bit 6 rg_m2_wf5g_tx_pa_en U RW default = 'h1 ++// Bit 7 rg_m2_wf5g_tx_mxr_en U RW default = 'h1 ++// Bit 8 rg_m2_wf5g_tx_ib_en U RW default = 'h1 ++// Bit 9 rg_m3_wf5g_tx_pa_en U RW default = 'h0 ++// Bit 10 rg_m3_wf5g_tx_mxr_en U RW default = 'h0 ++// Bit 11 rg_m3_wf5g_tx_ib_en U RW default = 'h0 ++// Bit 31 :16 rg_wf5g_tx_rsv U RW default = 'h0 ++typedef union RG_TX_A3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M0_WF5G_TX_PA_EN : 1; ++ unsigned int RG_M0_WF5G_TX_MXR_EN : 1; ++ unsigned int RG_M0_WF5G_TX_IB_EN : 1; ++ unsigned int RG_M1_WF5G_TX_PA_EN : 1; ++ unsigned int RG_M1_WF5G_TX_MXR_EN : 1; ++ unsigned int RG_M1_WF5G_TX_IB_EN : 1; ++ unsigned int RG_M2_WF5G_TX_PA_EN : 1; ++ unsigned int RG_M2_WF5G_TX_MXR_EN : 1; ++ unsigned int RG_M2_WF5G_TX_IB_EN : 1; ++ unsigned int RG_M3_WF5G_TX_PA_EN : 1; ++ unsigned int RG_M3_WF5G_TX_MXR_EN : 1; ++ unsigned int RG_M3_WF5G_TX_IB_EN : 1; ++ unsigned int rsvd_0 : 4; ++ unsigned int RG_WF5G_TX_RSV : 16; ++ } b; ++} RG_TX_A3_FIELD_T; ++ ++#define RG_TX_A4 (RF_D_TX_REG_BASE + 0x10) ++// Bit 2 :0 rg_wf2g_tx_pa_vgcg0 U RW default = 'h7 ++// Bit 7 :3 rg_wf2g_tx_mxr_cbank U RW default = 'h4 ++// Bit 10 :8 rg_wf2g_tx_mxr_vgcg1 U RW default = 'h7 ++// Bit 13 :11 rg_wf2g_tx_mxr_lo_vb U RW default = 'h7 ++// Bit 16 :14 rg_wf2g_tx_mxr_lobuf_ict U RW default = 'h1 ++// Bit 20 :17 rg_wf2g_tx_var_u U RW default = 'h8 ++// Bit 24 :21 rg_wf2g_tx_var_d U RW default = 'h8 ++typedef union RG_TX_A4_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_TX_PA_VGCG0 : 3; ++ unsigned int RG_WF2G_TX_MXR_CBANK : 5; ++ unsigned int RG_WF2G_TX_MXR_VGCG1 : 3; ++ unsigned int RG_WF2G_TX_MXR_LO_VB : 3; ++ unsigned int RG_WF2G_TX_MXR_LOBUF_ICT : 3; ++ unsigned int RG_WF2G_TX_VAR_U : 4; ++ unsigned int RG_WF2G_TX_VAR_D : 4; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_TX_A4_FIELD_T; ++ ++#define RG_TX_A5 (RF_D_TX_REG_BASE + 0x14) ++// Bit 2 :0 rg_wf2g_tx_adb_cbank U RW default = 'h3 ++// Bit 6 :3 rg_wf2g_tx_adb_dcib U RW default = 'h0 ++// Bit 10 :7 rg_wf2g_tx_adb_dcvb U RW default = 'h0 ++// Bit 11 rg_wf2g_tx_adb_en U RW default = 'h1 ++// Bit 12 rg_wf2g_tx_adb_ed_en U RW default = 'h1 ++// Bit 16 :13 rg_wf2g_tx_adb_ed_gain U RW default = 'h3 ++// Bit 19 :17 rg_wf2g_tx_adb_icgm U RW default = 'h2 ++// Bit 22 :20 rg_wf2g_tx_adb_iptat U RW default = 'h2 ++// Bit 25 :23 rg_wf2g_tx_ib_adj U RW default = 'h3 ++// Bit 26 rg_wf2g_tx_tssi_en U RW default = 'h0 ++// Bit 29 :27 rg_wf2g_tx_tssi_attn U RW default = 'h7 ++typedef union RG_TX_A5_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_TX_ADB_CBANK : 3; ++ unsigned int RG_WF2G_TX_ADB_DCIB : 4; ++ unsigned int RG_WF2G_TX_ADB_DCVB : 4; ++ unsigned int RG_WF2G_TX_ADB_EN : 1; ++ unsigned int RG_WF2G_TX_ADB_ED_EN : 1; ++ unsigned int RG_WF2G_TX_ADB_ED_GAIN : 4; ++ unsigned int RG_WF2G_TX_ADB_ICGM : 3; ++ unsigned int RG_WF2G_TX_ADB_IPTAT : 3; ++ unsigned int RG_WF2G_TX_IB_ADJ : 3; ++ unsigned int RG_WF2G_TX_TSSI_EN : 1; ++ unsigned int RG_WF2G_TX_TSSI_ATTN : 3; ++ unsigned int rsvd_0 : 2; ++ } b; ++} RG_TX_A5_FIELD_T; ++ ++#define RG_TX_A6 (RF_D_TX_REG_BASE + 0x18) ++// Bit 2 :0 rg_wf2g_tx_tssi_lo_vb U RW default = 'h3 ++// Bit 3 rg_wf2g_tx_iqcal_en U RW default = 'h0 ++// Bit 4 rg_wf2g_tx_rxiqcal_en U RW default = 'h0 ++// Bit 12 :5 rg_wf2g_tx_tp_sel U RW default = 'h0 ++// Bit 13 rg_wf2g_tx_tp_en U RW default = 'h0 ++// Bit 16 :14 rg_wf2g_tx_pa_gain_man U RW default = 'h7 ++// Bit 19 :17 rg_wf2g_tx_mxr_gain_man U RW default = 'h7 ++// Bit 20 rg_wf2g_tx_man_mode U RW default = 'h0 ++typedef union RG_TX_A6_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_TX_TSSI_LO_VB : 3; ++ unsigned int RG_WF2G_TX_IQCAL_EN : 1; ++ unsigned int RG_WF2G_TX_RXIQCAL_EN : 1; ++ unsigned int RG_WF2G_TX_TP_SEL : 8; ++ unsigned int RG_WF2G_TX_TP_EN : 1; ++ unsigned int RG_WF2G_TX_PA_GAIN_MAN : 3; ++ unsigned int RG_WF2G_TX_MXR_GAIN_MAN : 3; ++ unsigned int RG_WF2G_TX_MAN_MODE : 1; ++ unsigned int rsvd_0 : 11; ++ } b; ++} RG_TX_A6_FIELD_T; ++ ++#define RG_TX_A7 (RF_D_TX_REG_BASE + 0x1c) ++// Bit 0 rg_m0_wf2g_tx_pa_en U RW default = 'h0 ++// Bit 1 rg_m0_wf2g_tx_mxr_en U RW default = 'h0 ++// Bit 2 rg_m0_wf2g_tx_var_en U RW default = 'h0 ++// Bit 3 rg_m0_wf2g_tx_ib_en U RW default = 'h0 ++// Bit 4 rg_m1_wf2g_tx_pa_en U RW default = 'h0 ++// Bit 5 rg_m1_wf2g_tx_mxr_en U RW default = 'h0 ++// Bit 6 rg_m1_wf2g_tx_var_en U RW default = 'h0 ++// Bit 7 rg_m1_wf2g_tx_ib_en U RW default = 'h0 ++// Bit 8 rg_m2_wf2g_tx_pa_en U RW default = 'h0 ++// Bit 9 rg_m2_wf2g_tx_mxr_en U RW default = 'h0 ++// Bit 10 rg_m2_wf2g_tx_var_en U RW default = 'h0 ++// Bit 11 rg_m2_wf2g_tx_ib_en U RW default = 'h0 ++// Bit 12 rg_m3_wf2g_tx_pa_en U RW default = 'h0 ++// Bit 13 rg_m3_wf2g_tx_mxr_en U RW default = 'h0 ++// Bit 14 rg_m3_wf2g_tx_var_en U RW default = 'h0 ++// Bit 15 rg_m3_wf2g_tx_ib_en U RW default = 'h0 ++// Bit 31 :16 rg_wf2g_tx_rsv U RW default = 'h0 ++typedef union RG_TX_A7_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M0_WF2G_TX_PA_EN : 1; ++ unsigned int RG_M0_WF2G_TX_MXR_EN : 1; ++ unsigned int RG_M0_WF2G_TX_VAR_EN : 1; ++ unsigned int RG_M0_WF2G_TX_IB_EN : 1; ++ unsigned int RG_M1_WF2G_TX_PA_EN : 1; ++ unsigned int RG_M1_WF2G_TX_MXR_EN : 1; ++ unsigned int RG_M1_WF2G_TX_VAR_EN : 1; ++ unsigned int RG_M1_WF2G_TX_IB_EN : 1; ++ unsigned int RG_M2_WF2G_TX_PA_EN : 1; ++ unsigned int RG_M2_WF2G_TX_MXR_EN : 1; ++ unsigned int RG_M2_WF2G_TX_VAR_EN : 1; ++ unsigned int RG_M2_WF2G_TX_IB_EN : 1; ++ unsigned int RG_M3_WF2G_TX_PA_EN : 1; ++ unsigned int RG_M3_WF2G_TX_MXR_EN : 1; ++ unsigned int RG_M3_WF2G_TX_VAR_EN : 1; ++ unsigned int RG_M3_WF2G_TX_IB_EN : 1; ++ unsigned int RG_WF2G_TX_RSV : 16; ++ } b; ++} RG_TX_A7_FIELD_T; ++ ++#define RG_TX_A8 (RF_D_TX_REG_BASE + 0x20) ++// Bit 2 :0 rg_wf5g_tx_pa_gain_g1 U RW default = 'h7 ++// Bit 6 :4 rg_wf5g_tx_pa_gain_g2 U RW default = 'h7 ++// Bit 10 :8 rg_wf5g_tx_pa_gain_g3 U RW default = 'h3 ++// Bit 14 :12 rg_wf5g_tx_pa_gain_g4 U RW default = 'h1 ++// Bit 18 :16 rg_wf5g_tx_mxr_gain_g1 U RW default = 'h7 ++// Bit 22 :20 rg_wf5g_tx_mxr_gain_g2 U RW default = 'h7 ++// Bit 26 :24 rg_wf5g_tx_mxr_gain_g3 U RW default = 'h3 ++// Bit 30 :28 rg_wf5g_tx_mxr_gain_g4 U RW default = 'h1 ++typedef union RG_TX_A8_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_TX_PA_GAIN_G1 : 3; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF5G_TX_PA_GAIN_G2 : 3; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF5G_TX_PA_GAIN_G3 : 3; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF5G_TX_PA_GAIN_G4 : 3; ++ unsigned int rsvd_3 : 1; ++ unsigned int RG_WF5G_TX_MXR_GAIN_G1 : 3; ++ unsigned int rsvd_4 : 1; ++ unsigned int RG_WF5G_TX_MXR_GAIN_G2 : 3; ++ unsigned int rsvd_5 : 1; ++ unsigned int RG_WF5G_TX_MXR_GAIN_G3 : 3; ++ unsigned int rsvd_6 : 1; ++ unsigned int RG_WF5G_TX_MXR_GAIN_G4 : 3; ++ unsigned int rsvd_7 : 1; ++ } b; ++} RG_TX_A8_FIELD_T; ++ ++#define RG_TX_A9 (RF_D_TX_REG_BASE + 0x24) ++// Bit 2 :0 rg_wf2g_tx_pa_gain_g1 U RW default = 'h7 ++// Bit 6 :4 rg_wf2g_tx_pa_gain_g2 U RW default = 'h7 ++// Bit 10 :8 rg_wf2g_tx_pa_gain_g3 U RW default = 'h3 ++// Bit 14 :12 rg_wf2g_tx_pa_gain_g4 U RW default = 'h1 ++// Bit 18 :16 rg_wf2g_tx_mxr_gain_g1 U RW default = 'h7 ++// Bit 22 :20 rg_wf2g_tx_mxr_gain_g2 U RW default = 'h7 ++// Bit 26 :24 rg_wf2g_tx_mxr_gain_g3 U RW default = 'h3 ++// Bit 30 :28 rg_wf2g_tx_mxr_gain_g4 U RW default = 'h1 ++typedef union RG_TX_A9_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF2G_TX_PA_GAIN_G1 : 3; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_WF2G_TX_PA_GAIN_G2 : 3; ++ unsigned int rsvd_1 : 1; ++ unsigned int RG_WF2G_TX_PA_GAIN_G3 : 3; ++ unsigned int rsvd_2 : 1; ++ unsigned int RG_WF2G_TX_PA_GAIN_G4 : 3; ++ unsigned int rsvd_3 : 1; ++ unsigned int RG_WF2G_TX_MXR_GAIN_G1 : 3; ++ unsigned int rsvd_4 : 1; ++ unsigned int RG_WF2G_TX_MXR_GAIN_G2 : 3; ++ unsigned int rsvd_5 : 1; ++ unsigned int RG_WF2G_TX_MXR_GAIN_G3 : 3; ++ unsigned int rsvd_6 : 1; ++ unsigned int RG_WF2G_TX_MXR_GAIN_G4 : 3; ++ unsigned int rsvd_7 : 1; ++ } b; ++} RG_TX_A9_FIELD_T; ++ ++#define RG_TX_A10 (RF_D_TX_REG_BASE + 0x28) ++// Bit 0 rg_m4_wf5g_tx_pa_en U RW default = 'h1 ++// Bit 1 rg_m4_wf5g_tx_mxr_en U RW default = 'h1 ++// Bit 2 rg_m4_wf5g_tx_ib_en U RW default = 'h1 ++// Bit 3 rg_m5_wf5g_tx_pa_en U RW default = 'h0 ++// Bit 4 rg_m5_wf5g_tx_mxr_en U RW default = 'h0 ++// Bit 5 rg_m5_wf5g_tx_ib_en U RW default = 'h0 ++// Bit 6 rg_m6_wf5g_tx_pa_en U RW default = 'h0 ++// Bit 7 rg_m6_wf5g_tx_mxr_en U RW default = 'h0 ++// Bit 8 rg_m6_wf5g_tx_ib_en U RW default = 'h0 ++// Bit 9 rg_m7_wf5g_tx_pa_en U RW default = 'h0 ++// Bit 10 rg_m7_wf5g_tx_mxr_en U RW default = 'h0 ++// Bit 11 rg_m7_wf5g_tx_ib_en U RW default = 'h0 ++typedef union RG_TX_A10_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M4_WF5G_TX_PA_EN : 1; ++ unsigned int RG_M4_WF5G_TX_MXR_EN : 1; ++ unsigned int RG_M4_WF5G_TX_IB_EN : 1; ++ unsigned int RG_M5_WF5G_TX_PA_EN : 1; ++ unsigned int RG_M5_WF5G_TX_MXR_EN : 1; ++ unsigned int RG_M5_WF5G_TX_IB_EN : 1; ++ unsigned int RG_M6_WF5G_TX_PA_EN : 1; ++ unsigned int RG_M6_WF5G_TX_MXR_EN : 1; ++ unsigned int RG_M6_WF5G_TX_IB_EN : 1; ++ unsigned int RG_M7_WF5G_TX_PA_EN : 1; ++ unsigned int RG_M7_WF5G_TX_MXR_EN : 1; ++ unsigned int RG_M7_WF5G_TX_IB_EN : 1; ++ unsigned int rsvd_0 : 20; ++ } b; ++} RG_TX_A10_FIELD_T; ++ ++#define RG_TX_A11 (RF_D_TX_REG_BASE + 0x2c) ++// Bit 0 rg_m4_wf2g_tx_pa_en U RW default = 'h0 ++// Bit 1 rg_m4_wf2g_tx_mxr_en U RW default = 'h0 ++// Bit 2 rg_m4_wf2g_tx_var_en U RW default = 'h0 ++// Bit 3 rg_m4_wf2g_tx_ib_en U RW default = 'h0 ++// Bit 4 rg_m5_wf2g_tx_pa_en U RW default = 'h0 ++// Bit 5 rg_m5_wf2g_tx_mxr_en U RW default = 'h0 ++// Bit 6 rg_m5_wf2g_tx_var_en U RW default = 'h0 ++// Bit 7 rg_m5_wf2g_tx_ib_en U RW default = 'h0 ++// Bit 8 rg_m6_wf2g_tx_pa_en U RW default = 'h1 ++// Bit 9 rg_m6_wf2g_tx_mxr_en U RW default = 'h1 ++// Bit 10 rg_m6_wf2g_tx_var_en U RW default = 'h1 ++// Bit 11 rg_m6_wf2g_tx_ib_en U RW default = 'h1 ++// Bit 12 rg_m7_wf2g_tx_pa_en U RW default = 'h0 ++// Bit 13 rg_m7_wf2g_tx_mxr_en U RW default = 'h0 ++// Bit 14 rg_m7_wf2g_tx_var_en U RW default = 'h0 ++// Bit 15 rg_m7_wf2g_tx_ib_en U RW default = 'h0 ++typedef union RG_TX_A11_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_M4_WF2G_TX_PA_EN : 1; ++ unsigned int RG_M4_WF2G_TX_MXR_EN : 1; ++ unsigned int RG_M4_WF2G_TX_VAR_EN : 1; ++ unsigned int RG_M4_WF2G_TX_IB_EN : 1; ++ unsigned int RG_M5_WF2G_TX_PA_EN : 1; ++ unsigned int RG_M5_WF2G_TX_MXR_EN : 1; ++ unsigned int RG_M5_WF2G_TX_VAR_EN : 1; ++ unsigned int RG_M5_WF2G_TX_IB_EN : 1; ++ unsigned int RG_M6_WF2G_TX_PA_EN : 1; ++ unsigned int RG_M6_WF2G_TX_MXR_EN : 1; ++ unsigned int RG_M6_WF2G_TX_VAR_EN : 1; ++ unsigned int RG_M6_WF2G_TX_IB_EN : 1; ++ unsigned int RG_M7_WF2G_TX_PA_EN : 1; ++ unsigned int RG_M7_WF2G_TX_MXR_EN : 1; ++ unsigned int RG_M7_WF2G_TX_VAR_EN : 1; ++ unsigned int RG_M7_WF2G_TX_IB_EN : 1; ++ unsigned int rsvd_0 : 16; ++ } b; ++} RG_TX_A11_FIELD_T; ++ ++#define RG_TX_A12 (RF_D_TX_REG_BASE + 0x30) ++// Bit 7 :0 rg_wf_tx_gain_man U RW default = 'h0 ++// Bit 8 rg_wf_tx_gain_man_mode U RW default = 'h0 ++// Bit 23 :16 rg_wf_tx_pa_en_delay_bnd U RW default = 'h14 ++// Bit 24 rg_wf_tx_pa_en_delay_bypass U RW default = 'h0 ++typedef union RG_TX_A12_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF_TX_GAIN_MAN : 8; ++ unsigned int RG_WF_TX_GAIN_MAN_MODE : 1; ++ unsigned int rsvd_0 : 7; ++ unsigned int RG_WF_TX_PA_EN_DELAY_BND : 8; ++ unsigned int RG_WF_TX_PA_EN_DELAY_BYPASS : 1; ++ unsigned int rsvd_1 : 7; ++ } b; ++} RG_TX_A12_FIELD_T; ++ ++#define RG_TX_A13 (RF_D_TX_REG_BASE + 0x34) ++// Bit 4 :0 rg_wf5g_tx_mxr_cbank_g1 U RW default = 'h7 ++// Bit 9 :5 rg_wf5g_tx_mxr_cbank_g2 U RW default = 'h7 ++// Bit 14 :10 rg_wf5g_tx_mxr_cbank_g3 U RW default = 'h7 ++// Bit 19 :15 rg_wf5g_tx_mxr_cbank_g4 U RW default = 'h3 ++// Bit 24 :20 rg_wf5g_tx_mxr_cbank_man U RW default = 'h4 ++typedef union RG_TX_A13_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int RG_WF5G_TX_MXR_CBANK_G1 : 5; ++ unsigned int RG_WF5G_TX_MXR_CBANK_G2 : 5; ++ unsigned int RG_WF5G_TX_MXR_CBANK_G3 : 5; ++ unsigned int RG_WF5G_TX_MXR_CBANK_G4 : 5; ++ unsigned int RG_WF5G_TX_MXR_CBANK_MAN : 5; ++ unsigned int rsvd_0 : 7; ++ } b; ++} RG_TX_A13_FIELD_T; ++ ++#endif ++ +diff --git a/drivers/net/wireless/w1/common/rf_d_xosc_reg.h b/drivers/net/wireless/w1/common/rf_d_xosc_reg.h +new file mode 100644 +index 0000000000000000000000000000000000000000..1e5bfa1aaaf78ffd86da3372f3aa2fb21109221e +--- /dev/null ++++ b/drivers/net/wireless/w1/common/rf_d_xosc_reg.h +@@ -0,0 +1,121 @@ ++#ifdef RF_D_XOSC_REG +#else -+#define RF_D_ADDA_CORE_REG -+ -+ -+#define RF_D_ADDA_CORE_REG_BASE (0xa0e000) -+ -+#define RG_CORE_A0 (RF_D_ADDA_CORE_REG_BASE + 0x0) -+// Bit 31 :0 rg_core_cfg0 U RW default = 'h0 -+typedef union RG_CORE_A0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_core_cfg0 : 32; -+ } b; -+} RG_CORE_A0_FIELD_T; ++#define RF_D_XOSC_REG + -+#define RG_CORE_A1 (RF_D_ADDA_CORE_REG_BASE + 0x4) -+// Bit 31 :0 rg_core_cfg1 U RW default = 'h0 -+typedef union RG_CORE_A1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_core_cfg1 : 32; -+ } b; -+} RG_CORE_A1_FIELD_T; -+ -+#define RG_CORE_A2 (RF_D_ADDA_CORE_REG_BASE + 0x8) -+// Bit 0 rg_core_enb_man U RW default = 'h0 -+// Bit 4 rg_core_enb_man_en U RW default = 'h0 -+// Bit 8 rg_xmit_enb_man U RW default = 'h0 -+// Bit 12 rg_xmit_enb_man_en U RW default = 'h0 -+// Bit 16 rg_recv_enb_man U RW default = 'h0 -+// Bit 20 rg_recv_enb_man_en U RW default = 'h0 -+// Bit 24 rg_esti_enb_man U RW default = 'h0 -+// Bit 28 rg_esti_enb_man_en U RW default = 'h0 -+typedef union RG_CORE_A2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_core_enb_man : 1; -+ unsigned int rsvd_0 : 3; -+ unsigned int rg_core_enb_man_en : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int rg_xmit_enb_man : 1; -+ unsigned int rsvd_2 : 3; -+ unsigned int rg_xmit_enb_man_en : 1; -+ unsigned int rsvd_3 : 3; -+ unsigned int rg_recv_enb_man : 1; -+ unsigned int rsvd_4 : 3; -+ unsigned int rg_recv_enb_man_en : 1; -+ unsigned int rsvd_5 : 3; -+ unsigned int rg_esti_enb_man : 1; -+ unsigned int rsvd_6 : 3; -+ unsigned int rg_esti_enb_man_en : 1; -+ unsigned int rsvd_7 : 3; -+ } b; -+} RG_CORE_A2_FIELD_T; ++#define CHIP_ANA_REG_BASE (0xf01000) + -+#define RG_CORE_A3 (RF_D_ADDA_CORE_REG_BASE + 0xc) -+// Bit 12 :0 rg_freq_mhz_man U RW default = 'h0 -+// Bit 15 rg_freq_mhz_man_en U RW default = 'h0 -+// Bit 24 rg_2g_5g_man U RW default = 'h0 -+// Bit 31 rg_2g_5g_man_en U RW default = 'h0 -+typedef union RG_CORE_A3_FIELD ++#define RG_XOSC_A7 (CHIP_ANA_REG_BASE + 0x20) ++// Bit 0 rg_xo_bg_en_man U RW default = 'h1 ++// Bit 2 rg_xo_bg_en_man_sel U RW default = 'h0 ++// Bit 3 rg_xo_ldo_bypass_en U RW default = 'h0 ++// Bit 4 rg_xo_ldo_en_man U RW default = 'h1 ++// Bit 5 rg_xo_ldo_en_man_sel U RW default = 'h0 ++// Bit 7 :6 rg_xo_ldo_fbr_ctrl U RW default = 'h2 ++// Bit 13 :8 rg_xo_ldo_vref_cal U RW default = 'h10 ++// Bit 14 rg_xo_en_man U RW default = 'h1 ++// Bit 15 rg_xo_en_man_sel U RW default = 'h0 ++// Bit 16 rg_xo_sel U RW default = 'h0 ++// Bit 21 :17 rg_xo_core_bias_rcal_ctrl U RW default = 'h10 ++typedef union RG_XOSC_A7_FIELD +{ + unsigned int data; + struct + { -+ unsigned int rg_freq_mhz_man : 13; -+ unsigned int rsvd_0 : 2; -+ unsigned int rg_freq_mhz_man_en : 1; -+ unsigned int rsvd_1 : 8; -+ unsigned int rg_2g_5g_man : 1; -+ unsigned int rsvd_2 : 6; -+ unsigned int rg_2g_5g_man_en : 1; ++ unsigned int RG_XO_BG_EN_MAN : 1; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_XO_BG_EN_MAN_SEL : 1; ++ unsigned int RG_XO_LDO_BYPASS_EN : 1; ++ unsigned int RG_XO_LDO_EN_MAN : 1; ++ unsigned int RG_XO_LDO_EN_MAN_SEL : 1; ++ unsigned int RG_XO_LDO_FBR_CTRL : 2; ++ unsigned int RG_XO_LDO_VREF_CAL : 6; ++ unsigned int RG_XO_EN_MAN : 1; ++ unsigned int RG_XO_EN_MAN_SEL : 1; ++ unsigned int RG_XO_SEL : 1; ++ unsigned int RG_XO_CORE_BIAS_RCAL_CTRL : 5; ++ unsigned int rsvd_1 : 10; + } b; -+} RG_CORE_A3_FIELD_T; ++} RG_XOSC_A7_FIELD_T; + -+#define RG_CORE_A4 (RF_D_ADDA_CORE_REG_BASE + 0x10) -+// Bit 3 :0 rg_tx_pwrlvl_man U RW default = 'h0 -+// Bit 8 rg_tx_pwrlvl_man_en U RW default = 'h0 -+// Bit 17 :16 rg_tx_bw_man U RW default = 'h0 -+// Bit 20 rg_tx_bw_man_en U RW default = 'h0 -+// Bit 25 :24 rg_dac_fs_man U RW default = 'h0 -+// Bit 28 rg_dac_fs_man_en U RW default = 'h0 -+typedef union RG_CORE_A4_FIELD ++#define RG_XOSC_A8 (CHIP_ANA_REG_BASE + 0x24) ++// Bit 3 :0 rg_xo_core_cfixed_ctrl U RW default = 'h8 ++// Bit 11 :4 rg_xo_core_ctune_ctrl U RW default = 'h32 ++// Bit 15 :12 rg_xo_core_gmos_vb_sel U RW default = 'h8 ++// Bit 20 :17 rg_xo_pd_vref_sel U RW default = 'h8 ++typedef union RG_XOSC_A8_FIELD +{ + unsigned int data; + struct + { -+ unsigned int rg_tx_pwrlvl_man : 4; -+ unsigned int rsvd_0 : 4; -+ unsigned int rg_tx_pwrlvl_man_en : 1; -+ unsigned int rsvd_1 : 7; -+ unsigned int rg_tx_bw_man : 2; -+ unsigned int rsvd_2 : 2; -+ unsigned int rg_tx_bw_man_en : 1; -+ unsigned int rsvd_3 : 3; -+ unsigned int rg_dac_fs_man : 2; -+ unsigned int rsvd_4 : 2; -+ unsigned int rg_dac_fs_man_en : 1; -+ unsigned int rsvd_5 : 3; ++ unsigned int RG_XO_CORE_CFIXED_CTRL : 4; ++ unsigned int RG_XO_CORE_CTUNE_CTRL : 8; ++ unsigned int RG_XO_CORE_GMOS_VB_SEL : 4; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_XO_PD_VREF_SEL : 4; ++ unsigned int rsvd_1 : 11; + } b; -+} RG_CORE_A4_FIELD_T; ++} RG_XOSC_A8_FIELD_T; + -+#define RG_CORE_A5 (RF_D_ADDA_CORE_REG_BASE + 0x14) -+// Bit 7 :0 rg_rx_gain_man U RW default = 'h0 -+// Bit 8 rg_rx_gain_man_en U RW default = 'h0 -+// Bit 17 :16 rg_rx_bw_man U RW default = 'h0 -+// Bit 20 rg_rx_bw_man_en U RW default = 'h0 -+// Bit 25 :24 rg_adc_fs_man U RW default = 'h0 -+// Bit 28 rg_adc_fs_man_en U RW default = 'h0 -+typedef union RG_CORE_A5_FIELD ++#define RG_XOSC_A9 (CHIP_ANA_REG_BASE + 0x28) ++// Bit 3 :0 rg_xo_buf1_bias_ctrl U RW default = 'h8 ++// Bit 7 :4 rg_xo_buf2_bias_ctrl U RW default = 'h8 ++// Bit 11 :8 rg_xo_buf3_bias_ctrl U RW default = 'h8 ++// Bit 12 rg_xo_aml_cal_error_ctrl U RW default = 'h0 ++typedef union RG_XOSC_A9_FIELD +{ + unsigned int data; + struct + { -+ unsigned int rg_rx_gain_man : 8; -+ unsigned int rg_rx_gain_man_en : 1; -+ unsigned int rsvd_0 : 7; -+ unsigned int rg_rx_bw_man : 2; -+ unsigned int rsvd_1 : 2; -+ unsigned int rg_rx_bw_man_en : 1; -+ unsigned int rsvd_2 : 3; -+ unsigned int rg_adc_fs_man : 2; -+ unsigned int rsvd_3 : 2; -+ unsigned int rg_adc_fs_man_en : 1; -+ unsigned int rsvd_4 : 3; ++ unsigned int RG_XO_BUF1_BIAS_CTRL : 4; ++ unsigned int RG_XO_BUF2_BIAS_CTRL : 4; ++ unsigned int RG_XO_BUF3_BIAS_CTRL : 4; ++ unsigned int RG_XO_AML_CAL_ERROR_CTRL : 1; ++ unsigned int rsvd_0 : 19; + } b; -+} RG_CORE_A5_FIELD_T; ++} RG_XOSC_A9_FIELD_T; + -+#define RG_CORE_A6 (RF_D_ADDA_CORE_REG_BASE + 0x18) -+// Bit 1 :0 rg_rf_mode_man U RW default = 'h0 -+// Bit 4 rg_rf_mode_man_en U RW default = 'h0 -+// Bit 11 :8 rg_cali_mode_man U RW default = 'h0 -+// Bit 16 rg_cali_mode_man_en U RW default = 'h0 -+// Bit 20 rg_tx_rx_man_en U RW default = 'h0 -+// Bit 24 rg_tx_rx_man U RW default = 'h0 -+typedef union RG_CORE_A6_FIELD ++#define RG_XOSC_A11 (CHIP_ANA_REG_BASE + 0x30) ++// Bit 0 rg_xo_ldo_fc_en_man_sel U RW default = 'h0 ++// Bit 1 rg_xo_ldo_fc_en_man U RW default = 'h0 ++// Bit 2 rg_xo_pd_en_man_sel U RW default = 'h0 ++// Bit 3 rg_xo_pd_en_man U RW default = 'h1 ++// Bit 4 rg_xo_buf_core_en_man_sel U RW default = 'h0 ++// Bit 5 rg_xo_buf_core_en_man U RW default = 'h1 ++// Bit 6 rg_xo_buf_wf_en_man_sel U RW default = 'h0 ++// Bit 7 rg_xo_buf_wf_en_man U RW default = 'h1 ++// Bit 8 rg_xo_buf_dig_en_man_sel U RW default = 'h0 ++// Bit 9 rg_xo_buf_dig_en_man U RW default = 'h1 ++// Bit 10 rg_xo_buf_bb_en_man_sel U RW default = 'h0 ++// Bit 11 rg_xo_buf_bb_en_man U RW default = 'h1 ++// Bit 12 rg_xo_buf_bt_en_man_sel U RW default = 'h0 ++// Bit 13 rg_xo_buf_bt_en_man U RW default = 'h1 ++// Bit 15 rg_xo_core_bias_ctrl_man_sel U RW default = 'h0 ++// Bit 23 :16 rg_xo_core_bias_ctrl_man U RW default = 'hff ++// Bit 31 :24 rg_xosc_wait_bnd U RW default = 'h3f ++typedef union RG_XOSC_A11_FIELD +{ + unsigned int data; + struct + { -+ unsigned int rg_rf_mode_man : 2; -+ unsigned int rsvd_0 : 2; -+ unsigned int rg_rf_mode_man_en : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int rg_cali_mode_man : 4; -+ unsigned int rsvd_2 : 4; -+ unsigned int rg_cali_mode_man_en : 1; -+ unsigned int rsvd_3 : 3; -+ unsigned int rg_tx_rx_man_en : 1; -+ unsigned int rsvd_4 : 3; -+ unsigned int rg_tx_rx_man : 1; -+ unsigned int rsvd_5 : 7; ++ unsigned int RG_XO_LDO_FC_EN_MAN_SEL : 1; ++ unsigned int RG_XO_LDO_FC_EN_MAN : 1; ++ unsigned int RG_XO_PD_EN_MAN_SEL : 1; ++ unsigned int RG_XO_PD_EN_MAN : 1; ++ unsigned int RG_XO_BUF_CORE_EN_MAN_SEL : 1; ++ unsigned int RG_XO_BUF_CORE_EN_MAN : 1; ++ unsigned int RG_XO_BUF_WF_EN_MAN_SEL : 1; ++ unsigned int RG_XO_BUF_WF_EN_MAN : 1; ++ unsigned int RG_XO_BUF_DIG_EN_MAN_SEL : 1; ++ unsigned int RG_XO_BUF_DIG_EN_MAN : 1; ++ unsigned int RG_XO_BUF_BB_EN_MAN_SEL : 1; ++ unsigned int RG_XO_BUF_BB_EN_MAN : 1; ++ unsigned int RG_XO_BUF_BT_EN_MAN_SEL : 1; ++ unsigned int RG_XO_BUF_BT_EN_MAN : 1; ++ unsigned int rsvd_0 : 1; ++ unsigned int RG_XO_CORE_BIAS_CTRL_MAN_SEL : 1; ++ unsigned int RG_XO_CORE_BIAS_CTRL_MAN : 8; ++ unsigned int RG_XOSC_WAIT_BND : 8; + } b; -+} RG_CORE_A6_FIELD_T; ++} RG_XOSC_A11_FIELD_T; + +#endif -+ -diff --git a/drivers/net/wireless/w1/common/rf_d_adda_esti_reg.h b/drivers/net/wireless/w1/common/rf_d_adda_esti_reg.h +\ No newline at end of file +diff --git a/drivers/net/wireless/w1/common/wf_register.h b/drivers/net/wireless/w1/common/wf_register.h new file mode 100644 -index 000000000000..171c9610ea43 +index 0000000000000000000000000000000000000000..f2b2b78c05ffa15f7c02f1af2ecdbbbf092b0943 --- /dev/null -+++ b/drivers/net/wireless/w1/common/rf_d_adda_esti_reg.h -@@ -0,0 +1,1390 @@ -+#ifdef RF_D_ADDA_ESTI_REG -+#else -+#define RF_D_ADDA_ESTI_REG ++++ b/drivers/net/wireless/w1/common/wf_register.h +@@ -0,0 +1,21 @@ ++#ifndef __WF_REGISTER__ ++#define __WF_REGISTER__ + ++// aon ++#include "chip_ana_reg.h" ++#include "chip_intf_reg.h" ++#include "chip_pmu_reg.h" + -+#define RF_D_ADDA_ESTI_REG_BASE (0xa0ec00) ++// rf adda ++#include "rf_d_adda_core_reg.h" ++#include "rf_d_adda_esti_reg.h" ++#include "rf_d_adda_recv_reg.h" ++#include "rf_d_adda_xmit_reg.h" + -+#define RG_ESTI_A0 (RF_D_ADDA_ESTI_REG_BASE + 0x0) -+// Bit 31 :0 rg_esti_cfg0 U RW default = 'h0 -+typedef union RG_ESTI_A0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_esti_cfg0 : 32; -+ } b; -+} RG_ESTI_A0_FIELD_T; ++// rf ++#include "rf_d_rx_reg.h" ++#include "rf_d_sx_reg.h" ++#include "rf_d_top_reg.h" ++#include "rf_d_tx_reg.h" + -+#define RG_ESTI_A1 (RF_D_ADDA_ESTI_REG_BASE + 0x4) -+// Bit 31 :0 rg_esti_cfg1 U RW default = 'h0 -+typedef union RG_ESTI_A1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_esti_cfg1 : 32; -+ } b; -+} RG_ESTI_A1_FIELD_T; ++#endif +diff --git a/drivers/net/wireless/w1/common/wifi_adda_addr.h b/drivers/net/wireless/w1/common/wifi_adda_addr.h +new file mode 100644 +index 0000000000000000000000000000000000000000..b772bb73ee105c54a2a0e3542a1c3ae37a605f67 +--- /dev/null ++++ b/drivers/net/wireless/w1/common/wifi_adda_addr.h +@@ -0,0 +1,10 @@ ++#ifndef __WIFI_ADDA_ADDR_H__ ++#define __WIFI_ADDA_ADDR_H__ + -+#define RG_ESTI_A3 (RF_D_ADDA_ESTI_REG_BASE + 0xc) -+// Bit 14 :0 ro_rxirr_eup_0 U RO default = 'h0 -+// Bit 30 :16 ro_rxirr_eup_1 U RO default = 'h0 -+typedef union RG_ESTI_A3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rxirr_eup_0 : 15; -+ unsigned int rsvd_0 : 1; -+ unsigned int ro_rxirr_eup_1 : 15; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_ESTI_A3_FIELD_T; ++#define WIFI_ADDA (0xe000) + -+#define RG_ESTI_A4 (RF_D_ADDA_ESTI_REG_BASE + 0x10) -+// Bit 14 :0 ro_rxirr_eup_2 U RO default = 'h0 -+// Bit 30 :16 ro_rxirr_eup_3 U RO default = 'h0 -+typedef union RG_ESTI_A4_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rxirr_eup_2 : 15; -+ unsigned int rsvd_0 : 1; -+ unsigned int ro_rxirr_eup_3 : 15; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_ESTI_A4_FIELD_T; ++#define RG_ADDA_ADR_88 (WIFI_ADDA + 0x488) ++#define RG_IQ_SWAP_CTRL (WIFI_ADDA + 0x808) + -+#define RG_ESTI_A5 (RF_D_ADDA_ESTI_REG_BASE + 0x14) -+// Bit 14 :0 ro_rxirr_pup_0 U RO default = 'h0 -+// Bit 30 :16 ro_rxirr_pup_1 U RO default = 'h0 -+typedef union RG_ESTI_A5_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rxirr_pup_0 : 15; -+ unsigned int rsvd_0 : 1; -+ unsigned int ro_rxirr_pup_1 : 15; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_ESTI_A5_FIELD_T; ++#endif + -+#define RG_ESTI_A6 (RF_D_ADDA_ESTI_REG_BASE + 0x18) -+// Bit 14 :0 ro_rxirr_pup_2 U RO default = 'h0 -+// Bit 30 :16 ro_rxirr_pup_3 U RO default = 'h0 -+typedef union RG_ESTI_A6_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rxirr_pup_2 : 15; -+ unsigned int rsvd_0 : 1; -+ unsigned int ro_rxirr_pup_3 : 15; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_ESTI_A6_FIELD_T; +diff --git a/drivers/net/wireless/w1/common/wifi_agc_addr.h b/drivers/net/wireless/w1/common/wifi_agc_addr.h +new file mode 100644 +index 0000000000000000000000000000000000000000..e850665c2e07e8bed42a32467f152feadcfdb201 +--- /dev/null ++++ b/drivers/net/wireless/w1/common/wifi_agc_addr.h +@@ -0,0 +1,110 @@ ++#ifndef __ADDR_AGC_H__ ++#define __ADDR_AGC_H__ + -+#define RG_ESTI_A7 (RF_D_ADDA_ESTI_REG_BASE + 0x1c) -+// Bit 14 :0 ro_rxirr_elow_0 U RO default = 'h0 -+// Bit 30 :16 ro_rxirr_elow_1 U RO default = 'h0 -+typedef union RG_ESTI_A7_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rxirr_elow_0 : 15; -+ unsigned int rsvd_0 : 1; -+ unsigned int ro_rxirr_elow_1 : 15; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_ESTI_A7_FIELD_T; ++#define WIFI_AGC (0x8000) + -+#define RG_ESTI_A8 (RF_D_ADDA_ESTI_REG_BASE + 0x20) -+// Bit 14 :0 ro_rxirr_elow_2 U RO default = 'h0 -+// Bit 30 :16 ro_rxirr_elow_3 U RO default = 'h0 -+typedef union RG_ESTI_A8_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rxirr_elow_2 : 15; -+ unsigned int rsvd_0 : 1; -+ unsigned int ro_rxirr_elow_3 : 15; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_ESTI_A8_FIELD_T; ++#define RG_AGC_STF_LIMIT_CCA_COND_EN (WIFI_AGC + 0x6c) ++#define RG_AGC_CCA_COND_TS_CTRL (WIFI_AGC + 0x70) ++#define RG_AGC_RG_AGC_OB_CCA_RES (WIFI_AGC + 0x274) ++#define RG_AGC_RG_AGC_OB_CCA_COND01 (WIFI_AGC + 0x278) ++#define RG_AGC_RG_AGC_OB_CCA_COND23 (WIFI_AGC + 0x27c) ++#define RG_AGC_STATE (WIFI_AGC+0x258) ++#define RG_AGC_OB_IC_GAIN (WIFI_AGC+0x25c) ++#define RG_AGC_WATCH1 (WIFI_AGC+0x260) ++#define RG_AGC_WATCH2 (WIFI_AGC+0x264) ++#define RG_AGC_WATCH3 (WIFI_AGC+0x268) ++#define RG_AGC_WATCH4 (WIFI_AGC+0x26c) ++#define RG_AGC_OB_ANT_NFLOOR (WIFI_AGC+0x270) ++#define RG_AGC_OB_CCA_RES (WIFI_AGC+0x274) ++#define RG_AGC_OB_CCA_COND01 (WIFI_AGC+0x278) ++#define RG_AGC_OB_CCA_COND23 (WIFI_AGC+0x27c) ++#define RG_AGC_GAIN_SEL (WIFI_AGC+ 0x84) ++#define RG_AGC_STS_REG_0 (WIFI_AGC+ 0x64) ++#define RG_AGC_EN (WIFI_AGC+ 0x10) + -+#define RG_ESTI_A9 (RF_D_ADDA_ESTI_REG_BASE + 0x24) -+// Bit 14 :0 ro_rxirr_plow_0 U RO default = 'h0 -+// Bit 30 :16 ro_rxirr_plow_1 U RO default = 'h0 -+typedef union RG_ESTI_A9_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rxirr_plow_0 : 15; -+ unsigned int rsvd_0 : 1; -+ unsigned int ro_rxirr_plow_1 : 15; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_ESTI_A9_FIELD_T; + -+#define RG_ESTI_A10 (RF_D_ADDA_ESTI_REG_BASE + 0x28) -+// Bit 14 :0 ro_rxirr_plow_2 U RO default = 'h0 -+// Bit 30 :16 ro_rxirr_plow_3 U RO default = 'h0 -+typedef union RG_ESTI_A10_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rxirr_plow_2 : 15; -+ unsigned int rsvd_0 : 1; -+ unsigned int ro_rxirr_plow_3 : 15; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_ESTI_A10_FIELD_T; -+ -+#define RG_ESTI_A11 (RF_D_ADDA_ESTI_REG_BASE + 0x2c) -+// Bit 0 rg_iqib_enable U RW default = 'h0 -+// Bit 1 rg_iqib_hold U RW default = 'h0 -+// Bit 7 :4 rg_iqib_period U RW default = 'h0 -+// Bit 11 :8 rg_iqib_step_a U RW default = 'h1 -+// Bit 15 :12 rg_iqib_step_b U RW default = 'h1 -+// Bit 18 :16 rg_iqib_shift U RW default = 'h0 -+// Bit 20 rg_iqib_man_en U RW default = 'h0 -+// Bit 24 rg_rxirr_read_response U RW default = 'h0 -+// Bit 28 rg_rxirr_read_response_bypass U RW default = 'h0 -+// Bit 31 ro_rxirr_ready U RO default = 'h0 -+typedef union RG_ESTI_A11_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_iqib_enable : 1; -+ unsigned int rg_iqib_hold : 1; -+ unsigned int rsvd_0 : 2; -+ unsigned int rg_iqib_period : 4; -+ unsigned int rg_iqib_step_a : 4; -+ unsigned int rg_iqib_step_b : 4; -+ unsigned int rg_iqib_shift : 3; -+ unsigned int rsvd_1 : 1; -+ unsigned int rg_iqib_man_en : 1; -+ unsigned int rsvd_2 : 3; -+ unsigned int rg_rxirr_read_response : 1; -+ unsigned int rsvd_3 : 3; -+ unsigned int rg_rxirr_read_response_bypass : 1; -+ unsigned int rsvd_4 : 2; -+ unsigned int ro_rxirr_ready : 1; -+ } b; -+} RG_ESTI_A11_FIELD_T; ++struct AGC_CCA_COND_TS_CTRL_BITS { ++ unsigned int cca_cond_ts :8, ++ cca_cond_ts_num :20, ++ ed_avglen :3, ++ reserved41 :1; ++}; + -+#define RG_ESTI_A12 (RF_D_ADDA_ESTI_REG_BASE + 0x30) -+// Bit 21 :0 rg_set_b U RW default = 'h0 -+// Bit 31 rg_set_val U RW default = 'h0 -+typedef union RG_ESTI_A12_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_set_b : 22; -+ unsigned int rsvd_0 : 9; -+ unsigned int rg_set_val : 1; -+ } b; -+} RG_ESTI_A12_FIELD_T; ++struct AGC_OB_CCA_RES_BITS { ++ unsigned int cca_cond_rdy :1, ++ reserved170 :15, ++ cca_cond8 :16; ++}; + -+#define RG_ESTI_A13 (RF_D_ADDA_ESTI_REG_BASE + 0x34) -+// Bit 18 :0 rg_set_a U RW default = 'h0 -+typedef union RG_ESTI_A13_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_set_a : 19; -+ unsigned int rsvd_0 : 13; -+ } b; -+} RG_ESTI_A13_FIELD_T; ++struct AGC_STF_LIMIT_CCA_COND_EN_BITS { ++ unsigned int stf_cfo_limit :19, ++ reserved39 :1, ++ cca_cond_en :9, ++ cca_cal_force :1, ++ reserved40 :2; ++}; + -+#define RG_ESTI_A14 (RF_D_ADDA_ESTI_REG_BASE + 0x38) -+// Bit 3 :0 rg_dc_rm_leaky_factor U RW default = 'h0 -+// Bit 28 :4 rg_spectrum_ana_angle_man U RW default = 'h0 -+// Bit 31 rg_spectrum_ana_angle_man_en U RW default = 'h0 -+typedef union RG_ESTI_A14_FIELD ++#pragma pack(push ,1) ++struct agc_prt_info +{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_dc_rm_leaky_factor : 4; -+ unsigned int rg_spectrum_ana_angle_man : 25; -+ unsigned int rsvd_0 : 2; -+ unsigned int rg_spectrum_ana_angle_man_en : 1; -+ } b; -+} RG_ESTI_A14_FIELD_T; ++ unsigned short addr; ++ char *prt1; ++ char *prt2; ++}; + -+#define RG_ESTI_A15 (RF_D_ADDA_ESTI_REG_BASE + 0x3c) -+// Bit 31 :0 rg_esti_cfg2 U RW default = 'h0 -+typedef union RG_ESTI_A15_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_esti_cfg2 : 32; -+ } b; -+} RG_ESTI_A15_FIELD_T; -+ -+#define RG_ESTI_A16 (RF_D_ADDA_ESTI_REG_BASE + 0x40) -+// Bit 31 :0 rg_esti_cfg3 U RW default = 'h0 -+typedef union RG_ESTI_A16_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_esti_cfg3 : 32; -+ } b; -+} RG_ESTI_A16_FIELD_T; -+ -+#define RG_ESTI_A17 (RF_D_ADDA_ESTI_REG_BASE + 0x44) -+// Bit 6 :0 ro_dcoc_code_i U RO default = 'h0 -+// Bit 14 :8 ro_dcoc_code_q U RO default = 'h0 -+// Bit 16 ro_dcoc_code_ready U RO default = 'h0 -+// Bit 24 ro_dcoc_finish U RO default = 'h0 -+// Bit 28 rg_dcoc_read_response_bypass U RW default = 'h0 -+// Bit 31 rg_dcoc_read_response U RW default = 'h0 -+typedef union RG_ESTI_A17_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_dcoc_code_i : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int ro_dcoc_code_q : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int ro_dcoc_code_ready : 1; -+ unsigned int rsvd_2 : 7; -+ unsigned int ro_dcoc_finish : 1; -+ unsigned int rsvd_3 : 3; -+ unsigned int rg_dcoc_read_response_bypass : 1; -+ unsigned int rsvd_4 : 2; -+ unsigned int rg_dcoc_read_response : 1; -+ } b; -+} RG_ESTI_A17_FIELD_T; -+ -+#define RG_ESTI_A18 (RF_D_ADDA_ESTI_REG_BASE + 0x48) -+// Bit 3 :0 ro_lnatank_esti_code U RO default = 'h0 -+// Bit 8 ro_lnatank_esti_code_ready U RO default = 'h0 -+// Bit 16 ro_lnatank_esti_finish U RO default = 'h0 -+// Bit 28 rg_lnatank_read_response_bypass U RW default = 'h0 -+// Bit 31 rg_lnatank_read_response U RW default = 'h0 -+typedef union RG_ESTI_A18_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_lnatank_esti_code : 4; -+ unsigned int rsvd_0 : 4; -+ unsigned int ro_lnatank_esti_code_ready : 1; -+ unsigned int rsvd_1 : 7; -+ unsigned int ro_lnatank_esti_finish : 1; -+ unsigned int rsvd_2 : 11; -+ unsigned int rg_lnatank_read_response_bypass : 1; -+ unsigned int rsvd_3 : 2; -+ unsigned int rg_lnatank_read_response : 1; -+ } b; -+} RG_ESTI_A18_FIELD_T; -+ -+#define RG_ESTI_A19 (RF_D_ADDA_ESTI_REG_BASE + 0x4c) -+// Bit 7 :0 ro_txirr_dc_i U RO default = 'h0 -+// Bit 19 :12 ro_txirr_dc_q U RO default = 'h0 -+// Bit 24 ro_txirr_dc_ready U RO default = 'h0 -+// Bit 25 ro_txirr_code_ready U RO default = 'h0 -+// Bit 26 ro_txirr_mode_ready U RO default = 'h0 -+// Bit 28 rg_txirr_code_continue U RW default = 'h0 -+// Bit 29 rg_txirr_code_continue_bypass U RW default = 'h1 -+// Bit 30 rg_txirr_mode_continue U RW default = 'h0 -+// Bit 31 rg_txirr_mode_continue_bypass U RW default = 'h1 -+typedef union RG_ESTI_A19_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txirr_dc_i : 8; -+ unsigned int rsvd_0 : 4; -+ unsigned int ro_txirr_dc_q : 8; -+ unsigned int rsvd_1 : 4; -+ unsigned int ro_txirr_dc_ready : 1; -+ unsigned int ro_txirr_code_ready : 1; -+ unsigned int ro_txirr_mode_ready : 1; -+ unsigned int rsvd_2 : 1; -+ unsigned int rg_txirr_code_continue : 1; -+ unsigned int rg_txirr_code_continue_bypass : 1; -+ unsigned int rg_txirr_mode_continue : 1; -+ unsigned int rg_txirr_mode_continue_bypass : 1; -+ } b; -+} RG_ESTI_A19_FIELD_T; -+ -+#define RG_ESTI_A20 (RF_D_ADDA_ESTI_REG_BASE + 0x50) -+// Bit 7 :0 ro_txirr_alpha U RO default = 'h0 -+// Bit 19 :12 ro_txirr_theta U RO default = 'h0 -+// Bit 24 ro_txirr_irr_ready U RO default = 'h0 -+// Bit 28 rg_txirr_read_response_bypass U RW default = 'h0 -+// Bit 31 rg_txirr_read_response U RW default = 'h0 -+typedef union RG_ESTI_A20_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txirr_alpha : 8; -+ unsigned int rsvd_0 : 4; -+ unsigned int ro_txirr_theta : 8; -+ unsigned int rsvd_1 : 4; -+ unsigned int ro_txirr_irr_ready : 1; -+ unsigned int rsvd_2 : 3; -+ unsigned int rg_txirr_read_response_bypass : 1; -+ unsigned int rsvd_3 : 2; -+ unsigned int rg_txirr_read_response : 1; -+ } b; -+} RG_ESTI_A20_FIELD_T; -+ -+#define RG_ESTI_A21 (RF_D_ADDA_ESTI_REG_BASE + 0x54) -+// Bit 7 :0 rg_tx_dcmax_i U RW default = 'h33 -+// Bit 15 :8 rg_tx_dcmax_q U RW default = 'h33 -+// Bit 23 :16 rg_tx_alpha_max U RW default = 'h7b -+// Bit 31 :24 rg_tx_theta_max U RW default = 'h6b -+typedef union RG_ESTI_A21_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_dcmax_i : 8; -+ unsigned int rg_tx_dcmax_q : 8; -+ unsigned int rg_tx_alpha_max : 8; -+ unsigned int rg_tx_theta_max : 8; -+ } b; -+} RG_ESTI_A21_FIELD_T; -+ -+#define RG_ESTI_A22 (RF_D_ADDA_ESTI_REG_BASE + 0x58) -+// Bit 7 :0 rg_tx_dcmin_i U RW default = 'hcd -+// Bit 15 :8 rg_tx_dcmin_q U RW default = 'hcd -+// Bit 23 :16 rg_tx_alpha_min U RW default = 'h85 -+// Bit 31 :24 rg_tx_theta_min U RW default = 'h95 -+typedef union RG_ESTI_A22_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_dcmin_i : 8; -+ unsigned int rg_tx_dcmin_q : 8; -+ unsigned int rg_tx_alpha_min : 8; -+ unsigned int rg_tx_theta_min : 8; -+ } b; -+} RG_ESTI_A22_FIELD_T; -+ -+#define RG_ESTI_A23 (RF_D_ADDA_ESTI_REG_BASE + 0x5c) -+// Bit 3 :0 rg_tx_dc_i_step U RW default = 'h5 -+// Bit 7 :4 rg_tx_dc_q_step U RW default = 'h5 -+// Bit 11 :8 rg_tx_alpha_step U RW default = 'h3 -+// Bit 15 :12 rg_tx_theta_step U RW default = 'h4 -+// Bit 19 :16 rg_txirr_oper_bnd U RW default = 'h1 -+typedef union RG_ESTI_A23_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_dc_i_step : 4; -+ unsigned int rg_tx_dc_q_step : 4; -+ unsigned int rg_tx_alpha_step : 4; -+ unsigned int rg_tx_theta_step : 4; -+ unsigned int rg_txirr_oper_bnd : 4; -+ unsigned int rsvd_0 : 12; -+ } b; -+} RG_ESTI_A23_FIELD_T; -+ -+#define RG_ESTI_A24 (RF_D_ADDA_ESTI_REG_BASE + 0x60) -+// Bit 24 :0 rg_spectrum_ana_angle_dcoc U RW default = 'h0 -+typedef union RG_ESTI_A24_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_spectrum_ana_angle_dcoc : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_ESTI_A24_FIELD_T; -+ -+#define RG_ESTI_A25 (RF_D_ADDA_ESTI_REG_BASE + 0x64) -+// Bit 24 :0 rg_spectrum_ana_angle_lna U RW default = 'h1f99999 -+typedef union RG_ESTI_A25_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_spectrum_ana_angle_lna : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_ESTI_A25_FIELD_T; -+ -+#define RG_ESTI_A26 (RF_D_ADDA_ESTI_REG_BASE + 0x68) -+// Bit 24 :0 rg_spectrum_ana_angle_txirr U RW default = 'h1c00000 -+typedef union RG_ESTI_A26_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_spectrum_ana_angle_txirr : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_ESTI_A26_FIELD_T; -+ -+#define RG_ESTI_A27 (RF_D_ADDA_ESTI_REG_BASE + 0x6c) -+// Bit 24 :0 rg_spectrum_ana_angle_txdc U RW default = 'h1e00000 -+typedef union RG_ESTI_A27_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_spectrum_ana_angle_txdc : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_ESTI_A27_FIELD_T; -+ -+#define RG_ESTI_A28 (RF_D_ADDA_ESTI_REG_BASE + 0x70) -+// Bit 24 :0 rg_spectrum_ana_angle_dpd U RW default = 'h0 -+typedef union RG_ESTI_A28_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_spectrum_ana_angle_dpd : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_ESTI_A28_FIELD_T; -+ -+#define RG_ESTI_A29 (RF_D_ADDA_ESTI_REG_BASE + 0x74) -+// Bit 24 :0 rg_spectrum_ana_angle_pwc U RW default = 'h0 -+typedef union RG_ESTI_A29_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_spectrum_ana_angle_pwc : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_ESTI_A29_FIELD_T; -+ -+#define RG_ESTI_A30 (RF_D_ADDA_ESTI_REG_BASE + 0x78) -+// Bit 24 :0 rg_irr_tone_freq_0 U RW default = 'h4ccccc -+typedef union RG_ESTI_A30_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_tone_freq_0 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_ESTI_A30_FIELD_T; -+ -+#define RG_ESTI_A31 (RF_D_ADDA_ESTI_REG_BASE + 0x7c) -+// Bit 24 :0 rg_irr_tone_freq_1 U RW default = 'ha66666 -+typedef union RG_ESTI_A31_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_tone_freq_1 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_ESTI_A31_FIELD_T; -+ -+#define RG_ESTI_A32 (RF_D_ADDA_ESTI_REG_BASE + 0x80) -+// Bit 24 :0 rg_irr_tone_freq_2 U RW default = 'hd33333 -+typedef union RG_ESTI_A32_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_tone_freq_2 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_ESTI_A32_FIELD_T; -+ -+#define RG_ESTI_A33 (RF_D_ADDA_ESTI_REG_BASE + 0x84) -+// Bit 24 :0 rg_irr_tone_freq_3 U RW default = 'hf99999 -+typedef union RG_ESTI_A33_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_tone_freq_3 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_ESTI_A33_FIELD_T; -+ -+#define RG_ESTI_A34 (RF_D_ADDA_ESTI_REG_BASE + 0x88) -+// Bit 24 :0 rg_irr_tone_freq_4 U RW default = 'h1066666 -+typedef union RG_ESTI_A34_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_tone_freq_4 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_ESTI_A34_FIELD_T; -+ -+#define RG_ESTI_A35 (RF_D_ADDA_ESTI_REG_BASE + 0x8c) -+// Bit 24 :0 rg_irr_tone_freq_5 U RW default = 'h12ccccc -+typedef union RG_ESTI_A35_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_tone_freq_5 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_ESTI_A35_FIELD_T; -+ -+#define RG_ESTI_A36 (RF_D_ADDA_ESTI_REG_BASE + 0x90) -+// Bit 24 :0 rg_irr_tone_freq_6 U RW default = 'h1599999 -+typedef union RG_ESTI_A36_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_tone_freq_6 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_ESTI_A36_FIELD_T; -+ -+#define RG_ESTI_A37 (RF_D_ADDA_ESTI_REG_BASE + 0x94) -+// Bit 24 :0 rg_irr_tone_freq_7 U RW default = 'h1b33333 -+typedef union RG_ESTI_A37_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_tone_freq_7 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_ESTI_A37_FIELD_T; -+ -+#define RG_ESTI_A38 (RF_D_ADDA_ESTI_REG_BASE + 0x98) -+// Bit 15 :0 rg_irr_interp_coef_up0 U RW default = 'hf751 -+// Bit 31 :16 rg_irr_interp_coef_up1 U RW default = 'h97e -+typedef union RG_ESTI_A38_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_interp_coef_up0 : 16; -+ unsigned int rg_irr_interp_coef_up1 : 16; -+ } b; -+} RG_ESTI_A38_FIELD_T; -+ -+#define RG_ESTI_A39 (RF_D_ADDA_ESTI_REG_BASE + 0x9c) -+// Bit 15 :0 rg_irr_interp_coef_up2 U RW default = 'hfbb7 -+// Bit 31 :16 rg_irr_interp_coef_up3 U RW default = 'h292 -+typedef union RG_ESTI_A39_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_interp_coef_up2 : 16; -+ unsigned int rg_irr_interp_coef_up3 : 16; -+ } b; -+} RG_ESTI_A39_FIELD_T; -+ -+#define RG_ESTI_A40 (RF_D_ADDA_ESTI_REG_BASE + 0xa0) -+// Bit 15 :0 rg_irr_interp_coef_up4 U RW default = 'h369c -+// Bit 31 :16 rg_irr_interp_coef_up5 U RW default = 'hd196 -+typedef union RG_ESTI_A40_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_interp_coef_up4 : 16; -+ unsigned int rg_irr_interp_coef_up5 : 16; -+ } b; -+} RG_ESTI_A40_FIELD_T; -+ -+#define RG_ESTI_A41 (RF_D_ADDA_ESTI_REG_BASE + 0xa4) -+// Bit 15 :0 rg_irr_interp_coef_up6 U RW default = 'h1ae1 -+// Bit 31 :16 rg_irr_interp_coef_up7 U RW default = 'hf4d1 -+typedef union RG_ESTI_A41_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_interp_coef_up6 : 16; -+ unsigned int rg_irr_interp_coef_up7 : 16; -+ } b; -+} RG_ESTI_A41_FIELD_T; -+ -+#define RG_ESTI_A42 (RF_D_ADDA_ESTI_REG_BASE + 0xa8) -+// Bit 15 :0 rg_irr_interp_coef_up8 U RW default = 'had86 -+// Bit 31 :16 rg_irr_interp_coef_up9 U RW default = 'h4663 -+typedef union RG_ESTI_A42_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_interp_coef_up8 : 16; -+ unsigned int rg_irr_interp_coef_up9 : 16; -+ } b; -+} RG_ESTI_A42_FIELD_T; -+ -+#define RG_ESTI_A43 (RF_D_ADDA_ESTI_REG_BASE + 0xac) -+// Bit 15 :0 rg_irr_interp_coef_upa U RW default = 'hd7c6 -+// Bit 31 :16 rg_irr_interp_coef_upb U RW default = 'hdd8 -+typedef union RG_ESTI_A43_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_interp_coef_upa : 16; -+ unsigned int rg_irr_interp_coef_upb : 16; -+ } b; -+} RG_ESTI_A43_FIELD_T; -+ -+#define RG_ESTI_A44 (RF_D_ADDA_ESTI_REG_BASE + 0xb0) -+// Bit 15 :0 rg_irr_interp_coef_upc U RW default = 'h288d -+// Bit 31 :16 rg_irr_interp_coef_upd U RW default = 'hde88 -+typedef union RG_ESTI_A44_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_interp_coef_upc : 16; -+ unsigned int rg_irr_interp_coef_upd : 16; -+ } b; -+} RG_ESTI_A44_FIELD_T; -+ -+#define RG_ESTI_A45 (RF_D_ADDA_ESTI_REG_BASE + 0xb4) -+// Bit 15 :0 rg_irr_interp_coef_upe U RW default = 'h11a2 -+// Bit 31 :16 rg_irr_interp_coef_upf U RW default = 'hfac5 -+typedef union RG_ESTI_A45_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_interp_coef_upe : 16; -+ unsigned int rg_irr_interp_coef_upf : 16; -+ } b; -+} RG_ESTI_A45_FIELD_T; -+ -+#define RG_ESTI_A46 (RF_D_ADDA_ESTI_REG_BASE + 0xb8) -+// Bit 15 :0 rg_irr_interp_coef_low0 U RW default = 'h288d -+// Bit 31 :16 rg_irr_interp_coef_low1 U RW default = 'hde88 -+typedef union RG_ESTI_A46_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_interp_coef_low0 : 16; -+ unsigned int rg_irr_interp_coef_low1 : 16; -+ } b; -+} RG_ESTI_A46_FIELD_T; -+ -+#define RG_ESTI_A47 (RF_D_ADDA_ESTI_REG_BASE + 0xbc) -+// Bit 15 :0 rg_irr_interp_coef_low2 U RW default = 'h11a2 -+// Bit 31 :16 rg_irr_interp_coef_low3 U RW default = 'hfac5 -+typedef union RG_ESTI_A47_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_interp_coef_low2 : 16; -+ unsigned int rg_irr_interp_coef_low3 : 16; -+ } b; -+} RG_ESTI_A47_FIELD_T; -+ -+#define RG_ESTI_A48 (RF_D_ADDA_ESTI_REG_BASE + 0xc0) -+// Bit 15 :0 rg_irr_interp_coef_low4 U RW default = 'had86 -+// Bit 31 :16 rg_irr_interp_coef_low5 U RW default = 'h4663 -+typedef union RG_ESTI_A48_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_interp_coef_low4 : 16; -+ unsigned int rg_irr_interp_coef_low5 : 16; -+ } b; -+} RG_ESTI_A48_FIELD_T; -+ -+#define RG_ESTI_A49 (RF_D_ADDA_ESTI_REG_BASE + 0xc4) -+// Bit 15 :0 rg_irr_interp_coef_low6 U RW default = 'hd7c6 -+// Bit 31 :16 rg_irr_interp_coef_low7 U RW default = 'hdd8 -+typedef union RG_ESTI_A49_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_interp_coef_low6 : 16; -+ unsigned int rg_irr_interp_coef_low7 : 16; -+ } b; -+} RG_ESTI_A49_FIELD_T; -+ -+#define RG_ESTI_A50 (RF_D_ADDA_ESTI_REG_BASE + 0xc8) -+// Bit 15 :0 rg_irr_interp_coef_low8 U RW default = 'h369c -+// Bit 31 :16 rg_irr_interp_coef_low9 U RW default = 'hd196 -+typedef union RG_ESTI_A50_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_interp_coef_low8 : 16; -+ unsigned int rg_irr_interp_coef_low9 : 16; -+ } b; -+} RG_ESTI_A50_FIELD_T; -+ -+#define RG_ESTI_A51 (RF_D_ADDA_ESTI_REG_BASE + 0xcc) -+// Bit 15 :0 rg_irr_interp_coef_lowa U RW default = 'h1ae1 -+// Bit 31 :16 rg_irr_interp_coef_lowb U RW default = 'hf4d1 -+typedef union RG_ESTI_A51_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_interp_coef_lowa : 16; -+ unsigned int rg_irr_interp_coef_lowb : 16; -+ } b; -+} RG_ESTI_A51_FIELD_T; -+ -+#define RG_ESTI_A52 (RF_D_ADDA_ESTI_REG_BASE + 0xd0) -+// Bit 15 :0 rg_irr_interp_coef_lowc U RW default = 'hf751 -+// Bit 31 :16 rg_irr_interp_coef_lowd U RW default = 'h97e -+typedef union RG_ESTI_A52_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_interp_coef_lowc : 16; -+ unsigned int rg_irr_interp_coef_lowd : 16; -+ } b; -+} RG_ESTI_A52_FIELD_T; -+ -+#define RG_ESTI_A53 (RF_D_ADDA_ESTI_REG_BASE + 0xd4) -+// Bit 15 :0 rg_irr_interp_coef_lowe U RW default = 'hfbb7 -+// Bit 31 :16 rg_irr_interp_coef_lowf U RW default = 'h292 -+typedef union RG_ESTI_A53_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_irr_interp_coef_lowe : 16; -+ unsigned int rg_irr_interp_coef_lowf : 16; -+ } b; -+} RG_ESTI_A53_FIELD_T; -+ -+#define RG_ESTI_A54 (RF_D_ADDA_ESTI_REG_BASE + 0xd8) -+// Bit 3 :0 rg_rxirr_esti_len_avg_0 U RW default = 'h2 -+// Bit 7 :4 rg_rxirr_esti_miu_0 U RW default = 'h0 -+// Bit 15 :8 rg_rxirr_esti_navg_0 U RW default = 'h3 -+// Bit 19 :16 rg_rxirr_esti_len_avg_1 U RW default = 'h3 -+// Bit 23 :20 rg_rxirr_esti_miu_1 U RW default = 'h1 -+// Bit 31 :24 rg_rxirr_esti_navg_1 U RW default = 'h7 -+typedef union RG_ESTI_A54_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_rxirr_esti_len_avg_0 : 4; -+ unsigned int rg_rxirr_esti_miu_0 : 4; -+ unsigned int rg_rxirr_esti_navg_0 : 8; -+ unsigned int rg_rxirr_esti_len_avg_1 : 4; -+ unsigned int rg_rxirr_esti_miu_1 : 4; -+ unsigned int rg_rxirr_esti_navg_1 : 8; -+ } b; -+} RG_ESTI_A54_FIELD_T; -+ -+#define RG_ESTI_A55 (RF_D_ADDA_ESTI_REG_BASE + 0xdc) -+// Bit 3 :0 rg_rxirr_esti_len_avg_2 U RW default = 'h4 -+// Bit 7 :4 rg_rxirr_esti_miu_2 U RW default = 'h2 -+// Bit 15 :8 rg_rxirr_esti_navg_2 U RW default = 'hb -+// Bit 19 :16 rg_rxirr_esti_len_avg_3 U RW default = 'h4 -+// Bit 23 :20 rg_rxirr_esti_miu_3 U RW default = 'h3 -+// Bit 31 :24 rg_rxirr_esti_navg_3 U RW default = 'h13 -+typedef union RG_ESTI_A55_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_rxirr_esti_len_avg_2 : 4; -+ unsigned int rg_rxirr_esti_miu_2 : 4; -+ unsigned int rg_rxirr_esti_navg_2 : 8; -+ unsigned int rg_rxirr_esti_len_avg_3 : 4; -+ unsigned int rg_rxirr_esti_miu_3 : 4; -+ unsigned int rg_rxirr_esti_navg_3 : 8; -+ } b; -+} RG_ESTI_A55_FIELD_T; -+ -+#define RG_ESTI_A56 (RF_D_ADDA_ESTI_REG_BASE + 0xe0) -+// Bit 13 :0 ro_rxirr_interp_e_0 U RO default = 'h0 -+// Bit 29 :16 ro_rxirr_interp_e_1 U RO default = 'h0 -+typedef union RG_ESTI_A56_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rxirr_interp_e_0 : 14; -+ unsigned int rsvd_0 : 2; -+ unsigned int ro_rxirr_interp_e_1 : 14; -+ unsigned int rsvd_1 : 2; -+ } b; -+} RG_ESTI_A56_FIELD_T; -+ -+#define RG_ESTI_A57 (RF_D_ADDA_ESTI_REG_BASE + 0xe4) -+// Bit 13 :0 ro_rxirr_interp_e_2 U RO default = 'h0 -+// Bit 29 :16 ro_rxirr_interp_e_3 U RO default = 'h0 -+typedef union RG_ESTI_A57_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rxirr_interp_e_2 : 14; -+ unsigned int rsvd_0 : 2; -+ unsigned int ro_rxirr_interp_e_3 : 14; -+ unsigned int rsvd_1 : 2; -+ } b; -+} RG_ESTI_A57_FIELD_T; -+ -+#define RG_ESTI_A58 (RF_D_ADDA_ESTI_REG_BASE + 0xe8) -+// Bit 13 :0 ro_rxirr_interp_e_4 U RO default = 'h0 -+// Bit 29 :16 ro_rxirr_interp_e_5 U RO default = 'h0 -+typedef union RG_ESTI_A58_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rxirr_interp_e_4 : 14; -+ unsigned int rsvd_0 : 2; -+ unsigned int ro_rxirr_interp_e_5 : 14; -+ unsigned int rsvd_1 : 2; -+ } b; -+} RG_ESTI_A58_FIELD_T; -+ -+#define RG_ESTI_A59 (RF_D_ADDA_ESTI_REG_BASE + 0xec) -+// Bit 13 :0 ro_rxirr_interp_e_6 U RO default = 'h0 -+// Bit 29 :16 ro_rxirr_interp_e_7 U RO default = 'h0 -+typedef union RG_ESTI_A59_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rxirr_interp_e_6 : 14; -+ unsigned int rsvd_0 : 2; -+ unsigned int ro_rxirr_interp_e_7 : 14; -+ unsigned int rsvd_1 : 2; -+ } b; -+} RG_ESTI_A59_FIELD_T; -+ -+#define RG_ESTI_A60 (RF_D_ADDA_ESTI_REG_BASE + 0xf0) -+// Bit 13 :0 ro_rxirr_interp_p_0 U RO default = 'h0 -+// Bit 29 :16 ro_rxirr_interp_p_1 U RO default = 'h0 -+typedef union RG_ESTI_A60_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rxirr_interp_p_0 : 14; -+ unsigned int rsvd_0 : 2; -+ unsigned int ro_rxirr_interp_p_1 : 14; -+ unsigned int rsvd_1 : 2; -+ } b; -+} RG_ESTI_A60_FIELD_T; -+ -+#define RG_ESTI_A61 (RF_D_ADDA_ESTI_REG_BASE + 0xf4) -+// Bit 13 :0 ro_rxirr_interp_p_2 U RO default = 'h0 -+// Bit 29 :16 ro_rxirr_interp_p_3 U RO default = 'h0 -+typedef union RG_ESTI_A61_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rxirr_interp_p_2 : 14; -+ unsigned int rsvd_0 : 2; -+ unsigned int ro_rxirr_interp_p_3 : 14; -+ unsigned int rsvd_1 : 2; -+ } b; -+} RG_ESTI_A61_FIELD_T; -+ -+#define RG_ESTI_A62 (RF_D_ADDA_ESTI_REG_BASE + 0xf8) -+// Bit 13 :0 ro_rxirr_interp_p_4 U RO default = 'h0 -+// Bit 29 :16 ro_rxirr_interp_p_5 U RO default = 'h0 -+typedef union RG_ESTI_A62_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rxirr_interp_p_4 : 14; -+ unsigned int rsvd_0 : 2; -+ unsigned int ro_rxirr_interp_p_5 : 14; -+ unsigned int rsvd_1 : 2; -+ } b; -+} RG_ESTI_A62_FIELD_T; -+ -+#define RG_ESTI_A63 (RF_D_ADDA_ESTI_REG_BASE + 0xfc) -+// Bit 13 :0 ro_rxirr_interp_p_6 U RO default = 'h0 -+// Bit 29 :16 ro_rxirr_interp_p_7 U RO default = 'h0 -+typedef union RG_ESTI_A63_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rxirr_interp_p_6 : 14; -+ unsigned int rsvd_0 : 2; -+ unsigned int ro_rxirr_interp_p_7 : 14; -+ unsigned int rsvd_1 : 2; -+ } b; -+} RG_ESTI_A63_FIELD_T; -+ -+#define RG_ESTI_A64 (RF_D_ADDA_ESTI_REG_BASE + 0x100) -+// Bit 23 :0 rg_adda_wait_count U RW default = 'h50 -+typedef union RG_ESTI_A64_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_adda_wait_count : 24; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_ESTI_A64_FIELD_T; -+ -+#define RG_ESTI_A65 (RF_D_ADDA_ESTI_REG_BASE + 0x104) -+// Bit 14 :0 rg_adda_calc_count U RW default = 'h50 -+typedef union RG_ESTI_A65_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_adda_calc_count : 15; -+ unsigned int rsvd_0 : 17; -+ } b; -+} RG_ESTI_A65_FIELD_T; -+ -+#define RG_ESTI_A66 (RF_D_ADDA_ESTI_REG_BASE + 0x108) -+// Bit 27 :0 rg_adda_esti_count U RW default = 'h40000 -+typedef union RG_ESTI_A66_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_adda_esti_count : 28; -+ unsigned int rsvd_0 : 4; -+ } b; -+} RG_ESTI_A66_FIELD_T; -+ -+#define RG_ESTI_A67 (RF_D_ADDA_ESTI_REG_BASE + 0x10c) -+// Bit 0 rg_txpwc_read_response U RW default = 'h0 -+// Bit 4 rg_txpwc_read_response_bypass U RW default = 'h1 -+// Bit 16 :8 rg_txpwc_ph U RW default = 'h0 -+// Bit 28 :20 rg_txpwc_pl U RW default = 'h0 -+typedef union RG_ESTI_A67_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txpwc_read_response : 1; -+ unsigned int rsvd_0 : 3; -+ unsigned int rg_txpwc_read_response_bypass : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int rg_txpwc_ph : 9; -+ unsigned int rsvd_2 : 3; -+ unsigned int rg_txpwc_pl : 9; -+ unsigned int rsvd_3 : 3; -+ } b; -+} RG_ESTI_A67_FIELD_T; -+ -+#define RG_ESTI_A68 (RF_D_ADDA_ESTI_REG_BASE + 0x110) -+// Bit 7 :0 rg_txpwc_vh_amp U RW default = 'h0 -+// Bit 15 :8 rg_txpwc_vl_amp U RW default = 'h0 -+// Bit 25 :24 rg_txpwc_dc_cnt U RW default = 'h0 -+typedef union RG_ESTI_A68_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txpwc_vh_amp : 8; -+ unsigned int rg_txpwc_vl_amp : 8; -+ unsigned int rsvd_0 : 8; -+ unsigned int rg_txpwc_dc_cnt : 2; -+ unsigned int rsvd_1 : 6; -+ } b; -+} RG_ESTI_A68_FIELD_T; -+ -+#define RG_ESTI_A69 (RF_D_ADDA_ESTI_REG_BASE + 0x114) -+// Bit 8 :0 ro_txpwc_slope U RO default = 'h0 -+// Bit 26 :12 ro_txpwc_offset U RO default = 'h0 -+// Bit 31 ro_txpwc_ready U RO default = 'h0 -+typedef union RG_ESTI_A69_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txpwc_slope : 9; -+ unsigned int rsvd_0 : 3; -+ unsigned int ro_txpwc_offset : 15; -+ unsigned int rsvd_1 : 4; -+ unsigned int ro_txpwc_ready : 1; -+ } b; -+} RG_ESTI_A69_FIELD_T; -+ -+#define RG_ESTI_A70 (RF_D_ADDA_ESTI_REG_BASE + 0x118) -+// Bit 0 rg_txdpd_esti_read_response U RW default = 'h0 -+// Bit 2 rg_txdpd_esti_read_response_bypass U RW default = 'h0 -+// Bit 11 :4 rg_txdpd_esti_alpha U RW default = 'h33 -+// Bit 18 :12 rg_txdpd_esti_sync_gap U RW default = 'h20 -+// Bit 22 ro_txdpd_esti_ready U RO default = 'h0 -+// Bit 31 :24 rg_txdpd_esti_mp_pow_thresh U RW default = 'h6 -+typedef union RG_ESTI_A70_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_esti_read_response : 1; -+ unsigned int rsvd_0 : 1; -+ unsigned int rg_txdpd_esti_read_response_bypass : 1; -+ unsigned int rsvd_1 : 1; -+ unsigned int rg_txdpd_esti_alpha : 8; -+ unsigned int rg_txdpd_esti_sync_gap : 7; -+ unsigned int rsvd_2 : 3; -+ unsigned int ro_txdpd_esti_ready : 1; -+ unsigned int rsvd_3 : 1; -+ unsigned int rg_txdpd_esti_mp_pow_thresh : 8; -+ } b; -+} RG_ESTI_A70_FIELD_T; -+ -+#define RG_ESTI_A72 (RF_D_ADDA_ESTI_REG_BASE + 0x11c) -+// Bit 11 :0 ro_txdpd_esti_coef_i_0 U RO default = 'h0 -+// Bit 23 :12 ro_txdpd_esti_coef_q_0 U RO default = 'h0 -+typedef union RG_ESTI_A72_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txdpd_esti_coef_i_0 : 12; -+ unsigned int ro_txdpd_esti_coef_q_0 : 12; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_ESTI_A72_FIELD_T; -+ -+#define RG_ESTI_A73 (RF_D_ADDA_ESTI_REG_BASE + 0x120) -+// Bit 11 :0 ro_txdpd_esti_coef_i_1 U RO default = 'h0 -+// Bit 23 :12 ro_txdpd_esti_coef_q_1 U RO default = 'h0 -+typedef union RG_ESTI_A73_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txdpd_esti_coef_i_1 : 12; -+ unsigned int ro_txdpd_esti_coef_q_1 : 12; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_ESTI_A73_FIELD_T; -+ -+#define RG_ESTI_A74 (RF_D_ADDA_ESTI_REG_BASE + 0x124) -+// Bit 11 :0 ro_txdpd_esti_coef_i_2 U RO default = 'h0 -+// Bit 23 :12 ro_txdpd_esti_coef_q_2 U RO default = 'h0 -+typedef union RG_ESTI_A74_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txdpd_esti_coef_i_2 : 12; -+ unsigned int ro_txdpd_esti_coef_q_2 : 12; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_ESTI_A74_FIELD_T; -+ -+#define RG_ESTI_A75 (RF_D_ADDA_ESTI_REG_BASE + 0x128) -+// Bit 11 :0 ro_txdpd_esti_coef_i_3 U RO default = 'h0 -+// Bit 23 :12 ro_txdpd_esti_coef_q_3 U RO default = 'h0 -+typedef union RG_ESTI_A75_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txdpd_esti_coef_i_3 : 12; -+ unsigned int ro_txdpd_esti_coef_q_3 : 12; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_ESTI_A75_FIELD_T; -+ -+#define RG_ESTI_A76 (RF_D_ADDA_ESTI_REG_BASE + 0x12c) -+// Bit 11 :0 ro_txdpd_esti_coef_i_4 U RO default = 'h0 -+// Bit 23 :12 ro_txdpd_esti_coef_q_4 U RO default = 'h0 -+typedef union RG_ESTI_A76_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txdpd_esti_coef_i_4 : 12; -+ unsigned int ro_txdpd_esti_coef_q_4 : 12; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_ESTI_A76_FIELD_T; -+ -+#define RG_ESTI_A77 (RF_D_ADDA_ESTI_REG_BASE + 0x130) -+// Bit 11 :0 ro_txdpd_esti_coef_i_5 U RO default = 'h0 -+// Bit 23 :12 ro_txdpd_esti_coef_q_5 U RO default = 'h0 -+typedef union RG_ESTI_A77_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txdpd_esti_coef_i_5 : 12; -+ unsigned int ro_txdpd_esti_coef_q_5 : 12; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_ESTI_A77_FIELD_T; -+ -+#define RG_ESTI_A78 (RF_D_ADDA_ESTI_REG_BASE + 0x134) -+// Bit 11 :0 ro_txdpd_esti_coef_i_6 U RO default = 'h0 -+// Bit 23 :12 ro_txdpd_esti_coef_q_6 U RO default = 'h0 -+typedef union RG_ESTI_A78_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txdpd_esti_coef_i_6 : 12; -+ unsigned int ro_txdpd_esti_coef_q_6 : 12; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_ESTI_A78_FIELD_T; -+ -+#define RG_ESTI_A79 (RF_D_ADDA_ESTI_REG_BASE + 0x138) -+// Bit 11 :0 ro_txdpd_esti_coef_i_7 U RO default = 'h0 -+// Bit 23 :12 ro_txdpd_esti_coef_q_7 U RO default = 'h0 -+typedef union RG_ESTI_A79_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txdpd_esti_coef_i_7 : 12; -+ unsigned int ro_txdpd_esti_coef_q_7 : 12; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_ESTI_A79_FIELD_T; -+ -+#define RG_ESTI_A80 (RF_D_ADDA_ESTI_REG_BASE + 0x13c) -+// Bit 11 :0 ro_txdpd_esti_coef_i_8 U RO default = 'h0 -+// Bit 23 :12 ro_txdpd_esti_coef_q_8 U RO default = 'h0 -+typedef union RG_ESTI_A80_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txdpd_esti_coef_i_8 : 12; -+ unsigned int ro_txdpd_esti_coef_q_8 : 12; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_ESTI_A80_FIELD_T; -+ -+#define RG_ESTI_A81 (RF_D_ADDA_ESTI_REG_BASE + 0x140) -+// Bit 11 :0 ro_txdpd_esti_coef_i_9 U RO default = 'h0 -+// Bit 23 :12 ro_txdpd_esti_coef_q_9 U RO default = 'h0 -+typedef union RG_ESTI_A81_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txdpd_esti_coef_i_9 : 12; -+ unsigned int ro_txdpd_esti_coef_q_9 : 12; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_ESTI_A81_FIELD_T; -+ -+#define RG_ESTI_A82 (RF_D_ADDA_ESTI_REG_BASE + 0x144) -+// Bit 11 :0 ro_txdpd_esti_coef_i_a U RO default = 'h0 -+// Bit 23 :12 ro_txdpd_esti_coef_q_a U RO default = 'h0 -+typedef union RG_ESTI_A82_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txdpd_esti_coef_i_a : 12; -+ unsigned int ro_txdpd_esti_coef_q_a : 12; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_ESTI_A82_FIELD_T; -+ -+#define RG_ESTI_A83 (RF_D_ADDA_ESTI_REG_BASE + 0x148) -+// Bit 11 :0 ro_txdpd_esti_coef_i_b U RO default = 'h0 -+// Bit 23 :12 ro_txdpd_esti_coef_q_b U RO default = 'h0 -+typedef union RG_ESTI_A83_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txdpd_esti_coef_i_b : 12; -+ unsigned int ro_txdpd_esti_coef_q_b : 12; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_ESTI_A83_FIELD_T; -+ -+#define RG_ESTI_A84 (RF_D_ADDA_ESTI_REG_BASE + 0x14c) -+// Bit 11 :0 ro_txdpd_esti_coef_i_c U RO default = 'h0 -+// Bit 23 :12 ro_txdpd_esti_coef_q_c U RO default = 'h0 -+typedef union RG_ESTI_A84_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txdpd_esti_coef_i_c : 12; -+ unsigned int ro_txdpd_esti_coef_q_c : 12; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_ESTI_A84_FIELD_T; -+ -+#define RG_ESTI_A85 (RF_D_ADDA_ESTI_REG_BASE + 0x150) -+// Bit 11 :0 ro_txdpd_esti_coef_i_d U RO default = 'h0 -+// Bit 23 :12 ro_txdpd_esti_coef_q_d U RO default = 'h0 -+typedef union RG_ESTI_A85_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txdpd_esti_coef_i_d : 12; -+ unsigned int ro_txdpd_esti_coef_q_d : 12; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_ESTI_A85_FIELD_T; -+ -+#define RG_ESTI_A86 (RF_D_ADDA_ESTI_REG_BASE + 0x154) -+// Bit 11 :0 ro_txdpd_esti_coef_i_e U RO default = 'h0 -+// Bit 23 :12 ro_txdpd_esti_coef_q_e U RO default = 'h0 -+typedef union RG_ESTI_A86_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txdpd_esti_coef_i_e : 12; -+ unsigned int ro_txdpd_esti_coef_q_e : 12; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_ESTI_A86_FIELD_T; -+ -+#define RG_ESTI_A87 (RF_D_ADDA_ESTI_REG_BASE + 0x158) -+// Bit 0 rg_snr_esti_en U RW default = 'h1 -+// Bit 6 :4 rg_snr_esti_calctime U RW default = 'h0 -+// Bit 10 :8 rg_snr_alpha U RW default = 'h0 -+// Bit 18 :16 rg_txdpd_snr_esti_alpha U RW default = 'h0 -+typedef union RG_ESTI_A87_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_snr_esti_en : 1; -+ unsigned int rsvd_0 : 3; -+ unsigned int rg_snr_esti_calctime : 3; -+ unsigned int rsvd_1 : 1; -+ unsigned int rg_snr_alpha : 3; -+ unsigned int rsvd_2 : 5; -+ unsigned int rg_txdpd_snr_esti_alpha : 3; -+ unsigned int rsvd_3 : 13; -+ } b; -+} RG_ESTI_A87_FIELD_T; -+ -+#define RG_ESTI_A88 (RF_D_ADDA_ESTI_REG_BASE + 0x15c) -+// Bit 8 :0 ro_adda_snr_db U RO default = 'h0 -+// Bit 12 ro_adda_db_vld U RO default = 'h0 -+// Bit 24 :16 ro_adda_pwr_db U RO default = 'h0 -+typedef union RG_ESTI_A88_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_adda_snr_db : 9; -+ unsigned int rsvd_0 : 3; -+ unsigned int ro_adda_db_vld : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int ro_adda_pwr_db : 9; -+ unsigned int rsvd_2 : 7; -+ } b; -+} RG_ESTI_A88_FIELD_T; -+ -+#define RG_ESTI_A89 (RF_D_ADDA_ESTI_REG_BASE + 0x160) -+// Bit 8 :0 ro_txdpd_esti_snr_db U RO default = 'h0 -+typedef union RG_ESTI_A89_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txdpd_esti_snr_db : 9; -+ unsigned int rsvd_0 : 23; -+ } b; -+} RG_ESTI_A89_FIELD_T; -+ -+#define RG_ESTI_A90 (RF_D_ADDA_ESTI_REG_BASE + 0x164) -+// Bit 29 :0 ro_dcoc_dc_i U RO default = 'h0 -+typedef union RG_ESTI_A90_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_dcoc_dc_i : 30; -+ unsigned int rsvd_0 : 2; -+ } b; -+} RG_ESTI_A90_FIELD_T; -+ -+#define RG_ESTI_A91 (RF_D_ADDA_ESTI_REG_BASE + 0x168) -+// Bit 29 :0 ro_dcoc_dc_q U RO default = 'h0 -+typedef union RG_ESTI_A91_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_dcoc_dc_q : 30; -+ unsigned int rsvd_0 : 2; -+ } b; -+} RG_ESTI_A91_FIELD_T; -+ -+#define RG_ESTI_A92 (RF_D_ADDA_ESTI_REG_BASE + 0x16c) -+// Bit 31 :0 ro_txirr_dc_pow_low U RO default = 'h0 -+typedef union RG_ESTI_A92_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txirr_dc_pow_low : 32; -+ } b; -+} RG_ESTI_A92_FIELD_T; -+ -+#define RG_ESTI_A93 (RF_D_ADDA_ESTI_REG_BASE + 0x170) -+// Bit 22 :0 ro_txirr_dc_pow_high U RO default = 'h0 -+typedef union RG_ESTI_A93_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txirr_dc_pow_high : 23; -+ unsigned int rsvd_0 : 9; -+ } b; -+} RG_ESTI_A93_FIELD_T; -+ -+#define RG_ESTI_A94 (RF_D_ADDA_ESTI_REG_BASE + 0x174) -+// Bit 31 :0 ro_lnatank_esti_pow U RO default = 'h0 -+typedef union RG_ESTI_A94_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_lnatank_esti_pow : 32; -+ } b; -+} RG_ESTI_A94_FIELD_T; -+ -+#define RG_ESTI_A96 (RF_D_ADDA_ESTI_REG_BASE + 0x17c) -+// Bit 11 :0 ro_txdpd_gain U RO default = 'h0 -+typedef union RG_ESTI_A96_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txdpd_gain : 12; -+ unsigned int rsvd_0 : 20; -+ } b; -+} RG_ESTI_A96_FIELD_T; -+ -+#endif -+ -diff --git a/drivers/net/wireless/w1/common/rf_d_adda_recv_reg.h b/drivers/net/wireless/w1/common/rf_d_adda_recv_reg.h -new file mode 100644 -index 000000000000..b5c03e51fcde ---- /dev/null -+++ b/drivers/net/wireless/w1/common/rf_d_adda_recv_reg.h -@@ -0,0 +1,419 @@ -+#ifdef RF_D_ADDA_RECV_REG -+#else -+#define RF_D_ADDA_RECV_REG -+ -+ -+#define RF_D_ADDA_RECV_REG_BASE (0xa0e800) -+ -+#define RG_RECV_A0 (RF_D_ADDA_RECV_REG_BASE + 0x0) -+// Bit 31 :0 rg_recv_cfg0 U RW default = 'h0 -+typedef union RG_RECV_A0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_recv_cfg0 : 32; -+ } b; -+} RG_RECV_A0_FIELD_T; -+ -+#define RG_RECV_A1 (RF_D_ADDA_RECV_REG_BASE + 0x4) -+// Bit 31 :0 rg_recv_cfg1 U RW default = 'h0 -+typedef union RG_RECV_A1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_recv_cfg1 : 32; -+ } b; -+} RG_RECV_A1_FIELD_T; -+ -+#define RG_RECV_A2 (RF_D_ADDA_RECV_REG_BASE + 0x8) -+// Bit 0 rg_rxneg_msb U RW default = 'h0 -+// Bit 1 rg_rxiq_swap U RW default = 'h0 -+// Bit 11 :4 rg_rxi_dcoft U RW default = 'h0 -+// Bit 19 :12 rg_rxq_dcoft U RW default = 'h0 -+// Bit 20 rg_dcloop_bypass U RW default = 'h1 -+// Bit 24 rg_rx_adc_fs U RW default = 'h1 -+// Bit 28 rg_to_agc_en U RW default = 'h0 -+typedef union RG_RECV_A2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_rxneg_msb : 1; -+ unsigned int rg_rxiq_swap : 1; -+ unsigned int rsvd_0 : 2; -+ unsigned int rg_rxi_dcoft : 8; -+ unsigned int rg_rxq_dcoft : 8; -+ unsigned int rg_dcloop_bypass : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int rg_rx_adc_fs : 1; -+ unsigned int rsvd_2 : 3; -+ unsigned int rg_to_agc_en : 1; -+ unsigned int rsvd_3 : 3; -+ } b; -+} RG_RECV_A2_FIELD_T; -+ -+#define RG_RECV_A3 (RF_D_ADDA_RECV_REG_BASE + 0xc) -+// Bit 14 :0 rg_rxirr_eup_0 U RW default = 'h7f51 -+// Bit 30 :16 rg_rxirr_eup_1 U RW default = 'h46 -+typedef union RG_RECV_A3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_rxirr_eup_0 : 15; -+ unsigned int rsvd_0 : 1; -+ unsigned int rg_rxirr_eup_1 : 15; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_RECV_A3_FIELD_T; -+ -+#define RG_RECV_A4 (RF_D_ADDA_RECV_REG_BASE + 0x10) -+// Bit 14 :0 rg_rxirr_eup_2 U RW default = 'h7fb7 -+// Bit 30 :16 rg_rxirr_eup_3 U RW default = 'h17 -+typedef union RG_RECV_A4_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_rxirr_eup_2 : 15; -+ unsigned int rsvd_0 : 1; -+ unsigned int rg_rxirr_eup_3 : 15; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_RECV_A4_FIELD_T; -+ -+#define RG_RECV_A5 (RF_D_ADDA_RECV_REG_BASE + 0x14) -+// Bit 14 :0 rg_rxirr_pup_0 U RW default = 'h5a4 -+// Bit 30 :16 rg_rxirr_pup_1 U RW default = 'h7ff9 -+typedef union RG_RECV_A5_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_rxirr_pup_0 : 15; -+ unsigned int rsvd_0 : 1; -+ unsigned int rg_rxirr_pup_1 : 15; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_RECV_A5_FIELD_T; -+ -+#define RG_RECV_A6 (RF_D_ADDA_RECV_REG_BASE + 0x18) -+// Bit 14 :0 rg_rxirr_pup_2 U RW default = 'h7ff6 -+// Bit 30 :16 rg_rxirr_pup_3 U RW default = 'h7 -+typedef union RG_RECV_A6_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_rxirr_pup_2 : 15; -+ unsigned int rsvd_0 : 1; -+ unsigned int rg_rxirr_pup_3 : 15; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_RECV_A6_FIELD_T; -+ -+#define RG_RECV_A7 (RF_D_ADDA_RECV_REG_BASE + 0x1c) -+// Bit 14 :0 rg_rxirr_elow_0 U RW default = 'h7f7d -+// Bit 30 :16 rg_rxirr_elow_1 U RW default = 'h7fba -+typedef union RG_RECV_A7_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_rxirr_elow_0 : 15; -+ unsigned int rsvd_0 : 1; -+ unsigned int rg_rxirr_elow_1 : 15; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_RECV_A7_FIELD_T; -+ -+#define RG_RECV_A8 (RF_D_ADDA_RECV_REG_BASE + 0x20) -+// Bit 14 :0 rg_rxirr_elow_2 U RW default = 'h46 -+// Bit 30 :16 rg_rxirr_elow_3 U RW default = 'h7feb -+typedef union RG_RECV_A8_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_rxirr_elow_2 : 15; -+ unsigned int rsvd_0 : 1; -+ unsigned int rg_rxirr_elow_3 : 15; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_RECV_A8_FIELD_T; -+ -+#define RG_RECV_A9 (RF_D_ADDA_RECV_REG_BASE + 0x24) -+// Bit 14 :0 rg_rxirr_plow_0 U RW default = 'h5a5 -+// Bit 30 :16 rg_rxirr_plow_1 U RW default = 'h7ffa -+typedef union RG_RECV_A9_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_rxirr_plow_0 : 15; -+ unsigned int rsvd_0 : 1; -+ unsigned int rg_rxirr_plow_1 : 15; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_RECV_A9_FIELD_T; -+ -+#define RG_RECV_A10 (RF_D_ADDA_RECV_REG_BASE + 0x28) -+// Bit 14 :0 rg_rxirr_plow_2 U RW default = 'h7ff3 -+// Bit 30 :16 rg_rxirr_plow_3 U RW default = 'h8 -+typedef union RG_RECV_A10_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_rxirr_plow_2 : 15; -+ unsigned int rsvd_0 : 1; -+ unsigned int rg_rxirr_plow_3 : 15; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_RECV_A10_FIELD_T; -+ -+#define RG_RECV_A11 (RF_D_ADDA_RECV_REG_BASE + 0x2c) -+// Bit 0 rg_rxirr_man_mode U RW default = 'h1 -+// Bit 4 rg_rxirr_bypass U RW default = 'h1 -+// Bit 11 :8 rg_rx_async_wgap U RW default = 'ha -+typedef union RG_RECV_A11_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_rxirr_man_mode : 1; -+ unsigned int rsvd_0 : 3; -+ unsigned int rg_rxirr_bypass : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int rg_rx_async_wgap : 4; -+ unsigned int rsvd_2 : 20; -+ } b; -+} RG_RECV_A11_FIELD_T; -+ -+#define RG_RECV_A12 (RF_D_ADDA_RECV_REG_BASE + 0x30) -+// Bit 24 :0 rg_rxddc_angle U RW default = 'h0 -+// Bit 28 rg_rxddc_phs_reset U RW default = 'h0 -+// Bit 31 rg_rxddc_bypass U RW default = 'h1 -+typedef union RG_RECV_A12_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_rxddc_angle : 25; -+ unsigned int rsvd_0 : 3; -+ unsigned int rg_rxddc_phs_reset : 1; -+ unsigned int rsvd_1 : 2; -+ unsigned int rg_rxddc_bypass : 1; -+ } b; -+} RG_RECV_A12_FIELD_T; -+ -+#define RG_RECV_A13 (RF_D_ADDA_RECV_REG_BASE + 0x34) -+// Bit 8 :0 rg_dc_sub_thr_pow U RW default = 'h74 -+typedef union RG_RECV_A13_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_dc_sub_thr_pow : 9; -+ unsigned int rsvd_0 : 23; -+ } b; -+} RG_RECV_A13_FIELD_T; -+ -+#define RG_RECV_A14 (RF_D_ADDA_RECV_REG_BASE + 0x38) -+// Bit 8 :0 rg_hdmi_sub_thr_pow1 U RW default = 'h70 -+// Bit 20 :12 rg_hdmi_sub_thr_pow2 U RW default = 'h68 -+typedef union RG_RECV_A14_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_hdmi_sub_thr_pow1 : 9; -+ unsigned int rsvd_0 : 3; -+ unsigned int rg_hdmi_sub_thr_pow2 : 9; -+ unsigned int rsvd_1 : 11; -+ } b; -+} RG_RECV_A14_FIELD_T; -+ -+#define RG_RECV_A15 (RF_D_ADDA_RECV_REG_BASE + 0x3c) -+// Bit 8 :0 rg_cw_sub_thr_pow1 U RW default = 'h78 -+// Bit 20 :12 rg_cw_sub_thr_pow2 U RW default = 'h66 -+typedef union RG_RECV_A15_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_cw_sub_thr_pow1 : 9; -+ unsigned int rsvd_0 : 3; -+ unsigned int rg_cw_sub_thr_pow2 : 9; -+ unsigned int rsvd_1 : 11; -+ } b; -+} RG_RECV_A15_FIELD_T; -+ -+#define RG_RECV_A16 (RF_D_ADDA_RECV_REG_BASE + 0x40) -+// Bit 0 rg_cw_remove_sub_man_bypass0 U RW default = 'h0 -+// Bit 1 rg_cw_remove_sub_bypass_man_mode0 U RW default = 'h0 -+// Bit 4 rg_cw_remove_sub_man_bypass1 U RW default = 'h0 -+// Bit 5 rg_cw_remove_sub_bypass_man_mode1 U RW default = 'h0 -+// Bit 8 rg_cw_remove_sub_man_bypass2 U RW default = 'h0 -+// Bit 9 rg_cw_remove_sub_bypass_man_mode2 U RW default = 'h0 -+// Bit 12 rg_cw_remove_sub_man_bypass3 U RW default = 'h0 -+// Bit 13 rg_cw_remove_sub_bypass_man_mode3 U RW default = 'h0 -+// Bit 16 rg_cw_remove_sub_man_bypass4 U RW default = 'h0 -+// Bit 17 rg_cw_remove_sub_bypass_man_mode4 U RW default = 'h0 -+// Bit 20 rg_dc_bypass U RW default = 'h0 -+// Bit 24 rg_hdmi_bypass U RW default = 'h0 -+// Bit 28 rg_cw_bypass U RW default = 'h0 -+// Bit 30 rg_cw_remove_bypass_val U RW default = 'h1 -+// Bit 31 rg_cw_remove_bypass_man U RW default = 'h1 -+typedef union RG_RECV_A16_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_cw_remove_sub_man_bypass0 : 1; -+ unsigned int rg_cw_remove_sub_bypass_man_mode0 : 1; -+ unsigned int rsvd_0 : 2; -+ unsigned int rg_cw_remove_sub_man_bypass1 : 1; -+ unsigned int rg_cw_remove_sub_bypass_man_mode1 : 1; -+ unsigned int rsvd_1 : 2; -+ unsigned int rg_cw_remove_sub_man_bypass2 : 1; -+ unsigned int rg_cw_remove_sub_bypass_man_mode2 : 1; -+ unsigned int rsvd_2 : 2; -+ unsigned int rg_cw_remove_sub_man_bypass3 : 1; -+ unsigned int rg_cw_remove_sub_bypass_man_mode3 : 1; -+ unsigned int rsvd_3 : 2; -+ unsigned int rg_cw_remove_sub_man_bypass4 : 1; -+ unsigned int rg_cw_remove_sub_bypass_man_mode4 : 1; -+ unsigned int rsvd_4 : 2; -+ unsigned int rg_dc_bypass : 1; -+ unsigned int rsvd_5 : 3; -+ unsigned int rg_hdmi_bypass : 1; -+ unsigned int rsvd_6 : 3; -+ unsigned int rg_cw_bypass : 1; -+ unsigned int rsvd_7 : 1; -+ unsigned int rg_cw_remove_bypass_val : 1; -+ unsigned int rg_cw_remove_bypass_man : 1; -+ } b; -+} RG_RECV_A16_FIELD_T; -+ -+#define RG_RECV_A17 (RF_D_ADDA_RECV_REG_BASE + 0x44) -+// Bit 24 :0 rg_cw_remove_sub_angle_base1 U RW default = 'h1d33333 -+typedef union RG_RECV_A17_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_cw_remove_sub_angle_base1 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_RECV_A17_FIELD_T; -+ -+#define RG_RECV_A18 (RF_D_ADDA_RECV_REG_BASE + 0x48) -+// Bit 24 :0 rg_cw_remove_sub_angle_base2 U RW default = 'h800000 -+typedef union RG_RECV_A18_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_cw_remove_sub_angle_base2 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_RECV_A18_FIELD_T; -+ -+#define RG_RECV_A19 (RF_D_ADDA_RECV_REG_BASE + 0x4c) -+// Bit 24 :0 rg_cw_remove_sub_angle_base3 U RW default = 'h1e00000 -+typedef union RG_RECV_A19_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_cw_remove_sub_angle_base3 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_RECV_A19_FIELD_T; -+ -+#define RG_RECV_A20 (RF_D_ADDA_RECV_REG_BASE + 0x50) -+// Bit 24 :0 rg_cw_remove_sub_angle_base4 U RW default = 'he00000 -+typedef union RG_RECV_A20_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_cw_remove_sub_angle_base4 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_RECV_A20_FIELD_T; -+ -+#define RG_RECV_A21 (RF_D_ADDA_RECV_REG_BASE + 0x54) -+// Bit 9 :0 rg_dc_dc_remove_cnt U RW default = 'h3ff -+// Bit 25 :16 rg_hdmi_dc_remove_cnt U RW default = 'h3f -+typedef union RG_RECV_A21_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_dc_dc_remove_cnt : 10; -+ unsigned int rsvd_0 : 6; -+ unsigned int rg_hdmi_dc_remove_cnt : 10; -+ unsigned int rsvd_1 : 6; -+ } b; -+} RG_RECV_A21_FIELD_T; -+ -+#define RG_RECV_A22 (RF_D_ADDA_RECV_REG_BASE + 0x58) -+// Bit 9 :0 rg_cw_dc_remove_cnt U RW default = 'h3f -+typedef union RG_RECV_A22_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_cw_dc_remove_cnt : 10; -+ unsigned int rsvd_0 : 22; -+ } b; -+} RG_RECV_A22_FIELD_T; -+ -+#define RG_RECV_A23 (RF_D_ADDA_RECV_REG_BASE + 0x5c) -+// Bit 0 rg_cali_cw_rmv_bypass U RW default = 'h1 -+// Bit 4 rg_agc_cw_rmv_bypass U RW default = 'h1 -+typedef union RG_RECV_A23_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_cali_cw_rmv_bypass : 1; -+ unsigned int rsvd_0 : 3; -+ unsigned int rg_agc_cw_rmv_bypass : 1; -+ unsigned int rsvd_1 : 27; -+ } b; -+} RG_RECV_A23_FIELD_T; -+ -+#define RG_RECV_A24 (RF_D_ADDA_RECV_REG_BASE + 0x60) -+// Bit 8 :0 rg_cw_remove_gaindb_val U RW default = 'h84 -+// Bit 12 rg_cw_remove_gaindb_man U RW default = 'h0 -+typedef union RG_RECV_A24_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_cw_remove_gaindb_val : 9; -+ unsigned int rsvd_0 : 3; -+ unsigned int rg_cw_remove_gaindb_man : 1; -+ unsigned int rsvd_1 : 19; -+ } b; -+} RG_RECV_A24_FIELD_T; -+ -+#define RG_RECV_A25 (RF_D_ADDA_RECV_REG_BASE + 0x64) -+// Bit 0 rg_rssi_snr_est U RW default = 'h0 -+typedef union RG_RECV_A25_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_rssi_snr_est : 1; -+ unsigned int rsvd_0 : 31; -+ } b; -+} RG_RECV_A25_FIELD_T; -+ -+#endif -+ -diff --git a/drivers/net/wireless/w1/common/rf_d_adda_xmit_reg.h b/drivers/net/wireless/w1/common/rf_d_adda_xmit_reg.h -new file mode 100644 -index 000000000000..b53b647a7958 ---- /dev/null -+++ b/drivers/net/wireless/w1/common/rf_d_adda_xmit_reg.h -@@ -0,0 +1,1583 @@ -+#ifdef RF_D_ADDA_XMIT_REG -+#else -+#define RF_D_ADDA_XMIT_REG -+ -+ -+#define RF_D_ADDA_XMIT_REG_BASE (0xa0e400) -+ -+#define RG_XMIT_A0 (RF_D_ADDA_XMIT_REG_BASE + 0x0) -+// Bit 31 :0 rg_xmit_cfg0 U RW default = 'h0 -+typedef union RG_XMIT_A0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_xmit_cfg0 : 32; -+ } b; -+} RG_XMIT_A0_FIELD_T; -+ -+#define RG_XMIT_A1 (RF_D_ADDA_XMIT_REG_BASE + 0x4) -+// Bit 31 :0 rg_xmit_cfg1 U RW default = 'h0 -+typedef union RG_XMIT_A1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_xmit_cfg1 : 32; -+ } b; -+} RG_XMIT_A1_FIELD_T; -+ -+#define RG_XMIT_A2 (RF_D_ADDA_XMIT_REG_BASE + 0x8) -+// Bit 24 :0 rg_tg1_f_sel U RW default = 'h200000 -+// Bit 28 :25 rg_tg1_tone_gain U RW default = 'h0 -+// Bit 29 rg_tg1_enable U RW default = 'h0 -+// Bit 30 rg_tg1_tone_40 U RW default = 'h0 -+// Bit 31 rg_tg1_tone_man_en U RW default = 'h1 -+typedef union RG_XMIT_A2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tg1_f_sel : 25; -+ unsigned int rg_tg1_tone_gain : 4; -+ unsigned int rg_tg1_enable : 1; -+ unsigned int rg_tg1_tone_40 : 1; -+ unsigned int rg_tg1_tone_man_en : 1; -+ } b; -+} RG_XMIT_A2_FIELD_T; -+ -+#define RG_XMIT_A3 (RF_D_ADDA_XMIT_REG_BASE + 0xc) -+// Bit 24 :0 rg_tg2_f_sel U RW default = 'h200000 -+// Bit 28 :25 rg_tg2_tone_gain U RW default = 'h0 -+// Bit 29 rg_tg2_enable U RW default = 'h0 -+// Bit 30 rg_tg2_tone_40 U RW default = 'h0 -+// Bit 31 rg_tg2_tone_man_en U RW default = 'h1 -+typedef union RG_XMIT_A3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tg2_f_sel : 25; -+ unsigned int rg_tg2_tone_gain : 4; -+ unsigned int rg_tg2_enable : 1; -+ unsigned int rg_tg2_tone_40 : 1; -+ unsigned int rg_tg2_tone_man_en : 1; -+ } b; -+} RG_XMIT_A3_FIELD_T; -+ -+#define RG_XMIT_A4 (RF_D_ADDA_XMIT_REG_BASE + 0x10) -+// Bit 1 :0 rg_tx_signal_sel U RW default = 'h0 -+// Bit 14 :4 rg_tx_const_i U RW default = 'h0 -+// Bit 26 :16 rg_tx_const_q U RW default = 'h0 -+// Bit 31 rg_tx_const_v U RW default = 'h0 -+typedef union RG_XMIT_A4_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_signal_sel : 2; -+ unsigned int rsvd_0 : 2; -+ unsigned int rg_tx_const_i : 11; -+ unsigned int rsvd_1 : 1; -+ unsigned int rg_tx_const_q : 11; -+ unsigned int rsvd_2 : 4; -+ unsigned int rg_tx_const_v : 1; -+ } b; -+} RG_XMIT_A4_FIELD_T; -+ -+#define RG_XMIT_A5 (RF_D_ADDA_XMIT_REG_BASE + 0x14) -+// Bit 31 :0 rg_tim_ratio U RW default = 'h0 -+typedef union RG_XMIT_A5_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tim_ratio : 32; -+ } b; -+} RG_XMIT_A5_FIELD_T; -+ -+#define RG_XMIT_A6 (RF_D_ADDA_XMIT_REG_BASE + 0x18) -+// Bit 7 :0 rg_txirr_comp_theta0 U RW default = 'h0 -+// Bit 15 :8 rg_txirr_comp_theta1 U RW default = 'h0 -+// Bit 23 :16 rg_txirr_comp_theta2 U RW default = 'h0 -+// Bit 31 :24 rg_txirr_comp_theta3 U RW default = 'h0 -+typedef union RG_XMIT_A6_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txirr_comp_theta0 : 8; -+ unsigned int rg_txirr_comp_theta1 : 8; -+ unsigned int rg_txirr_comp_theta2 : 8; -+ unsigned int rg_txirr_comp_theta3 : 8; -+ } b; -+} RG_XMIT_A6_FIELD_T; -+ -+#define RG_XMIT_A7 (RF_D_ADDA_XMIT_REG_BASE + 0x1c) -+// Bit 7 :0 rg_txirr_comp_theta4 U RW default = 'h0 -+// Bit 15 :8 rg_txirr_comp_theta5 U RW default = 'h0 -+// Bit 23 :16 rg_txirr_comp_theta6 U RW default = 'h0 -+// Bit 31 :24 rg_txirr_comp_theta7 U RW default = 'h0 -+typedef union RG_XMIT_A7_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txirr_comp_theta4 : 8; -+ unsigned int rg_txirr_comp_theta5 : 8; -+ unsigned int rg_txirr_comp_theta6 : 8; -+ unsigned int rg_txirr_comp_theta7 : 8; -+ } b; -+} RG_XMIT_A7_FIELD_T; -+ -+#define RG_XMIT_A8 (RF_D_ADDA_XMIT_REG_BASE + 0x20) -+// Bit 7 :0 rg_txirr_comp_theta8 U RW default = 'h0 -+// Bit 15 :8 rg_txirr_comp_theta9 U RW default = 'h0 -+// Bit 23 :16 rg_txirr_comp_thetaa U RW default = 'h0 -+// Bit 31 :24 rg_txirr_comp_thetab U RW default = 'h0 -+typedef union RG_XMIT_A8_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txirr_comp_theta8 : 8; -+ unsigned int rg_txirr_comp_theta9 : 8; -+ unsigned int rg_txirr_comp_thetaa : 8; -+ unsigned int rg_txirr_comp_thetab : 8; -+ } b; -+} RG_XMIT_A8_FIELD_T; -+ -+#define RG_XMIT_A9 (RF_D_ADDA_XMIT_REG_BASE + 0x24) -+// Bit 7 :0 rg_txirr_comp_thetac U RW default = 'h0 -+// Bit 15 :8 rg_txirr_comp_thetad U RW default = 'h0 -+// Bit 23 :16 rg_txirr_comp_thetae U RW default = 'h0 -+// Bit 31 :24 rg_txirr_comp_thetaf U RW default = 'h0 -+typedef union RG_XMIT_A9_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txirr_comp_thetac : 8; -+ unsigned int rg_txirr_comp_thetad : 8; -+ unsigned int rg_txirr_comp_thetae : 8; -+ unsigned int rg_txirr_comp_thetaf : 8; -+ } b; -+} RG_XMIT_A9_FIELD_T; -+ -+#define RG_XMIT_A10 (RF_D_ADDA_XMIT_REG_BASE + 0x28) -+// Bit 7 :0 rg_txirr_comp_alpha0 U RW default = 'h0 -+// Bit 15 :8 rg_txirr_comp_alpha1 U RW default = 'h0 -+// Bit 23 :16 rg_txirr_comp_alpha2 U RW default = 'h0 -+// Bit 31 :24 rg_txirr_comp_alpha3 U RW default = 'h0 -+typedef union RG_XMIT_A10_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txirr_comp_alpha0 : 8; -+ unsigned int rg_txirr_comp_alpha1 : 8; -+ unsigned int rg_txirr_comp_alpha2 : 8; -+ unsigned int rg_txirr_comp_alpha3 : 8; -+ } b; -+} RG_XMIT_A10_FIELD_T; -+ -+#define RG_XMIT_A11 (RF_D_ADDA_XMIT_REG_BASE + 0x2c) -+// Bit 7 :0 rg_txirr_comp_alpha4 U RW default = 'h0 -+// Bit 15 :8 rg_txirr_comp_alpha5 U RW default = 'h0 -+// Bit 23 :16 rg_txirr_comp_alpha6 U RW default = 'h0 -+// Bit 31 :24 rg_txirr_comp_alpha7 U RW default = 'h0 -+typedef union RG_XMIT_A11_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txirr_comp_alpha4 : 8; -+ unsigned int rg_txirr_comp_alpha5 : 8; -+ unsigned int rg_txirr_comp_alpha6 : 8; -+ unsigned int rg_txirr_comp_alpha7 : 8; -+ } b; -+} RG_XMIT_A11_FIELD_T; -+ -+#define RG_XMIT_A12 (RF_D_ADDA_XMIT_REG_BASE + 0x30) -+// Bit 7 :0 rg_txirr_comp_alpha8 U RW default = 'h0 -+// Bit 15 :8 rg_txirr_comp_alpha9 U RW default = 'h0 -+// Bit 23 :16 rg_txirr_comp_alphaa U RW default = 'h0 -+// Bit 31 :24 rg_txirr_comp_alphab U RW default = 'h0 -+typedef union RG_XMIT_A12_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txirr_comp_alpha8 : 8; -+ unsigned int rg_txirr_comp_alpha9 : 8; -+ unsigned int rg_txirr_comp_alphaa : 8; -+ unsigned int rg_txirr_comp_alphab : 8; -+ } b; -+} RG_XMIT_A12_FIELD_T; -+ -+#define RG_XMIT_A13 (RF_D_ADDA_XMIT_REG_BASE + 0x34) -+// Bit 7 :0 rg_txirr_comp_alphac U RW default = 'h0 -+// Bit 15 :8 rg_txirr_comp_alphad U RW default = 'h0 -+// Bit 23 :16 rg_txirr_comp_alphae U RW default = 'h0 -+// Bit 31 :24 rg_txirr_comp_alphaf U RW default = 'h0 -+typedef union RG_XMIT_A13_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txirr_comp_alphac : 8; -+ unsigned int rg_txirr_comp_alphad : 8; -+ unsigned int rg_txirr_comp_alphae : 8; -+ unsigned int rg_txirr_comp_alphaf : 8; -+ } b; -+} RG_XMIT_A13_FIELD_T; -+ -+#define RG_XMIT_A18 (RF_D_ADDA_XMIT_REG_BASE + 0x48) -+// Bit 24 :0 rg_tx_pwrlvl0 U RW default = 'h800000 -+typedef union RG_XMIT_A18_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_pwrlvl0 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_XMIT_A18_FIELD_T; -+ -+#define RG_XMIT_A19 (RF_D_ADDA_XMIT_REG_BASE + 0x4c) -+// Bit 24 :0 rg_tx_pwrlvl1 U RW default = 'h800000 -+typedef union RG_XMIT_A19_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_pwrlvl1 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_XMIT_A19_FIELD_T; -+ -+#define RG_XMIT_A20 (RF_D_ADDA_XMIT_REG_BASE + 0x50) -+// Bit 24 :0 rg_tx_pwrlvl2 U RW default = 'h800000 -+typedef union RG_XMIT_A20_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_pwrlvl2 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_XMIT_A20_FIELD_T; -+ -+#define RG_XMIT_A21 (RF_D_ADDA_XMIT_REG_BASE + 0x54) -+// Bit 24 :0 rg_tx_pwrlvl3 U RW default = 'h800000 -+typedef union RG_XMIT_A21_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_pwrlvl3 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_XMIT_A21_FIELD_T; -+ -+#define RG_XMIT_A22 (RF_D_ADDA_XMIT_REG_BASE + 0x58) -+// Bit 24 :0 rg_tx_pwrlvl4 U RW default = 'h800000 -+typedef union RG_XMIT_A22_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_pwrlvl4 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_XMIT_A22_FIELD_T; -+ -+#define RG_XMIT_A23 (RF_D_ADDA_XMIT_REG_BASE + 0x5c) -+// Bit 24 :0 rg_tx_pwrlvl5 U RW default = 'h800000 -+typedef union RG_XMIT_A23_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_pwrlvl5 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_XMIT_A23_FIELD_T; -+ -+#define RG_XMIT_A24 (RF_D_ADDA_XMIT_REG_BASE + 0x60) -+// Bit 24 :0 rg_tx_pwrlvl6 U RW default = 'h800000 -+typedef union RG_XMIT_A24_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_pwrlvl6 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_XMIT_A24_FIELD_T; -+ -+#define RG_XMIT_A25 (RF_D_ADDA_XMIT_REG_BASE + 0x64) -+// Bit 24 :0 rg_tx_pwrlvl7 U RW default = 'h800000 -+typedef union RG_XMIT_A25_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_pwrlvl7 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_XMIT_A25_FIELD_T; -+ -+#define RG_XMIT_A26 (RF_D_ADDA_XMIT_REG_BASE + 0x68) -+// Bit 24 :0 rg_tx_pwrlvl8 U RW default = 'h800000 -+typedef union RG_XMIT_A26_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_pwrlvl8 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_XMIT_A26_FIELD_T; -+ -+#define RG_XMIT_A27 (RF_D_ADDA_XMIT_REG_BASE + 0x6c) -+// Bit 24 :0 rg_tx_pwrlvl9 U RW default = 'h800000 -+typedef union RG_XMIT_A27_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_pwrlvl9 : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_XMIT_A27_FIELD_T; -+ -+#define RG_XMIT_A28 (RF_D_ADDA_XMIT_REG_BASE + 0x70) -+// Bit 24 :0 rg_tx_pwrlvla U RW default = 'h800000 -+typedef union RG_XMIT_A28_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_pwrlvla : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_XMIT_A28_FIELD_T; -+ -+#define RG_XMIT_A29 (RF_D_ADDA_XMIT_REG_BASE + 0x74) -+// Bit 24 :0 rg_tx_pwrlvlb U RW default = 'h800000 -+typedef union RG_XMIT_A29_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_pwrlvlb : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_XMIT_A29_FIELD_T; -+ -+#define RG_XMIT_A30 (RF_D_ADDA_XMIT_REG_BASE + 0x78) -+// Bit 24 :0 rg_tx_pwrlvlc U RW default = 'h800000 -+typedef union RG_XMIT_A30_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_pwrlvlc : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_XMIT_A30_FIELD_T; -+ -+#define RG_XMIT_A31 (RF_D_ADDA_XMIT_REG_BASE + 0x7c) -+// Bit 24 :0 rg_tx_pwrlvld U RW default = 'h800000 -+typedef union RG_XMIT_A31_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_pwrlvld : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_XMIT_A31_FIELD_T; -+ -+#define RG_XMIT_A32 (RF_D_ADDA_XMIT_REG_BASE + 0x80) -+// Bit 24 :0 rg_tx_pwrlvle U RW default = 'h800000 -+typedef union RG_XMIT_A32_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_pwrlvle : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_XMIT_A32_FIELD_T; -+ -+#define RG_XMIT_A33 (RF_D_ADDA_XMIT_REG_BASE + 0x84) -+// Bit 24 :0 rg_tx_pwrlvlf U RW default = 'h800000 -+typedef union RG_XMIT_A33_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_pwrlvlf : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_XMIT_A33_FIELD_T; -+ -+#define RG_XMIT_A34 (RF_D_ADDA_XMIT_REG_BASE + 0x88) -+// Bit 0 rg_tx_iqmm_bypass U RW default = 'h1 -+// Bit 4 rg_tx_negate_msb U RW default = 'h1 -+// Bit 8 rg_tx_iq_swap U RW default = 'h0 -+// Bit 13 :12 rg_tx_dout_sel U RW default = 'h0 -+// Bit 19 :16 rg_tx_async_wgap U RW default = 'ha -+typedef union RG_XMIT_A34_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_iqmm_bypass : 1; -+ unsigned int rsvd_0 : 3; -+ unsigned int rg_tx_negate_msb : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int rg_tx_iq_swap : 1; -+ unsigned int rsvd_2 : 3; -+ unsigned int rg_tx_dout_sel : 2; -+ unsigned int rsvd_3 : 2; -+ unsigned int rg_tx_async_wgap : 4; -+ unsigned int rsvd_4 : 12; -+ } b; -+} RG_XMIT_A34_FIELD_T; -+ -+#define RG_XMIT_A45 (RF_D_ADDA_XMIT_REG_BASE + 0xb4) -+// Bit 24 :0 rg_man_tx_pwrlvl U RW default = 'h800000 -+// Bit 31 rg_tx_pwr_sel_man_en U RW default = 'h0 -+typedef union RG_XMIT_A45_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_man_tx_pwrlvl : 25; -+ unsigned int rsvd_0 : 6; -+ unsigned int rg_tx_pwr_sel_man_en : 1; -+ } b; -+} RG_XMIT_A45_FIELD_T; -+ -+#define RG_XMIT_A46 (RF_D_ADDA_XMIT_REG_BASE + 0xb8) -+// Bit 7 :0 rg_man_txirr_comp_theta U RW default = 'h0 -+// Bit 15 :8 rg_man_txirr_comp_alpha U RW default = 'h0 -+// Bit 16 rg_txpwc_comp_man_sel U RW default = 'h1 -+// Bit 31 :24 rg_txpwc_comp_man U RW default = 'h80 -+typedef union RG_XMIT_A46_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_man_txirr_comp_theta : 8; -+ unsigned int rg_man_txirr_comp_alpha : 8; -+ unsigned int rg_txpwc_comp_man_sel : 1; -+ unsigned int rsvd_0 : 7; -+ unsigned int rg_txpwc_comp_man : 8; -+ } b; -+} RG_XMIT_A46_FIELD_T; -+ -+#define RG_XMIT_A47 (RF_D_ADDA_XMIT_REG_BASE + 0xbc) -+// Bit 15 :0 rg_tx_ex_gain0 U RW default = 'h9 -+// Bit 31 :16 rg_tx_ex_gain1 U RW default = 'ha -+typedef union RG_XMIT_A47_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_ex_gain0 : 16; -+ unsigned int rg_tx_ex_gain1 : 16; -+ } b; -+} RG_XMIT_A47_FIELD_T; -+ -+#define RG_XMIT_A48 (RF_D_ADDA_XMIT_REG_BASE + 0xd0) -+// Bit 15 :0 rg_tx_ex_gain2 U RW default = 'h9 -+// Bit 31 :16 rg_tx_ex_gain3 U RW default = 'ha -+typedef union RG_XMIT_A48_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_ex_gain2 : 16; -+ unsigned int rg_tx_ex_gain3 : 16; -+ } b; -+} RG_XMIT_A48_FIELD_T; -+ -+#define RG_XMIT_A49 (RF_D_ADDA_XMIT_REG_BASE + 0xd4) -+// Bit 15 :0 rg_tx_ex_gain4 U RW default = 'h9 -+// Bit 31 :16 rg_tx_ex_gain5 U RW default = 'ha -+typedef union RG_XMIT_A49_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_ex_gain4 : 16; -+ unsigned int rg_tx_ex_gain5 : 16; -+ } b; -+} RG_XMIT_A49_FIELD_T; -+ -+#define RG_XMIT_A50 (RF_D_ADDA_XMIT_REG_BASE + 0xd8) -+// Bit 15 :0 rg_tx_ex_gain6 U RW default = 'h9 -+// Bit 31 :16 rg_tx_ex_gain7 U RW default = 'ha -+typedef union RG_XMIT_A50_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_ex_gain6 : 16; -+ unsigned int rg_tx_ex_gain7 : 16; -+ } b; -+} RG_XMIT_A50_FIELD_T; -+ -+#define RG_XMIT_A51 (RF_D_ADDA_XMIT_REG_BASE + 0xdc) -+// Bit 15 :0 rg_tx_ex_gain8 U RW default = 'h9 -+// Bit 31 :16 rg_tx_ex_gain9 U RW default = 'ha -+typedef union RG_XMIT_A51_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_ex_gain8 : 16; -+ unsigned int rg_tx_ex_gain9 : 16; -+ } b; -+} RG_XMIT_A51_FIELD_T; -+ -+#define RG_XMIT_A52 (RF_D_ADDA_XMIT_REG_BASE + 0xe0) -+// Bit 15 :0 rg_tx_ex_gaina U RW default = 'h9 -+// Bit 31 :16 rg_tx_ex_gainb U RW default = 'ha -+typedef union RG_XMIT_A52_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_ex_gaina : 16; -+ unsigned int rg_tx_ex_gainb : 16; -+ } b; -+} RG_XMIT_A52_FIELD_T; -+ -+#define RG_XMIT_A53 (RF_D_ADDA_XMIT_REG_BASE + 0xe4) -+// Bit 15 :0 rg_tx_ex_gainc U RW default = 'h9 -+// Bit 31 :16 rg_tx_ex_gaind U RW default = 'ha -+typedef union RG_XMIT_A53_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_ex_gainc : 16; -+ unsigned int rg_tx_ex_gaind : 16; -+ } b; -+} RG_XMIT_A53_FIELD_T; -+ -+#define RG_XMIT_A54 (RF_D_ADDA_XMIT_REG_BASE + 0xe8) -+// Bit 15 :0 rg_tx_ex_gaine U RW default = 'h9 -+// Bit 31 :16 rg_tx_ex_gainf U RW default = 'ha -+typedef union RG_XMIT_A54_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_ex_gaine : 16; -+ unsigned int rg_tx_ex_gainf : 16; -+ } b; -+} RG_XMIT_A54_FIELD_T; -+ -+#define RG_XMIT_A55 (RF_D_ADDA_XMIT_REG_BASE + 0xec) -+// Bit 15 :0 rg_tx_gain U RW default = 'h0 -+// Bit 16 rg_tx_set U RW default = 'h0 -+typedef union RG_XMIT_A55_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_gain : 16; -+ unsigned int rg_tx_set : 1; -+ unsigned int rsvd_0 : 15; -+ } b; -+} RG_XMIT_A55_FIELD_T; -+ -+#define RG_XMIT_A56 (RF_D_ADDA_XMIT_REG_BASE + 0xf0) -+// Bit 7 :0 rg_txdpd_comp_in_gain U RW default = 'h80 -+// Bit 18 :8 rg_txdpd_comp_out_gain U RW default = 'h80 -+// Bit 24 rg_txdpd_comp_type U RW default = 'h1 -+// Bit 26 rg_txdpd_comp_bypass U RW default = 'h1 -+// Bit 28 rg_txdpd_comp_bypass_man U RW default = 'h1 -+// Bit 31 rg_txdpd_comp_coef_man_sel U RW default = 'h0 -+typedef union RG_XMIT_A56_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_in_gain : 8; -+ unsigned int rg_txdpd_comp_out_gain : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_type : 1; -+ unsigned int rsvd_1 : 1; -+ unsigned int rg_txdpd_comp_bypass : 1; -+ unsigned int rsvd_2 : 1; -+ unsigned int rg_txdpd_comp_bypass_man : 1; -+ unsigned int rsvd_3 : 2; -+ unsigned int rg_txdpd_comp_coef_man_sel : 1; -+ } b; -+} RG_XMIT_A56_FIELD_T; -+ -+#define RG_XMIT_A57 (RF_D_ADDA_XMIT_REG_BASE + 0xf4) -+// Bit 11 :0 rg_txdpd_comp_coef_i_0_man U RW default = 'hff9 -+// Bit 27 :16 rg_txdpd_comp_coef_q_0_man U RW default = 'h46 -+typedef union RG_XMIT_A57_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_coef_i_0_man : 12; -+ unsigned int rsvd_0 : 4; -+ unsigned int rg_txdpd_comp_coef_q_0_man : 12; -+ unsigned int rsvd_1 : 4; -+ } b; -+} RG_XMIT_A57_FIELD_T; -+ -+#define RG_XMIT_A58 (RF_D_ADDA_XMIT_REG_BASE + 0xf8) -+// Bit 11 :0 rg_txdpd_comp_coef_i_1_man U RW default = 'hff8 -+// Bit 27 :16 rg_txdpd_comp_coef_q_1_man U RW default = 'h13 -+typedef union RG_XMIT_A58_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_coef_i_1_man : 12; -+ unsigned int rsvd_0 : 4; -+ unsigned int rg_txdpd_comp_coef_q_1_man : 12; -+ unsigned int rsvd_1 : 4; -+ } b; -+} RG_XMIT_A58_FIELD_T; -+ -+#define RG_XMIT_A59 (RF_D_ADDA_XMIT_REG_BASE + 0xfc) -+// Bit 11 :0 rg_txdpd_comp_coef_i_2_man U RW default = 'h10 -+// Bit 27 :16 rg_txdpd_comp_coef_q_2_man U RW default = 'h8 -+typedef union RG_XMIT_A59_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_coef_i_2_man : 12; -+ unsigned int rsvd_0 : 4; -+ unsigned int rg_txdpd_comp_coef_q_2_man : 12; -+ unsigned int rsvd_1 : 4; -+ } b; -+} RG_XMIT_A59_FIELD_T; -+ -+#define RG_XMIT_A60 (RF_D_ADDA_XMIT_REG_BASE + 0x100) -+// Bit 11 :0 rg_txdpd_comp_coef_i_3_man U RW default = 'he -+// Bit 27 :16 rg_txdpd_comp_coef_q_3_man U RW default = 'h93 -+typedef union RG_XMIT_A60_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_coef_i_3_man : 12; -+ unsigned int rsvd_0 : 4; -+ unsigned int rg_txdpd_comp_coef_q_3_man : 12; -+ unsigned int rsvd_1 : 4; -+ } b; -+} RG_XMIT_A60_FIELD_T; -+ -+#define RG_XMIT_A61 (RF_D_ADDA_XMIT_REG_BASE + 0x104) -+// Bit 11 :0 rg_txdpd_comp_coef_i_4_man U RW default = 'h16 -+// Bit 27 :16 rg_txdpd_comp_coef_q_4_man U RW default = 'h1f -+typedef union RG_XMIT_A61_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_coef_i_4_man : 12; -+ unsigned int rsvd_0 : 4; -+ unsigned int rg_txdpd_comp_coef_q_4_man : 12; -+ unsigned int rsvd_1 : 4; -+ } b; -+} RG_XMIT_A61_FIELD_T; -+ -+#define RG_XMIT_A62 (RF_D_ADDA_XMIT_REG_BASE + 0x108) -+// Bit 11 :0 rg_txdpd_comp_coef_i_5_man U RW default = 'hfe1 -+// Bit 27 :16 rg_txdpd_comp_coef_q_5_man U RW default = 'hff9 -+typedef union RG_XMIT_A62_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_coef_i_5_man : 12; -+ unsigned int rsvd_0 : 4; -+ unsigned int rg_txdpd_comp_coef_q_5_man : 12; -+ unsigned int rsvd_1 : 4; -+ } b; -+} RG_XMIT_A62_FIELD_T; -+ -+#define RG_XMIT_A63 (RF_D_ADDA_XMIT_REG_BASE + 0x10c) -+// Bit 11 :0 rg_txdpd_comp_coef_i_6_man U RW default = 'hf79 -+// Bit 27 :16 rg_txdpd_comp_coef_q_6_man U RW default = 'hc7f -+typedef union RG_XMIT_A63_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_coef_i_6_man : 12; -+ unsigned int rsvd_0 : 4; -+ unsigned int rg_txdpd_comp_coef_q_6_man : 12; -+ unsigned int rsvd_1 : 4; -+ } b; -+} RG_XMIT_A63_FIELD_T; -+ -+#define RG_XMIT_A64 (RF_D_ADDA_XMIT_REG_BASE + 0x110) -+// Bit 11 :0 rg_txdpd_comp_coef_i_7_man U RW default = 'h9 -+// Bit 27 :16 rg_txdpd_comp_coef_q_7_man U RW default = 'hf51 -+typedef union RG_XMIT_A64_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_coef_i_7_man : 12; -+ unsigned int rsvd_0 : 4; -+ unsigned int rg_txdpd_comp_coef_q_7_man : 12; -+ unsigned int rsvd_1 : 4; -+ } b; -+} RG_XMIT_A64_FIELD_T; -+ -+#define RG_XMIT_A65 (RF_D_ADDA_XMIT_REG_BASE + 0x114) -+// Bit 11 :0 rg_txdpd_comp_coef_i_8_man U RW default = 'hff1 -+// Bit 27 :16 rg_txdpd_comp_coef_q_8_man U RW default = 'h27 -+typedef union RG_XMIT_A65_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_coef_i_8_man : 12; -+ unsigned int rsvd_0 : 4; -+ unsigned int rg_txdpd_comp_coef_q_8_man : 12; -+ unsigned int rsvd_1 : 4; -+ } b; -+} RG_XMIT_A65_FIELD_T; -+ -+#define RG_XMIT_A66 (RF_D_ADDA_XMIT_REG_BASE + 0x118) -+// Bit 11 :0 rg_txdpd_comp_coef_i_9_man U RW default = 'hfeb -+// Bit 27 :16 rg_txdpd_comp_coef_q_9_man U RW default = 'hf4d -+typedef union RG_XMIT_A66_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_coef_i_9_man : 12; -+ unsigned int rsvd_0 : 4; -+ unsigned int rg_txdpd_comp_coef_q_9_man : 12; -+ unsigned int rsvd_1 : 4; -+ } b; -+} RG_XMIT_A66_FIELD_T; -+ -+#define RG_XMIT_A67 (RF_D_ADDA_XMIT_REG_BASE + 0x11c) -+// Bit 11 :0 rg_txdpd_comp_coef_i_a_man U RW default = 'h5 -+// Bit 27 :16 rg_txdpd_comp_coef_q_a_man U RW default = 'hfe4 -+typedef union RG_XMIT_A67_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_coef_i_a_man : 12; -+ unsigned int rsvd_0 : 4; -+ unsigned int rg_txdpd_comp_coef_q_a_man : 12; -+ unsigned int rsvd_1 : 4; -+ } b; -+} RG_XMIT_A67_FIELD_T; -+ -+#define RG_XMIT_A68 (RF_D_ADDA_XMIT_REG_BASE + 0x120) -+// Bit 11 :0 rg_txdpd_comp_coef_i_b_man U RW default = 'h6 -+// Bit 27 :16 rg_txdpd_comp_coef_q_b_man U RW default = 'hfee -+typedef union RG_XMIT_A68_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_coef_i_b_man : 12; -+ unsigned int rsvd_0 : 4; -+ unsigned int rg_txdpd_comp_coef_q_b_man : 12; -+ unsigned int rsvd_1 : 4; -+ } b; -+} RG_XMIT_A68_FIELD_T; -+ -+#define RG_XMIT_A69 (RF_D_ADDA_XMIT_REG_BASE + 0x124) -+// Bit 11 :0 rg_txdpd_comp_coef_i_c_man U RW default = 'h17 -+// Bit 27 :16 rg_txdpd_comp_coef_q_c_man U RW default = 'ha3 -+typedef union RG_XMIT_A69_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_coef_i_c_man : 12; -+ unsigned int rsvd_0 : 4; -+ unsigned int rg_txdpd_comp_coef_q_c_man : 12; -+ unsigned int rsvd_1 : 4; -+ } b; -+} RG_XMIT_A69_FIELD_T; -+ -+#define RG_XMIT_A70 (RF_D_ADDA_XMIT_REG_BASE + 0x128) -+// Bit 11 :0 rg_txdpd_comp_coef_i_d_man U RW default = 'hffc -+// Bit 27 :16 rg_txdpd_comp_coef_q_d_man U RW default = 'h16 -+typedef union RG_XMIT_A70_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_coef_i_d_man : 12; -+ unsigned int rsvd_0 : 4; -+ unsigned int rg_txdpd_comp_coef_q_d_man : 12; -+ unsigned int rsvd_1 : 4; -+ } b; -+} RG_XMIT_A70_FIELD_T; -+ -+#define RG_XMIT_A71 (RF_D_ADDA_XMIT_REG_BASE + 0x12c) -+// Bit 11 :0 rg_txdpd_comp_coef_i_e_man U RW default = 'hfff -+// Bit 27 :16 rg_txdpd_comp_coef_q_e_man U RW default = 'h5 -+typedef union RG_XMIT_A71_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_coef_i_e_man : 12; -+ unsigned int rsvd_0 : 4; -+ unsigned int rg_txdpd_comp_coef_q_e_man : 12; -+ unsigned int rsvd_1 : 4; -+ } b; -+} RG_XMIT_A71_FIELD_T; -+ -+#define RG_XMIT_A72 (RF_D_ADDA_XMIT_REG_BASE + 0x130) -+// Bit 12 :0 rg_txdpd_comp_low_thresh U RW default = 'hcd -+// Bit 28 :16 rg_txdpd_comp_high_thresh U RW default = 'h1000 -+typedef union RG_XMIT_A72_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_low_thresh : 13; -+ unsigned int rsvd_0 : 3; -+ unsigned int rg_txdpd_comp_high_thresh : 13; -+ unsigned int rsvd_1 : 3; -+ } b; -+} RG_XMIT_A72_FIELD_T; -+ -+#define RG_XMIT_A73 (RF_D_ADDA_XMIT_REG_BASE + 0x134) -+// Bit 10 :0 rg_txdpd_comp_lut_00_i U RW default = 'h101 -+// Bit 26 :16 rg_txdpd_comp_lut_00_q U RW default = 'h0 -+typedef union RG_XMIT_A73_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_00_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_00_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A73_FIELD_T; -+ -+#define RG_XMIT_A74 (RF_D_ADDA_XMIT_REG_BASE + 0x138) -+// Bit 10 :0 rg_txdpd_comp_lut_01_i U RW default = 'hfb -+// Bit 26 :16 rg_txdpd_comp_lut_01_q U RW default = 'h7fe -+typedef union RG_XMIT_A74_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_01_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_01_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A74_FIELD_T; -+ -+#define RG_XMIT_A75 (RF_D_ADDA_XMIT_REG_BASE + 0x13c) -+// Bit 10 :0 rg_txdpd_comp_lut_02_i U RW default = 'hf5 -+// Bit 26 :16 rg_txdpd_comp_lut_02_q U RW default = 'h7fb -+typedef union RG_XMIT_A75_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_02_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_02_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A75_FIELD_T; -+ -+#define RG_XMIT_A76 (RF_D_ADDA_XMIT_REG_BASE + 0x140) -+// Bit 10 :0 rg_txdpd_comp_lut_03_i U RW default = 'hf2 -+// Bit 26 :16 rg_txdpd_comp_lut_03_q U RW default = 'h7fb -+typedef union RG_XMIT_A76_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_03_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_03_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A76_FIELD_T; -+ -+#define RG_XMIT_A77 (RF_D_ADDA_XMIT_REG_BASE + 0x144) -+// Bit 10 :0 rg_txdpd_comp_lut_04_i U RW default = 'hf2 -+// Bit 26 :16 rg_txdpd_comp_lut_04_q U RW default = 'h7fe -+typedef union RG_XMIT_A77_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_04_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_04_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A77_FIELD_T; -+ -+#define RG_XMIT_A78 (RF_D_ADDA_XMIT_REG_BASE + 0x148) -+// Bit 10 :0 rg_txdpd_comp_lut_05_i U RW default = 'hf0 -+// Bit 26 :16 rg_txdpd_comp_lut_05_q U RW default = 'h0 -+typedef union RG_XMIT_A78_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_05_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_05_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A78_FIELD_T; -+ -+#define RG_XMIT_A79 (RF_D_ADDA_XMIT_REG_BASE + 0x14c) -+// Bit 10 :0 rg_txdpd_comp_lut_06_i U RW default = 'hee -+// Bit 26 :16 rg_txdpd_comp_lut_06_q U RW default = 'h2 -+typedef union RG_XMIT_A79_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_06_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_06_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A79_FIELD_T; -+ -+#define RG_XMIT_A80 (RF_D_ADDA_XMIT_REG_BASE + 0x150) -+// Bit 10 :0 rg_txdpd_comp_lut_07_i U RW default = 'heb -+// Bit 26 :16 rg_txdpd_comp_lut_07_q U RW default = 'h4 -+typedef union RG_XMIT_A80_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_07_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_07_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A80_FIELD_T; -+ -+#define RG_XMIT_A81 (RF_D_ADDA_XMIT_REG_BASE + 0x154) -+// Bit 10 :0 rg_txdpd_comp_lut_08_i U RW default = 'he8 -+// Bit 26 :16 rg_txdpd_comp_lut_08_q U RW default = 'h5 -+typedef union RG_XMIT_A81_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_08_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_08_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A81_FIELD_T; -+ -+#define RG_XMIT_A82 (RF_D_ADDA_XMIT_REG_BASE + 0x158) -+// Bit 10 :0 rg_txdpd_comp_lut_09_i U RW default = 'he6 -+// Bit 26 :16 rg_txdpd_comp_lut_09_q U RW default = 'h6 -+typedef union RG_XMIT_A82_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_09_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_09_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A82_FIELD_T; -+ -+#define RG_XMIT_A83 (RF_D_ADDA_XMIT_REG_BASE + 0x15c) -+// Bit 10 :0 rg_txdpd_comp_lut_10_i U RW default = 'he4 -+// Bit 26 :16 rg_txdpd_comp_lut_10_q U RW default = 'h7 -+typedef union RG_XMIT_A83_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_10_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_10_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A83_FIELD_T; -+ -+#define RG_XMIT_A84 (RF_D_ADDA_XMIT_REG_BASE + 0x160) -+// Bit 10 :0 rg_txdpd_comp_lut_11_i U RW default = 'he4 -+// Bit 26 :16 rg_txdpd_comp_lut_11_q U RW default = 'h8 -+typedef union RG_XMIT_A84_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_11_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_11_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A84_FIELD_T; -+ -+#define RG_XMIT_A85 (RF_D_ADDA_XMIT_REG_BASE + 0x164) -+// Bit 10 :0 rg_txdpd_comp_lut_12_i U RW default = 'he6 -+// Bit 26 :16 rg_txdpd_comp_lut_12_q U RW default = 'h9 -+typedef union RG_XMIT_A85_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_12_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_12_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A85_FIELD_T; -+ -+#define RG_XMIT_A86 (RF_D_ADDA_XMIT_REG_BASE + 0x168) -+// Bit 10 :0 rg_txdpd_comp_lut_13_i U RW default = 'hea -+// Bit 26 :16 rg_txdpd_comp_lut_13_q U RW default = 'h9 -+typedef union RG_XMIT_A86_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_13_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_13_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A86_FIELD_T; -+ -+#define RG_XMIT_A87 (RF_D_ADDA_XMIT_REG_BASE + 0x16c) -+// Bit 10 :0 rg_txdpd_comp_lut_14_i U RW default = 'hef -+// Bit 26 :16 rg_txdpd_comp_lut_14_q U RW default = 'h8 -+typedef union RG_XMIT_A87_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_14_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_14_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A87_FIELD_T; -+ -+#define RG_XMIT_A88 (RF_D_ADDA_XMIT_REG_BASE + 0x170) -+// Bit 10 :0 rg_txdpd_comp_lut_15_i U RW default = 'hf6 -+// Bit 26 :16 rg_txdpd_comp_lut_15_q U RW default = 'h7 -+typedef union RG_XMIT_A88_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_15_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_15_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A88_FIELD_T; -+ -+#define RG_XMIT_A89 (RF_D_ADDA_XMIT_REG_BASE + 0x174) -+// Bit 10 :0 rg_txdpd_comp_lut_16_i U RW default = 'hfe -+// Bit 26 :16 rg_txdpd_comp_lut_16_q U RW default = 'h5 -+typedef union RG_XMIT_A89_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_16_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_16_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A89_FIELD_T; -+ -+#define RG_XMIT_A90 (RF_D_ADDA_XMIT_REG_BASE + 0x178) -+// Bit 10 :0 rg_txdpd_comp_lut_17_i U RW default = 'h108 -+// Bit 26 :16 rg_txdpd_comp_lut_17_q U RW default = 'h2 -+typedef union RG_XMIT_A90_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_17_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_17_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A90_FIELD_T; -+ -+#define RG_XMIT_A91 (RF_D_ADDA_XMIT_REG_BASE + 0x17c) -+// Bit 10 :0 rg_txdpd_comp_lut_18_i U RW default = 'h113 -+// Bit 26 :16 rg_txdpd_comp_lut_18_q U RW default = 'h7ff -+typedef union RG_XMIT_A91_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_18_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_18_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A91_FIELD_T; -+ -+#define RG_XMIT_A92 (RF_D_ADDA_XMIT_REG_BASE + 0x180) -+// Bit 10 :0 rg_txdpd_comp_lut_19_i U RW default = 'h11e -+// Bit 26 :16 rg_txdpd_comp_lut_19_q U RW default = 'h7fd -+typedef union RG_XMIT_A92_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_19_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_19_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A92_FIELD_T; -+ -+#define RG_XMIT_A93 (RF_D_ADDA_XMIT_REG_BASE + 0x184) -+// Bit 10 :0 rg_txdpd_comp_lut_20_i U RW default = 'h129 -+// Bit 26 :16 rg_txdpd_comp_lut_20_q U RW default = 'h7fa -+typedef union RG_XMIT_A93_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_20_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_20_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A93_FIELD_T; -+ -+#define RG_XMIT_A94 (RF_D_ADDA_XMIT_REG_BASE + 0x188) -+// Bit 10 :0 rg_txdpd_comp_lut_21_i U RW default = 'h135 -+// Bit 26 :16 rg_txdpd_comp_lut_21_q U RW default = 'h7f7 -+typedef union RG_XMIT_A94_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_21_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_21_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A94_FIELD_T; -+ -+#define RG_XMIT_A95 (RF_D_ADDA_XMIT_REG_BASE + 0x18c) -+// Bit 10 :0 rg_txdpd_comp_lut_22_i U RW default = 'h140 -+// Bit 26 :16 rg_txdpd_comp_lut_22_q U RW default = 'h7f4 -+typedef union RG_XMIT_A95_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_22_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_22_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A95_FIELD_T; -+ -+#define RG_XMIT_A96 (RF_D_ADDA_XMIT_REG_BASE + 0x190) -+// Bit 10 :0 rg_txdpd_comp_lut_23_i U RW default = 'h14b -+// Bit 26 :16 rg_txdpd_comp_lut_23_q U RW default = 'h7f1 -+typedef union RG_XMIT_A96_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_23_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_23_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A96_FIELD_T; -+ -+#define RG_XMIT_A97 (RF_D_ADDA_XMIT_REG_BASE + 0x194) -+// Bit 10 :0 rg_txdpd_comp_lut_24_i U RW default = 'h157 -+// Bit 26 :16 rg_txdpd_comp_lut_24_q U RW default = 'h7ee -+typedef union RG_XMIT_A97_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_24_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_24_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A97_FIELD_T; -+ -+#define RG_XMIT_A98 (RF_D_ADDA_XMIT_REG_BASE + 0x198) -+// Bit 10 :0 rg_txdpd_comp_lut_25_i U RW default = 'h163 -+// Bit 26 :16 rg_txdpd_comp_lut_25_q U RW default = 'h7ec -+typedef union RG_XMIT_A98_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_25_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_25_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A98_FIELD_T; -+ -+#define RG_XMIT_A99 (RF_D_ADDA_XMIT_REG_BASE + 0x19c) -+// Bit 10 :0 rg_txdpd_comp_lut_26_i U RW default = 'h170 -+// Bit 26 :16 rg_txdpd_comp_lut_26_q U RW default = 'h7e9 -+typedef union RG_XMIT_A99_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_26_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_26_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A99_FIELD_T; -+ -+#define RG_XMIT_A100 (RF_D_ADDA_XMIT_REG_BASE + 0x1a0) -+// Bit 10 :0 rg_txdpd_comp_lut_27_i U RW default = 'h17b -+// Bit 26 :16 rg_txdpd_comp_lut_27_q U RW default = 'h7e6 -+typedef union RG_XMIT_A100_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_27_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_27_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A100_FIELD_T; -+ -+#define RG_XMIT_A101 (RF_D_ADDA_XMIT_REG_BASE + 0x1a4) -+// Bit 10 :0 rg_txdpd_comp_lut_28_i U RW default = 'h185 -+// Bit 26 :16 rg_txdpd_comp_lut_28_q U RW default = 'h7e2 -+typedef union RG_XMIT_A101_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_28_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_28_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A101_FIELD_T; -+ -+#define RG_XMIT_A102 (RF_D_ADDA_XMIT_REG_BASE + 0x1a8) -+// Bit 10 :0 rg_txdpd_comp_lut_29_i U RW default = 'h18d -+// Bit 26 :16 rg_txdpd_comp_lut_29_q U RW default = 'h7df -+typedef union RG_XMIT_A102_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_29_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_29_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A102_FIELD_T; -+ -+#define RG_XMIT_A103 (RF_D_ADDA_XMIT_REG_BASE + 0x1ac) -+// Bit 10 :0 rg_txdpd_comp_lut_30_i U RW default = 'h199 -+// Bit 26 :16 rg_txdpd_comp_lut_30_q U RW default = 'h7dc -+typedef union RG_XMIT_A103_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_30_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_30_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A103_FIELD_T; -+ -+#define RG_XMIT_A104 (RF_D_ADDA_XMIT_REG_BASE + 0x1b0) -+// Bit 10 :0 rg_txdpd_comp_lut_31_i U RW default = 'h1ad -+// Bit 26 :16 rg_txdpd_comp_lut_31_q U RW default = 'h7da -+typedef union RG_XMIT_A104_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_31_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_31_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A104_FIELD_T; -+ -+#define RG_XMIT_A105 (RF_D_ADDA_XMIT_REG_BASE + 0x1b4) -+// Bit 12 :0 rg_txdpd_comp_high_thresh_recip U RW default = 'h10d -+// Bit 30 :16 rg_txdpd_coef_update_en U RW default = 'h7fff -+typedef union RG_XMIT_A105_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_high_thresh_recip : 13; -+ unsigned int rsvd_0 : 3; -+ unsigned int rg_txdpd_coef_update_en : 15; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_XMIT_A105_FIELD_T; -+ -+#define RG_XMIT_A106 (RF_D_ADDA_XMIT_REG_BASE + 0x1b8) -+// Bit 7 :0 rg_tx_atten_factor U RW default = 'h8 -+// Bit 8 rg_tx_atten_factor_man_mode U RW default = 'h1 -+typedef union RG_XMIT_A106_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_atten_factor : 8; -+ unsigned int rg_tx_atten_factor_man_mode : 1; -+ unsigned int rsvd_0 : 23; -+ } b; -+} RG_XMIT_A106_FIELD_T; -+ -+#define RG_XMIT_A107 (RF_D_ADDA_XMIT_REG_BASE + 0x1bc) -+// Bit 7 :0 rg_tx_coeff_20m_0 U RW default = 'hfb -+// Bit 15 :8 rg_tx_coeff_20m_1 U RW default = 'hfb -+// Bit 23 :16 rg_tx_coeff_20m_2 U RW default = 'h2 -+// Bit 31 :24 rg_tx_coeff_20m_3 U RW default = 'h11 -+typedef union RG_XMIT_A107_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_coeff_20m_0 : 8; -+ unsigned int rg_tx_coeff_20m_1 : 8; -+ unsigned int rg_tx_coeff_20m_2 : 8; -+ unsigned int rg_tx_coeff_20m_3 : 8; -+ } b; -+} RG_XMIT_A107_FIELD_T; -+ -+#define RG_XMIT_A108 (RF_D_ADDA_XMIT_REG_BASE + 0x1c0) -+// Bit 7 :0 rg_tx_coeff_20m_4 U RW default = 'h25 -+// Bit 15 :8 rg_tx_coeff_20m_5 U RW default = 'h37 -+// Bit 23 :16 rg_tx_coeff_20m_6 U RW default = 'h3e -+typedef union RG_XMIT_A108_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_coeff_20m_4 : 8; -+ unsigned int rg_tx_coeff_20m_5 : 8; -+ unsigned int rg_tx_coeff_20m_6 : 8; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_XMIT_A108_FIELD_T; -+ -+#define RG_XMIT_A109 (RF_D_ADDA_XMIT_REG_BASE + 0x1c4) -+// Bit 7 :0 rg_tx_coeff_40m_0 U RW default = 'h2 -+// Bit 15 :8 rg_tx_coeff_40m_1 U RW default = 'hfc -+// Bit 23 :16 rg_tx_coeff_40m_2 U RW default = 'hf3 -+// Bit 31 :24 rg_tx_coeff_40m_3 U RW default = 'hf8 -+typedef union RG_XMIT_A109_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_coeff_40m_0 : 8; -+ unsigned int rg_tx_coeff_40m_1 : 8; -+ unsigned int rg_tx_coeff_40m_2 : 8; -+ unsigned int rg_tx_coeff_40m_3 : 8; -+ } b; -+} RG_XMIT_A109_FIELD_T; -+ -+#define RG_XMIT_A110 (RF_D_ADDA_XMIT_REG_BASE + 0x1c8) -+// Bit 7 :0 rg_tx_coeff_40m_4 U RW default = 'h1a -+// Bit 15 :8 rg_tx_coeff_40m_5 U RW default = 'h49 -+// Bit 23 :16 rg_tx_coeff_40m_6 U RW default = 'h60 -+typedef union RG_XMIT_A110_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_coeff_40m_4 : 8; -+ unsigned int rg_tx_coeff_40m_5 : 8; -+ unsigned int rg_tx_coeff_40m_6 : 8; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_XMIT_A110_FIELD_T; -+ -+#define RG_XMIT_A111 (RF_D_ADDA_XMIT_REG_BASE + 0x1cc) -+// Bit 1 :0 rg_txirr_theta_step U RW default = 'h0 -+typedef union RG_XMIT_A111_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txirr_theta_step : 2; -+ unsigned int rsvd_0 : 30; -+ } b; -+} RG_XMIT_A111_FIELD_T; -+ -+#define RG_XMIT_A112 (RF_D_ADDA_XMIT_REG_BASE + 0x1d0) -+// Bit 7 :0 rg_tx_atten_factor0 U RW default = 'h8 -+// Bit 15 :8 rg_tx_atten_factor1 U RW default = 'h8 -+// Bit 23 :16 rg_tx_atten_factor2 U RW default = 'h8 -+// Bit 31 :24 rg_tx_atten_factor3 U RW default = 'h8 -+typedef union RG_XMIT_A112_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_atten_factor0 : 8; -+ unsigned int rg_tx_atten_factor1 : 8; -+ unsigned int rg_tx_atten_factor2 : 8; -+ unsigned int rg_tx_atten_factor3 : 8; -+ } b; -+} RG_XMIT_A112_FIELD_T; -+ -+#define RG_XMIT_A113 (RF_D_ADDA_XMIT_REG_BASE + 0x1d4) -+// Bit 7 :0 rg_tx_atten_factor4 U RW default = 'h8 -+// Bit 15 :8 rg_tx_atten_factor5 U RW default = 'h8 -+// Bit 23 :16 rg_tx_atten_factor6 U RW default = 'h8 -+// Bit 31 :24 rg_tx_atten_factor7 U RW default = 'h8 -+typedef union RG_XMIT_A113_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_atten_factor4 : 8; -+ unsigned int rg_tx_atten_factor5 : 8; -+ unsigned int rg_tx_atten_factor6 : 8; -+ unsigned int rg_tx_atten_factor7 : 8; -+ } b; -+} RG_XMIT_A113_FIELD_T; -+ -+#define RG_XMIT_A114 (RF_D_ADDA_XMIT_REG_BASE + 0x1d8) -+// Bit 7 :0 rg_tx_atten_factor8 U RW default = 'h8 -+// Bit 15 :8 rg_tx_atten_factor9 U RW default = 'h8 -+// Bit 23 :16 rg_tx_atten_factora U RW default = 'h8 -+// Bit 31 :24 rg_tx_atten_factorb U RW default = 'h8 -+typedef union RG_XMIT_A114_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_atten_factor8 : 8; -+ unsigned int rg_tx_atten_factor9 : 8; -+ unsigned int rg_tx_atten_factora : 8; -+ unsigned int rg_tx_atten_factorb : 8; -+ } b; -+} RG_XMIT_A114_FIELD_T; -+ -+#define RG_XMIT_A115 (RF_D_ADDA_XMIT_REG_BASE + 0x1dc) -+// Bit 7 :0 rg_tx_atten_factorc U RW default = 'h8 -+// Bit 15 :8 rg_tx_atten_factord U RW default = 'h8 -+// Bit 23 :16 rg_tx_atten_factore U RW default = 'h8 -+// Bit 31 :24 rg_tx_atten_factorf U RW default = 'h8 -+typedef union RG_XMIT_A115_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_tx_atten_factorc : 8; -+ unsigned int rg_tx_atten_factord : 8; -+ unsigned int rg_tx_atten_factore : 8; -+ unsigned int rg_tx_atten_factorf : 8; -+ } b; -+} RG_XMIT_A115_FIELD_T; -+ -+#define RG_XMIT_A116 (RF_D_ADDA_XMIT_REG_BASE + 0x1e0) -+// Bit 10 :0 rg_txdpd_comp_lut_32_i U RW default = 'h0 -+// Bit 26 :16 rg_txdpd_comp_lut_32_q U RW default = 'h0 -+typedef union RG_XMIT_A116_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_txdpd_comp_lut_32_i : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_txdpd_comp_lut_32_q : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A116_FIELD_T; -+ -+#define RG_XMIT_A117 (RF_D_ADDA_XMIT_REG_BASE + 0x1e4) -+// Bit 10 :0 rg_trig_wave_min U RW default = 'h401 -+// Bit 26 :16 rg_trig_wave_max U RW default = 'h3ff -+typedef union RG_XMIT_A117_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_trig_wave_min : 11; -+ unsigned int rsvd_0 : 5; -+ unsigned int rg_trig_wave_max : 11; -+ unsigned int rsvd_1 : 5; -+ } b; -+} RG_XMIT_A117_FIELD_T; -+ -+#define RG_XMIT_A118 (RF_D_ADDA_XMIT_REG_BASE + 0x1e8) -+// Bit 10 :0 rg_trig_wave_step U RW default = 'h5 -+// Bit 27 :12 rg_trig_wave_length U RW default = 'h2 -+// Bit 30 rg_trig_wave_q_hold U RW default = 'h0 -+// Bit 31 rg_trig_wave_en U RW default = 'h0 -+typedef union RG_XMIT_A118_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_trig_wave_step : 11; -+ unsigned int rsvd_0 : 1; -+ unsigned int rg_trig_wave_length : 16; -+ unsigned int rsvd_1 : 2; -+ unsigned int rg_trig_wave_q_hold : 1; -+ unsigned int rg_trig_wave_en : 1; -+ } b; -+} RG_XMIT_A118_FIELD_T; -+ -+#define RG_XMIT_A119 (RF_D_ADDA_XMIT_REG_BASE + 0x1ec) -+// Bit 0 rg_const_sel U RW default = 'h0 -+typedef union RG_XMIT_A119_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_const_sel : 1; -+ unsigned int rsvd_0 : 31; -+ } b; -+} RG_XMIT_A119_FIELD_T; -+ -+#endif -+ -diff --git a/drivers/net/wireless/w1/common/rf_d_rx_reg.h b/drivers/net/wireless/w1/common/rf_d_rx_reg.h -new file mode 100644 -index 000000000000..8ac34b1e8b04 ---- /dev/null -+++ b/drivers/net/wireless/w1/common/rf_d_rx_reg.h -@@ -0,0 +1,2486 @@ -+#ifdef RF_D_RX_REG -+#else -+#define RF_D_RX_REG -+ -+ -+#define RF_D_RX_REG_BASE (0xc00) -+ -+#define RG_RX_A0 (RF_D_RX_REG_BASE + 0x0) -+// Bit 31 :0 rg_wf_rx_dig_rsv0 U RW default = 'hffff -+typedef union RG_RX_A0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_DIG_RSV0 : 32; -+ } b; -+} RG_RX_A0_FIELD_T; -+ -+#define RG_RX_A1 (RF_D_RX_REG_BASE + 0x4) -+// Bit 31 :0 rg_wf_rx_dig_rsv1 U RW default = 'hffff -+typedef union RG_RX_A1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_DIG_RSV1 : 32; -+ } b; -+} RG_RX_A1_FIELD_T; -+ -+#define RG_RX_A2 (RF_D_RX_REG_BASE + 0x8) -+// Bit 0 rg_wf_rx_bbbm_man_mode U RW default = 'h0 -+// Bit 3 :2 rg_wf_rx_bw_sel U RW default = 'h0 -+// Bit 4 rg_wf_rx_adcfs_sel U RW default = 'h0 -+// Bit 15 :8 rg_wf_rx_gain_man U RW default = 'h9c -+// Bit 16 rg_wf_rx_gain_man_mode U RW default = 'h0 -+// Bit 23 :20 rg_wf_rx_osc_freq U RW default = 'h5 -+typedef union RG_RX_A2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_BBBM_MAN_MODE : 1; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF_RX_BW_SEL : 2; -+ unsigned int RG_WF_RX_ADCFS_SEL : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int RG_WF_RX_GAIN_MAN : 8; -+ unsigned int RG_WF_RX_GAIN_MAN_MODE : 1; -+ unsigned int rsvd_2 : 3; -+ unsigned int RG_WF_RX_OSC_FREQ : 4; -+ unsigned int rsvd_3 : 8; -+ } b; -+} RG_RX_A2_FIELD_T; -+ -+#define RG_RX_A3 (RF_D_RX_REG_BASE + 0xc) -+// Bit 0 rg_m0_wf_rx_fe_topbias_en U RW default = 'h0 -+// Bit 1 rg_m0_wf_rx_lna_bias_en U RW default = 'h0 -+// Bit 2 rg_m0_wf_rx_gm_bias_en U RW default = 'h0 -+// Bit 3 rg_m0_wf_rx_mxr_bias_en U RW default = 'h0 -+// Bit 4 rg_m0_wf5g_rx_lna_trsw_en U RW default = 'h0 -+// Bit 5 rg_m0_wf5g_rx_lna_en U RW default = 'h0 -+// Bit 6 rg_m0_wf5g_rx_gm_en U RW default = 'h0 -+// Bit 7 rg_m0_wf5g_rx_mxr_en U RW default = 'h0 -+// Bit 8 rg_m0_wf5g_rx_dpd_en U RW default = 'h0 -+// Bit 9 rg_m0_wf5g_rx_irrcal_en U RW default = 'h0 -+// Bit 10 rg_m0_wf2g_rx_lna_trsw_en U RW default = 'h0 -+// Bit 11 rg_m0_wf2g_rx_lna_en U RW default = 'h0 -+// Bit 12 rg_m0_wf2g_rx_gm_en U RW default = 'h0 -+// Bit 13 rg_m0_wf2g_rx_mxr_en U RW default = 'h0 -+// Bit 14 rg_m0_wf2g_rx_irrcal_en U RW default = 'h0 -+// Bit 15 rg_m0_wf2g_rx_dpd_en U RW default = 'h0 -+// Bit 17 rg_m0_wf_rtx_abb_topbias_en U RW default = 'h0 -+// Bit 18 rg_m0_wf_rtx_abb_rx_en U RW default = 'h0 -+// Bit 22 rg_m0_wf_rx_tia_bias_en U RW default = 'h0 -+// Bit 23 rg_m0_wf_rx_rssipga_bias_en U RW default = 'h0 -+// Bit 24 rg_m0_wf_rx_lpf_bias_en U RW default = 'h0 -+// Bit 25 rg_m0_wf_rx_tia_en U RW default = 'h0 -+// Bit 26 rg_m0_wf_rx_rssipga_en U RW default = 'h0 -+// Bit 27 rg_m0_wf_rx_lpf_en U RW default = 'h0 -+// Bit 28 rg_m0_wf_rx_lpf_i_dcoc_en U RW default = 'h0 -+// Bit 29 rg_m0_wf_rx_lpf_q_dcoc_en U RW default = 'h0 -+typedef union RG_RX_A3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M0_WF_RX_FE_TOPBIAS_EN : 1; -+ unsigned int RG_M0_WF_RX_LNA_BIAS_EN : 1; -+ unsigned int RG_M0_WF_RX_GM_BIAS_EN : 1; -+ unsigned int RG_M0_WF_RX_MXR_BIAS_EN : 1; -+ unsigned int RG_M0_WF5G_RX_LNA_TRSW_EN : 1; -+ unsigned int RG_M0_WF5G_RX_LNA_EN : 1; -+ unsigned int RG_M0_WF5G_RX_GM_EN : 1; -+ unsigned int RG_M0_WF5G_RX_MXR_EN : 1; -+ unsigned int RG_M0_WF5G_RX_DPD_EN : 1; -+ unsigned int RG_M0_WF5G_RX_IRRCAL_EN : 1; -+ unsigned int RG_M0_WF2G_RX_LNA_TRSW_EN : 1; -+ unsigned int RG_M0_WF2G_RX_LNA_EN : 1; -+ unsigned int RG_M0_WF2G_RX_GM_EN : 1; -+ unsigned int RG_M0_WF2G_RX_MXR_EN : 1; -+ unsigned int RG_M0_WF2G_RX_IRRCAL_EN : 1; -+ unsigned int RG_M0_WF2G_RX_DPD_EN : 1; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_M0_WF_RTX_ABB_TOPBIAS_EN : 1; -+ unsigned int RG_M0_WF_RTX_ABB_RX_EN : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int RG_M0_WF_RX_TIA_BIAS_EN : 1; -+ unsigned int RG_M0_WF_RX_RSSIPGA_BIAS_EN : 1; -+ unsigned int RG_M0_WF_RX_LPF_BIAS_EN : 1; -+ unsigned int RG_M0_WF_RX_TIA_EN : 1; -+ unsigned int RG_M0_WF_RX_RSSIPGA_EN : 1; -+ unsigned int RG_M0_WF_RX_LPF_EN : 1; -+ unsigned int RG_M0_WF_RX_LPF_I_DCOC_EN : 1; -+ unsigned int RG_M0_WF_RX_LPF_Q_DCOC_EN : 1; -+ unsigned int rsvd_2 : 2; -+ } b; -+} RG_RX_A3_FIELD_T; -+ -+#define RG_RX_A4 (RF_D_RX_REG_BASE + 0x10) -+// Bit 0 rg_m1_wf_rx_fe_topbias_en U RW default = 'h0 -+// Bit 1 rg_m1_wf_rx_lna_bias_en U RW default = 'h0 -+// Bit 2 rg_m1_wf_rx_gm_bias_en U RW default = 'h0 -+// Bit 3 rg_m1_wf_rx_mxr_bias_en U RW default = 'h0 -+// Bit 4 rg_m1_wf5g_rx_lna_trsw_en U RW default = 'h0 -+// Bit 5 rg_m1_wf5g_rx_lna_en U RW default = 'h0 -+// Bit 6 rg_m1_wf5g_rx_gm_en U RW default = 'h0 -+// Bit 7 rg_m1_wf5g_rx_mxr_en U RW default = 'h0 -+// Bit 8 rg_m1_wf5g_rx_dpd_en U RW default = 'h0 -+// Bit 9 rg_m1_wf5g_rx_irrcal_en U RW default = 'h0 -+// Bit 10 rg_m1_wf2g_rx_lna_trsw_en U RW default = 'h0 -+// Bit 11 rg_m1_wf2g_rx_lna_en U RW default = 'h0 -+// Bit 12 rg_m1_wf2g_rx_gm_en U RW default = 'h0 -+// Bit 13 rg_m1_wf2g_rx_mxr_en U RW default = 'h0 -+// Bit 14 rg_m1_wf2g_rx_irrcal_en U RW default = 'h0 -+// Bit 15 rg_m1_wf2g_rx_dpd_en U RW default = 'h0 -+// Bit 17 rg_m1_wf_rtx_abb_topbias_en U RW default = 'h0 -+// Bit 18 rg_m1_wf_rtx_abb_rx_en U RW default = 'h0 -+// Bit 22 rg_m1_wf_rx_tia_bias_en U RW default = 'h0 -+// Bit 23 rg_m1_wf_rx_rssipga_bias_en U RW default = 'h0 -+// Bit 24 rg_m1_wf_rx_lpf_bias_en U RW default = 'h0 -+// Bit 25 rg_m1_wf_rx_tia_en U RW default = 'h0 -+// Bit 26 rg_m1_wf_rx_rssipga_en U RW default = 'h0 -+// Bit 27 rg_m1_wf_rx_lpf_en U RW default = 'h0 -+// Bit 28 rg_m1_wf_rx_lpf_i_dcoc_en U RW default = 'h0 -+// Bit 29 rg_m1_wf_rx_lpf_q_dcoc_en U RW default = 'h0 -+typedef union RG_RX_A4_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M1_WF_RX_FE_TOPBIAS_EN : 1; -+ unsigned int RG_M1_WF_RX_LNA_BIAS_EN : 1; -+ unsigned int RG_M1_WF_RX_GM_BIAS_EN : 1; -+ unsigned int RG_M1_WF_RX_MXR_BIAS_EN : 1; -+ unsigned int RG_M1_WF5G_RX_LNA_TRSW_EN : 1; -+ unsigned int RG_M1_WF5G_RX_LNA_EN : 1; -+ unsigned int RG_M1_WF5G_RX_GM_EN : 1; -+ unsigned int RG_M1_WF5G_RX_MXR_EN : 1; -+ unsigned int RG_M1_WF5G_RX_DPD_EN : 1; -+ unsigned int RG_M1_WF5G_RX_IRRCAL_EN : 1; -+ unsigned int RG_M1_WF2G_RX_LNA_TRSW_EN : 1; -+ unsigned int RG_M1_WF2G_RX_LNA_EN : 1; -+ unsigned int RG_M1_WF2G_RX_GM_EN : 1; -+ unsigned int RG_M1_WF2G_RX_MXR_EN : 1; -+ unsigned int RG_M1_WF2G_RX_IRRCAL_EN : 1; -+ unsigned int RG_M1_WF2G_RX_DPD_EN : 1; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_M1_WF_RTX_ABB_TOPBIAS_EN : 1; -+ unsigned int RG_M1_WF_RTX_ABB_RX_EN : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int RG_M1_WF_RX_TIA_BIAS_EN : 1; -+ unsigned int RG_M1_WF_RX_RSSIPGA_BIAS_EN : 1; -+ unsigned int RG_M1_WF_RX_LPF_BIAS_EN : 1; -+ unsigned int RG_M1_WF_RX_TIA_EN : 1; -+ unsigned int RG_M1_WF_RX_RSSIPGA_EN : 1; -+ unsigned int RG_M1_WF_RX_LPF_EN : 1; -+ unsigned int RG_M1_WF_RX_LPF_I_DCOC_EN : 1; -+ unsigned int RG_M1_WF_RX_LPF_Q_DCOC_EN : 1; -+ unsigned int rsvd_2 : 2; -+ } b; -+} RG_RX_A4_FIELD_T; -+ -+#define RG_RX_A5 (RF_D_RX_REG_BASE + 0x14) -+// Bit 0 rg_m2_wf_rx_fe_topbias_en U RW default = 'h1 -+// Bit 1 rg_m2_wf_rx_lna_bias_en U RW default = 'h0 -+// Bit 2 rg_m2_wf_rx_gm_bias_en U RW default = 'h0 -+// Bit 3 rg_m2_wf_rx_mxr_bias_en U RW default = 'h0 -+// Bit 4 rg_m2_wf5g_rx_lna_trsw_en U RW default = 'h1 -+// Bit 5 rg_m2_wf5g_rx_lna_en U RW default = 'h0 -+// Bit 6 rg_m2_wf5g_rx_gm_en U RW default = 'h0 -+// Bit 7 rg_m2_wf5g_rx_mxr_en U RW default = 'h0 -+// Bit 8 rg_m2_wf5g_rx_dpd_en U RW default = 'h0 -+// Bit 9 rg_m2_wf5g_rx_irrcal_en U RW default = 'h0 -+// Bit 10 rg_m2_wf2g_rx_lna_trsw_en U RW default = 'h0 -+// Bit 11 rg_m2_wf2g_rx_lna_en U RW default = 'h0 -+// Bit 12 rg_m2_wf2g_rx_gm_en U RW default = 'h0 -+// Bit 13 rg_m2_wf2g_rx_mxr_en U RW default = 'h0 -+// Bit 14 rg_m2_wf2g_rx_irrcal_en U RW default = 'h0 -+// Bit 15 rg_m2_wf2g_rx_dpd_en U RW default = 'h0 -+// Bit 17 rg_m2_wf_rtx_abb_topbias_en U RW default = 'h1 -+// Bit 18 rg_m2_wf_rtx_abb_rx_en U RW default = 'h0 -+// Bit 22 rg_m2_wf_rx_tia_bias_en U RW default = 'h0 -+// Bit 23 rg_m2_wf_rx_rssipga_bias_en U RW default = 'h0 -+// Bit 24 rg_m2_wf_rx_lpf_bias_en U RW default = 'h0 -+// Bit 25 rg_m2_wf_rx_tia_en U RW default = 'h0 -+// Bit 26 rg_m2_wf_rx_rssipga_en U RW default = 'h0 -+// Bit 27 rg_m2_wf_rx_lpf_en U RW default = 'h0 -+// Bit 28 rg_m2_wf_rx_lpf_i_dcoc_en U RW default = 'h0 -+// Bit 29 rg_m2_wf_rx_lpf_q_dcoc_en U RW default = 'h0 -+typedef union RG_RX_A5_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M2_WF_RX_FE_TOPBIAS_EN : 1; -+ unsigned int RG_M2_WF_RX_LNA_BIAS_EN : 1; -+ unsigned int RG_M2_WF_RX_GM_BIAS_EN : 1; -+ unsigned int RG_M2_WF_RX_MXR_BIAS_EN : 1; -+ unsigned int RG_M2_WF5G_RX_LNA_TRSW_EN : 1; -+ unsigned int RG_M2_WF5G_RX_LNA_EN : 1; -+ unsigned int RG_M2_WF5G_RX_GM_EN : 1; -+ unsigned int RG_M2_WF5G_RX_MXR_EN : 1; -+ unsigned int RG_M2_WF5G_RX_DPD_EN : 1; -+ unsigned int RG_M2_WF5G_RX_IRRCAL_EN : 1; -+ unsigned int RG_M2_WF2G_RX_LNA_TRSW_EN : 1; -+ unsigned int RG_M2_WF2G_RX_LNA_EN : 1; -+ unsigned int RG_M2_WF2G_RX_GM_EN : 1; -+ unsigned int RG_M2_WF2G_RX_MXR_EN : 1; -+ unsigned int RG_M2_WF2G_RX_IRRCAL_EN : 1; -+ unsigned int RG_M2_WF2G_RX_DPD_EN : 1; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_M2_WF_RTX_ABB_TOPBIAS_EN : 1; -+ unsigned int RG_M2_WF_RTX_ABB_RX_EN : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int RG_M2_WF_RX_TIA_BIAS_EN : 1; -+ unsigned int RG_M2_WF_RX_RSSIPGA_BIAS_EN : 1; -+ unsigned int RG_M2_WF_RX_LPF_BIAS_EN : 1; -+ unsigned int RG_M2_WF_RX_TIA_EN : 1; -+ unsigned int RG_M2_WF_RX_RSSIPGA_EN : 1; -+ unsigned int RG_M2_WF_RX_LPF_EN : 1; -+ unsigned int RG_M2_WF_RX_LPF_I_DCOC_EN : 1; -+ unsigned int RG_M2_WF_RX_LPF_Q_DCOC_EN : 1; -+ unsigned int rsvd_2 : 2; -+ } b; -+} RG_RX_A5_FIELD_T; -+ -+#define RG_RX_A6 (RF_D_RX_REG_BASE + 0x18) -+// Bit 0 rg_m3_wf_rx_fe_topbias_en U RW default = 'h1 -+// Bit 1 rg_m3_wf_rx_lna_bias_en U RW default = 'h1 -+// Bit 2 rg_m3_wf_rx_gm_bias_en U RW default = 'h1 -+// Bit 3 rg_m3_wf_rx_mxr_bias_en U RW default = 'h1 -+// Bit 4 rg_m3_wf5g_rx_lna_trsw_en U RW default = 'h0 -+// Bit 5 rg_m3_wf5g_rx_lna_en U RW default = 'h1 -+// Bit 6 rg_m3_wf5g_rx_gm_en U RW default = 'h1 -+// Bit 7 rg_m3_wf5g_rx_mxr_en U RW default = 'h1 -+// Bit 8 rg_m3_wf5g_rx_dpd_en U RW default = 'h0 -+// Bit 9 rg_m3_wf5g_rx_irrcal_en U RW default = 'h0 -+// Bit 10 rg_m3_wf2g_rx_lna_trsw_en U RW default = 'h0 -+// Bit 11 rg_m3_wf2g_rx_lna_en U RW default = 'h0 -+// Bit 12 rg_m3_wf2g_rx_gm_en U RW default = 'h0 -+// Bit 13 rg_m3_wf2g_rx_mxr_en U RW default = 'h0 -+// Bit 14 rg_m3_wf2g_rx_irrcal_en U RW default = 'h0 -+// Bit 15 rg_m3_wf2g_rx_dpd_en U RW default = 'h0 -+// Bit 17 rg_m3_wf_rtx_abb_topbias_en U RW default = 'h1 -+// Bit 18 rg_m3_wf_rtx_abb_rx_en U RW default = 'h1 -+// Bit 22 rg_m3_wf_rx_tia_bias_en U RW default = 'h1 -+// Bit 23 rg_m3_wf_rx_rssipga_bias_en U RW default = 'h1 -+// Bit 24 rg_m3_wf_rx_lpf_bias_en U RW default = 'h1 -+// Bit 25 rg_m3_wf_rx_tia_en U RW default = 'h1 -+// Bit 26 rg_m3_wf_rx_rssipga_en U RW default = 'h1 -+// Bit 27 rg_m3_wf_rx_lpf_en U RW default = 'h1 -+// Bit 28 rg_m3_wf_rx_lpf_i_dcoc_en U RW default = 'h1 -+// Bit 29 rg_m3_wf_rx_lpf_q_dcoc_en U RW default = 'h1 -+typedef union RG_RX_A6_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M3_WF_RX_FE_TOPBIAS_EN : 1; -+ unsigned int RG_M3_WF_RX_LNA_BIAS_EN : 1; -+ unsigned int RG_M3_WF_RX_GM_BIAS_EN : 1; -+ unsigned int RG_M3_WF_RX_MXR_BIAS_EN : 1; -+ unsigned int RG_M3_WF5G_RX_LNA_TRSW_EN : 1; -+ unsigned int RG_M3_WF5G_RX_LNA_EN : 1; -+ unsigned int RG_M3_WF5G_RX_GM_EN : 1; -+ unsigned int RG_M3_WF5G_RX_MXR_EN : 1; -+ unsigned int RG_M3_WF5G_RX_DPD_EN : 1; -+ unsigned int RG_M3_WF5G_RX_IRRCAL_EN : 1; -+ unsigned int RG_M3_WF2G_RX_LNA_TRSW_EN : 1; -+ unsigned int RG_M3_WF2G_RX_LNA_EN : 1; -+ unsigned int RG_M3_WF2G_RX_GM_EN : 1; -+ unsigned int RG_M3_WF2G_RX_MXR_EN : 1; -+ unsigned int RG_M3_WF2G_RX_IRRCAL_EN : 1; -+ unsigned int RG_M3_WF2G_RX_DPD_EN : 1; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_M3_WF_RTX_ABB_TOPBIAS_EN : 1; -+ unsigned int RG_M3_WF_RTX_ABB_RX_EN : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int RG_M3_WF_RX_TIA_BIAS_EN : 1; -+ unsigned int RG_M3_WF_RX_RSSIPGA_BIAS_EN : 1; -+ unsigned int RG_M3_WF_RX_LPF_BIAS_EN : 1; -+ unsigned int RG_M3_WF_RX_TIA_EN : 1; -+ unsigned int RG_M3_WF_RX_RSSIPGA_EN : 1; -+ unsigned int RG_M3_WF_RX_LPF_EN : 1; -+ unsigned int RG_M3_WF_RX_LPF_I_DCOC_EN : 1; -+ unsigned int RG_M3_WF_RX_LPF_Q_DCOC_EN : 1; -+ unsigned int rsvd_2 : 2; -+ } b; -+} RG_RX_A6_FIELD_T; -+ -+#define RG_RX_A7 (RF_D_RX_REG_BASE + 0x1c) -+// Bit 3 :0 rg_wf5g_rx_lna_tank_sel_band0 U RW default = 'h9 -+// Bit 7 :4 rg_wf5g_rx_lna_tank_sel_band1 U RW default = 'h9 -+// Bit 11 :8 rg_wf5g_rx_lna_tank_sel_band2 U RW default = 'h8 -+// Bit 15 :12 rg_wf5g_rx_lna_tank_sel_band3 U RW default = 'h7 -+// Bit 19 :16 rg_wf5g_rx_lna_tank_sel_band4 U RW default = 'h6 -+// Bit 23 :20 rg_wf5g_rx_lna_tank_sel_band5 U RW default = 'h5 -+// Bit 27 :24 rg_wf5g_rx_lna_tank_sel_band6 U RW default = 'h4 -+// Bit 31 :28 rg_wf5g_rx_lna_tank_sel_band7 U RW default = 'h4 -+typedef union RG_RX_A7_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND0 : 4; -+ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND1 : 4; -+ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND2 : 4; -+ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND3 : 4; -+ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND4 : 4; -+ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND5 : 4; -+ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND6 : 4; -+ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND7 : 4; -+ } b; -+} RG_RX_A7_FIELD_T; -+ -+#define RG_RX_A8 (RF_D_RX_REG_BASE + 0x20) -+// Bit 3 :0 rg_wf5g_rx_lna_tank_sel_band8 U RW default = 'h3 -+// Bit 7 :4 rg_wf5g_rx_lna_tank_sel_band9 U RW default = 'h2 -+// Bit 11 :8 rg_wf5g_rx_lna_tank_sel_man U RW default = 'h2 -+// Bit 12 rg_wf5g_rx_lna_tank_sel_man_mode U RW default = 'h0 -+// Bit 19 :16 rg_wf2g_rx_lna_tank_sel U RW default = 'h5 -+// Bit 23 :20 rg_wf2g_rx_lna_tank_sel_man U RW default = 'h5 -+// Bit 24 rg_wf2g_rx_lna_tank_sel_man_mode U RW default = 'h0 -+typedef union RG_RX_A8_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND8 : 4; -+ unsigned int RG_WF5G_RX_LNA_TANK_SEL_BAND9 : 4; -+ unsigned int RG_WF5G_RX_LNA_TANK_SEL_MAN : 4; -+ unsigned int RG_WF5G_RX_LNA_TANK_SEL_MAN_MODE : 1; -+ unsigned int rsvd_0 : 3; -+ unsigned int RG_WF2G_RX_LNA_TANK_SEL : 4; -+ unsigned int RG_WF2G_RX_LNA_TANK_SEL_MAN : 4; -+ unsigned int RG_WF2G_RX_LNA_TANK_SEL_MAN_MODE : 1; -+ unsigned int rsvd_1 : 7; -+ } b; -+} RG_RX_A8_FIELD_T; -+ -+#define RG_RX_A9 (RF_D_RX_REG_BASE + 0x24) -+// Bit 2 :0 rg_wf5g_rx_lna_tank_offset_g1 U RW default = 'h0 -+// Bit 6 :4 rg_wf5g_rx_lna_tank_offset_g2 U RW default = 'h0 -+// Bit 10 :8 rg_wf5g_rx_lna_tank_offset_g3 U RW default = 'h0 -+// Bit 14 :12 rg_wf5g_rx_lna_tank_offset_g4 U RW default = 'h2 -+// Bit 18 :16 rg_wf5g_rx_lna_tank_offset_g5 U RW default = 'h2 -+// Bit 26 :24 rg_wf5g_rx_lna_tank_offset_g6 U RW default = 'h2 -+// Bit 30 :28 rg_wf5g_rx_lna_tank_offset_g7 U RW default = 'h2 -+typedef union RG_RX_A9_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LNA_TANK_OFFSET_G1 : 3; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF5G_RX_LNA_TANK_OFFSET_G2 : 3; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF5G_RX_LNA_TANK_OFFSET_G3 : 3; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF5G_RX_LNA_TANK_OFFSET_G4 : 3; -+ unsigned int rsvd_3 : 1; -+ unsigned int RG_WF5G_RX_LNA_TANK_OFFSET_G5 : 3; -+ unsigned int rsvd_4 : 5; -+ unsigned int RG_WF5G_RX_LNA_TANK_OFFSET_G6 : 3; -+ unsigned int rsvd_5 : 1; -+ unsigned int RG_WF5G_RX_LNA_TANK_OFFSET_G7 : 3; -+ unsigned int rsvd_6 : 1; -+ } b; -+} RG_RX_A9_FIELD_T; -+ -+#define RG_RX_A10 (RF_D_RX_REG_BASE + 0x28) -+// Bit 2 :0 rg_wf2g_rx_lna_tank_offset_g1 U RW default = 'h0 -+// Bit 6 :4 rg_wf2g_rx_lna_tank_offset_g2 U RW default = 'h0 -+// Bit 10 :8 rg_wf2g_rx_lna_tank_offset_g3 U RW default = 'h0 -+// Bit 14 :12 rg_wf2g_rx_lna_tank_offset_g4 U RW default = 'h0 -+// Bit 18 :16 rg_wf2g_rx_lna_tank_offset_g5 U RW default = 'h0 -+// Bit 26 :24 rg_wf2g_rx_lna_tank_offset_g6 U RW default = 'h2 -+// Bit 30 :28 rg_wf2g_rx_lna_tank_offset_g7 U RW default = 'h3 -+typedef union RG_RX_A10_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LNA_TANK_OFFSET_G1 : 3; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF2G_RX_LNA_TANK_OFFSET_G2 : 3; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF2G_RX_LNA_TANK_OFFSET_G3 : 3; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF2G_RX_LNA_TANK_OFFSET_G4 : 3; -+ unsigned int rsvd_3 : 1; -+ unsigned int RG_WF2G_RX_LNA_TANK_OFFSET_G5 : 3; -+ unsigned int rsvd_4 : 5; -+ unsigned int RG_WF2G_RX_LNA_TANK_OFFSET_G6 : 3; -+ unsigned int rsvd_5 : 1; -+ unsigned int RG_WF2G_RX_LNA_TANK_OFFSET_G7 : 3; -+ unsigned int rsvd_6 : 1; -+ } b; -+} RG_RX_A10_FIELD_T; -+ -+#define RG_RX_A11 (RF_D_RX_REG_BASE + 0x2c) -+// Bit 6 :0 rg_wf_rxfe_gain_g1 U RW default = 'h12 -+// Bit 14 :8 rg_wf_rxfe_gain_g2 U RW default = 'h1a -+// Bit 22 :16 rg_wf_rxfe_gain_g3 U RW default = 'h32 -+// Bit 30 :24 rg_wf_rxfe_gain_g4 U RW default = 'h3a -+typedef union RG_RX_A11_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RXFE_GAIN_G1 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF_RXFE_GAIN_G2 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF_RXFE_GAIN_G3 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF_RXFE_GAIN_G4 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A11_FIELD_T; -+ -+#define RG_RX_A12 (RF_D_RX_REG_BASE + 0x30) -+// Bit 6 :0 rg_wf_rxfe_gain_g5 U RW default = 'h52 -+// Bit 14 :8 rg_wf_rxfe_gain_g6 U RW default = 'h5a -+// Bit 22 :16 rg_wf_rxfe_gain_g7 U RW default = 'h72 -+// Bit 30 :24 rg_wf_rxfe_gain_g8 U RW default = 'h7a -+typedef union RG_RX_A12_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RXFE_GAIN_G5 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF_RXFE_GAIN_G6 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF_RXFE_GAIN_G7 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF_RXFE_GAIN_G8 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A12_FIELD_T; -+ -+#define RG_RX_A13 (RF_D_RX_REG_BASE + 0x34) -+// Bit 6 :0 rg_wf_rxfe_gain_g9 U RW default = 'h7e -+// Bit 22 :8 rg_wf_rxfe_lpf_gain_man U RW default = 'h7ec -+// Bit 24 rg_wf_rxfe_lpf_gain_man_mode U RW default = 'h0 -+typedef union RG_RX_A13_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RXFE_GAIN_G9 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF_RXFE_LPF_GAIN_MAN : 15; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF_RXFE_LPF_GAIN_MAN_MODE : 1; -+ unsigned int rsvd_2 : 7; -+ } b; -+} RG_RX_A13_FIELD_T; -+ -+#define RG_RX_A14 (RF_D_RX_REG_BASE + 0x38) -+// Bit 2 :0 rg_wf5g_rx_lna_ictrl_g1 U RW default = 'h3 -+// Bit 6 :4 rg_wf5g_rx_lna_ictrl_g2 U RW default = 'h3 -+// Bit 10 :8 rg_wf5g_rx_lna_ictrl_g3 U RW default = 'h3 -+// Bit 14 :12 rg_wf5g_rx_lna_ictrl_g4 U RW default = 'h2 -+// Bit 18 :16 rg_wf5g_rx_lna_ictrl_g5 U RW default = 'h2 -+// Bit 22 :20 rg_wf5g_rx_lna_ictrl_g6 U RW default = 'h3 -+// Bit 26 :24 rg_wf5g_rx_lna_ictrl_g7 U RW default = 'h3 -+// Bit 30 :28 rg_wf5g_rx_lna_ictrl_man U RW default = 'h0 -+// Bit 31 rg_wf5g_rx_lna_ictrl_man_mode U RW default = 'h0 -+typedef union RG_RX_A14_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LNA_ICTRL_G1 : 3; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF5G_RX_LNA_ICTRL_G2 : 3; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF5G_RX_LNA_ICTRL_G3 : 3; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF5G_RX_LNA_ICTRL_G4 : 3; -+ unsigned int rsvd_3 : 1; -+ unsigned int RG_WF5G_RX_LNA_ICTRL_G5 : 3; -+ unsigned int rsvd_4 : 1; -+ unsigned int RG_WF5G_RX_LNA_ICTRL_G6 : 3; -+ unsigned int rsvd_5 : 1; -+ unsigned int RG_WF5G_RX_LNA_ICTRL_G7 : 3; -+ unsigned int rsvd_6 : 1; -+ unsigned int RG_WF5G_RX_LNA_ICTRL_MAN : 3; -+ unsigned int RG_WF5G_RX_LNA_ICTRL_MAN_MODE : 1; -+ } b; -+} RG_RX_A14_FIELD_T; -+ -+#define RG_RX_A15 (RF_D_RX_REG_BASE + 0x3c) -+// Bit 5 :0 rg_wf5g_rx_lna_slice_g1 U RW default = 'h1 -+// Bit 13 :8 rg_wf5g_rx_lna_slice_g2 U RW default = 'h1 -+// Bit 21 :16 rg_wf5g_rx_lna_slice_g3 U RW default = 'h2 -+// Bit 29 :24 rg_wf5g_rx_lna_slice_g4 U RW default = 'h4 -+typedef union RG_RX_A15_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LNA_SLICE_G1 : 6; -+ unsigned int rsvd_0 : 2; -+ unsigned int RG_WF5G_RX_LNA_SLICE_G2 : 6; -+ unsigned int rsvd_1 : 2; -+ unsigned int RG_WF5G_RX_LNA_SLICE_G3 : 6; -+ unsigned int rsvd_2 : 2; -+ unsigned int RG_WF5G_RX_LNA_SLICE_G4 : 6; -+ unsigned int rsvd_3 : 2; -+ } b; -+} RG_RX_A15_FIELD_T; -+ -+#define RG_RX_A16 (RF_D_RX_REG_BASE + 0x40) -+// Bit 5 :0 rg_wf5g_rx_lna_slice_g5 U RW default = 'hc -+// Bit 13 :8 rg_wf5g_rx_lna_slice_g6 U RW default = 'h1c -+// Bit 21 :16 rg_wf5g_rx_lna_slice_g7 U RW default = 'h3c -+// Bit 29 :24 rg_wf5g_rx_lna_slice_man U RW default = 'h0 -+// Bit 31 rg_wf5g_rx_lna_slice_man_mode U RW default = 'h0 -+typedef union RG_RX_A16_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LNA_SLICE_G5 : 6; -+ unsigned int rsvd_0 : 2; -+ unsigned int RG_WF5G_RX_LNA_SLICE_G6 : 6; -+ unsigned int rsvd_1 : 2; -+ unsigned int RG_WF5G_RX_LNA_SLICE_G7 : 6; -+ unsigned int rsvd_2 : 2; -+ unsigned int RG_WF5G_RX_LNA_SLICE_MAN : 6; -+ unsigned int rsvd_3 : 1; -+ unsigned int RG_WF5G_RX_LNA_SLICE_MAN_MODE : 1; -+ } b; -+} RG_RX_A16_FIELD_T; -+ -+#define RG_RX_A17 (RF_D_RX_REG_BASE + 0x44) -+// Bit 3 :0 rg_wf5g_rx_lna_rfb_lb_g1 U RW default = 'h5 -+// Bit 7 :4 rg_wf5g_rx_lna_rfb_lb_g2 U RW default = 'h2 -+// Bit 11 :8 rg_wf5g_rx_lna_rfb_lb_g3 U RW default = 'h4 -+// Bit 15 :12 rg_wf5g_rx_lna_rfb_lb_g4 U RW default = 'h7 -+// Bit 19 :16 rg_wf5g_rx_lna_rfb_lb_g5 U RW default = 'h7 -+// Bit 23 :20 rg_wf5g_rx_lna_rfb_lb_g6 U RW default = 'h7 -+// Bit 27 :24 rg_wf5g_rx_lna_rfb_lb_g7 U RW default = 'h0 -+// Bit 31 :28 rg_wf5g_rx_lna_rfb_hb_g1 U RW default = 'h2 -+typedef union RG_RX_A17_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LNA_RFB_LB_G1 : 4; -+ unsigned int RG_WF5G_RX_LNA_RFB_LB_G2 : 4; -+ unsigned int RG_WF5G_RX_LNA_RFB_LB_G3 : 4; -+ unsigned int RG_WF5G_RX_LNA_RFB_LB_G4 : 4; -+ unsigned int RG_WF5G_RX_LNA_RFB_LB_G5 : 4; -+ unsigned int RG_WF5G_RX_LNA_RFB_LB_G6 : 4; -+ unsigned int RG_WF5G_RX_LNA_RFB_LB_G7 : 4; -+ unsigned int RG_WF5G_RX_LNA_RFB_HB_G1 : 4; -+ } b; -+} RG_RX_A17_FIELD_T; -+ -+#define RG_RX_A18 (RF_D_RX_REG_BASE + 0x48) -+// Bit 3 :0 rg_wf5g_rx_lna_rfb_hb_g2 U RW default = 'h0 -+// Bit 7 :4 rg_wf5g_rx_lna_rfb_hb_g3 U RW default = 'h2 -+// Bit 11 :8 rg_wf5g_rx_lna_rfb_hb_g4 U RW default = 'h5 -+// Bit 15 :12 rg_wf5g_rx_lna_rfb_hb_g5 U RW default = 'h4 -+// Bit 19 :16 rg_wf5g_rx_lna_rfb_hb_g6 U RW default = 'h5 -+// Bit 23 :20 rg_wf5g_rx_lna_rfb_hb_g7 U RW default = 'h0 -+// Bit 27 :24 rg_wf5g_rx_lna_rfb_man U RW default = 'h0 -+// Bit 31 rg_wf5g_rx_lna_rfb_man_mode U RW default = 'h0 -+typedef union RG_RX_A18_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LNA_RFB_HB_G2 : 4; -+ unsigned int RG_WF5G_RX_LNA_RFB_HB_G3 : 4; -+ unsigned int RG_WF5G_RX_LNA_RFB_HB_G4 : 4; -+ unsigned int RG_WF5G_RX_LNA_RFB_HB_G5 : 4; -+ unsigned int RG_WF5G_RX_LNA_RFB_HB_G6 : 4; -+ unsigned int RG_WF5G_RX_LNA_RFB_HB_G7 : 4; -+ unsigned int RG_WF5G_RX_LNA_RFB_MAN : 4; -+ unsigned int rsvd_0 : 3; -+ unsigned int RG_WF5G_RX_LNA_RFB_MAN_MODE : 1; -+ } b; -+} RG_RX_A18_FIELD_T; -+ -+#define RG_RX_A19 (RF_D_RX_REG_BASE + 0x4c) -+// Bit 2 :0 rg_wf5g_rx_lna_rt_g1 U RW default = 'h5 -+// Bit 5 :3 rg_wf5g_rx_lna_rt_g2 U RW default = 'h7 -+// Bit 8 :6 rg_wf5g_rx_lna_rt_g3 U RW default = 'h5 -+// Bit 11 :9 rg_wf5g_rx_lna_rt_g4 U RW default = 'h5 -+// Bit 14 :12 rg_wf5g_rx_lna_rt_g5 U RW default = 'h3 -+// Bit 17 :15 rg_wf5g_rx_lna_rt_g6 U RW default = 'h1 -+// Bit 26 :24 rg_wf5g_rx_lna_rt_man U RW default = 'h0 -+// Bit 31 rg_wf5g_rx_lna_rt_man_mode U RW default = 'h0 -+typedef union RG_RX_A19_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LNA_RT_G1 : 3; -+ unsigned int RG_WF5G_RX_LNA_RT_G2 : 3; -+ unsigned int RG_WF5G_RX_LNA_RT_G3 : 3; -+ unsigned int RG_WF5G_RX_LNA_RT_G4 : 3; -+ unsigned int RG_WF5G_RX_LNA_RT_G5 : 3; -+ unsigned int RG_WF5G_RX_LNA_RT_G6 : 3; -+ unsigned int rsvd_0 : 6; -+ unsigned int RG_WF5G_RX_LNA_RT_MAN : 3; -+ unsigned int rsvd_1 : 4; -+ unsigned int RG_WF5G_RX_LNA_RT_MAN_MODE : 1; -+ } b; -+} RG_RX_A19_FIELD_T; -+ -+#define RG_RX_A20 (RF_D_RX_REG_BASE + 0x50) -+// Bit 2 :0 rg_wf5g_rx_lna_att_lb_g1 U RW default = 'h3 -+// Bit 5 :3 rg_wf5g_rx_lna_att_lb_g2 U RW default = 'h1 -+// Bit 8 :6 rg_wf5g_rx_lna_att_lb_g3 U RW default = 'h0 -+// Bit 11 :9 rg_wf5g_rx_lna_att_hb_g1 U RW default = 'h6 -+// Bit 14 :12 rg_wf5g_rx_lna_att_hb_g2 U RW default = 'h2 -+// Bit 17 :15 rg_wf5g_rx_lna_att_hb_g3 U RW default = 'h1 -+// Bit 26 :24 rg_wf5g_rx_lna_att_man U RW default = 'h0 -+// Bit 31 rg_wf5g_rx_lna_att_man_mode U RW default = 'h0 -+typedef union RG_RX_A20_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LNA_ATT_LB_G1 : 3; -+ unsigned int RG_WF5G_RX_LNA_ATT_LB_G2 : 3; -+ unsigned int RG_WF5G_RX_LNA_ATT_LB_G3 : 3; -+ unsigned int RG_WF5G_RX_LNA_ATT_HB_G1 : 3; -+ unsigned int RG_WF5G_RX_LNA_ATT_HB_G2 : 3; -+ unsigned int RG_WF5G_RX_LNA_ATT_HB_G3 : 3; -+ unsigned int rsvd_0 : 6; -+ unsigned int RG_WF5G_RX_LNA_ATT_MAN : 3; -+ unsigned int rsvd_1 : 4; -+ unsigned int RG_WF5G_RX_LNA_ATT_MAN_MODE : 1; -+ } b; -+} RG_RX_A20_FIELD_T; -+ -+#define RG_RX_A21 (RF_D_RX_REG_BASE + 0x54) -+// Bit 4 :0 rg_wf_rx_tia_cfix_sel_g1 U RW default = 'h1f -+// Bit 12 :8 rg_wf_rx_tia_cfix_sel_g2 U RW default = 'h1a -+// Bit 20 :16 rg_wf_rx_tia_cfix_sel_g3 U RW default = 'h14 -+// Bit 28 :24 rg_wf_rx_tia_cfix_sel_g4 U RW default = 'h1f -+typedef union RG_RX_A21_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_TIA_CFIX_SEL_G1 : 5; -+ unsigned int rsvd_0 : 3; -+ unsigned int RG_WF_RX_TIA_CFIX_SEL_G2 : 5; -+ unsigned int rsvd_1 : 3; -+ unsigned int RG_WF_RX_TIA_CFIX_SEL_G3 : 5; -+ unsigned int rsvd_2 : 3; -+ unsigned int RG_WF_RX_TIA_CFIX_SEL_G4 : 5; -+ unsigned int rsvd_3 : 3; -+ } b; -+} RG_RX_A21_FIELD_T; -+ -+#define RG_RX_A22 (RF_D_RX_REG_BASE + 0x58) -+// Bit 4 :0 rg_wf_rx_tia_cfix_sel_g5 U RW default = 'h1a -+// Bit 12 :8 rg_wf_rx_tia_cfix_sel_g6 U RW default = 'h14 -+// Bit 28 :24 rg_wf_rx_tia_cfix_sel_man U RW default = 'h0 -+// Bit 31 rg_wf_rx_tia_cfix_sel_man_mode U RW default = 'h0 -+typedef union RG_RX_A22_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_TIA_CFIX_SEL_G5 : 5; -+ unsigned int rsvd_0 : 3; -+ unsigned int RG_WF_RX_TIA_CFIX_SEL_G6 : 5; -+ unsigned int rsvd_1 : 11; -+ unsigned int RG_WF_RX_TIA_CFIX_SEL_MAN : 5; -+ unsigned int rsvd_2 : 2; -+ unsigned int RG_WF_RX_TIA_CFIX_SEL_MAN_MODE : 1; -+ } b; -+} RG_RX_A22_FIELD_T; -+ -+#define RG_RX_A23 (RF_D_RX_REG_BASE + 0x5c) -+// Bit 3 :0 rg_wf_rx_tia_cunit_sel_g1 U RW default = 'h5 -+// Bit 7 :4 rg_wf_rx_tia_cunit_sel_g2 U RW default = 'h3 -+// Bit 11 :8 rg_wf_rx_tia_cunit_sel_g3 U RW default = 'h3 -+// Bit 15 :12 rg_wf_rx_tia_cunit_sel_g4 U RW default = 'h2 -+// Bit 19 :16 rg_wf_rx_tia_cunit_sel_g5 U RW default = 'h1 -+// Bit 23 :20 rg_wf_rx_tia_cunit_sel_g6 U RW default = 'h1 -+// Bit 27 :24 rg_wf_rx_tia_cunit_sel_man U RW default = 'h0 -+// Bit 31 rg_wf_rx_tia_cunit_sel_man_mode U RW default = 'h0 -+typedef union RG_RX_A23_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_TIA_CUNIT_SEL_G1 : 4; -+ unsigned int RG_WF_RX_TIA_CUNIT_SEL_G2 : 4; -+ unsigned int RG_WF_RX_TIA_CUNIT_SEL_G3 : 4; -+ unsigned int RG_WF_RX_TIA_CUNIT_SEL_G4 : 4; -+ unsigned int RG_WF_RX_TIA_CUNIT_SEL_G5 : 4; -+ unsigned int RG_WF_RX_TIA_CUNIT_SEL_G6 : 4; -+ unsigned int RG_WF_RX_TIA_CUNIT_SEL_MAN : 4; -+ unsigned int rsvd_0 : 3; -+ unsigned int RG_WF_RX_TIA_CUNIT_SEL_MAN_MODE : 1; -+ } b; -+} RG_RX_A23_FIELD_T; -+ -+#define RG_RX_A24 (RF_D_RX_REG_BASE + 0x60) -+// Bit 3 :0 rg_wf_rx_lpf_sra_sel_bw20m U RW default = 'h1 -+// Bit 7 :4 rg_wf_rx_lpf_sra_sel_bw40m U RW default = 'h1 -+// Bit 11 :8 rg_wf_rx_lpf_sra_sel_bw80m U RW default = 'h3 -+// Bit 15 :12 rg_wf_rx_lpf_sra_sel_bw160m U RW default = 'h3 -+// Bit 27 :24 rg_wf_rx_lpf_sra_sel_man U RW default = 'h0 -+// Bit 31 rg_wf_rx_lpf_sra_sel_man_mode U RW default = 'h0 -+typedef union RG_RX_A24_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_LPF_SRA_SEL_BW20M : 4; -+ unsigned int RG_WF_RX_LPF_SRA_SEL_BW40M : 4; -+ unsigned int RG_WF_RX_LPF_SRA_SEL_BW80M : 4; -+ unsigned int RG_WF_RX_LPF_SRA_SEL_BW160M : 4; -+ unsigned int rsvd_0 : 8; -+ unsigned int RG_WF_RX_LPF_SRA_SEL_MAN : 4; -+ unsigned int rsvd_1 : 3; -+ unsigned int RG_WF_RX_LPF_SRA_SEL_MAN_MODE : 1; -+ } b; -+} RG_RX_A24_FIELD_T; -+ -+#define RG_RX_A25 (RF_D_RX_REG_BASE + 0x64) -+// Bit 3 :0 rg_wf_rx_lpf_sraq_sel_bw20m U RW default = 'h1 -+// Bit 7 :4 rg_wf_rx_lpf_sraq_sel_bw40m U RW default = 'h1 -+// Bit 11 :8 rg_wf_rx_lpf_sraq_sel_bw80m U RW default = 'h3 -+// Bit 15 :12 rg_wf_rx_lpf_sraq_sel_bw160m U RW default = 'h3 -+// Bit 27 :24 rg_wf_rx_lpf_sraq_sel_man U RW default = 'h0 -+// Bit 31 rg_wf_rx_lpf_sraq_sel_man_mode U RW default = 'h0 -+typedef union RG_RX_A25_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_LPF_SRAQ_SEL_BW20M : 4; -+ unsigned int RG_WF_RX_LPF_SRAQ_SEL_BW40M : 4; -+ unsigned int RG_WF_RX_LPF_SRAQ_SEL_BW80M : 4; -+ unsigned int RG_WF_RX_LPF_SRAQ_SEL_BW160M : 4; -+ unsigned int rsvd_0 : 8; -+ unsigned int RG_WF_RX_LPF_SRAQ_SEL_MAN : 4; -+ unsigned int rsvd_1 : 3; -+ unsigned int RG_WF_RX_LPF_SRAQ_SEL_MAN_MODE : 1; -+ } b; -+} RG_RX_A25_FIELD_T; -+ -+#define RG_RX_A26 (RF_D_RX_REG_BASE + 0x68) -+// Bit 4 :0 rg_wf_rx_lpf_cfix_sel_bw20m U RW default = 'h1a -+// Bit 9 :5 rg_wf_rx_lpf_cfix_sel_bw40m U RW default = 'h1a -+// Bit 14 :10 rg_wf_rx_lpf_cfix_sel_bw80m U RW default = 'h1a -+// Bit 19 :15 rg_wf_rx_lpf_cfix_sel_bw160m U RW default = 'h1a -+// Bit 24 :20 rg_wf_rx_lpf_cfix_sel_man U RW default = 'h0 -+// Bit 31 rg_wf_rx_lpf_cfix_sel_man_mode U RW default = 'h0 -+typedef union RG_RX_A26_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_LPF_CFIX_SEL_BW20M : 5; -+ unsigned int RG_WF_RX_LPF_CFIX_SEL_BW40M : 5; -+ unsigned int RG_WF_RX_LPF_CFIX_SEL_BW80M : 5; -+ unsigned int RG_WF_RX_LPF_CFIX_SEL_BW160M : 5; -+ unsigned int RG_WF_RX_LPF_CFIX_SEL_MAN : 5; -+ unsigned int rsvd_0 : 6; -+ unsigned int RG_WF_RX_LPF_CFIX_SEL_MAN_MODE : 1; -+ } b; -+} RG_RX_A26_FIELD_T; -+ -+#define RG_RX_A27 (RF_D_RX_REG_BASE + 0x6c) -+// Bit 2 :0 rg_wf_rx_lpf_c1unit_sel_bw20m U RW default = 'h5 -+// Bit 6 :4 rg_wf_rx_lpf_c1unit_sel_bw40m U RW default = 'h2 -+// Bit 10 :8 rg_wf_rx_lpf_c1unit_sel_bw80m U RW default = 'h2 -+// Bit 14 :12 rg_wf_rx_lpf_c1unit_sel_bw160m U RW default = 'h0 -+// Bit 18 :16 rg_wf_rx_lpf_c1unit_sel_man U RW default = 'h0 -+// Bit 20 rg_wf_rx_lpf_c1unit_sel_man_mode U RW default = 'h0 -+typedef union RG_RX_A27_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_LPF_C1UNIT_SEL_BW20M : 3; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF_RX_LPF_C1UNIT_SEL_BW40M : 3; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF_RX_LPF_C1UNIT_SEL_BW80M : 3; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF_RX_LPF_C1UNIT_SEL_BW160M : 3; -+ unsigned int rsvd_3 : 1; -+ unsigned int RG_WF_RX_LPF_C1UNIT_SEL_MAN : 3; -+ unsigned int rsvd_4 : 1; -+ unsigned int RG_WF_RX_LPF_C1UNIT_SEL_MAN_MODE : 1; -+ unsigned int rsvd_5 : 11; -+ } b; -+} RG_RX_A27_FIELD_T; -+ -+#define RG_RX_A28 (RF_D_RX_REG_BASE + 0x70) -+// Bit 2 :0 rg_wf_rx_lpf_c2unit_sel_bw20m U RW default = 'h5 -+// Bit 6 :4 rg_wf_rx_lpf_c2unit_sel_bw40m U RW default = 'h2 -+// Bit 10 :8 rg_wf_rx_lpf_c2unit_sel_bw80m U RW default = 'h2 -+// Bit 14 :12 rg_wf_rx_lpf_c2unit_sel_bw160m U RW default = 'h0 -+// Bit 18 :16 rg_wf_rx_lpf_c2unit_sel_man U RW default = 'h0 -+// Bit 20 rg_wf_rx_lpf_c2unit_sel_man_mode U RW default = 'h0 -+typedef union RG_RX_A28_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_LPF_C2UNIT_SEL_BW20M : 3; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF_RX_LPF_C2UNIT_SEL_BW40M : 3; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF_RX_LPF_C2UNIT_SEL_BW80M : 3; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF_RX_LPF_C2UNIT_SEL_BW160M : 3; -+ unsigned int rsvd_3 : 1; -+ unsigned int RG_WF_RX_LPF_C2UNIT_SEL_MAN : 3; -+ unsigned int rsvd_4 : 1; -+ unsigned int RG_WF_RX_LPF_C2UNIT_SEL_MAN_MODE : 1; -+ unsigned int rsvd_5 : 11; -+ } b; -+} RG_RX_A28_FIELD_T; -+ -+#define RG_RX_A29 (RF_D_RX_REG_BASE + 0x74) -+// Bit 3 :0 rg_wf_rx_lpf_rn_sel_bw20madc160m U RW default = 'h1 -+// Bit 7 :4 rg_wf_rx_lpf_rn_sel_bw40madc160m U RW default = 'h1 -+// Bit 11 :8 rg_wf_rx_lpf_rn_sel_bw80madc160m U RW default = 'h3 -+// Bit 15 :12 rg_wf_rx_lpf_rn_sel_bw80madc320m U RW default = 'h3 -+// Bit 19 :16 rg_wf_rx_lpf_rn_sel_bw160madc320m U RW default = 'h3 -+// Bit 23 :20 rg_wf_rx_lpf_rn_sel_man U RW default = 'h0 -+// Bit 31 rg_wf_rx_lpf_rn_sel_man_mode U RW default = 'h0 -+typedef union RG_RX_A29_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_LPF_RN_SEL_BW20MADC160M : 4; -+ unsigned int RG_WF_RX_LPF_RN_SEL_BW40MADC160M : 4; -+ unsigned int RG_WF_RX_LPF_RN_SEL_BW80MADC160M : 4; -+ unsigned int RG_WF_RX_LPF_RN_SEL_BW80MADC320M : 4; -+ unsigned int RG_WF_RX_LPF_RN_SEL_BW160MADC320M : 4; -+ unsigned int RG_WF_RX_LPF_RN_SEL_MAN : 4; -+ unsigned int rsvd_0 : 7; -+ unsigned int RG_WF_RX_LPF_RN_SEL_MAN_MODE : 1; -+ } b; -+} RG_RX_A29_FIELD_T; -+ -+#define RG_RX_A30 (RF_D_RX_REG_BASE + 0x78) -+// Bit 2 :0 rg_wf_rx_lpf_cn_sel_bw20madc160m U RW default = 'h3 -+// Bit 6 :4 rg_wf_rx_lpf_cn_sel_bw40madc160m U RW default = 'h3 -+// Bit 10 :8 rg_wf_rx_lpf_cn_sel_bw80madc160m U RW default = 'h3 -+// Bit 14 :12 rg_wf_rx_lpf_cn_sel_bw80madc320m U RW default = 'h1 -+// Bit 18 :16 rg_wf_rx_lpf_cn_sel_bw160madc320m U RW default = 'h0 -+// Bit 22 :20 rg_wf_rx_lpf_cn_sel_man U RW default = 'h0 -+// Bit 31 rg_wf_rx_lpf_cn_sel_man_mode U RW default = 'h0 -+typedef union RG_RX_A30_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_LPF_CN_SEL_BW20MADC160M : 3; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF_RX_LPF_CN_SEL_BW40MADC160M : 3; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF_RX_LPF_CN_SEL_BW80MADC160M : 3; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF_RX_LPF_CN_SEL_BW80MADC320M : 3; -+ unsigned int rsvd_3 : 1; -+ unsigned int RG_WF_RX_LPF_CN_SEL_BW160MADC320M : 3; -+ unsigned int rsvd_4 : 1; -+ unsigned int RG_WF_RX_LPF_CN_SEL_MAN : 3; -+ unsigned int rsvd_5 : 8; -+ unsigned int RG_WF_RX_LPF_CN_SEL_MAN_MODE : 1; -+ } b; -+} RG_RX_A30_FIELD_T; -+ -+#define RG_RX_A31 (RF_D_RX_REG_BASE + 0x7c) -+// Bit 4 :0 rg_wf_rx_lpf_cnfix_sel_bw20madc160m U RW default = 'h1a -+// Bit 9 :5 rg_wf_rx_lpf_cnfix_sel_bw40madc160m U RW default = 'h1a -+// Bit 14 :10 rg_wf_rx_lpf_cnfix_sel_bw80madc160m U RW default = 'h1a -+// Bit 19 :15 rg_wf_rx_lpf_cnfix_sel_bw80madc320m U RW default = 'h1a -+// Bit 24 :20 rg_wf_rx_lpf_cnfix_sel_bw160madc320m U RW default = 'h1a -+// Bit 29 :25 rg_wf_rx_lpf_cnfix_sel_man U RW default = 'h0 -+// Bit 31 rg_wf_rx_lpf_cnfix_sel_man_mode U RW default = 'h0 -+typedef union RG_RX_A31_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_LPF_CNFIX_SEL_BW20MADC160M : 5; -+ unsigned int RG_WF_RX_LPF_CNFIX_SEL_BW40MADC160M : 5; -+ unsigned int RG_WF_RX_LPF_CNFIX_SEL_BW80MADC160M : 5; -+ unsigned int RG_WF_RX_LPF_CNFIX_SEL_BW80MADC320M : 5; -+ unsigned int RG_WF_RX_LPF_CNFIX_SEL_BW160MADC320M : 5; -+ unsigned int RG_WF_RX_LPF_CNFIX_SEL_MAN : 5; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF_RX_LPF_CNFIX_SEL_MAN_MODE : 1; -+ } b; -+} RG_RX_A31_FIELD_T; -+ -+#define RG_RX_A32 (RF_D_RX_REG_BASE + 0x80) -+// Bit 6 :0 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg1 U RW default = 'h40 -+// Bit 14 :8 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg2 U RW default = 'h40 -+// Bit 22 :16 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg3 U RW default = 'h40 -+// Bit 30 :24 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg4 U RW default = 'h40 -+typedef union RG_RX_A32_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG1 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG2 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG3 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG4 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A32_FIELD_T; -+ -+#define RG_RX_A33 (RF_D_RX_REG_BASE + 0x84) -+// Bit 6 :0 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg5 U RW default = 'h40 -+// Bit 14 :8 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg6 U RW default = 'h40 -+// Bit 22 :16 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg7 U RW default = 'h40 -+// Bit 30 :24 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg8 U RW default = 'h40 -+typedef union RG_RX_A33_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG5 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG6 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG7 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG8 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A33_FIELD_T; -+ -+#define RG_RX_A34 (RF_D_RX_REG_BASE + 0x88) -+// Bit 6 :0 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg9 U RW default = 'h40 -+// Bit 14 :8 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg10 U RW default = 'h40 -+// Bit 22 :16 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg11 U RW default = 'h40 -+// Bit 30 :24 rg_wf5g_rx_lpf_i_dcoc_sel_tialglpfg12 U RW default = 'h40 -+typedef union RG_RX_A34_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG9 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG10 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG11 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIALGLPFG12 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A34_FIELD_T; -+ -+#define RG_RX_A35 (RF_D_RX_REG_BASE + 0x8c) -+// Bit 6 :0 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg1 U RW default = 'h40 -+// Bit 14 :8 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg2 U RW default = 'h40 -+// Bit 22 :16 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg3 U RW default = 'h40 -+// Bit 30 :24 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg4 U RW default = 'h40 -+typedef union RG_RX_A35_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG1 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG2 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG3 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG4 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A35_FIELD_T; -+ -+#define RG_RX_A36 (RF_D_RX_REG_BASE + 0x90) -+// Bit 6 :0 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg5 U RW default = 'h40 -+// Bit 14 :8 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg6 U RW default = 'h40 -+// Bit 22 :16 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg7 U RW default = 'h40 -+// Bit 30 :24 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg8 U RW default = 'h40 -+typedef union RG_RX_A36_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG5 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG6 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG7 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG8 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A36_FIELD_T; -+ -+#define RG_RX_A37 (RF_D_RX_REG_BASE + 0x94) -+// Bit 6 :0 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg9 U RW default = 'h40 -+// Bit 14 :8 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg10 U RW default = 'h40 -+// Bit 22 :16 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg11 U RW default = 'h40 -+// Bit 30 :24 rg_wf5g_rx_lpf_i_dcoc_sel_tiahglpfg12 U RW default = 'h40 -+typedef union RG_RX_A37_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG9 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG10 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG11 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF5G_RX_LPF_I_DCOC_SEL_TIAHGLPFG12 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A37_FIELD_T; -+ -+#define RG_RX_A38 (RF_D_RX_REG_BASE + 0x98) -+// Bit 6 :0 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg1 U RW default = 'h40 -+// Bit 14 :8 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg2 U RW default = 'h40 -+// Bit 22 :16 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg3 U RW default = 'h40 -+// Bit 30 :24 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg4 U RW default = 'h40 -+typedef union RG_RX_A38_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG1 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG2 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG3 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG4 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A38_FIELD_T; -+ -+#define RG_RX_A39 (RF_D_RX_REG_BASE + 0x9c) -+// Bit 6 :0 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg5 U RW default = 'h40 -+// Bit 14 :8 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg6 U RW default = 'h40 -+// Bit 22 :16 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg7 U RW default = 'h40 -+// Bit 30 :24 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg8 U RW default = 'h40 -+typedef union RG_RX_A39_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG5 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG6 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG7 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG8 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A39_FIELD_T; -+ -+#define RG_RX_A40 (RF_D_RX_REG_BASE + 0xa0) -+// Bit 6 :0 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg9 U RW default = 'h40 -+// Bit 14 :8 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg10 U RW default = 'h40 -+// Bit 22 :16 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg11 U RW default = 'h40 -+// Bit 30 :24 rg_wf5g_rx_lpf_q_dcoc_sel_tialglpfg12 U RW default = 'h40 -+typedef union RG_RX_A40_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG9 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG10 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG11 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIALGLPFG12 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A40_FIELD_T; -+ -+#define RG_RX_A41 (RF_D_RX_REG_BASE + 0xa4) -+// Bit 6 :0 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg1 U RW default = 'h40 -+// Bit 14 :8 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg2 U RW default = 'h40 -+// Bit 22 :16 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg3 U RW default = 'h40 -+// Bit 30 :24 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg4 U RW default = 'h40 -+typedef union RG_RX_A41_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG1 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG2 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG3 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG4 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A41_FIELD_T; -+ -+#define RG_RX_A42 (RF_D_RX_REG_BASE + 0xa8) -+// Bit 6 :0 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg5 U RW default = 'h40 -+// Bit 14 :8 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg6 U RW default = 'h40 -+// Bit 22 :16 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg7 U RW default = 'h40 -+// Bit 30 :24 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg8 U RW default = 'h40 -+typedef union RG_RX_A42_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG5 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG6 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG7 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG8 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A42_FIELD_T; -+ -+#define RG_RX_A43 (RF_D_RX_REG_BASE + 0xac) -+// Bit 6 :0 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg9 U RW default = 'h40 -+// Bit 14 :8 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg10 U RW default = 'h40 -+// Bit 22 :16 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg11 U RW default = 'h40 -+// Bit 30 :24 rg_wf5g_rx_lpf_q_dcoc_sel_tiahglpfg12 U RW default = 'h40 -+typedef union RG_RX_A43_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG9 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG10 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG11 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF5G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG12 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A43_FIELD_T; -+ -+#define RG_RX_A44 (RF_D_RX_REG_BASE + 0xb0) -+// Bit 6 :0 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg1 U RW default = 'h40 -+// Bit 14 :8 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg2 U RW default = 'h40 -+// Bit 22 :16 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg3 U RW default = 'h40 -+// Bit 30 :24 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg4 U RW default = 'h40 -+typedef union RG_RX_A44_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG1 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG2 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG3 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG4 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A44_FIELD_T; -+ -+#define RG_RX_A45 (RF_D_RX_REG_BASE + 0xb4) -+// Bit 6 :0 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg5 U RW default = 'h40 -+// Bit 14 :8 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg6 U RW default = 'h40 -+// Bit 22 :16 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg7 U RW default = 'h40 -+// Bit 30 :24 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg8 U RW default = 'h40 -+typedef union RG_RX_A45_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG5 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG6 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG7 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG8 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A45_FIELD_T; -+ -+#define RG_RX_A46 (RF_D_RX_REG_BASE + 0xb8) -+// Bit 6 :0 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg9 U RW default = 'h40 -+// Bit 14 :8 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg10 U RW default = 'h40 -+// Bit 22 :16 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg11 U RW default = 'h40 -+// Bit 30 :24 rg_wf2g_rx_lpf_i_dcoc_sel_tialglpfg12 U RW default = 'h40 -+typedef union RG_RX_A46_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG9 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG10 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG11 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIALGLPFG12 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A46_FIELD_T; -+ -+#define RG_RX_A47 (RF_D_RX_REG_BASE + 0xbc) -+// Bit 6 :0 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg1 U RW default = 'h40 -+// Bit 14 :8 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg2 U RW default = 'h40 -+// Bit 22 :16 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg3 U RW default = 'h40 -+// Bit 30 :24 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg4 U RW default = 'h40 -+typedef union RG_RX_A47_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG1 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG2 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG3 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG4 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A47_FIELD_T; -+ -+#define RG_RX_A48 (RF_D_RX_REG_BASE + 0xc0) -+// Bit 6 :0 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg5 U RW default = 'h40 -+// Bit 14 :8 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg6 U RW default = 'h40 -+// Bit 22 :16 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg7 U RW default = 'h40 -+// Bit 30 :24 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg8 U RW default = 'h40 -+typedef union RG_RX_A48_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG5 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG6 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG7 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG8 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A48_FIELD_T; -+ -+#define RG_RX_A49 (RF_D_RX_REG_BASE + 0xc4) -+// Bit 6 :0 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg9 U RW default = 'h40 -+// Bit 14 :8 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg10 U RW default = 'h40 -+// Bit 22 :16 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg11 U RW default = 'h40 -+// Bit 30 :24 rg_wf2g_rx_lpf_i_dcoc_sel_tiahglpfg12 U RW default = 'h40 -+typedef union RG_RX_A49_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG9 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG10 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG11 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF2G_RX_LPF_I_DCOC_SEL_TIAHGLPFG12 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A49_FIELD_T; -+ -+#define RG_RX_A50 (RF_D_RX_REG_BASE + 0xc8) -+// Bit 6 :0 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg1 U RW default = 'h40 -+// Bit 14 :8 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg2 U RW default = 'h40 -+// Bit 22 :16 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg3 U RW default = 'h40 -+// Bit 30 :24 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg4 U RW default = 'h40 -+typedef union RG_RX_A50_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG1 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG2 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG3 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG4 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A50_FIELD_T; -+ -+#define RG_RX_A51 (RF_D_RX_REG_BASE + 0xcc) -+// Bit 6 :0 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg5 U RW default = 'h40 -+// Bit 14 :8 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg6 U RW default = 'h40 -+// Bit 22 :16 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg7 U RW default = 'h40 -+// Bit 30 :24 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg8 U RW default = 'h40 -+typedef union RG_RX_A51_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG5 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG6 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG7 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG8 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A51_FIELD_T; -+ -+#define RG_RX_A52 (RF_D_RX_REG_BASE + 0xd0) -+// Bit 6 :0 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg9 U RW default = 'h40 -+// Bit 14 :8 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg10 U RW default = 'h40 -+// Bit 22 :16 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg11 U RW default = 'h40 -+// Bit 30 :24 rg_wf2g_rx_lpf_q_dcoc_sel_tialglpfg12 U RW default = 'h40 -+typedef union RG_RX_A52_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG9 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG10 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG11 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIALGLPFG12 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A52_FIELD_T; -+ -+#define RG_RX_A53 (RF_D_RX_REG_BASE + 0xd4) -+// Bit 6 :0 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg1 U RW default = 'h40 -+// Bit 14 :8 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg2 U RW default = 'h40 -+// Bit 22 :16 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg3 U RW default = 'h40 -+// Bit 30 :24 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg4 U RW default = 'h40 -+typedef union RG_RX_A53_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG1 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG2 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG3 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG4 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A53_FIELD_T; -+ -+#define RG_RX_A54 (RF_D_RX_REG_BASE + 0xd8) -+// Bit 6 :0 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg5 U RW default = 'h40 -+// Bit 14 :8 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg6 U RW default = 'h40 -+// Bit 22 :16 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg7 U RW default = 'h40 -+// Bit 30 :24 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg8 U RW default = 'h40 -+typedef union RG_RX_A54_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG5 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG6 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG7 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG8 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A54_FIELD_T; -+ -+#define RG_RX_A55 (RF_D_RX_REG_BASE + 0xdc) -+// Bit 6 :0 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg9 U RW default = 'h40 -+// Bit 14 :8 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg10 U RW default = 'h40 -+// Bit 22 :16 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg11 U RW default = 'h40 -+// Bit 30 :24 rg_wf2g_rx_lpf_q_dcoc_sel_tiahglpfg12 U RW default = 'h40 -+typedef union RG_RX_A55_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG9 : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG10 : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG11 : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF2G_RX_LPF_Q_DCOC_SEL_TIAHGLPFG12 : 7; -+ unsigned int rsvd_3 : 1; -+ } b; -+} RG_RX_A55_FIELD_T; -+ -+#define RG_RX_A56 (RF_D_RX_REG_BASE + 0xe0) -+// Bit 6 :0 rg_wf_rx_lpf_i_dcoc_sel_man U RW default = 'h40 -+// Bit 8 rg_wf_rx_lpf_i_dcoc_sel_man_mode U RW default = 'h0 -+// Bit 22 :16 rg_wf_rx_lpf_q_dcoc_sel_man U RW default = 'h40 -+// Bit 24 rg_wf_rx_lpf_q_dcoc_sel_man_mode U RW default = 'h0 -+typedef union RG_RX_A56_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_LPF_I_DCOC_SEL_MAN : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF_RX_LPF_I_DCOC_SEL_MAN_MODE : 1; -+ unsigned int rsvd_1 : 7; -+ unsigned int RG_WF_RX_LPF_Q_DCOC_SEL_MAN : 7; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF_RX_LPF_Q_DCOC_SEL_MAN_MODE : 1; -+ unsigned int rsvd_3 : 7; -+ } b; -+} RG_RX_A56_FIELD_T; -+ -+#define RG_RX_A57 (RF_D_RX_REG_BASE + 0xe4) -+// Bit 1 :0 rg_wf_rx_rck_t1 U RW default = 'h0 -+// Bit 3 :2 rg_wf_rx_rck_t2 U RW default = 'h0 -+// Bit 5 :4 rg_wf_rx_rck_t3 U RW default = 'h0 -+// Bit 7 :6 rg_wf_rx_rck_t4 U RW default = 'h0 -+// Bit 9 :8 rg_wf_rx_rck_t5 U RW default = 'h0 -+// Bit 11 :10 rg_wf_rx_rck_t6 U RW default = 'h0 -+// Bit 22 :20 rg_wf_rx_rck_refsel_man U RW default = 'h1 -+// Bit 24 rg_wf_rx_rck_refsel_man_mode U RW default = 'h0 -+// Bit 31 rg_wf_rx_rck_cali_en U RW default = 'h0 -+typedef union RG_RX_A57_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_RCK_T1 : 2; -+ unsigned int RG_WF_RX_RCK_T2 : 2; -+ unsigned int RG_WF_RX_RCK_T3 : 2; -+ unsigned int RG_WF_RX_RCK_T4 : 2; -+ unsigned int RG_WF_RX_RCK_T5 : 2; -+ unsigned int RG_WF_RX_RCK_T6 : 2; -+ unsigned int rsvd_0 : 8; -+ unsigned int RG_WF_RX_RCK_REFSEL_MAN : 3; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF_RX_RCK_REFSEL_MAN_MODE : 1; -+ unsigned int rsvd_2 : 6; -+ unsigned int RG_WF_RX_RCK_CALI_EN : 1; -+ } b; -+} RG_RX_A57_FIELD_T; -+ -+#define RG_RX_A58 (RF_D_RX_REG_BASE + 0xe8) -+// Bit 3 :0 rg_wf_rx_lpf_rck_ioffset_bw20m U RW default = 'h0 -+// Bit 7 :4 rg_wf_rx_lpf_rck_ioffset_bw40m U RW default = 'h0 -+// Bit 11 :8 rg_wf_rx_lpf_rck_ioffset_bw80m U RW default = 'h0 -+// Bit 15 :12 rg_wf_rx_lpf_rck_ioffset_bw160m U RW default = 'h0 -+// Bit 26 :20 rg_wf_rx_lpf_ctune_isel_man U RW default = 'h0 -+// Bit 31 rg_wf_rx_lpf_ctune_isel_man_mode U RW default = 'h0 -+typedef union RG_RX_A58_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_LPF_RCK_IOFFSET_BW20M : 4; -+ unsigned int RG_WF_RX_LPF_RCK_IOFFSET_BW40M : 4; -+ unsigned int RG_WF_RX_LPF_RCK_IOFFSET_BW80M : 4; -+ unsigned int RG_WF_RX_LPF_RCK_IOFFSET_BW160M : 4; -+ unsigned int rsvd_0 : 4; -+ unsigned int RG_WF_RX_LPF_CTUNE_ISEL_MAN : 7; -+ unsigned int rsvd_1 : 4; -+ unsigned int RG_WF_RX_LPF_CTUNE_ISEL_MAN_MODE : 1; -+ } b; -+} RG_RX_A58_FIELD_T; -+ -+#define RG_RX_A59 (RF_D_RX_REG_BASE + 0xec) -+// Bit 3 :0 rg_wf_rx_lpf_rck_qoffset_bw20m U RW default = 'h0 -+// Bit 7 :4 rg_wf_rx_lpf_rck_qoffset_bw40m U RW default = 'h0 -+// Bit 11 :8 rg_wf_rx_lpf_rck_qoffset_bw80m U RW default = 'h0 -+// Bit 15 :12 rg_wf_rx_lpf_rck_qoffset_bw160m U RW default = 'h0 -+// Bit 26 :20 rg_wf_rx_lpf_ctune_qsel_man U RW default = 'h0 -+// Bit 31 rg_wf_rx_lpf_ctune_qsel_man_mode U RW default = 'h0 -+typedef union RG_RX_A59_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_LPF_RCK_QOFFSET_BW20M : 4; -+ unsigned int RG_WF_RX_LPF_RCK_QOFFSET_BW40M : 4; -+ unsigned int RG_WF_RX_LPF_RCK_QOFFSET_BW80M : 4; -+ unsigned int RG_WF_RX_LPF_RCK_QOFFSET_BW160M : 4; -+ unsigned int rsvd_0 : 4; -+ unsigned int RG_WF_RX_LPF_CTUNE_QSEL_MAN : 7; -+ unsigned int rsvd_1 : 4; -+ unsigned int RG_WF_RX_LPF_CTUNE_QSEL_MAN_MODE : 1; -+ } b; -+} RG_RX_A59_FIELD_T; -+ -+#define RG_RX_A60 (RF_D_RX_REG_BASE + 0xf0) -+// Bit 3 :0 rg_wf_rx_tia_rck_ioffset U RW default = 'h0 -+// Bit 10 :4 rg_wf_rx_tia_ctune_isel_man U RW default = 'h0 -+// Bit 15 rg_wf_rx_tia_ctune_isel_man_mode U RW default = 'h0 -+// Bit 19 :16 rg_wf_rx_tia_rck_qoffset U RW default = 'h0 -+// Bit 26 :20 rg_wf_rx_tia_ctune_qsel_man U RW default = 'h0 -+// Bit 31 rg_wf_rx_tia_ctune_qsel_man_mode U RW default = 'h0 -+typedef union RG_RX_A60_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_TIA_RCK_IOFFSET : 4; -+ unsigned int RG_WF_RX_TIA_CTUNE_ISEL_MAN : 7; -+ unsigned int rsvd_0 : 4; -+ unsigned int RG_WF_RX_TIA_CTUNE_ISEL_MAN_MODE : 1; -+ unsigned int RG_WF_RX_TIA_RCK_QOFFSET : 4; -+ unsigned int RG_WF_RX_TIA_CTUNE_QSEL_MAN : 7; -+ unsigned int rsvd_1 : 4; -+ unsigned int RG_WF_RX_TIA_CTUNE_QSEL_MAN_MODE : 1; -+ } b; -+} RG_RX_A60_FIELD_T; -+ -+#define RG_RX_A61 (RF_D_RX_REG_BASE + 0xf4) -+// Bit 3 :0 rg_wf_rx_lpf_notch_rck_offset_adc160m U RW default = 'h0 -+// Bit 10 :4 rg_wf_rx_lpf_notch_ctune_sel_man U RW default = 'h0 -+// Bit 15 rg_wf_rx_lpf_notch_ctune_sel_man_mode U RW default = 'h0 -+// Bit 19 :16 rg_wf_rx_lpf_notch_rck_offset_adc320m U RW default = 'h0 -+typedef union RG_RX_A61_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_LPF_NOTCH_RCK_OFFSET_ADC160M : 4; -+ unsigned int RG_WF_RX_LPF_NOTCH_CTUNE_SEL_MAN : 7; -+ unsigned int rsvd_0 : 4; -+ unsigned int RG_WF_RX_LPF_NOTCH_CTUNE_SEL_MAN_MODE : 1; -+ unsigned int RG_WF_RX_LPF_NOTCH_RCK_OFFSET_ADC320M : 4; -+ unsigned int rsvd_1 : 12; -+ } b; -+} RG_RX_A61_FIELD_T; -+ -+#define RG_RX_A62 (RF_D_RX_REG_BASE + 0xf8) -+// Bit 3 :0 rg_wf_rx_rssipga_rck_ioffset U RW default = 'h0 -+// Bit 10 :4 rg_wf_rx_rssipga_ctune_isel_man U RW default = 'h0 -+// Bit 15 rg_wf_rx_rssipga_ctune_isel_man_mode U RW default = 'h0 -+// Bit 19 :16 rg_wf_rx_rssipga_rck_qoffset U RW default = 'h0 -+// Bit 26 :20 rg_wf_rx_rssipga_ctune_qsel_man U RW default = 'h0 -+// Bit 31 rg_wf_rx_rssipga_ctune_qsel_man_mode U RW default = 'h0 -+typedef union RG_RX_A62_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_RSSIPGA_RCK_IOFFSET : 4; -+ unsigned int RG_WF_RX_RSSIPGA_CTUNE_ISEL_MAN : 7; -+ unsigned int rsvd_0 : 4; -+ unsigned int RG_WF_RX_RSSIPGA_CTUNE_ISEL_MAN_MODE : 1; -+ unsigned int RG_WF_RX_RSSIPGA_RCK_QOFFSET : 4; -+ unsigned int RG_WF_RX_RSSIPGA_CTUNE_QSEL_MAN : 7; -+ unsigned int rsvd_1 : 4; -+ unsigned int RG_WF_RX_RSSIPGA_CTUNE_QSEL_MAN_MODE : 1; -+ } b; -+} RG_RX_A62_FIELD_T; -+ -+#define RG_RX_A63 (RF_D_RX_REG_BASE + 0xfc) -+// Bit 6 :0 ro_wf_rx_rck U RO default = 'h0 -+// Bit 8 ro_wf_rx_rck_vld U RO default = 'h0 -+typedef union RG_RX_A63_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RO_WF_RX_RCK : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RO_WF_RX_RCK_VLD : 1; -+ unsigned int rsvd_1 : 23; -+ } b; -+} RG_RX_A63_FIELD_T; -+ -+#define RG_RX_A64 (RF_D_RX_REG_BASE + 0x100) -+// Bit 0 rg_wf_rx_rssipga_sca_en U RW default = 'h1 -+// Bit 5 :1 rg_wf_rx_rssipga_cfix_sel U RW default = 'h1a -+// Bit 8 :6 rg_wf_rx_rssipga_ictrl U RW default = 'h3 -+// Bit 11 :9 rg_wf_rx_rssipga_ictrl_agclock U RW default = 'h0 -+// Bit 15 :12 rg_wf_rx_rssipga_drvctrl U RW default = 'h3 -+// Bit 19 :16 rg_wf_rx_rssipga_drvctrl_agclock U RW default = 'h0 -+// Bit 21 :20 rg_wf_rx_rssipga_drv U RW default = 'h1 -+// Bit 23 :22 rg_wf_rx_rssipga_drv_agclock U RW default = 'h0 -+// Bit 26 :24 rg_wf_rx_rssipga_vcmsel U RW default = 'h4 -+// Bit 29 :27 rg_wf_rx_rssipga_gain U RW default = 'h0 -+typedef union RG_RX_A64_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_RSSIPGA_SCA_EN : 1; -+ unsigned int RG_WF_RX_RSSIPGA_CFIX_SEL : 5; -+ unsigned int RG_WF_RX_RSSIPGA_ICTRL : 3; -+ unsigned int RG_WF_RX_RSSIPGA_ICTRL_AGCLOCK : 3; -+ unsigned int RG_WF_RX_RSSIPGA_DRVCTRL : 4; -+ unsigned int RG_WF_RX_RSSIPGA_DRVCTRL_AGCLOCK : 4; -+ unsigned int RG_WF_RX_RSSIPGA_DRV : 2; -+ unsigned int RG_WF_RX_RSSIPGA_DRV_AGCLOCK : 2; -+ unsigned int RG_WF_RX_RSSIPGA_VCMSEL : 3; -+ unsigned int RG_WF_RX_RSSIPGA_GAIN : 3; -+ unsigned int rsvd_0 : 2; -+ } b; -+} RG_RX_A64_FIELD_T; -+ -+#define RG_RX_A65 (RF_D_RX_REG_BASE + 0x104) -+// Bit 0 rg_wf_rx_irrcalfrom_tx_en U RW default = 'h1 -+// Bit 3 :1 rg_wf5g_rx_irrcal_buf_ictrl U RW default = 'h3 -+// Bit 6 :4 rg_wf5g_rx_lna_cal_att U RW default = 'h0 -+// Bit 9 :7 rg_wf2g_rx_irrcal_buf_ictrl U RW default = 'h3 -+// Bit 12 :10 rg_wf2g_rx_lna_cal_att U RW default = 'h2 -+// Bit 15 :13 rg_wf_rx_gm_vcmsel U RW default = 'h4 -+typedef union RG_RX_A65_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_IRRCALFROM_TX_EN : 1; -+ unsigned int RG_WF5G_RX_IRRCAL_BUF_ICTRL : 3; -+ unsigned int RG_WF5G_RX_LNA_CAL_ATT : 3; -+ unsigned int RG_WF2G_RX_IRRCAL_BUF_ICTRL : 3; -+ unsigned int RG_WF2G_RX_LNA_CAL_ATT : 3; -+ unsigned int RG_WF_RX_GM_VCMSEL : 3; -+ unsigned int rsvd_0 : 16; -+ } b; -+} RG_RX_A65_FIELD_T; -+ -+#define RG_RX_A66 (RF_D_RX_REG_BASE + 0x108) -+// Bit 1 :0 rg_wf5g_rx_dpd_att_ctrl U RW default = 'h1 -+// Bit 4 :2 rg_wf5g_rx_dpd_gm_gain U RW default = 'h7 -+// Bit 7 :5 rg_wf5g_rx_dpd_gm_ictrl U RW default = 'h3 -+// Bit 11 :8 rg_wf5g_rx_dpd_mxr_lodrv_ictrl U RW default = 'h3 -+// Bit 14 :12 rg_wf5g_rx_gm_ictrl U RW default = 'h3 -+// Bit 18 :15 rg_wf5g_rx_mxr_lodrv_ictrl U RW default = 'h3 -+// Bit 22 :19 rg_wf5g_rx_mxr_vbsel U RW default = 'h2 -+// Bit 25 :23 rg_wf5g_rx_mxr_vcmsel U RW default = 'h3 -+typedef union RG_RX_A66_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_RX_DPD_ATT_CTRL : 2; -+ unsigned int RG_WF5G_RX_DPD_GM_GAIN : 3; -+ unsigned int RG_WF5G_RX_DPD_GM_ICTRL : 3; -+ unsigned int RG_WF5G_RX_DPD_MXR_LODRV_ICTRL : 4; -+ unsigned int RG_WF5G_RX_GM_ICTRL : 3; -+ unsigned int RG_WF5G_RX_MXR_LODRV_ICTRL : 4; -+ unsigned int RG_WF5G_RX_MXR_VBSEL : 4; -+ unsigned int RG_WF5G_RX_MXR_VCMSEL : 3; -+ unsigned int rsvd_0 : 6; -+ } b; -+} RG_RX_A66_FIELD_T; -+ -+#define RG_RX_A67 (RF_D_RX_REG_BASE + 0x10c) -+// Bit 1 rg_wf_rx_tia_sca_en U RW default = 'h1 -+// Bit 16 :14 rg_wf_rx_tia_ictrl U RW default = 'h3 -+// Bit 19 :17 rg_wf_rx_tia_drvctrl U RW default = 'h3 -+typedef union RG_RX_A67_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF_RX_TIA_SCA_EN : 1; -+ unsigned int rsvd_1 : 12; -+ unsigned int RG_WF_RX_TIA_ICTRL : 3; -+ unsigned int RG_WF_RX_TIA_DRVCTRL : 3; -+ unsigned int rsvd_2 : 12; -+ } b; -+} RG_RX_A67_FIELD_T; -+ -+#define RG_RX_A68 (RF_D_RX_REG_BASE + 0x110) -+// Bit 0 rg_wf_rx_lpf_sra1_en U RW default = 'h1 -+// Bit 1 rg_wf_rx_lpf_sra2_en U RW default = 'h1 -+// Bit 2 rg_wf_rx_lpf_sra3_en U RW default = 'h1 -+// Bit 3 rg_wf_rx_lpf_sra4_en U RW default = 'h1 -+// Bit 4 rg_wf_rx_lpf_sca1_en U RW default = 'h1 -+// Bit 5 rg_wf_rx_lpf_sca2_en U RW default = 'h1 -+// Bit 6 rg_wf_rx_lpf_rn1_en U RW default = 'h1 -+// Bit 7 rg_wf_rx_lpf_notch_en U RW default = 'h1 -+// Bit 8 rg_wf_rx_lpf_op1_en U RW default = 'h1 -+// Bit 9 rg_wf_rx_lpf_op2_en U RW default = 'h1 -+// Bit 10 rg_wf5g_txlpbk2tia_en U RW default = 'h0 -+// Bit 11 rg_wf2g_txlpbk2tia_en U RW default = 'h0 -+// Bit 12 rg_wf_rx_adcbuf_en U RW default = 'h0 -+// Bit 16 :13 rg_wf_rx_adcbuf_sra_sel U RW default = 'h0 -+typedef union RG_RX_A68_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_LPF_SRA1_EN : 1; -+ unsigned int RG_WF_RX_LPF_SRA2_EN : 1; -+ unsigned int RG_WF_RX_LPF_SRA3_EN : 1; -+ unsigned int RG_WF_RX_LPF_SRA4_EN : 1; -+ unsigned int RG_WF_RX_LPF_SCA1_EN : 1; -+ unsigned int RG_WF_RX_LPF_SCA2_EN : 1; -+ unsigned int RG_WF_RX_LPF_RN1_EN : 1; -+ unsigned int RG_WF_RX_LPF_NOTCH_EN : 1; -+ unsigned int RG_WF_RX_LPF_OP1_EN : 1; -+ unsigned int RG_WF_RX_LPF_OP2_EN : 1; -+ unsigned int RG_WF5G_TXLPBK2TIA_EN : 1; -+ unsigned int RG_WF2G_TXLPBK2TIA_EN : 1; -+ unsigned int RG_WF_RX_ADCBUF_EN : 1; -+ unsigned int RG_WF_RX_ADCBUF_SRA_SEL : 4; -+ unsigned int rsvd_0 : 15; -+ } b; -+} RG_RX_A68_FIELD_T; -+ -+#define RG_RX_A69 (RF_D_RX_REG_BASE + 0x114) -+// Bit 2 :0 rg_wf_rx_vcmsel U RW default = 'h4 -+// Bit 5 :3 rg_wf_rx_lpf_op1_drvctrl U RW default = 'h3 -+// Bit 9 :6 rg_wf_rx_lpf_op2_drvctrl U RW default = 'h3 -+typedef union RG_RX_A69_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_VCMSEL : 3; -+ unsigned int RG_WF_RX_LPF_OP1_DRVCTRL : 3; -+ unsigned int RG_WF_RX_LPF_OP2_DRVCTRL : 4; -+ unsigned int rsvd_0 : 22; -+ } b; -+} RG_RX_A69_FIELD_T; -+ -+#define RG_RX_A71 (RF_D_RX_REG_BASE + 0x11c) -+// Bit 0 rg_wf_rx_fe_tp_en U RW default = 'h0 -+// Bit 8 :1 rg_wf_rx_fe_tp_sel U RW default = 'h0 -+// Bit 9 rg_wf_rtx_abb_tp_en U RW default = 'h0 -+// Bit 17 :10 rg_wf_rtx_abb_tp_sel U RW default = 'h0 -+// Bit 31 :18 rg_wf_rx_reserved8 U RW default = 'h0 -+typedef union RG_RX_A71_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_FE_TP_EN : 1; -+ unsigned int RG_WF_RX_FE_TP_SEL : 8; -+ unsigned int RG_WF_RTX_ABB_TP_EN : 1; -+ unsigned int RG_WF_RTX_ABB_TP_SEL : 8; -+ unsigned int RG_WF_RX_RESERVED8 : 14; -+ } b; -+} RG_RX_A71_FIELD_T; -+ -+#define RG_RX_A72 (RF_D_RX_REG_BASE + 0x120) -+// Bit 31 :0 rg_wf_rx_rsv0 U RW default = 'h0 -+typedef union RG_RX_A72_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_RSV0 : 32; -+ } b; -+} RG_RX_A72_FIELD_T; -+ -+#define RG_RX_A73 (RF_D_RX_REG_BASE + 0x124) -+// Bit 31 :0 rg_wf_rx_rsv1 U RW default = 'h0 -+typedef union RG_RX_A73_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_RSV1 : 32; -+ } b; -+} RG_RX_A73_FIELD_T; -+ -+#define RG_RX_A74 (RF_D_RX_REG_BASE + 0x128) -+// Bit 2 :0 rg_wf_rx_lpf_dcoc_rsel_bw20m U RW default = 'h3 -+// Bit 5 :3 rg_wf_rx_lpf_dcoc_rsel_bw40m U RW default = 'h3 -+// Bit 8 :6 rg_wf_rx_lpf_dcoc_rsel_bw80m U RW default = 'h0 -+// Bit 11 :9 rg_wf_rx_lpf_dcoc_rsel_bw160m U RW default = 'h0 -+// Bit 14 :12 rg_wf_rx_lpf_dcoc_rgsel_bw20m U RW default = 'h3 -+// Bit 17 :15 rg_wf_rx_lpf_dcoc_rgsel_bw40m U RW default = 'h3 -+// Bit 20 :18 rg_wf_rx_lpf_dcoc_rgsel_bw80m U RW default = 'h0 -+// Bit 23 :21 rg_wf_rx_lpf_dcoc_rgsel_bw160m U RW default = 'h0 -+// Bit 26 :24 rg_wf_rx_lpf_dcoc_rsel_man U RW default = 'h0 -+// Bit 27 rg_wf_rx_lpf_dcoc_rsel_man_mode U RW default = 'h0 -+// Bit 30 :28 rg_wf_rx_lpf_dcoc_rgsel_man U RW default = 'h0 -+// Bit 31 rg_wf_rx_lpf_dcoc_rgsel_man_mode U RW default = 'h0 -+typedef union RG_RX_A74_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_LPF_DCOC_RSEL_BW20M : 3; -+ unsigned int RG_WF_RX_LPF_DCOC_RSEL_BW40M : 3; -+ unsigned int RG_WF_RX_LPF_DCOC_RSEL_BW80M : 3; -+ unsigned int RG_WF_RX_LPF_DCOC_RSEL_BW160M : 3; -+ unsigned int RG_WF_RX_LPF_DCOC_RGSEL_BW20M : 3; -+ unsigned int RG_WF_RX_LPF_DCOC_RGSEL_BW40M : 3; -+ unsigned int RG_WF_RX_LPF_DCOC_RGSEL_BW80M : 3; -+ unsigned int RG_WF_RX_LPF_DCOC_RGSEL_BW160M : 3; -+ unsigned int RG_WF_RX_LPF_DCOC_RSEL_MAN : 3; -+ unsigned int RG_WF_RX_LPF_DCOC_RSEL_MAN_MODE : 1; -+ unsigned int RG_WF_RX_LPF_DCOC_RGSEL_MAN : 3; -+ unsigned int RG_WF_RX_LPF_DCOC_RGSEL_MAN_MODE : 1; -+ } b; -+} RG_RX_A74_FIELD_T; -+ -+#define RG_RX_A75 (RF_D_RX_REG_BASE + 0x12c) -+// Bit 2 :0 rg_wf_rx_lpf_op1_ictrl_bw20m U RW default = 'h1 -+// Bit 5 :3 rg_wf_rx_lpf_op1_ictrl_bw40m U RW default = 'h2 -+// Bit 8 :6 rg_wf_rx_lpf_op1_ictrl_bw80m U RW default = 'h3 -+// Bit 11 :9 rg_wf_rx_lpf_op1_ictrl_bw160m U RW default = 'h4 -+// Bit 14 :12 rg_wf_rx_lpf_op1_ictrl_man U RW default = 'h0 -+// Bit 15 rg_wf_rx_lpf_op1_ictrl_man_mode U RW default = 'h0 -+// Bit 17 :16 rg_wf_rx_lpf_op1_drv_bw20m U RW default = 'h0 -+// Bit 19 :18 rg_wf_rx_lpf_op1_drv_bw40m U RW default = 'h1 -+// Bit 21 :20 rg_wf_rx_lpf_op1_drv_bw80m U RW default = 'h2 -+// Bit 23 :22 rg_wf_rx_lpf_op1_drv_bw160m U RW default = 'h3 -+// Bit 25 :24 rg_wf_rx_lpf_op1_drv_man U RW default = 'h0 -+// Bit 26 rg_wf_rx_lpf_op1_drv_man_mode U RW default = 'h0 -+typedef union RG_RX_A75_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_LPF_OP1_ICTRL_BW20M : 3; -+ unsigned int RG_WF_RX_LPF_OP1_ICTRL_BW40M : 3; -+ unsigned int RG_WF_RX_LPF_OP1_ICTRL_BW80M : 3; -+ unsigned int RG_WF_RX_LPF_OP1_ICTRL_BW160M : 3; -+ unsigned int RG_WF_RX_LPF_OP1_ICTRL_MAN : 3; -+ unsigned int RG_WF_RX_LPF_OP1_ICTRL_MAN_MODE : 1; -+ unsigned int RG_WF_RX_LPF_OP1_DRV_BW20M : 2; -+ unsigned int RG_WF_RX_LPF_OP1_DRV_BW40M : 2; -+ unsigned int RG_WF_RX_LPF_OP1_DRV_BW80M : 2; -+ unsigned int RG_WF_RX_LPF_OP1_DRV_BW160M : 2; -+ unsigned int RG_WF_RX_LPF_OP1_DRV_MAN : 2; -+ unsigned int RG_WF_RX_LPF_OP1_DRV_MAN_MODE : 1; -+ unsigned int rsvd_0 : 5; -+ } b; -+} RG_RX_A75_FIELD_T; -+ -+#define RG_RX_A76 (RF_D_RX_REG_BASE + 0x130) -+// Bit 2 :0 rg_wf_rx_lpf_op2_ictrl_bw20m U RW default = 'h1 -+// Bit 5 :3 rg_wf_rx_lpf_op2_ictrl_bw40m U RW default = 'h2 -+// Bit 8 :6 rg_wf_rx_lpf_op2_ictrl_bw80m U RW default = 'h3 -+// Bit 11 :9 rg_wf_rx_lpf_op2_ictrl_bw160m U RW default = 'h4 -+// Bit 14 :12 rg_wf_rx_lpf_op2_ictrl_man U RW default = 'h0 -+// Bit 15 rg_wf_rx_lpf_op2_ictrl_man_mode U RW default = 'h0 -+// Bit 17 :16 rg_wf_rx_lpf_op2_drv_bw20m U RW default = 'h1 -+// Bit 19 :18 rg_wf_rx_lpf_op2_drv_bw40m U RW default = 'h1 -+// Bit 21 :20 rg_wf_rx_lpf_op2_drv_bw80m U RW default = 'h1 -+// Bit 23 :22 rg_wf_rx_lpf_op2_drv_bw160m U RW default = 'h2 -+// Bit 25 :24 rg_wf_rx_lpf_op2_drv_man U RW default = 'h0 -+// Bit 26 rg_wf_rx_lpf_op2_drv_man_mode U RW default = 'h0 -+typedef union RG_RX_A76_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_LPF_OP2_ICTRL_BW20M : 3; -+ unsigned int RG_WF_RX_LPF_OP2_ICTRL_BW40M : 3; -+ unsigned int RG_WF_RX_LPF_OP2_ICTRL_BW80M : 3; -+ unsigned int RG_WF_RX_LPF_OP2_ICTRL_BW160M : 3; -+ unsigned int RG_WF_RX_LPF_OP2_ICTRL_MAN : 3; -+ unsigned int RG_WF_RX_LPF_OP2_ICTRL_MAN_MODE : 1; -+ unsigned int RG_WF_RX_LPF_OP2_DRV_BW20M : 2; -+ unsigned int RG_WF_RX_LPF_OP2_DRV_BW40M : 2; -+ unsigned int RG_WF_RX_LPF_OP2_DRV_BW80M : 2; -+ unsigned int RG_WF_RX_LPF_OP2_DRV_BW160M : 2; -+ unsigned int RG_WF_RX_LPF_OP2_DRV_MAN : 2; -+ unsigned int RG_WF_RX_LPF_OP2_DRV_MAN_MODE : 1; -+ unsigned int rsvd_0 : 5; -+ } b; -+} RG_RX_A76_FIELD_T; -+ -+#define RG_RX_A77 (RF_D_RX_REG_BASE + 0x134) -+// Bit 1 :0 rg_wf_rx_lpf_op1_rcc_lg U RW default = 'h3 -+// Bit 3 :2 rg_wf_rx_lpf_op1_rcc_mg U RW default = 'h2 -+// Bit 5 :4 rg_wf_rx_lpf_op1_rcc_hg U RW default = 'h1 -+// Bit 7 :6 rg_wf_rx_lpf_op1_rcc_man U RW default = 'h0 -+// Bit 8 rg_wf_rx_lpf_op1_rcc_man_mode U RW default = 'h0 -+// Bit 10 :9 rg_wf_rx_lpf_op1_rcm_lg U RW default = 'h1 -+// Bit 12 :11 rg_wf_rx_lpf_op1_rcm_mg U RW default = 'h2 -+// Bit 14 :13 rg_wf_rx_lpf_op1_rcm_hg U RW default = 'h3 -+// Bit 16 :15 rg_wf_rx_lpf_op1_rcm_man U RW default = 'h0 -+// Bit 17 rg_wf_rx_lpf_op1_rcm_man_mode U RW default = 'h0 -+// Bit 19 :18 rg_wf_rx_lpf_op2_rcc_bw20m U RW default = 'h3 -+// Bit 21 :20 rg_wf_rx_lpf_op2_rcc_bw40m U RW default = 'h2 -+// Bit 23 :22 rg_wf_rx_lpf_op2_rcc_bw80m U RW default = 'h1 -+// Bit 25 :24 rg_wf_rx_lpf_op2_rcc_bw160m U RW default = 'h1 -+// Bit 27 :26 rg_wf_rx_lpf_op2_rcc_man U RW default = 'h0 -+// Bit 28 rg_wf_rx_lpf_op2_rcc_man_mode U RW default = 'h0 -+typedef union RG_RX_A77_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_LPF_OP1_RCC_LG : 2; -+ unsigned int RG_WF_RX_LPF_OP1_RCC_MG : 2; -+ unsigned int RG_WF_RX_LPF_OP1_RCC_HG : 2; -+ unsigned int RG_WF_RX_LPF_OP1_RCC_MAN : 2; -+ unsigned int RG_WF_RX_LPF_OP1_RCC_MAN_MODE : 1; -+ unsigned int RG_WF_RX_LPF_OP1_RCM_LG : 2; -+ unsigned int RG_WF_RX_LPF_OP1_RCM_MG : 2; -+ unsigned int RG_WF_RX_LPF_OP1_RCM_HG : 2; -+ unsigned int RG_WF_RX_LPF_OP1_RCM_MAN : 2; -+ unsigned int RG_WF_RX_LPF_OP1_RCM_MAN_MODE : 1; -+ unsigned int RG_WF_RX_LPF_OP2_RCC_BW20M : 2; -+ unsigned int RG_WF_RX_LPF_OP2_RCC_BW40M : 2; -+ unsigned int RG_WF_RX_LPF_OP2_RCC_BW80M : 2; -+ unsigned int RG_WF_RX_LPF_OP2_RCC_BW160M : 2; -+ unsigned int RG_WF_RX_LPF_OP2_RCC_MAN : 2; -+ unsigned int RG_WF_RX_LPF_OP2_RCC_MAN_MODE : 1; -+ unsigned int rsvd_0 : 3; -+ } b; -+} RG_RX_A77_FIELD_T; -+ -+#define RG_RX_A78 (RF_D_RX_REG_BASE + 0x138) -+// Bit 10 :9 rg_wf_rx_lpf_op2_rcm_bw20m U RW default = 'h3 -+// Bit 12 :11 rg_wf_rx_lpf_op2_rcm_bw40m U RW default = 'h3 -+// Bit 14 :13 rg_wf_rx_lpf_op2_rcm_bw80m U RW default = 'h3 -+// Bit 16 :15 rg_wf_rx_lpf_op2_rcm_bw160m U RW default = 'h3 -+// Bit 18 :17 rg_wf_rx_lpf_op2_rcm_man U RW default = 'h0 -+// Bit 19 rg_wf_rx_lpf_op2_rcm_man_mode U RW default = 'h0 -+// Bit 31 rg_wf2g_rx_lna_slice_man_mode U RW default = 'h0 -+typedef union RG_RX_A78_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rsvd_0 : 9; -+ unsigned int RG_WF_RX_LPF_OP2_RCM_BW20M : 2; -+ unsigned int RG_WF_RX_LPF_OP2_RCM_BW40M : 2; -+ unsigned int RG_WF_RX_LPF_OP2_RCM_BW80M : 2; -+ unsigned int RG_WF_RX_LPF_OP2_RCM_BW160M : 2; -+ unsigned int RG_WF_RX_LPF_OP2_RCM_MAN : 2; -+ unsigned int RG_WF_RX_LPF_OP2_RCM_MAN_MODE : 1; -+ unsigned int rsvd_1 : 11; -+ unsigned int RG_WF2G_RX_LNA_SLICE_MAN_MODE : 1; -+ } b; -+} RG_RX_A78_FIELD_T; -+ -+#define RG_RX_A79 (RF_D_RX_REG_BASE + 0x13c) -+// Bit 2 :0 rg_wf2g_rx_lna_ictrl_g1 U RW default = 'h3 -+// Bit 6 :4 rg_wf2g_rx_lna_ictrl_g2 U RW default = 'h4 -+// Bit 10 :8 rg_wf2g_rx_lna_ictrl_g3 U RW default = 'h4 -+// Bit 14 :12 rg_wf2g_rx_lna_ictrl_g4 U RW default = 'h4 -+// Bit 18 :16 rg_wf2g_rx_lna_ictrl_g5 U RW default = 'h2 -+// Bit 22 :20 rg_wf2g_rx_lna_ictrl_g6 U RW default = 'h2 -+// Bit 26 :24 rg_wf2g_rx_lna_ictrl_g7 U RW default = 'h3 -+// Bit 30 :28 rg_wf2g_rx_lna_ictrl_man U RW default = 'h0 -+// Bit 31 rg_wf2g_rx_lna_ictrl_man_mode U RW default = 'h0 -+typedef union RG_RX_A79_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LNA_ICTRL_G1 : 3; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF2G_RX_LNA_ICTRL_G2 : 3; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF2G_RX_LNA_ICTRL_G3 : 3; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF2G_RX_LNA_ICTRL_G4 : 3; -+ unsigned int rsvd_3 : 1; -+ unsigned int RG_WF2G_RX_LNA_ICTRL_G5 : 3; -+ unsigned int rsvd_4 : 1; -+ unsigned int RG_WF2G_RX_LNA_ICTRL_G6 : 3; -+ unsigned int rsvd_5 : 1; -+ unsigned int RG_WF2G_RX_LNA_ICTRL_G7 : 3; -+ unsigned int rsvd_6 : 1; -+ unsigned int RG_WF2G_RX_LNA_ICTRL_MAN : 3; -+ unsigned int RG_WF2G_RX_LNA_ICTRL_MAN_MODE : 1; -+ } b; -+} RG_RX_A79_FIELD_T; -+ -+#define RG_RX_A80 (RF_D_RX_REG_BASE + 0x140) -+// Bit 7 :0 rg_wf2g_rx_lna_slice_g1 U RW default = 'h49 -+// Bit 15 :8 rg_wf2g_rx_lna_slice_g2 U RW default = 'h92 -+// Bit 23 :16 rg_wf2g_rx_lna_slice_g3 U RW default = 'h93 -+// Bit 31 :24 rg_wf2g_rx_lna_slice_g4 U RW default = 'ha -+typedef union RG_RX_A80_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LNA_SLICE_G1 : 8; -+ unsigned int RG_WF2G_RX_LNA_SLICE_G2 : 8; -+ unsigned int RG_WF2G_RX_LNA_SLICE_G3 : 8; -+ unsigned int RG_WF2G_RX_LNA_SLICE_G4 : 8; -+ } b; -+} RG_RX_A80_FIELD_T; -+ -+#define RG_RX_A81 (RF_D_RX_REG_BASE + 0x144) -+// Bit 7 :0 rg_wf2g_rx_lna_slice_g5 U RW default = 'h1a -+// Bit 15 :8 rg_wf2g_rx_lna_slice_g6 U RW default = 'h7b -+// Bit 23 :16 rg_wf2g_rx_lna_slice_g7 U RW default = 'hfa -+// Bit 31 :24 rg_wf2g_rx_lna_slice_man U RW default = 'h0 -+typedef union RG_RX_A81_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LNA_SLICE_G5 : 8; -+ unsigned int RG_WF2G_RX_LNA_SLICE_G6 : 8; -+ unsigned int RG_WF2G_RX_LNA_SLICE_G7 : 8; -+ unsigned int RG_WF2G_RX_LNA_SLICE_MAN : 8; -+ } b; -+} RG_RX_A81_FIELD_T; -+ -+#define RG_RX_A82 (RF_D_RX_REG_BASE + 0x148) -+// Bit 4 :0 rg_wf2g_rx_lna_rfb_g1 U RW default = 'h0 -+// Bit 9 :5 rg_wf2g_rx_lna_rfb_g2 U RW default = 'h0 -+// Bit 14 :10 rg_wf2g_rx_lna_rfb_g3 U RW default = 'h0 -+// Bit 19 :15 rg_wf2g_rx_lna_rfb_g4 U RW default = 'h2 -+// Bit 24 :20 rg_wf2g_rx_lna_rfb_g5 U RW default = 'h4 -+// Bit 29 :25 rg_wf2g_rx_lna_rfb_g6 U RW default = 'h8 -+typedef union RG_RX_A82_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LNA_RFB_G1 : 5; -+ unsigned int RG_WF2G_RX_LNA_RFB_G2 : 5; -+ unsigned int RG_WF2G_RX_LNA_RFB_G3 : 5; -+ unsigned int RG_WF2G_RX_LNA_RFB_G4 : 5; -+ unsigned int RG_WF2G_RX_LNA_RFB_G5 : 5; -+ unsigned int RG_WF2G_RX_LNA_RFB_G6 : 5; -+ unsigned int rsvd_0 : 2; -+ } b; -+} RG_RX_A82_FIELD_T; -+ -+#define RG_RX_A83 (RF_D_RX_REG_BASE + 0x14c) -+// Bit 4 :0 rg_wf2g_rx_lna_rfb_g7 U RW default = 'h0 -+// Bit 9 :5 rg_wf2g_rx_lna_rfb_man U RW default = 'h0 -+// Bit 10 rg_wf2g_rx_lna_rfb_man_mode U RW default = 'h0 -+typedef union RG_RX_A83_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LNA_RFB_G7 : 5; -+ unsigned int RG_WF2G_RX_LNA_RFB_MAN : 5; -+ unsigned int RG_WF2G_RX_LNA_RFB_MAN_MODE : 1; -+ unsigned int rsvd_0 : 21; -+ } b; -+} RG_RX_A83_FIELD_T; -+ -+#define RG_RX_A84 (RF_D_RX_REG_BASE + 0x150) -+// Bit 2 :0 rg_wf2g_rx_lna_rt_g1 U RW default = 'h5 -+// Bit 5 :3 rg_wf2g_rx_lna_rt_g2 U RW default = 'h5 -+// Bit 8 :6 rg_wf2g_rx_lna_rt_g3 U RW default = 'h5 -+// Bit 11 :9 rg_wf2g_rx_lna_rt_g4 U RW default = 'h5 -+// Bit 14 :12 rg_wf2g_rx_lna_rt_g5 U RW default = 'h5 -+// Bit 17 :15 rg_wf2g_rx_lna_rt_g6 U RW default = 'h0 -+// Bit 26 :24 rg_wf2g_rx_lna_rt_man U RW default = 'h0 -+// Bit 31 rg_wf2g_rx_lna_rt_man_mode U RW default = 'h0 -+typedef union RG_RX_A84_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LNA_RT_G1 : 3; -+ unsigned int RG_WF2G_RX_LNA_RT_G2 : 3; -+ unsigned int RG_WF2G_RX_LNA_RT_G3 : 3; -+ unsigned int RG_WF2G_RX_LNA_RT_G4 : 3; -+ unsigned int RG_WF2G_RX_LNA_RT_G5 : 3; -+ unsigned int RG_WF2G_RX_LNA_RT_G6 : 3; -+ unsigned int rsvd_0 : 6; -+ unsigned int RG_WF2G_RX_LNA_RT_MAN : 3; -+ unsigned int rsvd_1 : 4; -+ unsigned int RG_WF2G_RX_LNA_RT_MAN_MODE : 1; -+ } b; -+} RG_RX_A84_FIELD_T; -+ -+#define RG_RX_A85 (RF_D_RX_REG_BASE + 0x154) -+// Bit 2 :0 rg_wf2g_rx_lna_att_g1 U RW default = 'h0 -+// Bit 5 :3 rg_wf2g_rx_lna_att_g2 U RW default = 'h2 -+// Bit 8 :6 rg_wf2g_rx_lna_att_g3 U RW default = 'h3 -+// Bit 11 :9 rg_wf2g_rx_lna_att_man U RW default = 'h0 -+// Bit 12 rg_wf2g_rx_lna_att_man_mode U RW default = 'h0 -+typedef union RG_RX_A85_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LNA_ATT_G1 : 3; -+ unsigned int RG_WF2G_RX_LNA_ATT_G2 : 3; -+ unsigned int RG_WF2G_RX_LNA_ATT_G3 : 3; -+ unsigned int RG_WF2G_RX_LNA_ATT_MAN : 3; -+ unsigned int RG_WF2G_RX_LNA_ATT_MAN_MODE : 1; -+ unsigned int rsvd_0 : 19; -+ } b; -+} RG_RX_A85_FIELD_T; -+ -+#define RG_RX_A86 (RF_D_RX_REG_BASE + 0x158) -+// Bit 1 :0 rg_wf2g_rx_dpd_att_ctrl U RW default = 'h1 -+// Bit 4 :2 rg_wf2g_rx_dpd_gm_gain U RW default = 'h7 -+// Bit 7 :5 rg_wf2g_rx_dpd_gm_ictrl U RW default = 'h3 -+// Bit 11 :8 rg_wf2g_rx_dpd_mxr_lodrv_ictrl U RW default = 'h3 -+// Bit 14 :12 rg_wf2g_rx_gm_ictrl U RW default = 'h3 -+// Bit 18 :15 rg_wf2g_rx_mxr_lodrv_ictrl U RW default = 'h3 -+// Bit 22 :19 rg_wf2g_rx_mxr_vbsel U RW default = 'h2 -+// Bit 25 :23 rg_wf2g_rx_mxr_vcmsel U RW default = 'h3 -+typedef union RG_RX_A86_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_DPD_ATT_CTRL : 2; -+ unsigned int RG_WF2G_RX_DPD_GM_GAIN : 3; -+ unsigned int RG_WF2G_RX_DPD_GM_ICTRL : 3; -+ unsigned int RG_WF2G_RX_DPD_MXR_LODRV_ICTRL : 4; -+ unsigned int RG_WF2G_RX_GM_ICTRL : 3; -+ unsigned int RG_WF2G_RX_MXR_LODRV_ICTRL : 4; -+ unsigned int RG_WF2G_RX_MXR_VBSEL : 4; -+ unsigned int RG_WF2G_RX_MXR_VCMSEL : 3; -+ unsigned int rsvd_0 : 6; -+ } b; -+} RG_RX_A86_FIELD_T; -+ -+#define RG_RX_A87 (RF_D_RX_REG_BASE + 0x15c) -+// Bit 7 :0 rg_wf2g_rx_lna_priority U RW default = 'hdb -+typedef union RG_RX_A87_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LNA_PRIORITY : 8; -+ unsigned int rsvd_0 : 24; -+ } b; -+} RG_RX_A87_FIELD_T; -+ -+#define RG_RX_A88 (RF_D_RX_REG_BASE + 0x160) -+// Bit 0 rg_m4_wf_rx_fe_topbias_en U RW default = 'h1 -+// Bit 1 rg_m4_wf_rx_lna_bias_en U RW default = 'h1 -+// Bit 2 rg_m4_wf_rx_gm_bias_en U RW default = 'h1 -+// Bit 3 rg_m4_wf_rx_mxr_bias_en U RW default = 'h1 -+// Bit 4 rg_m4_wf5g_rx_lna_trsw_en U RW default = 'h1 -+// Bit 5 rg_m4_wf5g_rx_lna_en U RW default = 'h0 -+// Bit 6 rg_m4_wf5g_rx_gm_en U RW default = 'h0 -+// Bit 7 rg_m4_wf5g_rx_mxr_en U RW default = 'h0 -+// Bit 8 rg_m4_wf5g_rx_dpd_en U RW default = 'h1 -+// Bit 9 rg_m4_wf5g_rx_irrcal_en U RW default = 'h0 -+// Bit 10 rg_m4_wf2g_rx_lna_trsw_en U RW default = 'h0 -+// Bit 11 rg_m4_wf2g_rx_lna_en U RW default = 'h0 -+// Bit 12 rg_m4_wf2g_rx_gm_en U RW default = 'h0 -+// Bit 13 rg_m4_wf2g_rx_mxr_en U RW default = 'h0 -+// Bit 14 rg_m4_wf2g_rx_irrcal_en U RW default = 'h0 -+// Bit 15 rg_m4_wf2g_rx_dpd_en U RW default = 'h0 -+// Bit 17 rg_m4_wf_rtx_abb_topbias_en U RW default = 'h1 -+// Bit 18 rg_m4_wf_rtx_abb_rx_en U RW default = 'h1 -+// Bit 22 rg_m4_wf_rx_tia_bias_en U RW default = 'h1 -+// Bit 23 rg_m4_wf_rx_rssipga_bias_en U RW default = 'h1 -+// Bit 24 rg_m4_wf_rx_lpf_bias_en U RW default = 'h1 -+// Bit 25 rg_m4_wf_rx_tia_en U RW default = 'h1 -+// Bit 26 rg_m4_wf_rx_rssipga_en U RW default = 'h1 -+// Bit 27 rg_m4_wf_rx_lpf_en U RW default = 'h1 -+// Bit 28 rg_m4_wf_rx_lpf_i_dcoc_en U RW default = 'h1 -+// Bit 29 rg_m4_wf_rx_lpf_q_dcoc_en U RW default = 'h1 -+typedef union RG_RX_A88_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M4_WF_RX_FE_TOPBIAS_EN : 1; -+ unsigned int RG_M4_WF_RX_LNA_BIAS_EN : 1; -+ unsigned int RG_M4_WF_RX_GM_BIAS_EN : 1; -+ unsigned int RG_M4_WF_RX_MXR_BIAS_EN : 1; -+ unsigned int RG_M4_WF5G_RX_LNA_TRSW_EN : 1; -+ unsigned int RG_M4_WF5G_RX_LNA_EN : 1; -+ unsigned int RG_M4_WF5G_RX_GM_EN : 1; -+ unsigned int RG_M4_WF5G_RX_MXR_EN : 1; -+ unsigned int RG_M4_WF5G_RX_DPD_EN : 1; -+ unsigned int RG_M4_WF5G_RX_IRRCAL_EN : 1; -+ unsigned int RG_M4_WF2G_RX_LNA_TRSW_EN : 1; -+ unsigned int RG_M4_WF2G_RX_LNA_EN : 1; -+ unsigned int RG_M4_WF2G_RX_GM_EN : 1; -+ unsigned int RG_M4_WF2G_RX_MXR_EN : 1; -+ unsigned int RG_M4_WF2G_RX_IRRCAL_EN : 1; -+ unsigned int RG_M4_WF2G_RX_DPD_EN : 1; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_M4_WF_RTX_ABB_TOPBIAS_EN : 1; -+ unsigned int RG_M4_WF_RTX_ABB_RX_EN : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int RG_M4_WF_RX_TIA_BIAS_EN : 1; -+ unsigned int RG_M4_WF_RX_RSSIPGA_BIAS_EN : 1; -+ unsigned int RG_M4_WF_RX_LPF_BIAS_EN : 1; -+ unsigned int RG_M4_WF_RX_TIA_EN : 1; -+ unsigned int RG_M4_WF_RX_RSSIPGA_EN : 1; -+ unsigned int RG_M4_WF_RX_LPF_EN : 1; -+ unsigned int RG_M4_WF_RX_LPF_I_DCOC_EN : 1; -+ unsigned int RG_M4_WF_RX_LPF_Q_DCOC_EN : 1; -+ unsigned int rsvd_2 : 2; -+ } b; -+} RG_RX_A88_FIELD_T; -+ -+#define RG_RX_A89 (RF_D_RX_REG_BASE + 0x164) -+// Bit 0 rg_m5_wf_rx_fe_topbias_en U RW default = 'h0 -+// Bit 1 rg_m5_wf_rx_lna_bias_en U RW default = 'h0 -+// Bit 2 rg_m5_wf_rx_gm_bias_en U RW default = 'h0 -+// Bit 3 rg_m5_wf_rx_mxr_bias_en U RW default = 'h0 -+// Bit 4 rg_m5_wf5g_rx_lna_trsw_en U RW default = 'h0 -+// Bit 5 rg_m5_wf5g_rx_lna_en U RW default = 'h0 -+// Bit 6 rg_m5_wf5g_rx_gm_en U RW default = 'h0 -+// Bit 7 rg_m5_wf5g_rx_mxr_en U RW default = 'h0 -+// Bit 8 rg_m5_wf5g_rx_dpd_en U RW default = 'h0 -+// Bit 9 rg_m5_wf5g_rx_irrcal_en U RW default = 'h0 -+// Bit 10 rg_m5_wf2g_rx_lna_trsw_en U RW default = 'h0 -+// Bit 11 rg_m5_wf2g_rx_lna_en U RW default = 'h0 -+// Bit 12 rg_m5_wf2g_rx_gm_en U RW default = 'h0 -+// Bit 13 rg_m5_wf2g_rx_mxr_en U RW default = 'h0 -+// Bit 14 rg_m5_wf2g_rx_irrcal_en U RW default = 'h0 -+// Bit 15 rg_m5_wf2g_rx_dpd_en U RW default = 'h0 -+// Bit 17 rg_m5_wf_rtx_abb_topbias_en U RW default = 'h0 -+// Bit 18 rg_m5_wf_rtx_abb_rx_en U RW default = 'h0 -+// Bit 22 rg_m5_wf_rx_tia_bias_en U RW default = 'h0 -+// Bit 23 rg_m5_wf_rx_rssipga_bias_en U RW default = 'h0 -+// Bit 24 rg_m5_wf_rx_lpf_bias_en U RW default = 'h0 -+// Bit 25 rg_m5_wf_rx_tia_en U RW default = 'h0 -+// Bit 26 rg_m5_wf_rx_rssipga_en U RW default = 'h0 -+// Bit 27 rg_m5_wf_rx_lpf_en U RW default = 'h0 -+// Bit 28 rg_m5_wf_rx_lpf_i_dcoc_en U RW default = 'h0 -+// Bit 29 rg_m5_wf_rx_lpf_q_dcoc_en U RW default = 'h0 -+typedef union RG_RX_A89_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M5_WF_RX_FE_TOPBIAS_EN : 1; -+ unsigned int RG_M5_WF_RX_LNA_BIAS_EN : 1; -+ unsigned int RG_M5_WF_RX_GM_BIAS_EN : 1; -+ unsigned int RG_M5_WF_RX_MXR_BIAS_EN : 1; -+ unsigned int RG_M5_WF5G_RX_LNA_TRSW_EN : 1; -+ unsigned int RG_M5_WF5G_RX_LNA_EN : 1; -+ unsigned int RG_M5_WF5G_RX_GM_EN : 1; -+ unsigned int RG_M5_WF5G_RX_MXR_EN : 1; -+ unsigned int RG_M5_WF5G_RX_DPD_EN : 1; -+ unsigned int RG_M5_WF5G_RX_IRRCAL_EN : 1; -+ unsigned int RG_M5_WF2G_RX_LNA_TRSW_EN : 1; -+ unsigned int RG_M5_WF2G_RX_LNA_EN : 1; -+ unsigned int RG_M5_WF2G_RX_GM_EN : 1; -+ unsigned int RG_M5_WF2G_RX_MXR_EN : 1; -+ unsigned int RG_M5_WF2G_RX_IRRCAL_EN : 1; -+ unsigned int RG_M5_WF2G_RX_DPD_EN : 1; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_M5_WF_RTX_ABB_TOPBIAS_EN : 1; -+ unsigned int RG_M5_WF_RTX_ABB_RX_EN : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int RG_M5_WF_RX_TIA_BIAS_EN : 1; -+ unsigned int RG_M5_WF_RX_RSSIPGA_BIAS_EN : 1; -+ unsigned int RG_M5_WF_RX_LPF_BIAS_EN : 1; -+ unsigned int RG_M5_WF_RX_TIA_EN : 1; -+ unsigned int RG_M5_WF_RX_RSSIPGA_EN : 1; -+ unsigned int RG_M5_WF_RX_LPF_EN : 1; -+ unsigned int RG_M5_WF_RX_LPF_I_DCOC_EN : 1; -+ unsigned int RG_M5_WF_RX_LPF_Q_DCOC_EN : 1; -+ unsigned int rsvd_2 : 2; -+ } b; -+} RG_RX_A89_FIELD_T; -+ -+#define RG_RX_A90 (RF_D_RX_REG_BASE + 0x168) -+// Bit 0 rg_m6_wf_rx_fe_topbias_en U RW default = 'h1 -+// Bit 1 rg_m6_wf_rx_lna_bias_en U RW default = 'h0 -+// Bit 2 rg_m6_wf_rx_gm_bias_en U RW default = 'h0 -+// Bit 3 rg_m6_wf_rx_mxr_bias_en U RW default = 'h0 -+// Bit 4 rg_m6_wf5g_rx_lna_trsw_en U RW default = 'h0 -+// Bit 5 rg_m6_wf5g_rx_lna_en U RW default = 'h0 -+// Bit 6 rg_m6_wf5g_rx_gm_en U RW default = 'h0 -+// Bit 7 rg_m6_wf5g_rx_mxr_en U RW default = 'h0 -+// Bit 8 rg_m6_wf5g_rx_dpd_en U RW default = 'h0 -+// Bit 9 rg_m6_wf5g_rx_irrcal_en U RW default = 'h0 -+// Bit 10 rg_m6_wf2g_rx_lna_trsw_en U RW default = 'h1 -+// Bit 11 rg_m6_wf2g_rx_lna_en U RW default = 'h0 -+// Bit 12 rg_m6_wf2g_rx_gm_en U RW default = 'h0 -+// Bit 13 rg_m6_wf2g_rx_mxr_en U RW default = 'h0 -+// Bit 14 rg_m6_wf2g_rx_irrcal_en U RW default = 'h0 -+// Bit 15 rg_m6_wf2g_rx_dpd_en U RW default = 'h0 -+// Bit 17 rg_m6_wf_rtx_abb_topbias_en U RW default = 'h1 -+// Bit 18 rg_m6_wf_rtx_abb_rx_en U RW default = 'h0 -+// Bit 22 rg_m6_wf_rx_tia_bias_en U RW default = 'h0 -+// Bit 23 rg_m6_wf_rx_rssipga_bias_en U RW default = 'h0 -+// Bit 24 rg_m6_wf_rx_lpf_bias_en U RW default = 'h0 -+// Bit 25 rg_m6_wf_rx_tia_en U RW default = 'h0 -+// Bit 26 rg_m6_wf_rx_rssipga_en U RW default = 'h0 -+// Bit 27 rg_m6_wf_rx_lpf_en U RW default = 'h0 -+// Bit 28 rg_m6_wf_rx_lpf_i_dcoc_en U RW default = 'h0 -+// Bit 29 rg_m6_wf_rx_lpf_q_dcoc_en U RW default = 'h0 -+typedef union RG_RX_A90_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M6_WF_RX_FE_TOPBIAS_EN : 1; -+ unsigned int RG_M6_WF_RX_LNA_BIAS_EN : 1; -+ unsigned int RG_M6_WF_RX_GM_BIAS_EN : 1; -+ unsigned int RG_M6_WF_RX_MXR_BIAS_EN : 1; -+ unsigned int RG_M6_WF5G_RX_LNA_TRSW_EN : 1; -+ unsigned int RG_M6_WF5G_RX_LNA_EN : 1; -+ unsigned int RG_M6_WF5G_RX_GM_EN : 1; -+ unsigned int RG_M6_WF5G_RX_MXR_EN : 1; -+ unsigned int RG_M6_WF5G_RX_DPD_EN : 1; -+ unsigned int RG_M6_WF5G_RX_IRRCAL_EN : 1; -+ unsigned int RG_M6_WF2G_RX_LNA_TRSW_EN : 1; -+ unsigned int RG_M6_WF2G_RX_LNA_EN : 1; -+ unsigned int RG_M6_WF2G_RX_GM_EN : 1; -+ unsigned int RG_M6_WF2G_RX_MXR_EN : 1; -+ unsigned int RG_M6_WF2G_RX_IRRCAL_EN : 1; -+ unsigned int RG_M6_WF2G_RX_DPD_EN : 1; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_M6_WF_RTX_ABB_TOPBIAS_EN : 1; -+ unsigned int RG_M6_WF_RTX_ABB_RX_EN : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int RG_M6_WF_RX_TIA_BIAS_EN : 1; -+ unsigned int RG_M6_WF_RX_RSSIPGA_BIAS_EN : 1; -+ unsigned int RG_M6_WF_RX_LPF_BIAS_EN : 1; -+ unsigned int RG_M6_WF_RX_TIA_EN : 1; -+ unsigned int RG_M6_WF_RX_RSSIPGA_EN : 1; -+ unsigned int RG_M6_WF_RX_LPF_EN : 1; -+ unsigned int RG_M6_WF_RX_LPF_I_DCOC_EN : 1; -+ unsigned int RG_M6_WF_RX_LPF_Q_DCOC_EN : 1; -+ unsigned int rsvd_2 : 2; -+ } b; -+} RG_RX_A90_FIELD_T; -+ -+#define RG_RX_A91 (RF_D_RX_REG_BASE + 0x16c) -+// Bit 0 rg_m7_wf_rx_fe_topbias_en U RW default = 'h1 -+// Bit 1 rg_m7_wf_rx_lna_bias_en U RW default = 'h1 -+// Bit 2 rg_m7_wf_rx_gm_bias_en U RW default = 'h1 -+// Bit 3 rg_m7_wf_rx_mxr_bias_en U RW default = 'h1 -+// Bit 4 rg_m7_wf5g_rx_lna_trsw_en U RW default = 'h0 -+// Bit 5 rg_m7_wf5g_rx_lna_en U RW default = 'h0 -+// Bit 6 rg_m7_wf5g_rx_gm_en U RW default = 'h0 -+// Bit 7 rg_m7_wf5g_rx_mxr_en U RW default = 'h0 -+// Bit 8 rg_m7_wf5g_rx_dpd_en U RW default = 'h0 -+// Bit 9 rg_m7_wf5g_rx_irrcal_en U RW default = 'h0 -+// Bit 10 rg_m7_wf2g_rx_lna_trsw_en U RW default = 'h0 -+// Bit 11 rg_m7_wf2g_rx_lna_en U RW default = 'h1 -+// Bit 12 rg_m7_wf2g_rx_gm_en U RW default = 'h1 -+// Bit 13 rg_m7_wf2g_rx_mxr_en U RW default = 'h1 -+// Bit 14 rg_m7_wf2g_rx_irrcal_en U RW default = 'h0 -+// Bit 15 rg_m7_wf2g_rx_dpd_en U RW default = 'h0 -+// Bit 17 rg_m7_wf_rtx_abb_topbias_en U RW default = 'h1 -+// Bit 18 rg_m7_wf_rtx_abb_rx_en U RW default = 'h1 -+// Bit 22 rg_m7_wf_rx_tia_bias_en U RW default = 'h1 -+// Bit 23 rg_m7_wf_rx_rssipga_bias_en U RW default = 'h1 -+// Bit 24 rg_m7_wf_rx_lpf_bias_en U RW default = 'h1 -+// Bit 25 rg_m7_wf_rx_tia_en U RW default = 'h1 -+// Bit 26 rg_m7_wf_rx_rssipga_en U RW default = 'h1 -+// Bit 27 rg_m7_wf_rx_lpf_en U RW default = 'h1 -+// Bit 28 rg_m7_wf_rx_lpf_i_dcoc_en U RW default = 'h1 -+// Bit 29 rg_m7_wf_rx_lpf_q_dcoc_en U RW default = 'h1 -+typedef union RG_RX_A91_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M7_WF_RX_FE_TOPBIAS_EN : 1; -+ unsigned int RG_M7_WF_RX_LNA_BIAS_EN : 1; -+ unsigned int RG_M7_WF_RX_GM_BIAS_EN : 1; -+ unsigned int RG_M7_WF_RX_MXR_BIAS_EN : 1; -+ unsigned int RG_M7_WF5G_RX_LNA_TRSW_EN : 1; -+ unsigned int RG_M7_WF5G_RX_LNA_EN : 1; -+ unsigned int RG_M7_WF5G_RX_GM_EN : 1; -+ unsigned int RG_M7_WF5G_RX_MXR_EN : 1; -+ unsigned int RG_M7_WF5G_RX_DPD_EN : 1; -+ unsigned int RG_M7_WF5G_RX_IRRCAL_EN : 1; -+ unsigned int RG_M7_WF2G_RX_LNA_TRSW_EN : 1; -+ unsigned int RG_M7_WF2G_RX_LNA_EN : 1; -+ unsigned int RG_M7_WF2G_RX_GM_EN : 1; -+ unsigned int RG_M7_WF2G_RX_MXR_EN : 1; -+ unsigned int RG_M7_WF2G_RX_IRRCAL_EN : 1; -+ unsigned int RG_M7_WF2G_RX_DPD_EN : 1; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_M7_WF_RTX_ABB_TOPBIAS_EN : 1; -+ unsigned int RG_M7_WF_RTX_ABB_RX_EN : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int RG_M7_WF_RX_TIA_BIAS_EN : 1; -+ unsigned int RG_M7_WF_RX_RSSIPGA_BIAS_EN : 1; -+ unsigned int RG_M7_WF_RX_LPF_BIAS_EN : 1; -+ unsigned int RG_M7_WF_RX_TIA_EN : 1; -+ unsigned int RG_M7_WF_RX_RSSIPGA_EN : 1; -+ unsigned int RG_M7_WF_RX_LPF_EN : 1; -+ unsigned int RG_M7_WF_RX_LPF_I_DCOC_EN : 1; -+ unsigned int RG_M7_WF_RX_LPF_Q_DCOC_EN : 1; -+ unsigned int rsvd_2 : 2; -+ } b; -+} RG_RX_A91_FIELD_T; -+ -+#define RG_RX_A92 (RF_D_RX_REG_BASE + 0x170) -+// Bit 2 :0 rg_wf2g_rx_lna_ictrl_g67 U RW default = 'h3 -+// Bit 5 :3 rg_wf2g_rx_lna_ictrl_g57 U RW default = 'h2 -+// Bit 8 :6 rg_wf2g_rx_lna_ictrl_g47 U RW default = 'h2 -+// Bit 11 :9 rg_wf2g_rx_lna_ictrl_g37 U RW default = 'h5 -+// Bit 14 :12 rg_wf2g_rx_lna_ictrl_g56 U RW default = 'h3 -+// Bit 17 :15 rg_wf2g_rx_lna_ictrl_g46 U RW default = 'h2 -+// Bit 20 :18 rg_wf2g_rx_lna_ictrl_g36 U RW default = 'h5 -+// Bit 23 :21 rg_wf2g_rx_lna_ictrl_g45 U RW default = 'h3 -+// Bit 26 :24 rg_wf2g_rx_lna_ictrl_g35 U RW default = 'h3 -+// Bit 29 :27 rg_wf2g_rx_lna_ictrl_g34 U RW default = 'h2 -+typedef union RG_RX_A92_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LNA_ICTRL_G67 : 3; -+ unsigned int RG_WF2G_RX_LNA_ICTRL_G57 : 3; -+ unsigned int RG_WF2G_RX_LNA_ICTRL_G47 : 3; -+ unsigned int RG_WF2G_RX_LNA_ICTRL_G37 : 3; -+ unsigned int RG_WF2G_RX_LNA_ICTRL_G56 : 3; -+ unsigned int RG_WF2G_RX_LNA_ICTRL_G46 : 3; -+ unsigned int RG_WF2G_RX_LNA_ICTRL_G36 : 3; -+ unsigned int RG_WF2G_RX_LNA_ICTRL_G45 : 3; -+ unsigned int RG_WF2G_RX_LNA_ICTRL_G35 : 3; -+ unsigned int RG_WF2G_RX_LNA_ICTRL_G34 : 3; -+ unsigned int rsvd_0 : 2; -+ } b; -+} RG_RX_A92_FIELD_T; -+ -+#define RG_RX_A93 (RF_D_RX_REG_BASE + 0x174) -+// Bit 4 :0 rg_wf2g_rx_lna_rfb_g77 U RW default = 'h0 -+// Bit 9 :5 rg_wf2g_btrx_lna_rfb_g77 U RW default = 'h0 -+// Bit 11 :10 rg_wf_agc_lock_option U RW default = 'h3 -+// Bit 23 :16 rg_wf_rx_lna_en_delay_bnd U RW default = 'h14 -+// Bit 24 rg_wf_rx_lna_en_delay_bypass U RW default = 'h0 -+typedef union RG_RX_A93_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_RX_LNA_RFB_G77 : 5; -+ unsigned int RG_WF2G_BTRX_LNA_RFB_G77 : 5; -+ unsigned int RG_WF_AGC_LOCK_OPTION : 2; -+ unsigned int rsvd_0 : 4; -+ unsigned int RG_WF_RX_LNA_EN_DELAY_BND : 8; -+ unsigned int RG_WF_RX_LNA_EN_DELAY_BYPASS : 1; -+ unsigned int rsvd_1 : 7; -+ } b; -+} RG_RX_A93_FIELD_T; -+ -+#define RG_RX_A94 (RF_D_RX_REG_BASE + 0x178) -+// Bit 12 rg_wf_daclpbk2adc_en U RW default = 'h0 -+// Bit 13 rg_wf_rx_lpf_testout_en U RW default = 'h0 -+// Bit 14 rg_wf_rx_rssipga_testout_en U RW default = 'h0 -+typedef union RG_RX_A94_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rsvd_0 : 12; -+ unsigned int RG_WF_DACLPBK2ADC_EN : 1; -+ unsigned int RG_WF_RX_LPF_TESTOUT_EN : 1; -+ unsigned int RG_WF_RX_RSSIPGA_TESTOUT_EN : 1; -+ unsigned int rsvd_1 : 17; -+ } b; -+} RG_RX_A94_FIELD_T; -+ -+#endif -+ -diff --git a/drivers/net/wireless/w1/common/rf_d_sx_reg.h b/drivers/net/wireless/w1/common/rf_d_sx_reg.h -new file mode 100644 -index 000000000000..ca37aae62396 ---- /dev/null -+++ b/drivers/net/wireless/w1/common/rf_d_sx_reg.h -@@ -0,0 +1,1093 @@ -+#ifdef RF_D_SX_REG -+#else -+#define RF_D_SX_REG -+ -+ -+#define RF_D_SX_REG_BASE (0x400) -+ -+#define RG_SX_A0 (RF_D_SX_REG_BASE + 0x0) -+// Bit 0 rg_wf_sx_fcal_en U RW default = 'h0 -+// Bit 2 rg_wf_sx_cali_start_man_mode U RW default = 'h1 -+// Bit 4 rg_wf_sx_sdm_frac_en U RW default = 'h1 -+// Bit 12 :8 rg_wf_sx_fcal_mode_sel U RW default = 'h1b -+// Bit 16 rg_wf_sx_rf_osc_double U RW default = 'h0 -+// Bit 20 rg_wf_sx_dig_osc_double U RW default = 'h0 -+// Bit 31 rg_wf_sx_soft_reset U RW default = 'h0 -+typedef union RG_SX_A0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_FCAL_EN : 1; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF_SX_CALI_START_MAN_MODE : 1; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF_SX_SDM_FRAC_EN : 1; -+ unsigned int rsvd_2 : 3; -+ unsigned int RG_WF_SX_FCAL_MODE_SEL : 5; -+ unsigned int rsvd_3 : 3; -+ unsigned int RG_WF_SX_RF_OSC_DOUBLE : 1; -+ unsigned int rsvd_4 : 3; -+ unsigned int RG_WF_SX_DIG_OSC_DOUBLE : 1; -+ unsigned int rsvd_5 : 10; -+ unsigned int RG_WF_SX_SOFT_RESET : 1; -+ } b; -+} RG_SX_A0_FIELD_T; -+ -+#define RG_SX_A1 (RF_D_SX_REG_BASE + 0x4) -+// Bit 0 rg_wf_sx_fcal_sel_p U RW default = 'h0 -+// Bit 10 :4 rg_wf_sx_vcoc_p U RW default = 'h40 -+// Bit 12 rg_wf_sx_fcal_sel_t U RW default = 'h0 -+// Bit 20 :16 rg_wf_sx_vcoc_t U RW default = 'h10 -+// Bit 24 rg_wf_sx_ldo_fc_man U RW default = 'h0 -+// Bit 28 rg_wf_sx_ldo_fc U RW default = 'h0 -+typedef union RG_SX_A1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_FCAL_SEL_P : 1; -+ unsigned int rsvd_0 : 3; -+ unsigned int RG_WF_SX_VCOC_P : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF_SX_FCAL_SEL_T : 1; -+ unsigned int rsvd_2 : 3; -+ unsigned int RG_WF_SX_VCOC_T : 5; -+ unsigned int rsvd_3 : 3; -+ unsigned int RG_WF_SX_LDO_FC_MAN : 1; -+ unsigned int rsvd_4 : 3; -+ unsigned int RG_WF_SX_LDO_FC : 1; -+ unsigned int rsvd_5 : 3; -+ } b; -+} RG_SX_A1_FIELD_T; -+ -+#define RG_SX_A2 (RF_D_SX_REG_BASE + 0x8) -+// Bit 6 :0 ro_da_wf_sx_vcoc_p U RO default = 'h0 -+// Bit 20 :16 ro_da_wf_sx_vcoc_t U RO default = 'h0 -+// Bit 24 ro_wf_sx_mxrtank_cali_ready U RO default = 'h0 -+// Bit 25 ro_wf_sx_chn_map_ready U RO default = 'h0 -+// Bit 26 ro_wf_sx_p_cali_ready U RO default = 'h0 -+// Bit 27 ro_wf_sx_a_cali_ready U RO default = 'h0 -+// Bit 28 ro_wf_sx_t_cali_ready U RO default = 'h0 -+// Bit 29 ro_ad_wf_sx_ready U RO default = 'h0 -+// Bit 31 ro_cali_end_flg U RO default = 'h0 -+typedef union RG_SX_A2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RO_DA_WF_SX_VCOC_P : 7; -+ unsigned int rsvd_0 : 9; -+ unsigned int RO_DA_WF_SX_VCOC_T : 5; -+ unsigned int rsvd_1 : 3; -+ unsigned int RO_WF_SX_MXRTANK_CALI_READY : 1; -+ unsigned int RO_WF_SX_CHN_MAP_READY : 1; -+ unsigned int RO_WF_SX_P_CALI_READY : 1; -+ unsigned int RO_WF_SX_A_CALI_READY : 1; -+ unsigned int RO_WF_SX_T_CALI_READY : 1; -+ unsigned int RO_AD_WF_SX_READY : 1; -+ unsigned int rsvd_2 : 1; -+ unsigned int RO_CALI_END_FLG : 1; -+ } b; -+} RG_SX_A2_FIELD_T; -+ -+#define RG_SX_A3 (RF_D_SX_REG_BASE + 0xc) -+// Bit 1 :0 rg_wf_sx_ldo_fc_waittime U RW default = 'h2 -+// Bit 5 :4 rg_wf_sx_set_code_waittime U RW default = 'h1 -+// Bit 9 :8 rg_wf_sx_fcal_cw_waittime U RW default = 'h1 -+// Bit 13 :12 rg_wf_sx_tr_wait_waittime U RW default = 'h1 -+// Bit 17 :16 rg_wf_sx_acal_vco_waittime U RW default = 'h1 -+// Bit 21 :20 rg_wf_sx_tr_switch_bnd U RW default = 'h0 -+typedef union RG_SX_A3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_LDO_FC_WAITTIME : 2; -+ unsigned int rsvd_0 : 2; -+ unsigned int RG_WF_SX_SET_CODE_WAITTIME : 2; -+ unsigned int rsvd_1 : 2; -+ unsigned int RG_WF_SX_FCAL_CW_WAITTIME : 2; -+ unsigned int rsvd_2 : 2; -+ unsigned int RG_WF_SX_TR_WAIT_WAITTIME : 2; -+ unsigned int rsvd_3 : 2; -+ unsigned int RG_WF_SX_ACAL_VCO_WAITTIME : 2; -+ unsigned int rsvd_4 : 2; -+ unsigned int RG_WF_SX_TR_SWITCH_BND : 2; -+ unsigned int rsvd_5 : 10; -+ } b; -+} RG_SX_A3_FIELD_T; -+ -+#define RG_SX_A4 (RF_D_SX_REG_BASE + 0x10) -+// Bit 0 rg_wf_sx_vco_i_man U RW default = 'h0 -+// Bit 7 :4 rg_wf_sx_vco_i U RW default = 'h8 -+// Bit 15 :8 rg_wf_sx_pd_vctrl_sel U RW default = 'h3 -+typedef union RG_SX_A4_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_VCO_I_MAN : 1; -+ unsigned int rsvd_0 : 3; -+ unsigned int RG_WF_SX_VCO_I : 4; -+ unsigned int RG_WF_SX_PD_VCTRL_SEL : 8; -+ unsigned int rsvd_1 : 16; -+ } b; -+} RG_SX_A4_FIELD_T; -+ -+#define RG_SX_A5 (RF_D_SX_REG_BASE + 0x14) -+// Bit 3 :0 ro_wf_sx_vco_i U RO default = 'h0 -+// Bit 4 ro_da_wf_sx_vco_acfinish U RO default = 'h0 -+// Bit 8 ro_ad_wf_sx_vco_alc_out U RO default = 'h0 -+// Bit 23 :16 ro_wf_sx_pt_fsm U RO default = 'h0 -+// Bit 30 :24 ro_wf_sx_top_fsm U RO default = 'h0 -+typedef union RG_SX_A5_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RO_WF_SX_VCO_I : 4; -+ unsigned int RO_DA_WF_SX_VCO_ACFINISH : 1; -+ unsigned int rsvd_0 : 3; -+ unsigned int RO_AD_WF_SX_VCO_ALC_OUT : 1; -+ unsigned int rsvd_1 : 7; -+ unsigned int RO_WF_SX_PT_FSM : 8; -+ unsigned int RO_WF_SX_TOP_FSM : 7; -+ unsigned int rsvd_2 : 1; -+ } b; -+} RG_SX_A5_FIELD_T; -+ -+#define RG_SX_A6 (RF_D_SX_REG_BASE + 0x18) -+// Bit 0 rg_sx_pdiv_sel U RW default = 'h1 -+// Bit 7 :4 rg_sx_osc_freq U RW default = 'h3 -+// Bit 15 :8 rg_2gb_sx_channel U RW default = 'h8 -+// Bit 23 :16 rg_5gb_sx_channel U RW default = 'h64 -+// Bit 27 :24 rg_wifi_freq_mode_man U RW default = 'h0 -+// Bit 31 rg_wifi_freq_mode_man_mode U RW default = 'h0 -+typedef union RG_SX_A6_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_SX_PDIV_SEL : 1; -+ unsigned int rsvd_0 : 3; -+ unsigned int RG_SX_OSC_FREQ : 4; -+ unsigned int RG_2GB_SX_CHANNEL : 8; -+ unsigned int RG_5GB_SX_CHANNEL : 8; -+ unsigned int RG_WIFI_FREQ_MODE_MAN : 4; -+ unsigned int rsvd_1 : 3; -+ unsigned int RG_WIFI_FREQ_MODE_MAN_MODE : 1; -+ } b; -+} RG_SX_A6_FIELD_T; -+ -+#define RG_SX_A7 (RF_D_SX_REG_BASE + 0x1c) -+// Bit 0 rg_sx_rfch_man_en U RW default = 'h0 -+// Bit 14 :4 rg_wf_sx_rfctrl_int U RW default = 'h0 -+typedef union RG_SX_A7_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_SX_RFCH_MAN_EN : 1; -+ unsigned int rsvd_0 : 3; -+ unsigned int RG_WF_SX_RFCTRL_INT : 11; -+ unsigned int rsvd_1 : 17; -+ } b; -+} RG_SX_A7_FIELD_T; -+ -+#define RG_SX_A8 (RF_D_SX_REG_BASE + 0x20) -+// Bit 24 :0 rg_wf_sx_rfctrl_frac U RW default = 'h0 -+typedef union RG_SX_A8_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_RFCTRL_FRAC : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_SX_A8_FIELD_T; -+ -+#define RG_SX_A9 (RF_D_SX_REG_BASE + 0x24) -+// Bit 15 :0 rg_sx_fcal_ntargt U RW default = 'h0 -+// Bit 16 rg_sx_fcal_ntargt_man U RW default = 'h0 -+typedef union RG_SX_A9_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_SX_FCAL_NTARGT : 16; -+ unsigned int RG_SX_FCAL_NTARGT_MAN : 1; -+ unsigned int rsvd_0 : 15; -+ } b; -+} RG_SX_A9_FIELD_T; -+ -+#define RG_SX_A10 (RF_D_SX_REG_BASE + 0x28) -+// Bit 15 :0 ro_wf_sx_fcal_cnt U RO default = 'h0 -+// Bit 28 :16 ro_wf_sx_rf_freq_mhz U RO default = 'h0 -+typedef union RG_SX_A10_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RO_WF_SX_FCAL_CNT : 16; -+ unsigned int RO_WF_SX_RF_FREQ_MHZ : 13; -+ unsigned int rsvd_0 : 3; -+ } b; -+} RG_SX_A10_FIELD_T; -+ -+#define RG_SX_A11 (RF_D_SX_REG_BASE + 0x2c) -+// Bit 1 :0 rg_wf_sx_fcal_hvt U RW default = 'h1 -+// Bit 5 :4 rg_wf_sx_fcal_lvt U RW default = 'h1 -+typedef union RG_SX_A11_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_FCAL_HVT : 2; -+ unsigned int rsvd_0 : 2; -+ unsigned int RG_WF_SX_FCAL_LVT : 2; -+ unsigned int rsvd_1 : 26; -+ } b; -+} RG_SX_A11_FIELD_T; -+ -+#define RG_SX_A12 (RF_D_SX_REG_BASE + 0x30) -+// Bit 10 :0 ro_sx_rfctrl_nint U RO default = 'h0 -+typedef union RG_SX_A12_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RO_SX_RFCTRL_NINT : 11; -+ unsigned int rsvd_0 : 21; -+ } b; -+} RG_SX_A12_FIELD_T; -+ -+#define RG_SX_A13 (RF_D_SX_REG_BASE + 0x34) -+// Bit 24 :0 ro_sx_rfctrl_nfrac U RO default = 'h0 -+typedef union RG_SX_A13_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RO_SX_RFCTRL_NFRAC : 25; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_SX_A13_FIELD_T; -+ -+#define RG_SX_A14 (RF_D_SX_REG_BASE + 0x38) -+// Bit 15 :0 ro_sx_fcal_ntargt U RO default = 'h0 -+typedef union RG_SX_A14_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RO_SX_FCAL_NTARGT : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} RG_SX_A14_FIELD_T; -+ -+#define RG_SX_A15 (RF_D_SX_REG_BASE + 0x3c) -+// Bit 6 rg_tr_switch_man U RW default = 'h0 -+// Bit 7 rg_tr_switch_val U RW default = 'h0 -+typedef union RG_SX_A15_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rsvd_0 : 6; -+ unsigned int RG_TR_SWITCH_MAN : 1; -+ unsigned int RG_TR_SWITCH_VAL : 1; -+ unsigned int rsvd_1 : 24; -+ } b; -+} RG_SX_A15_FIELD_T; -+ -+#define RG_SX_A16 (RF_D_SX_REG_BASE + 0x40) -+// Bit 2 :0 rg_wf_sx_log_pdthreshold_man U RW default = 'h7 -+// Bit 4 rg_wf_sx_log_pd_man_mode U RW default = 'h0 -+// Bit 8 rg_wf_sx_log_pdtest_en U RW default = 'h0 -+typedef union RG_SX_A16_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_LOG_PDTHRESHOLD_MAN : 3; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF_SX_LOG_PD_MAN_MODE : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int RG_WF_SX_LOG_PDTEST_EN : 1; -+ unsigned int rsvd_2 : 23; -+ } b; -+} RG_SX_A16_FIELD_T; -+ -+#define RG_SX_A17 (RF_D_SX_REG_BASE + 0x44) -+// Bit 3 :0 rg_wf_sx_log5g_mxr_banksel_man0 U RW default = 'he -+// Bit 7 :4 rg_wf_sx_log5g_mxr_banksel_man1 U RW default = 'hd -+// Bit 11 :8 rg_wf_sx_log5g_mxr_banksel_man2 U RW default = 'hc -+// Bit 15 :12 rg_wf_sx_log5g_mxr_banksel_man3 U RW default = 'hb -+// Bit 19 :16 rg_wf_sx_log5g_mxr_banksel_man4 U RW default = 'ha -+// Bit 23 :20 rg_wf_sx_log5g_mxr_banksel_man5 U RW default = 'h9 -+// Bit 27 :24 rg_wf_sx_log5g_mxr_banksel_man6 U RW default = 'h8 -+// Bit 31 :28 rg_wf_sx_log5g_mxr_banksel_man7 U RW default = 'h7 -+typedef union RG_SX_A17_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN0 : 4; -+ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN1 : 4; -+ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN2 : 4; -+ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN3 : 4; -+ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN4 : 4; -+ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN5 : 4; -+ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN6 : 4; -+ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN7 : 4; -+ } b; -+} RG_SX_A17_FIELD_T; -+ -+#define RG_SX_A18 (RF_D_SX_REG_BASE + 0x48) -+// Bit 3 :0 rg_wf_sx_log5g_mxr_banksel_man8 U RW default = 'h6 -+// Bit 7 :4 rg_wf_sx_log5g_mxr_banksel_man9 U RW default = 'h4 -+// Bit 11 :8 rg_wf_sx_log2g_mxr_banksel_man U RW default = 'h6 -+typedef union RG_SX_A18_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN8 : 4; -+ unsigned int RG_WF_SX_LOG5G_MXR_BANKSEL_MAN9 : 4; -+ unsigned int RG_WF_SX_LOG2G_MXR_BANKSEL_MAN : 4; -+ unsigned int rsvd_0 : 20; -+ } b; -+} RG_SX_A18_FIELD_T; -+ -+#define RG_SX_A20 (RF_D_SX_REG_BASE + 0x50) -+// Bit 3 :0 ro_wf_sx_log5g_mxr_banksel_0 U RO default = 'h0 -+// Bit 7 :4 ro_wf_sx_log5g_mxr_banksel_1 U RO default = 'h0 -+// Bit 11 :8 ro_wf_sx_log5g_mxr_banksel_2 U RO default = 'h0 -+// Bit 15 :12 ro_wf_sx_log5g_mxr_banksel_3 U RO default = 'h0 -+// Bit 19 :16 ro_wf_sx_log5g_mxr_banksel_4 U RO default = 'h0 -+// Bit 23 :20 ro_wf_sx_log5g_mxr_banksel_5 U RO default = 'h0 -+// Bit 27 :24 ro_wf_sx_log5g_mxr_banksel_6 U RO default = 'h0 -+// Bit 31 :28 ro_wf_sx_log5g_mxr_banksel_7 U RO default = 'h0 -+typedef union RG_SX_A20_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_0 : 4; -+ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_1 : 4; -+ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_2 : 4; -+ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_3 : 4; -+ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_4 : 4; -+ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_5 : 4; -+ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_6 : 4; -+ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_7 : 4; -+ } b; -+} RG_SX_A20_FIELD_T; -+ -+#define RG_SX_A21 (RF_D_SX_REG_BASE + 0x54) -+// Bit 3 :0 ro_wf_sx_log5g_mxr_banksel_8 U RO default = 'h0 -+// Bit 7 :4 ro_wf_sx_log5g_mxr_banksel_9 U RO default = 'h0 -+// Bit 11 :8 ro_wf_sx_log2g_mxr_banksel U RO default = 'h0 -+typedef union RG_SX_A21_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_8 : 4; -+ unsigned int RO_WF_SX_LOG5G_MXR_BANKSEL_9 : 4; -+ unsigned int RO_WF_SX_LOG2G_MXR_BANKSEL : 4; -+ unsigned int rsvd_0 : 20; -+ } b; -+} RG_SX_A21_FIELD_T; -+ -+#define RG_SX_A23 (RF_D_SX_REG_BASE + 0x5c) -+// Bit 0 rg_m0_wf_sx_vco_en U RW default = 'h0 -+// Bit 1 rg_m0_wf_sx_vco_acal_en U RW default = 'h0 -+// Bit 2 rg_m0_wf_sx_pfd_en U RW default = 'h0 -+// Bit 3 rg_m0_wf_sx_cp_en U RW default = 'h0 -+// Bit 4 rg_m0_wf_sx_vco_ldo_en U RW default = 'h0 -+// Bit 5 rg_m0_wf_sx_cp_ldo_en U RW default = 'h0 -+// Bit 6 rg_m0_wf_sx_lpf_comp_en U RW default = 'h0 -+// Bit 7 rg_m0_wf_sx_log5g_mxr_en U RW default = 'h0 -+// Bit 8 rg_m0_wf_sx_log5g_inv_en U RW default = 'h0 -+// Bit 9 rg_m0_wf_sx_log5g_div_en U RW default = 'h0 -+// Bit 10 rg_m0_wf_sx_log5g_iqdiv_en U RW default = 'h0 -+// Bit 11 rg_m0_wf_sx_log5g_rxlo_en U RW default = 'h0 -+// Bit 12 rg_m0_wf_sx_log5g_dpdlo_en U RW default = 'h0 -+// Bit 13 rg_m0_wf_sx_log5g_txlo_en U RW default = 'h0 -+// Bit 14 rg_m0_wf_sx_log2g_mxr_en U RW default = 'h0 -+// Bit 15 rg_m0_wf_sx_log2g_div_en U RW default = 'h0 -+// Bit 16 rg_m0_wf_sx_log2g_iqdiv_en U RW default = 'h0 -+// Bit 17 rg_m0_wf_sx_log2g_rxlo_en U RW default = 'h0 -+// Bit 18 rg_m0_wf_sx_log2g_dpdlo_en U RW default = 'h0 -+// Bit 19 rg_m0_wf_sx_log2g_txlo_en U RW default = 'h0 -+typedef union RG_SX_A23_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M0_WF_SX_VCO_EN : 1; -+ unsigned int RG_M0_WF_SX_VCO_ACAL_EN : 1; -+ unsigned int RG_M0_WF_SX_PFD_EN : 1; -+ unsigned int RG_M0_WF_SX_CP_EN : 1; -+ unsigned int RG_M0_WF_SX_VCO_LDO_EN : 1; -+ unsigned int RG_M0_WF_SX_CP_LDO_EN : 1; -+ unsigned int RG_M0_WF_SX_LPF_COMP_EN : 1; -+ unsigned int RG_M0_WF_SX_LOG5G_MXR_EN : 1; -+ unsigned int RG_M0_WF_SX_LOG5G_INV_EN : 1; -+ unsigned int RG_M0_WF_SX_LOG5G_DIV_EN : 1; -+ unsigned int RG_M0_WF_SX_LOG5G_IQDIV_EN : 1; -+ unsigned int RG_M0_WF_SX_LOG5G_RXLO_EN : 1; -+ unsigned int RG_M0_WF_SX_LOG5G_DPDLO_EN : 1; -+ unsigned int RG_M0_WF_SX_LOG5G_TXLO_EN : 1; -+ unsigned int RG_M0_WF_SX_LOG2G_MXR_EN : 1; -+ unsigned int RG_M0_WF_SX_LOG2G_DIV_EN : 1; -+ unsigned int RG_M0_WF_SX_LOG2G_IQDIV_EN : 1; -+ unsigned int RG_M0_WF_SX_LOG2G_RXLO_EN : 1; -+ unsigned int RG_M0_WF_SX_LOG2G_DPDLO_EN : 1; -+ unsigned int RG_M0_WF_SX_LOG2G_TXLO_EN : 1; -+ unsigned int rsvd_0 : 12; -+ } b; -+} RG_SX_A23_FIELD_T; -+ -+#define RG_SX_A24 (RF_D_SX_REG_BASE + 0x60) -+// Bit 0 rg_m1_wf_sx_vco_en U RW default = 'h1 -+// Bit 1 rg_m1_wf_sx_vco_acal_en U RW default = 'h1 -+// Bit 2 rg_m1_wf_sx_pfd_en U RW default = 'h1 -+// Bit 3 rg_m1_wf_sx_cp_en U RW default = 'h1 -+// Bit 4 rg_m1_wf_sx_vco_ldo_en U RW default = 'h1 -+// Bit 5 rg_m1_wf_sx_cp_ldo_en U RW default = 'h1 -+// Bit 6 rg_m1_wf_sx_lpf_comp_en U RW default = 'h1 -+// Bit 7 rg_m1_wf_sx_log5g_mxr_en U RW default = 'h1 -+// Bit 8 rg_m1_wf_sx_log5g_inv_en U RW default = 'h1 -+// Bit 9 rg_m1_wf_sx_log5g_div_en U RW default = 'h1 -+// Bit 10 rg_m1_wf_sx_log5g_iqdiv_en U RW default = 'h1 -+// Bit 11 rg_m1_wf_sx_log5g_rxlo_en U RW default = 'h0 -+// Bit 12 rg_m1_wf_sx_log5g_dpdlo_en U RW default = 'h0 -+// Bit 13 rg_m1_wf_sx_log5g_txlo_en U RW default = 'h0 -+// Bit 14 rg_m1_wf_sx_log2g_mxr_en U RW default = 'h0 -+// Bit 15 rg_m1_wf_sx_log2g_div_en U RW default = 'h0 -+// Bit 16 rg_m1_wf_sx_log2g_iqdiv_en U RW default = 'h0 -+// Bit 17 rg_m1_wf_sx_log2g_rxlo_en U RW default = 'h0 -+// Bit 18 rg_m1_wf_sx_log2g_dpdlo_en U RW default = 'h0 -+// Bit 19 rg_m1_wf_sx_log2g_txlo_en U RW default = 'h0 -+typedef union RG_SX_A24_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M1_WF_SX_VCO_EN : 1; -+ unsigned int RG_M1_WF_SX_VCO_ACAL_EN : 1; -+ unsigned int RG_M1_WF_SX_PFD_EN : 1; -+ unsigned int RG_M1_WF_SX_CP_EN : 1; -+ unsigned int RG_M1_WF_SX_VCO_LDO_EN : 1; -+ unsigned int RG_M1_WF_SX_CP_LDO_EN : 1; -+ unsigned int RG_M1_WF_SX_LPF_COMP_EN : 1; -+ unsigned int RG_M1_WF_SX_LOG5G_MXR_EN : 1; -+ unsigned int RG_M1_WF_SX_LOG5G_INV_EN : 1; -+ unsigned int RG_M1_WF_SX_LOG5G_DIV_EN : 1; -+ unsigned int RG_M1_WF_SX_LOG5G_IQDIV_EN : 1; -+ unsigned int RG_M1_WF_SX_LOG5G_RXLO_EN : 1; -+ unsigned int RG_M1_WF_SX_LOG5G_DPDLO_EN : 1; -+ unsigned int RG_M1_WF_SX_LOG5G_TXLO_EN : 1; -+ unsigned int RG_M1_WF_SX_LOG2G_MXR_EN : 1; -+ unsigned int RG_M1_WF_SX_LOG2G_DIV_EN : 1; -+ unsigned int RG_M1_WF_SX_LOG2G_IQDIV_EN : 1; -+ unsigned int RG_M1_WF_SX_LOG2G_RXLO_EN : 1; -+ unsigned int RG_M1_WF_SX_LOG2G_DPDLO_EN : 1; -+ unsigned int RG_M1_WF_SX_LOG2G_TXLO_EN : 1; -+ unsigned int rsvd_0 : 12; -+ } b; -+} RG_SX_A24_FIELD_T; -+ -+#define RG_SX_A25 (RF_D_SX_REG_BASE + 0x64) -+// Bit 0 rg_m2_wf_sx_vco_en U RW default = 'h1 -+// Bit 1 rg_m2_wf_sx_vco_acal_en U RW default = 'h1 -+// Bit 2 rg_m2_wf_sx_pfd_en U RW default = 'h1 -+// Bit 3 rg_m2_wf_sx_cp_en U RW default = 'h1 -+// Bit 4 rg_m2_wf_sx_vco_ldo_en U RW default = 'h1 -+// Bit 5 rg_m2_wf_sx_cp_ldo_en U RW default = 'h1 -+// Bit 6 rg_m2_wf_sx_lpf_comp_en U RW default = 'h1 -+// Bit 7 rg_m2_wf_sx_log5g_mxr_en U RW default = 'h1 -+// Bit 8 rg_m2_wf_sx_log5g_inv_en U RW default = 'h1 -+// Bit 9 rg_m2_wf_sx_log5g_div_en U RW default = 'h1 -+// Bit 10 rg_m2_wf_sx_log5g_iqdiv_en U RW default = 'h1 -+// Bit 11 rg_m2_wf_sx_log5g_rxlo_en U RW default = 'h0 -+// Bit 12 rg_m2_wf_sx_log5g_dpdlo_en U RW default = 'h0 -+// Bit 13 rg_m2_wf_sx_log5g_txlo_en U RW default = 'h1 -+// Bit 14 rg_m2_wf_sx_log2g_mxr_en U RW default = 'h0 -+// Bit 15 rg_m2_wf_sx_log2g_div_en U RW default = 'h0 -+// Bit 16 rg_m2_wf_sx_log2g_iqdiv_en U RW default = 'h0 -+// Bit 17 rg_m2_wf_sx_log2g_rxlo_en U RW default = 'h0 -+// Bit 18 rg_m2_wf_sx_log2g_dpdlo_en U RW default = 'h0 -+// Bit 19 rg_m2_wf_sx_log2g_txlo_en U RW default = 'h1 -+typedef union RG_SX_A25_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M2_WF_SX_VCO_EN : 1; -+ unsigned int RG_M2_WF_SX_VCO_ACAL_EN : 1; -+ unsigned int RG_M2_WF_SX_PFD_EN : 1; -+ unsigned int RG_M2_WF_SX_CP_EN : 1; -+ unsigned int RG_M2_WF_SX_VCO_LDO_EN : 1; -+ unsigned int RG_M2_WF_SX_CP_LDO_EN : 1; -+ unsigned int RG_M2_WF_SX_LPF_COMP_EN : 1; -+ unsigned int RG_M2_WF_SX_LOG5G_MXR_EN : 1; -+ unsigned int RG_M2_WF_SX_LOG5G_INV_EN : 1; -+ unsigned int RG_M2_WF_SX_LOG5G_DIV_EN : 1; -+ unsigned int RG_M2_WF_SX_LOG5G_IQDIV_EN : 1; -+ unsigned int RG_M2_WF_SX_LOG5G_RXLO_EN : 1; -+ unsigned int RG_M2_WF_SX_LOG5G_DPDLO_EN : 1; -+ unsigned int RG_M2_WF_SX_LOG5G_TXLO_EN : 1; -+ unsigned int RG_M2_WF_SX_LOG2G_MXR_EN : 1; -+ unsigned int RG_M2_WF_SX_LOG2G_DIV_EN : 1; -+ unsigned int RG_M2_WF_SX_LOG2G_IQDIV_EN : 1; -+ unsigned int RG_M2_WF_SX_LOG2G_RXLO_EN : 1; -+ unsigned int RG_M2_WF_SX_LOG2G_DPDLO_EN : 1; -+ unsigned int RG_M2_WF_SX_LOG2G_TXLO_EN : 1; -+ unsigned int rsvd_0 : 12; -+ } b; -+} RG_SX_A25_FIELD_T; -+ -+#define RG_SX_A26 (RF_D_SX_REG_BASE + 0x68) -+// Bit 0 rg_m3_wf_sx_vco_en U RW default = 'h1 -+// Bit 1 rg_m3_wf_sx_vco_acal_en U RW default = 'h1 -+// Bit 2 rg_m3_wf_sx_pfd_en U RW default = 'h1 -+// Bit 3 rg_m3_wf_sx_cp_en U RW default = 'h1 -+// Bit 4 rg_m3_wf_sx_vco_ldo_en U RW default = 'h1 -+// Bit 5 rg_m3_wf_sx_cp_ldo_en U RW default = 'h1 -+// Bit 6 rg_m3_wf_sx_lpf_comp_en U RW default = 'h1 -+// Bit 7 rg_m3_wf_sx_log5g_mxr_en U RW default = 'h1 -+// Bit 8 rg_m3_wf_sx_log5g_inv_en U RW default = 'h1 -+// Bit 9 rg_m3_wf_sx_log5g_div_en U RW default = 'h1 -+// Bit 10 rg_m3_wf_sx_log5g_iqdiv_en U RW default = 'h1 -+// Bit 11 rg_m3_wf_sx_log5g_rxlo_en U RW default = 'h1 -+// Bit 12 rg_m3_wf_sx_log5g_dpdlo_en U RW default = 'h0 -+// Bit 13 rg_m3_wf_sx_log5g_txlo_en U RW default = 'h0 -+// Bit 14 rg_m3_wf_sx_log2g_mxr_en U RW default = 'h0 -+// Bit 15 rg_m3_wf_sx_log2g_div_en U RW default = 'h0 -+// Bit 16 rg_m3_wf_sx_log2g_iqdiv_en U RW default = 'h0 -+// Bit 17 rg_m3_wf_sx_log2g_rxlo_en U RW default = 'h0 -+// Bit 18 rg_m3_wf_sx_log2g_dpdlo_en U RW default = 'h0 -+// Bit 19 rg_m3_wf_sx_log2g_txlo_en U RW default = 'h0 -+typedef union RG_SX_A26_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M3_WF_SX_VCO_EN : 1; -+ unsigned int RG_M3_WF_SX_VCO_ACAL_EN : 1; -+ unsigned int RG_M3_WF_SX_PFD_EN : 1; -+ unsigned int RG_M3_WF_SX_CP_EN : 1; -+ unsigned int RG_M3_WF_SX_VCO_LDO_EN : 1; -+ unsigned int RG_M3_WF_SX_CP_LDO_EN : 1; -+ unsigned int RG_M3_WF_SX_LPF_COMP_EN : 1; -+ unsigned int RG_M3_WF_SX_LOG5G_MXR_EN : 1; -+ unsigned int RG_M3_WF_SX_LOG5G_INV_EN : 1; -+ unsigned int RG_M3_WF_SX_LOG5G_DIV_EN : 1; -+ unsigned int RG_M3_WF_SX_LOG5G_IQDIV_EN : 1; -+ unsigned int RG_M3_WF_SX_LOG5G_RXLO_EN : 1; -+ unsigned int RG_M3_WF_SX_LOG5G_DPDLO_EN : 1; -+ unsigned int RG_M3_WF_SX_LOG5G_TXLO_EN : 1; -+ unsigned int RG_M3_WF_SX_LOG2G_MXR_EN : 1; -+ unsigned int RG_M3_WF_SX_LOG2G_DIV_EN : 1; -+ unsigned int RG_M3_WF_SX_LOG2G_IQDIV_EN : 1; -+ unsigned int RG_M3_WF_SX_LOG2G_RXLO_EN : 1; -+ unsigned int RG_M3_WF_SX_LOG2G_DPDLO_EN : 1; -+ unsigned int RG_M3_WF_SX_LOG2G_TXLO_EN : 1; -+ unsigned int rsvd_0 : 12; -+ } b; -+} RG_SX_A26_FIELD_T; -+ -+#define RG_SX_A27 (RF_D_SX_REG_BASE + 0x6c) -+// Bit 31 :0 rg_wf_sx_dig_rsv0 U RW default = 'hffff -+typedef union RG_SX_A27_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_DIG_RSV0 : 32; -+ } b; -+} RG_SX_A27_FIELD_T; -+ -+#define RG_SX_A32 (RF_D_SX_REG_BASE + 0x80) -+// Bit 2 :0 rg_wf_sx_lpf_bw U RW default = 'h7 -+// Bit 5 :4 rg_wf_sx_pfd_delay U RW default = 'h0 -+// Bit 10 :8 rg_wf_sx_cp_offset U RW default = 'h5 -+// Bit 13 :12 rg_wf_sx_stable_cnt U RW default = 'h0 -+// Bit 16 rg_wf_sx_stable_en_man_mode U RW default = 'h0 -+// Bit 20 rg_wf_sx_stable_en_man U RW default = 'h0 -+typedef union RG_SX_A32_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_LPF_BW : 3; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF_SX_PFD_DELAY : 2; -+ unsigned int rsvd_1 : 2; -+ unsigned int RG_WF_SX_CP_OFFSET : 3; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF_SX_STABLE_CNT : 2; -+ unsigned int rsvd_3 : 2; -+ unsigned int RG_WF_SX_STABLE_EN_MAN_MODE : 1; -+ unsigned int rsvd_4 : 3; -+ unsigned int RG_WF_SX_STABLE_EN_MAN : 1; -+ unsigned int rsvd_5 : 11; -+ } b; -+} RG_SX_A32_FIELD_T; -+ -+#define RG_SX_A34 (RF_D_SX_REG_BASE + 0x88) -+// Bit 8 :4 rg_wf_sx_vco_ldo_vref_adj U RW default = 'h14 -+// Bit 20 :16 rg_wf_sx_cp_ldo_vref_adj U RW default = 'h10 -+typedef union RG_SX_A34_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rsvd_0 : 4; -+ unsigned int RG_WF_SX_VCO_LDO_VREF_ADJ : 5; -+ unsigned int rsvd_1 : 7; -+ unsigned int RG_WF_SX_CP_LDO_VREF_ADJ : 5; -+ unsigned int rsvd_2 : 11; -+ } b; -+} RG_SX_A34_FIELD_T; -+ -+#define RG_SX_A35 (RF_D_SX_REG_BASE + 0x8c) -+// Bit 2 :0 rg_wf_sx_cp_i U RW default = 'h5 -+// Bit 4 :3 rg_wf_sx_pfd_lock_t U RW default = 'h0 -+// Bit 5 rg_wf_sx_pfd_ph_en U RW default = 'h1 -+// Bit 6 rg_wf_sx_pfd_sel U RW default = 'h0 -+// Bit 8 rg_wf_sx_mmd_pw_en U RW default = 'h1 -+// Bit 9 rg_wf_sx_cp_bypass_mode U RW default = 'h0 -+// Bit 10 rg_wf_sx_lpf_bypass_mode U RW default = 'h0 -+// Bit 11 rg_wf_sx_lpf_resample_mode U RW default = 'h1 -+// Bit 12 rg_wf_sx_cp_cali_ctrl U RW default = 'h0 -+// Bit 13 rg_wf_sx_lpf_cali_ctrl U RW default = 'h0 -+// Bit 14 rg_wf_sx_cp_rc_ctrl U RW default = 'h0 -+// Bit 15 rg_wf_sx_ldo_hf_rc_ctrl U RW default = 'h1 -+// Bit 16 rg_wf_sx_ldo_hf_rc_modesel U RW default = 'h0 -+// Bit 17 rg_wf_sx_ldo_lf_rc_ctrl U RW default = 'h1 -+// Bit 18 rg_wf_sx_ldo_lf_rc_modesel U RW default = 'h0 -+// Bit 19 rg_wf_sx_pll_rst_man U RW default = 'h0 -+// Bit 20 rg_wf_sx_pll_rst_man_val U RW default = 'h0 -+// Bit 22 :21 rg_wf_sx_vctrl_sel U RW default = 'h0 -+// Bit 24 :23 rg_wf_sx_vco_var_dc U RW default = 'h3 -+// Bit 25 rg_wf_sx_fcal_div U RW default = 'h1 -+// Bit 27 :26 rg_wf_sx_vco_2nd_capn U RW default = 'h1 -+// Bit 29 :28 rg_wf_sx_vco_2nd_capp U RW default = 'h1 -+// Bit 30 rg_sx_vco_lpf_testmode U RW default = 'h0 -+typedef union RG_SX_A35_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_CP_I : 3; -+ unsigned int RG_WF_SX_PFD_LOCK_T : 2; -+ unsigned int RG_WF_SX_PFD_PH_EN : 1; -+ unsigned int RG_WF_SX_PFD_SEL : 1; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF_SX_MMD_PW_EN : 1; -+ unsigned int RG_WF_SX_CP_BYPASS_MODE : 1; -+ unsigned int RG_WF_SX_LPF_BYPASS_MODE : 1; -+ unsigned int RG_WF_SX_LPF_RESAMPLE_MODE : 1; -+ unsigned int RG_WF_SX_CP_CALI_CTRL : 1; -+ unsigned int RG_WF_SX_LPF_CALI_CTRL : 1; -+ unsigned int RG_WF_SX_CP_RC_CTRL : 1; -+ unsigned int RG_WF_SX_LDO_HF_RC_CTRL : 1; -+ unsigned int RG_WF_SX_LDO_HF_RC_MODESEL : 1; -+ unsigned int RG_WF_SX_LDO_LF_RC_CTRL : 1; -+ unsigned int RG_WF_SX_LDO_LF_RC_MODESEL : 1; -+ unsigned int RG_WF_SX_PLL_RST_MAN : 1; -+ unsigned int RG_WF_SX_PLL_RST_MAN_VAL : 1; -+ unsigned int RG_WF_SX_VCTRL_SEL : 2; -+ unsigned int RG_WF_SX_VCO_VAR_DC : 2; -+ unsigned int RG_WF_SX_FCAL_DIV : 1; -+ unsigned int RG_WF_SX_VCO_2ND_CAPN : 2; -+ unsigned int RG_WF_SX_VCO_2ND_CAPP : 2; -+ unsigned int RG_SX_VCO_LPF_TESTMODE : 1; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_SX_A35_FIELD_T; -+ -+#define RG_SX_A36 (RF_D_SX_REG_BASE + 0x90) -+// Bit 0 rg_wf_sx_log5g_pd_en_man U RW default = 'h0 -+// Bit 4 rg_wf_sx_log2g_pd_en_man U RW default = 'h0 -+// Bit 11 :8 rg_wf_sx_log5g_mxr_ictrl U RW default = 'ha -+// Bit 15 :12 rg_wf_sx_log5g_div_vdd U RW default = 'h1 -+// Bit 31 rg_wf_sx_log5g_reserve1 U RW default = 'h0 -+typedef union RG_SX_A36_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_LOG5G_PD_EN_MAN : 1; -+ unsigned int rsvd_0 : 3; -+ unsigned int RG_WF_SX_LOG2G_PD_EN_MAN : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int RG_WF_SX_LOG5G_MXR_ICTRL : 4; -+ unsigned int RG_WF_SX_LOG5G_DIV_VDD : 4; -+ unsigned int rsvd_2 : 15; -+ unsigned int RG_WF_SX_LOG5G_RESERVE1 : 1; -+ } b; -+} RG_SX_A36_FIELD_T; -+ -+#define RG_SX_A37 (RF_D_SX_REG_BASE + 0x94) -+// Bit 3 :0 rg_wf_sx_log5g_rxlo_vdd U RW default = 'h7 -+// Bit 7 :4 rg_wf_sx_log5g_dpdlo_vdd U RW default = 'h7 -+// Bit 11 :8 rg_wf_sx_log5g_txlo_vdd U RW default = 'h7 -+// Bit 15 :12 rg_wf_sx_log5g_iqdiv_rctrl U RW default = 'h0 -+// Bit 20 :16 rg_wf_sx_log5g_iqdiv_ictrl U RW default = 'h6 -+typedef union RG_SX_A37_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_LOG5G_RXLO_VDD : 4; -+ unsigned int RG_WF_SX_LOG5G_DPDLO_VDD : 4; -+ unsigned int RG_WF_SX_LOG5G_TXLO_VDD : 4; -+ unsigned int RG_WF_SX_LOG5G_IQDIV_RCTRL : 4; -+ unsigned int RG_WF_SX_LOG5G_IQDIV_ICTRL : 5; -+ unsigned int rsvd_0 : 11; -+ } b; -+} RG_SX_A37_FIELD_T; -+ -+#define RG_SX_A38 (RF_D_SX_REG_BASE + 0x98) -+// Bit 3 :0 rg_wf_sx_log2g_mxr_vdd U RW default = 'hf -+// Bit 7 :4 rg_wf_sx_log2g_div_vdd U RW default = 'h1 -+// Bit 11 :8 rg_wf_sx_log2g_iqdiv_vdd U RW default = 'h1 -+// Bit 15 :12 rg_wf_sx_log2g_rxlo_vdd U RW default = 'h4 -+// Bit 19 :16 rg_wf_sx_log2g_dpdlo_vdd U RW default = 'h4 -+// Bit 23 :20 rg_wf_sx_log2g_txlo_vdd U RW default = 'h4 -+typedef union RG_SX_A38_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_LOG2G_MXR_VDD : 4; -+ unsigned int RG_WF_SX_LOG2G_DIV_VDD : 4; -+ unsigned int RG_WF_SX_LOG2G_IQDIV_VDD : 4; -+ unsigned int RG_WF_SX_LOG2G_RXLO_VDD : 4; -+ unsigned int RG_WF_SX_LOG2G_DPDLO_VDD : 4; -+ unsigned int RG_WF_SX_LOG2G_TXLO_VDD : 4; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_SX_A38_FIELD_T; -+ -+#define RG_SX_A42 (RF_D_SX_REG_BASE + 0xa8) -+// Bit 31 :0 rg_wf_sx_rsv0 U RW default = 'hfffb -+typedef union RG_SX_A42_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_RSV0 : 32; -+ } b; -+} RG_SX_A42_FIELD_T; -+ -+#define RG_SX_A43 (RF_D_SX_REG_BASE + 0xac) -+// Bit 31 :0 rg_wf_sx_rsv1 U RW default = 'hffff -+typedef union RG_SX_A43_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_RSV1 : 32; -+ } b; -+} RG_SX_A43_FIELD_T; -+ -+#define RG_SX_A44 (RF_D_SX_REG_BASE + 0xb0) -+// Bit 0 rg_wf_sx_double_edge_sel U RW default = 'h0 -+// Bit 1 rg_wf_sx_double_bypass_mode U RW default = 'h1 -+// Bit 2 rg_wf_sx_double_dig_loop_en U RW default = 'h0 -+// Bit 3 rg_wf_sx_double_ana_loop_en U RW default = 'h0 -+// Bit 4 rg_wf_sx_double_half_lsb_ctrl U RW default = 'h0 -+// Bit 5 rg_wf_sx_double_half_lsb_sel U RW default = 'h1 -+// Bit 6 rg_wf_sx_double_post_delay_en U RW default = 'h1 -+// Bit 7 rg_wf_sx_double_pre_delay_en U RW default = 'h1 -+// Bit 8 rg_wf_sx_double_op_en U RW default = 'h1 -+// Bit 11 :9 rg_wf_sx_double_vref_sel U RW default = 'h4 -+// Bit 19 :12 rg_wf_sx_double_reserved U RW default = 'h0 -+// Bit 21 rg_wf_sx_double_rst_man_mode U RW default = 'h0 -+// Bit 22 rg_wf_sx_double_rst_man U RW default = 'h0 -+// Bit 23 rg_wf_sx_double_tune_man_mode U RW default = 'h0 -+// Bit 30 :24 rg_wf_sx_double_tune_man U RW default = 'h0 -+typedef union RG_SX_A44_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_DOUBLE_EDGE_SEL : 1; -+ unsigned int RG_WF_SX_DOUBLE_BYPASS_MODE : 1; -+ unsigned int RG_WF_SX_DOUBLE_DIG_LOOP_EN : 1; -+ unsigned int RG_WF_SX_DOUBLE_ANA_LOOP_EN : 1; -+ unsigned int RG_WF_SX_DOUBLE_HALF_LSB_CTRL : 1; -+ unsigned int RG_WF_SX_DOUBLE_HALF_LSB_SEL : 1; -+ unsigned int RG_WF_SX_DOUBLE_POST_DELAY_EN : 1; -+ unsigned int RG_WF_SX_DOUBLE_PRE_DELAY_EN : 1; -+ unsigned int RG_WF_SX_DOUBLE_OP_EN : 1; -+ unsigned int RG_WF_SX_DOUBLE_VREF_SEL : 3; -+ unsigned int RG_WF_SX_DOUBLE_RESERVED : 8; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF_SX_DOUBLE_RST_MAN_MODE : 1; -+ unsigned int RG_WF_SX_DOUBLE_RST_MAN : 1; -+ unsigned int RG_WF_SX_DOUBLE_TUNE_MAN_MODE : 1; -+ unsigned int RG_WF_SX_DOUBLE_TUNE_MAN : 7; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_SX_A44_FIELD_T; -+ -+#define RG_SX_A45 (RF_D_SX_REG_BASE + 0xb4) -+// Bit 0 rg_wf_sx_open_drain_tp_en U RW default = 'h0 -+// Bit 1 rg_wf_sx_vco_vctrl_tp_sel U RW default = 'h0 -+// Bit 2 rg_wf_sx_tp_en U RW default = 'h0 -+// Bit 5 :3 rg_wf_sx_tp_sel U RW default = 'h4 -+// Bit 6 rg_wf_sx_fb_clk_edge_sel U RW default = 'h0 -+// Bit 7 rg_wf_sx_clk_edge_sel U RW default = 'h0 -+// Bit 8 rg_wf_sx_double_cali_en U RW default = 'h0 -+// Bit 9 rg_wf_sx_double_en U RW default = 'h0 -+// Bit 13 :12 rg_wf_sx_double_waittime_25u U RW default = 'h0 -+// Bit 15 :14 rg_wf_sx_double_waittime_40u U RW default = 'h0 -+// Bit 23 :16 rg_wf_sx_double_check_code_cnt U RW default = 'h80 -+// Bit 31 rg_wf_sx_double_duty_flag_sel U RW default = 'h0 -+typedef union RG_SX_A45_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_SX_OPEN_DRAIN_TP_EN : 1; -+ unsigned int RG_WF_SX_VCO_VCTRL_TP_SEL : 1; -+ unsigned int RG_WF_SX_TP_EN : 1; -+ unsigned int RG_WF_SX_TP_SEL : 3; -+ unsigned int RG_WF_SX_FB_CLK_EDGE_SEL : 1; -+ unsigned int RG_WF_SX_CLK_EDGE_SEL : 1; -+ unsigned int RG_WF_SX_DOUBLE_CALI_EN : 1; -+ unsigned int RG_WF_SX_DOUBLE_EN : 1; -+ unsigned int rsvd_0 : 2; -+ unsigned int RG_WF_SX_DOUBLE_WAITTIME_25U : 2; -+ unsigned int RG_WF_SX_DOUBLE_WAITTIME_40U : 2; -+ unsigned int RG_WF_SX_DOUBLE_CHECK_CODE_CNT : 8; -+ unsigned int rsvd_1 : 7; -+ unsigned int RG_WF_SX_DOUBLE_DUTY_FLAG_SEL : 1; -+ } b; -+} RG_SX_A45_FIELD_T; -+ -+#define RG_SX_A46 (RF_D_SX_REG_BASE + 0xb8) -+// Bit 0 rg_m4_wf_sx_vco_en U RW default = 'h1 -+// Bit 1 rg_m4_wf_sx_vco_acal_en U RW default = 'h1 -+// Bit 2 rg_m4_wf_sx_pfd_en U RW default = 'h1 -+// Bit 3 rg_m4_wf_sx_cp_en U RW default = 'h1 -+// Bit 4 rg_m4_wf_sx_vco_ldo_en U RW default = 'h1 -+// Bit 5 rg_m4_wf_sx_cp_ldo_en U RW default = 'h1 -+// Bit 6 rg_m4_wf_sx_lpf_comp_en U RW default = 'h1 -+// Bit 7 rg_m4_wf_sx_log5g_mxr_en U RW default = 'h1 -+// Bit 8 rg_m4_wf_sx_log5g_inv_en U RW default = 'h1 -+// Bit 9 rg_m4_wf_sx_log5g_div_en U RW default = 'h1 -+// Bit 10 rg_m4_wf_sx_log5g_iqdiv_en U RW default = 'h1 -+// Bit 11 rg_m4_wf_sx_log5g_rxlo_en U RW default = 'h0 -+// Bit 12 rg_m4_wf_sx_log5g_dpdlo_en U RW default = 'h1 -+// Bit 13 rg_m4_wf_sx_log5g_txlo_en U RW default = 'h1 -+// Bit 14 rg_m4_wf_sx_log2g_mxr_en U RW default = 'h0 -+// Bit 15 rg_m4_wf_sx_log2g_div_en U RW default = 'h0 -+// Bit 16 rg_m4_wf_sx_log2g_iqdiv_en U RW default = 'h0 -+// Bit 17 rg_m4_wf_sx_log2g_rxlo_en U RW default = 'h0 -+// Bit 18 rg_m4_wf_sx_log2g_dpdlo_en U RW default = 'h0 -+// Bit 19 rg_m4_wf_sx_log2g_txlo_en U RW default = 'h0 -+typedef union RG_SX_A46_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M4_WF_SX_VCO_EN : 1; -+ unsigned int RG_M4_WF_SX_VCO_ACAL_EN : 1; -+ unsigned int RG_M4_WF_SX_PFD_EN : 1; -+ unsigned int RG_M4_WF_SX_CP_EN : 1; -+ unsigned int RG_M4_WF_SX_VCO_LDO_EN : 1; -+ unsigned int RG_M4_WF_SX_CP_LDO_EN : 1; -+ unsigned int RG_M4_WF_SX_LPF_COMP_EN : 1; -+ unsigned int RG_M4_WF_SX_LOG5G_MXR_EN : 1; -+ unsigned int RG_M4_WF_SX_LOG5G_INV_EN : 1; -+ unsigned int RG_M4_WF_SX_LOG5G_DIV_EN : 1; -+ unsigned int RG_M4_WF_SX_LOG5G_IQDIV_EN : 1; -+ unsigned int RG_M4_WF_SX_LOG5G_RXLO_EN : 1; -+ unsigned int RG_M4_WF_SX_LOG5G_DPDLO_EN : 1; -+ unsigned int RG_M4_WF_SX_LOG5G_TXLO_EN : 1; -+ unsigned int RG_M4_WF_SX_LOG2G_MXR_EN : 1; -+ unsigned int RG_M4_WF_SX_LOG2G_DIV_EN : 1; -+ unsigned int RG_M4_WF_SX_LOG2G_IQDIV_EN : 1; -+ unsigned int RG_M4_WF_SX_LOG2G_RXLO_EN : 1; -+ unsigned int RG_M4_WF_SX_LOG2G_DPDLO_EN : 1; -+ unsigned int RG_M4_WF_SX_LOG2G_TXLO_EN : 1; -+ unsigned int rsvd_0 : 12; -+ } b; -+} RG_SX_A46_FIELD_T; -+ -+#define RG_SX_A47 (RF_D_SX_REG_BASE + 0xbc) -+// Bit 0 rg_m5_wf_sx_vco_en U RW default = 'h1 -+// Bit 1 rg_m5_wf_sx_vco_acal_en U RW default = 'h1 -+// Bit 2 rg_m5_wf_sx_pfd_en U RW default = 'h1 -+// Bit 3 rg_m5_wf_sx_cp_en U RW default = 'h1 -+// Bit 4 rg_m5_wf_sx_vco_ldo_en U RW default = 'h1 -+// Bit 5 rg_m5_wf_sx_cp_ldo_en U RW default = 'h1 -+// Bit 6 rg_m5_wf_sx_lpf_comp_en U RW default = 'h1 -+// Bit 7 rg_m5_wf_sx_log5g_mxr_en U RW default = 'h0 -+// Bit 8 rg_m5_wf_sx_log5g_inv_en U RW default = 'h0 -+// Bit 9 rg_m5_wf_sx_log5g_div_en U RW default = 'h0 -+// Bit 10 rg_m5_wf_sx_log5g_iqdiv_en U RW default = 'h0 -+// Bit 11 rg_m5_wf_sx_log5g_rxlo_en U RW default = 'h0 -+// Bit 12 rg_m5_wf_sx_log5g_dpdlo_en U RW default = 'h0 -+// Bit 13 rg_m5_wf_sx_log5g_txlo_en U RW default = 'h0 -+// Bit 14 rg_m5_wf_sx_log2g_mxr_en U RW default = 'h1 -+// Bit 15 rg_m5_wf_sx_log2g_div_en U RW default = 'h1 -+// Bit 16 rg_m5_wf_sx_log2g_iqdiv_en U RW default = 'h1 -+// Bit 17 rg_m5_wf_sx_log2g_rxlo_en U RW default = 'h0 -+// Bit 18 rg_m5_wf_sx_log2g_dpdlo_en U RW default = 'h0 -+// Bit 19 rg_m5_wf_sx_log2g_txlo_en U RW default = 'h0 -+typedef union RG_SX_A47_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M5_WF_SX_VCO_EN : 1; -+ unsigned int RG_M5_WF_SX_VCO_ACAL_EN : 1; -+ unsigned int RG_M5_WF_SX_PFD_EN : 1; -+ unsigned int RG_M5_WF_SX_CP_EN : 1; -+ unsigned int RG_M5_WF_SX_VCO_LDO_EN : 1; -+ unsigned int RG_M5_WF_SX_CP_LDO_EN : 1; -+ unsigned int RG_M5_WF_SX_LPF_COMP_EN : 1; -+ unsigned int RG_M5_WF_SX_LOG5G_MXR_EN : 1; -+ unsigned int RG_M5_WF_SX_LOG5G_INV_EN : 1; -+ unsigned int RG_M5_WF_SX_LOG5G_DIV_EN : 1; -+ unsigned int RG_M5_WF_SX_LOG5G_IQDIV_EN : 1; -+ unsigned int RG_M5_WF_SX_LOG5G_RXLO_EN : 1; -+ unsigned int RG_M5_WF_SX_LOG5G_DPDLO_EN : 1; -+ unsigned int RG_M5_WF_SX_LOG5G_TXLO_EN : 1; -+ unsigned int RG_M5_WF_SX_LOG2G_MXR_EN : 1; -+ unsigned int RG_M5_WF_SX_LOG2G_DIV_EN : 1; -+ unsigned int RG_M5_WF_SX_LOG2G_IQDIV_EN : 1; -+ unsigned int RG_M5_WF_SX_LOG2G_RXLO_EN : 1; -+ unsigned int RG_M5_WF_SX_LOG2G_DPDLO_EN : 1; -+ unsigned int RG_M5_WF_SX_LOG2G_TXLO_EN : 1; -+ unsigned int rsvd_0 : 12; -+ } b; -+} RG_SX_A47_FIELD_T; -+ -+#define RG_SX_A48 (RF_D_SX_REG_BASE + 0xc0) -+// Bit 0 rg_m6_wf_sx_vco_en U RW default = 'h1 -+// Bit 1 rg_m6_wf_sx_vco_acal_en U RW default = 'h1 -+// Bit 2 rg_m6_wf_sx_pfd_en U RW default = 'h1 -+// Bit 3 rg_m6_wf_sx_cp_en U RW default = 'h1 -+// Bit 4 rg_m6_wf_sx_vco_ldo_en U RW default = 'h1 -+// Bit 5 rg_m6_wf_sx_cp_ldo_en U RW default = 'h1 -+// Bit 6 rg_m6_wf_sx_lpf_comp_en U RW default = 'h1 -+// Bit 7 rg_m6_wf_sx_log5g_mxr_en U RW default = 'h0 -+// Bit 8 rg_m6_wf_sx_log5g_inv_en U RW default = 'h0 -+// Bit 9 rg_m6_wf_sx_log5g_div_en U RW default = 'h0 -+// Bit 10 rg_m6_wf_sx_log5g_iqdiv_en U RW default = 'h0 -+// Bit 11 rg_m6_wf_sx_log5g_rxlo_en U RW default = 'h0 -+// Bit 12 rg_m6_wf_sx_log5g_dpdlo_en U RW default = 'h0 -+// Bit 13 rg_m6_wf_sx_log5g_txlo_en U RW default = 'h0 -+// Bit 14 rg_m6_wf_sx_log2g_mxr_en U RW default = 'h1 -+// Bit 15 rg_m6_wf_sx_log2g_div_en U RW default = 'h1 -+// Bit 16 rg_m6_wf_sx_log2g_iqdiv_en U RW default = 'h1 -+// Bit 17 rg_m6_wf_sx_log2g_rxlo_en U RW default = 'h0 -+// Bit 18 rg_m6_wf_sx_log2g_dpdlo_en U RW default = 'h0 -+// Bit 19 rg_m6_wf_sx_log2g_txlo_en U RW default = 'h1 -+typedef union RG_SX_A48_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M6_WF_SX_VCO_EN : 1; -+ unsigned int RG_M6_WF_SX_VCO_ACAL_EN : 1; -+ unsigned int RG_M6_WF_SX_PFD_EN : 1; -+ unsigned int RG_M6_WF_SX_CP_EN : 1; -+ unsigned int RG_M6_WF_SX_VCO_LDO_EN : 1; -+ unsigned int RG_M6_WF_SX_CP_LDO_EN : 1; -+ unsigned int RG_M6_WF_SX_LPF_COMP_EN : 1; -+ unsigned int RG_M6_WF_SX_LOG5G_MXR_EN : 1; -+ unsigned int RG_M6_WF_SX_LOG5G_INV_EN : 1; -+ unsigned int RG_M6_WF_SX_LOG5G_DIV_EN : 1; -+ unsigned int RG_M6_WF_SX_LOG5G_IQDIV_EN : 1; -+ unsigned int RG_M6_WF_SX_LOG5G_RXLO_EN : 1; -+ unsigned int RG_M6_WF_SX_LOG5G_DPDLO_EN : 1; -+ unsigned int RG_M6_WF_SX_LOG5G_TXLO_EN : 1; -+ unsigned int RG_M6_WF_SX_LOG2G_MXR_EN : 1; -+ unsigned int RG_M6_WF_SX_LOG2G_DIV_EN : 1; -+ unsigned int RG_M6_WF_SX_LOG2G_IQDIV_EN : 1; -+ unsigned int RG_M6_WF_SX_LOG2G_RXLO_EN : 1; -+ unsigned int RG_M6_WF_SX_LOG2G_DPDLO_EN : 1; -+ unsigned int RG_M6_WF_SX_LOG2G_TXLO_EN : 1; -+ unsigned int rsvd_0 : 12; -+ } b; -+} RG_SX_A48_FIELD_T; -+ -+#define RG_SX_A49 (RF_D_SX_REG_BASE + 0xc4) -+// Bit 0 rg_m7_wf_sx_vco_en U RW default = 'h1 -+// Bit 1 rg_m7_wf_sx_vco_acal_en U RW default = 'h1 -+// Bit 2 rg_m7_wf_sx_pfd_en U RW default = 'h1 -+// Bit 3 rg_m7_wf_sx_cp_en U RW default = 'h1 -+// Bit 4 rg_m7_wf_sx_vco_ldo_en U RW default = 'h1 -+// Bit 5 rg_m7_wf_sx_cp_ldo_en U RW default = 'h1 -+// Bit 6 rg_m7_wf_sx_lpf_comp_en U RW default = 'h1 -+// Bit 7 rg_m7_wf_sx_log5g_mxr_en U RW default = 'h0 -+// Bit 8 rg_m7_wf_sx_log5g_inv_en U RW default = 'h0 -+// Bit 9 rg_m7_wf_sx_log5g_div_en U RW default = 'h0 -+// Bit 10 rg_m7_wf_sx_log5g_iqdiv_en U RW default = 'h0 -+// Bit 11 rg_m7_wf_sx_log5g_rxlo_en U RW default = 'h0 -+// Bit 12 rg_m7_wf_sx_log5g_dpdlo_en U RW default = 'h0 -+// Bit 13 rg_m7_wf_sx_log5g_txlo_en U RW default = 'h0 -+// Bit 14 rg_m7_wf_sx_log2g_mxr_en U RW default = 'h1 -+// Bit 15 rg_m7_wf_sx_log2g_div_en U RW default = 'h1 -+// Bit 16 rg_m7_wf_sx_log2g_iqdiv_en U RW default = 'h1 -+// Bit 17 rg_m7_wf_sx_log2g_rxlo_en U RW default = 'h1 -+// Bit 18 rg_m7_wf_sx_log2g_dpdlo_en U RW default = 'h0 -+// Bit 19 rg_m7_wf_sx_log2g_txlo_en U RW default = 'h0 -+typedef union RG_SX_A49_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M7_WF_SX_VCO_EN : 1; -+ unsigned int RG_M7_WF_SX_VCO_ACAL_EN : 1; -+ unsigned int RG_M7_WF_SX_PFD_EN : 1; -+ unsigned int RG_M7_WF_SX_CP_EN : 1; -+ unsigned int RG_M7_WF_SX_VCO_LDO_EN : 1; -+ unsigned int RG_M7_WF_SX_CP_LDO_EN : 1; -+ unsigned int RG_M7_WF_SX_LPF_COMP_EN : 1; -+ unsigned int RG_M7_WF_SX_LOG5G_MXR_EN : 1; -+ unsigned int RG_M7_WF_SX_LOG5G_INV_EN : 1; -+ unsigned int RG_M7_WF_SX_LOG5G_DIV_EN : 1; -+ unsigned int RG_M7_WF_SX_LOG5G_IQDIV_EN : 1; -+ unsigned int RG_M7_WF_SX_LOG5G_RXLO_EN : 1; -+ unsigned int RG_M7_WF_SX_LOG5G_DPDLO_EN : 1; -+ unsigned int RG_M7_WF_SX_LOG5G_TXLO_EN : 1; -+ unsigned int RG_M7_WF_SX_LOG2G_MXR_EN : 1; -+ unsigned int RG_M7_WF_SX_LOG2G_DIV_EN : 1; -+ unsigned int RG_M7_WF_SX_LOG2G_IQDIV_EN : 1; -+ unsigned int RG_M7_WF_SX_LOG2G_RXLO_EN : 1; -+ unsigned int RG_M7_WF_SX_LOG2G_DPDLO_EN : 1; -+ unsigned int RG_M7_WF_SX_LOG2G_TXLO_EN : 1; -+ unsigned int rsvd_0 : 12; -+ } b; -+} RG_SX_A49_FIELD_T; -+ -+#define RG_SX_A50 (RF_D_SX_REG_BASE + 0xc8) -+// Bit 6 :0 ro_wf_sx_double_tune U RO default = 'h0 -+// Bit 8 ro_wf_sx_double_tune_ready U RO default = 'h0 -+typedef union RG_SX_A50_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RO_WF_SX_DOUBLE_TUNE : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int RO_WF_SX_DOUBLE_TUNE_READY : 1; -+ unsigned int rsvd_1 : 23; -+ } b; -+} RG_SX_A50_FIELD_T; -+ -+#endif -+ -diff --git a/drivers/net/wireless/w1/common/rf_d_top_reg.h b/drivers/net/wireless/w1/common/rf_d_top_reg.h -new file mode 100644 -index 000000000000..6448f506bab5 ---- /dev/null -+++ b/drivers/net/wireless/w1/common/rf_d_top_reg.h -@@ -0,0 +1,790 @@ -+#ifdef RF_D_TOP_REG -+#else -+#define RF_D_TOP_REG -+ -+ -+#define RF_D_TOP_REG_BASE (0x0) -+ -+#define RG_TOP_A0 (RF_D_TOP_REG_BASE + 0x0) -+// Bit 31 :0 rg_wf_rx_dig_rsv0 U RW default = 'hffff -+typedef union RG_TOP_A0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_DIG_RSV0 : 32; -+ } b; -+} RG_TOP_A0_FIELD_T; -+ -+#define RG_TOP_A1 (RF_D_TOP_REG_BASE + 0x4) -+// Bit 31 :0 rg_wf_rx_dig_rsv1 U RW default = 'hffff -+typedef union RG_TOP_A1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_RX_DIG_RSV1 : 32; -+ } b; -+} RG_TOP_A1_FIELD_T; -+ -+#define RG_TOP_A2 (RF_D_TOP_REG_BASE + 0x8) -+// Bit 2 :0 rg_wf_mode_man U RW default = 'h0 -+// Bit 4 rg_wf_mode_man_mode U RW default = 'h0 -+// Bit 7 :6 rg_wf_sleep_mode U RW default = 'h0 -+// Bit 9 :8 rg_wf5g_sx_mode U RW default = 'h1 -+// Bit 11 :10 rg_wf5g_tx_mode U RW default = 'h2 -+// Bit 13 :12 rg_wf5g_rx_mode U RW default = 'h3 -+// Bit 15 :14 rg_wf5g_dpd_mode U RW default = 'h0 -+// Bit 17 :16 rg_wf2g_sx_mode U RW default = 'h1 -+// Bit 19 :18 rg_wf2g_tx_mode U RW default = 'h2 -+// Bit 21 :20 rg_wf2g_rx_mode U RW default = 'h3 -+// Bit 24 rg_wf_rf_mode U RW default = 'h0 -+// Bit 26 rg_wf_agc_lock_man U RW default = 'h0 -+// Bit 28 rg_wf_agc_lock_man_mode U RW default = 'h0 -+// Bit 30 :29 rg_wf_trswitch_edge_mask U RW default = 'h0 -+typedef union RG_TOP_A2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_MODE_MAN : 3; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF_MODE_MAN_MODE : 1; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF_SLEEP_MODE : 2; -+ unsigned int RG_WF5G_SX_MODE : 2; -+ unsigned int RG_WF5G_TX_MODE : 2; -+ unsigned int RG_WF5G_RX_MODE : 2; -+ unsigned int RG_WF5G_DPD_MODE : 2; -+ unsigned int RG_WF2G_SX_MODE : 2; -+ unsigned int RG_WF2G_TX_MODE : 2; -+ unsigned int RG_WF2G_RX_MODE : 2; -+ unsigned int rsvd_2 : 2; -+ unsigned int RG_WF_RF_MODE : 1; -+ unsigned int rsvd_3 : 1; -+ unsigned int RG_WF_AGC_LOCK_MAN : 1; -+ unsigned int rsvd_4 : 1; -+ unsigned int RG_WF_AGC_LOCK_MAN_MODE : 1; -+ unsigned int RG_WF_TRSWITCH_EDGE_MASK : 2; -+ unsigned int rsvd_5 : 1; -+ } b; -+} RG_TOP_A2_FIELD_T; -+ -+#define RG_TOP_A3 (RF_D_TOP_REG_BASE + 0xc) -+// Bit 0 rg_wf_trx_hf_ldo_fc_sel U RW default = 'h0 -+// Bit 1 rg_wf_trx_hf_ldo_fc_en_man_mode U RW default = 'h0 -+// Bit 2 rg_wf_trx_hf_ldo_fc_en_man U RW default = 'h0 -+// Bit 7 :3 rg_wf_trx_hf_ldo_vsel U RW default = 'h10 -+// Bit 8 rg_wf_trx_hf_ldo_rc_ctrl U RW default = 'h1 -+// Bit 9 rg_wf_trx_lf_ldo_fc_sel U RW default = 'h0 -+// Bit 10 rg_wf_trx_lf_ldo_fc_en_man_mode U RW default = 'h0 -+// Bit 11 rg_wf_trx_lf_ldo_fc_en_man U RW default = 'h0 -+// Bit 16 :12 rg_wf_trx_lf_ldo_vsel U RW default = 'h10 -+// Bit 17 rg_wf_trx_lf_ldo_rc_ctrl U RW default = 'h1 -+// Bit 20 :18 rg_wf_top_dc_test_sel U RW default = 'h0 -+// Bit 23 :21 rg_wf_top_ac_test_sel U RW default = 'h0 -+// Bit 24 rg_wf_top_dc_test_en U RW default = 'h0 -+// Bit 25 rg_wf_top_ac_test_en U RW default = 'h0 -+// Bit 26 rg_wf_top_tx_test_en U RW default = 'h0 -+// Bit 27 rg_wf_top_rx_test_en U RW default = 'h0 -+// Bit 28 rg_wf_top_adc_test_en U RW default = 'h0 -+// Bit 29 rg_wf_top_rcal_test_en U RW default = 'h0 -+// Bit 30 rg_wf_top_xosc_test_en U RW default = 'h0 -+// Bit 31 rg_wf_top_bbpll_test_en U RW default = 'h0 -+typedef union RG_TOP_A3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_TRX_HF_LDO_FC_SEL : 1; -+ unsigned int RG_WF_TRX_HF_LDO_FC_EN_MAN_MODE : 1; -+ unsigned int RG_WF_TRX_HF_LDO_FC_EN_MAN : 1; -+ unsigned int RG_WF_TRX_HF_LDO_VSEL : 5; -+ unsigned int RG_WF_TRX_HF_LDO_RC_CTRL : 1; -+ unsigned int RG_WF_TRX_LF_LDO_FC_SEL : 1; -+ unsigned int RG_WF_TRX_LF_LDO_FC_EN_MAN_MODE : 1; -+ unsigned int RG_WF_TRX_LF_LDO_FC_EN_MAN : 1; -+ unsigned int RG_WF_TRX_LF_LDO_VSEL : 5; -+ unsigned int RG_WF_TRX_LF_LDO_RC_CTRL : 1; -+ unsigned int RG_WF_TOP_DC_TEST_SEL : 3; -+ unsigned int RG_WF_TOP_AC_TEST_SEL : 3; -+ unsigned int RG_WF_TOP_DC_TEST_EN : 1; -+ unsigned int RG_WF_TOP_AC_TEST_EN : 1; -+ unsigned int RG_WF_TOP_TX_TEST_EN : 1; -+ unsigned int RG_WF_TOP_RX_TEST_EN : 1; -+ unsigned int RG_WF_TOP_ADC_TEST_EN : 1; -+ unsigned int RG_WF_TOP_RCAL_TEST_EN : 1; -+ unsigned int RG_WF_TOP_XOSC_TEST_EN : 1; -+ unsigned int RG_WF_TOP_BBPLL_TEST_EN : 1; -+ } b; -+} RG_TOP_A3_FIELD_T; -+ -+#define RG_TOP_A4 (RF_D_TOP_REG_BASE + 0x10) -+// Bit 15 :0 rg_wf_top_reserved0 U RW default = 'h0 -+// Bit 31 :16 rg_wf_top_reserved1 U RW default = 'hffff -+typedef union RG_TOP_A4_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_TOP_RESERVED0 : 16; -+ unsigned int RG_WF_TOP_RESERVED1 : 16; -+ } b; -+} RG_TOP_A4_FIELD_T; -+ -+#define RG_TOP_A5 (RF_D_TOP_REG_BASE + 0x14) -+// Bit 0 rg_m0_wf_trx_hf_ldo_en U RW default = 'h0 -+// Bit 1 rg_m0_wf_trx_hf_ldo_tx1_en U RW default = 'h0 -+// Bit 2 rg_m0_wf_trx_hf_ldo_tx2_en U RW default = 'h0 -+// Bit 3 rg_m0_wf_trx_hf_ldo_rxb_en U RW default = 'h0 -+// Bit 4 rg_m0_wf_trx_hf_ldo_rx1_en U RW default = 'h0 -+// Bit 5 rg_m0_wf_trx_hf_ldo_rx2_en U RW default = 'h0 -+// Bit 6 rg_m0_wf_trx_hf_ldo_lo_en U RW default = 'h0 -+// Bit 7 rg_m0_wf_trx_lf_ldo_en U RW default = 'h0 -+// Bit 8 rg_m0_wf_trx_lf_ldo_tx_en U RW default = 'h0 -+// Bit 9 rg_m0_wf_trx_lf_ldo_rx_en U RW default = 'h0 -+typedef union RG_TOP_A5_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M0_WF_TRX_HF_LDO_EN : 1; -+ unsigned int RG_M0_WF_TRX_HF_LDO_TX1_EN : 1; -+ unsigned int RG_M0_WF_TRX_HF_LDO_TX2_EN : 1; -+ unsigned int RG_M0_WF_TRX_HF_LDO_RXB_EN : 1; -+ unsigned int RG_M0_WF_TRX_HF_LDO_RX1_EN : 1; -+ unsigned int RG_M0_WF_TRX_HF_LDO_RX2_EN : 1; -+ unsigned int RG_M0_WF_TRX_HF_LDO_LO_EN : 1; -+ unsigned int RG_M0_WF_TRX_LF_LDO_EN : 1; -+ unsigned int RG_M0_WF_TRX_LF_LDO_TX_EN : 1; -+ unsigned int RG_M0_WF_TRX_LF_LDO_RX_EN : 1; -+ unsigned int rsvd_0 : 22; -+ } b; -+} RG_TOP_A5_FIELD_T; -+ -+#define RG_TOP_A6 (RF_D_TOP_REG_BASE + 0x18) -+// Bit 0 rg_m1_wf_trx_hf_ldo_en U RW default = 'h1 -+// Bit 1 rg_m1_wf_trx_hf_ldo_tx1_en U RW default = 'h0 -+// Bit 2 rg_m1_wf_trx_hf_ldo_tx2_en U RW default = 'h0 -+// Bit 3 rg_m1_wf_trx_hf_ldo_rxb_en U RW default = 'h0 -+// Bit 4 rg_m1_wf_trx_hf_ldo_rx1_en U RW default = 'h0 -+// Bit 5 rg_m1_wf_trx_hf_ldo_rx2_en U RW default = 'h0 -+// Bit 6 rg_m1_wf_trx_hf_ldo_lo_en U RW default = 'h1 -+// Bit 7 rg_m1_wf_trx_lf_ldo_en U RW default = 'h0 -+// Bit 8 rg_m1_wf_trx_lf_ldo_tx_en U RW default = 'h0 -+// Bit 9 rg_m1_wf_trx_lf_ldo_rx_en U RW default = 'h0 -+typedef union RG_TOP_A6_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M1_WF_TRX_HF_LDO_EN : 1; -+ unsigned int RG_M1_WF_TRX_HF_LDO_TX1_EN : 1; -+ unsigned int RG_M1_WF_TRX_HF_LDO_TX2_EN : 1; -+ unsigned int RG_M1_WF_TRX_HF_LDO_RXB_EN : 1; -+ unsigned int RG_M1_WF_TRX_HF_LDO_RX1_EN : 1; -+ unsigned int RG_M1_WF_TRX_HF_LDO_RX2_EN : 1; -+ unsigned int RG_M1_WF_TRX_HF_LDO_LO_EN : 1; -+ unsigned int RG_M1_WF_TRX_LF_LDO_EN : 1; -+ unsigned int RG_M1_WF_TRX_LF_LDO_TX_EN : 1; -+ unsigned int RG_M1_WF_TRX_LF_LDO_RX_EN : 1; -+ unsigned int rsvd_0 : 22; -+ } b; -+} RG_TOP_A6_FIELD_T; -+ -+#define RG_TOP_A7 (RF_D_TOP_REG_BASE + 0x1c) -+// Bit 0 rg_m2_wf_trx_hf_ldo_en U RW default = 'h1 -+// Bit 1 rg_m2_wf_trx_hf_ldo_tx1_en U RW default = 'h1 -+// Bit 2 rg_m2_wf_trx_hf_ldo_tx2_en U RW default = 'h1 -+// Bit 3 rg_m2_wf_trx_hf_ldo_rxb_en U RW default = 'h0 -+// Bit 4 rg_m2_wf_trx_hf_ldo_rx1_en U RW default = 'h0 -+// Bit 5 rg_m2_wf_trx_hf_ldo_rx2_en U RW default = 'h0 -+// Bit 6 rg_m2_wf_trx_hf_ldo_lo_en U RW default = 'h1 -+// Bit 7 rg_m2_wf_trx_lf_ldo_en U RW default = 'h1 -+// Bit 8 rg_m2_wf_trx_lf_ldo_tx_en U RW default = 'h1 -+// Bit 9 rg_m2_wf_trx_lf_ldo_rx_en U RW default = 'h0 -+typedef union RG_TOP_A7_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M2_WF_TRX_HF_LDO_EN : 1; -+ unsigned int RG_M2_WF_TRX_HF_LDO_TX1_EN : 1; -+ unsigned int RG_M2_WF_TRX_HF_LDO_TX2_EN : 1; -+ unsigned int RG_M2_WF_TRX_HF_LDO_RXB_EN : 1; -+ unsigned int RG_M2_WF_TRX_HF_LDO_RX1_EN : 1; -+ unsigned int RG_M2_WF_TRX_HF_LDO_RX2_EN : 1; -+ unsigned int RG_M2_WF_TRX_HF_LDO_LO_EN : 1; -+ unsigned int RG_M2_WF_TRX_LF_LDO_EN : 1; -+ unsigned int RG_M2_WF_TRX_LF_LDO_TX_EN : 1; -+ unsigned int RG_M2_WF_TRX_LF_LDO_RX_EN : 1; -+ unsigned int rsvd_0 : 22; -+ } b; -+} RG_TOP_A7_FIELD_T; -+ -+#define RG_TOP_A8 (RF_D_TOP_REG_BASE + 0x20) -+// Bit 0 rg_m3_wf_trx_hf_ldo_en U RW default = 'h1 -+// Bit 1 rg_m3_wf_trx_hf_ldo_tx1_en U RW default = 'h0 -+// Bit 2 rg_m3_wf_trx_hf_ldo_tx2_en U RW default = 'h0 -+// Bit 3 rg_m3_wf_trx_hf_ldo_rxb_en U RW default = 'h1 -+// Bit 4 rg_m3_wf_trx_hf_ldo_rx1_en U RW default = 'h1 -+// Bit 5 rg_m3_wf_trx_hf_ldo_rx2_en U RW default = 'h1 -+// Bit 6 rg_m3_wf_trx_hf_ldo_lo_en U RW default = 'h1 -+// Bit 7 rg_m3_wf_trx_lf_ldo_en U RW default = 'h1 -+// Bit 8 rg_m3_wf_trx_lf_ldo_tx_en U RW default = 'h0 -+// Bit 9 rg_m3_wf_trx_lf_ldo_rx_en U RW default = 'h1 -+typedef union RG_TOP_A8_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M3_WF_TRX_HF_LDO_EN : 1; -+ unsigned int RG_M3_WF_TRX_HF_LDO_TX1_EN : 1; -+ unsigned int RG_M3_WF_TRX_HF_LDO_TX2_EN : 1; -+ unsigned int RG_M3_WF_TRX_HF_LDO_RXB_EN : 1; -+ unsigned int RG_M3_WF_TRX_HF_LDO_RX1_EN : 1; -+ unsigned int RG_M3_WF_TRX_HF_LDO_RX2_EN : 1; -+ unsigned int RG_M3_WF_TRX_HF_LDO_LO_EN : 1; -+ unsigned int RG_M3_WF_TRX_LF_LDO_EN : 1; -+ unsigned int RG_M3_WF_TRX_LF_LDO_TX_EN : 1; -+ unsigned int RG_M3_WF_TRX_LF_LDO_RX_EN : 1; -+ unsigned int rsvd_0 : 22; -+ } b; -+} RG_TOP_A8_FIELD_T; -+ -+#define RG_TOP_A9 (RF_D_TOP_REG_BASE + 0x40) -+// Bit 0 rg_wf_adda_ldo_lf_rc_ctrl U RW default = 'h0 -+// Bit 1 rg_wf_adda_ldo_rc_modelsel U RW default = 'h0 -+// Bit 6 :2 rg_wf_adda_ldo_vref_adj U RW default = 'h0 -+// Bit 7 rg_wf_adda_ldo_load_en U RW default = 'h0 -+// Bit 23 :8 rg_wf_adda_rsv U RW default = 'h0 -+// Bit 24 rg_wf_dac_bit9_inv U RW default = 'h0 -+// Bit 30 :28 rg_wf_dac_clk_delay_i U RW default = 'h1 -+typedef union RG_TOP_A9_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_wf_adda_ldo_lf_rc_ctrl : 1; -+ unsigned int rg_wf_adda_ldo_rc_modelsel : 1; -+ unsigned int rg_wf_adda_ldo_vref_adj : 5; -+ unsigned int rg_wf_adda_ldo_load_en : 1; -+ unsigned int rg_wf_adda_rsv : 16; -+ unsigned int rg_wf_dac_bit9_inv : 1; -+ unsigned int rsvd_0 : 3; -+ unsigned int rg_wf_dac_clk_delay_i : 3; -+ unsigned int rsvd_1 : 1; -+ } b; -+} RG_TOP_A9_FIELD_T; -+ -+#define RG_TOP_A11 (RF_D_TOP_REG_BASE + 0x48) -+// Bit 2 :0 rg_wf_dac_clk_delay_q U RW default = 'h1 -+// Bit 6 :3 rg_wf_dac_dcoc_i U RW default = 'h0 -+// Bit 10 :7 rg_wf_dac_dcoc_q U RW default = 'h0 -+// Bit 11 rg_wf_dac_dem_en U RW default = 'h0 -+// Bit 12 rg_wf_dac_driver_adj U RW default = 'h0 -+// Bit 16 :13 rg_wf_dac_op_drive U RW default = 'hf -+// Bit 18 :17 rg_wf_dac_op_ibias U RW default = 'h3 -+// Bit 22 :19 rg_wf_dac_ovcm U RW default = 'h0 -+// Bit 23 rg_wf_dac_fs_sel U RW default = 'h1 -+// Bit 28 :24 rg_wf_dac_rc_adj_i U RW default = 'h8 -+typedef union RG_TOP_A11_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_wf_dac_clk_delay_q : 3; -+ unsigned int rg_wf_dac_dcoc_i : 4; -+ unsigned int rg_wf_dac_dcoc_q : 4; -+ unsigned int rg_wf_dac_dem_en : 1; -+ unsigned int rg_wf_dac_driver_adj : 1; -+ unsigned int rg_wf_dac_op_drive : 4; -+ unsigned int rg_wf_dac_op_ibias : 2; -+ unsigned int rg_wf_dac_ovcm : 4; -+ unsigned int rg_wf_dac_fs_sel : 1; -+ unsigned int rg_wf_dac_rc_adj_i : 5; -+ unsigned int rsvd_0 : 3; -+ } b; -+} RG_TOP_A11_FIELD_T; -+ -+#define RG_TOP_A12 (RF_D_TOP_REG_BASE + 0x4c) -+// Bit 4 :0 rg_wf_dac_rc_adj_q U RW default = 'h8 -+// Bit 12 :5 rg_wf_dac_rsv U RW default = 'h86 -+// Bit 15 :13 rg_wf_dac_vimc_i U RW default = 'h0 -+// Bit 18 :16 rg_wf_dac_vimc_q U RW default = 'h0 -+// Bit 20 :19 rg_wf_dac_pole_sel U RW default = 'h0 -+// Bit 21 rg_wf_dac_tia_mux_sel_i U RW default = 'h0 -+// Bit 22 rg_wf_dac_tia_mux_sel_q U RW default = 'h0 -+// Bit 24 :23 rg_wf_radc_bs_sel U RW default = 'h1 -+// Bit 25 rg_wf_radc_c_adj U RW default = 'h0 -+// Bit 28 :26 rg_wf_radc_clk_delay_adj U RW default = 'h1 -+// Bit 29 rg_wf_radc_ref_adj U RW default = 'h0 -+typedef union RG_TOP_A12_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_wf_dac_rc_adj_q : 5; -+ unsigned int rg_wf_dac_rsv : 8; -+ unsigned int rg_wf_dac_vimc_i : 3; -+ unsigned int rg_wf_dac_vimc_q : 3; -+ unsigned int rg_wf_dac_pole_sel : 2; -+ unsigned int rg_wf_dac_tia_mux_sel_i : 1; -+ unsigned int rg_wf_dac_tia_mux_sel_q : 1; -+ unsigned int rg_wf_radc_bs_sel : 2; -+ unsigned int rg_wf_radc_c_adj : 1; -+ unsigned int rg_wf_radc_clk_delay_adj : 3; -+ unsigned int rg_wf_radc_ref_adj : 1; -+ unsigned int rsvd_0 : 2; -+ } b; -+} RG_TOP_A12_FIELD_T; -+ -+#define RG_TOP_A13 (RF_D_TOP_REG_BASE + 0x50) -+// Bit 7 :0 rg_wf_radc_resv U RW default = 'h3 -+// Bit 8 rg_wf_radc_skip_sel U RW default = 'h0 -+// Bit 10 :9 rg_wf_wadc_bs_sel U RW default = 'h2 -+// Bit 11 rg_wf_wadc_ch1_latch U RW default = 'h0 -+// Bit 16 :12 rg_wf_wadc_ch1_os_corr_i_man U RW default = 'h0 -+// Bit 21 :17 rg_wf_wadc_ch1_os_corr_q_man U RW default = 'h0 -+// Bit 22 rg_wf_wadc_ch2_latch U RW default = 'h0 -+// Bit 27 :23 rg_wf_wadc_ch2_os_corr_i_man U RW default = 'h0 -+// Bit 28 rg_wf_wadc_ch_os_corr_man_sel U RW default = 'h1 -+// Bit 29 rg_wf_wadc_force_ch_man_sel U RW default = 'h1 -+typedef union RG_TOP_A13_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_wf_radc_resv : 8; -+ unsigned int rg_wf_radc_skip_sel : 1; -+ unsigned int rg_wf_wadc_bs_sel : 2; -+ unsigned int rg_wf_wadc_ch1_latch : 1; -+ unsigned int rg_wf_wadc_ch1_os_corr_i_man : 5; -+ unsigned int rg_wf_wadc_ch1_os_corr_q_man : 5; -+ unsigned int rg_wf_wadc_ch2_latch : 1; -+ unsigned int rg_wf_wadc_ch2_os_corr_i_man : 5; -+ unsigned int rg_wf_wadc_ch_os_corr_man_sel : 1; -+ unsigned int rg_wf_wadc_force_ch_man_sel : 1; -+ unsigned int rsvd_0 : 2; -+ } b; -+} RG_TOP_A13_FIELD_T; -+ -+#define RG_TOP_A14 (RF_D_TOP_REG_BASE + 0x54) -+// Bit 4 :0 rg_wf_wadc_ch2_os_corr_q_man U RW default = 'h0 -+// Bit 5 rg_wf_wadc_clk_phase U RW default = 'h0 -+// Bit 7 :6 rg_wf_wadc_delay_adj U RW default = 'h0 -+// Bit 8 rg_wf_wadc_div2 U RW default = 'h1 -+// Bit 13 :9 rg_wf_wadc_divn U RW default = 'h0 -+// Bit 14 rg_wf_wadc_fs_sel U RW default = 'h0 -+// Bit 15 rg_wf_wadc_force_ch1_man U RW default = 'h1 -+// Bit 16 rg_wf_wadc_force_ch2_man U RW default = 'h0 -+// Bit 17 rg_wf_wadc_oscorr_en U RW default = 'h0 -+// Bit 18 rg_wf_wadc_clkout_phase U RW default = 'h0 -+// Bit 19 rg_wf_wadc_skip_sel U RW default = 'h0 -+// Bit 21 :20 rg_wf_wadc_waittime U RW default = 'h0 -+// Bit 23 :22 rg_wf_wadc_calctime U RW default = 'h0 -+// Bit 24 rg_wf_adda_ldo_fc U RW default = 'h0 -+typedef union RG_TOP_A14_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_wf_wadc_ch2_os_corr_q_man : 5; -+ unsigned int rg_wf_wadc_clk_phase : 1; -+ unsigned int rg_wf_wadc_delay_adj : 2; -+ unsigned int rg_wf_wadc_div2 : 1; -+ unsigned int rg_wf_wadc_divn : 5; -+ unsigned int rg_wf_wadc_fs_sel : 1; -+ unsigned int rg_wf_wadc_force_ch1_man : 1; -+ unsigned int rg_wf_wadc_force_ch2_man : 1; -+ unsigned int rg_wf_wadc_oscorr_en : 1; -+ unsigned int rg_wf_wadc_clkout_phase : 1; -+ unsigned int rg_wf_wadc_skip_sel : 1; -+ unsigned int rg_wf_wadc_waittime : 2; -+ unsigned int rg_wf_wadc_calctime : 2; -+ unsigned int rg_wf_adda_ldo_fc : 1; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_TOP_A14_FIELD_T; -+ -+#define RG_TOP_A15 (RF_D_TOP_REG_BASE + 0x58) -+// Bit 0 rg_wf_adda_man_mode U RW default = 'h1 -+// Bit 6 :4 rg_wf_dac_ampctrl_man U RW default = 'h4 -+// Bit 12 rg_wf_tx_tia_ibias_en_h U RW default = 'h1 -+// Bit 18 :16 rg_wf_tx_ibias_pata U RW default = 'h0 -+// Bit 22 :20 rg_wf_tx_ibias_zt U RW default = 'h0 -+typedef union RG_TOP_A15_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_wf_adda_man_mode : 1; -+ unsigned int rsvd_0 : 3; -+ unsigned int rg_wf_dac_ampctrl_man : 3; -+ unsigned int rsvd_1 : 5; -+ unsigned int rg_wf_tx_tia_ibias_en_h : 1; -+ unsigned int rsvd_2 : 3; -+ unsigned int rg_wf_tx_ibias_pata : 3; -+ unsigned int rsvd_3 : 1; -+ unsigned int rg_wf_tx_ibias_zt : 3; -+ unsigned int rsvd_4 : 9; -+ } b; -+} RG_TOP_A15_FIELD_T; -+ -+#define RG_TOP_A16 (RF_D_TOP_REG_BASE + 0x5c) -+// Bit 4 :0 ro_wf_wadc_ch1_os_corr_i U RO default = 'h0 -+// Bit 9 :5 ro_wf_wadc_ch1_os_corr_q U RO default = 'h0 -+// Bit 14 :10 ro_wf_wadc_ch2_os_corr_i U RO default = 'h0 -+// Bit 19 :15 ro_wf_wadc_ch2_os_corr_q U RO default = 'h0 -+typedef union RG_TOP_A16_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_wf_wadc_ch1_os_corr_i : 5; -+ unsigned int ro_wf_wadc_ch1_os_corr_q : 5; -+ unsigned int ro_wf_wadc_ch2_os_corr_i : 5; -+ unsigned int ro_wf_wadc_ch2_os_corr_q : 5; -+ unsigned int rsvd_0 : 12; -+ } b; -+} RG_TOP_A16_FIELD_T; -+ -+#define RG_TOP_A17 (RF_D_TOP_REG_BASE + 0x60) -+// Bit 0 rg_m0_wf_adda_ldo_en U RW default = 'h0 -+// Bit 1 rg_m0_wf_dac_enable U RW default = 'h0 -+// Bit 2 rg_m0_wf_radc_en U RW default = 'h0 -+// Bit 3 rg_m0_wf_wadc_enable_i U RW default = 'h0 -+// Bit 4 rg_m0_wf_wadc_enable_q U RW default = 'h0 -+typedef union RG_TOP_A17_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_m0_wf_adda_ldo_en : 1; -+ unsigned int rg_m0_wf_dac_enable : 1; -+ unsigned int rg_m0_wf_radc_en : 1; -+ unsigned int rg_m0_wf_wadc_enable_i : 1; -+ unsigned int rg_m0_wf_wadc_enable_q : 1; -+ unsigned int rsvd_0 : 27; -+ } b; -+} RG_TOP_A17_FIELD_T; -+ -+#define RG_TOP_A18 (RF_D_TOP_REG_BASE + 0x64) -+// Bit 0 rg_m1_wf_adda_ldo_en U RW default = 'h0 -+// Bit 1 rg_m1_wf_dac_enable U RW default = 'h0 -+// Bit 2 rg_m1_wf_radc_en U RW default = 'h0 -+// Bit 3 rg_m1_wf_wadc_enable_i U RW default = 'h0 -+// Bit 4 rg_m1_wf_wadc_enable_q U RW default = 'h0 -+typedef union RG_TOP_A18_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_m1_wf_adda_ldo_en : 1; -+ unsigned int rg_m1_wf_dac_enable : 1; -+ unsigned int rg_m1_wf_radc_en : 1; -+ unsigned int rg_m1_wf_wadc_enable_i : 1; -+ unsigned int rg_m1_wf_wadc_enable_q : 1; -+ unsigned int rsvd_0 : 27; -+ } b; -+} RG_TOP_A18_FIELD_T; -+ -+#define RG_TOP_A19 (RF_D_TOP_REG_BASE + 0x68) -+// Bit 0 rg_m2_wf_adda_ldo_en U RW default = 'h1 -+// Bit 1 rg_m2_wf_dac_enable U RW default = 'h1 -+// Bit 2 rg_m2_wf_radc_en U RW default = 'h0 -+// Bit 3 rg_m2_wf_wadc_enable_i U RW default = 'h0 -+// Bit 4 rg_m2_wf_wadc_enable_q U RW default = 'h0 -+typedef union RG_TOP_A19_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_m2_wf_adda_ldo_en : 1; -+ unsigned int rg_m2_wf_dac_enable : 1; -+ unsigned int rg_m2_wf_radc_en : 1; -+ unsigned int rg_m2_wf_wadc_enable_i : 1; -+ unsigned int rg_m2_wf_wadc_enable_q : 1; -+ unsigned int rsvd_0 : 27; -+ } b; -+} RG_TOP_A19_FIELD_T; -+ -+#define RG_TOP_A20 (RF_D_TOP_REG_BASE + 0x6c) -+// Bit 0 rg_m3_wf_adda_ldo_en U RW default = 'h1 -+// Bit 1 rg_m3_wf_dac_enable U RW default = 'h0 -+// Bit 2 rg_m3_wf_radc_en U RW default = 'h1 -+// Bit 3 rg_m3_wf_wadc_enable_i U RW default = 'h1 -+// Bit 4 rg_m3_wf_wadc_enable_q U RW default = 'h1 -+typedef union RG_TOP_A20_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_m3_wf_adda_ldo_en : 1; -+ unsigned int rg_m3_wf_dac_enable : 1; -+ unsigned int rg_m3_wf_radc_en : 1; -+ unsigned int rg_m3_wf_wadc_enable_i : 1; -+ unsigned int rg_m3_wf_wadc_enable_q : 1; -+ unsigned int rsvd_0 : 27; -+ } b; -+} RG_TOP_A20_FIELD_T; -+ -+#define RG_TOP_A21 (RF_D_TOP_REG_BASE + 0x70) -+// Bit 0 rg_m4_wf_adda_ldo_en U RW default = 'h1 -+// Bit 1 rg_m4_wf_dac_enable U RW default = 'h1 -+// Bit 2 rg_m4_wf_radc_en U RW default = 'h0 -+// Bit 3 rg_m4_wf_wadc_enable_i U RW default = 'h1 -+// Bit 4 rg_m4_wf_wadc_enable_q U RW default = 'h1 -+typedef union RG_TOP_A21_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_m4_wf_adda_ldo_en : 1; -+ unsigned int rg_m4_wf_dac_enable : 1; -+ unsigned int rg_m4_wf_radc_en : 1; -+ unsigned int rg_m4_wf_wadc_enable_i : 1; -+ unsigned int rg_m4_wf_wadc_enable_q : 1; -+ unsigned int rsvd_0 : 27; -+ } b; -+} RG_TOP_A21_FIELD_T; -+ -+#define RG_TOP_A22 (RF_D_TOP_REG_BASE + 0x74) -+// Bit 0 rg_m5_wf_adda_ldo_en U RW default = 'h0 -+// Bit 1 rg_m5_wf_dac_enable U RW default = 'h0 -+// Bit 2 rg_m5_wf_radc_en U RW default = 'h0 -+// Bit 3 rg_m5_wf_wadc_enable_i U RW default = 'h0 -+// Bit 4 rg_m5_wf_wadc_enable_q U RW default = 'h0 -+typedef union RG_TOP_A22_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_m5_wf_adda_ldo_en : 1; -+ unsigned int rg_m5_wf_dac_enable : 1; -+ unsigned int rg_m5_wf_radc_en : 1; -+ unsigned int rg_m5_wf_wadc_enable_i : 1; -+ unsigned int rg_m5_wf_wadc_enable_q : 1; -+ unsigned int rsvd_0 : 27; -+ } b; -+} RG_TOP_A22_FIELD_T; -+ -+#define RG_TOP_A23 (RF_D_TOP_REG_BASE + 0x78) -+// Bit 0 rg_m6_wf_adda_ldo_en U RW default = 'h1 -+// Bit 1 rg_m6_wf_dac_enable U RW default = 'h1 -+// Bit 2 rg_m6_wf_radc_en U RW default = 'h0 -+// Bit 3 rg_m6_wf_wadc_enable_i U RW default = 'h0 -+// Bit 4 rg_m6_wf_wadc_enable_q U RW default = 'h0 -+typedef union RG_TOP_A23_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_m6_wf_adda_ldo_en : 1; -+ unsigned int rg_m6_wf_dac_enable : 1; -+ unsigned int rg_m6_wf_radc_en : 1; -+ unsigned int rg_m6_wf_wadc_enable_i : 1; -+ unsigned int rg_m6_wf_wadc_enable_q : 1; -+ unsigned int rsvd_0 : 27; -+ } b; -+} RG_TOP_A23_FIELD_T; -+ -+#define RG_TOP_A24 (RF_D_TOP_REG_BASE + 0x7c) -+// Bit 0 rg_m7_wf_adda_ldo_en U RW default = 'h1 -+// Bit 1 rg_m7_wf_dac_enable U RW default = 'h0 -+// Bit 2 rg_m7_wf_radc_en U RW default = 'h1 -+// Bit 3 rg_m7_wf_wadc_enable_i U RW default = 'h1 -+// Bit 4 rg_m7_wf_wadc_enable_q U RW default = 'h1 -+typedef union RG_TOP_A24_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rg_m7_wf_adda_ldo_en : 1; -+ unsigned int rg_m7_wf_dac_enable : 1; -+ unsigned int rg_m7_wf_radc_en : 1; -+ unsigned int rg_m7_wf_wadc_enable_i : 1; -+ unsigned int rg_m7_wf_wadc_enable_q : 1; -+ unsigned int rsvd_0 : 27; -+ } b; -+} RG_TOP_A24_FIELD_T; -+ -+#define RG_TOP_A27 (RF_D_TOP_REG_BASE + 0x88) -+// Bit 0 rg_m4_wf_trx_hf_ldo_en U RW default = 'h1 -+// Bit 1 rg_m4_wf_trx_hf_ldo_tx1_en U RW default = 'h1 -+// Bit 2 rg_m4_wf_trx_hf_ldo_tx2_en U RW default = 'h1 -+// Bit 3 rg_m4_wf_trx_hf_ldo_rxb_en U RW default = 'h1 -+// Bit 4 rg_m4_wf_trx_hf_ldo_rx1_en U RW default = 'h1 -+// Bit 5 rg_m4_wf_trx_hf_ldo_rx2_en U RW default = 'h1 -+// Bit 6 rg_m4_wf_trx_hf_ldo_lo_en U RW default = 'h1 -+// Bit 7 rg_m4_wf_trx_lf_ldo_en U RW default = 'h1 -+// Bit 8 rg_m4_wf_trx_lf_ldo_tx_en U RW default = 'h1 -+// Bit 9 rg_m4_wf_trx_lf_ldo_rx_en U RW default = 'h1 -+typedef union RG_TOP_A27_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M4_WF_TRX_HF_LDO_EN : 1; -+ unsigned int RG_M4_WF_TRX_HF_LDO_TX1_EN : 1; -+ unsigned int RG_M4_WF_TRX_HF_LDO_TX2_EN : 1; -+ unsigned int RG_M4_WF_TRX_HF_LDO_RXB_EN : 1; -+ unsigned int RG_M4_WF_TRX_HF_LDO_RX1_EN : 1; -+ unsigned int RG_M4_WF_TRX_HF_LDO_RX2_EN : 1; -+ unsigned int RG_M4_WF_TRX_HF_LDO_LO_EN : 1; -+ unsigned int RG_M4_WF_TRX_LF_LDO_EN : 1; -+ unsigned int RG_M4_WF_TRX_LF_LDO_TX_EN : 1; -+ unsigned int RG_M4_WF_TRX_LF_LDO_RX_EN : 1; -+ unsigned int rsvd_0 : 22; -+ } b; -+} RG_TOP_A27_FIELD_T; -+ -+#define RG_TOP_A28 (RF_D_TOP_REG_BASE + 0x8c) -+// Bit 0 rg_m5_wf_trx_hf_ldo_en U RW default = 'h1 -+// Bit 1 rg_m5_wf_trx_hf_ldo_tx1_en U RW default = 'h0 -+// Bit 2 rg_m5_wf_trx_hf_ldo_tx2_en U RW default = 'h0 -+// Bit 3 rg_m5_wf_trx_hf_ldo_rxb_en U RW default = 'h0 -+// Bit 4 rg_m5_wf_trx_hf_ldo_rx1_en U RW default = 'h0 -+// Bit 5 rg_m5_wf_trx_hf_ldo_rx2_en U RW default = 'h0 -+// Bit 6 rg_m5_wf_trx_hf_ldo_lo_en U RW default = 'h1 -+// Bit 7 rg_m5_wf_trx_lf_ldo_en U RW default = 'h0 -+// Bit 8 rg_m5_wf_trx_lf_ldo_tx_en U RW default = 'h0 -+// Bit 9 rg_m5_wf_trx_lf_ldo_rx_en U RW default = 'h0 -+typedef union RG_TOP_A28_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M5_WF_TRX_HF_LDO_EN : 1; -+ unsigned int RG_M5_WF_TRX_HF_LDO_TX1_EN : 1; -+ unsigned int RG_M5_WF_TRX_HF_LDO_TX2_EN : 1; -+ unsigned int RG_M5_WF_TRX_HF_LDO_RXB_EN : 1; -+ unsigned int RG_M5_WF_TRX_HF_LDO_RX1_EN : 1; -+ unsigned int RG_M5_WF_TRX_HF_LDO_RX2_EN : 1; -+ unsigned int RG_M5_WF_TRX_HF_LDO_LO_EN : 1; -+ unsigned int RG_M5_WF_TRX_LF_LDO_EN : 1; -+ unsigned int RG_M5_WF_TRX_LF_LDO_TX_EN : 1; -+ unsigned int RG_M5_WF_TRX_LF_LDO_RX_EN : 1; -+ unsigned int rsvd_0 : 22; -+ } b; -+} RG_TOP_A28_FIELD_T; -+ -+#define RG_TOP_A29 (RF_D_TOP_REG_BASE + 0x90) -+// Bit 0 rg_m6_wf_trx_hf_ldo_en U RW default = 'h1 -+// Bit 1 rg_m6_wf_trx_hf_ldo_tx1_en U RW default = 'h1 -+// Bit 2 rg_m6_wf_trx_hf_ldo_tx2_en U RW default = 'h1 -+// Bit 3 rg_m6_wf_trx_hf_ldo_rxb_en U RW default = 'h0 -+// Bit 4 rg_m6_wf_trx_hf_ldo_rx1_en U RW default = 'h0 -+// Bit 5 rg_m6_wf_trx_hf_ldo_rx2_en U RW default = 'h0 -+// Bit 6 rg_m6_wf_trx_hf_ldo_lo_en U RW default = 'h1 -+// Bit 7 rg_m6_wf_trx_lf_ldo_en U RW default = 'h1 -+// Bit 8 rg_m6_wf_trx_lf_ldo_tx_en U RW default = 'h1 -+// Bit 9 rg_m6_wf_trx_lf_ldo_rx_en U RW default = 'h0 -+typedef union RG_TOP_A29_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M6_WF_TRX_HF_LDO_EN : 1; -+ unsigned int RG_M6_WF_TRX_HF_LDO_TX1_EN : 1; -+ unsigned int RG_M6_WF_TRX_HF_LDO_TX2_EN : 1; -+ unsigned int RG_M6_WF_TRX_HF_LDO_RXB_EN : 1; -+ unsigned int RG_M6_WF_TRX_HF_LDO_RX1_EN : 1; -+ unsigned int RG_M6_WF_TRX_HF_LDO_RX2_EN : 1; -+ unsigned int RG_M6_WF_TRX_HF_LDO_LO_EN : 1; -+ unsigned int RG_M6_WF_TRX_LF_LDO_EN : 1; -+ unsigned int RG_M6_WF_TRX_LF_LDO_TX_EN : 1; -+ unsigned int RG_M6_WF_TRX_LF_LDO_RX_EN : 1; -+ unsigned int rsvd_0 : 22; -+ } b; -+} RG_TOP_A29_FIELD_T; -+ -+#define RG_TOP_A30 (RF_D_TOP_REG_BASE + 0x94) -+// Bit 0 rg_m7_wf_trx_hf_ldo_en U RW default = 'h1 -+// Bit 1 rg_m7_wf_trx_hf_ldo_tx1_en U RW default = 'h0 -+// Bit 2 rg_m7_wf_trx_hf_ldo_tx2_en U RW default = 'h0 -+// Bit 3 rg_m7_wf_trx_hf_ldo_rxb_en U RW default = 'h1 -+// Bit 4 rg_m7_wf_trx_hf_ldo_rx1_en U RW default = 'h1 -+// Bit 5 rg_m7_wf_trx_hf_ldo_rx2_en U RW default = 'h1 -+// Bit 6 rg_m7_wf_trx_hf_ldo_lo_en U RW default = 'h1 -+// Bit 7 rg_m7_wf_trx_lf_ldo_en U RW default = 'h1 -+// Bit 8 rg_m7_wf_trx_lf_ldo_tx_en U RW default = 'h0 -+// Bit 9 rg_m7_wf_trx_lf_ldo_rx_en U RW default = 'h1 -+typedef union RG_TOP_A30_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M7_WF_TRX_HF_LDO_EN : 1; -+ unsigned int RG_M7_WF_TRX_HF_LDO_TX1_EN : 1; -+ unsigned int RG_M7_WF_TRX_HF_LDO_TX2_EN : 1; -+ unsigned int RG_M7_WF_TRX_HF_LDO_RXB_EN : 1; -+ unsigned int RG_M7_WF_TRX_HF_LDO_RX1_EN : 1; -+ unsigned int RG_M7_WF_TRX_HF_LDO_RX2_EN : 1; -+ unsigned int RG_M7_WF_TRX_HF_LDO_LO_EN : 1; -+ unsigned int RG_M7_WF_TRX_LF_LDO_EN : 1; -+ unsigned int RG_M7_WF_TRX_LF_LDO_TX_EN : 1; -+ unsigned int RG_M7_WF_TRX_LF_LDO_RX_EN : 1; -+ unsigned int rsvd_0 : 22; -+ } b; -+} RG_TOP_A30_FIELD_T; -+ -+#define RG_TOP_A31 (RF_D_TOP_REG_BASE + 0x98) -+// Bit 31 :0 rg_wf_ad_inv U RW default = 'h0 -+typedef union RG_TOP_A31_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_AD_INV : 32; -+ } b; -+} RG_TOP_A31_FIELD_T; -+ -+#define RG_TOP_A32 (RF_D_TOP_REG_BASE + 0x9c) -+// Bit 23 :0 ro_wf_top_ad_monitor U RO default = 'h0 -+typedef union RG_TOP_A32_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RO_WF_TOP_AD_MONITOR : 24; -+ unsigned int rsvd_0 : 8; -+ } b; -+} RG_TOP_A32_FIELD_T; -+ -+#define RG_TOP_A33 (RF_D_TOP_REG_BASE + 0xa0) -+// Bit 1 :0 rg_wf_trx_ldo_fc_cnt U RW default = 'h0 -+typedef union RG_TOP_A33_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_TRX_LDO_FC_CNT : 2; -+ unsigned int rsvd_0 : 30; -+ } b; -+} RG_TOP_A33_FIELD_T; -+ -+#define RG_TOP_A34 (RF_D_TOP_REG_BASE + 0xa4) -+// Bit 1 :0 ro_hw_wf_trx_mode U RO default = 'h0 -+// Bit 11 :4 ro_hw_wf_rx_gain U RO default = 'h0 -+// Bit 13 :12 ro_hw_wf_bw U RO default = 'h0 -+// Bit 23 :16 ro_hw_wf_tx_gain U RO default = 'h0 -+// Bit 24 ro_hw_wf_agc_lock U RO default = 'h0 -+typedef union RG_TOP_A34_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RO_HW_WF_TRX_MODE : 2; -+ unsigned int rsvd_0 : 2; -+ unsigned int RO_HW_WF_RX_GAIN : 8; -+ unsigned int RO_HW_WF_BW : 2; -+ unsigned int rsvd_1 : 2; -+ unsigned int RO_HW_WF_TX_GAIN : 8; -+ unsigned int RO_HW_WF_AGC_LOCK : 1; -+ unsigned int rsvd_2 : 7; -+ } b; -+} RG_TOP_A34_FIELD_T; -+ -+#endif -+ -diff --git a/drivers/net/wireless/w1/common/rf_d_tx_reg.h b/drivers/net/wireless/w1/common/rf_d_tx_reg.h -new file mode 100644 -index 000000000000..4392b1f1e92c ---- /dev/null -+++ b/drivers/net/wireless/w1/common/rf_d_tx_reg.h -@@ -0,0 +1,430 @@ -+#ifdef RF_D_TX_REG -+#else -+#define RF_D_TX_REG -+ -+ -+#define RF_D_TX_REG_BASE (0x800) -+ -+#define RG_TX_A0 (RF_D_TX_REG_BASE + 0x0) -+// Bit 2 :0 rg_wf5g_tx_pa_vgcg0 U RW default = 'h4 -+// Bit 6 :4 rg_wf5g_tx_mxr_vgcg1 U RW default = 'h3 -+// Bit 10 :8 rg_wf5g_tx_mxr_lo_vb U RW default = 'h3 -+// Bit 14 :12 rg_wf5g_tx_mxr_lobuf_ict U RW default = 'h4 -+typedef union RG_TX_A0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_TX_PA_VGCG0 : 3; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF5G_TX_MXR_VGCG1 : 3; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF5G_TX_MXR_LO_VB : 3; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF5G_TX_MXR_LOBUF_ICT : 3; -+ unsigned int rsvd_3 : 17; -+ } b; -+} RG_TX_A0_FIELD_T; -+ -+#define RG_TX_A1 (RF_D_TX_REG_BASE + 0x4) -+// Bit 2 :0 rg_wf5g_tx_adb_cbank U RW default = 'h7 -+// Bit 6 :3 rg_wf5g_tx_adb_dc U RW default = 'h4 -+// Bit 10 :7 rg_wf5g_tx_adb_vb_ct U RW default = 'h0 -+// Bit 11 rg_wf5g_tx_adb_en U RW default = 'h1 -+// Bit 12 rg_wf5g_tx_adb_ed_en U RW default = 'h1 -+// Bit 16 :13 rg_wf5g_tx_adb_ed_gain U RW default = 'h4 -+// Bit 19 :17 rg_wf5g_tx_adb_icgm U RW default = 'h3 -+// Bit 22 :20 rg_wf5g_tx_adb_iptat U RW default = 'h0 -+// Bit 25 :23 rg_wf5g_tx_ib_adj U RW default = 'h0 -+typedef union RG_TX_A1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_TX_ADB_CBANK : 3; -+ unsigned int RG_WF5G_TX_ADB_DC : 4; -+ unsigned int RG_WF5G_TX_ADB_VB_CT : 4; -+ unsigned int RG_WF5G_TX_ADB_EN : 1; -+ unsigned int RG_WF5G_TX_ADB_ED_EN : 1; -+ unsigned int RG_WF5G_TX_ADB_ED_GAIN : 4; -+ unsigned int RG_WF5G_TX_ADB_ICGM : 3; -+ unsigned int RG_WF5G_TX_ADB_IPTAT : 3; -+ unsigned int RG_WF5G_TX_IB_ADJ : 3; -+ unsigned int rsvd_0 : 6; -+ } b; -+} RG_TX_A1_FIELD_T; -+ -+#define RG_TX_A2 (RF_D_TX_REG_BASE + 0x8) -+// Bit 0 rg_wf5g_tx_tssi_en U RW default = 'h0 -+// Bit 3 :1 rg_wf5g_tx_tssi_attn U RW default = 'h7 -+// Bit 6 :4 rg_wf5g_tx_tssi_lo_vb U RW default = 'h3 -+// Bit 7 rg_wf5g_tx_iqcal_en U RW default = 'h0 -+// Bit 8 rg_wf5g_tx_rxiqcal_en U RW default = 'h0 -+// Bit 16 :9 rg_wf5g_tx_tp_sel U RW default = 'h0 -+// Bit 17 rg_wf5g_tx_tp_en U RW default = 'h0 -+// Bit 20 :18 rg_wf5g_tx_pa_gain_man U RW default = 'h7 -+// Bit 23 :21 rg_wf5g_tx_mxr_gain_man U RW default = 'h7 -+// Bit 24 rg_wf5g_tx_man_mode U RW default = 'h0 -+typedef union RG_TX_A2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_TX_TSSI_EN : 1; -+ unsigned int RG_WF5G_TX_TSSI_ATTN : 3; -+ unsigned int RG_WF5G_TX_TSSI_LO_VB : 3; -+ unsigned int RG_WF5G_TX_IQCAL_EN : 1; -+ unsigned int RG_WF5G_TX_RXIQCAL_EN : 1; -+ unsigned int RG_WF5G_TX_TP_SEL : 8; -+ unsigned int RG_WF5G_TX_TP_EN : 1; -+ unsigned int RG_WF5G_TX_PA_GAIN_MAN : 3; -+ unsigned int RG_WF5G_TX_MXR_GAIN_MAN : 3; -+ unsigned int RG_WF5G_TX_MAN_MODE : 1; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_TX_A2_FIELD_T; -+ -+#define RG_TX_A3 (RF_D_TX_REG_BASE + 0xc) -+// Bit 0 rg_m0_wf5g_tx_pa_en U RW default = 'h0 -+// Bit 1 rg_m0_wf5g_tx_mxr_en U RW default = 'h0 -+// Bit 2 rg_m0_wf5g_tx_ib_en U RW default = 'h0 -+// Bit 3 rg_m1_wf5g_tx_pa_en U RW default = 'h0 -+// Bit 4 rg_m1_wf5g_tx_mxr_en U RW default = 'h0 -+// Bit 5 rg_m1_wf5g_tx_ib_en U RW default = 'h0 -+// Bit 6 rg_m2_wf5g_tx_pa_en U RW default = 'h1 -+// Bit 7 rg_m2_wf5g_tx_mxr_en U RW default = 'h1 -+// Bit 8 rg_m2_wf5g_tx_ib_en U RW default = 'h1 -+// Bit 9 rg_m3_wf5g_tx_pa_en U RW default = 'h0 -+// Bit 10 rg_m3_wf5g_tx_mxr_en U RW default = 'h0 -+// Bit 11 rg_m3_wf5g_tx_ib_en U RW default = 'h0 -+// Bit 31 :16 rg_wf5g_tx_rsv U RW default = 'h0 -+typedef union RG_TX_A3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M0_WF5G_TX_PA_EN : 1; -+ unsigned int RG_M0_WF5G_TX_MXR_EN : 1; -+ unsigned int RG_M0_WF5G_TX_IB_EN : 1; -+ unsigned int RG_M1_WF5G_TX_PA_EN : 1; -+ unsigned int RG_M1_WF5G_TX_MXR_EN : 1; -+ unsigned int RG_M1_WF5G_TX_IB_EN : 1; -+ unsigned int RG_M2_WF5G_TX_PA_EN : 1; -+ unsigned int RG_M2_WF5G_TX_MXR_EN : 1; -+ unsigned int RG_M2_WF5G_TX_IB_EN : 1; -+ unsigned int RG_M3_WF5G_TX_PA_EN : 1; -+ unsigned int RG_M3_WF5G_TX_MXR_EN : 1; -+ unsigned int RG_M3_WF5G_TX_IB_EN : 1; -+ unsigned int rsvd_0 : 4; -+ unsigned int RG_WF5G_TX_RSV : 16; -+ } b; -+} RG_TX_A3_FIELD_T; -+ -+#define RG_TX_A4 (RF_D_TX_REG_BASE + 0x10) -+// Bit 2 :0 rg_wf2g_tx_pa_vgcg0 U RW default = 'h7 -+// Bit 7 :3 rg_wf2g_tx_mxr_cbank U RW default = 'h4 -+// Bit 10 :8 rg_wf2g_tx_mxr_vgcg1 U RW default = 'h7 -+// Bit 13 :11 rg_wf2g_tx_mxr_lo_vb U RW default = 'h7 -+// Bit 16 :14 rg_wf2g_tx_mxr_lobuf_ict U RW default = 'h1 -+// Bit 20 :17 rg_wf2g_tx_var_u U RW default = 'h8 -+// Bit 24 :21 rg_wf2g_tx_var_d U RW default = 'h8 -+typedef union RG_TX_A4_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_TX_PA_VGCG0 : 3; -+ unsigned int RG_WF2G_TX_MXR_CBANK : 5; -+ unsigned int RG_WF2G_TX_MXR_VGCG1 : 3; -+ unsigned int RG_WF2G_TX_MXR_LO_VB : 3; -+ unsigned int RG_WF2G_TX_MXR_LOBUF_ICT : 3; -+ unsigned int RG_WF2G_TX_VAR_U : 4; -+ unsigned int RG_WF2G_TX_VAR_D : 4; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_TX_A4_FIELD_T; -+ -+#define RG_TX_A5 (RF_D_TX_REG_BASE + 0x14) -+// Bit 2 :0 rg_wf2g_tx_adb_cbank U RW default = 'h3 -+// Bit 6 :3 rg_wf2g_tx_adb_dcib U RW default = 'h0 -+// Bit 10 :7 rg_wf2g_tx_adb_dcvb U RW default = 'h0 -+// Bit 11 rg_wf2g_tx_adb_en U RW default = 'h1 -+// Bit 12 rg_wf2g_tx_adb_ed_en U RW default = 'h1 -+// Bit 16 :13 rg_wf2g_tx_adb_ed_gain U RW default = 'h3 -+// Bit 19 :17 rg_wf2g_tx_adb_icgm U RW default = 'h2 -+// Bit 22 :20 rg_wf2g_tx_adb_iptat U RW default = 'h2 -+// Bit 25 :23 rg_wf2g_tx_ib_adj U RW default = 'h3 -+// Bit 26 rg_wf2g_tx_tssi_en U RW default = 'h0 -+// Bit 29 :27 rg_wf2g_tx_tssi_attn U RW default = 'h7 -+typedef union RG_TX_A5_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_TX_ADB_CBANK : 3; -+ unsigned int RG_WF2G_TX_ADB_DCIB : 4; -+ unsigned int RG_WF2G_TX_ADB_DCVB : 4; -+ unsigned int RG_WF2G_TX_ADB_EN : 1; -+ unsigned int RG_WF2G_TX_ADB_ED_EN : 1; -+ unsigned int RG_WF2G_TX_ADB_ED_GAIN : 4; -+ unsigned int RG_WF2G_TX_ADB_ICGM : 3; -+ unsigned int RG_WF2G_TX_ADB_IPTAT : 3; -+ unsigned int RG_WF2G_TX_IB_ADJ : 3; -+ unsigned int RG_WF2G_TX_TSSI_EN : 1; -+ unsigned int RG_WF2G_TX_TSSI_ATTN : 3; -+ unsigned int rsvd_0 : 2; -+ } b; -+} RG_TX_A5_FIELD_T; -+ -+#define RG_TX_A6 (RF_D_TX_REG_BASE + 0x18) -+// Bit 2 :0 rg_wf2g_tx_tssi_lo_vb U RW default = 'h3 -+// Bit 3 rg_wf2g_tx_iqcal_en U RW default = 'h0 -+// Bit 4 rg_wf2g_tx_rxiqcal_en U RW default = 'h0 -+// Bit 12 :5 rg_wf2g_tx_tp_sel U RW default = 'h0 -+// Bit 13 rg_wf2g_tx_tp_en U RW default = 'h0 -+// Bit 16 :14 rg_wf2g_tx_pa_gain_man U RW default = 'h7 -+// Bit 19 :17 rg_wf2g_tx_mxr_gain_man U RW default = 'h7 -+// Bit 20 rg_wf2g_tx_man_mode U RW default = 'h0 -+typedef union RG_TX_A6_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_TX_TSSI_LO_VB : 3; -+ unsigned int RG_WF2G_TX_IQCAL_EN : 1; -+ unsigned int RG_WF2G_TX_RXIQCAL_EN : 1; -+ unsigned int RG_WF2G_TX_TP_SEL : 8; -+ unsigned int RG_WF2G_TX_TP_EN : 1; -+ unsigned int RG_WF2G_TX_PA_GAIN_MAN : 3; -+ unsigned int RG_WF2G_TX_MXR_GAIN_MAN : 3; -+ unsigned int RG_WF2G_TX_MAN_MODE : 1; -+ unsigned int rsvd_0 : 11; -+ } b; -+} RG_TX_A6_FIELD_T; -+ -+#define RG_TX_A7 (RF_D_TX_REG_BASE + 0x1c) -+// Bit 0 rg_m0_wf2g_tx_pa_en U RW default = 'h0 -+// Bit 1 rg_m0_wf2g_tx_mxr_en U RW default = 'h0 -+// Bit 2 rg_m0_wf2g_tx_var_en U RW default = 'h0 -+// Bit 3 rg_m0_wf2g_tx_ib_en U RW default = 'h0 -+// Bit 4 rg_m1_wf2g_tx_pa_en U RW default = 'h0 -+// Bit 5 rg_m1_wf2g_tx_mxr_en U RW default = 'h0 -+// Bit 6 rg_m1_wf2g_tx_var_en U RW default = 'h0 -+// Bit 7 rg_m1_wf2g_tx_ib_en U RW default = 'h0 -+// Bit 8 rg_m2_wf2g_tx_pa_en U RW default = 'h0 -+// Bit 9 rg_m2_wf2g_tx_mxr_en U RW default = 'h0 -+// Bit 10 rg_m2_wf2g_tx_var_en U RW default = 'h0 -+// Bit 11 rg_m2_wf2g_tx_ib_en U RW default = 'h0 -+// Bit 12 rg_m3_wf2g_tx_pa_en U RW default = 'h0 -+// Bit 13 rg_m3_wf2g_tx_mxr_en U RW default = 'h0 -+// Bit 14 rg_m3_wf2g_tx_var_en U RW default = 'h0 -+// Bit 15 rg_m3_wf2g_tx_ib_en U RW default = 'h0 -+// Bit 31 :16 rg_wf2g_tx_rsv U RW default = 'h0 -+typedef union RG_TX_A7_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M0_WF2G_TX_PA_EN : 1; -+ unsigned int RG_M0_WF2G_TX_MXR_EN : 1; -+ unsigned int RG_M0_WF2G_TX_VAR_EN : 1; -+ unsigned int RG_M0_WF2G_TX_IB_EN : 1; -+ unsigned int RG_M1_WF2G_TX_PA_EN : 1; -+ unsigned int RG_M1_WF2G_TX_MXR_EN : 1; -+ unsigned int RG_M1_WF2G_TX_VAR_EN : 1; -+ unsigned int RG_M1_WF2G_TX_IB_EN : 1; -+ unsigned int RG_M2_WF2G_TX_PA_EN : 1; -+ unsigned int RG_M2_WF2G_TX_MXR_EN : 1; -+ unsigned int RG_M2_WF2G_TX_VAR_EN : 1; -+ unsigned int RG_M2_WF2G_TX_IB_EN : 1; -+ unsigned int RG_M3_WF2G_TX_PA_EN : 1; -+ unsigned int RG_M3_WF2G_TX_MXR_EN : 1; -+ unsigned int RG_M3_WF2G_TX_VAR_EN : 1; -+ unsigned int RG_M3_WF2G_TX_IB_EN : 1; -+ unsigned int RG_WF2G_TX_RSV : 16; -+ } b; -+} RG_TX_A7_FIELD_T; -+ -+#define RG_TX_A8 (RF_D_TX_REG_BASE + 0x20) -+// Bit 2 :0 rg_wf5g_tx_pa_gain_g1 U RW default = 'h7 -+// Bit 6 :4 rg_wf5g_tx_pa_gain_g2 U RW default = 'h7 -+// Bit 10 :8 rg_wf5g_tx_pa_gain_g3 U RW default = 'h3 -+// Bit 14 :12 rg_wf5g_tx_pa_gain_g4 U RW default = 'h1 -+// Bit 18 :16 rg_wf5g_tx_mxr_gain_g1 U RW default = 'h7 -+// Bit 22 :20 rg_wf5g_tx_mxr_gain_g2 U RW default = 'h7 -+// Bit 26 :24 rg_wf5g_tx_mxr_gain_g3 U RW default = 'h3 -+// Bit 30 :28 rg_wf5g_tx_mxr_gain_g4 U RW default = 'h1 -+typedef union RG_TX_A8_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_TX_PA_GAIN_G1 : 3; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF5G_TX_PA_GAIN_G2 : 3; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF5G_TX_PA_GAIN_G3 : 3; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF5G_TX_PA_GAIN_G4 : 3; -+ unsigned int rsvd_3 : 1; -+ unsigned int RG_WF5G_TX_MXR_GAIN_G1 : 3; -+ unsigned int rsvd_4 : 1; -+ unsigned int RG_WF5G_TX_MXR_GAIN_G2 : 3; -+ unsigned int rsvd_5 : 1; -+ unsigned int RG_WF5G_TX_MXR_GAIN_G3 : 3; -+ unsigned int rsvd_6 : 1; -+ unsigned int RG_WF5G_TX_MXR_GAIN_G4 : 3; -+ unsigned int rsvd_7 : 1; -+ } b; -+} RG_TX_A8_FIELD_T; -+ -+#define RG_TX_A9 (RF_D_TX_REG_BASE + 0x24) -+// Bit 2 :0 rg_wf2g_tx_pa_gain_g1 U RW default = 'h7 -+// Bit 6 :4 rg_wf2g_tx_pa_gain_g2 U RW default = 'h7 -+// Bit 10 :8 rg_wf2g_tx_pa_gain_g3 U RW default = 'h3 -+// Bit 14 :12 rg_wf2g_tx_pa_gain_g4 U RW default = 'h1 -+// Bit 18 :16 rg_wf2g_tx_mxr_gain_g1 U RW default = 'h7 -+// Bit 22 :20 rg_wf2g_tx_mxr_gain_g2 U RW default = 'h7 -+// Bit 26 :24 rg_wf2g_tx_mxr_gain_g3 U RW default = 'h3 -+// Bit 30 :28 rg_wf2g_tx_mxr_gain_g4 U RW default = 'h1 -+typedef union RG_TX_A9_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF2G_TX_PA_GAIN_G1 : 3; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_WF2G_TX_PA_GAIN_G2 : 3; -+ unsigned int rsvd_1 : 1; -+ unsigned int RG_WF2G_TX_PA_GAIN_G3 : 3; -+ unsigned int rsvd_2 : 1; -+ unsigned int RG_WF2G_TX_PA_GAIN_G4 : 3; -+ unsigned int rsvd_3 : 1; -+ unsigned int RG_WF2G_TX_MXR_GAIN_G1 : 3; -+ unsigned int rsvd_4 : 1; -+ unsigned int RG_WF2G_TX_MXR_GAIN_G2 : 3; -+ unsigned int rsvd_5 : 1; -+ unsigned int RG_WF2G_TX_MXR_GAIN_G3 : 3; -+ unsigned int rsvd_6 : 1; -+ unsigned int RG_WF2G_TX_MXR_GAIN_G4 : 3; -+ unsigned int rsvd_7 : 1; -+ } b; -+} RG_TX_A9_FIELD_T; -+ -+#define RG_TX_A10 (RF_D_TX_REG_BASE + 0x28) -+// Bit 0 rg_m4_wf5g_tx_pa_en U RW default = 'h1 -+// Bit 1 rg_m4_wf5g_tx_mxr_en U RW default = 'h1 -+// Bit 2 rg_m4_wf5g_tx_ib_en U RW default = 'h1 -+// Bit 3 rg_m5_wf5g_tx_pa_en U RW default = 'h0 -+// Bit 4 rg_m5_wf5g_tx_mxr_en U RW default = 'h0 -+// Bit 5 rg_m5_wf5g_tx_ib_en U RW default = 'h0 -+// Bit 6 rg_m6_wf5g_tx_pa_en U RW default = 'h0 -+// Bit 7 rg_m6_wf5g_tx_mxr_en U RW default = 'h0 -+// Bit 8 rg_m6_wf5g_tx_ib_en U RW default = 'h0 -+// Bit 9 rg_m7_wf5g_tx_pa_en U RW default = 'h0 -+// Bit 10 rg_m7_wf5g_tx_mxr_en U RW default = 'h0 -+// Bit 11 rg_m7_wf5g_tx_ib_en U RW default = 'h0 -+typedef union RG_TX_A10_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M4_WF5G_TX_PA_EN : 1; -+ unsigned int RG_M4_WF5G_TX_MXR_EN : 1; -+ unsigned int RG_M4_WF5G_TX_IB_EN : 1; -+ unsigned int RG_M5_WF5G_TX_PA_EN : 1; -+ unsigned int RG_M5_WF5G_TX_MXR_EN : 1; -+ unsigned int RG_M5_WF5G_TX_IB_EN : 1; -+ unsigned int RG_M6_WF5G_TX_PA_EN : 1; -+ unsigned int RG_M6_WF5G_TX_MXR_EN : 1; -+ unsigned int RG_M6_WF5G_TX_IB_EN : 1; -+ unsigned int RG_M7_WF5G_TX_PA_EN : 1; -+ unsigned int RG_M7_WF5G_TX_MXR_EN : 1; -+ unsigned int RG_M7_WF5G_TX_IB_EN : 1; -+ unsigned int rsvd_0 : 20; -+ } b; -+} RG_TX_A10_FIELD_T; -+ -+#define RG_TX_A11 (RF_D_TX_REG_BASE + 0x2c) -+// Bit 0 rg_m4_wf2g_tx_pa_en U RW default = 'h0 -+// Bit 1 rg_m4_wf2g_tx_mxr_en U RW default = 'h0 -+// Bit 2 rg_m4_wf2g_tx_var_en U RW default = 'h0 -+// Bit 3 rg_m4_wf2g_tx_ib_en U RW default = 'h0 -+// Bit 4 rg_m5_wf2g_tx_pa_en U RW default = 'h0 -+// Bit 5 rg_m5_wf2g_tx_mxr_en U RW default = 'h0 -+// Bit 6 rg_m5_wf2g_tx_var_en U RW default = 'h0 -+// Bit 7 rg_m5_wf2g_tx_ib_en U RW default = 'h0 -+// Bit 8 rg_m6_wf2g_tx_pa_en U RW default = 'h1 -+// Bit 9 rg_m6_wf2g_tx_mxr_en U RW default = 'h1 -+// Bit 10 rg_m6_wf2g_tx_var_en U RW default = 'h1 -+// Bit 11 rg_m6_wf2g_tx_ib_en U RW default = 'h1 -+// Bit 12 rg_m7_wf2g_tx_pa_en U RW default = 'h0 -+// Bit 13 rg_m7_wf2g_tx_mxr_en U RW default = 'h0 -+// Bit 14 rg_m7_wf2g_tx_var_en U RW default = 'h0 -+// Bit 15 rg_m7_wf2g_tx_ib_en U RW default = 'h0 -+typedef union RG_TX_A11_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_M4_WF2G_TX_PA_EN : 1; -+ unsigned int RG_M4_WF2G_TX_MXR_EN : 1; -+ unsigned int RG_M4_WF2G_TX_VAR_EN : 1; -+ unsigned int RG_M4_WF2G_TX_IB_EN : 1; -+ unsigned int RG_M5_WF2G_TX_PA_EN : 1; -+ unsigned int RG_M5_WF2G_TX_MXR_EN : 1; -+ unsigned int RG_M5_WF2G_TX_VAR_EN : 1; -+ unsigned int RG_M5_WF2G_TX_IB_EN : 1; -+ unsigned int RG_M6_WF2G_TX_PA_EN : 1; -+ unsigned int RG_M6_WF2G_TX_MXR_EN : 1; -+ unsigned int RG_M6_WF2G_TX_VAR_EN : 1; -+ unsigned int RG_M6_WF2G_TX_IB_EN : 1; -+ unsigned int RG_M7_WF2G_TX_PA_EN : 1; -+ unsigned int RG_M7_WF2G_TX_MXR_EN : 1; -+ unsigned int RG_M7_WF2G_TX_VAR_EN : 1; -+ unsigned int RG_M7_WF2G_TX_IB_EN : 1; -+ unsigned int rsvd_0 : 16; -+ } b; -+} RG_TX_A11_FIELD_T; -+ -+#define RG_TX_A12 (RF_D_TX_REG_BASE + 0x30) -+// Bit 7 :0 rg_wf_tx_gain_man U RW default = 'h0 -+// Bit 8 rg_wf_tx_gain_man_mode U RW default = 'h0 -+// Bit 23 :16 rg_wf_tx_pa_en_delay_bnd U RW default = 'h14 -+// Bit 24 rg_wf_tx_pa_en_delay_bypass U RW default = 'h0 -+typedef union RG_TX_A12_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF_TX_GAIN_MAN : 8; -+ unsigned int RG_WF_TX_GAIN_MAN_MODE : 1; -+ unsigned int rsvd_0 : 7; -+ unsigned int RG_WF_TX_PA_EN_DELAY_BND : 8; -+ unsigned int RG_WF_TX_PA_EN_DELAY_BYPASS : 1; -+ unsigned int rsvd_1 : 7; -+ } b; -+} RG_TX_A12_FIELD_T; -+ -+#define RG_TX_A13 (RF_D_TX_REG_BASE + 0x34) -+// Bit 4 :0 rg_wf5g_tx_mxr_cbank_g1 U RW default = 'h7 -+// Bit 9 :5 rg_wf5g_tx_mxr_cbank_g2 U RW default = 'h7 -+// Bit 14 :10 rg_wf5g_tx_mxr_cbank_g3 U RW default = 'h7 -+// Bit 19 :15 rg_wf5g_tx_mxr_cbank_g4 U RW default = 'h3 -+// Bit 24 :20 rg_wf5g_tx_mxr_cbank_man U RW default = 'h4 -+typedef union RG_TX_A13_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_WF5G_TX_MXR_CBANK_G1 : 5; -+ unsigned int RG_WF5G_TX_MXR_CBANK_G2 : 5; -+ unsigned int RG_WF5G_TX_MXR_CBANK_G3 : 5; -+ unsigned int RG_WF5G_TX_MXR_CBANK_G4 : 5; -+ unsigned int RG_WF5G_TX_MXR_CBANK_MAN : 5; -+ unsigned int rsvd_0 : 7; -+ } b; -+} RG_TX_A13_FIELD_T; -+ -+#endif -+ -diff --git a/drivers/net/wireless/w1/common/rf_d_xosc_reg.h b/drivers/net/wireless/w1/common/rf_d_xosc_reg.h -new file mode 100644 -index 000000000000..1e5bfa1aaaf7 ---- /dev/null -+++ b/drivers/net/wireless/w1/common/rf_d_xosc_reg.h -@@ -0,0 +1,121 @@ -+#ifdef RF_D_XOSC_REG -+#else -+#define RF_D_XOSC_REG -+ -+#define CHIP_ANA_REG_BASE (0xf01000) -+ -+#define RG_XOSC_A7 (CHIP_ANA_REG_BASE + 0x20) -+// Bit 0 rg_xo_bg_en_man U RW default = 'h1 -+// Bit 2 rg_xo_bg_en_man_sel U RW default = 'h0 -+// Bit 3 rg_xo_ldo_bypass_en U RW default = 'h0 -+// Bit 4 rg_xo_ldo_en_man U RW default = 'h1 -+// Bit 5 rg_xo_ldo_en_man_sel U RW default = 'h0 -+// Bit 7 :6 rg_xo_ldo_fbr_ctrl U RW default = 'h2 -+// Bit 13 :8 rg_xo_ldo_vref_cal U RW default = 'h10 -+// Bit 14 rg_xo_en_man U RW default = 'h1 -+// Bit 15 rg_xo_en_man_sel U RW default = 'h0 -+// Bit 16 rg_xo_sel U RW default = 'h0 -+// Bit 21 :17 rg_xo_core_bias_rcal_ctrl U RW default = 'h10 -+typedef union RG_XOSC_A7_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_XO_BG_EN_MAN : 1; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_XO_BG_EN_MAN_SEL : 1; -+ unsigned int RG_XO_LDO_BYPASS_EN : 1; -+ unsigned int RG_XO_LDO_EN_MAN : 1; -+ unsigned int RG_XO_LDO_EN_MAN_SEL : 1; -+ unsigned int RG_XO_LDO_FBR_CTRL : 2; -+ unsigned int RG_XO_LDO_VREF_CAL : 6; -+ unsigned int RG_XO_EN_MAN : 1; -+ unsigned int RG_XO_EN_MAN_SEL : 1; -+ unsigned int RG_XO_SEL : 1; -+ unsigned int RG_XO_CORE_BIAS_RCAL_CTRL : 5; -+ unsigned int rsvd_1 : 10; -+ } b; -+} RG_XOSC_A7_FIELD_T; -+ -+#define RG_XOSC_A8 (CHIP_ANA_REG_BASE + 0x24) -+// Bit 3 :0 rg_xo_core_cfixed_ctrl U RW default = 'h8 -+// Bit 11 :4 rg_xo_core_ctune_ctrl U RW default = 'h32 -+// Bit 15 :12 rg_xo_core_gmos_vb_sel U RW default = 'h8 -+// Bit 20 :17 rg_xo_pd_vref_sel U RW default = 'h8 -+typedef union RG_XOSC_A8_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_XO_CORE_CFIXED_CTRL : 4; -+ unsigned int RG_XO_CORE_CTUNE_CTRL : 8; -+ unsigned int RG_XO_CORE_GMOS_VB_SEL : 4; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_XO_PD_VREF_SEL : 4; -+ unsigned int rsvd_1 : 11; -+ } b; -+} RG_XOSC_A8_FIELD_T; -+ -+#define RG_XOSC_A9 (CHIP_ANA_REG_BASE + 0x28) -+// Bit 3 :0 rg_xo_buf1_bias_ctrl U RW default = 'h8 -+// Bit 7 :4 rg_xo_buf2_bias_ctrl U RW default = 'h8 -+// Bit 11 :8 rg_xo_buf3_bias_ctrl U RW default = 'h8 -+// Bit 12 rg_xo_aml_cal_error_ctrl U RW default = 'h0 -+typedef union RG_XOSC_A9_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_XO_BUF1_BIAS_CTRL : 4; -+ unsigned int RG_XO_BUF2_BIAS_CTRL : 4; -+ unsigned int RG_XO_BUF3_BIAS_CTRL : 4; -+ unsigned int RG_XO_AML_CAL_ERROR_CTRL : 1; -+ unsigned int rsvd_0 : 19; -+ } b; -+} RG_XOSC_A9_FIELD_T; -+ -+#define RG_XOSC_A11 (CHIP_ANA_REG_BASE + 0x30) -+// Bit 0 rg_xo_ldo_fc_en_man_sel U RW default = 'h0 -+// Bit 1 rg_xo_ldo_fc_en_man U RW default = 'h0 -+// Bit 2 rg_xo_pd_en_man_sel U RW default = 'h0 -+// Bit 3 rg_xo_pd_en_man U RW default = 'h1 -+// Bit 4 rg_xo_buf_core_en_man_sel U RW default = 'h0 -+// Bit 5 rg_xo_buf_core_en_man U RW default = 'h1 -+// Bit 6 rg_xo_buf_wf_en_man_sel U RW default = 'h0 -+// Bit 7 rg_xo_buf_wf_en_man U RW default = 'h1 -+// Bit 8 rg_xo_buf_dig_en_man_sel U RW default = 'h0 -+// Bit 9 rg_xo_buf_dig_en_man U RW default = 'h1 -+// Bit 10 rg_xo_buf_bb_en_man_sel U RW default = 'h0 -+// Bit 11 rg_xo_buf_bb_en_man U RW default = 'h1 -+// Bit 12 rg_xo_buf_bt_en_man_sel U RW default = 'h0 -+// Bit 13 rg_xo_buf_bt_en_man U RW default = 'h1 -+// Bit 15 rg_xo_core_bias_ctrl_man_sel U RW default = 'h0 -+// Bit 23 :16 rg_xo_core_bias_ctrl_man U RW default = 'hff -+// Bit 31 :24 rg_xosc_wait_bnd U RW default = 'h3f -+typedef union RG_XOSC_A11_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int RG_XO_LDO_FC_EN_MAN_SEL : 1; -+ unsigned int RG_XO_LDO_FC_EN_MAN : 1; -+ unsigned int RG_XO_PD_EN_MAN_SEL : 1; -+ unsigned int RG_XO_PD_EN_MAN : 1; -+ unsigned int RG_XO_BUF_CORE_EN_MAN_SEL : 1; -+ unsigned int RG_XO_BUF_CORE_EN_MAN : 1; -+ unsigned int RG_XO_BUF_WF_EN_MAN_SEL : 1; -+ unsigned int RG_XO_BUF_WF_EN_MAN : 1; -+ unsigned int RG_XO_BUF_DIG_EN_MAN_SEL : 1; -+ unsigned int RG_XO_BUF_DIG_EN_MAN : 1; -+ unsigned int RG_XO_BUF_BB_EN_MAN_SEL : 1; -+ unsigned int RG_XO_BUF_BB_EN_MAN : 1; -+ unsigned int RG_XO_BUF_BT_EN_MAN_SEL : 1; -+ unsigned int RG_XO_BUF_BT_EN_MAN : 1; -+ unsigned int rsvd_0 : 1; -+ unsigned int RG_XO_CORE_BIAS_CTRL_MAN_SEL : 1; -+ unsigned int RG_XO_CORE_BIAS_CTRL_MAN : 8; -+ unsigned int RG_XOSC_WAIT_BND : 8; -+ } b; -+} RG_XOSC_A11_FIELD_T; -+ -+#endif -\ No newline at end of file -diff --git a/drivers/net/wireless/w1/common/wf_register.h b/drivers/net/wireless/w1/common/wf_register.h -new file mode 100644 -index 000000000000..f2b2b78c05ff ---- /dev/null -+++ b/drivers/net/wireless/w1/common/wf_register.h -@@ -0,0 +1,21 @@ -+#ifndef __WF_REGISTER__ -+#define __WF_REGISTER__ -+ -+// aon -+#include "chip_ana_reg.h" -+#include "chip_intf_reg.h" -+#include "chip_pmu_reg.h" -+ -+// rf adda -+#include "rf_d_adda_core_reg.h" -+#include "rf_d_adda_esti_reg.h" -+#include "rf_d_adda_recv_reg.h" -+#include "rf_d_adda_xmit_reg.h" -+ -+// rf -+#include "rf_d_rx_reg.h" -+#include "rf_d_sx_reg.h" -+#include "rf_d_top_reg.h" -+#include "rf_d_tx_reg.h" -+ -+#endif -diff --git a/drivers/net/wireless/w1/common/wifi_adda_addr.h b/drivers/net/wireless/w1/common/wifi_adda_addr.h -new file mode 100644 -index 000000000000..b772bb73ee10 ---- /dev/null -+++ b/drivers/net/wireless/w1/common/wifi_adda_addr.h -@@ -0,0 +1,10 @@ -+#ifndef __WIFI_ADDA_ADDR_H__ -+#define __WIFI_ADDA_ADDR_H__ -+ -+#define WIFI_ADDA (0xe000) -+ -+#define RG_ADDA_ADR_88 (WIFI_ADDA + 0x488) -+#define RG_IQ_SWAP_CTRL (WIFI_ADDA + 0x808) -+ -+#endif -+ -diff --git a/drivers/net/wireless/w1/common/wifi_agc_addr.h b/drivers/net/wireless/w1/common/wifi_agc_addr.h -new file mode 100644 -index 000000000000..e850665c2e07 ---- /dev/null -+++ b/drivers/net/wireless/w1/common/wifi_agc_addr.h -@@ -0,0 +1,110 @@ -+#ifndef __ADDR_AGC_H__ -+#define __ADDR_AGC_H__ -+ -+#define WIFI_AGC (0x8000) -+ -+#define RG_AGC_STF_LIMIT_CCA_COND_EN (WIFI_AGC + 0x6c) -+#define RG_AGC_CCA_COND_TS_CTRL (WIFI_AGC + 0x70) -+#define RG_AGC_RG_AGC_OB_CCA_RES (WIFI_AGC + 0x274) -+#define RG_AGC_RG_AGC_OB_CCA_COND01 (WIFI_AGC + 0x278) -+#define RG_AGC_RG_AGC_OB_CCA_COND23 (WIFI_AGC + 0x27c) -+#define RG_AGC_STATE (WIFI_AGC+0x258) -+#define RG_AGC_OB_IC_GAIN (WIFI_AGC+0x25c) -+#define RG_AGC_WATCH1 (WIFI_AGC+0x260) -+#define RG_AGC_WATCH2 (WIFI_AGC+0x264) -+#define RG_AGC_WATCH3 (WIFI_AGC+0x268) -+#define RG_AGC_WATCH4 (WIFI_AGC+0x26c) -+#define RG_AGC_OB_ANT_NFLOOR (WIFI_AGC+0x270) -+#define RG_AGC_OB_CCA_RES (WIFI_AGC+0x274) -+#define RG_AGC_OB_CCA_COND01 (WIFI_AGC+0x278) -+#define RG_AGC_OB_CCA_COND23 (WIFI_AGC+0x27c) -+#define RG_AGC_GAIN_SEL (WIFI_AGC+ 0x84) -+#define RG_AGC_STS_REG_0 (WIFI_AGC+ 0x64) -+#define RG_AGC_EN (WIFI_AGC+ 0x10) -+ -+ -+struct AGC_CCA_COND_TS_CTRL_BITS { -+ unsigned int cca_cond_ts :8, -+ cca_cond_ts_num :20, -+ ed_avglen :3, -+ reserved41 :1; -+}; -+ -+struct AGC_OB_CCA_RES_BITS { -+ unsigned int cca_cond_rdy :1, -+ reserved170 :15, -+ cca_cond8 :16; -+}; -+ -+struct AGC_STF_LIMIT_CCA_COND_EN_BITS { -+ unsigned int stf_cfo_limit :19, -+ reserved39 :1, -+ cca_cond_en :9, -+ cca_cal_force :1, -+ reserved40 :2; -+}; -+ -+#pragma pack(push ,1) -+struct agc_prt_info -+{ -+ unsigned short addr; -+ char *prt1; -+ char *prt2; -+}; -+ -+struct sts_agc_state { -+ unsigned int rsv1:8,state:4,rsv2:20; -+}; -+ -+struct sts_agc_ob_ic_gain { -+ unsigned int r_rx_ic_gain:8,r_agc_fine_db:9,rsv:15; -+}; -+ -+struct sts_agc_watch1 { -+ unsigned int r_pow_sat_db:9, rsv1:3, r_primary20_db:9, rsv2:11; -+}; -+ -+struct sts_agc_watch2 { -+ unsigned int r_primary40_db:9, rsv1:3,r_primary80_db:9,rsv2:11; -+}; -+ -+struct sts_agc_watch3 { -+ unsigned int r_rssi0_db:10, rsv1:2,r_rssi1_db:10,rsv2:10; -+}; -+ -+struct sts_agc_watch4 { -+ unsigned int r_rssi2_db:10, rsv1:2,r_rssi3_db:10,rsv2:10; -+}; -+ -+struct sts_ob_ant_nfloor { -+ unsigned int r_snr_qdb:10, rsv1:2,r_ant_nfloor_qdb:10,rsv2:10; -+}; -+ -+struct sts_ob_cca_res { -+ unsigned int cca_cond_rdy:1, rsv1:15, cca_cond8:16; -+}; -+ -+struct sts_ob_cca_cond01 { -+ unsigned int cca_cond0:16, cca_cond1:16; -+}; -+ -+struct sts_ob_cca_cond23 { -+ unsigned int cca_cond2:16, cca_cond3:16; -+}; -+ -+union sts_agc_reg_u { -+ struct sts_agc_state state; -+ struct sts_agc_ob_ic_gain ic_gain; -+ struct sts_agc_watch1 wtc1; -+ struct sts_agc_watch2 wtc2; -+ struct sts_agc_watch3 wtc3; -+ struct sts_agc_watch4 wtc4; -+ struct sts_ob_ant_nfloor ant_nfloor; -+ struct sts_ob_cca_res cca_res; -+ struct sts_ob_cca_cond01 cca_cond_m1; -+ struct sts_ob_cca_cond23 cca_cond_m2; -+}; -+ -+#pragma pack(pop) -+ -+#endif -diff --git a/drivers/net/wireless/w1/common/wifi_aon_addr.h b/drivers/net/wireless/w1/common/wifi_aon_addr.h -new file mode 100644 -index 000000000000..3a38a28fe50a ---- /dev/null -+++ b/drivers/net/wireless/w1/common/wifi_aon_addr.h -@@ -0,0 +1,24 @@ -+#ifndef __ADDR_AON_H__ -+#define __ADDR_AON_H__ -+ -+ -+//#define WIFI_AON (0xf800) -+#define WIFI_AON (0x00F00000) -+ -+// pmu status -+#define PMU_PWR_OFF 0x0 -+#define PMU_PWR_XOSC 0x1 -+#define PMU_XOSC_WAIT 0x2 -+#define PMU_XOSC_DPLL 0x3 -+#define PMU_DPLL_WAIT 0x4 -+#define PMU_DPLL_ACT 0x5 -+#define PMU_ACT_MODE 0x6 -+#define PMU_ACT_SLEEP 0x7 -+#define PMU_SLEEP_MODE 0x8 -+#define PMU_SLEEP_WAKE 0x9 -+#define PMU_WAKE_WAIT 0xa -+#define PMU_WAKE_XOSC 0xb -+ -+#define WIFI_RG_AON_CFG4 (WIFI_AON + 0x78) -+#define WIFI_RG_AON_CFG5 (WIFI_AON + 0x7C) -+#endif -diff --git a/drivers/net/wireless/w1/common/wifi_coex_addr.h b/drivers/net/wireless/w1/common/wifi_coex_addr.h -new file mode 100644 -index 000000000000..68be97d11a79 ---- /dev/null -+++ b/drivers/net/wireless/w1/common/wifi_coex_addr.h -@@ -0,0 +1,34 @@ -+#ifndef __WIFI_COEX_ADDR_H__ -+#define __WIFI_COEX_ADDR_H__ -+ -+#define WIFI_COEX (0x00f06000) -+ -+#define RG_COEX_PRIORITY_M6 (WIFI_COEX + 0xbc) -+#define RG_COEX_PRD_NUM_M6 (WIFI_COEX + 0xc0) -+#define RG_COEX_ACT_NUM_M6 (WIFI_COEX + 0xc4) -+#define RG_COEX_OFFSET_NUM_M6 (WIFI_COEX + 0xc8) -+#define RG_COEX_INT_OFFSET_M6 (WIFI_COEX + 0xcc) -+#define RG_COEX_INI2_OFFSET_M6 (WIFI_COEX + 0xd0) -+ -+#define RG_COEX_HS5W_MANUAL0 (WIFI_COEX + 0x4) -+#define RG_COEX_HS5W_MANUAL1 (WIFI_COEX + 0x8) -+#define RG_COEX_HS5W_MANUAL2 (WIFI_COEX + 0xc) -+#define RG_COEX_HS5W_MANUAL3 (WIFI_COEX + 0x10) -+#define RG_COEX_HS5W_MANUAL4 (WIFI_COEX + 0x14) -+ -+#define RG_COEX_HS5W_CTRL0 (WIFI_COEX + 0x18) -+#define RG_COEX_HS5W_CTRL1 (WIFI_COEX + 0x1c) -+ -+#define RG_COEX_RF_STABLE_CTRL (WIFI_COEX + 0x20) -+#define RG_COEX_BT_OWNER_CTRL (WIFI_COEX + 0x24) -+#define RG_COEX_WF_OWNER_CTRL (WIFI_COEX + 0x28) -+ -+#define RG_COEX_BT_LOGIC_INFO (WIFI_COEX + 0x200) -+#define COEX_EN_ESCO (0x00000010) -+#define RG_COEX_CFG1 (WIFI_COEX + 0x19c) -+#define RG_COEX_IRQ_END_TIME (WIFI_COEX + 0x304) -+#define RG_COEX_WF_IRQ_MSK (WIFI_COEX + 0x39c) -+#define RG_COEX_BT_IRQ_MSK (WIFI_COEX + 0x3a0) -+ -+#endif -+ -diff --git a/drivers/net/wireless/w1/common/wifi_i2c_addr.h b/drivers/net/wireless/w1/common/wifi_i2c_addr.h -new file mode 100644 -index 000000000000..54b3762e3b23 ---- /dev/null -+++ b/drivers/net/wireless/w1/common/wifi_i2c_addr.h -@@ -0,0 +1,14 @@ -+#ifndef __WIFI_I2C_ADDR_H__ -+#define __WIFI_I2C_ADDR_H__ -+ -+#define WIFI_I2C (0x4800) -+ -+#define WIFI_I2C_M0_CONTROL_REG (WIFI_I2C + (0x00 << 2)) -+#define WIFI_I2C_M0_SLAVE_ADDR (WIFI_I2C + (0x01 << 2)) -+#define WIFI_I2C_M0_TOKEN_LIST0 (WIFI_I2C + (0x02 << 2)) -+#define WIFI_I2C_M0_TOKEN_LIST1 (WIFI_I2C + (0x03 << 2)) -+#define WIFI_I2C_M0_WDATA_REG0 (WIFI_I2C + (0x04 << 2)) -+#define WIFI_I2C_M0_WDATA_REG1 (WIFI_I2C + (0x05 << 2)) -+#define WIFI_I2C_M0_RDATA_REG0 (WIFI_I2C + (0x06 << 2)) -+ -+#endif -diff --git a/drivers/net/wireless/w1/common/wifi_intf_addr.h b/drivers/net/wireless/w1/common/wifi_intf_addr.h -new file mode 100644 -index 000000000000..7ec21d85f4a1 ---- /dev/null -+++ b/drivers/net/wireless/w1/common/wifi_intf_addr.h -@@ -0,0 +1,26 @@ -+#ifndef __ADDR_INTF_H__ -+#define __ADDR_INTF_H__ -+ -+ -+#define WIFI_INTF (0xd000) -+ -+#define RG_INTF_CTRL_CLK (WIFI_INTF + 0xb0) -+#define RG_INTF_CPU_CLK (WIFI_INTF + 0x090) -+#define RG_INTF_APB_CLK (WIFI_INTF + 0x094) -+#define RG_INTF_MAC_CLK (WIFI_INTF + 0x098) -+#define RG_INTF_DAC_CLK (WIFI_INTF + 0x0a0) -+#define RG_INTF_ADC_CLK (WIFI_INTF + 0x0a4) -+#define RG_INTF_VIT_CLK (WIFI_INTF + 0x0ac) -+#define RG_INTF_11BRX_CLK (WIFI_INTF + 0x0bc) -+#define RG_INTF_320M_CLK (WIFI_INTF + 0x100) -+#define RG_INTF_240M_CLK (WIFI_INTF + 0x104) -+#define RG_INTF_BTCPU_CLK (WIFI_INTF + 0x108) -+#define RG_INTF_BTMAC_CLK (WIFI_INTF + 0x10c) -+#define RG_INTF_LDPC_CLK (WIFI_INTF + 0x118) -+#define RG_INTF_PIN_MUX_REG1 (WIFI_INTF + 0x004) -+#define RG_INTF_SHARE_64K_CAP (WIFI_INTF + 0x0e4) -+#define RG_INTF_PHY_CLK (WIFI_INTF + 0x0a8) -+#define RG_INTF_RTC_CLK_CTRL (WIFI_INTF + 0xc0) -+#define RG_INTF_MAC_TIMER_CTRL1 (WIFI_INTF + 0xd0) -+ -+#endif -diff --git a/drivers/net/wireless/w1/common/wifi_mac_addr.h b/drivers/net/wireless/w1/common/wifi_mac_addr.h -new file mode 100644 -index 000000000000..b3cc16e976da ---- /dev/null -+++ b/drivers/net/wireless/w1/common/wifi_mac_addr.h -@@ -0,0 +1,109 @@ -+#ifndef __WIFI_MAC_ADDR_H__ -+#define __WIFI_MAC_ADDR_H__ -+ -+#define WIFI_MAC (0x0000) -+#define RG_MAC_COUNT1 (WIFI_MAC + 0xb0) -+#define RG_MAC_LOCAL_ADDRL0 (WIFI_MAC+0X1c) -+#define RG_MAC_LOCAL_ADDRH0 (WIFI_MAC+0X20) -+ -+#define RG_MAC_BSSID0LO_REG (WIFI_MAC+0x3c) -+#define RG_MAC_BSSID0HI_REG (WIFI_MAC+0x40) -+ -+#define RG_MAC_COUNT2 (WIFI_MAC+0Xb4) -+#define RG_MAC_CHANNEL_INDEX (WIFI_MAC+0X1e0) -+#define RG_MAC_BSSIDLO_N(_vid) (RG_MAC_BSSID0LO_REG+(_vid)*8) -+#define RG_MAC_BSSIDHI_N(_vid) (RG_MAC_BSSID0HI_REG+(_vid)*8) -+#define RG_MAC_LOCAL_ADDRLN(_vid) (RG_MAC_LOCAL_ADDRL0+(_vid)*8) -+#define RG_MAC_LOCAL_ADDRHN(_vid) (RG_MAC_LOCAL_ADDRH0+(_vid)*8) -+ -+#define RG_MAC_CNT_CTRL_FIQ (WIFI_MAC + 0x5c ) -+#define RG_MAC_FRM_TYPE_CNT_CTRL (WIFI_MAC + 0xa4) -+#define RG_MAC_RX_DATA_LOCAL_CNT (WIFI_MAC + 0x1b8) -+#define RG_MAC_RX_DATA_OTHER_CNT (WIFI_MAC + 0x1bc) -+#define RG_MAC_RX_DATA_MUTIL_CNT (WIFI_MAC + 0x1c0) -+#define RG_MAC_TX_STT_CHK (WIFI_MAC + 0x1a8) -+#define RG_MAC_TX_END_CHK (WIFI_MAC + 0x1ac) -+#define RG_MAC_TX_EN_CHK (WIFI_MAC + 0x1b0) -+#define RG_MAC_TX_ENWR_CHK (WIFI_MAC + 0x1b4) -+ -+#define RG_MAC_IRQ_STATUS_CNT0 (WIFI_MAC + 0x60) -+#define RG_MAC_IRQ_STATUS_CNT1 (WIFI_MAC + 0x64) -+#define RG_MAC_IRQ_STATUS_CNT2 (WIFI_MAC + 0x68) -+#define RG_MAC_IRQ_STATUS_CNT3 (WIFI_MAC + 0x74) -+#define RG_MAC_FRM_TYPE_CNT0 (WIFI_MAC + 0xa8) -+#define RG_MAC_FRM_TYPE_CNT1 (WIFI_MAC + 0xac) -+#define RG_MAC_FRM_TYPE_CNT2 (WIFI_MAC + 0xf4) -+#define RG_MAC_FRM_TYPE_CNT3 (WIFI_MAC + 0xf8) -+#define RG_MAC_BCN_CTRL_REG (WIFI_MAC + 0x234) -+#define RG_MAC_RX_WPTR (WIFI_MAC + 0x1fc) -+#define RG_MAC_RX_FRPTR (WIFI_MAC + 0x200) -+#define RG_MAC_RX_HRPTR (WIFI_MAC + 0x204) -+ -+ -+ -+struct data_rx_local_cnt_bits{ -+ unsigned int data_local_cnt: 29, -+ data_local_cnt_qos:1, -+ data_local_cnt_clr:1, -+ data_local_cnt_en:1; -+}; -+ -+struct data_rx_cnt_bits{ -+ unsigned int cnt:30, -+ clr:1, -+ en:1; -+}; -+ -+ -+struct tx_cnt_ctrl_bits -+{ -+ unsigned int cnt :26, -+ en:1, -+ clr:1, -+ rsv:4; -+}; -+ -+struct cnt_ctrl_bits -+{ -+ unsigned int type_idx0 :6, -+ type_idx1 :6, -+ type_idx2 :6, -+ type_idx3 :6, -+ en0 :1, -+ en1 :1, -+ en2 :1, -+ en3 :1, -+ clr0 :1, -+ clr1 :1, -+ clr2 :1, -+ clr3 :1; -+}; -+ -+ -+struct ctrl_idx{ -+ unsigned char idx0; -+ unsigned char idx1; -+ unsigned char idx2; -+ unsigned char idx3; -+ unsigned char qos_en; -+}; -+ -+union sts_mac_reg_u{ -+ unsigned int x; -+ struct ctrl_idx op_idx; -+ struct tx_cnt_ctrl_bits tx_cnt_ctrl; -+ struct cnt_ctrl_bits cnt_ctrl; -+ struct data_rx_cnt_bits rx_other_cnt; -+ struct data_rx_cnt_bits rx_mutil_cnt; -+ struct data_rx_local_cnt_bits rx_local_cnt; -+}; -+ -+struct sts_irq_ctrl{ -+ unsigned int cnt:29,func_code:3 ; -+}; -+ -+struct sts_sw_cnt_ctrl{ -+ unsigned int cnt:29,func_code:3 ; -+}; -+ -+#endif -diff --git a/drivers/net/wireless/w1/common/wifi_mac_main_reg.h b/drivers/net/wireless/w1/common/wifi_mac_main_reg.h -new file mode 100644 -index 000000000000..94dcb0aef372 ---- /dev/null -+++ b/drivers/net/wireless/w1/common/wifi_mac_main_reg.h -@@ -0,0 +1,1085 @@ -+#ifdef WIFI_MAC_MAIN_REG -+#else -+#define WIFI_MAC_MAIN_REG -+ -+ -+#define WIFI_MAC_MAIN_REG_BASE (0xa00000) -+ -+#define MAC_CONTROL (WIFI_MAC_MAIN_REG_BASE + 0x0) -+// Bit 0 reg_a1mis_abort_en U RW default = 'h0 -+// Bit 1 reg_swirq U RW default = 'h0 -+// Bit 2 reg_sniffer_enable U RW default = 'h0 -+// Bit 3 reg_smpdu_bitmap_update U RW default = 'h0 -+// Bit 4 reg_txstartit_earlymode U RW default = 'h0 -+// Bit 5 reg_ofdm_padding U RW default = 'h1 -+// Bit 6 reg_status_count_enable U RW default = 'h1 -+// Bit 11 reg_frequency_band U RW default = 'h0 -+// Bit 12 reg_tximmstop U RW default = 'h0 -+// Bit 13 reg_endian U RW default = 'h1 -+// Bit 14 reg_cca_rst_req U RW default = 'h0 -+// Bit 15 reg_fiqenable_rdrst U RW default = 'h0 -+// Bit 17 reg_tcpip_offload_on U RW default = 'h1 -+// Bit 18 reg_bws_ta_disable U RW default = 'h1 -+// Bit 19 reg_vht_txtime_sel U RW default = 'h0 -+// Bit 20 reg_qosnull_notupd_bitmap U RW default = 'h0 -+typedef union MAC_CONTROL_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_a1mis_abort_en : 1; -+ unsigned int reg_swirq : 1; -+ unsigned int reg_sniffer_enable : 1; -+ unsigned int reg_smpdu_bitmap_update : 1; -+ unsigned int reg_txstartit_earlymode : 1; -+ unsigned int reg_ofdm_padding : 1; -+ unsigned int reg_status_count_enable : 1; -+ unsigned int rsvd_0 : 4; -+ unsigned int reg_frequency_band : 1; -+ unsigned int reg_tximmstop : 1; -+ unsigned int reg_endian : 1; -+ unsigned int reg_cca_rst_req : 1; -+ unsigned int reg_fiqenable_rdrst : 1; -+ unsigned int rsvd_1 : 1; -+ unsigned int reg_tcpip_offload_on : 1; -+ unsigned int reg_bws_ta_disable : 1; -+ unsigned int reg_vht_txtime_sel : 1; -+ unsigned int reg_qosnull_notupd_bitmap : 1; -+ unsigned int rsvd_2 : 11; -+ } b; -+} MAC_CONTROL_FIELD_T; -+ -+#define MAC_IRQ_MASK (WIFI_MAC_MAIN_REG_BASE + 0x4) -+// Bit 0 reg_txstart_mask U RW default = 'h0 -+// Bit 1 reg_txend_mask U RW default = 'h0 -+// Bit 9 reg_ackto_mask U RW default = 'h0 -+// Bit 11 reg_rxstart_mask U RW default = 'h0 -+// Bit 12 reg_rxend_mask U RW default = 'h0 -+// Bit 31 :16 reg_abscount_mask U RW default = 'h0 -+typedef union MAC_IRQ_MASK_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_txstart_mask : 1; -+ unsigned int reg_txend_mask : 1; -+ unsigned int rsvd_0 : 7; -+ unsigned int reg_ackto_mask : 1; -+ unsigned int rsvd_1 : 1; -+ unsigned int reg_rxstart_mask : 1; -+ unsigned int reg_rxend_mask : 1; -+#ifdef PROJECT_T9026 -+ unsigned int rsvd_2 : 7; -+ unsigned int reg_abscount_mask : 12; -+#else -+ unsigned int rsvd_2 : 3; -+ unsigned int reg_abscount_mask : 16; -+#endif -+ } b; -+} MAC_IRQ_MASK_FIELD_T; -+ -+#define MAC_IRQ_STATUS (WIFI_MAC_MAIN_REG_BASE + 0xc) -+// Bit 0 reg_txstart_it U W1C default = 'h0 -+// Bit 1 reg_txend_it U W1C default = 'h0 -+// Bit 3 :2 ro_txvmac_id U RO default = 'h0 -+// Bit 7 :4 ro_txstart_queue U RO default = 'h0 -+// Bit 8 ro_txenderr U RO default = 'h0 -+// Bit 9 reg_ackto_it U W1C default = 'h0 -+// Bit 10 ro_txcol_flag U RO default = 'h0 -+// Bit 11 reg_rxstart_it U W1C default = 'h0 -+// Bit 12 reg_rxend_it U W1C default = 'h0 -+// Bit 13 ro_rxmpdu_ok U RO default = 'h0 -+// Bit 14 ro_unicast U RO default = 'h0 -+// Bit 15 ro_a1match U RO default = 'h0 -+// Bit 16 ro_bssidmatch U RO default = 'h0 -+// Bit 18 ro_srambuf_full1 U RO default = 'h0 -+// Bit 19 reg_swirq_it U W1C default = 'h0 -+// Bit 25 :20 reg_tx_frame_type U RW default = 'h0 -+// Bit 30 reg_abscount_intr U W1C default = 'h0 -+// Bit 31 reg_fiq_enable U RW default = 'h0 -+typedef union MAC_IRQ_STATUS_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_txstart_it : 1; -+ unsigned int reg_txend_it : 1; -+ unsigned int ro_txvmac_id : 2; -+ unsigned int ro_txstart_queue : 4; -+ unsigned int ro_txenderr : 1; -+ unsigned int reg_ackto_it : 1; -+ unsigned int ro_txcol_flag : 1; -+ unsigned int reg_rxstart_it : 1; -+ unsigned int reg_rxend_it : 1; -+ unsigned int ro_rxmpdu_ok : 1; -+ unsigned int ro_unicast : 1; -+ unsigned int ro_a1match : 1; -+ unsigned int ro_bssidmatch : 1; -+ unsigned int rsvd_0 : 1; -+ unsigned int ro_srambuf_full1 : 1; -+ unsigned int reg_swirq_it : 1; -+ unsigned int reg_tx_frame_type : 6; -+ unsigned int rsvd_1 : 4; -+ unsigned int reg_abscount_intr : 1; -+ unsigned int reg_fiq_enable : 1; -+ } b; -+} MAC_IRQ_STATUS_FIELD_T; -+ -+#define MAC_ERR_STATUS (WIFI_MAC_MAIN_REG_BASE + 0x10) -+// Bit 0 ro_fiac_fw_timeout_err U RO default = 'h0 -+// Bit 1 ro_hw_timeout_err U RO default = 'h0 -+// Bit 2 ro_tx_wd_timeout_err U RO default = 'h0 -+// Bit 3 ro_txinvalidlen_err U RO default = 'h0 -+// Bit 4 ro_tx_keymiss U RO default = 'h0 -+// Bit 5 ro_tximmstop_err U RO default = 'h0 -+// Bit 9 :6 ro_tx_phyerror U RO default = 'h0 -+// Bit 18 :10 ro_txcol_queue U RO default = 'h0 -+// Bit 19 ro_tx_not_grant U RO default = 'h0 -+// Bit 22 ro_srambuf_full2 U RO default = 'h0 -+// Bit 23 ro_fcserr U RO default = 'h0 -+// Bit 24 ro_rxfifoov U RO default = 'h0 -+// Bit 25 ro_rx_wd_timeout_err U RO default = 'h0 -+// Bit 26 ro_short_length U RO default = 'h0 -+// Bit 27 ro_length_error U RO default = 'h0 -+// Bit 31 :28 ro_rx_phyerror U RO default = 'h0 -+typedef union MAC_ERR_STATUS_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_fiac_fw_timeout_err : 1; -+ unsigned int ro_hw_timeout_err : 1; -+ unsigned int ro_tx_wd_timeout_err : 1; -+ unsigned int ro_txinvalidlen_err : 1; -+ unsigned int ro_tx_keymiss : 1; -+ unsigned int ro_tximmstop_err : 1; -+ unsigned int ro_tx_phyerror : 4; -+ unsigned int ro_txcol_queue : 9; -+ unsigned int ro_tx_not_grant : 1; -+ unsigned int rsvd_0 : 2; -+ unsigned int ro_srambuf_full2 : 1; -+ unsigned int ro_fcserr : 1; -+ unsigned int ro_rxfifoov : 1; -+ unsigned int ro_rx_wd_timeout_err : 1; -+ unsigned int ro_short_length : 1; -+ unsigned int ro_length_error : 1; -+ unsigned int ro_rx_phyerror : 4; -+ } b; -+} MAC_ERR_STATUS_FIELD_T; -+ -+#define ABS_STATUS (WIFI_MAC_MAIN_REG_BASE + 0x14) -+// Bit 16 reg_mac_absstatus0 U W1C default = 'h0 -+// Bit 17 reg_mac_absstatus1 U W1C default = 'h0 -+// Bit 18 reg_mac_absstatus2 U W1C default = 'h0 -+// Bit 19 reg_mac_absstatus3 U W1C default = 'h0 -+// Bit 20 reg_mac_absstatus4 U W1C default = 'h0 -+// Bit 21 reg_mac_absstatus5 U W1C default = 'h0 -+// Bit 22 reg_mac_absstatus6 U W1C default = 'h0 -+// Bit 23 reg_mac_absstatus7 U W1C default = 'h0 -+// Bit 24 reg_mac_absstatus8 U W1C default = 'h0 -+// Bit 25 reg_mac_absstatus9 U W1C default = 'h0 -+// Bit 26 reg_mac_absstatus10 U W1C default = 'h0 -+// Bit 27 reg_mac_absstatus11 U W1C default = 'h0 -+// Bit 28 reg_mac_absstatus12 U W1C default = 'h0 -+// Bit 29 reg_mac_absstatus13 U W1C default = 'h0 -+// Bit 30 reg_mac_absstatus14 U W1C default = 'h0 -+// Bit 31 reg_mac_absstatus15 U W1C default = 'h0 -+typedef union ABS_STATUS_FIELD -+{ -+ unsigned int data; -+#ifdef PROJECT_T9026 -+ struct -+ { -+ unsigned int rsvd_0 : 20; -+ unsigned int reg_mac_absstatus0 : 1; -+ unsigned int reg_mac_absstatus1 : 1; -+ unsigned int reg_mac_absstatus2 : 1; -+ unsigned int reg_mac_absstatus3 : 1; -+ unsigned int reg_mac_absstatus4 : 1; -+ unsigned int reg_mac_absstatus5 : 1; -+ unsigned int reg_mac_absstatus6 : 1; -+ unsigned int reg_mac_absstatus7 : 1; -+ unsigned int reg_mac_absstatus8 : 1; -+ unsigned int reg_mac_absstatus9 : 1; -+ unsigned int reg_mac_absstatus10 : 1; -+ unsigned int reg_mac_absstatus11 : 1; -+ } b; -+#else -+ struct -+ { -+ unsigned int rsvd_0 : 16; -+ unsigned int reg_mac_absstatus0 : 1; -+ unsigned int reg_mac_absstatus1 : 1; -+ unsigned int reg_mac_absstatus2 : 1; -+ unsigned int reg_mac_absstatus3 : 1; -+ unsigned int reg_mac_absstatus4 : 1; -+ unsigned int reg_mac_absstatus5 : 1; -+ unsigned int reg_mac_absstatus6 : 1; -+ unsigned int reg_mac_absstatus7 : 1; -+ unsigned int reg_mac_absstatus8 : 1; -+ unsigned int reg_mac_absstatus9 : 1; -+ unsigned int reg_mac_absstatus10 : 1; -+ unsigned int reg_mac_absstatus11 : 1; -+ unsigned int reg_mac_absstatus12 : 1; -+ unsigned int reg_mac_absstatus13 : 1; -+ unsigned int reg_mac_absstatus14 : 1; -+ unsigned int reg_mac_absstatus15 : 1; -+ } b; -+#endif -+} ABS_STATUS_FIELD_T; -+ -+#define MAC_LOCAL_ADDRLO0 (WIFI_MAC_MAIN_REG_BASE + 0x1c) -+// Bit 31 :0 reg_mac_local_addrlo0 U RW default = 'h1279ffff -+typedef union MAC_LOCAL_ADDRLO0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_local_addrlo0 : 32; -+ } b; -+} MAC_LOCAL_ADDRLO0_FIELD_T; -+ -+#define MAC_LOCAL_ADDRHI0 (WIFI_MAC_MAIN_REG_BASE + 0x20) -+// Bit 15 :0 reg_mac_local_addrhi0 U RW default = 'h5634 -+typedef union MAC_LOCAL_ADDRHI0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_local_addrhi0 : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} MAC_LOCAL_ADDRHI0_FIELD_T; -+ -+#define MAC_LOCAL_ADDRLO1 (WIFI_MAC_MAIN_REG_BASE + 0x24) -+// Bit 31 :0 reg_mac_local_addrlo1 U RW default = 'h1279ffff -+typedef union MAC_LOCAL_ADDRLO1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_local_addrlo1 : 32; -+ } b; -+} MAC_LOCAL_ADDRLO1_FIELD_T; -+ -+#define MAC_LOCAL_ADDRHI1 (WIFI_MAC_MAIN_REG_BASE + 0x28) -+// Bit 15 :0 reg_mac_local_addrhi1 U RW default = 'h5634 -+typedef union MAC_LOCAL_ADDRHI1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_local_addrhi1 : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} MAC_LOCAL_ADDRHI1_FIELD_T; -+ -+#define MAC_LOCAL_ADDRLO2 (WIFI_MAC_MAIN_REG_BASE + 0x2c) -+// Bit 31 :0 reg_mac_local_addrlo2 U RW default = 'h1279ffff -+typedef union MAC_LOCAL_ADDRLO2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_local_addrlo2 : 32; -+ } b; -+} MAC_LOCAL_ADDRLO2_FIELD_T; -+ -+#define MAC_LOCAL_ADDRHI2 (WIFI_MAC_MAIN_REG_BASE + 0x30) -+// Bit 15 :0 reg_mac_local_addrhi2 U RW default = 'h5634 -+typedef union MAC_LOCAL_ADDRHI2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_local_addrhi2 : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} MAC_LOCAL_ADDRHI2_FIELD_T; -+ -+#define MAC_LOCAL_ADDRLO3 (WIFI_MAC_MAIN_REG_BASE + 0x34) -+// Bit 31 :0 reg_mac_local_addrlo3 U RW default = 'h1279ffff -+typedef union MAC_LOCAL_ADDRLO3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_local_addrlo3 : 32; -+ } b; -+} MAC_LOCAL_ADDRLO3_FIELD_T; -+ -+#define MAC_LOCAL_ADDRHI3 (WIFI_MAC_MAIN_REG_BASE + 0x38) -+// Bit 15 :0 reg_mac_local_addrhi3 U RW default = 'h5634 -+typedef union MAC_LOCAL_ADDRHI3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_local_addrhi3 : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} MAC_LOCAL_ADDRHI3_FIELD_T; -+ -+#define MAC_LOCAL_BSSIDLO0 (WIFI_MAC_MAIN_REG_BASE + 0x3c) -+// Bit 31 :0 reg_mac_local_bssidlo0 U RW default = 'h0 -+typedef union MAC_LOCAL_BSSIDLO0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_local_bssidlo0 : 32; -+ } b; -+} MAC_LOCAL_BSSIDLO0_FIELD_T; -+ -+#define MAC_LOCAL_BSSIDHI0 (WIFI_MAC_MAIN_REG_BASE + 0x40) -+// Bit 15 :0 reg_mac_local_bssidhi0 U RW default = 'h0 -+typedef union MAC_LOCAL_BSSIDHI0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_local_bssidhi0 : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} MAC_LOCAL_BSSIDHI0_FIELD_T; -+ -+#define MAC_LOCAL_BSSIDLO1 (WIFI_MAC_MAIN_REG_BASE + 0x44) -+// Bit 31 :0 reg_mac_local_bssidlo1 U RW default = 'h0 -+typedef union MAC_LOCAL_BSSIDLO1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_local_bssidlo1 : 32; -+ } b; -+} MAC_LOCAL_BSSIDLO1_FIELD_T; -+ -+#define MAC_LOCAL_BSSIDHI1 (WIFI_MAC_MAIN_REG_BASE + 0x48) -+// Bit 15 :0 reg_mac_local_bssidhi1 U RW default = 'h0 -+typedef union MAC_LOCAL_BSSIDHI1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_local_bssidhi1 : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} MAC_LOCAL_BSSIDHI1_FIELD_T; -+ -+#define MAC_LOCAL_BSSIDLO2 (WIFI_MAC_MAIN_REG_BASE + 0x4c) -+// Bit 31 :0 reg_mac_local_bssidlo2 U RW default = 'h0 -+typedef union MAC_LOCAL_BSSIDLO2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_local_bssidlo2 : 32; -+ } b; -+} MAC_LOCAL_BSSIDLO2_FIELD_T; -+ -+#define MAC_LOCAL_BSSIDHI2 (WIFI_MAC_MAIN_REG_BASE + 0x50) -+// Bit 15 :0 reg_mac_local_bssidhi2 U RW default = 'h0 -+typedef union MAC_LOCAL_BSSIDHI2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_local_bssidhi2 : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} MAC_LOCAL_BSSIDHI2_FIELD_T; -+ -+#define MAC_LOCAL_BSSIDLO3 (WIFI_MAC_MAIN_REG_BASE + 0x54) -+// Bit 31 :0 reg_mac_local_bssidlo3 U RW default = 'h0 -+typedef union MAC_LOCAL_BSSIDLO3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_local_bssidlo3 : 32; -+ } b; -+} MAC_LOCAL_BSSIDLO3_FIELD_T; -+ -+#define MAC_LOCAL_BSSIDHI3 (WIFI_MAC_MAIN_REG_BASE + 0x58) -+// Bit 15 :0 reg_mac_local_bssidhi3 U RW default = 'h0 -+typedef union MAC_LOCAL_BSSIDHI3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_local_bssidhi3 : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} MAC_LOCAL_BSSIDHI3_FIELD_T; -+ -+#define STATUS_CNT_CTRL_IRQ (WIFI_MAC_MAIN_REG_BASE + 0x5c) -+// Bit 5 :0 reg_fiq_status_cnt_idx0 U RW default = 'h0 -+// Bit 11 :6 reg_fiq_status_cnt_idx1 U RW default = 'h1 -+// Bit 17 :12 reg_fiq_status_cnt_idx2 U RW default = 'h9 -+// Bit 23 :18 reg_fiq_status_cnt_idx3 U RW default = 'h13 -+// Bit 24 reg_fiq_status_cnt_en0 U RW default = 'h1 -+// Bit 25 reg_fiq_status_cnt_en1 U RW default = 'h1 -+// Bit 26 reg_fiq_status_cnt_en2 U RW default = 'h1 -+// Bit 27 reg_fiq_status_cnt_en3 U RW default = 'h0 -+// Bit 28 reg_fiq_status_cnt_clr0 U RW default = 'h0 -+// Bit 29 reg_fiq_status_cnt_clr1 U RW default = 'h0 -+// Bit 30 reg_fiq_status_cnt_clr2 U RW default = 'h0 -+// Bit 31 reg_fiq_status_cnt_clr3 U RW default = 'h0 -+typedef union STATUS_CNT_CTRL_IRQ_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_fiq_status_cnt_idx0 : 6; -+ unsigned int reg_fiq_status_cnt_idx1 : 6; -+ unsigned int reg_fiq_status_cnt_idx2 : 6; -+ unsigned int reg_fiq_status_cnt_idx3 : 6; -+ unsigned int reg_fiq_status_cnt_en0 : 1; -+ unsigned int reg_fiq_status_cnt_en1 : 1; -+ unsigned int reg_fiq_status_cnt_en2 : 1; -+ unsigned int reg_fiq_status_cnt_en3 : 1; -+ unsigned int reg_fiq_status_cnt_clr0 : 1; -+ unsigned int reg_fiq_status_cnt_clr1 : 1; -+ unsigned int reg_fiq_status_cnt_clr2 : 1; -+ unsigned int reg_fiq_status_cnt_clr3 : 1; -+ } b; -+} STATUS_CNT_CTRL_IRQ_FIELD_T; -+ -+#define IRQ_STATUS_CNT0 (WIFI_MAC_MAIN_REG_BASE + 0x60) -+// Bit 31 :0 ro_fiq_status_cnt0 U RO default = 'h0 -+typedef union IRQ_STATUS_CNT0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_fiq_status_cnt0 : 32; -+ } b; -+} IRQ_STATUS_CNT0_FIELD_T; -+ -+#define IRQ_STATUS_CNT1 (WIFI_MAC_MAIN_REG_BASE + 0x64) -+// Bit 31 :0 ro_fiq_status_cnt1 U RO default = 'h0 -+typedef union IRQ_STATUS_CNT1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_fiq_status_cnt1 : 32; -+ } b; -+} IRQ_STATUS_CNT1_FIELD_T; -+ -+#define IRQ_STATUS_CNT2 (WIFI_MAC_MAIN_REG_BASE + 0x68) -+// Bit 31 :0 ro_fiq_status_cnt2 U RO default = 'h0 -+typedef union IRQ_STATUS_CNT2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_fiq_status_cnt2 : 32; -+ } b; -+} IRQ_STATUS_CNT2_FIELD_T; -+ -+#define MAC_CLKJIC0 (WIFI_MAC_MAIN_REG_BASE + 0x6c) -+// Bit 7 :0 reg_rx_clk_jic U RW default = 'hff -+// Bit 15 :8 reg_tx_clk_jic U RW default = 'hff -+// Bit 23 :16 reg_timer_clk_jic U RW default = 'hff -+// Bit 31 :24 reg_reg_clk_jic U RW default = 'hff -+typedef union MAC_CLKJIC0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_rx_clk_jic : 8; -+ unsigned int reg_tx_clk_jic : 8; -+ unsigned int reg_timer_clk_jic : 8; -+ unsigned int reg_reg_clk_jic : 8; -+ } b; -+} MAC_CLKJIC0_FIELD_T; -+ -+#define MAC_CLKJIC1 (WIFI_MAC_MAIN_REG_BASE + 0x70) -+// Bit 11 :0 reg_dp_clk_jic U RW default = 'hfff -+// Bit 21 :16 reg_ahb_clk_jic U RW default = 'h3f -+typedef union MAC_CLKJIC1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_dp_clk_jic : 12; -+ unsigned int rsvd_0 : 4; -+ unsigned int reg_ahb_clk_jic : 6; -+ unsigned int rsvd_1 : 10; -+ } b; -+} MAC_CLKJIC1_FIELD_T; -+ -+#define IRQ_STATUS_CNT3 (WIFI_MAC_MAIN_REG_BASE + 0x74) -+// Bit 31 :0 ro_fiq_status_cnt3 U RO default = 'h0 -+typedef union IRQ_STATUS_CNT3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_fiq_status_cnt3 : 32; -+ } b; -+} IRQ_STATUS_CNT3_FIELD_T; -+ -+#define MAC_DEBUG0 (WIFI_MAC_MAIN_REG_BASE + 0x78) -+// Bit 31 :0 reg_mac_debug0 U RW default = 'h0 -+typedef union MAC_DEBUG0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_debug0 : 32; -+ } b; -+} MAC_DEBUG0_FIELD_T; -+ -+#define MAC_DEBUG1 (WIFI_MAC_MAIN_REG_BASE + 0x7c) -+// Bit 31 :0 reg_mac_debug1 U RW default = 'h0 -+typedef union MAC_DEBUG1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_debug1 : 32; -+ } b; -+} MAC_DEBUG1_FIELD_T; -+ -+#define MAC_DEBUG2 (WIFI_MAC_MAIN_REG_BASE + 0x80) -+// Bit 31 :0 reg_mac_debug2 U RW default = 'h0 -+typedef union MAC_DEBUG2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_debug2 : 32; -+ } b; -+} MAC_DEBUG2_FIELD_T; -+ -+#define MAC_DEBUG3 (WIFI_MAC_MAIN_REG_BASE + 0x84) -+// Bit 31 :0 reg_mac_debug3 U RW default = 'h0 -+typedef union MAC_DEBUG3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_debug3 : 32; -+ } b; -+} MAC_DEBUG3_FIELD_T; -+ -+#define MAC_FIACMAXDEL (WIFI_MAC_MAIN_REG_BASE + 0x88) -+// Bit 6 :0 reg_txvector_hw_maxdel U RW default = 'h3e -+// Bit 12 :8 reg_fiac_maxdela U RW default = 'h18 -+// Bit 20 :16 reg_fiac_maxdelb U RW default = 'h10 -+typedef union MAC_FIACMAXDEL_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_txvector_hw_maxdel : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int reg_fiac_maxdela : 5; -+ unsigned int rsvd_1 : 3; -+ unsigned int reg_fiac_maxdelb : 5; -+ unsigned int rsvd_2 : 11; -+ } b; -+} MAC_FIACMAXDEL_FIELD_T; -+ -+#define DEVICE0_MODE (WIFI_MAC_MAIN_REG_BASE + 0x90) -+// Bit 31 :0 reg_device0_mode U RW default = 'h0 -+typedef union DEVICE0_MODE_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_device0_mode : 32; -+ } b; -+} DEVICE0_MODE_FIELD_T; -+ -+#define DEVICE1_MODE (WIFI_MAC_MAIN_REG_BASE + 0x94) -+// Bit 31 :0 reg_device1_mode U RW default = 'h0 -+typedef union DEVICE1_MODE_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_device1_mode : 32; -+ } b; -+} DEVICE1_MODE_FIELD_T; -+ -+#define DEVICE2_MODE (WIFI_MAC_MAIN_REG_BASE + 0x98) -+// Bit 31 :0 reg_device2_mode U RW default = 'h0 -+typedef union DEVICE2_MODE_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_device2_mode : 32; -+ } b; -+} DEVICE2_MODE_FIELD_T; -+ -+#define DEVICE3_MODE (WIFI_MAC_MAIN_REG_BASE + 0x9c) -+// Bit 31 :0 reg_device3_mode U RW default = 'h0 -+typedef union DEVICE3_MODE_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_device3_mode : 32; -+ } b; -+} DEVICE3_MODE_FIELD_T; -+ -+#define MAC_INTNUM (WIFI_MAC_MAIN_REG_BASE + 0xa0) -+// Bit 15 :0 reg_rxend_cnt U RW default = 'h0 -+// Bit 31 :16 reg_rxstart_cnt U RW default = 'h0 -+typedef union MAC_INTNUM_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_rxend_cnt : 16; -+ unsigned int reg_rxstart_cnt : 16; -+ } b; -+} MAC_INTNUM_FIELD_T; -+ -+#define FRAME_TYPE_CNT_CTRL (WIFI_MAC_MAIN_REG_BASE + 0xa4) -+// Bit 5 :0 reg_frame_type_idx0 U RW default = 'h1b -+// Bit 11 :6 reg_frame_type_idx1 U RW default = 'h1c -+// Bit 17 :12 reg_frame_type_idx2 U RW default = 'h1d -+// Bit 23 :18 reg_frame_type_idx3 U RW default = 'h28 -+// Bit 24 reg_frame_cnt_en0 U RW default = 'h1 -+// Bit 25 reg_frame_cnt_en1 U RW default = 'h1 -+// Bit 26 reg_frame_cnt_en2 U RW default = 'h1 -+// Bit 27 reg_frame_cnt_en3 U RW default = 'h1 -+// Bit 28 reg_frame_cnt_clr0 U RW default = 'h0 -+// Bit 29 reg_frame_cnt_clr1 U RW default = 'h0 -+// Bit 30 reg_frame_cnt_clr2 U RW default = 'h0 -+// Bit 31 reg_frame_cnt_clr3 U RW default = 'h0 -+typedef union FRAME_TYPE_CNT_CTRL_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_frame_type_idx0 : 6; -+ unsigned int reg_frame_type_idx1 : 6; -+ unsigned int reg_frame_type_idx2 : 6; -+ unsigned int reg_frame_type_idx3 : 6; -+ unsigned int reg_frame_cnt_en0 : 1; -+ unsigned int reg_frame_cnt_en1 : 1; -+ unsigned int reg_frame_cnt_en2 : 1; -+ unsigned int reg_frame_cnt_en3 : 1; -+ unsigned int reg_frame_cnt_clr0 : 1; -+ unsigned int reg_frame_cnt_clr1 : 1; -+ unsigned int reg_frame_cnt_clr2 : 1; -+ unsigned int reg_frame_cnt_clr3 : 1; -+ } b; -+} FRAME_TYPE_CNT_CTRL_FIELD_T; -+ -+#define FRAM_TYPE_CNT0 (WIFI_MAC_MAIN_REG_BASE + 0xa8) -+// Bit 31 :0 ro_frame_cnt0 U RO default = 'h0 -+typedef union FRAM_TYPE_CNT0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_frame_cnt0 : 32; -+ } b; -+} FRAM_TYPE_CNT0_FIELD_T; -+ -+#define FRAM_TYPE_CNT1 (WIFI_MAC_MAIN_REG_BASE + 0xac) -+// Bit 31 :0 ro_frame_cnt1 U RO default = 'h0 -+typedef union FRAM_TYPE_CNT1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_frame_cnt1 : 32; -+ } b; -+} FRAM_TYPE_CNT1_FIELD_T; -+ -+#define FRAM_TYPE_CNT2 (WIFI_MAC_MAIN_REG_BASE + 0xf4) -+// Bit 31 :0 ro_frame_cnt2 U RO default = 'h0 -+typedef union FRAM_TYPE_CNT2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_frame_cnt2 : 32; -+ } b; -+} FRAM_TYPE_CNT2_FIELD_T; -+ -+#define FRAM_TYPE_CNT3 (WIFI_MAC_MAIN_REG_BASE + 0xf8) -+// Bit 31 :0 ro_frame_cnt3 U RO default = 'h0 -+typedef union FRAM_TYPE_CNT3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_frame_cnt3 : 32; -+ } b; -+} FRAM_TYPE_CNT3_FIELD_T; -+ -+#define PACKET_IFS_US (WIFI_MAC_MAIN_REG_BASE + 0x124) -+// Bit 7 :0 reg_dot11n_sifs_us U RW default = 'ha -+// Bit 15 :8 reg_dot11b_sifs_us U RW default = 'ha -+// Bit 19 :16 reg_rifs_us U RW default = 'h2 -+// Bit 23 :20 reg_signal_extension_us U RW default = 'h6 -+// Bit 31 :24 reg_packet_ifs_rsvd U RW default = 'h0 -+typedef union PACKET_IFS_US_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_dot11n_sifs_us : 8; -+ unsigned int reg_dot11b_sifs_us : 8; -+ unsigned int reg_rifs_us : 4; -+ unsigned int reg_signal_extension_us : 4; -+ unsigned int reg_packet_ifs_rsvd : 8; -+ } b; -+} PACKET_IFS_US_FIELD_T; -+ -+#define CTRL_FRAME_MASK (WIFI_MAC_MAIN_REG_BASE + 0x138) -+// Bit 3 :0 reg_tx_control_frame_mask U RW default = 'h0 -+typedef union CTRL_FRAME_MASK_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_tx_control_frame_mask : 4; -+ unsigned int rsvd_0 : 28; -+ } b; -+} CTRL_FRAME_MASK_FIELD_T; -+ -+#define MAC_KEYINFO0 (WIFI_MAC_MAIN_REG_BASE + 0x140) -+// Bit 3 :0 reg_unicast_cipher_type0 U RW default = 'h0 -+// Bit 7 :4 reg_multicast_cipher_type0 U RW default = 'h0 -+// Bit 8 reg_multicast_key_lock0 U RW default = 'h0 -+// Bit 19 :16 reg_unicast_cipher_type1 U RW default = 'h0 -+// Bit 23 :20 reg_multicast_cipher_type1 U RW default = 'h0 -+// Bit 24 reg_multicast_key_lock1 U RW default = 'h0 -+typedef union MAC_KEYINFO0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_unicast_cipher_type0 : 4; -+ unsigned int reg_multicast_cipher_type0 : 4; -+ unsigned int reg_multicast_key_lock0 : 1; -+ unsigned int rsvd_0 : 7; -+ unsigned int reg_unicast_cipher_type1 : 4; -+ unsigned int reg_multicast_cipher_type1 : 4; -+ unsigned int reg_multicast_key_lock1 : 1; -+ unsigned int rsvd_1 : 7; -+ } b; -+} MAC_KEYINFO0_FIELD_T; -+ -+#define MAC_KEYINFO1 (WIFI_MAC_MAIN_REG_BASE + 0x144) -+// Bit 3 :0 reg_unicast_cipher_type2 U RW default = 'h0 -+// Bit 7 :4 reg_multicast_cipher_type2 U RW default = 'h0 -+// Bit 8 reg_multicast_key_lock2 U RW default = 'h0 -+// Bit 19 :16 reg_unicast_cipher_type3 U RW default = 'h0 -+// Bit 23 :20 reg_multicast_cipher_type3 U RW default = 'h0 -+// Bit 24 reg_multicast_key_lock3 U RW default = 'h0 -+typedef union MAC_KEYINFO1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_unicast_cipher_type2 : 4; -+ unsigned int reg_multicast_cipher_type2 : 4; -+ unsigned int reg_multicast_key_lock2 : 1; -+ unsigned int rsvd_0 : 7; -+ unsigned int reg_unicast_cipher_type3 : 4; -+ unsigned int reg_multicast_cipher_type3 : 4; -+ unsigned int reg_multicast_key_lock3 : 1; -+ unsigned int rsvd_1 : 7; -+ } b; -+} MAC_KEYINFO1_FIELD_T; -+ -+#define MAC_KEYTABLE_CMD (WIFI_MAC_MAIN_REG_BASE + 0x148) -+// Bit 11 :0 reg_keytable_cmd_addr U RW default = 'h0 -+// Bit 15 :12 reg_keytable_cmd_cipher_type U RW default = 'h0 -+// Bit 18 :16 reg_keytable_cmd_type U RW default = 'h0 -+// Bit 19 reg_keytable_cmd_multikey_sel U RW default = 'h0 -+// Bit 27 :20 reg_keytable_cmd_stationid U RW default = 'h0 -+// Bit 29 :28 ro_keytable_cmd_fail U RO default = 'h0 -+// Bit 30 reg_keytable_cmd_en U RW default = 'h0 -+// Bit 31 reg_keytable_cmd_ready U RW default = 'h1 -+typedef union MAC_KEYTABLE_CMD_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_keytable_cmd_addr : 12; -+ unsigned int reg_keytable_cmd_cipher_type : 4; -+ unsigned int reg_keytable_cmd_type : 3; -+ unsigned int reg_keytable_cmd_multikey_sel : 1; -+ unsigned int reg_keytable_cmd_stationid : 8; -+ unsigned int ro_keytable_cmd_fail : 2; -+ unsigned int reg_keytable_cmd_en : 1; -+ unsigned int reg_keytable_cmd_ready : 1; -+ } b; -+} MAC_KEYTABLE_CMD_FIELD_T; -+ -+#define MAC_KEYTABLE_DATA (WIFI_MAC_MAIN_REG_BASE + 0x14c) -+// Bit 31 :0 reg_mac_keytable_data U RW default = 'h0 -+typedef union MAC_KEYTABLE_DATA_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_keytable_data : 32; -+ } b; -+} MAC_KEYTABLE_DATA_FIELD_T; -+ -+#define MAC_KEYTABLE_DATA2 (WIFI_MAC_MAIN_REG_BASE + 0x150) -+// Bit 31 :0 reg_mac_keytable_data2 U RW default = 'h0 -+typedef union MAC_KEYTABLE_DATA2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_keytable_data2 : 32; -+ } b; -+} MAC_KEYTABLE_DATA2_FIELD_T; -+ -+#define MAC_KEYTABLE_DATA3 (WIFI_MAC_MAIN_REG_BASE + 0x154) -+// Bit 31 :0 reg_mac_keytable_data3 U RW default = 'h0 -+typedef union MAC_KEYTABLE_DATA3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_keytable_data3 : 32; -+ } b; -+} MAC_KEYTABLE_DATA3_FIELD_T; -+ -+#define MAC_KEYTABLE_DATA4 (WIFI_MAC_MAIN_REG_BASE + 0x158) -+// Bit 31 :0 reg_mac_keytable_data4 U RW default = 'h0 -+typedef union MAC_KEYTABLE_DATA4_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_keytable_data4 : 32; -+ } b; -+} MAC_KEYTABLE_DATA4_FIELD_T; -+ -+#define MAC_KEYTABLE_DATA5 (WIFI_MAC_MAIN_REG_BASE + 0x15c) -+// Bit 31 :0 reg_mac_keytable_data5 U RW default = 'h0 -+typedef union MAC_KEYTABLE_DATA5_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_keytable_data5 : 32; -+ } b; -+} MAC_KEYTABLE_DATA5_FIELD_T; -+ -+#define MAC_KEYTABLE_DATA6 (WIFI_MAC_MAIN_REG_BASE + 0x160) -+// Bit 31 :0 reg_mac_keytable_data6 U RW default = 'h0 -+typedef union MAC_KEYTABLE_DATA6_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_keytable_data6 : 32; -+ } b; -+} MAC_KEYTABLE_DATA6_FIELD_T; -+ -+#define MAC_KEYTABLE_DATA7 (WIFI_MAC_MAIN_REG_BASE + 0x164) -+// Bit 31 :0 reg_mac_keytable_data7 U RW default = 'h0 -+typedef union MAC_KEYTABLE_DATA7_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_keytable_data7 : 32; -+ } b; -+} MAC_KEYTABLE_DATA7_FIELD_T; -+ -+#define MAC_KEYTABLE_DATA8 (WIFI_MAC_MAIN_REG_BASE + 0x168) -+// Bit 31 :0 reg_mac_keytable_data8 U RW default = 'h0 -+typedef union MAC_KEYTABLE_DATA8_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_keytable_data8 : 32; -+ } b; -+} MAC_KEYTABLE_DATA8_FIELD_T; -+ -+#define MAC_KEYTABLE_DATA9 (WIFI_MAC_MAIN_REG_BASE + 0x16c) -+// Bit 31 :0 reg_mac_keytable_data9 U RW default = 'h0 -+typedef union MAC_KEYTABLE_DATA9_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_keytable_data9 : 32; -+ } b; -+} MAC_KEYTABLE_DATA9_FIELD_T; -+ -+#define MAC_KEYTABLE_DATA10 (WIFI_MAC_MAIN_REG_BASE + 0x170) -+// Bit 31 :0 reg_mac_keytable_data10 U RW default = 'h0 -+typedef union MAC_KEYTABLE_DATA10_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_keytable_data10 : 32; -+ } b; -+} MAC_KEYTABLE_DATA10_FIELD_T; -+ -+#define MAC_KEYTABLE_DATA11 (WIFI_MAC_MAIN_REG_BASE + 0x174) -+// Bit 31 :0 reg_mac_keytable_data11 U RW default = 'h0 -+typedef union MAC_KEYTABLE_DATA11_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_keytable_data11 : 32; -+ } b; -+} MAC_KEYTABLE_DATA11_FIELD_T; -+ -+#define MAC_KEYMAP (WIFI_MAC_MAIN_REG_BASE + 0x178) -+// Bit 7 :0 reg_keytable_offset0 U RW default = 'h0 -+// Bit 15 :8 reg_keytable_offset1 U RW default = 'h0 -+// Bit 23 :16 reg_keytable_offset2 U RW default = 'h0 -+// Bit 31 :24 reg_keytable_offset3 U RW default = 'h0 -+typedef union MAC_KEYMAP_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_keytable_offset0 : 8; -+ unsigned int reg_keytable_offset1 : 8; -+ unsigned int reg_keytable_offset2 : 8; -+ unsigned int reg_keytable_offset3 : 8; -+ } b; -+} MAC_KEYMAP_FIELD_T; -+ -+#define MAC_DBG_STATUS1 (WIFI_MAC_MAIN_REG_BASE + 0x190) -+// Bit 4 :0 ro_key_err_type U RO default = 'h0 -+typedef union MAC_DBG_STATUS1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_key_err_type : 5; -+ unsigned int rsvd_0 : 27; -+ } b; -+} MAC_DBG_STATUS1_FIELD_T; -+ -+#define TX_START_CHK (WIFI_MAC_MAIN_REG_BASE + 0x1a8) -+// Bit 25 :0 ro_txstart_cnt U RO default = 'h0 -+// Bit 26 reg_txstart_cnt_en U RW default = 'h0 -+// Bit 27 reg_txstart_cnt_clr U RW default = 'h1 -+// Bit 31 :28 reg_check_tx_queue U RW default = 'h9 -+typedef union TX_START_CHK_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txstart_cnt : 26; -+ unsigned int reg_txstart_cnt_en : 1; -+ unsigned int reg_txstart_cnt_clr : 1; -+ unsigned int reg_check_tx_queue : 4; -+ } b; -+} TX_START_CHK_FIELD_T; -+ -+#define TX_END_CHK (WIFI_MAC_MAIN_REG_BASE + 0x1ac) -+// Bit 25 :0 ro_txend_cnt U RO default = 'h0 -+// Bit 26 reg_txend_cnt_en U RW default = 'h0 -+// Bit 27 reg_txend_cnt_clr U RW default = 'h1 -+typedef union TX_END_CHK_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txend_cnt : 26; -+ unsigned int reg_txend_cnt_en : 1; -+ unsigned int reg_txend_cnt_clr : 1; -+ unsigned int rsvd_0 : 4; -+ } b; -+} TX_END_CHK_FIELD_T; -+ -+#define TX_ENABLE_CHK (WIFI_MAC_MAIN_REG_BASE + 0x1b0) -+// Bit 25 :0 ro_txenable_cnt U RO default = 'h0 -+// Bit 26 reg_txenable_cnt_en U RW default = 'h0 -+// Bit 27 reg_txenable_cnt_clr U RW default = 'h1 -+typedef union TX_ENABLE_CHK_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txenable_cnt : 26; -+ unsigned int reg_txenable_cnt_en : 1; -+ unsigned int reg_txenable_cnt_clr : 1; -+ unsigned int rsvd_0 : 4; -+ } b; -+} TX_ENABLE_CHK_FIELD_T; -+ -+#define TX_ENABLEWR_CHK (WIFI_MAC_MAIN_REG_BASE + 0x1b4) -+// Bit 25 :0 ro_txenable_wr_cnt_en U RO default = 'h0 -+// Bit 26 reg_txenable_wr_cnt_en U RW default = 'h0 -+// Bit 27 reg_txenable_wr_cnt_clr U RW default = 'h1 -+typedef union TX_ENABLEWR_CHK_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_txenable_wr_cnt_en : 26; -+ unsigned int reg_txenable_wr_cnt_en : 1; -+ unsigned int reg_txenable_wr_cnt_clr : 1; -+ unsigned int rsvd_0 : 4; -+ } b; -+} TX_ENABLEWR_CHK_FIELD_T; -+ -+#define MAC_DATA_LOCAL_CNT (WIFI_MAC_MAIN_REG_BASE + 0x1b8) -+// Bit 28 :0 ro_mac_data_local_cnt U RO default = 'h0 -+// Bit 29 reg_mac_data_local_cnt_qos U RW default = 'h0 -+// Bit 30 reg_mac_data_local_cnt_clr U RW default = 'h0 -+// Bit 31 reg_mac_data_local_cnt_en U RW default = 'h0 -+typedef union MAC_DATA_LOCAL_CNT_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_mac_data_local_cnt : 29; -+ unsigned int reg_mac_data_local_cnt_qos : 1; -+ unsigned int reg_mac_data_local_cnt_clr : 1; -+ unsigned int reg_mac_data_local_cnt_en : 1; -+ } b; -+} MAC_DATA_LOCAL_CNT_FIELD_T; -+ -+#define MAC_DATA_OTHER_CNT (WIFI_MAC_MAIN_REG_BASE + 0x1bc) -+// Bit 29 :0 ro_mac_data_other_cnt U RO default = 'h0 -+// Bit 30 reg_mac_data_other_cnt_clr U RW default = 'h0 -+// Bit 31 reg_mac_data_other_cnt_en U RW default = 'h0 -+typedef union MAC_DATA_OTHER_CNT_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_mac_data_other_cnt : 30; -+ unsigned int reg_mac_data_other_cnt_clr : 1; -+ unsigned int reg_mac_data_other_cnt_en : 1; -+ } b; -+} MAC_DATA_OTHER_CNT_FIELD_T; -+ -+#define MAC_DATA_MULTI_CNT (WIFI_MAC_MAIN_REG_BASE + 0x1c0) -+// Bit 29 :0 ro_mac_data_multi_cnt U RO default = 'h0 -+// Bit 30 reg_mac_data_multi_cnt_clr U RW default = 'h0 -+// Bit 31 reg_mac_data_multi_cnt_en U RW default = 'h0 -+typedef union MAC_DATA_MULTI_CNT_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_mac_data_multi_cnt : 30; -+ unsigned int reg_mac_data_multi_cnt_clr : 1; -+ unsigned int reg_mac_data_multi_cnt_en : 1; -+ } b; -+} MAC_DATA_MULTI_CNT_FIELD_T; -+ -+#endif -+ -diff --git a/drivers/net/wireless/w1/common/wifi_mac_rx_reg.h b/drivers/net/wireless/w1/common/wifi_mac_rx_reg.h -new file mode 100644 -index 000000000000..1291feb7601a ---- /dev/null -+++ b/drivers/net/wireless/w1/common/wifi_mac_rx_reg.h -@@ -0,0 +1,313 @@ -+#ifdef WIFI_MAC_RX_REG -+#else -+#define WIFI_MAC_RX_REG -+ -+ -+#define WIFI_MAC_RX_REG_BASE (0xa00000) -+ -+#define MAC_RXWD_TIMER (WIFI_MAC_RX_REG_BASE + 0x1c4) -+// Bit 19 :0 reg_rx_wd_timer_duration U RW default = 'h4e20 -+// Bit 21 reg_rx_wd_timer_en U RW default = 'h1 -+// Bit 27 :24 reg_rxend_wait_cnum U RW default = 'h6 -+// Bit 31 :28 reg_rxstart_wait_cnum U RW default = 'h8 -+typedef union MAC_RXWD_TIMER_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_rx_wd_timer_duration : 20; -+ unsigned int rsvd_0 : 1; -+ unsigned int reg_rx_wd_timer_en : 1; -+ unsigned int rsvd_1 : 2; -+ unsigned int reg_rxend_wait_cnum : 4; -+ unsigned int reg_rxstart_wait_cnum : 4; -+ } b; -+} MAC_RXWD_TIMER_FIELD_T; -+ -+#define MAC_CHANNEL_NUM (WIFI_MAC_RX_REG_BASE + 0x1e0) -+// Bit 7 :0 reg_rx_channel_num U RW default = 'h0 -+typedef union MAC_CHANNEL_NUM_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_rx_channel_num : 8; -+ unsigned int rsvd_0 : 24; -+ } b; -+} MAC_CHANNEL_NUM_FIELD_T; -+ -+#define MAC_RX_BEACON_BASEADDR (WIFI_MAC_RX_REG_BASE + 0x1e4) -+// Bit 31 :0 reg_rx_beacon_baseaddr U RW default = 'h0 -+typedef union MAC_RX_BEACON_BASEADDR_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_rx_beacon_baseaddr : 32; -+ } b; -+} MAC_RX_BEACON_BASEADDR_FIELD_T; -+ -+#define MAC_RXENDTIME (WIFI_MAC_RX_REG_BASE + 0x1e8) -+// Bit 31 :0 ro_mac_rxendtime U RO default = 'h0 -+typedef union MAC_RXENDTIME_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_mac_rxendtime : 32; -+ } b; -+} MAC_RXENDTIME_FIELD_T; -+ -+#define MAC_RXSTARTTIME (WIFI_MAC_RX_REG_BASE + 0x1ec) -+// Bit 31 :0 ro_mac_rxstarttime U RO default = 'h0 -+typedef union MAC_RXSTARTTIME_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_mac_rxstarttime : 32; -+ } b; -+} MAC_RXSTARTTIME_FIELD_T; -+ -+#define MAC_RX_BASEADDR (WIFI_MAC_RX_REG_BASE + 0x1f0) -+// Bit 31 :0 reg_rx_baseaddr U RW default = 'h0 -+typedef union MAC_RX_BASEADDR_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_rx_baseaddr : 32; -+ } b; -+} MAC_RX_BASEADDR_FIELD_T; -+ -+#define MAC_RX_EPOINTER (WIFI_MAC_RX_REG_BASE + 0x1f4) -+// Bit 15 :0 reg_rx_eptr U RW default = 'h0 -+typedef union MAC_RX_EPOINTER_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_rx_eptr : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} MAC_RX_EPOINTER_FIELD_T; -+ -+#define MAC_RX_COUNT (WIFI_MAC_RX_REG_BASE + 0x1f8) -+// Bit 15 :0 reg_rx_count_o U RW default = 'h0 -+typedef union MAC_RX_COUNT_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_rx_count_o : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} MAC_RX_COUNT_FIELD_T; -+ -+#define MAC_RX_WPOINTER (WIFI_MAC_RX_REG_BASE + 0x1fc) -+// Bit 15 :0 reg_rx_wptr_o U RW default = 'h0 -+typedef union MAC_RX_WPOINTER_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_rx_wptr_o : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} MAC_RX_WPOINTER_FIELD_T; -+ -+#define MAC_RX_FRPOINTER (WIFI_MAC_RX_REG_BASE + 0x200) -+// Bit 15 :0 reg_rx_frptr U RW default = 'h0 -+typedef union MAC_RX_FRPOINTER_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_rx_frptr : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} MAC_RX_FRPOINTER_FIELD_T; -+ -+#define MAC_RX_HRPOINTER (WIFI_MAC_RX_REG_BASE + 0x204) -+// Bit 15 :0 ro_rx_hrptr_o U RO default = 'h0 -+typedef union MAC_RX_HRPOINTER_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rx_hrptr_o : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} MAC_RX_HRPOINTER_FIELD_T; -+ -+#define MAC_BITMAPTABLE_CMD (WIFI_MAC_RX_REG_BASE + 0x20c) -+// Bit 8 :0 reg_bitmaptable_cmd_addr U RW default = 'h0 -+// Bit 17 :16 reg_bitmaptable_cmd_type U RW default = 'h0 -+// Bit 29 ro_bitmaptable_cmd_fail U RO default = 'h0 -+// Bit 30 reg_bitmaptable_cmd_en U RW default = 'h0 -+// Bit 31 reg_bitmaptable_ready U RW default = 'h1 -+typedef union MAC_BITMAPTABLE_CMD_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_bitmaptable_cmd_addr : 9; -+ unsigned int rsvd_0 : 7; -+ unsigned int reg_bitmaptable_cmd_type : 2; -+ unsigned int rsvd_1 : 11; -+ unsigned int ro_bitmaptable_cmd_fail : 1; -+ unsigned int reg_bitmaptable_cmd_en : 1; -+ unsigned int reg_bitmaptable_ready : 1; -+ } b; -+} MAC_BITMAPTABLE_CMD_FIELD_T; -+ -+#define MAC_BITMAPTABLE_DATA (WIFI_MAC_RX_REG_BASE + 0x210) -+// Bit 31 :0 reg_mac_bitmaptable_data U RW default = 'h0 -+typedef union MAC_BITMAPTABLE_DATA_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_bitmaptable_data : 32; -+ } b; -+} MAC_BITMAPTABLE_DATA_FIELD_T; -+ -+#define MAC_BITMAPTABLE_DATA2 (WIFI_MAC_RX_REG_BASE + 0x214) -+// Bit 31 :0 reg_mac_bitmaptable_data2 U RW default = 'h0 -+typedef union MAC_BITMAPTABLE_DATA2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_bitmaptable_data2 : 32; -+ } b; -+} MAC_BITMAPTABLE_DATA2_FIELD_T; -+ -+#define MAC_BITMAPTABLE_DATA3 (WIFI_MAC_RX_REG_BASE + 0x218) -+// Bit 23 :0 reg_mac_bitmaptable_data3 U RW default = 'h0 -+typedef union MAC_BITMAPTABLE_DATA3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_bitmaptable_data3 : 24; -+ unsigned int rsvd_0 : 8; -+ } b; -+} MAC_BITMAPTABLE_DATA3_FIELD_T; -+ -+#define MAC_RXINFO (WIFI_MAC_RX_REG_BASE + 0x21c) -+// Bit 7 :0 ro_rx_rate U RO default = 'h0 -+// Bit 15 :10 ro_rx_packet_type U RO default = 'h0 -+// Bit 17 :16 ro_rx_a1match_id U RO default = 'h0 -+// Bit 21 :20 ro_rx_bssidmatch_id U RO default = 'h0 -+// Bit 31 :24 ro_rx_rssi_ant0 U RO default = 'h0 -+typedef union MAC_RXINFO_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rx_rate : 8; -+ unsigned int rsvd_0 : 2; -+ unsigned int ro_rx_packet_type : 6; -+ unsigned int ro_rx_a1match_id : 2; -+ unsigned int rsvd_1 : 2; -+ unsigned int ro_rx_bssidmatch_id : 2; -+ unsigned int rsvd_2 : 2; -+ unsigned int ro_rx_rssi_ant0 : 8; -+ } b; -+} MAC_RXINFO_FIELD_T; -+ -+#define MAC_RXINFO2 (WIFI_MAC_RX_REG_BASE + 0x220) -+// Bit 31 :0 ro_rx_a2_lo U RO default = 'h0 -+typedef union MAC_RXINFO2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_rx_a2_lo : 32; -+ } b; -+} MAC_RXINFO2_FIELD_T; -+ -+#define MAC_BMFM_INFO (WIFI_MAC_RX_REG_BASE + 0x224) -+// Bit 0 reg_cdbk_info U RW default = 'h0 -+// Bit 5 :4 reg_ng U RW default = 'h0 -+// Bit 19 :8 rxrat_ndp_vector U RW default = 'h60b -+// Bit 23 :20 reg_wfull_space U RW default = 'h4 -+// Bit 28 reg_bmfm_disable U RW default = 'h0 -+typedef union MAC_BMFM_INFO_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_cdbk_info : 1; -+ unsigned int rsvd_0 : 3; -+ unsigned int reg_ng : 2; -+ unsigned int rsvd_1 : 2; -+ unsigned int rxrat_ndp_vector : 12; -+ unsigned int reg_wfull_space : 4; -+ unsigned int rsvd_2 : 4; -+ unsigned int reg_bmfm_disable : 1; -+ unsigned int rsvd_3 : 3; -+ } b; -+} MAC_BMFM_INFO_FIELD_T; -+ -+#define MAC_AID (WIFI_MAC_RX_REG_BASE + 0x228) -+// Bit 15 :0 mac_aid U RW default = 'h0 -+typedef union MAC_AID_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int mac_aid : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} MAC_AID_FIELD_T; -+ -+#define MAC_BMFM_CNT (WIFI_MAC_RX_REG_BASE + 0x22c) -+// Bit 15 :0 cnt_bmfm_pkt U RO default = 'h0 -+// Bit 31 :16 cnt_bmfm_pkt_err U RO default = 'h0 -+typedef union MAC_BMFM_CNT_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int cnt_bmfm_pkt : 16; -+ unsigned int cnt_bmfm_pkt_err : 16; -+ } b; -+} MAC_BMFM_CNT_FIELD_T; -+ -+#define MAC_COMPRESSED_BMFM_CNT (WIFI_MAC_RX_REG_BASE + 0x230) -+// Bit 15 :0 cnt_compressed_bmfm_frame U RO default = 'h0 -+typedef union MAC_COMPRESSED_BMFM_CNT_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int cnt_compressed_bmfm_frame : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} MAC_COMPRESSED_BMFM_CNT_FIELD_T; -+ -+#define MAC_RX_BEACON_CTRL (WIFI_MAC_RX_REG_BASE + 0x234) -+// Bit 15 :0 reg_rx_beacon_buf_len U RW default = 'h0 -+// Bit 16 reg_rx_beacon_path_sel U RW default = 'h0 -+// Bit 19 :17 ro_rx_beacon_page_num U RO default = 'h0 -+// Bit 29 :20 reg_rx_beacon_clr_timer U RW default = 'h50 -+// Bit 30 reg_rx_beacon_page_mode U RW default = 'h0 -+// Bit 31 reg_rx_beacon_flag U RW default = 'h0 -+typedef union MAC_RX_BEACON_CTRL_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_rx_beacon_buf_len : 16; -+ unsigned int reg_rx_beacon_path_sel : 1; -+ unsigned int ro_rx_beacon_page_num : 3; -+ unsigned int reg_rx_beacon_clr_timer : 10; -+ unsigned int reg_rx_beacon_page_mode : 1; -+ unsigned int reg_rx_beacon_flag : 1; -+ } b; -+} MAC_RX_BEACON_CTRL_FIELD_T; -+ -+#endif -+ -diff --git a/drivers/net/wireless/w1/common/wifi_mac_timer_reg.h b/drivers/net/wireless/w1/common/wifi_mac_timer_reg.h -new file mode 100644 -index 000000000000..176e37bface4 ---- /dev/null -+++ b/drivers/net/wireless/w1/common/wifi_mac_timer_reg.h -@@ -0,0 +1,565 @@ -+#ifdef WIFI_MAC_TIMER_REG -+#else -+#define WIFI_MAC_TIMER_REG -+ -+ -+#define WIFI_MAC_TIMER_REG_BASE (0xa00000) -+ -+#define MAC_COUNT1 (WIFI_MAC_TIMER_REG_BASE + 0xb0) -+// Bit 6 :0 reg_txsifsb U RW default = 'h2c -+// Bit 14 :8 reg_rxsifsb U RW default = 'h1c -+// Bit 15 reg_rxsifsb_sel U RW default = 'h0 -+// Bit 22 :16 reg_ccasifs U RW default = 'h28 -+// Bit 28 :24 reg_txstartdel U RW default = 'h2 -+// Bit 31 :29 reg_rxendwait U RW default = 'h3 -+typedef union MAC_COUNT1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_txsifsb : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int reg_rxsifsb : 7; -+ unsigned int reg_rxsifsb_sel : 1; -+ unsigned int reg_ccasifs : 7; -+ unsigned int rsvd_1 : 1; -+ unsigned int reg_txstartdel : 5; -+ unsigned int reg_rxendwait : 3; -+ } b; -+} MAC_COUNT1_FIELD_T; -+ -+#define MAC_COUNT2 (WIFI_MAC_TIMER_REG_BASE + 0xb4) -+// Bit 6 :0 reg_txsifsa U RW default = 'h40 -+// Bit 14 :8 reg_rxsifsa U RW default = 'h24 -+// Bit 15 reg_rxsifsa_sel U RW default = 'h0 -+// Bit 21 :16 reg_slot U RW default = 'h9 -+// Bit 28 :24 reg_fiac_fw_maxdel U RW default = 'hf -+typedef union MAC_COUNT2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_txsifsa : 7; -+ unsigned int rsvd_0 : 1; -+ unsigned int reg_rxsifsa : 7; -+ unsigned int reg_rxsifsa_sel : 1; -+ unsigned int reg_slot : 6; -+ unsigned int rsvd_1 : 2; -+ unsigned int reg_fiac_fw_maxdel : 5; -+ unsigned int rsvd_2 : 3; -+ } b; -+} MAC_COUNT2_FIELD_T; -+ -+#define MAC_COUNT3 (WIFI_MAC_TIMER_REG_BASE + 0xb8) -+// Bit 8 :0 reg_backoff_hold U RW default = 'h0 -+// Bit 12 reg_backoff_all_hold U RW default = 'h0 -+// Bit 17 :16 reg_txop_hold_status U RW default = 'h0 -+typedef union MAC_COUNT3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_backoff_hold : 9; -+ unsigned int rsvd_0 : 3; -+ unsigned int reg_backoff_all_hold : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int reg_txop_hold_status : 2; -+ unsigned int rsvd_2 : 14; -+ } b; -+} MAC_COUNT3_FIELD_T; -+ -+#define MAC_BACKOFF_CONTROL (WIFI_MAC_TIMER_REG_BASE + 0xbc) -+// Bit 7 :0 reg_slotn_s U RW default = 'h1 -+// Bit 11 reg_sifsn_s U RW default = 'h1 -+// Bit 15 reg_backoff_way U RW default = 'h1 -+// Bit 16 reg_ackto_way U RW default = 'h0 -+typedef union MAC_BACKOFF_CONTROL_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_slotn_s : 8; -+ unsigned int rsvd_0 : 3; -+ unsigned int reg_sifsn_s : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int reg_backoff_way : 1; -+ unsigned int reg_ackto_way : 1; -+ unsigned int rsvd_2 : 15; -+ } b; -+} MAC_BACKOFF_CONTROL_FIELD_T; -+ -+#define MAC_ABSCNT0 (WIFI_MAC_TIMER_REG_BASE + 0xc0) -+// Bit 25 :0 reg_abscnt0 U RW default = 'h0 -+typedef union MAC_ABSCNT0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_abscnt0 : 26; -+ unsigned int rsvd_0 : 6; -+ } b; -+} MAC_ABSCNT0_FIELD_T; -+ -+#define MAC_ABSCNT1 (WIFI_MAC_TIMER_REG_BASE + 0xc4) -+// Bit 25 :0 reg_abscnt1 U RW default = 'h0 -+typedef union MAC_ABSCNT1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_abscnt1 : 26; -+ unsigned int rsvd_0 : 6; -+ } b; -+} MAC_ABSCNT1_FIELD_T; -+ -+#define MAC_ABSCNT2 (WIFI_MAC_TIMER_REG_BASE + 0xc8) -+// Bit 25 :0 reg_abscnt2 U RW default = 'h0 -+typedef union MAC_ABSCNT2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_abscnt2 : 26; -+ unsigned int rsvd_0 : 6; -+ } b; -+} MAC_ABSCNT2_FIELD_T; -+ -+#define MAC_ABSCNT3 (WIFI_MAC_TIMER_REG_BASE + 0xcc) -+// Bit 25 :0 reg_abscnt3 U RW default = 'h0 -+typedef union MAC_ABSCNT3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_abscnt3 : 26; -+ unsigned int rsvd_0 : 6; -+ } b; -+} MAC_ABSCNT3_FIELD_T; -+ -+#define MAC_ABSCNT4 (WIFI_MAC_TIMER_REG_BASE + 0xd0) -+// Bit 25 :0 reg_abscnt4 U RW default = 'h0 -+typedef union MAC_ABSCNT4_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_abscnt4 : 26; -+ unsigned int rsvd_0 : 6; -+ } b; -+} MAC_ABSCNT4_FIELD_T; -+ -+#define MAC_ABSCNT5 (WIFI_MAC_TIMER_REG_BASE + 0xd4) -+// Bit 25 :0 reg_abscnt5 U RW default = 'h0 -+typedef union MAC_ABSCNT5_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_abscnt5 : 26; -+ unsigned int rsvd_0 : 6; -+ } b; -+} MAC_ABSCNT5_FIELD_T; -+ -+#define MAC_ABSCNT6 (WIFI_MAC_TIMER_REG_BASE + 0xd8) -+// Bit 25 :0 reg_abscnt6 U RW default = 'h0 -+typedef union MAC_ABSCNT6_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_abscnt6 : 26; -+ unsigned int rsvd_0 : 6; -+ } b; -+} MAC_ABSCNT6_FIELD_T; -+ -+#define MAC_ABSCNT7 (WIFI_MAC_TIMER_REG_BASE + 0xdc) -+// Bit 25 :0 reg_abscnt7 U RW default = 'h0 -+typedef union MAC_ABSCNT7_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_abscnt7 : 26; -+ unsigned int rsvd_0 : 6; -+ } b; -+} MAC_ABSCNT7_FIELD_T; -+ -+#define MAC_ABSCNT8 (WIFI_MAC_TIMER_REG_BASE + 0xe0) -+// Bit 25 :0 reg_abscnt8 U RW default = 'h0 -+typedef union MAC_ABSCNT8_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_abscnt8 : 26; -+ unsigned int rsvd_0 : 6; -+ } b; -+} MAC_ABSCNT8_FIELD_T; -+ -+#define MAC_ABSCNT9 (WIFI_MAC_TIMER_REG_BASE + 0xe4) -+// Bit 25 :0 reg_abscnt9 U RW default = 'h0 -+typedef union MAC_ABSCNT9_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_abscnt9 : 26; -+ unsigned int rsvd_0 : 6; -+ } b; -+} MAC_ABSCNT9_FIELD_T; -+ -+#define MAC_ABSCNT10 (WIFI_MAC_TIMER_REG_BASE + 0xe8) -+// Bit 25 :0 reg_abscnt10 U RW default = 'h0 -+typedef union MAC_ABSCNT10_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_abscnt10 : 26; -+ unsigned int rsvd_0 : 6; -+ } b; -+} MAC_ABSCNT10_FIELD_T; -+ -+#define MAC_ABSCNT11 (WIFI_MAC_TIMER_REG_BASE + 0xec) -+// Bit 25 :0 reg_abscnt11 U RW default = 'h0 -+typedef union MAC_ABSCNT11_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_abscnt11 : 26; -+ unsigned int rsvd_0 : 6; -+ } b; -+} MAC_ABSCNT11_FIELD_T; -+ -+#ifndef PROJECT_T9026 -+#define MAC_ABSCNT12 (WIFI_MAC_TIMER_REG_BASE + 0x1d0) -+// Bit 25 :0 reg_abscnt12 U RW default = 'h0 -+typedef union MAC_ABSCNT12_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_abscnt12 : 26; -+ unsigned int rsvd_0 : 6; -+ } b; -+} MAC_ABSCNT12_FIELD_T; -+ -+#define MAC_ABSCNT13 (WIFI_MAC_TIMER_REG_BASE + 0x1d4) -+// Bit 25 :0 reg_abscnt13 U RW default = 'h0 -+typedef union MAC_ABSCNT13_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_abscnt13 : 26; -+ unsigned int rsvd_0 : 6; -+ } b; -+} MAC_ABSCNT13_FIELD_T; -+ -+#define MAC_ABSCNT14 (WIFI_MAC_TIMER_REG_BASE + 0x1d8) -+// Bit 25 :0 reg_abscnt14 U RW default = 'h0 -+typedef union MAC_ABSCNT14_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_abscnt14 : 26; -+ unsigned int rsvd_0 : 6; -+ } b; -+} MAC_ABSCNT14_FIELD_T; -+ -+#define MAC_ABSCNT15 (WIFI_MAC_TIMER_REG_BASE + 0x1dc) -+// Bit 25 :0 reg_abscnt15 U RW default = 'h0 -+typedef union MAC_ABSCNT15_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_abscnt15 : 26; -+ unsigned int rsvd_0 : 6; -+ } b; -+} MAC_ABSCNT15_FIELD_T; -+#endif -+ -+#define TIMER_CONFIG (WIFI_MAC_TIMER_REG_BASE + 0xfc) -+// Bit 3 :0 reg_tx_priority_ctrl U RW default = 'hc -+// Bit 9 :4 reg_tx_duration_ctrl U RW default = 'h0 -+// Bit 10 reg_tx_request_mode U RW default = 'h1 -+// Bit 11 reg_tx_enable_clr_sel U RW default = 'h0 -+// Bit 15 :12 reg_tx_start_cnt_thr U RW default = 'h4 -+// Bit 31 :16 reg_vcs_thr U RW default = 'h1000 -+typedef union TIMER_CONFIG_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_tx_priority_ctrl : 4; -+ unsigned int reg_tx_duration_ctrl : 6; -+ unsigned int reg_tx_request_mode : 1; -+ unsigned int reg_tx_enable_clr_sel : 1; -+ unsigned int reg_tx_start_cnt_thr : 4; -+ unsigned int reg_vcs_thr : 16; -+ } b; -+} TIMER_CONFIG_FIELD_T; -+ -+#define MAC_TXCONTROL_NONQOS (WIFI_MAC_TIMER_REG_BASE + 0x100) -+// Bit 9 :0 reg_slot_num_o_nonqos U RW default = 'h0 -+// Bit 15 :10 reg_tx_duration_nonqos U RW default = 'h8 -+// Bit 19 :16 reg_aifsn_nonqos U RW default = 'h0 -+// Bit 23 :20 reg_cca_busy_mask_nonqos U RW default = 'h0 -+// Bit 24 reg_tx_enable_nonqos U RW default = 'h0 -+// Bit 26 :25 reg_tx_bandwidth_nonqos U RW default = 'h0 -+// Bit 31 :28 reg_tx_priority_nonqos U RW default = 'h0 -+typedef union MAC_TXCONTROL_NONQOS_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_slot_num_o_nonqos : 10; -+ unsigned int reg_tx_duration_nonqos : 6; -+ unsigned int reg_aifsn_nonqos : 4; -+ unsigned int reg_cca_busy_mask_nonqos : 4; -+ unsigned int reg_tx_enable_nonqos : 1; -+ unsigned int reg_tx_bandwidth_nonqos : 2; -+ unsigned int rsvd_0 : 1; -+ unsigned int reg_tx_priority_nonqos : 4; -+ } b; -+} MAC_TXCONTROL_NONQOS_FIELD_T; -+ -+#define MAC_TXCONTROL_ACP0 (WIFI_MAC_TIMER_REG_BASE + 0x104) -+// Bit 9 :0 reg_slot_num_o_acp0 U RW default = 'h0 -+// Bit 15 :10 reg_tx_duration_acp0 U RW default = 'h8 -+// Bit 19 :16 reg_aifsn_acp0 U RW default = 'h0 -+// Bit 23 :20 reg_cca_busy_mask_acp0 U RW default = 'h0 -+// Bit 24 reg_tx_enable_acp0 U RW default = 'h0 -+// Bit 26 :25 reg_tx_bandwidth_acp0 U RW default = 'h0 -+// Bit 31 :28 reg_tx_priority_acp0 U RW default = 'h0 -+typedef union MAC_TXCONTROL_ACP0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_slot_num_o_acp0 : 10; -+ unsigned int reg_tx_duration_acp0 : 6; -+ unsigned int reg_aifsn_acp0 : 4; -+ unsigned int reg_cca_busy_mask_acp0 : 4; -+ unsigned int reg_tx_enable_acp0 : 1; -+ unsigned int reg_tx_bandwidth_acp0 : 2; -+ unsigned int rsvd_0 : 1; -+ unsigned int reg_tx_priority_acp0 : 4; -+ } b; -+} MAC_TXCONTROL_ACP0_FIELD_T; -+ -+#define MAC_TXCONTROL_ACP1 (WIFI_MAC_TIMER_REG_BASE + 0x108) -+// Bit 9 :0 reg_slot_num_o_acp1 U RW default = 'h0 -+// Bit 15 :10 reg_tx_duration_acp1 U RW default = 'h8 -+// Bit 19 :16 reg_aifsn_acp1 U RW default = 'h0 -+// Bit 23 :20 reg_cca_busy_mask_acp1 U RW default = 'h0 -+// Bit 24 reg_tx_enable_acp1 U RW default = 'h0 -+// Bit 26 :25 reg_tx_bandwidth_acp1 U RW default = 'h0 -+// Bit 31 :28 reg_tx_priority_acp1 U RW default = 'h0 -+typedef union MAC_TXCONTROL_ACP1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_slot_num_o_acp1 : 10; -+ unsigned int reg_tx_duration_acp1 : 6; -+ unsigned int reg_aifsn_acp1 : 4; -+ unsigned int reg_cca_busy_mask_acp1 : 4; -+ unsigned int reg_tx_enable_acp1 : 1; -+ unsigned int reg_tx_bandwidth_acp1 : 2; -+ unsigned int rsvd_0 : 1; -+ unsigned int reg_tx_priority_acp1 : 4; -+ } b; -+} MAC_TXCONTROL_ACP1_FIELD_T; -+ -+#define MAC_TXCONTROL_ACP2 (WIFI_MAC_TIMER_REG_BASE + 0x10c) -+// Bit 9 :0 reg_slot_num_o_acp2 U RW default = 'h0 -+// Bit 15 :10 reg_tx_duration_acp2 U RW default = 'h8 -+// Bit 19 :16 reg_aifsn_acp2 U RW default = 'h0 -+// Bit 23 :20 reg_cca_busy_mask_acp2 U RW default = 'h0 -+// Bit 24 reg_tx_enable_acp2 U RW default = 'h0 -+// Bit 26 :25 reg_tx_bandwidth_acp2 U RW default = 'h0 -+// Bit 31 :28 reg_tx_priority_acp2 U RW default = 'h0 -+typedef union MAC_TXCONTROL_ACP2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_slot_num_o_acp2 : 10; -+ unsigned int reg_tx_duration_acp2 : 6; -+ unsigned int reg_aifsn_acp2 : 4; -+ unsigned int reg_cca_busy_mask_acp2 : 4; -+ unsigned int reg_tx_enable_acp2 : 1; -+ unsigned int reg_tx_bandwidth_acp2 : 2; -+ unsigned int rsvd_0 : 1; -+ unsigned int reg_tx_priority_acp2 : 4; -+ } b; -+} MAC_TXCONTROL_ACP2_FIELD_T; -+ -+#define MAC_TXCONTROL_ACP3 (WIFI_MAC_TIMER_REG_BASE + 0x110) -+// Bit 9 :0 reg_slot_num_o_acp3 U RW default = 'h0 -+// Bit 15 :10 reg_tx_duration_acp3 U RW default = 'h8 -+// Bit 19 :16 reg_aifsn_acp3 U RW default = 'h0 -+// Bit 23 :20 reg_cca_busy_mask_acp3 U RW default = 'h0 -+// Bit 24 reg_tx_enable_acp3 U RW default = 'h0 -+// Bit 26 :25 reg_tx_bandwidth_acp3 U RW default = 'h0 -+// Bit 31 :28 reg_tx_priority_acp3 U RW default = 'h0 -+typedef union MAC_TXCONTROL_ACP3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_slot_num_o_acp3 : 10; -+ unsigned int reg_tx_duration_acp3 : 6; -+ unsigned int reg_aifsn_acp3 : 4; -+ unsigned int reg_cca_busy_mask_acp3 : 4; -+ unsigned int reg_tx_enable_acp3 : 1; -+ unsigned int reg_tx_bandwidth_acp3 : 2; -+ unsigned int rsvd_0 : 1; -+ unsigned int reg_tx_priority_acp3 : 4; -+ } b; -+} MAC_TXCONTROL_ACP3_FIELD_T; -+ -+#define MAC_TXCONTROL_ACP4 (WIFI_MAC_TIMER_REG_BASE + 0x114) -+// Bit 9 :0 reg_slot_num_o_acp4 U RW default = 'h0 -+// Bit 15 :10 reg_tx_duration_acp4 U RW default = 'h8 -+// Bit 19 :16 reg_aifsn_acp4 U RW default = 'h0 -+// Bit 23 :20 reg_cca_busy_mask_acp4 U RW default = 'h0 -+// Bit 24 reg_tx_enable_acp4 U RW default = 'h0 -+// Bit 26 :25 reg_tx_bandwidth_acp4 U RW default = 'h0 -+// Bit 31 :28 reg_tx_priority_acp4 U RW default = 'h0 -+typedef union MAC_TXCONTROL_ACP4_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_slot_num_o_acp4 : 10; -+ unsigned int reg_tx_duration_acp4 : 6; -+ unsigned int reg_aifsn_acp4 : 4; -+ unsigned int reg_cca_busy_mask_acp4 : 4; -+ unsigned int reg_tx_enable_acp4 : 1; -+ unsigned int reg_tx_bandwidth_acp4 : 2; -+ unsigned int rsvd_0 : 1; -+ unsigned int reg_tx_priority_acp4 : 4; -+ } b; -+} MAC_TXCONTROL_ACP4_FIELD_T; -+ -+#define MAC_TXCONTROL_ACP5 (WIFI_MAC_TIMER_REG_BASE + 0x118) -+// Bit 9 :0 reg_slot_num_o_acp5 U RW default = 'h0 -+// Bit 15 :10 reg_tx_duration_acp5 U RW default = 'h8 -+// Bit 19 :16 reg_aifsn_acp5 U RW default = 'h0 -+// Bit 23 :20 reg_cca_busy_mask_acp5 U RW default = 'h0 -+// Bit 24 reg_tx_enable_acp5 U RW default = 'h0 -+// Bit 26 :25 reg_tx_bandwidth_acp5 U RW default = 'h0 -+// Bit 31 :28 reg_tx_priority_acp5 U RW default = 'h0 -+typedef union MAC_TXCONTROL_ACP5_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_slot_num_o_acp5 : 10; -+ unsigned int reg_tx_duration_acp5 : 6; -+ unsigned int reg_aifsn_acp5 : 4; -+ unsigned int reg_cca_busy_mask_acp5 : 4; -+ unsigned int reg_tx_enable_acp5 : 1; -+ unsigned int reg_tx_bandwidth_acp5 : 2; -+ unsigned int rsvd_0 : 1; -+ unsigned int reg_tx_priority_acp5 : 4; -+ } b; -+} MAC_TXCONTROL_ACP5_FIELD_T; -+ -+#define MAC_TXCONTROL_ACP6 (WIFI_MAC_TIMER_REG_BASE + 0x11c) -+// Bit 9 :0 reg_slot_num_o_acp6 U RW default = 'h0 -+// Bit 15 :10 reg_tx_duration_acp6 U RW default = 'h8 -+// Bit 19 :16 reg_aifsn_acp6 U RW default = 'h0 -+// Bit 23 :20 reg_cca_busy_mask_acp6 U RW default = 'h0 -+// Bit 24 reg_tx_enable_acp6 U RW default = 'h0 -+// Bit 26 :25 reg_tx_bandwidth_acp6 U RW default = 'h0 -+// Bit 31 :28 reg_tx_priority_acp6 U RW default = 'h0 -+typedef union MAC_TXCONTROL_ACP6_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_slot_num_o_acp6 : 10; -+ unsigned int reg_tx_duration_acp6 : 6; -+ unsigned int reg_aifsn_acp6 : 4; -+ unsigned int reg_cca_busy_mask_acp6 : 4; -+ unsigned int reg_tx_enable_acp6 : 1; -+ unsigned int reg_tx_bandwidth_acp6 : 2; -+ unsigned int rsvd_0 : 1; -+ unsigned int reg_tx_priority_acp6 : 4; -+ } b; -+} MAC_TXCONTROL_ACP6_FIELD_T; -+ -+#define MAC_TXCONTROL_ACP7 (WIFI_MAC_TIMER_REG_BASE + 0x120) -+// Bit 9 :0 reg_slot_num_o_acp7 U RW default = 'h0 -+// Bit 15 :10 reg_tx_duration_acp7 U RW default = 'h8 -+// Bit 19 :16 reg_aifsn_acp7 U RW default = 'h0 -+// Bit 23 :20 reg_cca_busy_mask_acp7 U RW default = 'h0 -+// Bit 24 reg_tx_enable_acp7 U RW default = 'h0 -+// Bit 26 :25 reg_tx_bandwidth_acp7 U RW default = 'h0 -+// Bit 31 :28 reg_tx_priority_acp7 U RW default = 'h0 -+typedef union MAC_TXCONTROL_ACP7_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_slot_num_o_acp7 : 10; -+ unsigned int reg_tx_duration_acp7 : 6; -+ unsigned int reg_aifsn_acp7 : 4; -+ unsigned int reg_cca_busy_mask_acp7 : 4; -+ unsigned int reg_tx_enable_acp7 : 1; -+ unsigned int reg_tx_bandwidth_acp7 : 2; -+ unsigned int rsvd_0 : 1; -+ unsigned int reg_tx_priority_acp7 : 4; -+ } b; -+} MAC_TXCONTROL_ACP7_FIELD_T; -+ -+#define MAC_VCSUPDATE (WIFI_MAC_TIMER_REG_BASE + 0x128) -+// Bit 25 :0 reg_vcs_time U RW default = 'h0 -+// Bit 26 reg_vcs_enb U RW default = 'h0 -+// Bit 28 :27 reg_vcs_source U RW default = 'h0 -+// Bit 30 ro_vcs_enable U RO default = 'h0 -+// Bit 31 reg_vcs_up_enb U RW default = 'h0 -+typedef union MAC_VCSUPDATE_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_vcs_time : 26; -+ unsigned int reg_vcs_enb : 1; -+ unsigned int reg_vcs_source : 2; -+ unsigned int rsvd_0 : 1; -+ unsigned int ro_vcs_enable : 1; -+ unsigned int reg_vcs_up_enb : 1; -+ } b; -+} MAC_VCSUPDATE_FIELD_T; -+ -+#define MAC_TIME_HIGH (WIFI_MAC_TIMER_REG_BASE + 0x12c) -+// Bit 31 :0 reg_mac_time_high U RO default = 'h0 -+typedef union MAC_TIME_HIGH_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_time_high : 32; -+ } b; -+} MAC_TIME_HIGH_FIELD_T; -+ -+#define MAC_TIME_LOW (WIFI_MAC_TIMER_REG_BASE + 0x130) -+// Bit 31 :0 reg_mac_time_low U RO default = 'h0 -+typedef union MAC_TIME_LOW_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_time_low : 32; -+ } b; -+} MAC_TIME_LOW_FIELD_T; -+ -+#endif -+ -diff --git a/drivers/net/wireless/w1/common/wifi_mac_tx_reg.h b/drivers/net/wireless/w1/common/wifi_mac_tx_reg.h -new file mode 100644 -index 000000000000..e5dd9221bab2 ---- /dev/null -+++ b/drivers/net/wireless/w1/common/wifi_mac_tx_reg.h -@@ -0,0 +1,1341 @@ -+#ifdef WIFI_MAC_TX_REG -+#else -+#define WIFI_MAC_TX_REG -+ -+ -+#define WIFI_MAC_TX_REG_BASE (0xa00000) -+ -+#define MAC_TXSTARTTIME_HIGH (WIFI_MAC_TX_REG_BASE + 0x238) -+// Bit 31 :0 ro_mac_txstarttime_high U RO default = 'h0 -+typedef union MAC_TXSTARTTIME_HIGH_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_mac_txstarttime_high : 32; -+ } b; -+} MAC_TXSTARTTIME_HIGH_FIELD_T; -+ -+#define MAC_TXSTARTTIME_LOW (WIFI_MAC_TX_REG_BASE + 0x23c) -+// Bit 31 :0 ro_mac_txstarttime_low U RO default = 'h0 -+typedef union MAC_TXSTARTTIME_LOW_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_mac_txstarttime_low : 32; -+ } b; -+} MAC_TXSTARTTIME_LOW_FIELD_T; -+ -+#define MAC_TXENDTIME (WIFI_MAC_TX_REG_BASE + 0x240) -+// Bit 31 :0 ro_mac_txendtime U RO default = 'h0 -+typedef union MAC_TXENDTIME_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_mac_txendtime : 32; -+ } b; -+} MAC_TXENDTIME_FIELD_T; -+ -+#define MAC_TXPOINTER (WIFI_MAC_TX_REG_BASE + 0x244) -+// Bit 31 :0 reg_tx_table_ptr U RW default = 'h0 -+typedef union MAC_TXPOINTER_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_tx_table_ptr : 32; -+ } b; -+} MAC_TXPOINTER_FIELD_T; -+ -+#define MAC_TXCONTROL_FIAC (WIFI_MAC_TX_REG_BASE + 0x248) -+// Bit 15 :10 reg_tx_duration_fiac U RW default = 'h1 -+// Bit 24 reg_dcpready_fiac U RW default = 'h0 -+// Bit 31 :28 reg_tx_priority_fiac U RW default = 'h0 -+typedef union MAC_TXCONTROL_FIAC_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int rsvd_0 : 10; -+ unsigned int reg_tx_duration_fiac : 6; -+ unsigned int rsvd_1 : 8; -+ unsigned int reg_dcpready_fiac : 1; -+ unsigned int rsvd_2 : 3; -+ unsigned int reg_tx_priority_fiac : 4; -+ } b; -+} MAC_TXCONTROL_FIAC_FIELD_T; -+ -+#define MAC_TXWD_TIMER (WIFI_MAC_TX_REG_BASE + 0x24c) -+// Bit 23 :0 reg_tx_wd_timer_duration U RW default = 'h4e20 -+// Bit 31 reg_tx_wd_timer_en U RW default = 'h1 -+typedef union MAC_TXWD_TIMER_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_tx_wd_timer_duration : 24; -+ unsigned int rsvd_0 : 7; -+ unsigned int reg_tx_wd_timer_en : 1; -+ } b; -+} MAC_TXWD_TIMER_FIELD_T; -+ -+#define MAC_TXINFO (WIFI_MAC_TX_REG_BASE + 0x250) -+// Bit 0 reg_txend_queue_bitinfo0 U W1C default = 'h0 -+// Bit 1 reg_txend_queue_bitinfo1 U W1C default = 'h0 -+// Bit 2 reg_txend_queue_bitinfo2 U W1C default = 'h0 -+// Bit 3 reg_txend_queue_bitinfo3 U W1C default = 'h0 -+// Bit 4 reg_txend_queue_bitinfo4 U W1C default = 'h0 -+// Bit 5 reg_txend_queue_bitinfo5 U W1C default = 'h0 -+// Bit 6 reg_txend_queue_bitinfo6 U W1C default = 'h0 -+// Bit 7 reg_txend_queue_bitinfo7 U W1C default = 'h0 -+// Bit 8 reg_txend_queue_bitinfo8 U W1C default = 'h0 -+// Bit 9 reg_txend_queue_bitinfo9 U W1C default = 'h0 -+// Bit 25 :16 ro_txend_queue_errinfo U RO default = 'h0 -+typedef union MAC_TXINFO_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_txend_queue_bitinfo0 : 1; -+ unsigned int reg_txend_queue_bitinfo1 : 1; -+ unsigned int reg_txend_queue_bitinfo2 : 1; -+ unsigned int reg_txend_queue_bitinfo3 : 1; -+ unsigned int reg_txend_queue_bitinfo4 : 1; -+ unsigned int reg_txend_queue_bitinfo5 : 1; -+ unsigned int reg_txend_queue_bitinfo6 : 1; -+ unsigned int reg_txend_queue_bitinfo7 : 1; -+ unsigned int reg_txend_queue_bitinfo8 : 1; -+ unsigned int reg_txend_queue_bitinfo9 : 1; -+ unsigned int rsvd_0 : 6; -+ unsigned int ro_txend_queue_errinfo : 10; -+ unsigned int rsvd_1 : 6; -+ } b; -+} MAC_TXINFO_FIELD_T; -+ -+#define TX_CTRL_FRAME_SEND (WIFI_MAC_TX_REG_BASE + 0x258) -+// Bit 7 :0 reg_tx_other_info_len U RW default = 'h34 -+// Bit 10 :8 reg_dynamic_mcs U RW default = 'h1 -+// Bit 12 reg_dynamic_mcs_en U RW default = 'h1 -+// Bit 25 :16 reg_txout_time_thr U RW default = 'h320 -+// Bit 28 reg_txout_time_thr_en U RW default = 'h1 -+typedef union TX_CTRL_FRAME_SEND_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_tx_other_info_len : 8; -+ unsigned int reg_dynamic_mcs : 3; -+ unsigned int rsvd_0 : 1; -+ unsigned int reg_dynamic_mcs_en : 1; -+ unsigned int rsvd_1 : 3; -+ unsigned int reg_txout_time_thr : 10; -+ unsigned int rsvd_2 : 2; -+ unsigned int reg_txout_time_thr_en : 1; -+ unsigned int rsvd_3 : 3; -+ } b; -+} TX_CTRL_FRAME_SEND_FIELD_T; -+ -+#define TX_IAC_SEND_CTRL (WIFI_MAC_TX_REG_BASE + 0x25c) -+// Bit 0 reg_iac_frame_send U RW default = 'h0 -+// Bit 6 :4 reg_iac_frame_type U RW default = 'h0 -+// Bit 10 :8 reg_iac_tid_num U RW default = 'h0 -+// Bit 11 reg_iac_power_mode U RW default = 'h0 -+typedef union TX_IAC_SEND_CTRL_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_iac_frame_send : 1; -+ unsigned int rsvd_0 : 3; -+ unsigned int reg_iac_frame_type : 3; -+ unsigned int rsvd_1 : 1; -+ unsigned int reg_iac_tid_num : 3; -+ unsigned int reg_iac_power_mode : 1; -+ unsigned int rsvd_2 : 20; -+ } b; -+} TX_IAC_SEND_CTRL_FIELD_T; -+ -+#define TX_IAC_BAR_INFO (WIFI_MAC_TX_REG_BASE + 0x260) -+// Bit 3 :0 reg_iac_tid_0 U RW default = 'h0 -+// Bit 15 :4 reg_iac_bitmap_index_0 U RW default = 'h0 -+// Bit 19 :16 reg_iac_tid_1 U RW default = 'h0 -+// Bit 31 :20 reg_iac_bitmap_index_1 U RW default = 'h0 -+typedef union TX_IAC_BAR_INFO_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_iac_tid_0 : 4; -+ unsigned int reg_iac_bitmap_index_0 : 12; -+ unsigned int reg_iac_tid_1 : 4; -+ unsigned int reg_iac_bitmap_index_1 : 12; -+ } b; -+} TX_IAC_BAR_INFO_FIELD_T; -+ -+#define TXIAC_ADDR1_LOW (WIFI_MAC_TX_REG_BASE + 0x264) -+// Bit 31 :0 reg_txiac_addr1_low U RW default = 'h0 -+typedef union TXIAC_ADDR1_LOW_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_txiac_addr1_low : 32; -+ } b; -+} TXIAC_ADDR1_LOW_FIELD_T; -+ -+#define TXIAC_ADDR1_HIGH (WIFI_MAC_TX_REG_BASE + 0x268) -+// Bit 15 :0 reg_txiac_addr1_high U RW default = 'h0 -+typedef union TXIAC_ADDR1_HIGH_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_txiac_addr1_high : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} TXIAC_ADDR1_HIGH_FIELD_T; -+ -+#define TXIAC_ADDR2_LOW (WIFI_MAC_TX_REG_BASE + 0x26c) -+// Bit 31 :0 reg_txiac_addr2_low U RW default = 'h0 -+typedef union TXIAC_ADDR2_LOW_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_txiac_addr2_low : 32; -+ } b; -+} TXIAC_ADDR2_LOW_FIELD_T; -+ -+#define TXIAC_ADDR2_HIGH (WIFI_MAC_TX_REG_BASE + 0x270) -+// Bit 15 :0 reg_txiac_addr2_high U RW default = 'h0 -+typedef union TXIAC_ADDR2_HIGH_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_txiac_addr2_high : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} TXIAC_ADDR2_HIGH_FIELD_T; -+ -+#define TX_IAC_VECTOR (WIFI_MAC_TX_REG_BASE + 0x274) -+// Bit 31 :0 reg_txiac_vector U RW default = 'h0 -+typedef union TX_IAC_VECTOR_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_txiac_vector : 32; -+ } b; -+} TX_IAC_VECTOR_FIELD_T; -+ -+#define MAC_TXVECTOR_CONF (WIFI_MAC_TX_REG_BASE + 0x278) -+// Bit 15 :0 reg_mac_tx_service U RW default = 'h0 -+// Bit 18 :16 reg_mac_tx_htdltf_num U RW default = 'h1 -+// Bit 22 :20 reg_mac_tx_hteltf_num U RW default = 'h0 -+// Bit 26 :24 reg_mac_tx_vhtltf_num U RW default = 'h0 -+typedef union MAC_TXVECTOR_CONF_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_tx_service : 16; -+ unsigned int reg_mac_tx_htdltf_num : 3; -+ unsigned int rsvd_0 : 1; -+ unsigned int reg_mac_tx_hteltf_num : 3; -+ unsigned int rsvd_1 : 1; -+ unsigned int reg_mac_tx_vhtltf_num : 3; -+ unsigned int rsvd_2 : 5; -+ } b; -+} MAC_TXVECTOR_CONF_FIELD_T; -+ -+#define TXOP_REMAIN (WIFI_MAC_TX_REG_BASE + 0x27c) -+// Bit 14 :0 reg_txop_remain U RW default = 'h0 -+// Bit 25 :16 reg_rts_time U RW default = 'h0 -+// Bit 30 :28 reg_dyn_bwd_ctrl U RW default = 'h0 -+typedef union TXOP_REMAIN_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_txop_remain : 15; -+ unsigned int rsvd_0 : 1; -+ unsigned int reg_rts_time : 10; -+ unsigned int rsvd_1 : 2; -+ unsigned int reg_dyn_bwd_ctrl : 3; -+ unsigned int rsvd_2 : 1; -+ } b; -+} TXOP_REMAIN_FIELD_T; -+ -+#define FW_PKT_DURA_CALC_IN (WIFI_MAC_TX_REG_BASE + 0x280) -+// Bit 30 :0 reg_fw_pkt_dura_calc_in U RW default = 'h0 -+// Bit 31 reg_fw_pkt_dura_calc_req U RW default = 'h0 -+typedef union FW_PKT_DURA_CALC_IN_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_fw_pkt_dura_calc_in : 31; -+ unsigned int reg_fw_pkt_dura_calc_req : 1; -+ } b; -+} FW_PKT_DURA_CALC_IN_FIELD_T; -+ -+#define FW_PKT_DURA_CALC_OUT (WIFI_MAC_TX_REG_BASE + 0x284) -+// Bit 15 :0 ro_fw_pkt_dura_calc_out U RO default = 'h0 -+typedef union FW_PKT_DURA_CALC_OUT_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int ro_fw_pkt_dura_calc_out : 16; -+ unsigned int rsvd_0 : 16; -+ } b; -+} FW_PKT_DURA_CALC_OUT_FIELD_T; -+ -+#define TXOUT_ENDCNT_MAX (WIFI_MAC_TX_REG_BASE + 0x288) -+// Bit 3 :0 reg_txout_endcnt_max U RW default = 'h4 -+// Bit 15 :8 reg_tx_rts_rate U RW default = 'h4 -+// Bit 23 :16 reg_tx_time_gap U RW default = 'h10 -+typedef union TXOUT_ENDCNT_MAX_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_txout_endcnt_max : 4; -+ unsigned int rsvd_0 : 4; -+ unsigned int reg_tx_rts_rate : 8; -+ unsigned int reg_tx_time_gap : 8; -+ unsigned int rsvd_1 : 8; -+ } b; -+} TXOUT_ENDCNT_MAX_FIELD_T; -+ -+#define MAC_TXVECTOR_P1_NONQOS (WIFI_MAC_TX_REG_BASE + 0x28c) -+// Bit 29 :0 reg_mac_txvector_p1_nonqos U RW default = 'h0 -+// Bit 30 reg_mac_txvector_p1_nonqos_rts U RW default = 'h0 -+// Bit 31 reg_mac_txvector_p1_nonqos_cts U RW default = 'h0 -+typedef union MAC_TXVECTOR_P1_NONQOS_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_txvector_p1_nonqos : 30; -+ unsigned int reg_mac_txvector_p1_nonqos_rts : 1; -+ unsigned int reg_mac_txvector_p1_nonqos_cts : 1; -+ } b; -+} MAC_TXVECTOR_P1_NONQOS_FIELD_T; -+ -+#define MAC_TXVECTOR_P1_ACP0 (WIFI_MAC_TX_REG_BASE + 0x290) -+// Bit 29 :0 reg_mac_txvector_p1_acp0 U RW default = 'h0 -+// Bit 30 reg_mac_txvector_p1_acp0_rts U RW default = 'h0 -+// Bit 31 reg_mac_txvector_p1_acp0_cts U RW default = 'h0 -+typedef union MAC_TXVECTOR_P1_ACP0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_txvector_p1_acp0 : 30; -+ unsigned int reg_mac_txvector_p1_acp0_rts : 1; -+ unsigned int reg_mac_txvector_p1_acp0_cts : 1; -+ } b; -+} MAC_TXVECTOR_P1_ACP0_FIELD_T; -+ -+#define MAC_TXVECTOR_P1_ACP1 (WIFI_MAC_TX_REG_BASE + 0x294) -+// Bit 29 :0 reg_mac_txvector_p1_acp1 U RW default = 'h0 -+// Bit 30 reg_mac_txvector_p1_acp1_rts U RW default = 'h0 -+// Bit 31 reg_mac_txvector_p1_acp1_cts U RW default = 'h0 -+typedef union MAC_TXVECTOR_P1_ACP1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_txvector_p1_acp1 : 30; -+ unsigned int reg_mac_txvector_p1_acp1_rts : 1; -+ unsigned int reg_mac_txvector_p1_acp1_cts : 1; -+ } b; -+} MAC_TXVECTOR_P1_ACP1_FIELD_T; -+ -+#define MAC_TXVECTOR_P1_ACP2 (WIFI_MAC_TX_REG_BASE + 0x298) -+// Bit 29 :0 reg_mac_txvector_p1_acp2 U RW default = 'h0 -+// Bit 30 reg_mac_txvector_p1_acp2_rts U RW default = 'h0 -+// Bit 31 reg_mac_txvector_p1_acp2_cts U RW default = 'h0 -+typedef union MAC_TXVECTOR_P1_ACP2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_txvector_p1_acp2 : 30; -+ unsigned int reg_mac_txvector_p1_acp2_rts : 1; -+ unsigned int reg_mac_txvector_p1_acp2_cts : 1; -+ } b; -+} MAC_TXVECTOR_P1_ACP2_FIELD_T; -+ -+#define MAC_TXVECTOR_P1_ACP3 (WIFI_MAC_TX_REG_BASE + 0x29c) -+// Bit 29 :0 reg_mac_txvector_p1_acp3 U RW default = 'h0 -+// Bit 30 reg_mac_txvector_p1_acp3_rts U RW default = 'h0 -+// Bit 31 reg_mac_txvector_p1_acp3_cts U RW default = 'h0 -+typedef union MAC_TXVECTOR_P1_ACP3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_txvector_p1_acp3 : 30; -+ unsigned int reg_mac_txvector_p1_acp3_rts : 1; -+ unsigned int reg_mac_txvector_p1_acp3_cts : 1; -+ } b; -+} MAC_TXVECTOR_P1_ACP3_FIELD_T; -+ -+#define MAC_TXVECTOR_P1_ACP4 (WIFI_MAC_TX_REG_BASE + 0x2a0) -+// Bit 29 :0 reg_mac_txvector_p1_acp4 U RW default = 'h0 -+// Bit 30 reg_mac_txvector_p1_acp4_rts U RW default = 'h0 -+// Bit 31 reg_mac_txvector_p1_acp4_cts U RW default = 'h0 -+typedef union MAC_TXVECTOR_P1_ACP4_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_txvector_p1_acp4 : 30; -+ unsigned int reg_mac_txvector_p1_acp4_rts : 1; -+ unsigned int reg_mac_txvector_p1_acp4_cts : 1; -+ } b; -+} MAC_TXVECTOR_P1_ACP4_FIELD_T; -+ -+#define MAC_TXVECTOR_P1_ACP5 (WIFI_MAC_TX_REG_BASE + 0x2a4) -+// Bit 29 :0 reg_mac_txvector_p1_acp5 U RW default = 'h0 -+// Bit 30 reg_mac_txvector_p1_acp5_rts U RW default = 'h0 -+// Bit 31 reg_mac_txvector_p1_acp5_cts U RW default = 'h0 -+typedef union MAC_TXVECTOR_P1_ACP5_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_txvector_p1_acp5 : 30; -+ unsigned int reg_mac_txvector_p1_acp5_rts : 1; -+ unsigned int reg_mac_txvector_p1_acp5_cts : 1; -+ } b; -+} MAC_TXVECTOR_P1_ACP5_FIELD_T; -+ -+#define MAC_TXVECTOR_P1_ACP6 (WIFI_MAC_TX_REG_BASE + 0x2a8) -+// Bit 29 :0 reg_mac_txvector_p1_acp6 U RW default = 'h0 -+// Bit 30 reg_mac_txvector_p1_acp6_rts U RW default = 'h0 -+// Bit 31 reg_mac_txvector_p1_acp6_cts U RW default = 'h0 -+typedef union MAC_TXVECTOR_P1_ACP6_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_txvector_p1_acp6 : 30; -+ unsigned int reg_mac_txvector_p1_acp6_rts : 1; -+ unsigned int reg_mac_txvector_p1_acp6_cts : 1; -+ } b; -+} MAC_TXVECTOR_P1_ACP6_FIELD_T; -+ -+#define MAC_TXVECTOR_P1_ACP7 (WIFI_MAC_TX_REG_BASE + 0x2ac) -+// Bit 29 :0 reg_mac_txvector_p1_acp7 U RW default = 'h0 -+// Bit 30 reg_mac_txvector_p1_acp7_rts U RW default = 'h0 -+// Bit 31 reg_mac_txvector_p1_acp7_cts U RW default = 'h0 -+typedef union MAC_TXVECTOR_P1_ACP7_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_txvector_p1_acp7 : 30; -+ unsigned int reg_mac_txvector_p1_acp7_rts : 1; -+ unsigned int reg_mac_txvector_p1_acp7_cts : 1; -+ } b; -+} MAC_TXVECTOR_P1_ACP7_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL0 (WIFI_MAC_TX_REG_BASE + 0x2b4) -+// Bit 31 :0 reg_mac_rxpkt_control0 U RW default = 'he0000000 -+typedef union MAC_RXPKT_CONTROL0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control0 : 32; -+ } b; -+} MAC_RXPKT_CONTROL0_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL2 (WIFI_MAC_TX_REG_BASE + 0x2b8) -+// Bit 31 :0 reg_mac_rxpkt_control2 U RW default = 'he0000000 -+typedef union MAC_RXPKT_CONTROL2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control2 : 32; -+ } b; -+} MAC_RXPKT_CONTROL2_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL3 (WIFI_MAC_TX_REG_BASE + 0x2bc) -+// Bit 31 :0 reg_mac_rxpkt_control3 U RW default = 'h0 -+typedef union MAC_RXPKT_CONTROL3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control3 : 32; -+ } b; -+} MAC_RXPKT_CONTROL3_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL4 (WIFI_MAC_TX_REG_BASE + 0x2c0) -+// Bit 31 :0 reg_mac_rxpkt_control4 U RW default = 'he0000000 -+typedef union MAC_RXPKT_CONTROL4_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control4 : 32; -+ } b; -+} MAC_RXPKT_CONTROL4_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL6 (WIFI_MAC_TX_REG_BASE + 0x2c4) -+// Bit 31 :0 reg_mac_rxpkt_control6 U RW default = 'h20000000 -+typedef union MAC_RXPKT_CONTROL6_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control6 : 32; -+ } b; -+} MAC_RXPKT_CONTROL6_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL7 (WIFI_MAC_TX_REG_BASE + 0x2c8) -+// Bit 31 :0 reg_mac_rxpkt_control7 U RW default = 'h0 -+typedef union MAC_RXPKT_CONTROL7_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control7 : 32; -+ } b; -+} MAC_RXPKT_CONTROL7_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL8 (WIFI_MAC_TX_REG_BASE + 0x2cc) -+// Bit 31 :0 reg_mac_rxpkt_control8 U RW default = 'he0000000 -+typedef union MAC_RXPKT_CONTROL8_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control8 : 32; -+ } b; -+} MAC_RXPKT_CONTROL8_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL10 (WIFI_MAC_TX_REG_BASE + 0x2d0) -+// Bit 31 :0 reg_mac_rxpkt_control10 U RW default = 'h20000000 -+typedef union MAC_RXPKT_CONTROL10_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control10 : 32; -+ } b; -+} MAC_RXPKT_CONTROL10_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL11 (WIFI_MAC_TX_REG_BASE + 0x2d4) -+// Bit 31 :0 reg_mac_rxpkt_control11 U RW default = 'h0 -+typedef union MAC_RXPKT_CONTROL11_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control11 : 32; -+ } b; -+} MAC_RXPKT_CONTROL11_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL12 (WIFI_MAC_TX_REG_BASE + 0x2d8) -+// Bit 31 :0 reg_mac_rxpkt_control12 U RW default = 'he0000000 -+typedef union MAC_RXPKT_CONTROL12_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control12 : 32; -+ } b; -+} MAC_RXPKT_CONTROL12_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL14 (WIFI_MAC_TX_REG_BASE + 0x2dc) -+// Bit 31 :0 reg_mac_rxpkt_control14 U RW default = 'h20000000 -+typedef union MAC_RXPKT_CONTROL14_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control14 : 32; -+ } b; -+} MAC_RXPKT_CONTROL14_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL16 (WIFI_MAC_TX_REG_BASE + 0x2e0) -+// Bit 31 :0 reg_mac_rxpkt_control16 U RW default = 'he0000000 -+typedef union MAC_RXPKT_CONTROL16_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control16 : 32; -+ } b; -+} MAC_RXPKT_CONTROL16_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL18 (WIFI_MAC_TX_REG_BASE + 0x2e4) -+// Bit 31 :0 reg_mac_rxpkt_control18 U RW default = 'he0000000 -+typedef union MAC_RXPKT_CONTROL18_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control18 : 32; -+ } b; -+} MAC_RXPKT_CONTROL18_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL20 (WIFI_MAC_TX_REG_BASE + 0x2e8) -+// Bit 31 :0 reg_mac_rxpkt_control20 U RW default = 'he0000000 -+typedef union MAC_RXPKT_CONTROL20_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control20 : 32; -+ } b; -+} MAC_RXPKT_CONTROL20_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL22 (WIFI_MAC_TX_REG_BASE + 0x2ec) -+// Bit 31 :0 reg_mac_rxpkt_control22 U RW default = 'h0 -+typedef union MAC_RXPKT_CONTROL22_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control22 : 32; -+ } b; -+} MAC_RXPKT_CONTROL22_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL26 (WIFI_MAC_TX_REG_BASE + 0x2f0) -+// Bit 31 :0 reg_mac_rxpkt_control26 U RW default = 'h0 -+typedef union MAC_RXPKT_CONTROL26_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control26 : 32; -+ } b; -+} MAC_RXPKT_CONTROL26_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL29 (WIFI_MAC_TX_REG_BASE + 0x2f4) -+// Bit 31 :0 reg_mac_rxpkt_control29 U RW default = 'he0000000 -+typedef union MAC_RXPKT_CONTROL29_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control29 : 32; -+ } b; -+} MAC_RXPKT_CONTROL29_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL30 (WIFI_MAC_TX_REG_BASE + 0x2f8) -+// Bit 31 :0 reg_mac_rxpkt_control30 U RW default = 'h0 -+typedef union MAC_RXPKT_CONTROL30_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control30 : 32; -+ } b; -+} MAC_RXPKT_CONTROL30_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL32 (WIFI_MAC_TX_REG_BASE + 0x2fc) -+// Bit 31 :0 reg_mac_rxpkt_control32 U RW default = 'h20000000 -+typedef union MAC_RXPKT_CONTROL32_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control32 : 32; -+ } b; -+} MAC_RXPKT_CONTROL32_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL33 (WIFI_MAC_TX_REG_BASE + 0x300) -+// Bit 31 :0 reg_mac_rxpkt_control33 U RW default = 'hc0000000 -+typedef union MAC_RXPKT_CONTROL33_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control33 : 32; -+ } b; -+} MAC_RXPKT_CONTROL33_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL34 (WIFI_MAC_TX_REG_BASE + 0x304) -+// Bit 31 :0 reg_mac_rxpkt_control34 U RW default = 'he0000000 -+typedef union MAC_RXPKT_CONTROL34_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control34 : 32; -+ } b; -+} MAC_RXPKT_CONTROL34_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL36 (WIFI_MAC_TX_REG_BASE + 0x308) -+// Bit 31 :0 reg_mac_rxpkt_control36 U RW default = 'h20000000 -+typedef union MAC_RXPKT_CONTROL36_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control36 : 32; -+ } b; -+} MAC_RXPKT_CONTROL36_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL37 (WIFI_MAC_TX_REG_BASE + 0x30c) -+// Bit 31 :0 reg_mac_rxpkt_control37 U RW default = 'h0 -+typedef union MAC_RXPKT_CONTROL37_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control37 : 32; -+ } b; -+} MAC_RXPKT_CONTROL37_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL38 (WIFI_MAC_TX_REG_BASE + 0x310) -+// Bit 31 :0 reg_mac_rxpkt_control38 U RW default = 'h20000000 -+typedef union MAC_RXPKT_CONTROL38_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control38 : 32; -+ } b; -+} MAC_RXPKT_CONTROL38_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL40 (WIFI_MAC_TX_REG_BASE + 0x314) -+// Bit 31 :0 reg_mac_rxpkt_control40 U RW default = 'he0000000 -+typedef union MAC_RXPKT_CONTROL40_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control40 : 32; -+ } b; -+} MAC_RXPKT_CONTROL40_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL41 (WIFI_MAC_TX_REG_BASE + 0x318) -+// Bit 31 :0 reg_mac_rxpkt_control41 U RW default = 'he0000000 -+typedef union MAC_RXPKT_CONTROL41_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control41 : 32; -+ } b; -+} MAC_RXPKT_CONTROL41_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL42 (WIFI_MAC_TX_REG_BASE + 0x31c) -+// Bit 31 :0 reg_mac_rxpkt_control42 U RW default = 'h20000000 -+typedef union MAC_RXPKT_CONTROL42_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control42 : 32; -+ } b; -+} MAC_RXPKT_CONTROL42_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL44 (WIFI_MAC_TX_REG_BASE + 0x320) -+// Bit 31 :0 reg_mac_rxpkt_control44 U RW default = 'he0000000 -+typedef union MAC_RXPKT_CONTROL44_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control44 : 32; -+ } b; -+} MAC_RXPKT_CONTROL44_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL45 (WIFI_MAC_TX_REG_BASE + 0x324) -+// Bit 31 :0 reg_mac_rxpkt_control45 U RW default = 'hc0000000 -+typedef union MAC_RXPKT_CONTROL45_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control45 : 32; -+ } b; -+} MAC_RXPKT_CONTROL45_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL46 (WIFI_MAC_TX_REG_BASE + 0x328) -+// Bit 31 :0 reg_mac_rxpkt_control46 U RW default = 'h20000000 -+typedef union MAC_RXPKT_CONTROL46_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control46 : 32; -+ } b; -+} MAC_RXPKT_CONTROL46_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL48 (WIFI_MAC_TX_REG_BASE + 0x32c) -+// Bit 31 :0 reg_mac_rxpkt_control48 U RW default = 'he0000000 -+typedef union MAC_RXPKT_CONTROL48_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control48 : 32; -+ } b; -+} MAC_RXPKT_CONTROL48_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL49 (WIFI_MAC_TX_REG_BASE + 0x330) -+// Bit 31 :0 reg_mac_rxpkt_control49 U RW default = 'h0 -+typedef union MAC_RXPKT_CONTROL49_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control49 : 32; -+ } b; -+} MAC_RXPKT_CONTROL49_FIELD_T; -+ -+#define MAC_RXPKT_CONTROL50 (WIFI_MAC_TX_REG_BASE + 0x334) -+// Bit 31 :0 reg_mac_rxpkt_control50 U RW default = 'he0000000 -+typedef union MAC_RXPKT_CONTROL50_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control50 : 32; -+ } b; -+} MAC_RXPKT_CONTROL50_FIELD_T; ++struct sts_agc_state { ++ unsigned int rsv1:8,state:4,rsv2:20; ++}; + -+#define MAC_RXPKT_CONTROL52 (WIFI_MAC_TX_REG_BASE + 0x338) -+// Bit 31 :0 reg_mac_rxpkt_control52 U RW default = 'he0000000 -+typedef union MAC_RXPKT_CONTROL52_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control52 : 32; -+ } b; -+} MAC_RXPKT_CONTROL52_FIELD_T; ++struct sts_agc_ob_ic_gain { ++ unsigned int r_rx_ic_gain:8,r_agc_fine_db:9,rsv:15; ++}; + -+#define MAC_RXPKT_CONTROL53 (WIFI_MAC_TX_REG_BASE + 0x33c) -+// Bit 31 :0 reg_mac_rxpkt_control53 U RW default = 'h0 -+typedef union MAC_RXPKT_CONTROL53_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control53 : 32; -+ } b; -+} MAC_RXPKT_CONTROL53_FIELD_T; ++struct sts_agc_watch1 { ++ unsigned int r_pow_sat_db:9, rsv1:3, r_primary20_db:9, rsv2:11; ++}; + -+#define MAC_RXPKT_CONTROL56 (WIFI_MAC_TX_REG_BASE + 0x340) -+// Bit 31 :0 reg_mac_rxpkt_control56 U RW default = 'h20000000 -+typedef union MAC_RXPKT_CONTROL56_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control56 : 32; -+ } b; -+} MAC_RXPKT_CONTROL56_FIELD_T; ++struct sts_agc_watch2 { ++ unsigned int r_primary40_db:9, rsv1:3,r_primary80_db:9,rsv2:11; ++}; + -+#define MAC_RXPKT_CONTROL57 (WIFI_MAC_TX_REG_BASE + 0x344) -+// Bit 31 :0 reg_mac_rxpkt_control57 U RW default = 'h0 -+typedef union MAC_RXPKT_CONTROL57_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control57 : 32; -+ } b; -+} MAC_RXPKT_CONTROL57_FIELD_T; ++struct sts_agc_watch3 { ++ unsigned int r_rssi0_db:10, rsv1:2,r_rssi1_db:10,rsv2:10; ++}; + -+#define MAC_RXPKT_CONTROL58 (WIFI_MAC_TX_REG_BASE + 0x348) -+// Bit 31 :0 reg_mac_rxpkt_control58 U RW default = 'h20000000 -+typedef union MAC_RXPKT_CONTROL58_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control58 : 32; -+ } b; -+} MAC_RXPKT_CONTROL58_FIELD_T; ++struct sts_agc_watch4 { ++ unsigned int r_rssi2_db:10, rsv1:2,r_rssi3_db:10,rsv2:10; ++}; + -+#define MAC_RXPKT_CONTROL61 (WIFI_MAC_TX_REG_BASE + 0x34c) -+// Bit 31 :0 reg_mac_rxpkt_control61 U RW default = 'h0 -+typedef union MAC_RXPKT_CONTROL61_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control61 : 32; -+ } b; -+} MAC_RXPKT_CONTROL61_FIELD_T; ++struct sts_ob_ant_nfloor { ++ unsigned int r_snr_qdb:10, rsv1:2,r_ant_nfloor_qdb:10,rsv2:10; ++}; + -+#define MAC_RXPKT_CONTROL62 (WIFI_MAC_TX_REG_BASE + 0x350) -+// Bit 31 :0 reg_mac_rxpkt_control62 U RW default = 'h20000000 -+typedef union MAC_RXPKT_CONTROL62_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control62 : 32; -+ } b; -+} MAC_RXPKT_CONTROL62_FIELD_T; ++struct sts_ob_cca_res { ++ unsigned int cca_cond_rdy:1, rsv1:15, cca_cond8:16; ++}; + -+#define MAC_RXPKT_CONTROL24 (WIFI_MAC_TX_REG_BASE + 0x354) -+// Bit 31 :0 reg_mac_rxpkt_control24 U RW default = 'h20000000 -+typedef union MAC_RXPKT_CONTROL24_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control24 : 32; -+ } b; -+} MAC_RXPKT_CONTROL24_FIELD_T; ++struct sts_ob_cca_cond01 { ++ unsigned int cca_cond0:16, cca_cond1:16; ++}; + -+#define MAC_11B_LUT_1M (WIFI_MAC_TX_REG_BASE + 0x358) -+// Bit 31 :0 reg_mac_11b_lut_1m U RW default = 'h0 -+typedef union MAC_11B_LUT_1M_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11b_lut_1m : 32; -+ } b; -+} MAC_11B_LUT_1M_FIELD_T; ++struct sts_ob_cca_cond23 { ++ unsigned int cca_cond2:16, cca_cond3:16; ++}; + -+#define MAC_11B_LUT_2M (WIFI_MAC_TX_REG_BASE + 0x35c) -+// Bit 31 :0 reg_mac_11b_lut_2m U RW default = 'h11010000 -+typedef union MAC_11B_LUT_2M_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11b_lut_2m : 32; -+ } b; -+} MAC_11B_LUT_2M_FIELD_T; ++union sts_agc_reg_u { ++ struct sts_agc_state state; ++ struct sts_agc_ob_ic_gain ic_gain; ++ struct sts_agc_watch1 wtc1; ++ struct sts_agc_watch2 wtc2; ++ struct sts_agc_watch3 wtc3; ++ struct sts_agc_watch4 wtc4; ++ struct sts_ob_ant_nfloor ant_nfloor; ++ struct sts_ob_cca_res cca_res; ++ struct sts_ob_cca_cond01 cca_cond_m1; ++ struct sts_ob_cca_cond23 cca_cond_m2; ++}; + -+#define MAC_11B_LUT_5M (WIFI_MAC_TX_REG_BASE + 0x360) -+// Bit 31 :0 reg_mac_11b_lut_5m U RW default = 'h22020202 -+typedef union MAC_11B_LUT_5M_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11b_lut_5m : 32; -+ } b; -+} MAC_11B_LUT_5M_FIELD_T; ++#pragma pack(pop) + -+#define MAC_11B_LUT_11M (WIFI_MAC_TX_REG_BASE + 0x364) -+// Bit 31 :0 reg_mac_11b_lut_11m U RW default = 'h33030303 -+typedef union MAC_11B_LUT_11M_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11b_lut_11m : 32; -+ } b; -+} MAC_11B_LUT_11M_FIELD_T; ++#endif +diff --git a/drivers/net/wireless/w1/common/wifi_aon_addr.h b/drivers/net/wireless/w1/common/wifi_aon_addr.h +new file mode 100644 +index 0000000000000000000000000000000000000000..3a38a28fe50a813951ffdb2bfd08c951c20c2018 +--- /dev/null ++++ b/drivers/net/wireless/w1/common/wifi_aon_addr.h +@@ -0,0 +1,24 @@ ++#ifndef __ADDR_AON_H__ ++#define __ADDR_AON_H__ + -+#define MAC_11G_LUT_6M (WIFI_MAC_TX_REG_BASE + 0x368) -+// Bit 31 :0 reg_mac_11g_lut_6m U RW default = 'h44040404 -+typedef union MAC_11G_LUT_6M_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11g_lut_6m : 32; -+ } b; -+} MAC_11G_LUT_6M_FIELD_T; + -+#define MAC_11G_LUT_9M (WIFI_MAC_TX_REG_BASE + 0x36c) -+// Bit 31 :0 reg_mac_11g_lut_9m U RW default = 'h44050505 -+typedef union MAC_11G_LUT_9M_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11g_lut_9m : 32; -+ } b; -+} MAC_11G_LUT_9M_FIELD_T; ++//#define WIFI_AON (0xf800) ++#define WIFI_AON (0x00F00000) + -+#define MAC_11G_LUT_12M (WIFI_MAC_TX_REG_BASE + 0x370) -+// Bit 31 :0 reg_mac_11g_lut_12m U RW default = 'h55060606 -+typedef union MAC_11G_LUT_12M_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11g_lut_12m : 32; -+ } b; -+} MAC_11G_LUT_12M_FIELD_T; ++// pmu status ++#define PMU_PWR_OFF 0x0 ++#define PMU_PWR_XOSC 0x1 ++#define PMU_XOSC_WAIT 0x2 ++#define PMU_XOSC_DPLL 0x3 ++#define PMU_DPLL_WAIT 0x4 ++#define PMU_DPLL_ACT 0x5 ++#define PMU_ACT_MODE 0x6 ++#define PMU_ACT_SLEEP 0x7 ++#define PMU_SLEEP_MODE 0x8 ++#define PMU_SLEEP_WAKE 0x9 ++#define PMU_WAKE_WAIT 0xa ++#define PMU_WAKE_XOSC 0xb + -+#define MAC_11G_LUT_18M (WIFI_MAC_TX_REG_BASE + 0x374) -+// Bit 31 :0 reg_mac_11g_lut_18m U RW default = 'h55060606 -+typedef union MAC_11G_LUT_18M_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11g_lut_18m : 32; -+ } b; -+} MAC_11G_LUT_18M_FIELD_T; ++#define WIFI_RG_AON_CFG4 (WIFI_AON + 0x78) ++#define WIFI_RG_AON_CFG5 (WIFI_AON + 0x7C) ++#endif +diff --git a/drivers/net/wireless/w1/common/wifi_coex_addr.h b/drivers/net/wireless/w1/common/wifi_coex_addr.h +new file mode 100644 +index 0000000000000000000000000000000000000000..68be97d11a79ae26359c722a1b05889fa087cfb0 +--- /dev/null ++++ b/drivers/net/wireless/w1/common/wifi_coex_addr.h +@@ -0,0 +1,34 @@ ++#ifndef __WIFI_COEX_ADDR_H__ ++#define __WIFI_COEX_ADDR_H__ + -+#define MAC_11G_LUT_24M (WIFI_MAC_TX_REG_BASE + 0x378) -+// Bit 31 :0 reg_mac_11g_lut_24m U RW default = 'h56060606 -+typedef union MAC_11G_LUT_24M_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11g_lut_24m : 32; -+ } b; -+} MAC_11G_LUT_24M_FIELD_T; ++#define WIFI_COEX (0x00f06000) + -+#define MAC_11G_LUT_36M (WIFI_MAC_TX_REG_BASE + 0x37c) -+// Bit 31 :0 reg_mac_11g_lut_36m U RW default = 'h66080608 -+typedef union MAC_11G_LUT_36M_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11g_lut_36m : 32; -+ } b; -+} MAC_11G_LUT_36M_FIELD_T; ++#define RG_COEX_PRIORITY_M6 (WIFI_COEX + 0xbc) ++#define RG_COEX_PRD_NUM_M6 (WIFI_COEX + 0xc0) ++#define RG_COEX_ACT_NUM_M6 (WIFI_COEX + 0xc4) ++#define RG_COEX_OFFSET_NUM_M6 (WIFI_COEX + 0xc8) ++#define RG_COEX_INT_OFFSET_M6 (WIFI_COEX + 0xcc) ++#define RG_COEX_INI2_OFFSET_M6 (WIFI_COEX + 0xd0) + -+#define MAC_11G_LUT_48M (WIFI_MAC_TX_REG_BASE + 0x380) -+// Bit 31 :0 reg_mac_11g_lut_48m U RW default = 'h67080608 -+typedef union MAC_11G_LUT_48M_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11g_lut_48m : 32; -+ } b; -+} MAC_11G_LUT_48M_FIELD_T; ++#define RG_COEX_HS5W_MANUAL0 (WIFI_COEX + 0x4) ++#define RG_COEX_HS5W_MANUAL1 (WIFI_COEX + 0x8) ++#define RG_COEX_HS5W_MANUAL2 (WIFI_COEX + 0xc) ++#define RG_COEX_HS5W_MANUAL3 (WIFI_COEX + 0x10) ++#define RG_COEX_HS5W_MANUAL4 (WIFI_COEX + 0x14) + -+#define MAC_11G_LUT_54M (WIFI_MAC_TX_REG_BASE + 0x384) -+// Bit 31 :0 reg_mac_11g_lut_54m U RW default = 'h67080608 -+typedef union MAC_11G_LUT_54M_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11g_lut_54m : 32; -+ } b; -+} MAC_11G_LUT_54M_FIELD_T; ++#define RG_COEX_HS5W_CTRL0 (WIFI_COEX + 0x18) ++#define RG_COEX_HS5W_CTRL1 (WIFI_COEX + 0x1c) + -+#define MAC_11N_LUT_MCS0 (WIFI_MAC_TX_REG_BASE + 0x388) -+// Bit 31 :0 reg_mac_11n_lut_mcs0 U RW default = 'h88800404 -+typedef union MAC_11N_LUT_MCS0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11n_lut_mcs0 : 32; -+ } b; -+} MAC_11N_LUT_MCS0_FIELD_T; ++#define RG_COEX_RF_STABLE_CTRL (WIFI_COEX + 0x20) ++#define RG_COEX_BT_OWNER_CTRL (WIFI_COEX + 0x24) ++#define RG_COEX_WF_OWNER_CTRL (WIFI_COEX + 0x28) + -+#define MAC_11N_LUT_MCS1 (WIFI_MAC_TX_REG_BASE + 0x38c) -+// Bit 31 :0 reg_mac_11n_lut_mcs1 U RW default = 'h99810606 -+typedef union MAC_11N_LUT_MCS1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11n_lut_mcs1 : 32; -+ } b; -+} MAC_11N_LUT_MCS1_FIELD_T; ++#define RG_COEX_BT_LOGIC_INFO (WIFI_COEX + 0x200) ++#define COEX_EN_ESCO (0x00000010) ++#define RG_COEX_CFG1 (WIFI_COEX + 0x19c) ++#define RG_COEX_IRQ_END_TIME (WIFI_COEX + 0x304) ++#define RG_COEX_WF_IRQ_MSK (WIFI_COEX + 0x39c) ++#define RG_COEX_BT_IRQ_MSK (WIFI_COEX + 0x3a0) + -+#define MAC_11N_LUT_MCS2 (WIFI_MAC_TX_REG_BASE + 0x390) -+// Bit 31 :0 reg_mac_11n_lut_mcs2 U RW default = 'h9a810606 -+typedef union MAC_11N_LUT_MCS2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11n_lut_mcs2 : 32; -+ } b; -+} MAC_11N_LUT_MCS2_FIELD_T; ++#endif + -+#define MAC_11N_LUT_MCS3 (WIFI_MAC_TX_REG_BASE + 0x394) -+// Bit 31 :0 reg_mac_11n_lut_mcs3 U RW default = 'hbb830608 -+typedef union MAC_11N_LUT_MCS3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11n_lut_mcs3 : 32; -+ } b; -+} MAC_11N_LUT_MCS3_FIELD_T; +diff --git a/drivers/net/wireless/w1/common/wifi_i2c_addr.h b/drivers/net/wireless/w1/common/wifi_i2c_addr.h +new file mode 100644 +index 0000000000000000000000000000000000000000..54b3762e3b23357c556c2c1127bb41fb62a07e0e +--- /dev/null ++++ b/drivers/net/wireless/w1/common/wifi_i2c_addr.h +@@ -0,0 +1,14 @@ ++#ifndef __WIFI_I2C_ADDR_H__ ++#define __WIFI_I2C_ADDR_H__ + -+#define MAC_11N_LUT_MCS4 (WIFI_MAC_TX_REG_BASE + 0x398) -+// Bit 31 :0 reg_mac_11n_lut_mcs4 U RW default = 'hbc830608 -+typedef union MAC_11N_LUT_MCS4_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11n_lut_mcs4 : 32; -+ } b; -+} MAC_11N_LUT_MCS4_FIELD_T; ++#define WIFI_I2C (0x4800) + -+#define MAC_11N_LUT_MCS5 (WIFI_MAC_TX_REG_BASE + 0x39c) -+// Bit 31 :0 reg_mac_11n_lut_mcs5 U RW default = 'hbd830608 -+typedef union MAC_11N_LUT_MCS5_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11n_lut_mcs5 : 32; -+ } b; -+} MAC_11N_LUT_MCS5_FIELD_T; ++#define WIFI_I2C_M0_CONTROL_REG (WIFI_I2C + (0x00 << 2)) ++#define WIFI_I2C_M0_SLAVE_ADDR (WIFI_I2C + (0x01 << 2)) ++#define WIFI_I2C_M0_TOKEN_LIST0 (WIFI_I2C + (0x02 << 2)) ++#define WIFI_I2C_M0_TOKEN_LIST1 (WIFI_I2C + (0x03 << 2)) ++#define WIFI_I2C_M0_WDATA_REG0 (WIFI_I2C + (0x04 << 2)) ++#define WIFI_I2C_M0_WDATA_REG1 (WIFI_I2C + (0x05 << 2)) ++#define WIFI_I2C_M0_RDATA_REG0 (WIFI_I2C + (0x06 << 2)) + -+#define MAC_11N_LUT_MCS6 (WIFI_MAC_TX_REG_BASE + 0x3a0) -+// Bit 31 :0 reg_mac_11n_lut_mcs6 U RW default = 'hbe830608 -+typedef union MAC_11N_LUT_MCS6_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11n_lut_mcs6 : 32; -+ } b; -+} MAC_11N_LUT_MCS6_FIELD_T; ++#endif +diff --git a/drivers/net/wireless/w1/common/wifi_intf_addr.h b/drivers/net/wireless/w1/common/wifi_intf_addr.h +new file mode 100644 +index 0000000000000000000000000000000000000000..7ec21d85f4a191e947fc6ccbd048a16c61b173fd +--- /dev/null ++++ b/drivers/net/wireless/w1/common/wifi_intf_addr.h +@@ -0,0 +1,26 @@ ++#ifndef __ADDR_INTF_H__ ++#define __ADDR_INTF_H__ + -+#define MAC_11N_LUT_MCS7 (WIFI_MAC_TX_REG_BASE + 0x3a4) -+// Bit 31 :0 reg_mac_11n_lut_mcs7 U RW default = 'hbe830606 -+typedef union MAC_11N_LUT_MCS7_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11n_lut_mcs7 : 32; -+ } b; -+} MAC_11N_LUT_MCS7_FIELD_T; + -+#define MAC_11AC_LUT_MCS0 (WIFI_MAC_TX_REG_BASE + 0x3a8) -+// Bit 31 :0 reg_mac_11ac_lut_mcs0 U RW default = 'h48040404 -+typedef union MAC_11AC_LUT_MCS0_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11ac_lut_mcs0 : 32; -+ } b; -+} MAC_11AC_LUT_MCS0_FIELD_T; ++#define WIFI_INTF (0xd000) + -+#define MAC_11AC_LUT_MCS1 (WIFI_MAC_TX_REG_BASE + 0x3ac) -+// Bit 31 :0 reg_mac_11ac_lut_mcs1 U RW default = 'h59060606 -+typedef union MAC_11AC_LUT_MCS1_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11ac_lut_mcs1 : 32; -+ } b; -+} MAC_11AC_LUT_MCS1_FIELD_T; ++#define RG_INTF_CTRL_CLK (WIFI_INTF + 0xb0) ++#define RG_INTF_CPU_CLK (WIFI_INTF + 0x090) ++#define RG_INTF_APB_CLK (WIFI_INTF + 0x094) ++#define RG_INTF_MAC_CLK (WIFI_INTF + 0x098) ++#define RG_INTF_DAC_CLK (WIFI_INTF + 0x0a0) ++#define RG_INTF_ADC_CLK (WIFI_INTF + 0x0a4) ++#define RG_INTF_VIT_CLK (WIFI_INTF + 0x0ac) ++#define RG_INTF_11BRX_CLK (WIFI_INTF + 0x0bc) ++#define RG_INTF_320M_CLK (WIFI_INTF + 0x100) ++#define RG_INTF_240M_CLK (WIFI_INTF + 0x104) ++#define RG_INTF_BTCPU_CLK (WIFI_INTF + 0x108) ++#define RG_INTF_BTMAC_CLK (WIFI_INTF + 0x10c) ++#define RG_INTF_LDPC_CLK (WIFI_INTF + 0x118) ++#define RG_INTF_PIN_MUX_REG1 (WIFI_INTF + 0x004) ++#define RG_INTF_SHARE_64K_CAP (WIFI_INTF + 0x0e4) ++#define RG_INTF_PHY_CLK (WIFI_INTF + 0x0a8) ++#define RG_INTF_RTC_CLK_CTRL (WIFI_INTF + 0xc0) ++#define RG_INTF_MAC_TIMER_CTRL1 (WIFI_INTF + 0xd0) + -+#define MAC_11AC_LUT_MCS2 (WIFI_MAC_TX_REG_BASE + 0x3b0) -+// Bit 31 :0 reg_mac_11ac_lut_mcs2 U RW default = 'h5a060606 -+typedef union MAC_11AC_LUT_MCS2_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11ac_lut_mcs2 : 32; -+ } b; -+} MAC_11AC_LUT_MCS2_FIELD_T; ++#endif +diff --git a/drivers/net/wireless/w1/common/wifi_mac_addr.h b/drivers/net/wireless/w1/common/wifi_mac_addr.h +new file mode 100644 +index 0000000000000000000000000000000000000000..b3cc16e976daf0138cd992e8383206593e9b943d +--- /dev/null ++++ b/drivers/net/wireless/w1/common/wifi_mac_addr.h +@@ -0,0 +1,109 @@ ++#ifndef __WIFI_MAC_ADDR_H__ ++#define __WIFI_MAC_ADDR_H__ + -+#define MAC_11AC_LUT_MCS3 (WIFI_MAC_TX_REG_BASE + 0x3b4) -+// Bit 31 :0 reg_mac_11ac_lut_mcs3 U RW default = 'h6b080608 -+typedef union MAC_11AC_LUT_MCS3_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11ac_lut_mcs3 : 32; -+ } b; -+} MAC_11AC_LUT_MCS3_FIELD_T; ++#define WIFI_MAC (0x0000) ++#define RG_MAC_COUNT1 (WIFI_MAC + 0xb0) ++#define RG_MAC_LOCAL_ADDRL0 (WIFI_MAC+0X1c) ++#define RG_MAC_LOCAL_ADDRH0 (WIFI_MAC+0X20) + -+#define MAC_11AC_LUT_MCS4 (WIFI_MAC_TX_REG_BASE + 0x3b8) -+// Bit 31 :0 reg_mac_11ac_lut_mcs4 U RW default = 'h6c080608 -+typedef union MAC_11AC_LUT_MCS4_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11ac_lut_mcs4 : 32; -+ } b; -+} MAC_11AC_LUT_MCS4_FIELD_T; ++#define RG_MAC_BSSID0LO_REG (WIFI_MAC+0x3c) ++#define RG_MAC_BSSID0HI_REG (WIFI_MAC+0x40) + -+#define MAC_11AC_LUT_MCS5 (WIFI_MAC_TX_REG_BASE + 0x3bc) -+// Bit 31 :0 reg_mac_11ac_lut_mcs5 U RW default = 'h6d080608 -+typedef union MAC_11AC_LUT_MCS5_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11ac_lut_mcs5 : 32; -+ } b; -+} MAC_11AC_LUT_MCS5_FIELD_T; ++#define RG_MAC_COUNT2 (WIFI_MAC+0Xb4) ++#define RG_MAC_CHANNEL_INDEX (WIFI_MAC+0X1e0) ++#define RG_MAC_BSSIDLO_N(_vid) (RG_MAC_BSSID0LO_REG+(_vid)*8) ++#define RG_MAC_BSSIDHI_N(_vid) (RG_MAC_BSSID0HI_REG+(_vid)*8) ++#define RG_MAC_LOCAL_ADDRLN(_vid) (RG_MAC_LOCAL_ADDRL0+(_vid)*8) ++#define RG_MAC_LOCAL_ADDRHN(_vid) (RG_MAC_LOCAL_ADDRH0+(_vid)*8) + -+#define MAC_11AC_LUT_MCS6 (WIFI_MAC_TX_REG_BASE + 0x3c0) -+// Bit 31 :0 reg_mac_11ac_lut_mcs6 U RW default = 'h6e080608 -+typedef union MAC_11AC_LUT_MCS6_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11ac_lut_mcs6 : 32; -+ } b; -+} MAC_11AC_LUT_MCS6_FIELD_T; ++#define RG_MAC_CNT_CTRL_FIQ (WIFI_MAC + 0x5c ) ++#define RG_MAC_FRM_TYPE_CNT_CTRL (WIFI_MAC + 0xa4) ++#define RG_MAC_RX_DATA_LOCAL_CNT (WIFI_MAC + 0x1b8) ++#define RG_MAC_RX_DATA_OTHER_CNT (WIFI_MAC + 0x1bc) ++#define RG_MAC_RX_DATA_MUTIL_CNT (WIFI_MAC + 0x1c0) ++#define RG_MAC_TX_STT_CHK (WIFI_MAC + 0x1a8) ++#define RG_MAC_TX_END_CHK (WIFI_MAC + 0x1ac) ++#define RG_MAC_TX_EN_CHK (WIFI_MAC + 0x1b0) ++#define RG_MAC_TX_ENWR_CHK (WIFI_MAC + 0x1b4) + -+#define MAC_11AC_LUT_MCS7 (WIFI_MAC_TX_REG_BASE + 0x3c4) -+// Bit 31 :0 reg_mac_11ac_lut_mcs7 U RW default = 'h6e080608 -+typedef union MAC_11AC_LUT_MCS7_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11ac_lut_mcs7 : 32; -+ } b; -+} MAC_11AC_LUT_MCS7_FIELD_T; ++#define RG_MAC_IRQ_STATUS_CNT0 (WIFI_MAC + 0x60) ++#define RG_MAC_IRQ_STATUS_CNT1 (WIFI_MAC + 0x64) ++#define RG_MAC_IRQ_STATUS_CNT2 (WIFI_MAC + 0x68) ++#define RG_MAC_IRQ_STATUS_CNT3 (WIFI_MAC + 0x74) ++#define RG_MAC_FRM_TYPE_CNT0 (WIFI_MAC + 0xa8) ++#define RG_MAC_FRM_TYPE_CNT1 (WIFI_MAC + 0xac) ++#define RG_MAC_FRM_TYPE_CNT2 (WIFI_MAC + 0xf4) ++#define RG_MAC_FRM_TYPE_CNT3 (WIFI_MAC + 0xf8) ++#define RG_MAC_BCN_CTRL_REG (WIFI_MAC + 0x234) ++#define RG_MAC_RX_WPTR (WIFI_MAC + 0x1fc) ++#define RG_MAC_RX_FRPTR (WIFI_MAC + 0x200) ++#define RG_MAC_RX_HRPTR (WIFI_MAC + 0x204) + -+#define MAC_11AC_LUT_MCS8 (WIFI_MAC_TX_REG_BASE + 0x3c8) -+// Bit 31 :0 reg_mac_11ac_lut_mcs8 U RW default = 'h6f080608 -+typedef union MAC_11AC_LUT_MCS8_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11ac_lut_mcs8 : 32; -+ } b; -+} MAC_11AC_LUT_MCS8_FIELD_T; + -+#define MAC_11AC_LUT_MCS9 (WIFI_MAC_TX_REG_BASE + 0x3cc) -+// Bit 31 :0 reg_mac_11ac_lut_mcs9 U RW default = 'h6f0b080b -+typedef union MAC_11AC_LUT_MCS9_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_11ac_lut_mcs9 : 32; -+ } b; -+} MAC_11AC_LUT_MCS9_FIELD_T; + -+#define VID0_TIMESTAMP_HIGH (WIFI_MAC_TX_REG_BASE + 0x3d0) -+// Bit 31 :0 reg_vid0_timestamp_high U RW default = 'h0 -+typedef union VID0_TIMESTAMP_HIGH_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_vid0_timestamp_high : 32; -+ } b; -+} VID0_TIMESTAMP_HIGH_FIELD_T; ++struct data_rx_local_cnt_bits{ ++ unsigned int data_local_cnt: 29, ++ data_local_cnt_qos:1, ++ data_local_cnt_clr:1, ++ data_local_cnt_en:1; ++}; + -+#define VID0_TIMESTAMP_LOW (WIFI_MAC_TX_REG_BASE + 0x3d4) -+// Bit 31 :0 reg_vid0_timestamp_low U RW default = 'h0 -+typedef union VID0_TIMESTAMP_LOW_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_vid0_timestamp_low : 32; -+ } b; -+} VID0_TIMESTAMP_LOW_FIELD_T; ++struct data_rx_cnt_bits{ ++ unsigned int cnt:30, ++ clr:1, ++ en:1; ++}; + -+#define VID1_TIMESTAMP_HIGH (WIFI_MAC_TX_REG_BASE + 0x3d8) -+// Bit 31 :0 reg_vid1_timestamp_high U RW default = 'h0 -+typedef union VID1_TIMESTAMP_HIGH_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_vid1_timestamp_high : 32; -+ } b; -+} VID1_TIMESTAMP_HIGH_FIELD_T; + -+#define VID1_TIMESTAMP_LOW (WIFI_MAC_TX_REG_BASE + 0x3dc) -+// Bit 31 :0 reg_vid1_timestamp_low U RW default = 'h0 -+typedef union VID1_TIMESTAMP_LOW_FIELD ++struct tx_cnt_ctrl_bits +{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_vid1_timestamp_low : 32; -+ } b; -+} VID1_TIMESTAMP_LOW_FIELD_T; ++ unsigned int cnt :26, ++ en:1, ++ clr:1, ++ rsv:4; ++}; + -+#define VID2_TIMESTAMP_HIGH (WIFI_MAC_TX_REG_BASE + 0x3e0) -+// Bit 31 :0 reg_vid2_timestamp_high U RW default = 'h0 -+typedef union VID2_TIMESTAMP_HIGH_FIELD ++struct cnt_ctrl_bits +{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_vid2_timestamp_high : 32; -+ } b; -+} VID2_TIMESTAMP_HIGH_FIELD_T; ++ unsigned int type_idx0 :6, ++ type_idx1 :6, ++ type_idx2 :6, ++ type_idx3 :6, ++ en0 :1, ++ en1 :1, ++ en2 :1, ++ en3 :1, ++ clr0 :1, ++ clr1 :1, ++ clr2 :1, ++ clr3 :1; ++}; + -+#define VID2_TIMESTAMP_LOW (WIFI_MAC_TX_REG_BASE + 0x3e4) -+// Bit 31 :0 reg_vid2_timestamp_low U RW default = 'h0 -+typedef union VID2_TIMESTAMP_LOW_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_vid2_timestamp_low : 32; -+ } b; -+} VID2_TIMESTAMP_LOW_FIELD_T; + -+#define VID3_TIMESTAMP_HIGH (WIFI_MAC_TX_REG_BASE + 0x3e8) -+// Bit 31 :0 reg_vid3_timestamp_high U RW default = 'h0 -+typedef union VID3_TIMESTAMP_HIGH_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_vid3_timestamp_high : 32; -+ } b; -+} VID3_TIMESTAMP_HIGH_FIELD_T; ++struct ctrl_idx{ ++ unsigned char idx0; ++ unsigned char idx1; ++ unsigned char idx2; ++ unsigned char idx3; ++ unsigned char qos_en; ++}; + -+#define VID3_TIMESTAMP_LOW (WIFI_MAC_TX_REG_BASE + 0x3ec) -+// Bit 31 :0 reg_vid3_timestamp_low U RW default = 'h0 -+typedef union VID3_TIMESTAMP_LOW_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_vid3_timestamp_low : 32; -+ } b; -+} VID3_TIMESTAMP_LOW_FIELD_T; ++union sts_mac_reg_u{ ++ unsigned int x; ++ struct ctrl_idx op_idx; ++ struct tx_cnt_ctrl_bits tx_cnt_ctrl; ++ struct cnt_ctrl_bits cnt_ctrl; ++ struct data_rx_cnt_bits rx_other_cnt; ++ struct data_rx_cnt_bits rx_mutil_cnt; ++ struct data_rx_local_cnt_bits rx_local_cnt; ++}; + -+#define MAC_RXPKT_CONTROL17 (WIFI_MAC_TX_REG_BASE + 0x3f0) -+// Bit 31 :0 reg_mac_rxpkt_control17 U RW default = 'hc0000000 -+typedef union MAC_RXPKT_CONTROL17_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control17 : 32; -+ } b; -+} MAC_RXPKT_CONTROL17_FIELD_T; ++struct sts_irq_ctrl{ ++ unsigned int cnt:29,func_code:3 ; ++}; + -+#define MAC_RXPKT_CONTROL21 (WIFI_MAC_TX_REG_BASE + 0x3f4) -+// Bit 31 :0 reg_mac_rxpkt_control21 U RW default = 'hc0000000 -+typedef union MAC_RXPKT_CONTROL21_FIELD -+{ -+ unsigned int data; -+ struct -+ { -+ unsigned int reg_mac_rxpkt_control21 : 32; -+ } b; -+} MAC_RXPKT_CONTROL21_FIELD_T; ++struct sts_sw_cnt_ctrl{ ++ unsigned int cnt:29,func_code:3 ; ++}; + +#endif -+ +diff --git a/drivers/net/wireless/w1/common/wifi_mac_main_reg.h b/drivers/net/wireless/w1/common/wifi_mac_main_reg.h +new file mode 100644 +index 0000000000000000000000000000000000000000..fbce31e192100ce7d9c7aeff1acc9dae080e62c7 +--- /dev/null ++++ b/drivers/net/wireless/w1/common/wifi_mac_main_reg.h +@@ -0,0 +1,1085 @@ ++#ifdef WIFI_MAC_MAIN_REG ++#else ++#define WIFI_MAC_MAIN_REG ++ ++ ++#define WIFI_MAC_MAIN_REG_BASE (0xa00000) ++ ++#define MAC_CONTROL (WIFI_MAC_MAIN_REG_BASE + 0x0) ++// Bit 0 reg_a1mis_abort_en U RW default = 'h0 ++// Bit 1 reg_swirq U RW default = 'h0 ++// Bit 2 reg_sniffer_enable U RW default = 'h0 ++// Bit 3 reg_smpdu_bitmap_update U RW default = 'h0 ++// Bit 4 reg_txstartit_earlymode U RW default = 'h0 ++// Bit 5 reg_ofdm_padding U RW default = 'h1 ++// Bit 6 reg_status_count_enable U RW default = 'h1 ++// Bit 11 reg_frequency_band U RW default = 'h0 ++// Bit 12 reg_tximmstop U RW default = 'h0 ++// Bit 13 reg_endian U RW default = 'h1 ++// Bit 14 reg_cca_rst_req U RW default = 'h0 ++// Bit 15 reg_fiqenable_rdrst U RW default = 'h0 ++// Bit 17 reg_tcpip_offload_on U RW default = 'h1 ++// Bit 18 reg_bws_ta_disable U RW default = 'h1 ++// Bit 19 reg_vht_txtime_sel U RW default = 'h0 ++// Bit 20 reg_qosnull_notupd_bitmap U RW default = 'h0 ++typedef union MAC_CONTROL_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_a1mis_abort_en : 1; ++ unsigned int reg_swirq : 1; ++ unsigned int reg_sniffer_enable : 1; ++ unsigned int reg_smpdu_bitmap_update : 1; ++ unsigned int reg_txstartit_earlymode : 1; ++ unsigned int reg_ofdm_padding : 1; ++ unsigned int reg_status_count_enable : 1; ++ unsigned int rsvd_0 : 4; ++ unsigned int reg_frequency_band : 1; ++ unsigned int reg_tximmstop : 1; ++ unsigned int reg_endian : 1; ++ unsigned int reg_cca_rst_req : 1; ++ unsigned int reg_fiqenable_rdrst : 1; ++ unsigned int rsvd_1 : 1; ++ unsigned int reg_tcpip_offload_on : 1; ++ unsigned int reg_bws_ta_disable : 1; ++ unsigned int reg_vht_txtime_sel : 1; ++ unsigned int reg_qosnull_notupd_bitmap : 1; ++ unsigned int rsvd_2 : 11; ++ } b; ++} MAC_CONTROL_FIELD_T; ++ ++#define MAC_IRQ_MASK (WIFI_MAC_MAIN_REG_BASE + 0x4) ++// Bit 0 reg_txstart_mask U RW default = 'h0 ++// Bit 1 reg_txend_mask U RW default = 'h0 ++// Bit 9 reg_ackto_mask U RW default = 'h0 ++// Bit 11 reg_rxstart_mask U RW default = 'h0 ++// Bit 12 reg_rxend_mask U RW default = 'h0 ++// Bit 31 :16 reg_abscount_mask U RW default = 'h0 ++typedef union MAC_IRQ_MASK_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_txstart_mask : 1; ++ unsigned int reg_txend_mask : 1; ++ unsigned int rsvd_0 : 7; ++ unsigned int reg_ackto_mask : 1; ++ unsigned int rsvd_1 : 1; ++ unsigned int reg_rxstart_mask : 1; ++ unsigned int reg_rxend_mask : 1; ++#ifdef PROJECT_T9026 ++ unsigned int rsvd_2 : 7; ++ unsigned int reg_abscount_mask : 12; ++#else ++ unsigned int rsvd_2 : 3; ++ unsigned int reg_abscount_mask : 16; ++#endif ++ } b; ++} MAC_IRQ_MASK_FIELD_T; ++ ++#define MAC_IRQ_STATUS (WIFI_MAC_MAIN_REG_BASE + 0xc) ++// Bit 0 reg_txstart_it U W1C default = 'h0 ++// Bit 1 reg_txend_it U W1C default = 'h0 ++// Bit 3 :2 ro_txvmac_id U RO default = 'h0 ++// Bit 7 :4 ro_txstart_queue U RO default = 'h0 ++// Bit 8 ro_txenderr U RO default = 'h0 ++// Bit 9 reg_ackto_it U W1C default = 'h0 ++// Bit 10 ro_txcol_flag U RO default = 'h0 ++// Bit 11 reg_rxstart_it U W1C default = 'h0 ++// Bit 12 reg_rxend_it U W1C default = 'h0 ++// Bit 13 ro_rxmpdu_ok U RO default = 'h0 ++// Bit 14 ro_unicast U RO default = 'h0 ++// Bit 15 ro_a1match U RO default = 'h0 ++// Bit 16 ro_bssidmatch U RO default = 'h0 ++// Bit 18 ro_srambuf_full1 U RO default = 'h0 ++// Bit 19 reg_swirq_it U W1C default = 'h0 ++// Bit 25 :20 reg_tx_frame_type U RW default = 'h0 ++// Bit 30 reg_abscount_intr U W1C default = 'h0 ++// Bit 31 reg_fiq_enable U RW default = 'h0 ++typedef union MAC_IRQ_STATUS_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_txstart_it : 1; ++ unsigned int reg_txend_it : 1; ++ unsigned int ro_txvmac_id : 2; ++ unsigned int ro_txstart_queue : 4; ++ unsigned int ro_txenderr : 1; ++ unsigned int reg_ackto_it : 1; ++ unsigned int ro_txcol_flag : 1; ++ unsigned int reg_rxstart_it : 1; ++ unsigned int reg_rxend_it : 1; ++ unsigned int ro_rxmpdu_ok : 1; ++ unsigned int ro_unicast : 1; ++ unsigned int ro_a1match : 1; ++ unsigned int ro_bssidmatch : 1; ++ unsigned int rsvd_0 : 1; ++ unsigned int ro_srambuf_full1 : 1; ++ unsigned int reg_swirq_it : 1; ++ unsigned int reg_tx_frame_type : 6; ++ unsigned int rsvd_1 : 4; ++ unsigned int reg_abscount_intr : 1; ++ unsigned int reg_fiq_enable : 1; ++ } b; ++} MAC_IRQ_STATUS_FIELD_T; ++ ++#define MAC_ERR_STATUS (WIFI_MAC_MAIN_REG_BASE + 0x10) ++// Bit 0 ro_fiac_fw_timeout_err U RO default = 'h0 ++// Bit 1 ro_hw_timeout_err U RO default = 'h0 ++// Bit 2 ro_tx_wd_timeout_err U RO default = 'h0 ++// Bit 3 ro_txinvalidlen_err U RO default = 'h0 ++// Bit 4 ro_tx_keymiss U RO default = 'h0 ++// Bit 5 ro_tximmstop_err U RO default = 'h0 ++// Bit 9 :6 ro_tx_phyerror U RO default = 'h0 ++// Bit 18 :10 ro_txcol_queue U RO default = 'h0 ++// Bit 19 ro_tx_not_grant U RO default = 'h0 ++// Bit 22 ro_srambuf_full2 U RO default = 'h0 ++// Bit 23 ro_fcserr U RO default = 'h0 ++// Bit 24 ro_rxfifoov U RO default = 'h0 ++// Bit 25 ro_rx_wd_timeout_err U RO default = 'h0 ++// Bit 26 ro_short_length U RO default = 'h0 ++// Bit 27 ro_length_error U RO default = 'h0 ++// Bit 31 :28 ro_rx_phyerror U RO default = 'h0 ++typedef union MAC_ERR_STATUS_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_fiac_fw_timeout_err : 1; ++ unsigned int ro_hw_timeout_err : 1; ++ unsigned int ro_tx_wd_timeout_err : 1; ++ unsigned int ro_txinvalidlen_err : 1; ++ unsigned int ro_tx_keymiss : 1; ++ unsigned int ro_tximmstop_err : 1; ++ unsigned int ro_tx_phyerror : 4; ++ unsigned int ro_txcol_queue : 9; ++ unsigned int ro_tx_not_grant : 1; ++ unsigned int rsvd_0 : 2; ++ unsigned int ro_srambuf_full2 : 1; ++ unsigned int ro_fcserr : 1; ++ unsigned int ro_rxfifoov : 1; ++ unsigned int ro_rx_wd_timeout_err : 1; ++ unsigned int ro_short_length : 1; ++ unsigned int ro_length_error : 1; ++ unsigned int ro_rx_phyerror : 4; ++ } b; ++} MAC_ERR_STATUS_FIELD_T; ++ ++#define ABS_STATUS (WIFI_MAC_MAIN_REG_BASE + 0x14) ++// Bit 16 reg_mac_absstatus0 U W1C default = 'h0 ++// Bit 17 reg_mac_absstatus1 U W1C default = 'h0 ++// Bit 18 reg_mac_absstatus2 U W1C default = 'h0 ++// Bit 19 reg_mac_absstatus3 U W1C default = 'h0 ++// Bit 20 reg_mac_absstatus4 U W1C default = 'h0 ++// Bit 21 reg_mac_absstatus5 U W1C default = 'h0 ++// Bit 22 reg_mac_absstatus6 U W1C default = 'h0 ++// Bit 23 reg_mac_absstatus7 U W1C default = 'h0 ++// Bit 24 reg_mac_absstatus8 U W1C default = 'h0 ++// Bit 25 reg_mac_absstatus9 U W1C default = 'h0 ++// Bit 26 reg_mac_absstatus10 U W1C default = 'h0 ++// Bit 27 reg_mac_absstatus11 U W1C default = 'h0 ++// Bit 28 reg_mac_absstatus12 U W1C default = 'h0 ++// Bit 29 reg_mac_absstatus13 U W1C default = 'h0 ++// Bit 30 reg_mac_absstatus14 U W1C default = 'h0 ++// Bit 31 reg_mac_absstatus15 U W1C default = 'h0 ++typedef union ABS_STATUS_FIELD ++{ ++ unsigned int data; ++#ifdef PROJECT_T9026 ++ struct ++ { ++ unsigned int rsvd_0 : 20; ++ unsigned int reg_mac_absstatus0 : 1; ++ unsigned int reg_mac_absstatus1 : 1; ++ unsigned int reg_mac_absstatus2 : 1; ++ unsigned int reg_mac_absstatus3 : 1; ++ unsigned int reg_mac_absstatus4 : 1; ++ unsigned int reg_mac_absstatus5 : 1; ++ unsigned int reg_mac_absstatus6 : 1; ++ unsigned int reg_mac_absstatus7 : 1; ++ unsigned int reg_mac_absstatus8 : 1; ++ unsigned int reg_mac_absstatus9 : 1; ++ unsigned int reg_mac_absstatus10 : 1; ++ unsigned int reg_mac_absstatus11 : 1; ++ } b; ++#else ++ struct ++ { ++ unsigned int rsvd_0 : 16; ++ unsigned int reg_mac_absstatus0 : 1; ++ unsigned int reg_mac_absstatus1 : 1; ++ unsigned int reg_mac_absstatus2 : 1; ++ unsigned int reg_mac_absstatus3 : 1; ++ unsigned int reg_mac_absstatus4 : 1; ++ unsigned int reg_mac_absstatus5 : 1; ++ unsigned int reg_mac_absstatus6 : 1; ++ unsigned int reg_mac_absstatus7 : 1; ++ unsigned int reg_mac_absstatus8 : 1; ++ unsigned int reg_mac_absstatus9 : 1; ++ unsigned int reg_mac_absstatus10 : 1; ++ unsigned int reg_mac_absstatus11 : 1; ++ unsigned int reg_mac_absstatus12 : 1; ++ unsigned int reg_mac_absstatus13 : 1; ++ unsigned int reg_mac_absstatus14 : 1; ++ unsigned int reg_mac_absstatus15 : 1; ++ } b; ++#endif ++} ABS_STATUS_FIELD_T; ++ ++#define MAC_LOCAL_ADDRLO0 (WIFI_MAC_MAIN_REG_BASE + 0x1c) ++// Bit 31 :0 reg_mac_local_addrlo0 U RW default = 'h1279ffff ++typedef union MAC_LOCAL_ADDRLO0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_local_addrlo0 : 32; ++ } b; ++} MAC_LOCAL_ADDRLO0_FIELD_T; ++ ++#define MAC_LOCAL_ADDRHI0 (WIFI_MAC_MAIN_REG_BASE + 0x20) ++// Bit 15 :0 reg_mac_local_addrhi0 U RW default = 'h5634 ++typedef union MAC_LOCAL_ADDRHI0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_local_addrhi0 : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} MAC_LOCAL_ADDRHI0_FIELD_T; ++ ++#define MAC_LOCAL_ADDRLO1 (WIFI_MAC_MAIN_REG_BASE + 0x24) ++// Bit 31 :0 reg_mac_local_addrlo1 U RW default = 'h1279ffff ++typedef union MAC_LOCAL_ADDRLO1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_local_addrlo1 : 32; ++ } b; ++} MAC_LOCAL_ADDRLO1_FIELD_T; ++ ++#define MAC_LOCAL_ADDRHI1 (WIFI_MAC_MAIN_REG_BASE + 0x28) ++// Bit 15 :0 reg_mac_local_addrhi1 U RW default = 'h5634 ++typedef union MAC_LOCAL_ADDRHI1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_local_addrhi1 : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} MAC_LOCAL_ADDRHI1_FIELD_T; ++ ++#define MAC_LOCAL_ADDRLO2 (WIFI_MAC_MAIN_REG_BASE + 0x2c) ++// Bit 31 :0 reg_mac_local_addrlo2 U RW default = 'h1279ffff ++typedef union MAC_LOCAL_ADDRLO2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_local_addrlo2 : 32; ++ } b; ++} MAC_LOCAL_ADDRLO2_FIELD_T; ++ ++#define MAC_LOCAL_ADDRHI2 (WIFI_MAC_MAIN_REG_BASE + 0x30) ++// Bit 15 :0 reg_mac_local_addrhi2 U RW default = 'h5634 ++typedef union MAC_LOCAL_ADDRHI2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_local_addrhi2 : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} MAC_LOCAL_ADDRHI2_FIELD_T; ++ ++#define MAC_LOCAL_ADDRLO3 (WIFI_MAC_MAIN_REG_BASE + 0x34) ++// Bit 31 :0 reg_mac_local_addrlo3 U RW default = 'h1279ffff ++typedef union MAC_LOCAL_ADDRLO3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_local_addrlo3 : 32; ++ } b; ++} MAC_LOCAL_ADDRLO3_FIELD_T; ++ ++#define MAC_LOCAL_ADDRHI3 (WIFI_MAC_MAIN_REG_BASE + 0x38) ++// Bit 15 :0 reg_mac_local_addrhi3 U RW default = 'h5634 ++typedef union MAC_LOCAL_ADDRHI3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_local_addrhi3 : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} MAC_LOCAL_ADDRHI3_FIELD_T; ++ ++#define MAC_LOCAL_BSSIDLO0 (WIFI_MAC_MAIN_REG_BASE + 0x3c) ++// Bit 31 :0 reg_mac_local_bssidlo0 U RW default = 'h0 ++typedef union MAC_LOCAL_BSSIDLO0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_local_bssidlo0 : 32; ++ } b; ++} MAC_LOCAL_BSSIDLO0_FIELD_T; ++ ++#define MAC_LOCAL_BSSIDHI0 (WIFI_MAC_MAIN_REG_BASE + 0x40) ++// Bit 15 :0 reg_mac_local_bssidhi0 U RW default = 'h0 ++typedef union MAC_LOCAL_BSSIDHI0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_local_bssidhi0 : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} MAC_LOCAL_BSSIDHI0_FIELD_T; ++ ++#define MAC_LOCAL_BSSIDLO1 (WIFI_MAC_MAIN_REG_BASE + 0x44) ++// Bit 31 :0 reg_mac_local_bssidlo1 U RW default = 'h0 ++typedef union MAC_LOCAL_BSSIDLO1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_local_bssidlo1 : 32; ++ } b; ++} MAC_LOCAL_BSSIDLO1_FIELD_T; ++ ++#define MAC_LOCAL_BSSIDHI1 (WIFI_MAC_MAIN_REG_BASE + 0x48) ++// Bit 15 :0 reg_mac_local_bssidhi1 U RW default = 'h0 ++typedef union MAC_LOCAL_BSSIDHI1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_local_bssidhi1 : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} MAC_LOCAL_BSSIDHI1_FIELD_T; ++ ++#define MAC_LOCAL_BSSIDLO2 (WIFI_MAC_MAIN_REG_BASE + 0x4c) ++// Bit 31 :0 reg_mac_local_bssidlo2 U RW default = 'h0 ++typedef union MAC_LOCAL_BSSIDLO2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_local_bssidlo2 : 32; ++ } b; ++} MAC_LOCAL_BSSIDLO2_FIELD_T; ++ ++#define MAC_LOCAL_BSSIDHI2 (WIFI_MAC_MAIN_REG_BASE + 0x50) ++// Bit 15 :0 reg_mac_local_bssidhi2 U RW default = 'h0 ++typedef union MAC_LOCAL_BSSIDHI2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_local_bssidhi2 : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} MAC_LOCAL_BSSIDHI2_FIELD_T; ++ ++#define MAC_LOCAL_BSSIDLO3 (WIFI_MAC_MAIN_REG_BASE + 0x54) ++// Bit 31 :0 reg_mac_local_bssidlo3 U RW default = 'h0 ++typedef union MAC_LOCAL_BSSIDLO3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_local_bssidlo3 : 32; ++ } b; ++} MAC_LOCAL_BSSIDLO3_FIELD_T; ++ ++#define MAC_LOCAL_BSSIDHI3 (WIFI_MAC_MAIN_REG_BASE + 0x58) ++// Bit 15 :0 reg_mac_local_bssidhi3 U RW default = 'h0 ++typedef union MAC_LOCAL_BSSIDHI3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_local_bssidhi3 : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} MAC_LOCAL_BSSIDHI3_FIELD_T; ++ ++#define STATUS_CNT_CTRL_IRQ (WIFI_MAC_MAIN_REG_BASE + 0x5c) ++// Bit 5 :0 reg_fiq_status_cnt_idx0 U RW default = 'h0 ++// Bit 11 :6 reg_fiq_status_cnt_idx1 U RW default = 'h1 ++// Bit 17 :12 reg_fiq_status_cnt_idx2 U RW default = 'h9 ++// Bit 23 :18 reg_fiq_status_cnt_idx3 U RW default = 'h13 ++// Bit 24 reg_fiq_status_cnt_en0 U RW default = 'h1 ++// Bit 25 reg_fiq_status_cnt_en1 U RW default = 'h1 ++// Bit 26 reg_fiq_status_cnt_en2 U RW default = 'h1 ++// Bit 27 reg_fiq_status_cnt_en3 U RW default = 'h0 ++// Bit 28 reg_fiq_status_cnt_clr0 U RW default = 'h0 ++// Bit 29 reg_fiq_status_cnt_clr1 U RW default = 'h0 ++// Bit 30 reg_fiq_status_cnt_clr2 U RW default = 'h0 ++// Bit 31 reg_fiq_status_cnt_clr3 U RW default = 'h0 ++typedef union STATUS_CNT_CTRL_IRQ_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_fiq_status_cnt_idx0 : 6; ++ unsigned int reg_fiq_status_cnt_idx1 : 6; ++ unsigned int reg_fiq_status_cnt_idx2 : 6; ++ unsigned int reg_fiq_status_cnt_idx3 : 6; ++ unsigned int reg_fiq_status_cnt_en0 : 1; ++ unsigned int reg_fiq_status_cnt_en1 : 1; ++ unsigned int reg_fiq_status_cnt_en2 : 1; ++ unsigned int reg_fiq_status_cnt_en3 : 1; ++ unsigned int reg_fiq_status_cnt_clr0 : 1; ++ unsigned int reg_fiq_status_cnt_clr1 : 1; ++ unsigned int reg_fiq_status_cnt_clr2 : 1; ++ unsigned int reg_fiq_status_cnt_clr3 : 1; ++ } b; ++} STATUS_CNT_CTRL_IRQ_FIELD_T; ++ ++#define IRQ_STATUS_CNT0 (WIFI_MAC_MAIN_REG_BASE + 0x60) ++// Bit 31 :0 ro_fiq_status_cnt0 U RO default = 'h0 ++typedef union IRQ_STATUS_CNT0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_fiq_status_cnt0 : 32; ++ } b; ++} IRQ_STATUS_CNT0_FIELD_T; ++ ++#define IRQ_STATUS_CNT1 (WIFI_MAC_MAIN_REG_BASE + 0x64) ++// Bit 31 :0 ro_fiq_status_cnt1 U RO default = 'h0 ++typedef union IRQ_STATUS_CNT1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_fiq_status_cnt1 : 32; ++ } b; ++} IRQ_STATUS_CNT1_FIELD_T; ++ ++#define IRQ_STATUS_CNT2 (WIFI_MAC_MAIN_REG_BASE + 0x68) ++// Bit 31 :0 ro_fiq_status_cnt2 U RO default = 'h0 ++typedef union IRQ_STATUS_CNT2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_fiq_status_cnt2 : 32; ++ } b; ++} IRQ_STATUS_CNT2_FIELD_T; ++ ++#define MAC_CLKJIC0 (WIFI_MAC_MAIN_REG_BASE + 0x6c) ++// Bit 7 :0 reg_rx_clk_jic U RW default = 'hff ++// Bit 15 :8 reg_tx_clk_jic U RW default = 'hff ++// Bit 23 :16 reg_timer_clk_jic U RW default = 'hff ++// Bit 31 :24 reg_reg_clk_jic U RW default = 'hff ++typedef union MAC_CLKJIC0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_rx_clk_jic : 8; ++ unsigned int reg_tx_clk_jic : 8; ++ unsigned int reg_timer_clk_jic : 8; ++ unsigned int reg_reg_clk_jic : 8; ++ } b; ++} MAC_CLKJIC0_FIELD_T; ++ ++#define MAC_CLKJIC1 (WIFI_MAC_MAIN_REG_BASE + 0x70) ++// Bit 11 :0 reg_dp_clk_jic U RW default = 'hfff ++// Bit 21 :16 reg_ahb_clk_jic U RW default = 'h3f ++typedef union MAC_CLKJIC1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_dp_clk_jic : 12; ++ unsigned int rsvd_0 : 4; ++ unsigned int reg_ahb_clk_jic : 6; ++ unsigned int rsvd_1 : 10; ++ } b; ++} MAC_CLKJIC1_FIELD_T; ++ ++#define IRQ_STATUS_CNT3 (WIFI_MAC_MAIN_REG_BASE + 0x74) ++// Bit 31 :0 ro_fiq_status_cnt3 U RO default = 'h0 ++typedef union IRQ_STATUS_CNT3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_fiq_status_cnt3 : 32; ++ } b; ++} IRQ_STATUS_CNT3_FIELD_T; ++ ++#define MAC_DEBUG0 (WIFI_MAC_MAIN_REG_BASE + 0x78) ++// Bit 31 :0 reg_mac_debug0 U RW default = 'h0 ++typedef union MAC_DEBUG0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_debug0 : 32; ++ } b; ++} MAC_DEBUG0_FIELD_T; ++ ++#define MAC_DEBUG1 (WIFI_MAC_MAIN_REG_BASE + 0x7c) ++// Bit 31 :0 reg_mac_debug1 U RW default = 'h0 ++typedef union MAC_DEBUG1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_debug1 : 32; ++ } b; ++} MAC_DEBUG1_FIELD_T; ++ ++#define MAC_DEBUG2 (WIFI_MAC_MAIN_REG_BASE + 0x80) ++// Bit 31 :0 reg_mac_debug2 U RW default = 'h0 ++typedef union MAC_DEBUG2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_debug2 : 32; ++ } b; ++} MAC_DEBUG2_FIELD_T; ++ ++#define MAC_DEBUG3 (WIFI_MAC_MAIN_REG_BASE + 0x84) ++// Bit 31 :0 reg_mac_debug3 U RW default = 'h0 ++typedef union MAC_DEBUG3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_debug3 : 32; ++ } b; ++} MAC_DEBUG3_FIELD_T; ++ ++#define MAC_FIACMAXDEL (WIFI_MAC_MAIN_REG_BASE + 0x88) ++// Bit 6 :0 reg_txvector_hw_maxdel U RW default = 'h3e ++// Bit 12 :8 reg_fiac_maxdela U RW default = 'h18 ++// Bit 20 :16 reg_fiac_maxdelb U RW default = 'h10 ++typedef union MAC_FIACMAXDEL_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_txvector_hw_maxdel : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int reg_fiac_maxdela : 5; ++ unsigned int rsvd_1 : 3; ++ unsigned int reg_fiac_maxdelb : 5; ++ unsigned int rsvd_2 : 11; ++ } b; ++} MAC_FIACMAXDEL_FIELD_T; ++ ++#define DEVICE0_MODE (WIFI_MAC_MAIN_REG_BASE + 0x90) ++// Bit 31 :0 reg_device0_mode U RW default = 'h0 ++typedef union DEVICE0_MODE_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_device0_mode : 32; ++ } b; ++} DEVICE0_MODE_FIELD_T; ++ ++#define DEVICE1_MODE (WIFI_MAC_MAIN_REG_BASE + 0x94) ++// Bit 31 :0 reg_device1_mode U RW default = 'h0 ++typedef union DEVICE1_MODE_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_device1_mode : 32; ++ } b; ++} DEVICE1_MODE_FIELD_T; ++ ++#define DEVICE2_MODE (WIFI_MAC_MAIN_REG_BASE + 0x98) ++// Bit 31 :0 reg_device2_mode U RW default = 'h0 ++typedef union DEVICE2_MODE_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_device2_mode : 32; ++ } b; ++} DEVICE2_MODE_FIELD_T; ++ ++#define DEVICE3_MODE (WIFI_MAC_MAIN_REG_BASE + 0x9c) ++// Bit 31 :0 reg_device3_mode U RW default = 'h0 ++typedef union DEVICE3_MODE_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_device3_mode : 32; ++ } b; ++} DEVICE3_MODE_FIELD_T; ++ ++#define MAC_INTNUM (WIFI_MAC_MAIN_REG_BASE + 0xa0) ++// Bit 15 :0 reg_rxend_cnt U RW default = 'h0 ++// Bit 31 :16 reg_rxstart_cnt U RW default = 'h0 ++typedef union MAC_INTNUM_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_rxend_cnt : 16; ++ unsigned int reg_rxstart_cnt : 16; ++ } b; ++} MAC_INTNUM_FIELD_T; ++ ++#define FRAME_TYPE_CNT_CTRL (WIFI_MAC_MAIN_REG_BASE + 0xa4) ++// Bit 5 :0 reg_frame_type_idx0 U RW default = 'h1b ++// Bit 11 :6 reg_frame_type_idx1 U RW default = 'h1c ++// Bit 17 :12 reg_frame_type_idx2 U RW default = 'h1d ++// Bit 23 :18 reg_frame_type_idx3 U RW default = 'h28 ++// Bit 24 reg_frame_cnt_en0 U RW default = 'h1 ++// Bit 25 reg_frame_cnt_en1 U RW default = 'h1 ++// Bit 26 reg_frame_cnt_en2 U RW default = 'h1 ++// Bit 27 reg_frame_cnt_en3 U RW default = 'h1 ++// Bit 28 reg_frame_cnt_clr0 U RW default = 'h0 ++// Bit 29 reg_frame_cnt_clr1 U RW default = 'h0 ++// Bit 30 reg_frame_cnt_clr2 U RW default = 'h0 ++// Bit 31 reg_frame_cnt_clr3 U RW default = 'h0 ++typedef union FRAME_TYPE_CNT_CTRL_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_frame_type_idx0 : 6; ++ unsigned int reg_frame_type_idx1 : 6; ++ unsigned int reg_frame_type_idx2 : 6; ++ unsigned int reg_frame_type_idx3 : 6; ++ unsigned int reg_frame_cnt_en0 : 1; ++ unsigned int reg_frame_cnt_en1 : 1; ++ unsigned int reg_frame_cnt_en2 : 1; ++ unsigned int reg_frame_cnt_en3 : 1; ++ unsigned int reg_frame_cnt_clr0 : 1; ++ unsigned int reg_frame_cnt_clr1 : 1; ++ unsigned int reg_frame_cnt_clr2 : 1; ++ unsigned int reg_frame_cnt_clr3 : 1; ++ } b; ++} FRAME_TYPE_CNT_CTRL_FIELD_T; ++ ++#define FRAM_TYPE_CNT0 (WIFI_MAC_MAIN_REG_BASE + 0xa8) ++// Bit 31 :0 ro_frame_cnt0 U RO default = 'h0 ++typedef union FRAM_TYPE_CNT0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_frame_cnt0 : 32; ++ } b; ++} FRAM_TYPE_CNT0_FIELD_T; ++ ++#define FRAM_TYPE_CNT1 (WIFI_MAC_MAIN_REG_BASE + 0xac) ++// Bit 31 :0 ro_frame_cnt1 U RO default = 'h0 ++typedef union FRAM_TYPE_CNT1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_frame_cnt1 : 32; ++ } b; ++} FRAM_TYPE_CNT1_FIELD_T; ++ ++#define FRAM_TYPE_CNT2 (WIFI_MAC_MAIN_REG_BASE + 0xf4) ++// Bit 31 :0 ro_frame_cnt2 U RO default = 'h0 ++typedef union FRAM_TYPE_CNT2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_frame_cnt2 : 32; ++ } b; ++} FRAM_TYPE_CNT2_FIELD_T; ++ ++#define FRAM_TYPE_CNT3 (WIFI_MAC_MAIN_REG_BASE + 0xf8) ++// Bit 31 :0 ro_frame_cnt3 U RO default = 'h0 ++typedef union FRAM_TYPE_CNT3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_frame_cnt3 : 32; ++ } b; ++} FRAM_TYPE_CNT3_FIELD_T; ++ ++#define PACKET_IFS_US (WIFI_MAC_MAIN_REG_BASE + 0x124) ++// Bit 7 :0 reg_dot11n_sifs_us U RW default = 'ha ++// Bit 15 :8 reg_dot11b_sifs_us U RW default = 'ha ++// Bit 19 :16 reg_rifs_us U RW default = 'h2 ++// Bit 23 :20 reg_signal_extension_us U RW default = 'h6 ++// Bit 31 :24 reg_packet_ifs_rsvd U RW default = 'h0 ++typedef union PACKET_IFS_US_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_dot11n_sifs_us : 8; ++ unsigned int reg_dot11b_sifs_us : 8; ++ unsigned int reg_rifs_us : 4; ++ unsigned int reg_signal_extension_us : 4; ++ unsigned int reg_packet_ifs_rsvd : 8; ++ } b; ++} PACKET_IFS_US_FIELD_T; ++ ++#define CTRL_FRAME_MASK (WIFI_MAC_MAIN_REG_BASE + 0x138) ++// Bit 3 :0 reg_tx_control_frame_mask U RW default = 'h0 ++typedef union CTRL_FRAME_MASK_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_tx_control_frame_mask : 4; ++ unsigned int rsvd_0 : 28; ++ } b; ++} CTRL_FRAME_MASK_FIELD_T; ++ ++#define MAC_KEYINFO0 (WIFI_MAC_MAIN_REG_BASE + 0x140) ++// Bit 3 :0 reg_unicast_cipher_type0 U RW default = 'h0 ++// Bit 7 :4 reg_multicast_cipher_type0 U RW default = 'h0 ++// Bit 8 reg_multicast_key_lock0 U RW default = 'h0 ++// Bit 19 :16 reg_unicast_cipher_type1 U RW default = 'h0 ++// Bit 23 :20 reg_multicast_cipher_type1 U RW default = 'h0 ++// Bit 24 reg_multicast_key_lock1 U RW default = 'h0 ++typedef union MAC_KEYINFO0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_unicast_cipher_type0 : 4; ++ unsigned int reg_multicast_cipher_type0 : 4; ++ unsigned int reg_multicast_key_lock0 : 1; ++ unsigned int rsvd_0 : 7; ++ unsigned int reg_unicast_cipher_type1 : 4; ++ unsigned int reg_multicast_cipher_type1 : 4; ++ unsigned int reg_multicast_key_lock1 : 1; ++ unsigned int rsvd_1 : 7; ++ } b; ++} MAC_KEYINFO0_FIELD_T; ++ ++#define MAC_KEYINFO1 (WIFI_MAC_MAIN_REG_BASE + 0x144) ++// Bit 3 :0 reg_unicast_cipher_type2 U RW default = 'h0 ++// Bit 7 :4 reg_multicast_cipher_type2 U RW default = 'h0 ++// Bit 8 reg_multicast_key_lock2 U RW default = 'h0 ++// Bit 19 :16 reg_unicast_cipher_type3 U RW default = 'h0 ++// Bit 23 :20 reg_multicast_cipher_type3 U RW default = 'h0 ++// Bit 24 reg_multicast_key_lock3 U RW default = 'h0 ++typedef union MAC_KEYINFO1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_unicast_cipher_type2 : 4; ++ unsigned int reg_multicast_cipher_type2 : 4; ++ unsigned int reg_multicast_key_lock2 : 1; ++ unsigned int rsvd_0 : 7; ++ unsigned int reg_unicast_cipher_type3 : 4; ++ unsigned int reg_multicast_cipher_type3 : 4; ++ unsigned int reg_multicast_key_lock3 : 1; ++ unsigned int rsvd_1 : 7; ++ } b; ++} MAC_KEYINFO1_FIELD_T; ++ ++#define MAC_KEYTABLE_CMD (WIFI_MAC_MAIN_REG_BASE + 0x148) ++// Bit 11 :0 reg_keytable_cmd_addr U RW default = 'h0 ++// Bit 15 :12 reg_keytable_cmd_cipher_type U RW default = 'h0 ++// Bit 18 :16 reg_keytable_cmd_type U RW default = 'h0 ++// Bit 19 reg_keytable_cmd_multikey_sel U RW default = 'h0 ++// Bit 27 :20 reg_keytable_cmd_stationid U RW default = 'h0 ++// Bit 29 :28 ro_keytable_cmd_fail U RO default = 'h0 ++// Bit 30 reg_keytable_cmd_en U RW default = 'h0 ++// Bit 31 reg_keytable_cmd_ready U RW default = 'h1 ++typedef union MAC_KEYTABLE_CMD_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_keytable_cmd_addr : 12; ++ unsigned int reg_keytable_cmd_cipher_type : 4; ++ unsigned int reg_keytable_cmd_type : 3; ++ unsigned int reg_keytable_cmd_multikey_sel : 1; ++ unsigned int reg_keytable_cmd_stationid : 8; ++ unsigned int ro_keytable_cmd_fail : 2; ++ unsigned int reg_keytable_cmd_en : 1; ++ unsigned int reg_keytable_cmd_ready : 1; ++ } b; ++} MAC_KEYTABLE_CMD_FIELD_T; ++ ++#define MAC_KEYTABLE_DATA (WIFI_MAC_MAIN_REG_BASE + 0x14c) ++// Bit 31 :0 reg_mac_keytable_data U RW default = 'h0 ++typedef union MAC_KEYTABLE_DATA_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_keytable_data : 32; ++ } b; ++} MAC_KEYTABLE_DATA_FIELD_T; ++ ++#define MAC_KEYTABLE_DATA2 (WIFI_MAC_MAIN_REG_BASE + 0x150) ++// Bit 31 :0 reg_mac_keytable_data2 U RW default = 'h0 ++typedef union MAC_KEYTABLE_DATA2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_keytable_data2 : 32; ++ } b; ++} MAC_KEYTABLE_DATA2_FIELD_T; ++ ++#define MAC_KEYTABLE_DATA3 (WIFI_MAC_MAIN_REG_BASE + 0x154) ++// Bit 31 :0 reg_mac_keytable_data3 U RW default = 'h0 ++typedef union MAC_KEYTABLE_DATA3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_keytable_data3 : 32; ++ } b; ++} MAC_KEYTABLE_DATA3_FIELD_T; ++ ++#define MAC_KEYTABLE_DATA4 (WIFI_MAC_MAIN_REG_BASE + 0x158) ++// Bit 31 :0 reg_mac_keytable_data4 U RW default = 'h0 ++typedef union MAC_KEYTABLE_DATA4_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_keytable_data4 : 32; ++ } b; ++} MAC_KEYTABLE_DATA4_FIELD_T; ++ ++#define MAC_KEYTABLE_DATA5 (WIFI_MAC_MAIN_REG_BASE + 0x15c) ++// Bit 31 :0 reg_mac_keytable_data5 U RW default = 'h0 ++typedef union MAC_KEYTABLE_DATA5_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_keytable_data5 : 32; ++ } b; ++} MAC_KEYTABLE_DATA5_FIELD_T; ++ ++#define MAC_KEYTABLE_DATA6 (WIFI_MAC_MAIN_REG_BASE + 0x160) ++// Bit 31 :0 reg_mac_keytable_data6 U RW default = 'h0 ++typedef union MAC_KEYTABLE_DATA6_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_keytable_data6 : 32; ++ } b; ++} MAC_KEYTABLE_DATA6_FIELD_T; ++ ++#define MAC_KEYTABLE_DATA7 (WIFI_MAC_MAIN_REG_BASE + 0x164) ++// Bit 31 :0 reg_mac_keytable_data7 U RW default = 'h0 ++typedef union MAC_KEYTABLE_DATA7_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_keytable_data7 : 32; ++ } b; ++} MAC_KEYTABLE_DATA7_FIELD_T; ++ ++#define MAC_KEYTABLE_DATA8 (WIFI_MAC_MAIN_REG_BASE + 0x168) ++// Bit 31 :0 reg_mac_keytable_data8 U RW default = 'h0 ++typedef union MAC_KEYTABLE_DATA8_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_keytable_data8 : 32; ++ } b; ++} MAC_KEYTABLE_DATA8_FIELD_T; ++ ++#define MAC_KEYTABLE_DATA9 (WIFI_MAC_MAIN_REG_BASE + 0x16c) ++// Bit 31 :0 reg_mac_keytable_data9 U RW default = 'h0 ++typedef union MAC_KEYTABLE_DATA9_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_keytable_data9 : 32; ++ } b; ++} MAC_KEYTABLE_DATA9_FIELD_T; ++ ++#define MAC_KEYTABLE_DATA10 (WIFI_MAC_MAIN_REG_BASE + 0x170) ++// Bit 31 :0 reg_mac_keytable_data10 U RW default = 'h0 ++typedef union MAC_KEYTABLE_DATA10_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_keytable_data10 : 32; ++ } b; ++} MAC_KEYTABLE_DATA10_FIELD_T; ++ ++#define MAC_KEYTABLE_DATA11 (WIFI_MAC_MAIN_REG_BASE + 0x174) ++// Bit 31 :0 reg_mac_keytable_data11 U RW default = 'h0 ++typedef union MAC_KEYTABLE_DATA11_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_keytable_data11 : 32; ++ } b; ++} MAC_KEYTABLE_DATA11_FIELD_T; ++ ++#define MAC_KEYMAP (WIFI_MAC_MAIN_REG_BASE + 0x178) ++// Bit 7 :0 reg_keytable_offset0 U RW default = 'h0 ++// Bit 15 :8 reg_keytable_offset1 U RW default = 'h0 ++// Bit 23 :16 reg_keytable_offset2 U RW default = 'h0 ++// Bit 31 :24 reg_keytable_offset3 U RW default = 'h0 ++typedef union MAC_KEYMAP_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_keytable_offset0 : 8; ++ unsigned int reg_keytable_offset1 : 8; ++ unsigned int reg_keytable_offset2 : 8; ++ unsigned int reg_keytable_offset3 : 8; ++ } b; ++} MAC_KEYMAP_FIELD_T; ++ ++#define MAC_DBG_STATUS1 (WIFI_MAC_MAIN_REG_BASE + 0x190) ++// Bit 4 :0 ro_key_err_type U RO default = 'h0 ++typedef union MAC_DBG_STATUS1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_key_err_type : 5; ++ unsigned int rsvd_0 : 27; ++ } b; ++} MAC_DBG_STATUS1_FIELD_T; ++ ++#define TX_START_CHK (WIFI_MAC_MAIN_REG_BASE + 0x1a8) ++// Bit 25 :0 ro_txstart_cnt U RO default = 'h0 ++// Bit 26 reg_txstart_cnt_en U RW default = 'h0 ++// Bit 27 reg_txstart_cnt_clr U RW default = 'h1 ++// Bit 31 :28 reg_check_tx_queue U RW default = 'h9 ++typedef union TX_START_CHK_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txstart_cnt : 26; ++ unsigned int reg_txstart_cnt_en : 1; ++ unsigned int reg_txstart_cnt_clr : 1; ++ unsigned int reg_check_tx_queue : 4; ++ } b; ++} TX_START_CHK_FIELD_T; ++ ++#define TX_END_CHK (WIFI_MAC_MAIN_REG_BASE + 0x1ac) ++// Bit 25 :0 ro_txend_cnt U RO default = 'h0 ++// Bit 26 reg_txend_cnt_en U RW default = 'h0 ++// Bit 27 reg_txend_cnt_clr U RW default = 'h1 ++typedef union TX_END_CHK_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txend_cnt : 26; ++ unsigned int reg_txend_cnt_en : 1; ++ unsigned int reg_txend_cnt_clr : 1; ++ unsigned int rsvd_0 : 4; ++ } b; ++} TX_END_CHK_FIELD_T; ++ ++#define TX_ENABLE_CHK (WIFI_MAC_MAIN_REG_BASE + 0x1b0) ++// Bit 25 :0 ro_txenable_cnt U RO default = 'h0 ++// Bit 26 reg_txenable_cnt_en U RW default = 'h0 ++// Bit 27 reg_txenable_cnt_clr U RW default = 'h1 ++typedef union TX_ENABLE_CHK_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txenable_cnt : 26; ++ unsigned int reg_txenable_cnt_en : 1; ++ unsigned int reg_txenable_cnt_clr : 1; ++ unsigned int rsvd_0 : 4; ++ } b; ++} TX_ENABLE_CHK_FIELD_T; ++ ++#define TX_ENABLEWR_CHK (WIFI_MAC_MAIN_REG_BASE + 0x1b4) ++// Bit 25 :0 ro_txenable_wr_cnt_en U RO default = 'h0 ++// Bit 26 reg_txenable_wr_cnt_en U RW default = 'h0 ++// Bit 27 reg_txenable_wr_cnt_clr U RW default = 'h1 ++typedef union TX_ENABLEWR_CHK_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_txenable_wr_cnt_en : 26; ++ unsigned int reg_txenable_wr_cnt_en : 1; ++ unsigned int reg_txenable_wr_cnt_clr : 1; ++ unsigned int rsvd_0 : 4; ++ } b; ++} TX_ENABLEWR_CHK_FIELD_T; ++ ++#define MAC_DATA_LOCAL_CNT (WIFI_MAC_MAIN_REG_BASE + 0x1b8) ++// Bit 28 :0 ro_mac_data_local_cnt U RO default = 'h0 ++// Bit 29 reg_mac_data_local_cnt_qos U RW default = 'h0 ++// Bit 30 reg_mac_data_local_cnt_clr U RW default = 'h0 ++// Bit 31 reg_mac_data_local_cnt_en U RW default = 'h0 ++typedef union MAC_DATA_LOCAL_CNT_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_mac_data_local_cnt : 29; ++ unsigned int reg_mac_data_local_cnt_qos : 1; ++ unsigned int reg_mac_data_local_cnt_clr : 1; ++ unsigned int reg_mac_data_local_cnt_en : 1; ++ } b; ++} MAC_DATA_LOCAL_CNT_FIELD_T; ++ ++#define MAC_DATA_OTHER_CNT (WIFI_MAC_MAIN_REG_BASE + 0x1bc) ++// Bit 29 :0 ro_mac_data_other_cnt U RO default = 'h0 ++// Bit 30 reg_mac_data_other_cnt_clr U RW default = 'h0 ++// Bit 31 reg_mac_data_other_cnt_en U RW default = 'h0 ++typedef union MAC_DATA_OTHER_CNT_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_mac_data_other_cnt : 30; ++ unsigned int reg_mac_data_other_cnt_clr : 1; ++ unsigned int reg_mac_data_other_cnt_en : 1; ++ } b; ++} MAC_DATA_OTHER_CNT_FIELD_T; ++ ++#define MAC_DATA_MULTI_CNT (WIFI_MAC_MAIN_REG_BASE + 0x1c0) ++// Bit 29 :0 ro_mac_data_multi_cnt U RO default = 'h0 ++// Bit 30 reg_mac_data_multi_cnt_clr U RW default = 'h0 ++// Bit 31 reg_mac_data_multi_cnt_en U RW default = 'h0 ++typedef union MAC_DATA_MULTI_CNT_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_mac_data_multi_cnt : 30; ++ unsigned int reg_mac_data_multi_cnt_clr : 1; ++ unsigned int reg_mac_data_multi_cnt_en : 1; ++ } b; ++} MAC_DATA_MULTI_CNT_FIELD_T; ++ ++#endif ++ +diff --git a/drivers/net/wireless/w1/common/wifi_mac_rx_reg.h b/drivers/net/wireless/w1/common/wifi_mac_rx_reg.h +new file mode 100644 +index 0000000000000000000000000000000000000000..c669dacdd6168db80e84b143f4a6e8baa0d24d33 +--- /dev/null ++++ b/drivers/net/wireless/w1/common/wifi_mac_rx_reg.h +@@ -0,0 +1,313 @@ ++#ifdef WIFI_MAC_RX_REG ++#else ++#define WIFI_MAC_RX_REG ++ ++ ++#define WIFI_MAC_RX_REG_BASE (0xa00000) ++ ++#define MAC_RXWD_TIMER (WIFI_MAC_RX_REG_BASE + 0x1c4) ++// Bit 19 :0 reg_rx_wd_timer_duration U RW default = 'h4e20 ++// Bit 21 reg_rx_wd_timer_en U RW default = 'h1 ++// Bit 27 :24 reg_rxend_wait_cnum U RW default = 'h6 ++// Bit 31 :28 reg_rxstart_wait_cnum U RW default = 'h8 ++typedef union MAC_RXWD_TIMER_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_rx_wd_timer_duration : 20; ++ unsigned int rsvd_0 : 1; ++ unsigned int reg_rx_wd_timer_en : 1; ++ unsigned int rsvd_1 : 2; ++ unsigned int reg_rxend_wait_cnum : 4; ++ unsigned int reg_rxstart_wait_cnum : 4; ++ } b; ++} MAC_RXWD_TIMER_FIELD_T; ++ ++#define MAC_CHANNEL_NUM (WIFI_MAC_RX_REG_BASE + 0x1e0) ++// Bit 7 :0 reg_rx_channel_num U RW default = 'h0 ++typedef union MAC_CHANNEL_NUM_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_rx_channel_num : 8; ++ unsigned int rsvd_0 : 24; ++ } b; ++} MAC_CHANNEL_NUM_FIELD_T; ++ ++#define MAC_RX_BEACON_BASEADDR (WIFI_MAC_RX_REG_BASE + 0x1e4) ++// Bit 31 :0 reg_rx_beacon_baseaddr U RW default = 'h0 ++typedef union MAC_RX_BEACON_BASEADDR_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_rx_beacon_baseaddr : 32; ++ } b; ++} MAC_RX_BEACON_BASEADDR_FIELD_T; ++ ++#define MAC_RXENDTIME (WIFI_MAC_RX_REG_BASE + 0x1e8) ++// Bit 31 :0 ro_mac_rxendtime U RO default = 'h0 ++typedef union MAC_RXENDTIME_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_mac_rxendtime : 32; ++ } b; ++} MAC_RXENDTIME_FIELD_T; ++ ++#define MAC_RXSTARTTIME (WIFI_MAC_RX_REG_BASE + 0x1ec) ++// Bit 31 :0 ro_mac_rxstarttime U RO default = 'h0 ++typedef union MAC_RXSTARTTIME_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_mac_rxstarttime : 32; ++ } b; ++} MAC_RXSTARTTIME_FIELD_T; ++ ++#define MAC_RX_BASEADDR (WIFI_MAC_RX_REG_BASE + 0x1f0) ++// Bit 31 :0 reg_rx_baseaddr U RW default = 'h0 ++typedef union MAC_RX_BASEADDR_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_rx_baseaddr : 32; ++ } b; ++} MAC_RX_BASEADDR_FIELD_T; ++ ++#define MAC_RX_EPOINTER (WIFI_MAC_RX_REG_BASE + 0x1f4) ++// Bit 15 :0 reg_rx_eptr U RW default = 'h0 ++typedef union MAC_RX_EPOINTER_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_rx_eptr : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} MAC_RX_EPOINTER_FIELD_T; ++ ++#define MAC_RX_COUNT (WIFI_MAC_RX_REG_BASE + 0x1f8) ++// Bit 15 :0 reg_rx_count_o U RW default = 'h0 ++typedef union MAC_RX_COUNT_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_rx_count_o : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} MAC_RX_COUNT_FIELD_T; ++ ++#define MAC_RX_WPOINTER (WIFI_MAC_RX_REG_BASE + 0x1fc) ++// Bit 15 :0 reg_rx_wptr_o U RW default = 'h0 ++typedef union MAC_RX_WPOINTER_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_rx_wptr_o : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} MAC_RX_WPOINTER_FIELD_T; ++ ++#define MAC_RX_FRPOINTER (WIFI_MAC_RX_REG_BASE + 0x200) ++// Bit 15 :0 reg_rx_frptr U RW default = 'h0 ++typedef union MAC_RX_FRPOINTER_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_rx_frptr : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} MAC_RX_FRPOINTER_FIELD_T; ++ ++#define MAC_RX_HRPOINTER (WIFI_MAC_RX_REG_BASE + 0x204) ++// Bit 15 :0 ro_rx_hrptr_o U RO default = 'h0 ++typedef union MAC_RX_HRPOINTER_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rx_hrptr_o : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} MAC_RX_HRPOINTER_FIELD_T; ++ ++#define MAC_BITMAPTABLE_CMD (WIFI_MAC_RX_REG_BASE + 0x20c) ++// Bit 8 :0 reg_bitmaptable_cmd_addr U RW default = 'h0 ++// Bit 17 :16 reg_bitmaptable_cmd_type U RW default = 'h0 ++// Bit 29 ro_bitmaptable_cmd_fail U RO default = 'h0 ++// Bit 30 reg_bitmaptable_cmd_en U RW default = 'h0 ++// Bit 31 reg_bitmaptable_ready U RW default = 'h1 ++typedef union MAC_BITMAPTABLE_CMD_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_bitmaptable_cmd_addr : 9; ++ unsigned int rsvd_0 : 7; ++ unsigned int reg_bitmaptable_cmd_type : 2; ++ unsigned int rsvd_1 : 11; ++ unsigned int ro_bitmaptable_cmd_fail : 1; ++ unsigned int reg_bitmaptable_cmd_en : 1; ++ unsigned int reg_bitmaptable_ready : 1; ++ } b; ++} MAC_BITMAPTABLE_CMD_FIELD_T; ++ ++#define MAC_BITMAPTABLE_DATA (WIFI_MAC_RX_REG_BASE + 0x210) ++// Bit 31 :0 reg_mac_bitmaptable_data U RW default = 'h0 ++typedef union MAC_BITMAPTABLE_DATA_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_bitmaptable_data : 32; ++ } b; ++} MAC_BITMAPTABLE_DATA_FIELD_T; ++ ++#define MAC_BITMAPTABLE_DATA2 (WIFI_MAC_RX_REG_BASE + 0x214) ++// Bit 31 :0 reg_mac_bitmaptable_data2 U RW default = 'h0 ++typedef union MAC_BITMAPTABLE_DATA2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_bitmaptable_data2 : 32; ++ } b; ++} MAC_BITMAPTABLE_DATA2_FIELD_T; ++ ++#define MAC_BITMAPTABLE_DATA3 (WIFI_MAC_RX_REG_BASE + 0x218) ++// Bit 23 :0 reg_mac_bitmaptable_data3 U RW default = 'h0 ++typedef union MAC_BITMAPTABLE_DATA3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_bitmaptable_data3 : 24; ++ unsigned int rsvd_0 : 8; ++ } b; ++} MAC_BITMAPTABLE_DATA3_FIELD_T; ++ ++#define MAC_RXINFO (WIFI_MAC_RX_REG_BASE + 0x21c) ++// Bit 7 :0 ro_rx_rate U RO default = 'h0 ++// Bit 15 :10 ro_rx_packet_type U RO default = 'h0 ++// Bit 17 :16 ro_rx_a1match_id U RO default = 'h0 ++// Bit 21 :20 ro_rx_bssidmatch_id U RO default = 'h0 ++// Bit 31 :24 ro_rx_rssi_ant0 U RO default = 'h0 ++typedef union MAC_RXINFO_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rx_rate : 8; ++ unsigned int rsvd_0 : 2; ++ unsigned int ro_rx_packet_type : 6; ++ unsigned int ro_rx_a1match_id : 2; ++ unsigned int rsvd_1 : 2; ++ unsigned int ro_rx_bssidmatch_id : 2; ++ unsigned int rsvd_2 : 2; ++ unsigned int ro_rx_rssi_ant0 : 8; ++ } b; ++} MAC_RXINFO_FIELD_T; ++ ++#define MAC_RXINFO2 (WIFI_MAC_RX_REG_BASE + 0x220) ++// Bit 31 :0 ro_rx_a2_lo U RO default = 'h0 ++typedef union MAC_RXINFO2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_rx_a2_lo : 32; ++ } b; ++} MAC_RXINFO2_FIELD_T; ++ ++#define MAC_BMFM_INFO (WIFI_MAC_RX_REG_BASE + 0x224) ++// Bit 0 reg_cdbk_info U RW default = 'h0 ++// Bit 5 :4 reg_ng U RW default = 'h0 ++// Bit 19 :8 rxrat_ndp_vector U RW default = 'h60b ++// Bit 23 :20 reg_wfull_space U RW default = 'h4 ++// Bit 28 reg_bmfm_disable U RW default = 'h0 ++typedef union MAC_BMFM_INFO_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_cdbk_info : 1; ++ unsigned int rsvd_0 : 3; ++ unsigned int reg_ng : 2; ++ unsigned int rsvd_1 : 2; ++ unsigned int rxrat_ndp_vector : 12; ++ unsigned int reg_wfull_space : 4; ++ unsigned int rsvd_2 : 4; ++ unsigned int reg_bmfm_disable : 1; ++ unsigned int rsvd_3 : 3; ++ } b; ++} MAC_BMFM_INFO_FIELD_T; ++ ++#define MAC_AID (WIFI_MAC_RX_REG_BASE + 0x228) ++// Bit 15 :0 mac_aid U RW default = 'h0 ++typedef union MAC_AID_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int mac_aid : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} MAC_AID_FIELD_T; ++ ++#define MAC_BMFM_CNT (WIFI_MAC_RX_REG_BASE + 0x22c) ++// Bit 15 :0 cnt_bmfm_pkt U RO default = 'h0 ++// Bit 31 :16 cnt_bmfm_pkt_err U RO default = 'h0 ++typedef union MAC_BMFM_CNT_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int cnt_bmfm_pkt : 16; ++ unsigned int cnt_bmfm_pkt_err : 16; ++ } b; ++} MAC_BMFM_CNT_FIELD_T; ++ ++#define MAC_COMPRESSED_BMFM_CNT (WIFI_MAC_RX_REG_BASE + 0x230) ++// Bit 15 :0 cnt_compressed_bmfm_frame U RO default = 'h0 ++typedef union MAC_COMPRESSED_BMFM_CNT_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int cnt_compressed_bmfm_frame : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} MAC_COMPRESSED_BMFM_CNT_FIELD_T; ++ ++#define MAC_RX_BEACON_CTRL (WIFI_MAC_RX_REG_BASE + 0x234) ++// Bit 15 :0 reg_rx_beacon_buf_len U RW default = 'h0 ++// Bit 16 reg_rx_beacon_path_sel U RW default = 'h0 ++// Bit 19 :17 ro_rx_beacon_page_num U RO default = 'h0 ++// Bit 29 :20 reg_rx_beacon_clr_timer U RW default = 'h50 ++// Bit 30 reg_rx_beacon_page_mode U RW default = 'h0 ++// Bit 31 reg_rx_beacon_flag U RW default = 'h0 ++typedef union MAC_RX_BEACON_CTRL_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_rx_beacon_buf_len : 16; ++ unsigned int reg_rx_beacon_path_sel : 1; ++ unsigned int ro_rx_beacon_page_num : 3; ++ unsigned int reg_rx_beacon_clr_timer : 10; ++ unsigned int reg_rx_beacon_page_mode : 1; ++ unsigned int reg_rx_beacon_flag : 1; ++ } b; ++} MAC_RX_BEACON_CTRL_FIELD_T; ++ ++#endif ++ +diff --git a/drivers/net/wireless/w1/common/wifi_mac_timer_reg.h b/drivers/net/wireless/w1/common/wifi_mac_timer_reg.h +new file mode 100644 +index 0000000000000000000000000000000000000000..fa4e239c6bc6a59ffb6478f0c7c37c6f0fdb94a4 +--- /dev/null ++++ b/drivers/net/wireless/w1/common/wifi_mac_timer_reg.h +@@ -0,0 +1,565 @@ ++#ifdef WIFI_MAC_TIMER_REG ++#else ++#define WIFI_MAC_TIMER_REG ++ ++ ++#define WIFI_MAC_TIMER_REG_BASE (0xa00000) ++ ++#define MAC_COUNT1 (WIFI_MAC_TIMER_REG_BASE + 0xb0) ++// Bit 6 :0 reg_txsifsb U RW default = 'h2c ++// Bit 14 :8 reg_rxsifsb U RW default = 'h1c ++// Bit 15 reg_rxsifsb_sel U RW default = 'h0 ++// Bit 22 :16 reg_ccasifs U RW default = 'h28 ++// Bit 28 :24 reg_txstartdel U RW default = 'h2 ++// Bit 31 :29 reg_rxendwait U RW default = 'h3 ++typedef union MAC_COUNT1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_txsifsb : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int reg_rxsifsb : 7; ++ unsigned int reg_rxsifsb_sel : 1; ++ unsigned int reg_ccasifs : 7; ++ unsigned int rsvd_1 : 1; ++ unsigned int reg_txstartdel : 5; ++ unsigned int reg_rxendwait : 3; ++ } b; ++} MAC_COUNT1_FIELD_T; ++ ++#define MAC_COUNT2 (WIFI_MAC_TIMER_REG_BASE + 0xb4) ++// Bit 6 :0 reg_txsifsa U RW default = 'h40 ++// Bit 14 :8 reg_rxsifsa U RW default = 'h24 ++// Bit 15 reg_rxsifsa_sel U RW default = 'h0 ++// Bit 21 :16 reg_slot U RW default = 'h9 ++// Bit 28 :24 reg_fiac_fw_maxdel U RW default = 'hf ++typedef union MAC_COUNT2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_txsifsa : 7; ++ unsigned int rsvd_0 : 1; ++ unsigned int reg_rxsifsa : 7; ++ unsigned int reg_rxsifsa_sel : 1; ++ unsigned int reg_slot : 6; ++ unsigned int rsvd_1 : 2; ++ unsigned int reg_fiac_fw_maxdel : 5; ++ unsigned int rsvd_2 : 3; ++ } b; ++} MAC_COUNT2_FIELD_T; ++ ++#define MAC_COUNT3 (WIFI_MAC_TIMER_REG_BASE + 0xb8) ++// Bit 8 :0 reg_backoff_hold U RW default = 'h0 ++// Bit 12 reg_backoff_all_hold U RW default = 'h0 ++// Bit 17 :16 reg_txop_hold_status U RW default = 'h0 ++typedef union MAC_COUNT3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_backoff_hold : 9; ++ unsigned int rsvd_0 : 3; ++ unsigned int reg_backoff_all_hold : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int reg_txop_hold_status : 2; ++ unsigned int rsvd_2 : 14; ++ } b; ++} MAC_COUNT3_FIELD_T; ++ ++#define MAC_BACKOFF_CONTROL (WIFI_MAC_TIMER_REG_BASE + 0xbc) ++// Bit 7 :0 reg_slotn_s U RW default = 'h1 ++// Bit 11 reg_sifsn_s U RW default = 'h1 ++// Bit 15 reg_backoff_way U RW default = 'h1 ++// Bit 16 reg_ackto_way U RW default = 'h0 ++typedef union MAC_BACKOFF_CONTROL_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_slotn_s : 8; ++ unsigned int rsvd_0 : 3; ++ unsigned int reg_sifsn_s : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int reg_backoff_way : 1; ++ unsigned int reg_ackto_way : 1; ++ unsigned int rsvd_2 : 15; ++ } b; ++} MAC_BACKOFF_CONTROL_FIELD_T; ++ ++#define MAC_ABSCNT0 (WIFI_MAC_TIMER_REG_BASE + 0xc0) ++// Bit 25 :0 reg_abscnt0 U RW default = 'h0 ++typedef union MAC_ABSCNT0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_abscnt0 : 26; ++ unsigned int rsvd_0 : 6; ++ } b; ++} MAC_ABSCNT0_FIELD_T; ++ ++#define MAC_ABSCNT1 (WIFI_MAC_TIMER_REG_BASE + 0xc4) ++// Bit 25 :0 reg_abscnt1 U RW default = 'h0 ++typedef union MAC_ABSCNT1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_abscnt1 : 26; ++ unsigned int rsvd_0 : 6; ++ } b; ++} MAC_ABSCNT1_FIELD_T; ++ ++#define MAC_ABSCNT2 (WIFI_MAC_TIMER_REG_BASE + 0xc8) ++// Bit 25 :0 reg_abscnt2 U RW default = 'h0 ++typedef union MAC_ABSCNT2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_abscnt2 : 26; ++ unsigned int rsvd_0 : 6; ++ } b; ++} MAC_ABSCNT2_FIELD_T; ++ ++#define MAC_ABSCNT3 (WIFI_MAC_TIMER_REG_BASE + 0xcc) ++// Bit 25 :0 reg_abscnt3 U RW default = 'h0 ++typedef union MAC_ABSCNT3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_abscnt3 : 26; ++ unsigned int rsvd_0 : 6; ++ } b; ++} MAC_ABSCNT3_FIELD_T; ++ ++#define MAC_ABSCNT4 (WIFI_MAC_TIMER_REG_BASE + 0xd0) ++// Bit 25 :0 reg_abscnt4 U RW default = 'h0 ++typedef union MAC_ABSCNT4_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_abscnt4 : 26; ++ unsigned int rsvd_0 : 6; ++ } b; ++} MAC_ABSCNT4_FIELD_T; ++ ++#define MAC_ABSCNT5 (WIFI_MAC_TIMER_REG_BASE + 0xd4) ++// Bit 25 :0 reg_abscnt5 U RW default = 'h0 ++typedef union MAC_ABSCNT5_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_abscnt5 : 26; ++ unsigned int rsvd_0 : 6; ++ } b; ++} MAC_ABSCNT5_FIELD_T; ++ ++#define MAC_ABSCNT6 (WIFI_MAC_TIMER_REG_BASE + 0xd8) ++// Bit 25 :0 reg_abscnt6 U RW default = 'h0 ++typedef union MAC_ABSCNT6_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_abscnt6 : 26; ++ unsigned int rsvd_0 : 6; ++ } b; ++} MAC_ABSCNT6_FIELD_T; ++ ++#define MAC_ABSCNT7 (WIFI_MAC_TIMER_REG_BASE + 0xdc) ++// Bit 25 :0 reg_abscnt7 U RW default = 'h0 ++typedef union MAC_ABSCNT7_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_abscnt7 : 26; ++ unsigned int rsvd_0 : 6; ++ } b; ++} MAC_ABSCNT7_FIELD_T; ++ ++#define MAC_ABSCNT8 (WIFI_MAC_TIMER_REG_BASE + 0xe0) ++// Bit 25 :0 reg_abscnt8 U RW default = 'h0 ++typedef union MAC_ABSCNT8_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_abscnt8 : 26; ++ unsigned int rsvd_0 : 6; ++ } b; ++} MAC_ABSCNT8_FIELD_T; ++ ++#define MAC_ABSCNT9 (WIFI_MAC_TIMER_REG_BASE + 0xe4) ++// Bit 25 :0 reg_abscnt9 U RW default = 'h0 ++typedef union MAC_ABSCNT9_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_abscnt9 : 26; ++ unsigned int rsvd_0 : 6; ++ } b; ++} MAC_ABSCNT9_FIELD_T; ++ ++#define MAC_ABSCNT10 (WIFI_MAC_TIMER_REG_BASE + 0xe8) ++// Bit 25 :0 reg_abscnt10 U RW default = 'h0 ++typedef union MAC_ABSCNT10_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_abscnt10 : 26; ++ unsigned int rsvd_0 : 6; ++ } b; ++} MAC_ABSCNT10_FIELD_T; ++ ++#define MAC_ABSCNT11 (WIFI_MAC_TIMER_REG_BASE + 0xec) ++// Bit 25 :0 reg_abscnt11 U RW default = 'h0 ++typedef union MAC_ABSCNT11_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_abscnt11 : 26; ++ unsigned int rsvd_0 : 6; ++ } b; ++} MAC_ABSCNT11_FIELD_T; ++ ++#ifndef PROJECT_T9026 ++#define MAC_ABSCNT12 (WIFI_MAC_TIMER_REG_BASE + 0x1d0) ++// Bit 25 :0 reg_abscnt12 U RW default = 'h0 ++typedef union MAC_ABSCNT12_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_abscnt12 : 26; ++ unsigned int rsvd_0 : 6; ++ } b; ++} MAC_ABSCNT12_FIELD_T; ++ ++#define MAC_ABSCNT13 (WIFI_MAC_TIMER_REG_BASE + 0x1d4) ++// Bit 25 :0 reg_abscnt13 U RW default = 'h0 ++typedef union MAC_ABSCNT13_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_abscnt13 : 26; ++ unsigned int rsvd_0 : 6; ++ } b; ++} MAC_ABSCNT13_FIELD_T; ++ ++#define MAC_ABSCNT14 (WIFI_MAC_TIMER_REG_BASE + 0x1d8) ++// Bit 25 :0 reg_abscnt14 U RW default = 'h0 ++typedef union MAC_ABSCNT14_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_abscnt14 : 26; ++ unsigned int rsvd_0 : 6; ++ } b; ++} MAC_ABSCNT14_FIELD_T; ++ ++#define MAC_ABSCNT15 (WIFI_MAC_TIMER_REG_BASE + 0x1dc) ++// Bit 25 :0 reg_abscnt15 U RW default = 'h0 ++typedef union MAC_ABSCNT15_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_abscnt15 : 26; ++ unsigned int rsvd_0 : 6; ++ } b; ++} MAC_ABSCNT15_FIELD_T; ++#endif ++ ++#define TIMER_CONFIG (WIFI_MAC_TIMER_REG_BASE + 0xfc) ++// Bit 3 :0 reg_tx_priority_ctrl U RW default = 'hc ++// Bit 9 :4 reg_tx_duration_ctrl U RW default = 'h0 ++// Bit 10 reg_tx_request_mode U RW default = 'h1 ++// Bit 11 reg_tx_enable_clr_sel U RW default = 'h0 ++// Bit 15 :12 reg_tx_start_cnt_thr U RW default = 'h4 ++// Bit 31 :16 reg_vcs_thr U RW default = 'h1000 ++typedef union TIMER_CONFIG_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_tx_priority_ctrl : 4; ++ unsigned int reg_tx_duration_ctrl : 6; ++ unsigned int reg_tx_request_mode : 1; ++ unsigned int reg_tx_enable_clr_sel : 1; ++ unsigned int reg_tx_start_cnt_thr : 4; ++ unsigned int reg_vcs_thr : 16; ++ } b; ++} TIMER_CONFIG_FIELD_T; ++ ++#define MAC_TXCONTROL_NONQOS (WIFI_MAC_TIMER_REG_BASE + 0x100) ++// Bit 9 :0 reg_slot_num_o_nonqos U RW default = 'h0 ++// Bit 15 :10 reg_tx_duration_nonqos U RW default = 'h8 ++// Bit 19 :16 reg_aifsn_nonqos U RW default = 'h0 ++// Bit 23 :20 reg_cca_busy_mask_nonqos U RW default = 'h0 ++// Bit 24 reg_tx_enable_nonqos U RW default = 'h0 ++// Bit 26 :25 reg_tx_bandwidth_nonqos U RW default = 'h0 ++// Bit 31 :28 reg_tx_priority_nonqos U RW default = 'h0 ++typedef union MAC_TXCONTROL_NONQOS_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_slot_num_o_nonqos : 10; ++ unsigned int reg_tx_duration_nonqos : 6; ++ unsigned int reg_aifsn_nonqos : 4; ++ unsigned int reg_cca_busy_mask_nonqos : 4; ++ unsigned int reg_tx_enable_nonqos : 1; ++ unsigned int reg_tx_bandwidth_nonqos : 2; ++ unsigned int rsvd_0 : 1; ++ unsigned int reg_tx_priority_nonqos : 4; ++ } b; ++} MAC_TXCONTROL_NONQOS_FIELD_T; ++ ++#define MAC_TXCONTROL_ACP0 (WIFI_MAC_TIMER_REG_BASE + 0x104) ++// Bit 9 :0 reg_slot_num_o_acp0 U RW default = 'h0 ++// Bit 15 :10 reg_tx_duration_acp0 U RW default = 'h8 ++// Bit 19 :16 reg_aifsn_acp0 U RW default = 'h0 ++// Bit 23 :20 reg_cca_busy_mask_acp0 U RW default = 'h0 ++// Bit 24 reg_tx_enable_acp0 U RW default = 'h0 ++// Bit 26 :25 reg_tx_bandwidth_acp0 U RW default = 'h0 ++// Bit 31 :28 reg_tx_priority_acp0 U RW default = 'h0 ++typedef union MAC_TXCONTROL_ACP0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_slot_num_o_acp0 : 10; ++ unsigned int reg_tx_duration_acp0 : 6; ++ unsigned int reg_aifsn_acp0 : 4; ++ unsigned int reg_cca_busy_mask_acp0 : 4; ++ unsigned int reg_tx_enable_acp0 : 1; ++ unsigned int reg_tx_bandwidth_acp0 : 2; ++ unsigned int rsvd_0 : 1; ++ unsigned int reg_tx_priority_acp0 : 4; ++ } b; ++} MAC_TXCONTROL_ACP0_FIELD_T; ++ ++#define MAC_TXCONTROL_ACP1 (WIFI_MAC_TIMER_REG_BASE + 0x108) ++// Bit 9 :0 reg_slot_num_o_acp1 U RW default = 'h0 ++// Bit 15 :10 reg_tx_duration_acp1 U RW default = 'h8 ++// Bit 19 :16 reg_aifsn_acp1 U RW default = 'h0 ++// Bit 23 :20 reg_cca_busy_mask_acp1 U RW default = 'h0 ++// Bit 24 reg_tx_enable_acp1 U RW default = 'h0 ++// Bit 26 :25 reg_tx_bandwidth_acp1 U RW default = 'h0 ++// Bit 31 :28 reg_tx_priority_acp1 U RW default = 'h0 ++typedef union MAC_TXCONTROL_ACP1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_slot_num_o_acp1 : 10; ++ unsigned int reg_tx_duration_acp1 : 6; ++ unsigned int reg_aifsn_acp1 : 4; ++ unsigned int reg_cca_busy_mask_acp1 : 4; ++ unsigned int reg_tx_enable_acp1 : 1; ++ unsigned int reg_tx_bandwidth_acp1 : 2; ++ unsigned int rsvd_0 : 1; ++ unsigned int reg_tx_priority_acp1 : 4; ++ } b; ++} MAC_TXCONTROL_ACP1_FIELD_T; ++ ++#define MAC_TXCONTROL_ACP2 (WIFI_MAC_TIMER_REG_BASE + 0x10c) ++// Bit 9 :0 reg_slot_num_o_acp2 U RW default = 'h0 ++// Bit 15 :10 reg_tx_duration_acp2 U RW default = 'h8 ++// Bit 19 :16 reg_aifsn_acp2 U RW default = 'h0 ++// Bit 23 :20 reg_cca_busy_mask_acp2 U RW default = 'h0 ++// Bit 24 reg_tx_enable_acp2 U RW default = 'h0 ++// Bit 26 :25 reg_tx_bandwidth_acp2 U RW default = 'h0 ++// Bit 31 :28 reg_tx_priority_acp2 U RW default = 'h0 ++typedef union MAC_TXCONTROL_ACP2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_slot_num_o_acp2 : 10; ++ unsigned int reg_tx_duration_acp2 : 6; ++ unsigned int reg_aifsn_acp2 : 4; ++ unsigned int reg_cca_busy_mask_acp2 : 4; ++ unsigned int reg_tx_enable_acp2 : 1; ++ unsigned int reg_tx_bandwidth_acp2 : 2; ++ unsigned int rsvd_0 : 1; ++ unsigned int reg_tx_priority_acp2 : 4; ++ } b; ++} MAC_TXCONTROL_ACP2_FIELD_T; ++ ++#define MAC_TXCONTROL_ACP3 (WIFI_MAC_TIMER_REG_BASE + 0x110) ++// Bit 9 :0 reg_slot_num_o_acp3 U RW default = 'h0 ++// Bit 15 :10 reg_tx_duration_acp3 U RW default = 'h8 ++// Bit 19 :16 reg_aifsn_acp3 U RW default = 'h0 ++// Bit 23 :20 reg_cca_busy_mask_acp3 U RW default = 'h0 ++// Bit 24 reg_tx_enable_acp3 U RW default = 'h0 ++// Bit 26 :25 reg_tx_bandwidth_acp3 U RW default = 'h0 ++// Bit 31 :28 reg_tx_priority_acp3 U RW default = 'h0 ++typedef union MAC_TXCONTROL_ACP3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_slot_num_o_acp3 : 10; ++ unsigned int reg_tx_duration_acp3 : 6; ++ unsigned int reg_aifsn_acp3 : 4; ++ unsigned int reg_cca_busy_mask_acp3 : 4; ++ unsigned int reg_tx_enable_acp3 : 1; ++ unsigned int reg_tx_bandwidth_acp3 : 2; ++ unsigned int rsvd_0 : 1; ++ unsigned int reg_tx_priority_acp3 : 4; ++ } b; ++} MAC_TXCONTROL_ACP3_FIELD_T; ++ ++#define MAC_TXCONTROL_ACP4 (WIFI_MAC_TIMER_REG_BASE + 0x114) ++// Bit 9 :0 reg_slot_num_o_acp4 U RW default = 'h0 ++// Bit 15 :10 reg_tx_duration_acp4 U RW default = 'h8 ++// Bit 19 :16 reg_aifsn_acp4 U RW default = 'h0 ++// Bit 23 :20 reg_cca_busy_mask_acp4 U RW default = 'h0 ++// Bit 24 reg_tx_enable_acp4 U RW default = 'h0 ++// Bit 26 :25 reg_tx_bandwidth_acp4 U RW default = 'h0 ++// Bit 31 :28 reg_tx_priority_acp4 U RW default = 'h0 ++typedef union MAC_TXCONTROL_ACP4_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_slot_num_o_acp4 : 10; ++ unsigned int reg_tx_duration_acp4 : 6; ++ unsigned int reg_aifsn_acp4 : 4; ++ unsigned int reg_cca_busy_mask_acp4 : 4; ++ unsigned int reg_tx_enable_acp4 : 1; ++ unsigned int reg_tx_bandwidth_acp4 : 2; ++ unsigned int rsvd_0 : 1; ++ unsigned int reg_tx_priority_acp4 : 4; ++ } b; ++} MAC_TXCONTROL_ACP4_FIELD_T; ++ ++#define MAC_TXCONTROL_ACP5 (WIFI_MAC_TIMER_REG_BASE + 0x118) ++// Bit 9 :0 reg_slot_num_o_acp5 U RW default = 'h0 ++// Bit 15 :10 reg_tx_duration_acp5 U RW default = 'h8 ++// Bit 19 :16 reg_aifsn_acp5 U RW default = 'h0 ++// Bit 23 :20 reg_cca_busy_mask_acp5 U RW default = 'h0 ++// Bit 24 reg_tx_enable_acp5 U RW default = 'h0 ++// Bit 26 :25 reg_tx_bandwidth_acp5 U RW default = 'h0 ++// Bit 31 :28 reg_tx_priority_acp5 U RW default = 'h0 ++typedef union MAC_TXCONTROL_ACP5_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_slot_num_o_acp5 : 10; ++ unsigned int reg_tx_duration_acp5 : 6; ++ unsigned int reg_aifsn_acp5 : 4; ++ unsigned int reg_cca_busy_mask_acp5 : 4; ++ unsigned int reg_tx_enable_acp5 : 1; ++ unsigned int reg_tx_bandwidth_acp5 : 2; ++ unsigned int rsvd_0 : 1; ++ unsigned int reg_tx_priority_acp5 : 4; ++ } b; ++} MAC_TXCONTROL_ACP5_FIELD_T; ++ ++#define MAC_TXCONTROL_ACP6 (WIFI_MAC_TIMER_REG_BASE + 0x11c) ++// Bit 9 :0 reg_slot_num_o_acp6 U RW default = 'h0 ++// Bit 15 :10 reg_tx_duration_acp6 U RW default = 'h8 ++// Bit 19 :16 reg_aifsn_acp6 U RW default = 'h0 ++// Bit 23 :20 reg_cca_busy_mask_acp6 U RW default = 'h0 ++// Bit 24 reg_tx_enable_acp6 U RW default = 'h0 ++// Bit 26 :25 reg_tx_bandwidth_acp6 U RW default = 'h0 ++// Bit 31 :28 reg_tx_priority_acp6 U RW default = 'h0 ++typedef union MAC_TXCONTROL_ACP6_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_slot_num_o_acp6 : 10; ++ unsigned int reg_tx_duration_acp6 : 6; ++ unsigned int reg_aifsn_acp6 : 4; ++ unsigned int reg_cca_busy_mask_acp6 : 4; ++ unsigned int reg_tx_enable_acp6 : 1; ++ unsigned int reg_tx_bandwidth_acp6 : 2; ++ unsigned int rsvd_0 : 1; ++ unsigned int reg_tx_priority_acp6 : 4; ++ } b; ++} MAC_TXCONTROL_ACP6_FIELD_T; ++ ++#define MAC_TXCONTROL_ACP7 (WIFI_MAC_TIMER_REG_BASE + 0x120) ++// Bit 9 :0 reg_slot_num_o_acp7 U RW default = 'h0 ++// Bit 15 :10 reg_tx_duration_acp7 U RW default = 'h8 ++// Bit 19 :16 reg_aifsn_acp7 U RW default = 'h0 ++// Bit 23 :20 reg_cca_busy_mask_acp7 U RW default = 'h0 ++// Bit 24 reg_tx_enable_acp7 U RW default = 'h0 ++// Bit 26 :25 reg_tx_bandwidth_acp7 U RW default = 'h0 ++// Bit 31 :28 reg_tx_priority_acp7 U RW default = 'h0 ++typedef union MAC_TXCONTROL_ACP7_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_slot_num_o_acp7 : 10; ++ unsigned int reg_tx_duration_acp7 : 6; ++ unsigned int reg_aifsn_acp7 : 4; ++ unsigned int reg_cca_busy_mask_acp7 : 4; ++ unsigned int reg_tx_enable_acp7 : 1; ++ unsigned int reg_tx_bandwidth_acp7 : 2; ++ unsigned int rsvd_0 : 1; ++ unsigned int reg_tx_priority_acp7 : 4; ++ } b; ++} MAC_TXCONTROL_ACP7_FIELD_T; ++ ++#define MAC_VCSUPDATE (WIFI_MAC_TIMER_REG_BASE + 0x128) ++// Bit 25 :0 reg_vcs_time U RW default = 'h0 ++// Bit 26 reg_vcs_enb U RW default = 'h0 ++// Bit 28 :27 reg_vcs_source U RW default = 'h0 ++// Bit 30 ro_vcs_enable U RO default = 'h0 ++// Bit 31 reg_vcs_up_enb U RW default = 'h0 ++typedef union MAC_VCSUPDATE_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_vcs_time : 26; ++ unsigned int reg_vcs_enb : 1; ++ unsigned int reg_vcs_source : 2; ++ unsigned int rsvd_0 : 1; ++ unsigned int ro_vcs_enable : 1; ++ unsigned int reg_vcs_up_enb : 1; ++ } b; ++} MAC_VCSUPDATE_FIELD_T; ++ ++#define MAC_TIME_HIGH (WIFI_MAC_TIMER_REG_BASE + 0x12c) ++// Bit 31 :0 reg_mac_time_high U RO default = 'h0 ++typedef union MAC_TIME_HIGH_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_time_high : 32; ++ } b; ++} MAC_TIME_HIGH_FIELD_T; ++ ++#define MAC_TIME_LOW (WIFI_MAC_TIMER_REG_BASE + 0x130) ++// Bit 31 :0 reg_mac_time_low U RO default = 'h0 ++typedef union MAC_TIME_LOW_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_time_low : 32; ++ } b; ++} MAC_TIME_LOW_FIELD_T; ++ ++#endif ++ +diff --git a/drivers/net/wireless/w1/common/wifi_mac_tx_reg.h b/drivers/net/wireless/w1/common/wifi_mac_tx_reg.h +new file mode 100644 +index 0000000000000000000000000000000000000000..668baea16d4db17d6cdc7aea7ff5bf3c6ae64d64 +--- /dev/null ++++ b/drivers/net/wireless/w1/common/wifi_mac_tx_reg.h +@@ -0,0 +1,1341 @@ ++#ifdef WIFI_MAC_TX_REG ++#else ++#define WIFI_MAC_TX_REG ++ ++ ++#define WIFI_MAC_TX_REG_BASE (0xa00000) ++ ++#define MAC_TXSTARTTIME_HIGH (WIFI_MAC_TX_REG_BASE + 0x238) ++// Bit 31 :0 ro_mac_txstarttime_high U RO default = 'h0 ++typedef union MAC_TXSTARTTIME_HIGH_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_mac_txstarttime_high : 32; ++ } b; ++} MAC_TXSTARTTIME_HIGH_FIELD_T; ++ ++#define MAC_TXSTARTTIME_LOW (WIFI_MAC_TX_REG_BASE + 0x23c) ++// Bit 31 :0 ro_mac_txstarttime_low U RO default = 'h0 ++typedef union MAC_TXSTARTTIME_LOW_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_mac_txstarttime_low : 32; ++ } b; ++} MAC_TXSTARTTIME_LOW_FIELD_T; ++ ++#define MAC_TXENDTIME (WIFI_MAC_TX_REG_BASE + 0x240) ++// Bit 31 :0 ro_mac_txendtime U RO default = 'h0 ++typedef union MAC_TXENDTIME_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_mac_txendtime : 32; ++ } b; ++} MAC_TXENDTIME_FIELD_T; ++ ++#define MAC_TXPOINTER (WIFI_MAC_TX_REG_BASE + 0x244) ++// Bit 31 :0 reg_tx_table_ptr U RW default = 'h0 ++typedef union MAC_TXPOINTER_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_tx_table_ptr : 32; ++ } b; ++} MAC_TXPOINTER_FIELD_T; ++ ++#define MAC_TXCONTROL_FIAC (WIFI_MAC_TX_REG_BASE + 0x248) ++// Bit 15 :10 reg_tx_duration_fiac U RW default = 'h1 ++// Bit 24 reg_dcpready_fiac U RW default = 'h0 ++// Bit 31 :28 reg_tx_priority_fiac U RW default = 'h0 ++typedef union MAC_TXCONTROL_FIAC_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int rsvd_0 : 10; ++ unsigned int reg_tx_duration_fiac : 6; ++ unsigned int rsvd_1 : 8; ++ unsigned int reg_dcpready_fiac : 1; ++ unsigned int rsvd_2 : 3; ++ unsigned int reg_tx_priority_fiac : 4; ++ } b; ++} MAC_TXCONTROL_FIAC_FIELD_T; ++ ++#define MAC_TXWD_TIMER (WIFI_MAC_TX_REG_BASE + 0x24c) ++// Bit 23 :0 reg_tx_wd_timer_duration U RW default = 'h4e20 ++// Bit 31 reg_tx_wd_timer_en U RW default = 'h1 ++typedef union MAC_TXWD_TIMER_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_tx_wd_timer_duration : 24; ++ unsigned int rsvd_0 : 7; ++ unsigned int reg_tx_wd_timer_en : 1; ++ } b; ++} MAC_TXWD_TIMER_FIELD_T; ++ ++#define MAC_TXINFO (WIFI_MAC_TX_REG_BASE + 0x250) ++// Bit 0 reg_txend_queue_bitinfo0 U W1C default = 'h0 ++// Bit 1 reg_txend_queue_bitinfo1 U W1C default = 'h0 ++// Bit 2 reg_txend_queue_bitinfo2 U W1C default = 'h0 ++// Bit 3 reg_txend_queue_bitinfo3 U W1C default = 'h0 ++// Bit 4 reg_txend_queue_bitinfo4 U W1C default = 'h0 ++// Bit 5 reg_txend_queue_bitinfo5 U W1C default = 'h0 ++// Bit 6 reg_txend_queue_bitinfo6 U W1C default = 'h0 ++// Bit 7 reg_txend_queue_bitinfo7 U W1C default = 'h0 ++// Bit 8 reg_txend_queue_bitinfo8 U W1C default = 'h0 ++// Bit 9 reg_txend_queue_bitinfo9 U W1C default = 'h0 ++// Bit 25 :16 ro_txend_queue_errinfo U RO default = 'h0 ++typedef union MAC_TXINFO_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_txend_queue_bitinfo0 : 1; ++ unsigned int reg_txend_queue_bitinfo1 : 1; ++ unsigned int reg_txend_queue_bitinfo2 : 1; ++ unsigned int reg_txend_queue_bitinfo3 : 1; ++ unsigned int reg_txend_queue_bitinfo4 : 1; ++ unsigned int reg_txend_queue_bitinfo5 : 1; ++ unsigned int reg_txend_queue_bitinfo6 : 1; ++ unsigned int reg_txend_queue_bitinfo7 : 1; ++ unsigned int reg_txend_queue_bitinfo8 : 1; ++ unsigned int reg_txend_queue_bitinfo9 : 1; ++ unsigned int rsvd_0 : 6; ++ unsigned int ro_txend_queue_errinfo : 10; ++ unsigned int rsvd_1 : 6; ++ } b; ++} MAC_TXINFO_FIELD_T; ++ ++#define TX_CTRL_FRAME_SEND (WIFI_MAC_TX_REG_BASE + 0x258) ++// Bit 7 :0 reg_tx_other_info_len U RW default = 'h34 ++// Bit 10 :8 reg_dynamic_mcs U RW default = 'h1 ++// Bit 12 reg_dynamic_mcs_en U RW default = 'h1 ++// Bit 25 :16 reg_txout_time_thr U RW default = 'h320 ++// Bit 28 reg_txout_time_thr_en U RW default = 'h1 ++typedef union TX_CTRL_FRAME_SEND_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_tx_other_info_len : 8; ++ unsigned int reg_dynamic_mcs : 3; ++ unsigned int rsvd_0 : 1; ++ unsigned int reg_dynamic_mcs_en : 1; ++ unsigned int rsvd_1 : 3; ++ unsigned int reg_txout_time_thr : 10; ++ unsigned int rsvd_2 : 2; ++ unsigned int reg_txout_time_thr_en : 1; ++ unsigned int rsvd_3 : 3; ++ } b; ++} TX_CTRL_FRAME_SEND_FIELD_T; ++ ++#define TX_IAC_SEND_CTRL (WIFI_MAC_TX_REG_BASE + 0x25c) ++// Bit 0 reg_iac_frame_send U RW default = 'h0 ++// Bit 6 :4 reg_iac_frame_type U RW default = 'h0 ++// Bit 10 :8 reg_iac_tid_num U RW default = 'h0 ++// Bit 11 reg_iac_power_mode U RW default = 'h0 ++typedef union TX_IAC_SEND_CTRL_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_iac_frame_send : 1; ++ unsigned int rsvd_0 : 3; ++ unsigned int reg_iac_frame_type : 3; ++ unsigned int rsvd_1 : 1; ++ unsigned int reg_iac_tid_num : 3; ++ unsigned int reg_iac_power_mode : 1; ++ unsigned int rsvd_2 : 20; ++ } b; ++} TX_IAC_SEND_CTRL_FIELD_T; ++ ++#define TX_IAC_BAR_INFO (WIFI_MAC_TX_REG_BASE + 0x260) ++// Bit 3 :0 reg_iac_tid_0 U RW default = 'h0 ++// Bit 15 :4 reg_iac_bitmap_index_0 U RW default = 'h0 ++// Bit 19 :16 reg_iac_tid_1 U RW default = 'h0 ++// Bit 31 :20 reg_iac_bitmap_index_1 U RW default = 'h0 ++typedef union TX_IAC_BAR_INFO_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_iac_tid_0 : 4; ++ unsigned int reg_iac_bitmap_index_0 : 12; ++ unsigned int reg_iac_tid_1 : 4; ++ unsigned int reg_iac_bitmap_index_1 : 12; ++ } b; ++} TX_IAC_BAR_INFO_FIELD_T; ++ ++#define TXIAC_ADDR1_LOW (WIFI_MAC_TX_REG_BASE + 0x264) ++// Bit 31 :0 reg_txiac_addr1_low U RW default = 'h0 ++typedef union TXIAC_ADDR1_LOW_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_txiac_addr1_low : 32; ++ } b; ++} TXIAC_ADDR1_LOW_FIELD_T; ++ ++#define TXIAC_ADDR1_HIGH (WIFI_MAC_TX_REG_BASE + 0x268) ++// Bit 15 :0 reg_txiac_addr1_high U RW default = 'h0 ++typedef union TXIAC_ADDR1_HIGH_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_txiac_addr1_high : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} TXIAC_ADDR1_HIGH_FIELD_T; ++ ++#define TXIAC_ADDR2_LOW (WIFI_MAC_TX_REG_BASE + 0x26c) ++// Bit 31 :0 reg_txiac_addr2_low U RW default = 'h0 ++typedef union TXIAC_ADDR2_LOW_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_txiac_addr2_low : 32; ++ } b; ++} TXIAC_ADDR2_LOW_FIELD_T; ++ ++#define TXIAC_ADDR2_HIGH (WIFI_MAC_TX_REG_BASE + 0x270) ++// Bit 15 :0 reg_txiac_addr2_high U RW default = 'h0 ++typedef union TXIAC_ADDR2_HIGH_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_txiac_addr2_high : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} TXIAC_ADDR2_HIGH_FIELD_T; ++ ++#define TX_IAC_VECTOR (WIFI_MAC_TX_REG_BASE + 0x274) ++// Bit 31 :0 reg_txiac_vector U RW default = 'h0 ++typedef union TX_IAC_VECTOR_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_txiac_vector : 32; ++ } b; ++} TX_IAC_VECTOR_FIELD_T; ++ ++#define MAC_TXVECTOR_CONF (WIFI_MAC_TX_REG_BASE + 0x278) ++// Bit 15 :0 reg_mac_tx_service U RW default = 'h0 ++// Bit 18 :16 reg_mac_tx_htdltf_num U RW default = 'h1 ++// Bit 22 :20 reg_mac_tx_hteltf_num U RW default = 'h0 ++// Bit 26 :24 reg_mac_tx_vhtltf_num U RW default = 'h0 ++typedef union MAC_TXVECTOR_CONF_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_tx_service : 16; ++ unsigned int reg_mac_tx_htdltf_num : 3; ++ unsigned int rsvd_0 : 1; ++ unsigned int reg_mac_tx_hteltf_num : 3; ++ unsigned int rsvd_1 : 1; ++ unsigned int reg_mac_tx_vhtltf_num : 3; ++ unsigned int rsvd_2 : 5; ++ } b; ++} MAC_TXVECTOR_CONF_FIELD_T; ++ ++#define TXOP_REMAIN (WIFI_MAC_TX_REG_BASE + 0x27c) ++// Bit 14 :0 reg_txop_remain U RW default = 'h0 ++// Bit 25 :16 reg_rts_time U RW default = 'h0 ++// Bit 30 :28 reg_dyn_bwd_ctrl U RW default = 'h0 ++typedef union TXOP_REMAIN_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_txop_remain : 15; ++ unsigned int rsvd_0 : 1; ++ unsigned int reg_rts_time : 10; ++ unsigned int rsvd_1 : 2; ++ unsigned int reg_dyn_bwd_ctrl : 3; ++ unsigned int rsvd_2 : 1; ++ } b; ++} TXOP_REMAIN_FIELD_T; ++ ++#define FW_PKT_DURA_CALC_IN (WIFI_MAC_TX_REG_BASE + 0x280) ++// Bit 30 :0 reg_fw_pkt_dura_calc_in U RW default = 'h0 ++// Bit 31 reg_fw_pkt_dura_calc_req U RW default = 'h0 ++typedef union FW_PKT_DURA_CALC_IN_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_fw_pkt_dura_calc_in : 31; ++ unsigned int reg_fw_pkt_dura_calc_req : 1; ++ } b; ++} FW_PKT_DURA_CALC_IN_FIELD_T; ++ ++#define FW_PKT_DURA_CALC_OUT (WIFI_MAC_TX_REG_BASE + 0x284) ++// Bit 15 :0 ro_fw_pkt_dura_calc_out U RO default = 'h0 ++typedef union FW_PKT_DURA_CALC_OUT_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int ro_fw_pkt_dura_calc_out : 16; ++ unsigned int rsvd_0 : 16; ++ } b; ++} FW_PKT_DURA_CALC_OUT_FIELD_T; ++ ++#define TXOUT_ENDCNT_MAX (WIFI_MAC_TX_REG_BASE + 0x288) ++// Bit 3 :0 reg_txout_endcnt_max U RW default = 'h4 ++// Bit 15 :8 reg_tx_rts_rate U RW default = 'h4 ++// Bit 23 :16 reg_tx_time_gap U RW default = 'h10 ++typedef union TXOUT_ENDCNT_MAX_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_txout_endcnt_max : 4; ++ unsigned int rsvd_0 : 4; ++ unsigned int reg_tx_rts_rate : 8; ++ unsigned int reg_tx_time_gap : 8; ++ unsigned int rsvd_1 : 8; ++ } b; ++} TXOUT_ENDCNT_MAX_FIELD_T; ++ ++#define MAC_TXVECTOR_P1_NONQOS (WIFI_MAC_TX_REG_BASE + 0x28c) ++// Bit 29 :0 reg_mac_txvector_p1_nonqos U RW default = 'h0 ++// Bit 30 reg_mac_txvector_p1_nonqos_rts U RW default = 'h0 ++// Bit 31 reg_mac_txvector_p1_nonqos_cts U RW default = 'h0 ++typedef union MAC_TXVECTOR_P1_NONQOS_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_txvector_p1_nonqos : 30; ++ unsigned int reg_mac_txvector_p1_nonqos_rts : 1; ++ unsigned int reg_mac_txvector_p1_nonqos_cts : 1; ++ } b; ++} MAC_TXVECTOR_P1_NONQOS_FIELD_T; ++ ++#define MAC_TXVECTOR_P1_ACP0 (WIFI_MAC_TX_REG_BASE + 0x290) ++// Bit 29 :0 reg_mac_txvector_p1_acp0 U RW default = 'h0 ++// Bit 30 reg_mac_txvector_p1_acp0_rts U RW default = 'h0 ++// Bit 31 reg_mac_txvector_p1_acp0_cts U RW default = 'h0 ++typedef union MAC_TXVECTOR_P1_ACP0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_txvector_p1_acp0 : 30; ++ unsigned int reg_mac_txvector_p1_acp0_rts : 1; ++ unsigned int reg_mac_txvector_p1_acp0_cts : 1; ++ } b; ++} MAC_TXVECTOR_P1_ACP0_FIELD_T; ++ ++#define MAC_TXVECTOR_P1_ACP1 (WIFI_MAC_TX_REG_BASE + 0x294) ++// Bit 29 :0 reg_mac_txvector_p1_acp1 U RW default = 'h0 ++// Bit 30 reg_mac_txvector_p1_acp1_rts U RW default = 'h0 ++// Bit 31 reg_mac_txvector_p1_acp1_cts U RW default = 'h0 ++typedef union MAC_TXVECTOR_P1_ACP1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_txvector_p1_acp1 : 30; ++ unsigned int reg_mac_txvector_p1_acp1_rts : 1; ++ unsigned int reg_mac_txvector_p1_acp1_cts : 1; ++ } b; ++} MAC_TXVECTOR_P1_ACP1_FIELD_T; ++ ++#define MAC_TXVECTOR_P1_ACP2 (WIFI_MAC_TX_REG_BASE + 0x298) ++// Bit 29 :0 reg_mac_txvector_p1_acp2 U RW default = 'h0 ++// Bit 30 reg_mac_txvector_p1_acp2_rts U RW default = 'h0 ++// Bit 31 reg_mac_txvector_p1_acp2_cts U RW default = 'h0 ++typedef union MAC_TXVECTOR_P1_ACP2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_txvector_p1_acp2 : 30; ++ unsigned int reg_mac_txvector_p1_acp2_rts : 1; ++ unsigned int reg_mac_txvector_p1_acp2_cts : 1; ++ } b; ++} MAC_TXVECTOR_P1_ACP2_FIELD_T; ++ ++#define MAC_TXVECTOR_P1_ACP3 (WIFI_MAC_TX_REG_BASE + 0x29c) ++// Bit 29 :0 reg_mac_txvector_p1_acp3 U RW default = 'h0 ++// Bit 30 reg_mac_txvector_p1_acp3_rts U RW default = 'h0 ++// Bit 31 reg_mac_txvector_p1_acp3_cts U RW default = 'h0 ++typedef union MAC_TXVECTOR_P1_ACP3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_txvector_p1_acp3 : 30; ++ unsigned int reg_mac_txvector_p1_acp3_rts : 1; ++ unsigned int reg_mac_txvector_p1_acp3_cts : 1; ++ } b; ++} MAC_TXVECTOR_P1_ACP3_FIELD_T; ++ ++#define MAC_TXVECTOR_P1_ACP4 (WIFI_MAC_TX_REG_BASE + 0x2a0) ++// Bit 29 :0 reg_mac_txvector_p1_acp4 U RW default = 'h0 ++// Bit 30 reg_mac_txvector_p1_acp4_rts U RW default = 'h0 ++// Bit 31 reg_mac_txvector_p1_acp4_cts U RW default = 'h0 ++typedef union MAC_TXVECTOR_P1_ACP4_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_txvector_p1_acp4 : 30; ++ unsigned int reg_mac_txvector_p1_acp4_rts : 1; ++ unsigned int reg_mac_txvector_p1_acp4_cts : 1; ++ } b; ++} MAC_TXVECTOR_P1_ACP4_FIELD_T; ++ ++#define MAC_TXVECTOR_P1_ACP5 (WIFI_MAC_TX_REG_BASE + 0x2a4) ++// Bit 29 :0 reg_mac_txvector_p1_acp5 U RW default = 'h0 ++// Bit 30 reg_mac_txvector_p1_acp5_rts U RW default = 'h0 ++// Bit 31 reg_mac_txvector_p1_acp5_cts U RW default = 'h0 ++typedef union MAC_TXVECTOR_P1_ACP5_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_txvector_p1_acp5 : 30; ++ unsigned int reg_mac_txvector_p1_acp5_rts : 1; ++ unsigned int reg_mac_txvector_p1_acp5_cts : 1; ++ } b; ++} MAC_TXVECTOR_P1_ACP5_FIELD_T; ++ ++#define MAC_TXVECTOR_P1_ACP6 (WIFI_MAC_TX_REG_BASE + 0x2a8) ++// Bit 29 :0 reg_mac_txvector_p1_acp6 U RW default = 'h0 ++// Bit 30 reg_mac_txvector_p1_acp6_rts U RW default = 'h0 ++// Bit 31 reg_mac_txvector_p1_acp6_cts U RW default = 'h0 ++typedef union MAC_TXVECTOR_P1_ACP6_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_txvector_p1_acp6 : 30; ++ unsigned int reg_mac_txvector_p1_acp6_rts : 1; ++ unsigned int reg_mac_txvector_p1_acp6_cts : 1; ++ } b; ++} MAC_TXVECTOR_P1_ACP6_FIELD_T; ++ ++#define MAC_TXVECTOR_P1_ACP7 (WIFI_MAC_TX_REG_BASE + 0x2ac) ++// Bit 29 :0 reg_mac_txvector_p1_acp7 U RW default = 'h0 ++// Bit 30 reg_mac_txvector_p1_acp7_rts U RW default = 'h0 ++// Bit 31 reg_mac_txvector_p1_acp7_cts U RW default = 'h0 ++typedef union MAC_TXVECTOR_P1_ACP7_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_txvector_p1_acp7 : 30; ++ unsigned int reg_mac_txvector_p1_acp7_rts : 1; ++ unsigned int reg_mac_txvector_p1_acp7_cts : 1; ++ } b; ++} MAC_TXVECTOR_P1_ACP7_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL0 (WIFI_MAC_TX_REG_BASE + 0x2b4) ++// Bit 31 :0 reg_mac_rxpkt_control0 U RW default = 'he0000000 ++typedef union MAC_RXPKT_CONTROL0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control0 : 32; ++ } b; ++} MAC_RXPKT_CONTROL0_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL2 (WIFI_MAC_TX_REG_BASE + 0x2b8) ++// Bit 31 :0 reg_mac_rxpkt_control2 U RW default = 'he0000000 ++typedef union MAC_RXPKT_CONTROL2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control2 : 32; ++ } b; ++} MAC_RXPKT_CONTROL2_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL3 (WIFI_MAC_TX_REG_BASE + 0x2bc) ++// Bit 31 :0 reg_mac_rxpkt_control3 U RW default = 'h0 ++typedef union MAC_RXPKT_CONTROL3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control3 : 32; ++ } b; ++} MAC_RXPKT_CONTROL3_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL4 (WIFI_MAC_TX_REG_BASE + 0x2c0) ++// Bit 31 :0 reg_mac_rxpkt_control4 U RW default = 'he0000000 ++typedef union MAC_RXPKT_CONTROL4_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control4 : 32; ++ } b; ++} MAC_RXPKT_CONTROL4_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL6 (WIFI_MAC_TX_REG_BASE + 0x2c4) ++// Bit 31 :0 reg_mac_rxpkt_control6 U RW default = 'h20000000 ++typedef union MAC_RXPKT_CONTROL6_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control6 : 32; ++ } b; ++} MAC_RXPKT_CONTROL6_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL7 (WIFI_MAC_TX_REG_BASE + 0x2c8) ++// Bit 31 :0 reg_mac_rxpkt_control7 U RW default = 'h0 ++typedef union MAC_RXPKT_CONTROL7_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control7 : 32; ++ } b; ++} MAC_RXPKT_CONTROL7_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL8 (WIFI_MAC_TX_REG_BASE + 0x2cc) ++// Bit 31 :0 reg_mac_rxpkt_control8 U RW default = 'he0000000 ++typedef union MAC_RXPKT_CONTROL8_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control8 : 32; ++ } b; ++} MAC_RXPKT_CONTROL8_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL10 (WIFI_MAC_TX_REG_BASE + 0x2d0) ++// Bit 31 :0 reg_mac_rxpkt_control10 U RW default = 'h20000000 ++typedef union MAC_RXPKT_CONTROL10_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control10 : 32; ++ } b; ++} MAC_RXPKT_CONTROL10_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL11 (WIFI_MAC_TX_REG_BASE + 0x2d4) ++// Bit 31 :0 reg_mac_rxpkt_control11 U RW default = 'h0 ++typedef union MAC_RXPKT_CONTROL11_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control11 : 32; ++ } b; ++} MAC_RXPKT_CONTROL11_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL12 (WIFI_MAC_TX_REG_BASE + 0x2d8) ++// Bit 31 :0 reg_mac_rxpkt_control12 U RW default = 'he0000000 ++typedef union MAC_RXPKT_CONTROL12_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control12 : 32; ++ } b; ++} MAC_RXPKT_CONTROL12_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL14 (WIFI_MAC_TX_REG_BASE + 0x2dc) ++// Bit 31 :0 reg_mac_rxpkt_control14 U RW default = 'h20000000 ++typedef union MAC_RXPKT_CONTROL14_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control14 : 32; ++ } b; ++} MAC_RXPKT_CONTROL14_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL16 (WIFI_MAC_TX_REG_BASE + 0x2e0) ++// Bit 31 :0 reg_mac_rxpkt_control16 U RW default = 'he0000000 ++typedef union MAC_RXPKT_CONTROL16_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control16 : 32; ++ } b; ++} MAC_RXPKT_CONTROL16_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL18 (WIFI_MAC_TX_REG_BASE + 0x2e4) ++// Bit 31 :0 reg_mac_rxpkt_control18 U RW default = 'he0000000 ++typedef union MAC_RXPKT_CONTROL18_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control18 : 32; ++ } b; ++} MAC_RXPKT_CONTROL18_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL20 (WIFI_MAC_TX_REG_BASE + 0x2e8) ++// Bit 31 :0 reg_mac_rxpkt_control20 U RW default = 'he0000000 ++typedef union MAC_RXPKT_CONTROL20_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control20 : 32; ++ } b; ++} MAC_RXPKT_CONTROL20_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL22 (WIFI_MAC_TX_REG_BASE + 0x2ec) ++// Bit 31 :0 reg_mac_rxpkt_control22 U RW default = 'h0 ++typedef union MAC_RXPKT_CONTROL22_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control22 : 32; ++ } b; ++} MAC_RXPKT_CONTROL22_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL26 (WIFI_MAC_TX_REG_BASE + 0x2f0) ++// Bit 31 :0 reg_mac_rxpkt_control26 U RW default = 'h0 ++typedef union MAC_RXPKT_CONTROL26_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control26 : 32; ++ } b; ++} MAC_RXPKT_CONTROL26_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL29 (WIFI_MAC_TX_REG_BASE + 0x2f4) ++// Bit 31 :0 reg_mac_rxpkt_control29 U RW default = 'he0000000 ++typedef union MAC_RXPKT_CONTROL29_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control29 : 32; ++ } b; ++} MAC_RXPKT_CONTROL29_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL30 (WIFI_MAC_TX_REG_BASE + 0x2f8) ++// Bit 31 :0 reg_mac_rxpkt_control30 U RW default = 'h0 ++typedef union MAC_RXPKT_CONTROL30_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control30 : 32; ++ } b; ++} MAC_RXPKT_CONTROL30_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL32 (WIFI_MAC_TX_REG_BASE + 0x2fc) ++// Bit 31 :0 reg_mac_rxpkt_control32 U RW default = 'h20000000 ++typedef union MAC_RXPKT_CONTROL32_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control32 : 32; ++ } b; ++} MAC_RXPKT_CONTROL32_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL33 (WIFI_MAC_TX_REG_BASE + 0x300) ++// Bit 31 :0 reg_mac_rxpkt_control33 U RW default = 'hc0000000 ++typedef union MAC_RXPKT_CONTROL33_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control33 : 32; ++ } b; ++} MAC_RXPKT_CONTROL33_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL34 (WIFI_MAC_TX_REG_BASE + 0x304) ++// Bit 31 :0 reg_mac_rxpkt_control34 U RW default = 'he0000000 ++typedef union MAC_RXPKT_CONTROL34_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control34 : 32; ++ } b; ++} MAC_RXPKT_CONTROL34_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL36 (WIFI_MAC_TX_REG_BASE + 0x308) ++// Bit 31 :0 reg_mac_rxpkt_control36 U RW default = 'h20000000 ++typedef union MAC_RXPKT_CONTROL36_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control36 : 32; ++ } b; ++} MAC_RXPKT_CONTROL36_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL37 (WIFI_MAC_TX_REG_BASE + 0x30c) ++// Bit 31 :0 reg_mac_rxpkt_control37 U RW default = 'h0 ++typedef union MAC_RXPKT_CONTROL37_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control37 : 32; ++ } b; ++} MAC_RXPKT_CONTROL37_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL38 (WIFI_MAC_TX_REG_BASE + 0x310) ++// Bit 31 :0 reg_mac_rxpkt_control38 U RW default = 'h20000000 ++typedef union MAC_RXPKT_CONTROL38_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control38 : 32; ++ } b; ++} MAC_RXPKT_CONTROL38_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL40 (WIFI_MAC_TX_REG_BASE + 0x314) ++// Bit 31 :0 reg_mac_rxpkt_control40 U RW default = 'he0000000 ++typedef union MAC_RXPKT_CONTROL40_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control40 : 32; ++ } b; ++} MAC_RXPKT_CONTROL40_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL41 (WIFI_MAC_TX_REG_BASE + 0x318) ++// Bit 31 :0 reg_mac_rxpkt_control41 U RW default = 'he0000000 ++typedef union MAC_RXPKT_CONTROL41_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control41 : 32; ++ } b; ++} MAC_RXPKT_CONTROL41_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL42 (WIFI_MAC_TX_REG_BASE + 0x31c) ++// Bit 31 :0 reg_mac_rxpkt_control42 U RW default = 'h20000000 ++typedef union MAC_RXPKT_CONTROL42_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control42 : 32; ++ } b; ++} MAC_RXPKT_CONTROL42_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL44 (WIFI_MAC_TX_REG_BASE + 0x320) ++// Bit 31 :0 reg_mac_rxpkt_control44 U RW default = 'he0000000 ++typedef union MAC_RXPKT_CONTROL44_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control44 : 32; ++ } b; ++} MAC_RXPKT_CONTROL44_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL45 (WIFI_MAC_TX_REG_BASE + 0x324) ++// Bit 31 :0 reg_mac_rxpkt_control45 U RW default = 'hc0000000 ++typedef union MAC_RXPKT_CONTROL45_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control45 : 32; ++ } b; ++} MAC_RXPKT_CONTROL45_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL46 (WIFI_MAC_TX_REG_BASE + 0x328) ++// Bit 31 :0 reg_mac_rxpkt_control46 U RW default = 'h20000000 ++typedef union MAC_RXPKT_CONTROL46_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control46 : 32; ++ } b; ++} MAC_RXPKT_CONTROL46_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL48 (WIFI_MAC_TX_REG_BASE + 0x32c) ++// Bit 31 :0 reg_mac_rxpkt_control48 U RW default = 'he0000000 ++typedef union MAC_RXPKT_CONTROL48_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control48 : 32; ++ } b; ++} MAC_RXPKT_CONTROL48_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL49 (WIFI_MAC_TX_REG_BASE + 0x330) ++// Bit 31 :0 reg_mac_rxpkt_control49 U RW default = 'h0 ++typedef union MAC_RXPKT_CONTROL49_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control49 : 32; ++ } b; ++} MAC_RXPKT_CONTROL49_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL50 (WIFI_MAC_TX_REG_BASE + 0x334) ++// Bit 31 :0 reg_mac_rxpkt_control50 U RW default = 'he0000000 ++typedef union MAC_RXPKT_CONTROL50_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control50 : 32; ++ } b; ++} MAC_RXPKT_CONTROL50_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL52 (WIFI_MAC_TX_REG_BASE + 0x338) ++// Bit 31 :0 reg_mac_rxpkt_control52 U RW default = 'he0000000 ++typedef union MAC_RXPKT_CONTROL52_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control52 : 32; ++ } b; ++} MAC_RXPKT_CONTROL52_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL53 (WIFI_MAC_TX_REG_BASE + 0x33c) ++// Bit 31 :0 reg_mac_rxpkt_control53 U RW default = 'h0 ++typedef union MAC_RXPKT_CONTROL53_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control53 : 32; ++ } b; ++} MAC_RXPKT_CONTROL53_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL56 (WIFI_MAC_TX_REG_BASE + 0x340) ++// Bit 31 :0 reg_mac_rxpkt_control56 U RW default = 'h20000000 ++typedef union MAC_RXPKT_CONTROL56_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control56 : 32; ++ } b; ++} MAC_RXPKT_CONTROL56_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL57 (WIFI_MAC_TX_REG_BASE + 0x344) ++// Bit 31 :0 reg_mac_rxpkt_control57 U RW default = 'h0 ++typedef union MAC_RXPKT_CONTROL57_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control57 : 32; ++ } b; ++} MAC_RXPKT_CONTROL57_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL58 (WIFI_MAC_TX_REG_BASE + 0x348) ++// Bit 31 :0 reg_mac_rxpkt_control58 U RW default = 'h20000000 ++typedef union MAC_RXPKT_CONTROL58_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control58 : 32; ++ } b; ++} MAC_RXPKT_CONTROL58_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL61 (WIFI_MAC_TX_REG_BASE + 0x34c) ++// Bit 31 :0 reg_mac_rxpkt_control61 U RW default = 'h0 ++typedef union MAC_RXPKT_CONTROL61_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control61 : 32; ++ } b; ++} MAC_RXPKT_CONTROL61_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL62 (WIFI_MAC_TX_REG_BASE + 0x350) ++// Bit 31 :0 reg_mac_rxpkt_control62 U RW default = 'h20000000 ++typedef union MAC_RXPKT_CONTROL62_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control62 : 32; ++ } b; ++} MAC_RXPKT_CONTROL62_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL24 (WIFI_MAC_TX_REG_BASE + 0x354) ++// Bit 31 :0 reg_mac_rxpkt_control24 U RW default = 'h20000000 ++typedef union MAC_RXPKT_CONTROL24_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control24 : 32; ++ } b; ++} MAC_RXPKT_CONTROL24_FIELD_T; ++ ++#define MAC_11B_LUT_1M (WIFI_MAC_TX_REG_BASE + 0x358) ++// Bit 31 :0 reg_mac_11b_lut_1m U RW default = 'h0 ++typedef union MAC_11B_LUT_1M_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11b_lut_1m : 32; ++ } b; ++} MAC_11B_LUT_1M_FIELD_T; ++ ++#define MAC_11B_LUT_2M (WIFI_MAC_TX_REG_BASE + 0x35c) ++// Bit 31 :0 reg_mac_11b_lut_2m U RW default = 'h11010000 ++typedef union MAC_11B_LUT_2M_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11b_lut_2m : 32; ++ } b; ++} MAC_11B_LUT_2M_FIELD_T; ++ ++#define MAC_11B_LUT_5M (WIFI_MAC_TX_REG_BASE + 0x360) ++// Bit 31 :0 reg_mac_11b_lut_5m U RW default = 'h22020202 ++typedef union MAC_11B_LUT_5M_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11b_lut_5m : 32; ++ } b; ++} MAC_11B_LUT_5M_FIELD_T; ++ ++#define MAC_11B_LUT_11M (WIFI_MAC_TX_REG_BASE + 0x364) ++// Bit 31 :0 reg_mac_11b_lut_11m U RW default = 'h33030303 ++typedef union MAC_11B_LUT_11M_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11b_lut_11m : 32; ++ } b; ++} MAC_11B_LUT_11M_FIELD_T; ++ ++#define MAC_11G_LUT_6M (WIFI_MAC_TX_REG_BASE + 0x368) ++// Bit 31 :0 reg_mac_11g_lut_6m U RW default = 'h44040404 ++typedef union MAC_11G_LUT_6M_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11g_lut_6m : 32; ++ } b; ++} MAC_11G_LUT_6M_FIELD_T; ++ ++#define MAC_11G_LUT_9M (WIFI_MAC_TX_REG_BASE + 0x36c) ++// Bit 31 :0 reg_mac_11g_lut_9m U RW default = 'h44050505 ++typedef union MAC_11G_LUT_9M_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11g_lut_9m : 32; ++ } b; ++} MAC_11G_LUT_9M_FIELD_T; ++ ++#define MAC_11G_LUT_12M (WIFI_MAC_TX_REG_BASE + 0x370) ++// Bit 31 :0 reg_mac_11g_lut_12m U RW default = 'h55060606 ++typedef union MAC_11G_LUT_12M_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11g_lut_12m : 32; ++ } b; ++} MAC_11G_LUT_12M_FIELD_T; ++ ++#define MAC_11G_LUT_18M (WIFI_MAC_TX_REG_BASE + 0x374) ++// Bit 31 :0 reg_mac_11g_lut_18m U RW default = 'h55060606 ++typedef union MAC_11G_LUT_18M_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11g_lut_18m : 32; ++ } b; ++} MAC_11G_LUT_18M_FIELD_T; ++ ++#define MAC_11G_LUT_24M (WIFI_MAC_TX_REG_BASE + 0x378) ++// Bit 31 :0 reg_mac_11g_lut_24m U RW default = 'h56060606 ++typedef union MAC_11G_LUT_24M_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11g_lut_24m : 32; ++ } b; ++} MAC_11G_LUT_24M_FIELD_T; ++ ++#define MAC_11G_LUT_36M (WIFI_MAC_TX_REG_BASE + 0x37c) ++// Bit 31 :0 reg_mac_11g_lut_36m U RW default = 'h66080608 ++typedef union MAC_11G_LUT_36M_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11g_lut_36m : 32; ++ } b; ++} MAC_11G_LUT_36M_FIELD_T; ++ ++#define MAC_11G_LUT_48M (WIFI_MAC_TX_REG_BASE + 0x380) ++// Bit 31 :0 reg_mac_11g_lut_48m U RW default = 'h67080608 ++typedef union MAC_11G_LUT_48M_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11g_lut_48m : 32; ++ } b; ++} MAC_11G_LUT_48M_FIELD_T; ++ ++#define MAC_11G_LUT_54M (WIFI_MAC_TX_REG_BASE + 0x384) ++// Bit 31 :0 reg_mac_11g_lut_54m U RW default = 'h67080608 ++typedef union MAC_11G_LUT_54M_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11g_lut_54m : 32; ++ } b; ++} MAC_11G_LUT_54M_FIELD_T; ++ ++#define MAC_11N_LUT_MCS0 (WIFI_MAC_TX_REG_BASE + 0x388) ++// Bit 31 :0 reg_mac_11n_lut_mcs0 U RW default = 'h88800404 ++typedef union MAC_11N_LUT_MCS0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11n_lut_mcs0 : 32; ++ } b; ++} MAC_11N_LUT_MCS0_FIELD_T; ++ ++#define MAC_11N_LUT_MCS1 (WIFI_MAC_TX_REG_BASE + 0x38c) ++// Bit 31 :0 reg_mac_11n_lut_mcs1 U RW default = 'h99810606 ++typedef union MAC_11N_LUT_MCS1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11n_lut_mcs1 : 32; ++ } b; ++} MAC_11N_LUT_MCS1_FIELD_T; ++ ++#define MAC_11N_LUT_MCS2 (WIFI_MAC_TX_REG_BASE + 0x390) ++// Bit 31 :0 reg_mac_11n_lut_mcs2 U RW default = 'h9a810606 ++typedef union MAC_11N_LUT_MCS2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11n_lut_mcs2 : 32; ++ } b; ++} MAC_11N_LUT_MCS2_FIELD_T; ++ ++#define MAC_11N_LUT_MCS3 (WIFI_MAC_TX_REG_BASE + 0x394) ++// Bit 31 :0 reg_mac_11n_lut_mcs3 U RW default = 'hbb830608 ++typedef union MAC_11N_LUT_MCS3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11n_lut_mcs3 : 32; ++ } b; ++} MAC_11N_LUT_MCS3_FIELD_T; ++ ++#define MAC_11N_LUT_MCS4 (WIFI_MAC_TX_REG_BASE + 0x398) ++// Bit 31 :0 reg_mac_11n_lut_mcs4 U RW default = 'hbc830608 ++typedef union MAC_11N_LUT_MCS4_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11n_lut_mcs4 : 32; ++ } b; ++} MAC_11N_LUT_MCS4_FIELD_T; ++ ++#define MAC_11N_LUT_MCS5 (WIFI_MAC_TX_REG_BASE + 0x39c) ++// Bit 31 :0 reg_mac_11n_lut_mcs5 U RW default = 'hbd830608 ++typedef union MAC_11N_LUT_MCS5_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11n_lut_mcs5 : 32; ++ } b; ++} MAC_11N_LUT_MCS5_FIELD_T; ++ ++#define MAC_11N_LUT_MCS6 (WIFI_MAC_TX_REG_BASE + 0x3a0) ++// Bit 31 :0 reg_mac_11n_lut_mcs6 U RW default = 'hbe830608 ++typedef union MAC_11N_LUT_MCS6_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11n_lut_mcs6 : 32; ++ } b; ++} MAC_11N_LUT_MCS6_FIELD_T; ++ ++#define MAC_11N_LUT_MCS7 (WIFI_MAC_TX_REG_BASE + 0x3a4) ++// Bit 31 :0 reg_mac_11n_lut_mcs7 U RW default = 'hbe830606 ++typedef union MAC_11N_LUT_MCS7_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11n_lut_mcs7 : 32; ++ } b; ++} MAC_11N_LUT_MCS7_FIELD_T; ++ ++#define MAC_11AC_LUT_MCS0 (WIFI_MAC_TX_REG_BASE + 0x3a8) ++// Bit 31 :0 reg_mac_11ac_lut_mcs0 U RW default = 'h48040404 ++typedef union MAC_11AC_LUT_MCS0_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11ac_lut_mcs0 : 32; ++ } b; ++} MAC_11AC_LUT_MCS0_FIELD_T; ++ ++#define MAC_11AC_LUT_MCS1 (WIFI_MAC_TX_REG_BASE + 0x3ac) ++// Bit 31 :0 reg_mac_11ac_lut_mcs1 U RW default = 'h59060606 ++typedef union MAC_11AC_LUT_MCS1_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11ac_lut_mcs1 : 32; ++ } b; ++} MAC_11AC_LUT_MCS1_FIELD_T; ++ ++#define MAC_11AC_LUT_MCS2 (WIFI_MAC_TX_REG_BASE + 0x3b0) ++// Bit 31 :0 reg_mac_11ac_lut_mcs2 U RW default = 'h5a060606 ++typedef union MAC_11AC_LUT_MCS2_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11ac_lut_mcs2 : 32; ++ } b; ++} MAC_11AC_LUT_MCS2_FIELD_T; ++ ++#define MAC_11AC_LUT_MCS3 (WIFI_MAC_TX_REG_BASE + 0x3b4) ++// Bit 31 :0 reg_mac_11ac_lut_mcs3 U RW default = 'h6b080608 ++typedef union MAC_11AC_LUT_MCS3_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11ac_lut_mcs3 : 32; ++ } b; ++} MAC_11AC_LUT_MCS3_FIELD_T; ++ ++#define MAC_11AC_LUT_MCS4 (WIFI_MAC_TX_REG_BASE + 0x3b8) ++// Bit 31 :0 reg_mac_11ac_lut_mcs4 U RW default = 'h6c080608 ++typedef union MAC_11AC_LUT_MCS4_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11ac_lut_mcs4 : 32; ++ } b; ++} MAC_11AC_LUT_MCS4_FIELD_T; ++ ++#define MAC_11AC_LUT_MCS5 (WIFI_MAC_TX_REG_BASE + 0x3bc) ++// Bit 31 :0 reg_mac_11ac_lut_mcs5 U RW default = 'h6d080608 ++typedef union MAC_11AC_LUT_MCS5_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11ac_lut_mcs5 : 32; ++ } b; ++} MAC_11AC_LUT_MCS5_FIELD_T; ++ ++#define MAC_11AC_LUT_MCS6 (WIFI_MAC_TX_REG_BASE + 0x3c0) ++// Bit 31 :0 reg_mac_11ac_lut_mcs6 U RW default = 'h6e080608 ++typedef union MAC_11AC_LUT_MCS6_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11ac_lut_mcs6 : 32; ++ } b; ++} MAC_11AC_LUT_MCS6_FIELD_T; ++ ++#define MAC_11AC_LUT_MCS7 (WIFI_MAC_TX_REG_BASE + 0x3c4) ++// Bit 31 :0 reg_mac_11ac_lut_mcs7 U RW default = 'h6e080608 ++typedef union MAC_11AC_LUT_MCS7_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11ac_lut_mcs7 : 32; ++ } b; ++} MAC_11AC_LUT_MCS7_FIELD_T; ++ ++#define MAC_11AC_LUT_MCS8 (WIFI_MAC_TX_REG_BASE + 0x3c8) ++// Bit 31 :0 reg_mac_11ac_lut_mcs8 U RW default = 'h6f080608 ++typedef union MAC_11AC_LUT_MCS8_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11ac_lut_mcs8 : 32; ++ } b; ++} MAC_11AC_LUT_MCS8_FIELD_T; ++ ++#define MAC_11AC_LUT_MCS9 (WIFI_MAC_TX_REG_BASE + 0x3cc) ++// Bit 31 :0 reg_mac_11ac_lut_mcs9 U RW default = 'h6f0b080b ++typedef union MAC_11AC_LUT_MCS9_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_11ac_lut_mcs9 : 32; ++ } b; ++} MAC_11AC_LUT_MCS9_FIELD_T; ++ ++#define VID0_TIMESTAMP_HIGH (WIFI_MAC_TX_REG_BASE + 0x3d0) ++// Bit 31 :0 reg_vid0_timestamp_high U RW default = 'h0 ++typedef union VID0_TIMESTAMP_HIGH_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_vid0_timestamp_high : 32; ++ } b; ++} VID0_TIMESTAMP_HIGH_FIELD_T; ++ ++#define VID0_TIMESTAMP_LOW (WIFI_MAC_TX_REG_BASE + 0x3d4) ++// Bit 31 :0 reg_vid0_timestamp_low U RW default = 'h0 ++typedef union VID0_TIMESTAMP_LOW_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_vid0_timestamp_low : 32; ++ } b; ++} VID0_TIMESTAMP_LOW_FIELD_T; ++ ++#define VID1_TIMESTAMP_HIGH (WIFI_MAC_TX_REG_BASE + 0x3d8) ++// Bit 31 :0 reg_vid1_timestamp_high U RW default = 'h0 ++typedef union VID1_TIMESTAMP_HIGH_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_vid1_timestamp_high : 32; ++ } b; ++} VID1_TIMESTAMP_HIGH_FIELD_T; ++ ++#define VID1_TIMESTAMP_LOW (WIFI_MAC_TX_REG_BASE + 0x3dc) ++// Bit 31 :0 reg_vid1_timestamp_low U RW default = 'h0 ++typedef union VID1_TIMESTAMP_LOW_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_vid1_timestamp_low : 32; ++ } b; ++} VID1_TIMESTAMP_LOW_FIELD_T; ++ ++#define VID2_TIMESTAMP_HIGH (WIFI_MAC_TX_REG_BASE + 0x3e0) ++// Bit 31 :0 reg_vid2_timestamp_high U RW default = 'h0 ++typedef union VID2_TIMESTAMP_HIGH_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_vid2_timestamp_high : 32; ++ } b; ++} VID2_TIMESTAMP_HIGH_FIELD_T; ++ ++#define VID2_TIMESTAMP_LOW (WIFI_MAC_TX_REG_BASE + 0x3e4) ++// Bit 31 :0 reg_vid2_timestamp_low U RW default = 'h0 ++typedef union VID2_TIMESTAMP_LOW_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_vid2_timestamp_low : 32; ++ } b; ++} VID2_TIMESTAMP_LOW_FIELD_T; ++ ++#define VID3_TIMESTAMP_HIGH (WIFI_MAC_TX_REG_BASE + 0x3e8) ++// Bit 31 :0 reg_vid3_timestamp_high U RW default = 'h0 ++typedef union VID3_TIMESTAMP_HIGH_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_vid3_timestamp_high : 32; ++ } b; ++} VID3_TIMESTAMP_HIGH_FIELD_T; ++ ++#define VID3_TIMESTAMP_LOW (WIFI_MAC_TX_REG_BASE + 0x3ec) ++// Bit 31 :0 reg_vid3_timestamp_low U RW default = 'h0 ++typedef union VID3_TIMESTAMP_LOW_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_vid3_timestamp_low : 32; ++ } b; ++} VID3_TIMESTAMP_LOW_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL17 (WIFI_MAC_TX_REG_BASE + 0x3f0) ++// Bit 31 :0 reg_mac_rxpkt_control17 U RW default = 'hc0000000 ++typedef union MAC_RXPKT_CONTROL17_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control17 : 32; ++ } b; ++} MAC_RXPKT_CONTROL17_FIELD_T; ++ ++#define MAC_RXPKT_CONTROL21 (WIFI_MAC_TX_REG_BASE + 0x3f4) ++// Bit 31 :0 reg_mac_rxpkt_control21 U RW default = 'hc0000000 ++typedef union MAC_RXPKT_CONTROL21_FIELD ++{ ++ unsigned int data; ++ struct ++ { ++ unsigned int reg_mac_rxpkt_control21 : 32; ++ } b; ++} MAC_RXPKT_CONTROL21_FIELD_T; ++ ++#endif ++ diff --git a/drivers/net/wireless/w1/common/wifi_ofdm_addr.h b/drivers/net/wireless/w1/common/wifi_ofdm_addr.h new file mode 100644 -index 000000000000..37adb97d1353 +index 0000000000000000000000000000000000000000..37adb97d13539d56de1bfac614bb1bf436303d83 --- /dev/null +++ b/drivers/net/wireless/w1/common/wifi_ofdm_addr.h @@ -0,0 +1,8 @@ @@ -28062,7 +27871,7 @@ index 000000000000..37adb97d1353 + diff --git a/drivers/net/wireless/w1/common/wifi_phy_addr.h b/drivers/net/wireless/w1/common/wifi_phy_addr.h new file mode 100644 -index 000000000000..4020cc95188d +index 0000000000000000000000000000000000000000..4020cc95188dc300142d1b61bcca4f55aa95eb4f --- /dev/null +++ b/drivers/net/wireless/w1/common/wifi_phy_addr.h @@ -0,0 +1,15 @@ @@ -28083,7 +27892,7 @@ index 000000000000..4020cc95188d + diff --git a/drivers/net/wireless/w1/common/wifi_sdio_cfg_addr.h b/drivers/net/wireless/w1/common/wifi_sdio_cfg_addr.h new file mode 100644 -index 000000000000..181521572ad1 +index 0000000000000000000000000000000000000000..181521572ad1c152781b008581ca0be162cf044a --- /dev/null +++ b/drivers/net/wireless/w1/common/wifi_sdio_cfg_addr.h @@ -0,0 +1,37 @@ @@ -28126,7 +27935,7 @@ index 000000000000..181521572ad1 + diff --git a/drivers/net/wireless/w1/common/wifi_sdio_if_addr.h b/drivers/net/wireless/w1/common/wifi_sdio_if_addr.h new file mode 100644 -index 000000000000..bb92e6c95a6d +index 0000000000000000000000000000000000000000..bb92e6c95a6d95c271c8f76c9e936d44d3c4aa9b --- /dev/null +++ b/drivers/net/wireless/w1/common/wifi_sdio_if_addr.h @@ -0,0 +1,10 @@ @@ -28142,7 +27951,7 @@ index 000000000000..bb92e6c95a6d +#endif diff --git a/drivers/net/wireless/w1/common/wifi_sys_addr.h b/drivers/net/wireless/w1/common/wifi_sys_addr.h new file mode 100644 -index 000000000000..91937ac732f9 +index 0000000000000000000000000000000000000000..91937ac732f993a77308e8dc7d8a8880dd6e341f --- /dev/null +++ b/drivers/net/wireless/w1/common/wifi_sys_addr.h @@ -0,0 +1,21 @@ @@ -28169,7 +27978,7 @@ index 000000000000..91937ac732f9 + diff --git a/drivers/net/wireless/w1/common/wifi_top_addr.h b/drivers/net/wireless/w1/common/wifi_top_addr.h new file mode 100644 -index 000000000000..b9e82b28e295 +index 0000000000000000000000000000000000000000..b9e82b28e2952c8f7b722e4a10925ee53f221fcc --- /dev/null +++ b/drivers/net/wireless/w1/common/wifi_top_addr.h @@ -0,0 +1,27 @@ @@ -28202,7 +28011,7 @@ index 000000000000..b9e82b28e295 +#endif diff --git a/drivers/net/wireless/w1/common/wifi_uart_addr.h b/drivers/net/wireless/w1/common/wifi_uart_addr.h new file mode 100644 -index 000000000000..aa27adebfb2a +index 0000000000000000000000000000000000000000..aa27adebfb2a4b5ac2c35e858bda7849dd9db777 --- /dev/null +++ b/drivers/net/wireless/w1/common/wifi_uart_addr.h @@ -0,0 +1,41 @@ @@ -28249,10 +28058,10 @@ index 000000000000..aa27adebfb2a +#endif diff --git a/drivers/net/wireless/w1/vmac/Makefile b/drivers/net/wireless/w1/vmac/Makefile new file mode 100644 -index 000000000000..d552e804c66c +index 0000000000000000000000000000000000000000..f4ee56727c3bc1009e0d6b3c1e9050dba97f29eb --- /dev/null +++ b/drivers/net/wireless/w1/vmac/Makefile -@@ -0,0 +1,248 @@ +@@ -0,0 +1,249 @@ +ARCH?=arm64 + +ifeq ($(ARCH),) @@ -28324,7 +28133,6 @@ index 000000000000..d552e804c66c + +INCS := -I$(CUR_DIR) -I$(EXT_INCS) +KERNEL_SRC ?= $(KERNELDIR) -+ +#n=for normal mode,y=product mode +#n=not support WIFI_RF when boot up. y=support WIFI_RF when boot up +CONFIG_WIFI_RF_SUPPORT=y @@ -28405,6 +28213,10 @@ index 000000000000..d552e804c66c +EXTRA_CFLAGS += -DNOT_AMLOGIC_PLATFORM +endif + ++ifeq ($(CONFIG_LOW_MEMORY_PLATFORM),y) ++EXTRA_CFLAGS += -DLOW_MEMORY_PLATFORM ++endif ++ +ifeq ($(CONFIG_PT_SUPPORT),y) +$(warning Building PT image) +EXTRA_CFLAGS += -DDRV_PT_SUPPORT @@ -28463,7 +28275,6 @@ index 000000000000..d552e804c66c +else + +modules: -+ echo "W1SS1: make modules, PROJECT = $(PROJ_NAME)" + -rm ./print_version.c + perl ./create_version_file.pl + @echo "UNO_GXL_SUB_P200=$(UNO_GXL_SUB_P200)" @@ -28482,7 +28293,6 @@ index 000000000000..d552e804c66c +endif + +modules_install: -+ echo "W1SS1: make modules_install, PROJECT = $(PROJ_NAME)" + @$(MAKE) INSTALL_MOD_STRIP=1 M=$(M) -C $(KERNEL_SRC) modules_install + mkdir -p ${OUT_DIR}/../vendor_lib/modules + cd ${OUT_DIR}/$(M)/; find -name "*.ko" -exec cp {} ${OUT_DIR}/../vendor_lib/modules/ \; @@ -28503,10 +28313,10 @@ index 000000000000..d552e804c66c +endif diff --git a/drivers/net/wireless/w1/vmac/aml_static_buf.c b/drivers/net/wireless/w1/vmac/aml_static_buf.c new file mode 100644 -index 000000000000..fa50cf934ece +index 0000000000000000000000000000000000000000..863a79a71cd6523c5ebf970b22f3fa9de9ede33e --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_static_buf.c -@@ -0,0 +1,80 @@ +@@ -0,0 +1,69 @@ +/* + * drivers/amlogic/wifi/aml_static_buf.c + * @@ -28541,11 +28351,8 @@ index 000000000000..fa50cf934ece +#include +#endif + -+#ifdef NOT_AMLOGIC_PLATFORM +extern void *aml_mem_prealloc(int section, unsigned long size); -+#else -+extern void *bcmdhd_mem_prealloc(int section, unsigned long size); -+#endif ++ +enum aml_prealloc_index { + AML_RX_FIFO = 0, + AML_TX_DESC_BUF = 1 @@ -28565,11 +28372,7 @@ index 000000000000..fa50cf934ece + return NULL; + } + -+#ifdef NOT_AMLOGIC_PLATFORM + return aml_mem_prealloc(AML_RX, size); -+#else -+ return bcmdhd_mem_prealloc(AML_RX, size); -+#endif + } + if (section == AML_TX_DESC_BUF) { + if (size > AML_TX_DESC_BUF_SIZE) { @@ -28578,30 +28381,26 @@ index 000000000000..fa50cf934ece + return NULL; + } + -+#ifdef NOT_AMLOGIC_PLATFORM + return aml_mem_prealloc(AML_TX, size);; -+#else -+ return bcmdhd_mem_prealloc(AML_TX, size);; -+#endif + } + return NULL; +} + diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_drv_cfg_0.conf b/drivers/net/wireless/w1/vmac/aml_wifi_drv_cfg_0.conf new file mode 100644 -index 000000000000..09c4f41b34bf +index 0000000000000000000000000000000000000000..7a1cd22e76c4e4516422b7e08180270b0828adab --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_drv_cfg_0.conf @@ -0,0 +1,5 @@ -+#drv config band -+#2.4G band should set 2 -+#5G band should set 5 -+#both should set 6 ++#drv config band ++#2.4G band should set 2 ++#5G band should set 5 ++#both should set 6 +cfg_band=6 \ No newline at end of file diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_rf.txt b/drivers/net/wireless/w1/vmac/aml_wifi_rf.txt new file mode 100644 -index 000000000000..828f32e11c71 +index 0000000000000000000000000000000000000000..828f32e11c71237ecf4fe6467868a2f4b4b8ee9f --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_rf.txt @@ -0,0 +1,42 @@ @@ -28650,7 +28449,7 @@ index 000000000000..828f32e11c71 \ No newline at end of file diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_rf_0125.txt b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0125.txt new file mode 100644 -index 000000000000..8289daff448f +index 0000000000000000000000000000000000000000..8289daff448f96a15cd486c2c101aa4acb4072fe --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0125.txt @@ -0,0 +1,35 @@ @@ -28692,133 +28491,133 @@ index 000000000000..8289daff448f \ No newline at end of file diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_rf_0133.txt b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0133.txt new file mode 100644 -index 000000000000..3aaa53eb1de4 +index 0000000000000000000000000000000000000000..b53763887ded7d17e8e5729917d7f791e4fd501d --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0133.txt @@ -0,0 +1,35 @@ -+#config version info -+version=1 -+ -+#cali config -+cali_config=0x0 -+ -+#frequency offset -+freq_offset=0 -+htemp_freq_offset=4 -+ -+#p212 tssi offset cfg -+tssi_2g_offset=0xfc -+tssi_5g_offset_5200=0xf8 -+tssi_5g_offset_5400=0x0a -+tssi_5g_offset_5600=0xfc -+tssi_5g_offset_5800=0x18 -+ -+#wf2g spur remove enable cfg -+wf2g_spur_rmen=0 -+spur_freq=24478 -+ -+#rf count -+rf_count=2 -+ -+#wifi 2g/5g tx power table -+wftx_pwrtbl_en=1 -+ -+##0:11b(1,2) 1: 11b(5.5,11) 2:11a/g(6~12) 3:11a/g(18~36) 4:11a/g(48) 5:11a/g(54) -+##6:11n(MCS0~2) 7:11n(MCS3~5) 8:11n(MCS6) 9:11n(MCS7) 10:11ac(MCS0~2) -+##11:11n(MCS3~5) 12:11n(MCS6) 13:11n(MCS7) 14:11ac(MCS8) 15:11ac(MCS9) -+wf2g_20M_pwr_tbl=0xa0,0xa0,0x99,0x86,0x72,0x72,0x9d,0x88,0x6e,0x6e,0x84,0x7C,0x6C,0x6C,0x63,0x58 -+wf2g_40M_pwr_tbl=0xBA,0xBA,0xCB,0xCB,0xB5,0xB5,0x84,0x78,0x64,0x64,0x7C,0x75,0x6C,0x66,0x5D,0x58 -+wf5g_20M_pwr_tbl=0xBA,0xBA,0x78,0x6a,0x51,0x51,0x7e,0x62,0x52,0x44,0x7e,0x72,0x5C,0x5C,0x53,0x58 -+wf5g_40M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x76,0x68,0x52,0x52,0x7a,0x70,0x6C,0x66,0x5D,0x48 -+wf5g_80M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x7C,0x75,0x6C,0x6C,0x6F,0x6a,0x60,0x60,0x5a,0x3c ++#config version info ++version=1 ++ ++#cali config ++cali_config=0x0 ++ ++#frequency offset ++freq_offset=0 ++htemp_freq_offset=4 ++ ++#p212 tssi offset cfg ++tssi_2g_offset=0xfc ++tssi_5g_offset_5200=0xf8 ++tssi_5g_offset_5400=0x0a ++tssi_5g_offset_5600=0xfc ++tssi_5g_offset_5800=0x18 ++ ++#wf2g spur remove enable cfg ++wf2g_spur_rmen=0 ++spur_freq=24478 ++ ++#rf count ++rf_count=2 ++ ++#wifi 2g/5g tx power table ++wftx_pwrtbl_en=1 ++ ++##0:11b(1,2) 1: 11b(5.5,11) 2:11a/g(6~12) 3:11a/g(18~36) 4:11a/g(48) 5:11a/g(54) ++##6:11n(MCS0~2) 7:11n(MCS3~5) 8:11n(MCS6) 9:11n(MCS7) 10:11ac(MCS0~2) ++##11:11n(MCS3~5) 12:11n(MCS6) 13:11n(MCS7) 14:11ac(MCS8) 15:11ac(MCS9) ++wf2g_20M_pwr_tbl=0xa0,0xa0,0x99,0x86,0x72,0x72,0x9d,0x88,0x6e,0x6e,0x84,0x7C,0x6C,0x6C,0x63,0x58 ++wf2g_40M_pwr_tbl=0xBA,0xBA,0xCB,0xCB,0xB5,0xB5,0x84,0x78,0x64,0x64,0x7C,0x75,0x6C,0x66,0x5D,0x58 ++wf5g_20M_pwr_tbl=0xBA,0xBA,0x78,0x6a,0x51,0x51,0x7e,0x62,0x52,0x44,0x7e,0x72,0x5C,0x5C,0x53,0x58 ++wf5g_40M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x76,0x68,0x52,0x52,0x7a,0x70,0x6C,0x66,0x5D,0x48 ++wf5g_80M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x7C,0x75,0x6C,0x6C,0x6F,0x6a,0x60,0x60,0x5a,0x3c diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_rf_0211.txt b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0211.txt new file mode 100644 -index 000000000000..cb50b7b8118f +index 0000000000000000000000000000000000000000..ce6badb658eb74a72919ac350f016cc01c51d0e2 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0211.txt @@ -0,0 +1,36 @@ -+#config version info -W511 -+version=1 -+ -+#cali config -+cali_config=0x0 -+ -+#frequency offset -+freq_offset=0 -+htemp_freq_offset=4 -+ -+#p212 tssi offset cfg -+tssi_2g_offset=0xef -+tssi_5g_offset_5200=0xec -+tssi_5g_offset_5400=0xf2 -+tssi_5g_offset_5600=0xf8 -+tssi_5g_offset_5800=0x02 -+ -+#wf2g spur remove enable cfg -+wf2g_spur_rmen=0 -+spur_freq=24478 -+ -+#rf count -+rf_count=1 -+ -+#wifi 2g/5g tx power table -+wftx_pwrtbl_en=1 -+ -+##0:11b(1,2) 1: 11b(5.5,11) 2:11a/g(6~12) 3:11a/g(18~36) 4:11a/g(48) 5:11a/g(54) -+##6:11n(MCS0~2) 7:11n(MCS3~5) 8:11n(MCS6) 9:11n(MCS7) 10:11ac(MCS0~2) -+##11:11n(MCS3~5) 12:11n(MCS6) 13:11n(MCS7) 14:11ac(MCS8) 15:11ac(MCS9) -+wf2g_20M_pwr_tbl=0xBA,0xBA,0xaB,0xaB,0xa5,0xa5,0xb0,0xa5,0x91,0x91,0x84,0x7C,0x6C,0x6C,0x63,0x58 -+wf2g_40M_pwr_tbl=0xBA,0xBA,0xCB,0xCB,0xB5,0xB5,0xA6,0xA1,0x94,0x94,0x7C,0x75,0x6C,0x66,0x5D,0x58 -+wf5g_20M_pwr_tbl=0xBA,0xBA,0x78,0x78,0x65,0x65,0x84,0x7c,0x6c,0x6c,0x74,0x6C,0x5C,0x5C,0x53,0x58 -+wf5g_40M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x6C,0x65,0x5C,0x5C,0x6C,0x65,0x5C,0x56,0x4D,0x48 -+wf5g_80M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x7C,0x75,0x6C,0x6C,0x7F,0x7F,0x60,0x60,0x50,0x4f -+ ++#config version info -W511 ++version=1 ++ ++#cali config ++cali_config=0x0 ++ ++#frequency offset ++freq_offset=0 ++htemp_freq_offset=4 ++ ++#p212 tssi offset cfg ++tssi_2g_offset=0xef ++tssi_5g_offset_5200=0xec ++tssi_5g_offset_5400=0xf2 ++tssi_5g_offset_5600=0xf8 ++tssi_5g_offset_5800=0x02 ++ ++#wf2g spur remove enable cfg ++wf2g_spur_rmen=0 ++spur_freq=24478 ++ ++#rf count ++rf_count=1 ++ ++#wifi 2g/5g tx power table ++wftx_pwrtbl_en=1 ++ ++##0:11b(1,2) 1: 11b(5.5,11) 2:11a/g(6~12) 3:11a/g(18~36) 4:11a/g(48) 5:11a/g(54) ++##6:11n(MCS0~2) 7:11n(MCS3~5) 8:11n(MCS6) 9:11n(MCS7) 10:11ac(MCS0~2) ++##11:11n(MCS3~5) 12:11n(MCS6) 13:11n(MCS7) 14:11ac(MCS8) 15:11ac(MCS9) ++wf2g_20M_pwr_tbl=0xBA,0xBA,0xaB,0xaB,0xa5,0xa5,0xb0,0xa5,0x91,0x91,0x84,0x7C,0x6C,0x6C,0x63,0x58 ++wf2g_40M_pwr_tbl=0xBA,0xBA,0xCB,0xCB,0xB5,0xB5,0xA6,0xA1,0x94,0x94,0x7C,0x75,0x6C,0x66,0x5D,0x58 ++wf5g_20M_pwr_tbl=0xBA,0xBA,0x78,0x78,0x65,0x65,0x84,0x7c,0x6c,0x6c,0x74,0x6C,0x5C,0x5C,0x53,0x58 ++wf5g_40M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x6C,0x65,0x5C,0x5C,0x6C,0x65,0x5C,0x56,0x4D,0x48 ++wf5g_80M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x7C,0x75,0x6C,0x6C,0x7F,0x7F,0x60,0x60,0x50,0x4f ++ diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_rf_0231.txt b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0231.txt new file mode 100644 -index 000000000000..619bdf8e6615 +index 0000000000000000000000000000000000000000..7766ab0bc8bfae2f4486c6f4165c3a876fdeca57 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0231.txt @@ -0,0 +1,37 @@ -+#config version info -W522A -+version=1 -+ -+#cali config -+cali_config=0x0 -+ -+#frequency offset -+freq_offset=0x05 -+htemp_freq_offset=4 -+ -+#p212 tssi offset cfg -+tssi_2g_offset=0xef -+tssi_5g_offset_5200=0xec -+tssi_5g_offset_5400=0xf2 -+tssi_5g_offset_5600=0xf8 -+tssi_5g_offset_5800=0x04 -+ -+#wf2g spur remove enable cfg -+wf2g_spur_rmen=0 -+spur_freq=24478 -+ -+#rf count -+rf_count=2 -+ -+#wifi 2g/5g tx power table -+wftx_pwrtbl_en=1 -+ -+##0:11b(1,2) 1: 11b(5.5,11) 2:11a/g(6~12) 3:11a/g(18~36) 4:11a/g(48) 5:11a/g(54) -+##6:11n(MCS0~2) 7:11n(MCS3~5) 8:11n(MCS6) 9:11n(MCS7) 10:11ac(MCS0~2) -+##11:11n(MCS3~5) 12:11n(MCS6) 13:11n(MCS7) 14:11ac(MCS8) 15:11ac(MCS9) -+wf2g_20M_pwr_tbl=0xBA,0xBA,0xaB,0xaB,0xa5,0xa5,0xb0,0xa5,0x91,0x91,0x84,0x7C,0x6C,0x6C,0x63,0x58 -+wf2g_40M_pwr_tbl=0xBA,0xBA,0xCB,0xCB,0xB5,0xB5,0xA6,0xA1,0x94,0x94,0x7C,0x75,0x6C,0x66,0x5D,0x58 -+wf5g_20M_pwr_tbl=0xBA,0xBA,0x78,0x78,0x65,0x65,0x84,0x7c,0x6c,0x6c,0x7d,0x75,0x6C,0x6C,0x5d,0x58 -+wf5g_40M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x6C,0x65,0x5C,0x5C,0x74,0x75,0x6C,0x66,0x5D,0x50 -+wf5g_80M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x7C,0x75,0x6C,0x6C,0x7F,0x7F,0x60,0x60,0x50,0x4f -+ -+ ++#config version info -W522A ++version=1 ++ ++#cali config ++cali_config=0x0 ++ ++#frequency offset ++freq_offset=0x05 ++htemp_freq_offset=4 ++ ++#p212 tssi offset cfg ++tssi_2g_offset=0xef ++tssi_5g_offset_5200=0xec ++tssi_5g_offset_5400=0xf2 ++tssi_5g_offset_5600=0xf8 ++tssi_5g_offset_5800=0x04 ++ ++#wf2g spur remove enable cfg ++wf2g_spur_rmen=0 ++spur_freq=24478 ++ ++#rf count ++rf_count=2 ++ ++#wifi 2g/5g tx power table ++wftx_pwrtbl_en=1 ++ ++##0:11b(1,2) 1: 11b(5.5,11) 2:11a/g(6~12) 3:11a/g(18~36) 4:11a/g(48) 5:11a/g(54) ++##6:11n(MCS0~2) 7:11n(MCS3~5) 8:11n(MCS6) 9:11n(MCS7) 10:11ac(MCS0~2) ++##11:11n(MCS3~5) 12:11n(MCS6) 13:11n(MCS7) 14:11ac(MCS8) 15:11ac(MCS9) ++wf2g_20M_pwr_tbl=0xBA,0xBA,0xaB,0xaB,0xa5,0xa5,0xb0,0xa5,0x91,0x91,0x84,0x7C,0x6C,0x6C,0x63,0x58 ++wf2g_40M_pwr_tbl=0xBA,0xBA,0xCB,0xCB,0xB5,0xB5,0xA6,0xA1,0x94,0x94,0x7C,0x75,0x6C,0x66,0x5D,0x58 ++wf5g_20M_pwr_tbl=0xBA,0xBA,0x78,0x78,0x65,0x65,0x84,0x7c,0x6c,0x6c,0x7d,0x75,0x6C,0x6C,0x5d,0x58 ++wf5g_40M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x6C,0x65,0x5C,0x5C,0x74,0x75,0x6C,0x66,0x5D,0x50 ++wf5g_80M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x7C,0x75,0x6C,0x6C,0x7F,0x7F,0x60,0x60,0x50,0x4f ++ ++ diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_rf_0321.txt b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0321.txt new file mode 100644 -index 000000000000..95bf1ea35223 +index 0000000000000000000000000000000000000000..95bf1ea352233363407bd2d505ee5ec8fc7afbe9 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0321.txt @@ -0,0 +1,35 @@ @@ -28860,7 +28659,7 @@ index 000000000000..95bf1ea35223 \ No newline at end of file diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_rf_0331.txt b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0331.txt new file mode 100644 -index 000000000000..95bf1ea35223 +index 0000000000000000000000000000000000000000..95bf1ea352233363407bd2d505ee5ec8fc7afbe9 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0331.txt @@ -0,0 +1,35 @@ @@ -28902,7 +28701,7 @@ index 000000000000..95bf1ea35223 \ No newline at end of file diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_rf_0333.txt b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0333.txt new file mode 100644 -index 000000000000..95bf1ea35223 +index 0000000000000000000000000000000000000000..95bf1ea352233363407bd2d505ee5ec8fc7afbe9 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0333.txt @@ -0,0 +1,35 @@ @@ -28944,49 +28743,49 @@ index 000000000000..95bf1ea35223 \ No newline at end of file diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_rf_0531.txt b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0531.txt new file mode 100644 -index 000000000000..13bfbf8a2350 +index 0000000000000000000000000000000000000000..06fe1123d830860622bb8b12ef95e01d6c320bf6 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0531.txt @@ -0,0 +1,35 @@ -+#config version info -+version=1 -+ -+#cali config -+cali_config=0x0 -+ -+#frequency offset -+freq_offset=4 -+htemp_freq_offset=1 -+ -+#p212 tssi offset cfg -+tssi_2g_offset=0xf1 -+tssi_5g_offset_5200=0xf0 -+tssi_5g_offset_5400=0xf0 -+tssi_5g_offset_5600=0xf8 -+tssi_5g_offset_5800=0x01 -+ -+#wf2g spur remove enable cfg -+wf2g_spur_rmen=0 -+spur_freq=24478 -+ -+#rf count -+rf_count=2 -+ -+#wifi 2g/5g tx power table -+wftx_pwrtbl_en=1 -+ -+##0:11b(1,2) 1: 11b(5.5,11) 2:11a/g(6~12) 3:11a/g(18~36) 4:11a/g(48) 5:11a/g(54) -+##6:11n(MCS0~2) 7:11n(MCS3~5) 8:11n(MCS6) 9:11n(MCS7) 10:11ac(MCS0~2) -+##11:11n(MCS3~5) 12:11n(MCS6) 13:11n(MCS7) 14:11ac(MCS8) 15:11ac(MCS9) -+wf2g_20M_pwr_tbl=0xC4,0xC4,0xBB,0xA0,0x94,0x94,0xB0,0x8D,0x87,0x87,0x84,0x7C,0x6C,0x6C,0x63,0x58 -+wf2g_40M_pwr_tbl=0xBA,0xBA,0xCB,0xCB,0xB5,0xB5,0xAA,0x8A,0x84,0x84,0x74,0x75,0x6C,0x66,0x5D,0x58 -+wf5g_20M_pwr_tbl=0xBA,0xBA,0x7D,0x6C,0x68,0x6A,0x7A,0x60,0x59,0x65,0x7A,0x62,0x5F,0x5D,0x5A,0x62 -+wf5g_40M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x78,0x58,0x58,0x61,0x54,0x44,0x43,0x43,0x42,0x4A ++#config version info ++version=1 ++ ++#cali config ++cali_config=0x0 ++ ++#frequency offset ++freq_offset=4 ++htemp_freq_offset=1 ++ ++#p212 tssi offset cfg ++tssi_2g_offset=0xf1 ++tssi_5g_offset_5200=0xf0 ++tssi_5g_offset_5400=0xf0 ++tssi_5g_offset_5600=0xf8 ++tssi_5g_offset_5800=0x01 ++ ++#wf2g spur remove enable cfg ++wf2g_spur_rmen=0 ++spur_freq=24478 ++ ++#rf count ++rf_count=2 ++ ++#wifi 2g/5g tx power table ++wftx_pwrtbl_en=1 ++ ++##0:11b(1,2) 1: 11b(5.5,11) 2:11a/g(6~12) 3:11a/g(18~36) 4:11a/g(48) 5:11a/g(54) ++##6:11n(MCS0~2) 7:11n(MCS3~5) 8:11n(MCS6) 9:11n(MCS7) 10:11ac(MCS0~2) ++##11:11n(MCS3~5) 12:11n(MCS6) 13:11n(MCS7) 14:11ac(MCS8) 15:11ac(MCS9) ++wf2g_20M_pwr_tbl=0xC4,0xC4,0xBB,0xA0,0x94,0x94,0xB0,0x8D,0x87,0x87,0x84,0x7C,0x6C,0x6C,0x63,0x58 ++wf2g_40M_pwr_tbl=0xBA,0xBA,0xCB,0xCB,0xB5,0xB5,0xAA,0x8A,0x84,0x84,0x74,0x75,0x6C,0x66,0x5D,0x58 ++wf5g_20M_pwr_tbl=0xBA,0xBA,0x7D,0x6C,0x68,0x6A,0x7A,0x60,0x59,0x65,0x7A,0x62,0x5F,0x5D,0x5A,0x62 ++wf5g_40M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x78,0x58,0x58,0x61,0x54,0x44,0x43,0x43,0x42,0x4A +wf5g_80M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x7C,0x75,0x6C,0x6C,0x63,0x4D,0x4A,0x4A,0x4E,0x4E \ No newline at end of file diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_rf_0631.txt b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0631.txt new file mode 100644 -index 000000000000..5ce34d3ea668 +index 0000000000000000000000000000000000000000..5ce34d3ea6685b45b7390f13bf53226c0227fdb9 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0631.txt @@ -0,0 +1,35 @@ @@ -29027,7 +28826,7 @@ index 000000000000..5ce34d3ea668 +wf5g_80M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x7C,0x75,0x6C,0x6C,0x7F,0x6F,0x60,0x60,0x60,0x46 diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_rf_0632.txt b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0632.txt new file mode 100644 -index 000000000000..5ce34d3ea668 +index 0000000000000000000000000000000000000000..5ce34d3ea6685b45b7390f13bf53226c0227fdb9 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0632.txt @@ -0,0 +1,35 @@ @@ -29068,7 +28867,7 @@ index 000000000000..5ce34d3ea668 +wf5g_80M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x7C,0x75,0x6C,0x6C,0x7F,0x6F,0x60,0x60,0x60,0x46 diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_rf_0633.txt b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0633.txt new file mode 100644 -index 000000000000..983a5c22c966 +index 0000000000000000000000000000000000000000..983a5c22c966eea38abce1c086d45b710a2ff461 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0633.txt @@ -0,0 +1,35 @@ @@ -29109,7 +28908,7 @@ index 000000000000..983a5c22c966 +wf5g_80M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x7C,0x75,0x6C,0x6C,0x8F,0x7F,0x70,0x68,0x60,0x56 diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_rf_0731.txt b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0731.txt new file mode 100644 -index 000000000000..f88b100ba66f +index 0000000000000000000000000000000000000000..f88b100ba66f11ba2939b84ee954edf26a653148 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0731.txt @@ -0,0 +1,35 @@ @@ -29151,7 +28950,7 @@ index 000000000000..f88b100ba66f \ No newline at end of file diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_rf_0a11.txt b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0a11.txt new file mode 100644 -index 000000000000..610b6086bdb0 +index 0000000000000000000000000000000000000000..610b6086bdb0ff2bd4e7bb2f4ef91ea4a112808c --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0a11.txt @@ -0,0 +1,35 @@ @@ -29192,7 +28991,7 @@ index 000000000000..610b6086bdb0 +wf5g_80M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x7C,0x75,0x6C,0x6C,0x6F,0x6F,0x60,0x60,0x60,0x58 diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_rf_0a31.txt b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0a31.txt new file mode 100644 -index 000000000000..5a34b11af886 +index 0000000000000000000000000000000000000000..5a34b11af8862effd237102661b9de9abc0dd378 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_rf_0a31.txt @@ -0,0 +1,35 @@ @@ -29233,7 +29032,7 @@ index 000000000000..5a34b11af886 +wf5g_80M_pwr_tbl=0xBA,0xBA,0x84,0x84,0x75,0x75,0x7C,0x75,0x6C,0x6C,0x6F,0x6F,0x60,0x60,0x60,0x58 diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_rf_ampak.txt b/drivers/net/wireless/w1/vmac/aml_wifi_rf_ampak.txt new file mode 100644 -index 000000000000..13aae771acc4 +index 0000000000000000000000000000000000000000..13aae771acc485a2dc08c541eb9ab2b8d7ec5c05 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_rf_ampak.txt @@ -0,0 +1,38 @@ @@ -29278,7 +29077,7 @@ index 000000000000..13aae771acc4 \ No newline at end of file diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_rf_fn_link.txt b/drivers/net/wireless/w1/vmac/aml_wifi_rf_fn_link.txt new file mode 100644 -index 000000000000..13aae771acc4 +index 0000000000000000000000000000000000000000..13aae771acc485a2dc08c541eb9ab2b8d7ec5c05 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_rf_fn_link.txt @@ -0,0 +1,38 @@ @@ -29323,7 +29122,7 @@ index 000000000000..13aae771acc4 \ No newline at end of file diff --git a/drivers/net/wireless/w1/vmac/aml_wifi_rf_iton.txt b/drivers/net/wireless/w1/vmac/aml_wifi_rf_iton.txt new file mode 100644 -index 000000000000..13aae771acc4 +index 0000000000000000000000000000000000000000..13aae771acc485a2dc08c541eb9ab2b8d7ec5c05 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/aml_wifi_rf_iton.txt @@ -0,0 +1,38 @@ @@ -29368,7 +29167,7 @@ index 000000000000..13aae771acc4 \ No newline at end of file diff --git a/drivers/net/wireless/w1/vmac/create_version_file.pl b/drivers/net/wireless/w1/vmac/create_version_file.pl new file mode 100644 -index 000000000000..82713635503e +index 0000000000000000000000000000000000000000..1c1719ac1a044cac89241260aa62f9008680984f --- /dev/null +++ b/drivers/net/wireless/w1/vmac/create_version_file.pl @@ -0,0 +1,45 @@ @@ -29412,14 +29211,14 @@ index 000000000000..82713635503e + +print OUTPUT "#include \"wifi_hal_com.h\"\n\n"; +print OUTPUT "void print_driver_version(void) {\n"; -+print OUTPUT " printk(\"driver compile date: $date,driver hash: $drv_hash\\n\");\n"; -+print OUTPUT " printk(\"fw compile date: $fw_date,fw hash: $fw_hash,fw size: $fw_size\\n\");\n"; ++print OUTPUT " pr_info(\"driver compile date: $date,driver hash: $drv_hash\\n\");\n"; ++print OUTPUT " pr_info(\"fw compile date: $fw_date,fw hash: $fw_hash,fw size: $fw_size\\n\");\n"; +print OUTPUT "}\n"; + +close OUTPUT; diff --git a/drivers/net/wireless/w1/vmac/crypto/aes-ccm.c b/drivers/net/wireless/w1/vmac/crypto/aes-ccm.c new file mode 100644 -index 000000000000..ffc64471790a +index 0000000000000000000000000000000000000000..ffc64471790ac3dac6413136e770eecb4b03b543 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/aes-ccm.c @@ -0,0 +1,211 @@ @@ -29636,10 +29435,10 @@ index 000000000000..ffc64471790a +} diff --git a/drivers/net/wireless/w1/vmac/crypto/aes-ctr.c b/drivers/net/wireless/w1/vmac/crypto/aes-ctr.c new file mode 100644 -index 000000000000..7fa08b59c951 +index 0000000000000000000000000000000000000000..c8554b9745ea5a41793ca5eb5f441c1c073d8bf2 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/aes-ctr.c -@@ -0,0 +1,70 @@ +@@ -0,0 +1,72 @@ +/* + * AES-128/192/256 CTR + * @@ -29667,7 +29466,7 @@ index 000000000000..7fa08b59c951 + u8 *data, size_t data_len) +{ + void *ctx; -+ size_t j, len, left = data_len; ++ size_t j, left = data_len; + int i; + u8 *pos = data; + u8 counter[AES_BLOCK_SIZE], buf[AES_BLOCK_SIZE]; @@ -29678,6 +29477,8 @@ index 000000000000..7fa08b59c951 + os_memcpy(counter, nonce, AES_BLOCK_SIZE); + + while (left > 0) { ++ size_t len; ++ + aes_encrypt(ctx, counter, buf); + + len = (left < AES_BLOCK_SIZE) ? left : AES_BLOCK_SIZE; @@ -29712,7 +29513,7 @@ index 000000000000..7fa08b59c951 +} diff --git a/drivers/net/wireless/w1/vmac/crypto/aes-gcm.c b/drivers/net/wireless/w1/vmac/crypto/aes-gcm.c new file mode 100644 -index 000000000000..b8fedc13dbce +index 0000000000000000000000000000000000000000..b8fedc13dbce95bd8189a95997dbc54be792f0fc --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/aes-gcm.c @@ -0,0 +1,326 @@ @@ -30044,7 +29845,7 @@ index 000000000000..b8fedc13dbce +} diff --git a/drivers/net/wireless/w1/vmac/crypto/aes-internal-enc.c b/drivers/net/wireless/w1/vmac/crypto/aes-internal-enc.c new file mode 100644 -index 000000000000..dfbacd552efa +index 0000000000000000000000000000000000000000..dfbacd552efa4ec55deb9465909ff7cf69ff2709 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/aes-internal-enc.c @@ -0,0 +1,129 @@ @@ -30179,7 +29980,7 @@ index 000000000000..dfbacd552efa +} diff --git a/drivers/net/wireless/w1/vmac/crypto/aes-internal.c b/drivers/net/wireless/w1/vmac/crypto/aes-internal.c new file mode 100644 -index 000000000000..508342793165 +index 0000000000000000000000000000000000000000..50834279316566b1532793e811e5f6783824d468 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/aes-internal.c @@ -0,0 +1,843 @@ @@ -31028,7 +30829,7 @@ index 000000000000..508342793165 +} diff --git a/drivers/net/wireless/w1/vmac/crypto/aes-omac1.c b/drivers/net/wireless/w1/vmac/crypto/aes-omac1.c new file mode 100644 -index 000000000000..61428c6af6c3 +index 0000000000000000000000000000000000000000..61428c6af6c309c318f6d4b4ddb4913ed8f77e8f --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/aes-omac1.c @@ -0,0 +1,172 @@ @@ -31206,7 +31007,7 @@ index 000000000000..61428c6af6c3 +} diff --git a/drivers/net/wireless/w1/vmac/crypto/aes-siv.c b/drivers/net/wireless/w1/vmac/crypto/aes-siv.c new file mode 100644 -index 000000000000..27b8b0ffef2a +index 0000000000000000000000000000000000000000..27b8b0ffef2ae4efe6feb222113e629be7d290bc --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/aes-siv.c @@ -0,0 +1,207 @@ @@ -31419,7 +31220,7 @@ index 000000000000..27b8b0ffef2a +} diff --git a/drivers/net/wireless/w1/vmac/crypto/aes.h b/drivers/net/wireless/w1/vmac/crypto/aes.h new file mode 100644 -index 000000000000..8ab3de2ee83f +index 0000000000000000000000000000000000000000..8ab3de2ee83f390c0abc1cb3805f9352b03fb7e7 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/aes.h @@ -0,0 +1,21 @@ @@ -31446,7 +31247,7 @@ index 000000000000..8ab3de2ee83f +#endif /* AES_H */ diff --git a/drivers/net/wireless/w1/vmac/crypto/aes_i.h b/drivers/net/wireless/w1/vmac/crypto/aes_i.h new file mode 100644 -index 000000000000..54375cf35583 +index 0000000000000000000000000000000000000000..54375cf355837051c17f792828b1d7ba3f148418 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/aes_i.h @@ -0,0 +1,125 @@ @@ -31577,7 +31378,7 @@ index 000000000000..54375cf35583 +#endif /* AES_I_H */ diff --git a/drivers/net/wireless/w1/vmac/crypto/aes_siv.h b/drivers/net/wireless/w1/vmac/crypto/aes_siv.h new file mode 100644 -index 000000000000..fb05d80c1f12 +index 0000000000000000000000000000000000000000..fb05d80c1f12f68be46dd4125ec46f463a52d13b --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/aes_siv.h @@ -0,0 +1,21 @@ @@ -31604,7 +31405,7 @@ index 000000000000..fb05d80c1f12 +#endif /* AES_SIV_H */ diff --git a/drivers/net/wireless/w1/vmac/crypto/aes_wrap.h b/drivers/net/wireless/w1/vmac/crypto/aes_wrap.h new file mode 100644 -index 000000000000..5bad6adcfa90 +index 0000000000000000000000000000000000000000..5bad6adcfa9078860dd6a7e091ae2c0984c3f97e --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/aes_wrap.h @@ -0,0 +1,75 @@ @@ -31685,7 +31486,7 @@ index 000000000000..5bad6adcfa90 +#endif /* AES_WRAP_H */ diff --git a/drivers/net/wireless/w1/vmac/crypto/aml_crypto_wrap.c b/drivers/net/wireless/w1/vmac/crypto/aml_crypto_wrap.c new file mode 100644 -index 000000000000..33ba13ade187 +index 0000000000000000000000000000000000000000..4824d9357be470fdd35ac0ac9d95e717c540c022 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/aml_crypto_wrap.c @@ -0,0 +1,67 @@ @@ -31745,7 +31546,7 @@ index 000000000000..33ba13ade187 + err = vsnprintf(buf, MSG_LEN, fmt, args); + va_end(args); + -+ printk("%s", buf); ++ pr_info("%s", buf); +#undef MSG_LEN +} + @@ -31758,7 +31559,7 @@ index 000000000000..33ba13ade187 +} diff --git a/drivers/net/wireless/w1/vmac/crypto/aml_crypto_wrap.h b/drivers/net/wireless/w1/vmac/crypto/aml_crypto_wrap.h new file mode 100644 -index 000000000000..353b6d10adf2 +index 0000000000000000000000000000000000000000..353b6d10adf21813b15ce631496dc8a339c15d90 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/aml_crypto_wrap.h @@ -0,0 +1,117 @@ @@ -31881,7 +31682,7 @@ index 000000000000..353b6d10adf2 +#endif//_AML_CRYTO_WRAP_H_ diff --git a/drivers/net/wireless/w1/vmac/crypto/ccmp.c b/drivers/net/wireless/w1/vmac/crypto/ccmp.c new file mode 100644 -index 000000000000..5e17ba138eed +index 0000000000000000000000000000000000000000..35a900bb57d077d1090e0c118f2bf21a2373fbd6 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/ccmp.c @@ -0,0 +1,383 @@ @@ -32061,7 +31862,7 @@ index 000000000000..5e17ba138eed +} + + -+void ccmp_get_pn(u8 *pn, const u8 *data) ++static void ccmp_get_pn(u8 *pn, const u8 *data) +{ + pn[0] = data[7]; /* PN5 */ + pn[1] = data[6]; /* PN4 */ @@ -32270,7 +32071,7 @@ index 000000000000..5e17ba138eed +} diff --git a/drivers/net/wireless/w1/vmac/crypto/sha256-internal.c b/drivers/net/wireless/w1/vmac/crypto/sha256-internal.c new file mode 100644 -index 000000000000..6a89c4d15db7 +index 0000000000000000000000000000000000000000..6a89c4d15db71ba34a537e4934dda8127cd11c48 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/sha256-internal.c @@ -0,0 +1,230 @@ @@ -32506,7 +32307,7 @@ index 000000000000..6a89c4d15db7 +/* ===== end - public domain SHA256 implementation ===== */ diff --git a/drivers/net/wireless/w1/vmac/crypto/sha256-prf.c b/drivers/net/wireless/w1/vmac/crypto/sha256-prf.c new file mode 100644 -index 000000000000..14988cb18634 +index 0000000000000000000000000000000000000000..14988cb18634f7d2bed76dbe4e667fe3f9ade082 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/sha256-prf.c @@ -0,0 +1,109 @@ @@ -32621,7 +32422,7 @@ index 000000000000..14988cb18634 +} diff --git a/drivers/net/wireless/w1/vmac/crypto/sha256.c b/drivers/net/wireless/w1/vmac/crypto/sha256.c new file mode 100644 -index 000000000000..ea72732840c2 +index 0000000000000000000000000000000000000000..ea72732840c266222dd14d1a6b96be145829c526 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/sha256.c @@ -0,0 +1,104 @@ @@ -32731,7 +32532,7 @@ index 000000000000..ea72732840c2 +} diff --git a/drivers/net/wireless/w1/vmac/crypto/sha256.h b/drivers/net/wireless/w1/vmac/crypto/sha256.h new file mode 100644 -index 000000000000..5219022edd7d +index 0000000000000000000000000000000000000000..5219022edd7d636f4ff6d5abb603585bc6177a2a --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/sha256.h @@ -0,0 +1,30 @@ @@ -32767,7 +32568,7 @@ index 000000000000..5219022edd7d +#endif /* SHA256_H */ diff --git a/drivers/net/wireless/w1/vmac/crypto/sha256_i.h b/drivers/net/wireless/w1/vmac/crypto/sha256_i.h new file mode 100644 -index 000000000000..988aed1bcd4d +index 0000000000000000000000000000000000000000..988aed1bcd4db214ff904b0f6ed42cbd7e1e2b46 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/sha256_i.h @@ -0,0 +1,25 @@ @@ -32798,7 +32599,7 @@ index 000000000000..988aed1bcd4d +#endif /* SHA256_I_H */ diff --git a/drivers/net/wireless/w1/vmac/crypto/wlancrypto_wrap.h b/drivers/net/wireless/w1/vmac/crypto/wlancrypto_wrap.h new file mode 100644 -index 000000000000..c9e54e10d6ea +index 0000000000000000000000000000000000000000..c9e54e10d6ea155c3227dbd22873a16cb64935b5 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/crypto/wlancrypto_wrap.h @@ -0,0 +1,37 @@ @@ -32841,7 +32642,7 @@ index 000000000000..c9e54e10d6ea +#endif /* WLANCRYPTO_WRAP_H */ diff --git a/drivers/net/wireless/w1/vmac/dpd_memory_packet.h b/drivers/net/wireless/w1/vmac/dpd_memory_packet.h new file mode 100644 -index 000000000000..6b717ecd45e7 +index 0000000000000000000000000000000000000000..6b717ecd45e7cb5c2326f0a8ddb1a330571158b1 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/dpd_memory_packet.h @@ -0,0 +1,71 @@ @@ -32918,10 +32719,10 @@ index 000000000000..6b717ecd45e7 +#endif diff --git a/drivers/net/wireless/w1/vmac/opt_all.h b/drivers/net/wireless/w1/vmac/opt_all.h new file mode 100644 -index 000000000000..6784b8204ab1 +index 0000000000000000000000000000000000000000..6db59f5a76fd6c23fbc5dca2756b2f089afa4c45 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/opt_all.h -@@ -0,0 +1,268 @@ +@@ -0,0 +1,273 @@ +#ifndef _AML_OPT_ALL_H_ +#define _AML_OPT_ALL_H_ +#if defined (HAL_FPGA_VER) @@ -33012,6 +32813,8 @@ index 000000000000..6784b8204ab1 +#endif +/*End of HAL_FPGA_VER*/ + ++/* vendor remapped every pr_debug to pr_info here; keep the kernel's dynamic-debug pr_debug */ ++ +/*Start of HAL_SIM_VER*/ +#if defined (HAL_SIM_VER) + @@ -33020,8 +32823,12 @@ index 000000000000..6784b8204ab1 +#define BIT(n) (1UL<<(n)) +#define ALIGN(x,a) (((x)+(a)-1)&~((a)-1)) + -+ -+#define printk(...) do{if(FW_ID==1)io_printf("");else io_printf("");sv_time();io_printf(__VA_ARGS__);}while(0) ++#define pr_debug(...) do{if(FW_ID==1)io_printf("");else io_printf("");sv_time();io_printf(__VA_ARGS__);}while(0) ++#define pr_crit(...) pr_debug(__VA_ARGS__) ++#define pr_err(...) pr_debug(__VA_ARGS__) ++#define pr_warn(...) pr_debug(__VA_ARGS__) ++#define pr_info(...) pr_debug(__VA_ARGS__) ++#define pr_notice(...) pr_debug(__VA_ARGS__) +#define MODULE_LICENSE(a); +#define module_init(a); +#define module_exit(a); @@ -33117,7 +32924,6 @@ index 000000000000..6784b8204ab1 + +static void * OS_SKBBUF_FREE(struct sk_buff * skb) +{ -+ int i = 0; + skb->valid = 0; + return NULL; +} @@ -33192,7 +32998,7 @@ index 000000000000..6784b8204ab1 +#endif /*End of _AML_OPT_ALL_H_ */ diff --git a/drivers/net/wireless/w1/vmac/osdep.h b/drivers/net/wireless/w1/vmac/osdep.h new file mode 100644 -index 000000000000..f68a9e07e83c +index 0000000000000000000000000000000000000000..4075ccb3f24db9666ce9a967493cff371a408903 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/osdep.h @@ -0,0 +1,300 @@ @@ -33311,9 +33117,9 @@ index 000000000000..f68a9e07e83c + m_pn_buf[i].count++; + } + -+ printk("Zmalloc %p:%s\n", tmp, name); ++ pr_debug("Zmalloc %p:%s\n", tmp, name); + if (kmalloc_count >= 64) { -+ printk("amlogic WIFI:Array Overflow, please make sure array " ++ pr_err("amlogic WIFI:Array Overflow, please make sure array " + "length big enough in debug malloc process\n"); + } + return tmp; @@ -33333,7 +33139,7 @@ index 000000000000..f68a9e07e83c + f_pn_buf[i].count++; + } + -+ printk("kfree %p:%s\n", a, name); ++ pr_debug("kfree %p:%s\n", a, name); + if (kfree_count >= 64) { + ERROR_DEBUG_OUT("amlogic WIFI:Array Overflow, please make sure array " + "length big enough in debug malloc process\n"); @@ -33358,7 +33164,7 @@ index 000000000000..f68a9e07e83c +#endif + +#define NET_MALLOC(_size, _gfp, _str) ZMALLOC(ALIGN(_size + 1, 128), _str, _gfp) -+#define NET_FREE(_p, name) do { if ((_p) != NULL) FREE(_p, name); /* printk(" %s %d kfree %p \n",__func__,__LINE__,_p); */(_p) = NULL;} while(0) ++#define NET_FREE(_p, name) do { if ((_p) != NULL) FREE(_p, name); /* pr_debug(" %s %d kfree %p \n",__func__,__LINE__,_p); */(_p) = NULL;} while(0) + +#define CIRCLE_Add_One(_data,_total) do {\ + if((_data)== (_total)-1) \ @@ -33498,22 +33304,21 @@ index 000000000000..f68a9e07e83c +#endif diff --git a/drivers/net/wireless/w1/vmac/print_version.c b/drivers/net/wireless/w1/vmac/print_version.c new file mode 100644 -index 000000000000..cf26fe93550f +index 0000000000000000000000000000000000000000..ca5714e6144aaea2b76371979f8c493a63da5b5f --- /dev/null +++ b/drivers/net/wireless/w1/vmac/print_version.c -@@ -0,0 +1,6 @@ +@@ -0,0 +1,5 @@ +#include "wifi_hal_com.h" + +void print_driver_version(void) { -+ printk("driver compile date: 2021-12-24 18:32:09,driver hash: 33f8d79eac54ffddd3e2a4c92f50903e91b78580\n"); -+ printk("fw compile date: 2021-12-24 18:26:51,fw hash: ,fw size: 1071764\n"); ++ printk("driver version: v1.8.3.3_20260310-w1 driver:888ce88b817c15e731df70f+612585+643887+589776\n"); +} diff --git a/drivers/net/wireless/w1/vmac/rc80211_minstrel.c b/drivers/net/wireless/w1/vmac/rc80211_minstrel.c new file mode 100644 -index 000000000000..4a2a2f8fe34c +index 0000000000000000000000000000000000000000..b676e50ac5e95ddea1d0e285ccaa3a8080115aff --- /dev/null +++ b/drivers/net/wireless/w1/vmac/rc80211_minstrel.c -@@ -0,0 +1,870 @@ +@@ -0,0 +1,877 @@ +/* + * Copyright (C) 2008 Felix Fietkau + * @@ -33587,10 +33392,12 @@ index 000000000000..4a2a2f8fe34c +/* convert mac80211 rate index to local array index */ +static inline int rix_to_ndx(struct minstrel_sta_info *mi, int rix) +{ -+ int i = rix; ++ int i; ++ + for (i = rix; i >= 0; i--) + if (mi->r[i].rix == rix) + break; ++ + return i; +} + @@ -33617,10 +33424,11 @@ index 000000000000..4a2a2f8fe34c +static inline void minstrel_sort_best_tp_rates(struct minstrel_sta_info *mi, int i, u8 *tp_list) +{ + int j; -+ struct minstrel_rate_stats *tmp_mrs; + struct minstrel_rate_stats *cur_mrs = &mi->r[i].stats; + + for (j = MAX_THR_RATES; j > 0; --j) { ++ struct minstrel_rate_stats *tmp_mrs; ++ + tmp_mrs = &mi->r[tp_list[j - 1]].stats; + + mi->r[i].stats.tp_avg = minstrel_get_tp_avg(&mi->r[i], cur_mrs->prob_ewma); @@ -33677,13 +33485,14 @@ index 000000000000..4a2a2f8fe34c +} + +/* -+* Recalculate statistics and counters of a given rate -+*/ ++ * Recalculate statistics and counters of a given rate ++ */ +void minstrel_calc_rate_stats(struct minstrel_rate_stats *mrs) +{ -+ unsigned int cur_prob; + + if (unlikely(mrs->attempts > 0)) { ++ unsigned int cur_prob; ++ + cur_prob = MINSTREL_FRAC(mrs->success, mrs->attempts); + + if (unlikely(!mrs->att_hist)) { @@ -33706,7 +33515,7 @@ index 000000000000..4a2a2f8fe34c + mrs->attempts = 0; +} + -+unsigned int minstrel_legacy_rate_convert_to_ordinary(unsigned int rate) ++static unsigned int minstrel_legacy_rate_convert_to_ordinary(unsigned int rate) +{ + unsigned int ret = 0; + @@ -33864,12 +33673,14 @@ index 000000000000..4a2a2f8fe34c + struct minstrel_priv *mp = priv; + struct minstrel_sta_info *mi = priv_sta; + struct ieee80211_tx_rate *ar = info->status.rates; -+ int i, ndx; ++ int i; + int success; + + success = !!(info->flags & IEEE80211_TX_STAT_ACK); + + for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) { ++ int ndx; ++ + if (ar[i].idx < 0) + break; + @@ -33905,7 +33716,7 @@ index 000000000000..4a2a2f8fe34c + else if (info->control.use_cts_prot) + retry = MAX( 2, MIN(mr->retry_count_cts, retry)); + -+ //printk("%s retry_count_rtscts:%d, retry_count_cts:%d, retry:%d\n", ++ //pr_debug("%s retry_count_rtscts:%d, retry_count_cts:%d, retry:%d\n", + //__func__, mr->stats.retry_count_rtscts, mr->retry_count_cts, retry); + return retry; +} @@ -34087,7 +33898,6 @@ index 000000000000..4a2a2f8fe34c + struct minstrel_rate *mr = &mi->r[n]; + struct minstrel_rate_stats *mrs = &mi->r[n].stats; + unsigned int tx_time = 0, tx_time_cts = 0, tx_time_rtscts = 0; -+ unsigned int tx_time_single; + unsigned int cw = mp->cw_min; + int shift; + @@ -34113,6 +33923,8 @@ index 000000000000..4a2a2f8fe34c + tx_time = mr->perfect_tx_time + mi->sp_ack_dur; + + do { ++ unsigned int tx_time_single; ++ + /* add one retransmission */ + tx_time_single = mr->ack_time + mr->perfect_tx_time; + @@ -34146,7 +33958,7 @@ index 000000000000..4a2a2f8fe34c + + init_sample_table(mi); + minstrel_update_rates(mp, mi); -+ printk("%s(%d) n:%d\n", __func__, __LINE__, n); ++ pr_debug("%s(%d) n:%d\n", __func__, __LINE__, n); +} + +static void *minstrel_alloc_sta(void *priv, struct ieee80211_sta_aml *sta, gfp_t gfp) @@ -34386,7 +34198,7 @@ index 000000000000..4a2a2f8fe34c + diff --git a/drivers/net/wireless/w1/vmac/rc80211_minstrel.h b/drivers/net/wireless/w1/vmac/rc80211_minstrel.h new file mode 100644 -index 000000000000..85a3201273dc +index 0000000000000000000000000000000000000000..85a3201273dc459db3794cdcebdc8bcfb0aa0d30 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/rc80211_minstrel.h @@ -0,0 +1,233 @@ @@ -34625,10 +34437,10 @@ index 000000000000..85a3201273dc +#endif diff --git a/drivers/net/wireless/w1/vmac/rc80211_minstrel_ht.c b/drivers/net/wireless/w1/vmac/rc80211_minstrel_ht.c new file mode 100644 -index 000000000000..72f3e7af0920 +index 0000000000000000000000000000000000000000..7f3e3bcb46d5fc3b2bc1b734c283eb7b8aa3295e --- /dev/null +++ b/drivers/net/wireless/w1/vmac/rc80211_minstrel_ht.c -@@ -0,0 +1,1348 @@ +@@ -0,0 +1,1357 @@ +/* + * Copyright (C) 2010-2013 Felix Fietkau + * @@ -34842,17 +34654,18 @@ index 000000000000..72f3e7af0920 + u16 *tp_list) +{ + int cur_group, cur_idx, cur_tp_avg, cur_prob; -+ int tmp_group, tmp_idx, tmp_tp_avg, tmp_prob; + int j = MAX_THR_RATES; + + cur_group = index / MCS_GROUP_RATES; + cur_idx = index % MCS_GROUP_RATES; + cur_prob = mi->groups[cur_group].rates[cur_idx].prob_ewma; + cur_tp_avg = minstrel_ht_get_tp_avg(mi, cur_group, cur_idx, cur_prob); -+ /*for debug */ ++ /* for debug */ + mi->groups[cur_group].rates[cur_idx].tp_avg = cur_tp_avg; + + do { ++ int tmp_group, tmp_idx, tmp_tp_avg, tmp_prob; ++ + tmp_group = tp_list[j - 1] / MCS_GROUP_RATES; + tmp_idx = tp_list[j - 1] % MCS_GROUP_RATES; + tmp_prob = mi->groups[tmp_group].rates[tmp_idx].prob_ewma; @@ -34879,9 +34692,9 @@ index 000000000000..72f3e7af0920 + struct minstrel_mcs_group_data *mg; + struct minstrel_rate_stats *mrs; + int tmp_group, tmp_idx, tmp_tp_avg, tmp_prob; -+ int max_tp_group, cur_tp_avg, cur_group, cur_idx; ++ int max_tp_group, cur_group, cur_idx; + int max_gpr_group, max_gpr_idx; -+ int max_gpr_tp_avg, max_gpr_prob; ++ int max_gpr_prob; + + cur_group = index / MCS_GROUP_RATES; + cur_idx = index % MCS_GROUP_RATES; @@ -34905,6 +34718,8 @@ index 000000000000..72f3e7af0920 + max_gpr_prob = mi->groups[max_gpr_group].rates[max_gpr_idx].prob_ewma; + + if (mrs->prob_ewma > MINSTREL_FRAC(75, 100)) { ++ int cur_tp_avg, max_gpr_tp_avg; ++ + cur_tp_avg = minstrel_ht_get_tp_avg(mi, cur_group, cur_idx, mrs->prob_ewma); + if (cur_tp_avg > tmp_tp_avg) + mi->max_prob_rate = index; @@ -34933,7 +34748,6 @@ index 000000000000..72f3e7af0920 + u16 tmp_cck_tp_rate[MAX_THR_RATES]) +{ + unsigned int tmp_group, tmp_idx, tmp_cck_tp, tmp_mcs_tp, tmp_prob; -+ int i; + + tmp_group = tmp_cck_tp_rate[0] / MCS_GROUP_RATES; + tmp_idx = tmp_cck_tp_rate[0] % MCS_GROUP_RATES; @@ -34946,6 +34760,8 @@ index 000000000000..72f3e7af0920 + tmp_mcs_tp = minstrel_ht_get_tp_avg(mi, tmp_group, tmp_idx, tmp_prob); + + if (tmp_cck_tp > tmp_mcs_tp) { ++ int i; ++ + for(i = 0; i < MAX_THR_RATES; i++) { + minstrel_ht_sort_best_tp_rates(mi, tmp_cck_tp_rate[i], tmp_mcs_tp_rate); + } @@ -34954,8 +34770,6 @@ index 000000000000..72f3e7af0920 + +static void minstrel_ht_modify_tp_rates(struct minstrel_ht_sta *mi, u16 *tp_list, u16 *max_prob_rate) +{ -+ int cur_group, cur_idx, cur_tp_avg, cur_prob; -+ int final_idx, tmp_idx, tmp_tp_avg, tmp_prob; + int tp0_group = tp_list[0] / MCS_GROUP_RATES; + int tp0_idx = tp_list[0] % MCS_GROUP_RATES; + int rate_idx = tp0_idx; @@ -34970,6 +34784,9 @@ index 000000000000..72f3e7af0920 + tp0_idx = rate_idx; + + if ((*max_prob_rate % MCS_GROUP_RATES) >= tp0_idx) { ++ int cur_group, cur_idx, cur_tp_avg, cur_prob; ++ int final_idx, tmp_idx; ++ + cur_group = *max_prob_rate / MCS_GROUP_RATES; + cur_idx = tp0_idx ? tp0_idx -1 : tp0_idx; + cur_prob = mi->groups[cur_group].rates[cur_idx].prob_ewma; @@ -34977,6 +34794,8 @@ index 000000000000..72f3e7af0920 + final_idx = cur_idx; + + for (tmp_idx = cur_idx - 1; tmp_idx >= 0; tmp_idx--) { ++ int tmp_tp_avg, tmp_prob; ++ + tmp_prob = mi->groups[cur_group].rates[tmp_idx].prob_ewma; + tmp_tp_avg = minstrel_ht_get_tp_avg(mi, cur_group, tmp_idx, tmp_prob); + @@ -35034,7 +34853,7 @@ index 000000000000..72f3e7af0920 + + mrs = &mg->rates[i]; + if (mrs->succ_hist != 0) { -+ printk("clear rate:%d, input:%d\n", i, rate_index); ++ pr_debug("clear rate:%d, input:%d\n", i, rate_index); + mrs->attempts = 1; + mrs->last_attempts = 0; + mrs->att_hist = 0; @@ -35063,7 +34882,7 @@ index 000000000000..72f3e7af0920 +{ + struct minstrel_mcs_group_data *mg; + struct minstrel_rate_stats *mrs; -+ int group, i, j, cur_prob; ++ int group, i, j; + u16 tmp_mcs_tp_rate[MAX_THR_RATES], tmp_group_tp_rate[MAX_THR_RATES]; + u16 tmp_cck_tp_rate[MAX_THR_RATES], index; + @@ -35092,6 +34911,8 @@ index 000000000000..72f3e7af0920 + mi->sample_count++; + + for (i = 0; i < MCS_GROUP_RATES; i++) { ++ int cur_prob; ++ + if (!(mi->supported[group] & BIT(i))) + continue; + @@ -35160,9 +34981,10 @@ index 000000000000..72f3e7af0920 + struct minstrel_ht_sta *mi = &msp->ht; + struct minstrel_rate_stats *mrs; + int group; -+ unsigned char group_bw = 0; + + for (group = 0; group < ARRAY_SIZE(minstrel_mcs_groups); group++) { ++ unsigned char group_bw; ++ + group_bw = minstrel_mcs_groups[group].flags & IEEE80211_TX_RC_80_MHZ_WIDTH ? BW_80 + : minstrel_mcs_groups[group].flags & IEEE80211_TX_RC_40_MHZ_WIDTH ? BW_40 : BW_20; + @@ -35173,7 +34995,7 @@ index 000000000000..72f3e7af0920 + if (!(mi->supported[group] & BIT(max_rate))) + continue; + -+ printk("%s rate_index:%d, bw:%d\n", __func__, max_rate, bw); ++ pr_debug("%s rate_index:%d, bw:%d\n", __func__, max_rate, bw); + mrs = &mg->rates[max_rate]; + mrs->attempts = 2; + mrs->att_hist = 3; @@ -35213,9 +35035,9 @@ index 000000000000..72f3e7af0920 +static void +minstrel_set_next_sample_idx(struct minstrel_ht_sta *mi) +{ -+ struct minstrel_mcs_group_data *mg; -+ + for (;;) { ++ struct minstrel_mcs_group_data *mg; ++ + mi->sample_group++; + mi->sample_group %= ARRAY_SIZE(minstrel_mcs_groups); + mg = &mi->groups[mi->sample_group]; @@ -35265,7 +35087,7 @@ index 000000000000..72f3e7af0920 + struct ieee80211_tx_rate *ar = info->status.rates; + struct minstrel_rate_stats *rate, *rate2; + struct minstrel_priv *mp = priv; -+ bool last, update = false; ++ bool update = false; + int i; + + if (!msp->is_ht) @@ -35296,6 +35118,8 @@ index 000000000000..72f3e7af0920 + mi->sample_packets += info->status.ampdu_len; + + for (i = 0; i < 3; i++) { ++ bool last; ++ + last = !minstrel_ht_txstat_valid(mp, &ar[i + 1]); + + rate = minstrel_ht_get_stats(mp, mi, &ar[i]); @@ -35303,9 +35127,6 @@ index 000000000000..72f3e7af0920 + + if (last) { + rate->success += info->status.ampdu_ack_len; -+ } -+ -+ if (last) { + break; + } + } @@ -35776,7 +35597,7 @@ index 000000000000..72f3e7af0920 + continue; +#endif + mi->supported[i] = mcs->rx_mask[nss - 1]; -+ //printk("mi->supported:%08x:%d\n", mi->supported[i], i); ++ pr_debug("mi->supported:%08x:%d\n", mi->supported[i], i); + if (mi->supported[i]) + n_supported++; + continue; @@ -35810,7 +35631,7 @@ index 000000000000..72f3e7af0920 + } + + mi->supported[i] = minstrel_get_valid_vht_rates(bw, nss, vht_cap->vht_mcs.tx_mcs_map); -+ //printk("mi->supported:%08x:%d\n", mi->supported[i], i); ++ pr_debug("mi->supported:%08x:%d\n", mi->supported[i], i); + + if (mi->supported[i]) + n_supported++; @@ -35979,7 +35800,7 @@ index 000000000000..72f3e7af0920 +} diff --git a/drivers/net/wireless/w1/vmac/rc80211_minstrel_ht.h b/drivers/net/wireless/w1/vmac/rc80211_minstrel_ht.h new file mode 100644 -index 000000000000..d6243786c498 +index 0000000000000000000000000000000000000000..d6243786c498412e2b82a0ab59e34b6d65b8dfac --- /dev/null +++ b/drivers/net/wireless/w1/vmac/rc80211_minstrel_ht.h @@ -0,0 +1,284 @@ @@ -36269,7 +36090,7 @@ index 000000000000..d6243786c498 +#endif diff --git a/drivers/net/wireless/w1/vmac/rc80211_minstrel_init.c b/drivers/net/wireless/w1/vmac/rc80211_minstrel_init.c new file mode 100644 -index 000000000000..87898a956782 +index 0000000000000000000000000000000000000000..f75e31e5a77bec235d0ccd3d4bcd3401eab96573 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/rc80211_minstrel_init.c @@ -0,0 +1,907 @@ @@ -36464,14 +36285,14 @@ index 000000000000..87898a956782 +{ + struct minstrel_rate_control_ops *p_rate_control_ops = NULL; + -+ printk("%s\n", __func__); ++ pr_debug("%s\n", __func__); + g_aml_rate_adaptation_dev.ht_cap_info = 0; + p_rate_control_ops = get_rate_control_ops(); + p_rate_control_ops->free(g_minstel_pri); + g_minstel_pri = NULL; +} + -+unsigned int support_legacy_rate_init( struct wifi_station *sta , struct ieee80211_sta_aml *p_ieee_sta,unsigned int channel_band) ++static unsigned int support_legacy_rate_init( struct wifi_station *sta , struct ieee80211_sta_aml *p_ieee_sta,unsigned int channel_band) +{ + int i = 0; + unsigned int bit_val = 0; @@ -36545,7 +36366,7 @@ index 000000000000..87898a956782 + return 0; +} + -+void aml_rate_adaptation_dev_init(struct wifi_station *sta, int rate_mode, unsigned int channel_band, struct ieee80211_sta_aml *p_ieee_sta) ++static void aml_rate_adaptation_dev_init(struct wifi_station *sta, int rate_mode, unsigned int channel_band, struct ieee80211_sta_aml *p_ieee_sta) +{ + g_aml_rate_adaptation_dev.num_rf_chains = 1; + @@ -36572,19 +36393,19 @@ index 000000000000..87898a956782 + int i = 0; + g_aml_rate_adaptation_dev.sband = &aml_band_24ghz; + -+ printk("support rate start\n"); ++ pr_debug("support rate start\n"); + for (i = 0; i < sta->sta_rates.dot11_rate_num; i++) + { -+ printk("%02x ",sta->sta_rates.dot11_rate[i]); ++ pr_debug("%02x ",sta->sta_rates.dot11_rate[i]); + } -+ printk("\n"); ++ pr_debug("\n"); + } else { + g_aml_rate_adaptation_dev.sband = &aml_band_5ghz; + g_aml_rate_adaptation_dev.sband->vht_cap = aml_create_vht_cap(&g_aml_rate_adaptation_dev, rate_mode); + } +} + -+unsigned char get_fitable_bw(struct wifi_station *sta) { ++static unsigned char get_fitable_bw(struct wifi_station *sta) { + unsigned char bw; + + if (sta->sta_avg_bcn_rssi < sta->sta_wmac->wm_signal_power_bw_change_thresh_narrow) { @@ -36604,7 +36425,7 @@ index 000000000000..87898a956782 + return sta->sta_chbw; +} + -+unsigned char get_fitable_mcs_rate(struct wifi_station *sta, unsigned char bw) { ++static unsigned char get_fitable_mcs_rate(struct wifi_station *sta, unsigned char bw) { + int avg_rssi = 0; + unsigned char max_rate_rssi = 0; + unsigned char max_rate_snr = 0; @@ -36797,17 +36618,17 @@ index 000000000000..87898a956782 + struct wifi_station *sta = (struct wifi_station *)p_sta; + struct minstrel_rate_control_ops* p_rate_control_ops = NULL; + struct minstrel_rate_control_ops *p_rate_control_ops_ht = NULL; -+ printk("%s:%04x ", __func__, sta->sta_flags); ++ pr_debug("%s:%04x ", __func__, sta->sta_flags); + + if ((sta->sta_flags & WIFINET_NODE_VHT) || (sta->sta_flags & WIFINET_NODE_HT)) { + p_rate_control_ops_ht = get_rate_control_ops_ht(); -+ printk("ht free:%p\n", sta->sta_minstrel_ht_priv); ++ pr_debug("ht free:%p\n", sta->sta_minstrel_ht_priv); + p_rate_control_ops_ht->free_sta(sta->sta_minstrel_ht_priv); + sta->sta_minstrel_ht_priv = NULL; + + } else { + p_rate_control_ops = get_rate_control_ops(); -+ printk("free:%p\n", sta->sta_minstrel_info); ++ pr_debug("free:%p\n", sta->sta_minstrel_info); + p_rate_control_ops->free_sta(sta->sta_minstrel_info); + sta->sta_minstrel_info = NULL; + } @@ -36848,7 +36669,7 @@ index 000000000000..87898a956782 + rates[3].flags = 0; +} + -+int check_is_rate_fitable(struct wifi_station *sta, struct ieee80211_tx_info *info, void *priv_sta) { ++static int check_is_rate_fitable(struct wifi_station *sta, struct ieee80211_tx_info *info, void *priv_sta) { + struct minstrel_ht_sta_priv *msp = priv_sta; + struct minstrel_ht_sta *mi = &msp->ht; + int max_rate = 0; @@ -36889,7 +36710,7 @@ index 000000000000..87898a956782 + } +} + -+int minstrel_rate_index_to_vendor_rate_code(int minstrel_rate_idx, struct ieee80211_sta_aml *p_ieee80211_sta) ++static int minstrel_rate_index_to_vendor_rate_code(int minstrel_rate_idx, struct ieee80211_sta_aml *p_ieee80211_sta) +{ + enum ieee80211_band band = (enum ieee80211_band)g_aml_rate_adaptation_dev.sband->band; + @@ -36913,7 +36734,7 @@ index 000000000000..87898a956782 + return 0; +} + -+unsigned int protocol_rate_to_vendor_rate(unsigned int protocol_rate) ++static unsigned int protocol_rate_to_vendor_rate(unsigned int protocol_rate) +{ + + //For 11b: (0x82 -0x80) * 500K = 1M @@ -37175,140 +36996,140 @@ index 000000000000..87898a956782 + p_rate_control_ops->tx_status(g_minstel_pri, g_aml_rate_adaptation_dev.sband, priv_sta, &info); +} + -+void minstrel_set_sta_bandwidth( int bw ) ++static void minstrel_set_sta_bandwidth( int bw ) +{ + g_sta.bandwidth = bw; +} + diff --git a/drivers/net/wireless/w1/vmac/rc80211_minstrel_init.h b/drivers/net/wireless/w1/vmac/rc80211_minstrel_init.h new file mode 100644 -index 000000000000..d35e68cb7e3e +index 0000000000000000000000000000000000000000..bee322388d85b530b495dd80f8e7211c1b628efc --- /dev/null +++ b/drivers/net/wireless/w1/vmac/rc80211_minstrel_init.h @@ -0,0 +1,110 @@ -+#ifndef RC80211_MINSTREL_INIT_H -+#define RC80211_MINSTREL_INIT_H -+ -+#include "linux/types.h" -+ -+struct aml_rate_adaptation_dev { -+ struct ieee80211_supported_band *sband; -+ struct cfg80211_chan_def *chandef; -+ struct minstrel_priv *p_minstrel_priv; -+ u32 ht_cap_info; -+ u32 vht_cap_info; -+ u32 num_rf_chains; -+}; -+ -+/* HT Capabilities*/ -+#define WMI_HT_CAP_RX_STBC_MASK_SHIFT 4 -+#define WMI_HT_CAP_ENABLED 0x0001 /* HT Enabled/ disabled */ -+#define WMI_HT_CAP_TX_STBC 0x0002 /* B1 TX STBC */ -+#define WMI_HT_CAP_DYNAMIC_SMPS 0x0004 /* Dynamic MIMO powersave */ -+#define WMI_HT_CAP_HT20_SGI 0x0020 /* Short Guard Interval with HT20 */ -+#define WMI_HT_CAP_HT40_SGI 0x0040 -+#define WMI_HT_CAP_L_SIG_TXOP_PROT 0x0080 /* L-SIG TXOP Protection */ -+#define WMI_HT_CAP_LDPC 0x0200 /* LDPC supported */ -+#define WMI_HT_CAP_RX_STBC 0x0C00 /* B10-B11 RX STBC */ -+#define WMI_HT_CAP_MPDU_DENSITY 0x7000 /* MPDU Density */ -+ -+/* -+ * WMI_VHT_CAP_* these maps to ieee 802.11ac vht capability information -+ * field. The fields not defined here are not supported, or reserved. -+ * Do not change these masks and if you have to add new one follow the -+ * bitmask as specified by 802.11ac draft. -+ */ -+ -+#define WMI_VHT_CAP_MAX_MPDU_LEN_MASK 0x00000003 -+#define WMI_VHT_CAP_RX_LDPC 0x00000010 -+#define WMI_VHT_CAP_SGI_80MHZ 0x00000020 -+#define WMI_VHT_CAP_TX_STBC 0x00000080 -+#define WMI_VHT_CAP_RX_STBC_MASK 0x00000300 -+#define WMI_VHT_CAP_MAX_AMPDU_LEN_EXP 0x03800000 -+#define WMI_VHT_CAP_RX_FIXED_ANT 0x10000000 -+#define WMI_VHT_CAP_TX_FIXED_ANT 0x20000000 -+ -+/* The following also refer for max HT AMSDU */ -+#define WMI_VHT_CAP_MAX_MPDU_LEN_11454 0x00000002 -+ -+/* -+ * Interested readers refer to Rx/Tx MCS Map definition as defined in -+ * 802.11ac -+ */ -+#define WMI_VHT_MAX_SUPP_RATE_MASK 0x1fff0000 -+ -+#ifdef AUTO_RATE_SIM -+#define RATETAB_ENT(_rate, _rateid, _flags) { \ -+ .bitrate = (_rate), \ -+ .flags = (_flags), \ -+ .hw_value = (_rateid), \ -+} -+ -+#define CHAN2G(_channel, _freq, _flags) { \ -+ .band = IEEE80211_BAND_2GHZ, \ -+ .hw_value = (_channel), \ -+ .center_freq = (_freq), \ -+ .flags = (_flags), \ -+ .max_antenna_gain = 0, \ -+ .max_power = 30, \ -+} -+ -+#define CHAN5G(_channel, _flags) { \ -+ .band = IEEE80211_BAND_5GHZ, \ -+ .hw_value = (_channel), \ -+ .center_freq = 5000 + (5 * (_channel)), \ -+ .flags = (_flags), \ -+ .max_antenna_gain = 0, \ -+ .max_power = 30, \ -+} -+#endif -+#define aml_legacy_rates_size 12 -+#define aml_g_htcap IEEE80211_HT_CAP_SGI_20 -+#define aml_a_htcap (IEEE80211_HT_CAP_SUP_WIDTH_20_40 | \ -+ IEEE80211_HT_CAP_SGI_20 | \ -+ IEEE80211_HT_CAP_SGI_40) -+ -+void aml_minstrel_attach( void); -+void aml_minstrel_detach(void); -+ -+void aml_minstrel_init( -+#ifdef AUTO_RATE_SIM -+ void -+#else -+ void *p_sta -+#endif -+); -+void aml_minstrel_deinit(void *p_sta); -+ -+unsigned char minstrel_find_rate( -+ struct aml_ratecontrol ratectrl[] -+#ifndef AUTO_RATE_SIM -+, -+ void *p_sta -+#endif -+); -+void minstrel_tx_complete( -+ struct aml_ratecontrol *rc -+#ifndef AUTO_RATE_SIM -+, -+ void *p_sta -+#endif -+); -+ -+#endif ++#ifndef RC80211_MINSTREL_INIT_H ++#define RC80211_MINSTREL_INIT_H ++ ++#include "linux/types.h" ++ ++struct aml_rate_adaptation_dev { ++ struct ieee80211_supported_band *sband; ++ struct cfg80211_chan_def *chandef; ++ struct minstrel_priv *p_minstrel_priv; ++ u32 ht_cap_info; ++ u32 vht_cap_info; ++ u32 num_rf_chains; ++}; ++ ++/* HT Capabilities*/ ++#define WMI_HT_CAP_RX_STBC_MASK_SHIFT 4 ++#define WMI_HT_CAP_ENABLED 0x0001 /* HT Enabled/ disabled */ ++#define WMI_HT_CAP_TX_STBC 0x0002 /* B1 TX STBC */ ++#define WMI_HT_CAP_DYNAMIC_SMPS 0x0004 /* Dynamic MIMO powersave */ ++#define WMI_HT_CAP_HT20_SGI 0x0020 /* Short Guard Interval with HT20 */ ++#define WMI_HT_CAP_HT40_SGI 0x0040 ++#define WMI_HT_CAP_L_SIG_TXOP_PROT 0x0080 /* L-SIG TXOP Protection */ ++#define WMI_HT_CAP_LDPC 0x0200 /* LDPC supported */ ++#define WMI_HT_CAP_RX_STBC 0x0C00 /* B10-B11 RX STBC */ ++#define WMI_HT_CAP_MPDU_DENSITY 0x7000 /* MPDU Density */ ++ ++/* ++ * WMI_VHT_CAP_* these maps to ieee 802.11ac vht capability information ++ * field. The fields not defined here are not supported, or reserved. ++ * Do not change these masks and if you have to add new one follow the ++ * bitmask as specified by 802.11ac draft. ++ */ ++ ++#define WMI_VHT_CAP_MAX_MPDU_LEN_MASK 0x00000003 ++#define WMI_VHT_CAP_RX_LDPC 0x00000010 ++#define WMI_VHT_CAP_SGI_80MHZ 0x00000020 ++#define WMI_VHT_CAP_TX_STBC 0x00000080 ++#define WMI_VHT_CAP_RX_STBC_MASK 0x00000300 ++#define WMI_VHT_CAP_MAX_AMPDU_LEN_EXP 0x03800000 ++#define WMI_VHT_CAP_RX_FIXED_ANT 0x10000000 ++#define WMI_VHT_CAP_TX_FIXED_ANT 0x20000000 ++ ++/* The following also refer for max HT AMSDU */ ++#define WMI_VHT_CAP_MAX_MPDU_LEN_11454 0x00000002 ++ ++/* ++ * Interested readers refer to Rx/Tx MCS Map definition as defined in ++ * 802.11ac ++ */ ++#define WMI_VHT_MAX_SUPP_RATE_MASK 0x1fff0000 ++ ++#ifdef AUTO_RATE_SIM ++#define RATETAB_ENT(_rate, _rateid, _flags) { \ ++ .bitrate = (_rate), \ ++ .flags = (_flags), \ ++ .hw_value = (_rateid), \ ++} ++ ++#define CHAN2G(_channel, _freq, _flags) { \ ++ .band = IEEE80211_BAND_2GHZ, \ ++ .hw_value = (_channel), \ ++ .center_freq = (_freq), \ ++ .flags = (_flags), \ ++ .max_antenna_gain = 0, \ ++ .max_power = 30, \ ++} ++ ++#define CHAN5G(_channel, _flags) { \ ++ .band = IEEE80211_BAND_5GHZ, \ ++ .hw_value = (_channel), \ ++ .center_freq = 5000 + (5 * (_channel)), \ ++ .flags = (_flags), \ ++ .max_antenna_gain = 0, \ ++ .max_power = 30, \ ++} ++#endif ++#define aml_legacy_rates_size 12 ++#define aml_g_htcap IEEE80211_HT_CAP_SGI_20 ++#define aml_a_htcap (IEEE80211_HT_CAP_SUP_WIDTH_20_40 | \ ++ IEEE80211_HT_CAP_SGI_20 | \ ++ IEEE80211_HT_CAP_SGI_40) ++ ++void aml_minstrel_attach( void); ++void aml_minstrel_detach(void); ++ ++void aml_minstrel_init( ++#ifdef AUTO_RATE_SIM ++ void ++#else ++ void *p_sta ++#endif ++); ++void aml_minstrel_deinit(void *p_sta); ++ ++unsigned char minstrel_find_rate( ++ struct aml_ratecontrol ratectrl[] ++#ifndef AUTO_RATE_SIM ++, ++ void *p_sta ++#endif ++); ++void minstrel_tx_complete( ++ struct aml_ratecontrol *rc ++#ifndef AUTO_RATE_SIM ++, ++ void *p_sta ++#endif ++); ++ ++#endif diff --git a/drivers/net/wireless/w1/vmac/version.h b/drivers/net/wireless/w1/vmac/version.h new file mode 100644 -index 000000000000..ced321c6be85 +index 0000000000000000000000000000000000000000..9d06679fe8f2afdece5bb07f89a3b5f318cee99a --- /dev/null +++ b/drivers/net/wireless/w1/vmac/version.h @@ -0,0 +1 @@ -+#define DRIVERVERSION "v1.6.3_20240426-w1-br driver:ea3eb3c912b3467c59ff+419228+423143+406532" ++#define DRIVERVERSION "v1.8.3.3_20260310-w1 driver:888ce88b817c15e731df70f+612585+643887+589776" diff --git a/drivers/net/wireless/w1/vmac/w1_sdio/w1_sdio.c b/drivers/net/wireless/w1/vmac/w1_sdio/w1_sdio.c new file mode 100644 -index 000000000000..3f94d08f02ac +index 0000000000000000000000000000000000000000..283b3057de1cd7ec3cec6e848d7097ed610e3c76 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/w1_sdio/w1_sdio.c -@@ -0,0 +1,1412 @@ +@@ -0,0 +1,1435 @@ +#include "w1_sdio.h" +#include + @@ -37346,6 +37167,9 @@ index 000000000000..3f94d08f02ac +/* protect cmd53 and host sleep request */ +static DEFINE_MUTEX(wifi_sdio_power_mutex); + ++#define SDIO_DMA_BUF_SIZE PAGE_SIZE ++static void *sdio_dma_buf[SDIO_MAX_FUNCS]; ++ +void aml_wifi_sdio_power_lock(void) +{ + mutex_lock(&wifi_sdio_power_mutex); @@ -37361,13 +37185,13 @@ index 000000000000..3f94d08f02ac +int (*host_resume_req)(struct device *device); + + -+struct sdio_func *aml_priv_to_func(int func_n) ++static struct sdio_func *aml_priv_to_func(int func_n) +{ + ASSERT(func_n >= 0 && func_n < SDIO_FUNCNUM_MAX); + return g_w1_hwif_sdio.sdio_func_if[func_n]; +} + -+unsigned int aml_w1_bt_hi_read_word(unsigned int addr) ++static unsigned int aml_w1_bt_hi_read_word(unsigned int addr) +{ + unsigned int regdata = 0; + unsigned int reg_tmp; @@ -37394,7 +37218,7 @@ index 000000000000..3f94d08f02ac + return regdata; +} + -+void aml_w1_bt_hi_write_word(unsigned int addr,unsigned int data) ++static void aml_w1_bt_hi_write_word(unsigned int addr,unsigned int data) +{ + unsigned int reg_tmp; + /* @@ -37417,26 +37241,26 @@ index 000000000000..3f94d08f02ac + (unsigned char*)(SYS_TYPE)(addr & 0x1ffff), sizeof(unsigned int)); +} + -+void aml_w1_bt_sdio_read_sram (unsigned char *buf, unsigned char *addr, SYS_TYPE len) ++static void aml_w1_bt_sdio_read_sram (unsigned char *buf, unsigned char *addr, SYS_TYPE len) +{ + g_w1_hif_ops.hi_bottom_read(SDIO_FUNC5, ((SYS_TYPE)addr & SDIO_ADDR_MASK), + buf, len, (len > 8 ? SDIO_OPMODE_INCREMENT : SDIO_OPMODE_FIXED)); +} + +/*For BT use only start */ -+void aml_w1_bt_sdio_write_sram (unsigned char *buf, unsigned char *addr, SYS_TYPE len) ++static void aml_w1_bt_sdio_write_sram (unsigned char *buf, unsigned char *addr, SYS_TYPE len) +{ + g_w1_hif_ops.hi_bottom_write(SDIO_FUNC5, ((SYS_TYPE)addr & SDIO_ADDR_MASK), + buf, len, (len > 8 ? SDIO_OPMODE_INCREMENT : SDIO_OPMODE_FIXED)); +} + -+int aml_w1_sdio_write_reg32(unsigned long sram_addr, unsigned long sramdata) ++static int aml_w1_sdio_write_reg32(unsigned long sram_addr, unsigned long sramdata) +{ + return g_w1_hif_ops.hi_bottom_write(SDIO_FUNC1, sram_addr&SDIO_ADDR_MASK, + (unsigned char *)&sramdata, sizeof(unsigned long), SDIO_OPMODE_INCREMENT); +} + -+unsigned int aml_w1_aon_read_reg(unsigned int addr) ++static unsigned int aml_w1_aon_read_reg(unsigned int addr) +{ + unsigned int regdata = 0; + @@ -37445,7 +37269,7 @@ index 000000000000..3f94d08f02ac +} + +/* aon module address from 0x00f00000, we need read/write by sdio func5 */ -+void aml_w1_aon_write_reg(unsigned int addr,unsigned int data) ++static void aml_w1_aon_write_reg(unsigned int addr,unsigned int data) +{ + g_w1_hif_ops.bt_hi_write_word((addr), data); +} @@ -37468,16 +37292,11 @@ index 000000000000..3f94d08f02ac + ASSERT(func->num == func_num); + + AML_W1_BT_WIFI_MUTEX_ON(); -+ kmalloc_buf = (unsigned char *)kzalloc(len, GFP_DMA | GFP_ATOMIC);//virt_to_phys(fwICCM); -+ if (kmalloc_buf == NULL) { -+ ERROR_DEBUG_OUT("kmalloc buf fail\n"); -+ AML_W1_BT_WIFI_MUTEX_OFF(); -+ return SDIOH_API_RC_FAIL; -+ } -+ memcpy(kmalloc_buf, byte, len); + + /* Claim host controller */ + sdio_claim_host(func); ++ kmalloc_buf = sdio_dma_buf[func_num]; ++ memcpy(kmalloc_buf, byte, len); + + if (write) { + /* CMD52 Write */ @@ -37494,15 +37313,34 @@ index 000000000000..3f94d08f02ac +#if defined(DBG_PRINT_COST_TIME) + getnstimeofday(&now); + -+ printk("[sdio byte]: len=1 cost=%lds %luus\n", ++ pr_debug("[sdio byte]: len=1 cost=%lds %luus\n", + now.tv_sec-before.tv_sec, now.tv_nsec/1000 - before.tv_nsec/1000); +#endif /* End of DBG_PRINT_COST_TIME */ + -+ kfree(kmalloc_buf); + AML_W1_BT_WIFI_MUTEX_OFF(); + return (err_ret == 0) ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL; +} + ++static size_t aml_w1_sdio_align_size(struct sdio_func *func, unsigned int nbytes, ++ unsigned char write, unsigned int fix_incr) ++{ ++ bool fifo = (fix_incr == SDIO_OPMODE_FIXED); ++ ++ if (write && !fifo) { ++ /* write, increment */ ++ return sdio_align_size(func, nbytes); ++ } else if (write) { ++ /* write, fifo */ ++ return nbytes; ++ } else if (fifo) { ++ /* read */ ++ return nbytes; ++ } else { ++ /* read */ ++ return sdio_align_size(func, nbytes); ++ } ++} ++ +static int _aml_w1_sdio_request_buffer(unsigned char func_num, + unsigned int fix_incr, unsigned char write, unsigned int addr, void *buf, unsigned int nbytes) +{ @@ -37516,9 +37354,6 @@ index 000000000000..3f94d08f02ac + ASSERT(fix_incr == SDIO_OPMODE_FIXED|| fix_incr == SDIO_OPMODE_INCREMENT); + ASSERT(func->num == func_num); + -+ /* Claim host controller */ -+ sdio_claim_host(func); -+ + if (write && !fifo) + { + /* write, increment */ @@ -37542,20 +37377,18 @@ index 000000000000..3f94d08f02ac + err_ret = sdio_memcpy_fromio(func, buf, addr, align_nbytes); + } + -+ /* Release host controller */ -+ sdio_release_host(func); -+ + return (err_ret == 0) ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL; +} + +unsigned char aml_w1_sdio_bottom_read8(unsigned char func_num, int addr); + +//cmd53 -+int aml_w1_sdio_bottom_read(unsigned char func_num, int addr, void *buf, size_t len, int incr_addr) ++static int aml_w1_sdio_bottom_read(unsigned char func_num, int addr, void *buf, size_t len, int incr_addr) +{ + void *kmalloc_buf = NULL; + int result; -+ int align_len = 0; ++ struct sdio_func * func = aml_priv_to_func(func_num); ++ bool need_free_buf = false; + + ASSERT(func_num != SDIO_FUNC0); + @@ -37593,12 +37426,17 @@ index 000000000000..3f94d08f02ac + { + unsigned char fw_st = aml_w1_sdio_bottom_read8(SDIO_FUNC1, 0x23c) & 0xF; + if (fw_st != 6) -+ printk("%s:%d, BUG! fw_st %x, func_num %x, addr %x \n", __func__, __LINE__, fw_st, func_num, addr); ++ pr_err("%s:%d, BUG! fw_st %x, func_num %x, addr %x \n", __func__, __LINE__, fw_st, func_num, addr); + } + AML_W1_BT_WIFI_MUTEX_ON(); ++ ++ sdio_claim_host(func); ++ + /* read block mode */ + if (func_num != SDIO_FUNC6) + { ++ int align_len; ++ + if (incr_addr == SDIO_OPMODE_INCREMENT) + { + struct sdio_func * func = aml_priv_to_func(func_num); @@ -37607,7 +37445,12 @@ index 000000000000..3f94d08f02ac + else + align_len = len; + -+ kmalloc_buf = (unsigned char *)kzalloc(align_len, GFP_DMA|GFP_ATOMIC); ++ if (align_len > SDIO_DMA_BUF_SIZE) { ++ need_free_buf = true; ++ kmalloc_buf = kzalloc(align_len, GFP_DMA); ++ } else { ++ kmalloc_buf = sdio_dma_buf[func_num]; ++ } + } + else + { @@ -37617,6 +37460,9 @@ index 000000000000..3f94d08f02ac + if (kmalloc_buf == NULL) + { + ERROR_DEBUG_OUT("kmalloc buf fail\n"); ++ ++ sdio_release_host(func); ++ + AML_W1_BT_WIFI_MUTEX_OFF(); + aml_wifi_sdio_power_unlock(); + return SDIOH_API_RC_FAIL; @@ -37627,9 +37473,12 @@ index 000000000000..3f94d08f02ac + if (func_num != SDIO_FUNC6) + { + memcpy(buf, kmalloc_buf, len); -+ kfree(kmalloc_buf); ++ if (need_free_buf) ++ kfree(kmalloc_buf); + } + ++ sdio_release_host(func); ++ + AML_W1_BT_WIFI_MUTEX_OFF(); + aml_wifi_sdio_power_unlock(); + return result; @@ -37637,10 +37486,12 @@ index 000000000000..3f94d08f02ac + + +//cmd53 -+int aml_w1_sdio_bottom_write(unsigned char func_num, int addr, void *buf, size_t len, int incr_addr) ++static int aml_w1_sdio_bottom_write(unsigned char func_num, int addr, void *buf, size_t len, int incr_addr) +{ + void *kmalloc_buf; + int result; ++ struct sdio_func * func = aml_priv_to_func(func_num); ++ size_t sdio_aligned_len; + + if (!wifi_sdio_access) { + if (func_num == SDIO_FUNC5) { @@ -37677,40 +37528,52 @@ index 000000000000..3f94d08f02ac + { + unsigned char fw_st = aml_w1_sdio_bottom_read8(SDIO_FUNC1, 0x23c) & 0xF; + if (fw_st != 6) -+ printk("%s:%d, BUG! fw_st %x, func_num %x, addr %x \n", __func__, __LINE__, fw_st, func_num, addr); ++ pr_err("%s:%d, BUG! fw_st %x, func_num %x, addr %x \n", __func__, __LINE__, fw_st, func_num, addr); + } + + AML_W1_BT_WIFI_MUTEX_ON(); -+ kmalloc_buf = (unsigned char *)kzalloc(len, GFP_DMA | GFP_ATOMIC);//virt_to_phys(fwICCM); -+ if (kmalloc_buf == NULL) { -+ ERROR_DEBUG_OUT("kmalloc buf fail\n"); -+ AML_W1_BT_WIFI_MUTEX_OFF(); -+ aml_wifi_sdio_power_unlock(); -+ return SDIOH_API_RC_FAIL; ++ sdio_claim_host(func); ++ ++ sdio_aligned_len = aml_w1_sdio_align_size(func, len, SDIO_WRITE, incr_addr); ++ ++ if (sdio_aligned_len > SDIO_DMA_BUF_SIZE) { ++ kmalloc_buf = kzalloc(sdio_aligned_len, GFP_DMA); ++ if (!kmalloc_buf) { ++ ERROR_DEBUG_OUT("kmalloc buf fail\n"); ++ sdio_release_host(func); ++ AML_W1_BT_WIFI_MUTEX_OFF(); ++ aml_wifi_sdio_power_unlock(); ++ return SDIOH_API_RC_FAIL; ++ } ++ } else { ++ kmalloc_buf = sdio_dma_buf[func_num]; + } + memcpy(kmalloc_buf, buf, len); + + result = _aml_w1_sdio_request_buffer(func_num, incr_addr, SDIO_WRITE, addr, kmalloc_buf, len); ++ if (sdio_aligned_len > SDIO_DMA_BUF_SIZE) ++ kfree(kmalloc_buf); ++ ++ sdio_release_host(func); + -+ kfree(kmalloc_buf); + AML_W1_BT_WIFI_MUTEX_OFF(); + aml_wifi_sdio_power_unlock(); + return result; +} + -+void aml_w1_sdio_read_sram (unsigned char *buf, unsigned char *addr, SYS_TYPE len) ++static void aml_w1_sdio_read_sram (unsigned char *buf, unsigned char *addr, SYS_TYPE len) +{ + g_w1_hif_ops.hi_bottom_read(SDIO_FUNC2, (SYS_TYPE)addr&SDIO_ADDR_MASK, + buf, len, (len > 8 ? SDIO_OPMODE_INCREMENT : SDIO_OPMODE_FIXED)); +} + -+void aml_w1_sdio_write_sram (unsigned char *buf, unsigned char *addr, SYS_TYPE len) ++static void aml_w1_sdio_write_sram (unsigned char *buf, unsigned char *addr, SYS_TYPE len) +{ + g_w1_hif_ops.hi_bottom_write(SDIO_FUNC2, (SYS_TYPE)addr&SDIO_ADDR_MASK, + buf, len, (len > 8 ? SDIO_OPMODE_INCREMENT : SDIO_OPMODE_FIXED)); +} + -+unsigned int aml_w1_sdio_read_word(unsigned int addr) ++static unsigned int aml_w1_sdio_read_word(unsigned int addr) +{ + unsigned int regdata = 0; + @@ -37738,7 +37601,7 @@ index 000000000000..3f94d08f02ac + return regdata; +} + -+void aml_w1_sdio_write_word(unsigned int addr, unsigned int data) ++static void aml_w1_sdio_write_word(unsigned int addr, unsigned int data) +{ + // for bt access always on reg + if ((addr & 0x00f00000) == 0x00f00000) { @@ -37764,7 +37627,7 @@ index 000000000000..3f94d08f02ac +} + +//cmd52 -+int aml_w1_sdio_bottom_write8(unsigned char func_num, int addr, unsigned char data) ++static int aml_w1_sdio_bottom_write8(unsigned char func_num, int addr, unsigned char data) +{ + int ret = 0; + @@ -37788,13 +37651,13 @@ index 000000000000..3f94d08f02ac + buff[25:8], // regAddr + buff[39:32]); // regValue +*/ -+void aml_w1_sdio_bottom_write8_func0(unsigned long sram_addr, unsigned char sramdata) ++static void aml_w1_sdio_bottom_write8_func0(unsigned long sram_addr, unsigned char sramdata) +{ + _aml_w1_sdio_request_byte(SDIO_FUNC0, SDIO_WRITE, sram_addr, &sramdata); +} + +//cmd52 -+unsigned char aml_w1_sdio_bottom_read8_func0(unsigned long sram_addr) ++static unsigned char aml_w1_sdio_bottom_read8_func0(unsigned long sram_addr) +{ + unsigned char sramdata; + @@ -37802,7 +37665,7 @@ index 000000000000..3f94d08f02ac + return sramdata; +} + -+void aml_w1_sdio_write_cmd32(unsigned long sram_addr, unsigned long sramdata) ++static void aml_w1_sdio_write_cmd32(unsigned long sram_addr, unsigned long sramdata) +{ +#if defined (HAL_SIM_VER) + aml_sdio_read_write(sram_addr&SDIO_ADDR_MASK, (unsigned char *)&sramdata, 4, @@ -37813,7 +37676,7 @@ index 000000000000..3f94d08f02ac +#endif /* End of HAL_SIM_VER */ +} + -+int aml_w1_sdio_suspend(unsigned int suspend_enable) ++static int aml_w1_sdio_suspend(unsigned int suspend_enable) +{ + mmc_pm_flag_t flags; + struct sdio_func *func = NULL; @@ -37864,7 +37727,7 @@ index 000000000000..3f94d08f02ac + return ret; +} + -+unsigned long aml_w1_sdio_read_reg8(unsigned long sram_addr ) ++static unsigned long aml_w1_sdio_read_reg8(unsigned long sram_addr ) +{ + unsigned char regdata[8] = {0}; + @@ -37872,13 +37735,13 @@ index 000000000000..3f94d08f02ac + return regdata[0]; +} + -+void aml_w1_sdio_write_reg8(unsigned long sram_addr, unsigned long sramdata) ++static void aml_w1_sdio_write_reg8(unsigned long sram_addr, unsigned long sramdata) +{ + g_w1_hif_ops.hi_bottom_write(SDIO_FUNC1, sram_addr&SDIO_ADDR_MASK, + (unsigned char *)&sramdata, sizeof(unsigned long), SDIO_OPMODE_INCREMENT); +} + -+unsigned long aml_w1_sdio_read_reg32(unsigned long sram_addr) ++static unsigned long aml_w1_sdio_read_reg32(unsigned long sram_addr) +{ + unsigned long sramdata; + @@ -37886,7 +37749,7 @@ index 000000000000..3f94d08f02ac + return sramdata; +} + -+struct amlw_hif_scatter_req *aml_w1_sdio_scatter_req_get(void) ++static struct amlw_hif_scatter_req *aml_w1_sdio_scatter_req_get(void) +{ + struct amlw1_hwif_sdio *hif_sdio = &g_w1_hwif_sdio; + @@ -37928,7 +37791,7 @@ index 000000000000..3f94d08f02ac + return 0; +} + -+int aml_w1_sdio_enable_scatter(void) ++static int aml_w1_sdio_enable_scatter(void) +{ + struct amlw1_hwif_sdio *hif_sdio = &g_w1_hwif_sdio; + int ret; @@ -37946,7 +37809,7 @@ index 000000000000..3f94d08f02ac + return ret; +} + -+int aml_w1_sdio_scat_rw(struct scatterlist *sg_list, unsigned int sg_num, unsigned int blkcnt, ++static int aml_w1_sdio_scat_rw(struct scatterlist *sg_list, unsigned int sg_num, unsigned int blkcnt, + unsigned char func_num, unsigned int addr, unsigned char write) +{ + struct mmc_request mmc_req; @@ -37984,7 +37847,7 @@ index 000000000000..3f94d08f02ac + sdio_release_host(func); + + if (mmc_cmd.error || mmc_dat.error) { -+ printk("ERROR CMD53 %s cmd_error = %d data_error=%d\n", ++ pr_err("ERROR CMD53 %s cmd_error = %d data_error=%d\n", + write ? "write" : "read", mmc_cmd.error, mmc_dat.error); + ret = mmc_cmd.error; + } @@ -37993,7 +37856,7 @@ index 000000000000..3f94d08f02ac + return ret; +} + -+void aml_w1_sdio_scat_complete (struct amlw_hif_scatter_req * scat_req) ++static void aml_w1_sdio_scat_complete (struct amlw_hif_scatter_req * scat_req) +{ + int i; + struct amlw1_hwif_sdio *hif_sdio = &g_w1_hwif_sdio; @@ -38021,10 +37884,10 @@ index 000000000000..3f94d08f02ac + memset(scat_req->sgentries, 0, SDIO_MAX_SG_ENTRIES * sizeof(struct scatterlist)); +} + -+void aml_w1_sdio_cleanup_scatter(void) ++static void aml_w1_sdio_cleanup_scatter(void) +{ + struct amlw1_hwif_sdio *hif_sdio = &g_w1_hwif_sdio; -+ printk("[sdio sg cleanup]: enter\n"); ++ pr_debug("[sdio sg cleanup]: enter\n"); + + ASSERT(hif_sdio != NULL); + @@ -38035,18 +37898,18 @@ index 000000000000..3f94d08f02ac + + /* empty the free list */ + kfree(hif_sdio->scat_req); -+ printk("[sdio sg cleanup]: exit\n"); ++ pr_debug("[sdio sg cleanup]: exit\n"); + + return; +} + -+void aml_w1_sdio_recv_frame (unsigned char *buf, unsigned char *addr, SYS_TYPE len) ++static void aml_w1_sdio_recv_frame (unsigned char *buf, unsigned char *addr, SYS_TYPE len) +{ + g_w1_hif_ops.hi_bottom_read(SDIO_FUNC6, ((SYS_TYPE)addr & SDIO_ADDR_MASK), + buf, len, SDIO_OPMODE_INCREMENT); +} + -+void aml_w1_sdio_init_ops(void) ++static void aml_w1_sdio_init_ops(void) +{ + struct amlw1_hif_ops* ops = &g_w1_hif_ops; + @@ -38089,7 +37952,7 @@ index 000000000000..3f94d08f02ac + host_suspend_req = NULL; +} + -+int aml_w1_sdio_probe(struct sdio_func *func, const struct sdio_device_id *id) ++static int aml_w1_sdio_probe(struct sdio_func *func, const struct sdio_device_id *id) +{ + int ret = 0; + static struct sdio_func sdio_func_0; @@ -38101,7 +37964,7 @@ index 000000000000..3f94d08f02ac + + sdio_set_block_size(func, 512); + -+ printk("%s(%d): func->num %d sdio block size=%d, \n", __func__, __LINE__, ++ pr_debug("%s(%d): func->num %d sdio block size=%d, \n", __func__, __LINE__, + func->num, func->cur_blksize); + + if (func->num == 1) @@ -38111,14 +37974,14 @@ index 000000000000..3f94d08f02ac + g_w1_hwif_sdio.sdio_func_if[0] = &sdio_func_0; + } + g_w1_hwif_sdio.sdio_func_if[func->num] = func; -+ printk("%s(%d): func->num %d sdio_func=%p, \n", __func__, __LINE__, ++ pr_debug("%s(%d): func->num %d sdio_func=%p, \n", __func__, __LINE__, + func->num, func); + + sdio_release_host(func); + sdio_set_drvdata(func, (void *)(&g_w1_hwif_sdio)); + if (func->num != FUNCNUM_SDIO_LAST) + { -+ printk("%s(%d):func_num=%d, last func num=%d\n", __func__, __LINE__, ++ pr_debug("%s(%d):func_num=%d, last func num=%d\n", __func__, __LINE__, + func->num, FUNCNUM_SDIO_LAST); + return 0; + } @@ -38128,7 +37991,7 @@ index 000000000000..3f94d08f02ac + return ret; + +sdio_enable_error: -+ printk("sdio_enable_error: line %d\n",__LINE__); ++ pr_err("sdio_enable_error: line %d\n",__LINE__); + sdio_release_host(func); + + return ret; @@ -38141,9 +38004,9 @@ index 000000000000..3f94d08f02ac + return ; + } + -+ printk("\n==========================================\n"); -+ printk("aml_sdio_remove++ func->num =%d \n",func->num); -+ printk("==========================================\n"); ++ pr_debug("\n==========================================\n"); ++ pr_debug("aml_sdio_remove++ func->num =%d \n",func->num); ++ pr_debug("==========================================\n"); + + sdio_claim_host(func); + sdio_disable_func(func); @@ -38171,7 +38034,7 @@ index 000000000000..3f94d08f02ac +} + + -+void write_byte_8ba(unsigned char Bus, unsigned char SlaveAddr, ++static void write_byte_8ba(unsigned char Bus, unsigned char SlaveAddr, + unsigned char RegAddr, unsigned char Data) +{ + unsigned int tmp,cnt = 0; @@ -38206,14 +38069,14 @@ index 000000000000..3f94d08f02ac + + cnt++; + if (cnt == 1000) { -+ printk("-------[ERR]-----> i2c[W] err\n"); ++ pr_err("-------[ERR]-----> i2c[W] err\n"); + break; + } + } while (tmp & (1 << 2)); + +} + -+unsigned char read_byte_8ba(unsigned char Bus, unsigned char SlaveAddr, unsigned char RegAddr) ++static unsigned char read_byte_8ba(unsigned char Bus, unsigned char SlaveAddr, unsigned char RegAddr) +{ + //struct hw_interface* hif = hif_get_hw_interface(); + unsigned int tmp,cnt = 0; @@ -38250,7 +38113,7 @@ index 000000000000..3f94d08f02ac + + cnt++; + if (cnt == 1000) { -+ printk("-------[ERR]-----> i2c[W] err\n"); ++ pr_err("-------[ERR]-----> i2c[W] err\n"); + break; + } + } while (tmp & (1 << 2)); @@ -38261,13 +38124,13 @@ index 000000000000..3f94d08f02ac + + +//void write_rdaddr_32ba(U8 Bus, U8 SlaveAddr, U32 TkData0, U32 TkData1) -+void write_word_32ba(unsigned char Bus, unsigned char SlaveAddr, ++static void write_word_32ba(unsigned char Bus, unsigned char SlaveAddr, + unsigned int StartToken, unsigned int Data) +{ + //struct hw_interface* hif = hif_get_hw_interface(); + unsigned int tmp,cnt = 0; + -+ //printk("%s(%d) token 0x%x data 0x%x\n", __func__, __LINE__, StartToken,Data); ++ //pr_debug("%s(%d) token 0x%x data 0x%x\n", __func__, __LINE__, StartToken,Data); + + // Set the I2C bus to 100khz + tmp = aml_w1_sdio_read_word(I2C_CONTROL_REG); @@ -38310,7 +38173,7 @@ index 000000000000..3f94d08f02ac + } while (tmp & (1 << 2)); +} + -+unsigned int read_word_32ba(unsigned int SlaveAddr, unsigned int RegAddr) ++static unsigned int read_word_32ba(unsigned int SlaveAddr, unsigned int RegAddr) +{ + //struct hw_interface* hif = hif_get_hw_interface(); + unsigned int tmp,cnt = 0; @@ -38399,21 +38262,11 @@ index 000000000000..3f94d08f02ac + write_byte_8ba(bus, slave_addr, 0x8, bus); +} + -+void config_pmu_reg_off(void) ++static void config_pmu_reg_off(void) +{ -+ int value_pmu_A12 = 0; -+ int value_pmu_A15 = 0; -+ int value_pmu_A17 = 0; -+ int value_pmu_A18 = 0; -+ int value_pmu_A20 = 0; -+ int value_pmu_A22 = 0; -+ int value_pmu_A24 = 0; -+ int value_aon30 = 0; -+ + RG_AON_A30_FIELD_T reg_aon30_data; + RG_AON_A29_FIELD_T reg_aon29_data; + -+ unsigned char host_req_status= 0; + unsigned int reg_val = 0; + + //reg_val = rf_read_register(RG_TOP_A2); @@ -38440,15 +38293,17 @@ index 000000000000..3f94d08f02ac + aml_w1_sdio_write_word(RG_COEX_WF_OWNER_CTRL, reg_val); + + { -+ value_pmu_A12 = aml_w1_sdio_read_word(RG_PMU_A12); -+ value_pmu_A15 = aml_w1_sdio_read_word(RG_PMU_A15); -+ value_pmu_A17 = aml_w1_sdio_read_word(RG_PMU_A17); -+ value_pmu_A18 = aml_w1_sdio_read_word(RG_PMU_A18); -+ value_pmu_A20 = aml_w1_sdio_read_word(RG_PMU_A20); -+ value_pmu_A22 = aml_w1_sdio_read_word(RG_PMU_A22); -+ value_pmu_A24 = aml_w1_sdio_read_word(RG_PMU_A24); -+ value_aon30 = aml_w1_sdio_read_word(RG_AON_A30); -+ printk("%s power off: before write A12=0x%x, A15=0x%x, A17=0x%x, A18=0x%x, A20=0x%x, A22=0x%x, A24=0x%x, AON30=0x%x\n", ++ int value_pmu_A12 = aml_w1_sdio_read_word(RG_PMU_A12); ++ int value_pmu_A15 = aml_w1_sdio_read_word(RG_PMU_A15); ++ int value_pmu_A17 = aml_w1_sdio_read_word(RG_PMU_A17); ++ int value_pmu_A18 = aml_w1_sdio_read_word(RG_PMU_A18); ++ int value_pmu_A20 = aml_w1_sdio_read_word(RG_PMU_A20); ++ int value_pmu_A22 = aml_w1_sdio_read_word(RG_PMU_A22); ++ int value_pmu_A24 = aml_w1_sdio_read_word(RG_PMU_A24); ++ int value_aon30 = aml_w1_sdio_read_word(RG_AON_A30); ++ unsigned char host_req_status; ++ ++ pr_debug("%s power off: before write A12=0x%x, A15=0x%x, A17=0x%x, A18=0x%x, A20=0x%x, A22=0x%x, A24=0x%x, AON30=0x%x\n", + __func__, value_pmu_A12,value_pmu_A15,value_pmu_A17,value_pmu_A18,value_pmu_A20,value_pmu_A22,value_pmu_A24, value_aon30); + + aml_w1_sdio_write_word(RG_INTF_CPU_CLK, 0x4f070001); @@ -38479,7 +38334,7 @@ index 000000000000..3f94d08f02ac + value_pmu_A22 = aml_w1_sdio_read_word(RG_PMU_A22); + value_pmu_A24 = aml_w1_sdio_read_word(RG_PMU_A24); + value_aon30 = aml_w1_sdio_read_word(RG_AON_A30); -+ printk("%s power off: after write A12=0x%x, A15=0x%x, A17=0x%x, A18=0x%x, A20=0x%x, A22=0x%x, A24=0x%x, AON30=0x%x\n", ++ pr_debug("%s power off: after write A12=0x%x, A15=0x%x, A17=0x%x, A18=0x%x, A20=0x%x, A22=0x%x, A24=0x%x, AON30=0x%x\n", + __func__, value_pmu_A12,value_pmu_A15,value_pmu_A17,value_pmu_A18,value_pmu_A20,value_pmu_A22,value_pmu_A24, value_aon30); + + //force wifi pmu fsm to sleep mode @@ -38491,7 +38346,7 @@ index 000000000000..3f94d08f02ac +extern int wifi_irq_num(void); +static void aml_sdio_shutdown(struct device *device) +{ -+ printk("===>>> enter %s <<<===\n", __func__); ++ pr_debug("===>>> enter %s <<<===\n", __func__); + if (wifi_irq_enable == 1) { +#if (USE_SDIO_IRQ==1) + struct sdio_func *func = g_w1_hwif_sdio.sdio_func_if[SDIO_FUNC1]; @@ -38511,11 +38366,11 @@ index 000000000000..3f94d08f02ac + } + } else if (shutdown_i == 7) { + shutdown_i = 0; -+ printk("===>>> end <<<===\n"); ++ pr_debug("===>>> end <<<===\n"); + } else { + ; + } -+ printk("=== shutdown_i:%d ===\n", shutdown_i); ++ pr_debug("=== shutdown_i:%d ===\n", shutdown_i); +} + + @@ -38540,114 +38395,100 @@ index 000000000000..3f94d08f02ac + .drv.shutdown = aml_sdio_shutdown, +}; + -+#ifdef NOT_AMLOGIC_PLATFORM -+ -+#define AML_STATIC_VERSION_STR "101.10.361.10 (wlan=r892223-20210623-1)" -+ -+#define DHD_SKB_1PAGE_BUFSIZE (PAGE_SIZE * 1) -+#define DHD_SKB_2PAGE_BUFSIZE (PAGE_SIZE * 2) -+#define DHD_SKB_4PAGE_BUFSIZE (PAGE_SIZE * 4) -+ -+#define DHD_SKB_1PAGE_BUF_NUM 8 -+#define DHD_SKB_2PAGE_BUF_NUM 8 -+#define DHD_SKB_4PAGE_BUF_NUM 1 -+ -+#define FW_VERBOSE_RING_SIZE (256 * 1024) -+#define DHD_PREALLOC_MEMDUMP_RAM_SIZE (1290 * 1024) -+#define NAN_EVENT_RING_SIZE (64 * 1024) -+#define WLAN_SKB_1_2PAGE_BUF_NUM ((DHD_SKB_1PAGE_BUF_NUM) + \ -+ (DHD_SKB_2PAGE_BUF_NUM)) -+#define WLAN_SKB_BUF_NUM ((WLAN_SKB_1_2PAGE_BUF_NUM) + (DHD_SKB_4PAGE_BUF_NUM)) ++static void *wlan_preallocated_rx_buf; ++static void *wlan_preallocated_tx_desc_buf; + -+void *wlan_static_dhd_memdump_ram_buf; -+void *wlan_static_nan_event_ring_buf; -+void *wlan_static_fw_verbose_ring_buf; ++/* Two defines below taken from aml_static_buf.c. */ ++#define AML_RX 11 ++#define AML_TX 20 ++/* This is value '(RX_FIFO_SIZE + 2 * FUNC6_BLKSIZE)' ++ * from function 'hi_rx_fifo_init()' in wifi_hif.c. ++ */ ++#define RX_BUF_LEN 459776 + -+enum dhd_prealloc_index { -+ DHD_PREALLOC_SKB_BUF = 4, -+ DHD_PREALLOC_MEMDUMP_RAM = 11, -+ DHD_PREALLOC_FW_VERBOSE_RING = 20, -+ DHD_PREALLOC_NAN_EVENT_RING = 23, -+ DHD_PREALLOC_MAX -+}; ++/* This is value of variable 'bsize' from function ++ * 'wifi_mac_tx_init()' in wifi_mac_if.c. Note, it ++ * depends on size of 'struct drv_txdesc', so we take ++ * biggest size between 32 and 64 bits build. ++ */ ++#define TX_DESC_BUF_LEN 246272 + +void *aml_mem_prealloc(int section, unsigned long size) +{ -+ PRINT("sectoin %d, size %ld\n", section, size); ++ switch (section) { ++ case AML_RX: ++ if (size > RX_BUF_LEN) ++ return NULL; + -+ if (section == DHD_PREALLOC_MEMDUMP_RAM) { -+ if (size > DHD_PREALLOC_MEMDUMP_RAM_SIZE) { -+ PRINT("request MEMDUMP_RAM(%lu) > %d\n", -+ size, DHD_PREALLOC_MEMDUMP_RAM_SIZE); -+ return NULL; -+ } -+ return wlan_static_dhd_memdump_ram_buf; -+ } ++ return wlan_preallocated_rx_buf; ++ case AML_TX: ++ if (size > TX_DESC_BUF_LEN) ++ return NULL; + -+ if (section == DHD_PREALLOC_FW_VERBOSE_RING) { -+ if (size > FW_VERBOSE_RING_SIZE) { -+ PRINT("request FW_VERBOSE_RING(%lu) > %d\n", -+ size, FW_VERBOSE_RING_SIZE); -+ return NULL; -+ } -+ return wlan_static_fw_verbose_ring_buf; ++ return wlan_preallocated_tx_desc_buf; ++ default: ++ return NULL; + } -+ -+ if (section < 0 || section > DHD_PREALLOC_MAX) -+ PRINT("request section id(%d) is out of max %d\n", -+ section, DHD_PREALLOC_MAX); -+ -+ PRINT("failed to alloc section %d, size=%ld\n", -+ section, size); -+ -+ return NULL; +} +EXPORT_SYMBOL(aml_mem_prealloc); + -+int aml_init_wlan_mem(void) ++static int aml_init_wlan_mem(void) +{ -+ unsigned long size = 0; -+ PRINT("%s\n", AML_STATIC_VERSION_STR); -+ -+ wlan_static_dhd_memdump_ram_buf = kmalloc(DHD_PREALLOC_MEMDUMP_RAM_SIZE, GFP_KERNEL); -+ if (!wlan_static_dhd_memdump_ram_buf) -+ goto err_mem_alloc; -+ size += DHD_PREALLOC_MEMDUMP_RAM_SIZE; -+ PRINT("sectoin %d, size=%d\n", -+ DHD_PREALLOC_MEMDUMP_RAM, DHD_PREALLOC_MEMDUMP_RAM_SIZE); -+ -+ wlan_static_fw_verbose_ring_buf = kmalloc(FW_VERBOSE_RING_SIZE, GFP_KERNEL); -+ if (!wlan_static_fw_verbose_ring_buf) -+ goto err_mem_alloc; -+ size += FW_VERBOSE_RING_SIZE; -+ PRINT("sectoin %d, size=%d\n", -+ DHD_PREALLOC_FW_VERBOSE_RING, FW_VERBOSE_RING_SIZE); ++#if defined(LOW_MEMORY_PLATFORM) ++ wlan_preallocated_tx_desc_buf = kmalloc(TX_DESC_BUF_LEN, GFP_KERNEL | __GFP_NOFAIL); ++#else ++ wlan_preallocated_tx_desc_buf = kmalloc(TX_DESC_BUF_LEN, GFP_KERNEL); ++#endif ++ if (!wlan_preallocated_tx_desc_buf) ++ return -ENOMEM; + -+ PRINT("prealloc ok: %ld(%ldK)\n", size, size / 1024); ++#if defined(LOW_MEMORY_PLATFORM) ++ wlan_preallocated_rx_buf = kvmalloc(RX_BUF_LEN, GFP_KERNEL | __GFP_NOFAIL); ++#else ++ wlan_preallocated_rx_buf = kvmalloc(RX_BUF_LEN, GFP_KERNEL); ++#endif ++ if (!wlan_preallocated_rx_buf) { ++ vfree(wlan_preallocated_tx_desc_buf); ++ return -ENOMEM; ++ } + return 0; ++} + -+err_mem_alloc: -+ kfree(wlan_static_dhd_memdump_ram_buf); -+ kfree(wlan_static_fw_verbose_ring_buf); -+ PRINT("Failed to mem_alloc for WLAN\n"); -+ -+ return -ENOMEM; ++static void aml_deinit_wlan_mem(void) ++{ ++ kfree(wlan_preallocated_rx_buf); ++ vfree(wlan_preallocated_tx_desc_buf); +} -+#endif + -+int aml_w1_sdio_init(void) ++int aml_w1_sdio_init(void) +{ + int err = 0; ++ int i; + + //amlwifi_set_sdio_host_clk(200000000);//200MHZ ++ for (i = 0; i < ARRAY_SIZE(sdio_dma_buf); i++) { ++ sdio_dma_buf[i] = kzalloc(SDIO_DMA_BUF_SIZE, GFP_DMA); ++ if (!sdio_dma_buf[i]) { ++ err = -ENOMEM; ++ goto err_out; ++ } ++ } + + err = sdio_register_driver(&aml_w1_sdio_driver); + w1_sdio_driver_insmoded = 1; + wifi_in_insmod = 0; + wifi_in_rmmod = 0; + PRINT("*****************aml sdio common driver is insmoded********************\n"); -+ if (err) ++ if (err) { + PRINT("failed to register sdio driver: %d \n", err); ++ goto err_out; ++ } ++ ++ return 0; ++ ++err_out: ++ for (i = 0; i < ARRAY_SIZE(sdio_dma_buf); i++) ++ kfree(sdio_dma_buf[i]); + + return err; +} @@ -38655,11 +38496,14 @@ index 000000000000..3f94d08f02ac + +void aml_w1_sdio_exit(void) +{ ++ int i = 0; + PRINT("aml_w1_sdio_exit++ \n"); + sdio_unregister_driver(&aml_w1_sdio_driver); + w1_sdio_driver_insmoded = 0; + w1_sdio_after_porbe = 0; + PRINT("*****************aml sdio common driver is rmmoded********************\n"); ++ for (i = 0; i < ARRAY_SIZE(sdio_dma_buf); i++) ++ kfree(sdio_dma_buf[i]); +} +//EXPORT_SYMBOL(aml_w1_sdio_exit); + @@ -38700,22 +38544,22 @@ index 000000000000..3f94d08f02ac + +static int aml_w1_sdio_insmod(void) +{ -+#ifdef NOT_AMLOGIC_PLATFORM + int ret; + ret = aml_init_wlan_mem(); + if (ret) { + PRINT("aml_init_wlan_mem err: %d \n", ret); + return -ENOMEM; + } -+#endif ++ + aml_w1_sdio_init(); -+ printk("%s(%d) start...\n",__func__, __LINE__); ++ pr_debug("%s(%d) start...\n",__func__, __LINE__); + return 0; +} + +static void aml_w1_sdio_rmmod(void) +{ + aml_w1_sdio_exit(); ++ aml_deinit_wlan_mem(); +} + +module_init(aml_w1_sdio_insmod); @@ -38723,10 +38567,10 @@ index 000000000000..3f94d08f02ac +MODULE_LICENSE("GPL"); diff --git a/drivers/net/wireless/w1/vmac/w1_sdio/w1_sdio.h b/drivers/net/wireless/w1/vmac/w1_sdio/w1_sdio.h new file mode 100644 -index 000000000000..a625a427286e +index 0000000000000000000000000000000000000000..248a89e422bf055942e10a8731a6eb315230abd6 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/w1_sdio/w1_sdio.h -@@ -0,0 +1,185 @@ +@@ -0,0 +1,188 @@ +#include +#include +#include @@ -38747,7 +38591,7 @@ index 000000000000..a625a427286e +#include +#include +#include -+#include /* printk() */ ++#include /* pr_debug() */ +#include +#include +#include @@ -38761,18 +38605,18 @@ index 000000000000..a625a427286e +extern void amlwifi_set_sdio_host_clk(int clk); +extern void set_usb_bt_power(int is_on); + -+#define PRINT(...) do {printk("w1_sdio->");printk( __VA_ARGS__ );}while(0) ++#define PRINT(...) do {pr_debug("w1_sdio->");pr_debug( __VA_ARGS__ );}while(0) +#ifndef ASSERT +#define ASSERT(exp) do{ \ + if (!(exp)) { \ -+ printk("=>=>=>=>=>assert %s,%d\n",__func__,__LINE__); \ ++ pr_err("=>=>=>=>=>assert %s,%d\n",__func__,__LINE__); \ + /*BUG(); while(1); */ \ + } \ + } while (0); +#endif + +#define ERROR_DEBUG_OUT(format,...) do { \ -+ printk("FUNCTION: %s LINE: %d:"format"",__FUNCTION__, __LINE__, ##__VA_ARGS__); \ ++ pr_err("FUNCTION: %s LINE: %d:"format"",__FUNCTION__, __LINE__, ##__VA_ARGS__); \ + } while (0) + + @@ -38912,9 +38756,12 @@ index 000000000000..a625a427286e + int (*hif_suspend)(unsigned int suspend_enable); +}; + ++void aml_wifi_sdio_power_lock(void); ++void aml_wifi_sdio_power_unlock(void); ++void *aml_mem_prealloc(int section, unsigned long size); diff --git a/drivers/net/wireless/w1/vmac/wifi_android.c b/drivers/net/wireless/w1/vmac/wifi_android.c new file mode 100644 -index 000000000000..d21047324c2a +index 0000000000000000000000000000000000000000..196f47ebf0808d1d45e051c3bf2ed2c00717b2cf --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_android.c @@ -0,0 +1,491 @@ @@ -38992,14 +38839,14 @@ index 000000000000..d21047324c2a + bytes_written += snprintf(&command[bytes_written], total_len, "%s rssi %d\n", + wnet_vif->vm_mainsta->sta_essid, rssi); + -+ printk("sta_avg_rssi:%d, sta_avg_bcn_rssi:%d\n", ++ pr_debug("sta_avg_rssi:%d, sta_avg_bcn_rssi:%d\n", + (wnet_vif->vm_mainsta->sta_avg_rssi - 255), wnet_vif->vm_mainsta->sta_avg_bcn_rssi); + } + } + + return bytes_written; +} -+unsigned int aml_atoi(unsigned char* s) ++static unsigned int aml_atoi(unsigned char* s) +{ + + int num=0,flag=0; @@ -39073,7 +38920,7 @@ index 000000000000..d21047324c2a +{ + int ret = 0; + -+ printk("%s in\n", __FUNCTION__); ++ pr_debug("%s in\n", __FUNCTION__); + if (!dev) + { + ERROR_DEBUG_OUT("dev is null\n"); @@ -39088,7 +38935,7 @@ index 000000000000..d21047324c2a +{ + int ret = 0; + -+ printk("%s in\n", __FUNCTION__); ++ pr_debug("%s in\n", __FUNCTION__); + if (!dev) + { + ERROR_DEBUG_OUT("dev is null\n"); @@ -39411,94 +39258,94 @@ index 000000000000..d21047324c2a + diff --git a/drivers/net/wireless/w1/vmac/wifi_android.h b/drivers/net/wireless/w1/vmac/wifi_android.h new file mode 100644 -index 000000000000..aba262cb826a +index 0000000000000000000000000000000000000000..ca3e47afeb5c6a2434ea9897a5cb6ffa5ecdd23d --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_android.h @@ -0,0 +1,78 @@ -+/* -+ **************************************************************************************** -+ * -+ * Copyright (C) Amlogic 2010-2014 -+ * -+ * Project: 11N 80211 mac layer Software -+ * -+ * Description: -+ * wifi_mac android interface module -+ * -+ * -+ **************************************************************************************** -+ */ -+#ifndef _IEEE80211_ANDROID_H_ -+#define _IEEE80211_ANDROID_H_ -+ -+struct android_wifi_priv_cmd -+{ -+ char *buf; -+ int used_len; -+ int total_len; -+} ; -+ -+#ifdef CONFIG_COMPAT -+ typedef struct _compat_android_wifi_priv_cmd { -+ compat_caddr_t buf; -+ int used_len; -+ int total_len; -+ } compat_android_wifi_priv_cmd; -+#endif /* CONFIG_COMPAT */ -+ -+enum ANDROID_WIFI_CMD -+{ -+ ANDROID_WIFI_CMD_START = 0, -+ ANDROID_WIFI_CMD_STOP, -+ ANDROID_WIFI_CMD_SCAN_ACTIVE, -+ ANDROID_WIFI_CMD_SCAN_PASSIVE, -+ ANDROID_WIFI_CMD_RSSI, -+ ANDROID_WIFI_CMD_LINKSPEED = 5, -+ ANDROID_WIFI_CMD_RXFILTER_START, -+ ANDROID_WIFI_CMD_RXFILTER_STOP, -+ ANDROID_WIFI_CMD_RXFILTER_ADD, -+ ANDROID_WIFI_CMD_RXFILTER_REMOVE, -+ ANDROID_WIFI_CMD_BTCOEXSCAN_START = 10, -+ ANDROID_WIFI_CMD_BTCOEXSCAN_STOP, -+ ANDROID_WIFI_CMD_BTCOEXMODE, -+ ANDROID_WIFI_CMD_SETSUSPENDOPT, -+ ANDROID_WIFI_CMD_SETFWPATH, -+ ANDROID_WIFI_CMD_SETBAND = 15, -+ ANDROID_WIFI_CMD_GETBAND, -+ ANDROID_WIFI_CMD_COUNTRY, -+ ANDROID_WIFI_CMD_P2P_SET_NOA, -+ ANDROID_WIFI_CMD_P2P_GET_NOA, -+ ANDROID_WIFI_CMD_P2P_SET_PS = 20, -+ ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE, -+#ifdef PNO_SUPPORT -+ ANDROID_WIFI_CMD_PNOSSIDCLR_SET, -+ ANDROID_WIFI_CMD_PNOSETUP_SET, -+ ANDROID_WIFI_CMD_PNOENABLE_SET, -+ ANDROID_WIFI_CMD_PNODEBUG_SET, -+#endif -+ -+ ANDROID_WIFI_CMD_BLOCK, -+ -+ ANDROID_WIFI_CMD_WFD_ENABLE, -+ ANDROID_WIFI_CMD_WFD_DISABLE, -+ -+ ANDROID_WIFI_CMD_WFD_SET_TCPPORT, -+ ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT, -+ ANDROID_WIFI_CMD_WFD_SET_DEVTYPE, -+ ANDROID_WIFI_CMD_FW_REPAIR, -+ -+ ANDROID_WIFI_CMD_MAX -+}; -+ -+ -+int aml_android_priv_cmd(struct wlan_net_vif *wnet_vif, void __user *data, int cmd); -+#endif //_IEEE80211_ANDROID_H_ ++/* ++ **************************************************************************************** ++ * ++ * Copyright (C) Amlogic 2010-2014 ++ * ++ * Project: 11N 80211 mac layer Software ++ * ++ * Description: ++ * wifi_mac android interface module ++ * ++ * ++ **************************************************************************************** ++ */ ++#ifndef _IEEE80211_ANDROID_H_ ++#define _IEEE80211_ANDROID_H_ ++ ++struct android_wifi_priv_cmd ++{ ++ char *buf; ++ int used_len; ++ int total_len; ++} ; ++ ++#ifdef CONFIG_COMPAT ++ typedef struct _compat_android_wifi_priv_cmd { ++ compat_caddr_t buf; ++ int used_len; ++ int total_len; ++ } compat_android_wifi_priv_cmd; ++#endif /* CONFIG_COMPAT */ ++ ++enum ANDROID_WIFI_CMD ++{ ++ ANDROID_WIFI_CMD_START = 0, ++ ANDROID_WIFI_CMD_STOP, ++ ANDROID_WIFI_CMD_SCAN_ACTIVE, ++ ANDROID_WIFI_CMD_SCAN_PASSIVE, ++ ANDROID_WIFI_CMD_RSSI, ++ ANDROID_WIFI_CMD_LINKSPEED = 5, ++ ANDROID_WIFI_CMD_RXFILTER_START, ++ ANDROID_WIFI_CMD_RXFILTER_STOP, ++ ANDROID_WIFI_CMD_RXFILTER_ADD, ++ ANDROID_WIFI_CMD_RXFILTER_REMOVE, ++ ANDROID_WIFI_CMD_BTCOEXSCAN_START = 10, ++ ANDROID_WIFI_CMD_BTCOEXSCAN_STOP, ++ ANDROID_WIFI_CMD_BTCOEXMODE, ++ ANDROID_WIFI_CMD_SETSUSPENDOPT, ++ ANDROID_WIFI_CMD_SETFWPATH, ++ ANDROID_WIFI_CMD_SETBAND = 15, ++ ANDROID_WIFI_CMD_GETBAND, ++ ANDROID_WIFI_CMD_COUNTRY, ++ ANDROID_WIFI_CMD_P2P_SET_NOA, ++ ANDROID_WIFI_CMD_P2P_GET_NOA, ++ ANDROID_WIFI_CMD_P2P_SET_PS = 20, ++ ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE, ++#ifdef PNO_SUPPORT ++ ANDROID_WIFI_CMD_PNOSSIDCLR_SET, ++ ANDROID_WIFI_CMD_PNOSETUP_SET, ++ ANDROID_WIFI_CMD_PNOENABLE_SET, ++ ANDROID_WIFI_CMD_PNODEBUG_SET, ++#endif ++ ++ ANDROID_WIFI_CMD_BLOCK, ++ ++ ANDROID_WIFI_CMD_WFD_ENABLE, ++ ANDROID_WIFI_CMD_WFD_DISABLE, ++ ++ ANDROID_WIFI_CMD_WFD_SET_TCPPORT, ++ ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT, ++ ANDROID_WIFI_CMD_WFD_SET_DEVTYPE, ++ ANDROID_WIFI_CMD_FW_REPAIR, ++ ++ ANDROID_WIFI_CMD_MAX ++}; ++ ++ ++int aml_android_priv_cmd(struct wlan_net_vif *wnet_vif, void __user *data, int cmd); ++#endif //_IEEE80211_ANDROID_H_ diff --git a/drivers/net/wireless/w1/vmac/wifi_cfg80211.c b/drivers/net/wireless/w1/vmac/wifi_cfg80211.c new file mode 100644 -index 000000000000..b6e0dde8a4ca +index 0000000000000000000000000000000000000000..c08dbcfdb98af231513ee98826f2c566b38c157b --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_cfg80211.c -@@ -0,0 +1,7104 @@ +@@ -0,0 +1,7435 @@ +/* + **************************************************************************************** + * @@ -39521,6 +39368,10 @@ index 000000000000..b6e0dde8a4ca +#include "rf_d_adda_recv_reg.h" +#include "chip_intf_reg.h" +#include ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) && defined (CONFIG_AMLOGIC_KERNEL_VERSION)) \ ++ && __has_include() ++#include ++#endif +#include "wifi_pkt_desc.h" +#include "wifi_mac_sae.h" +#include "wifi_mac_action.h" @@ -40779,7 +40630,7 @@ index 000000000000..b6e0dde8a4ca + if (buf && len && (WIFINET_M_HOSTAP == wnet_vif->vm_opmode)) + { + AML_PRINT(AML_DBG_MODULES_P2P, "len=%d\n", len); -+ //dump_memory_internel(buf, len); ++ //dump_memory_internal(buf, len); + } +#endif + @@ -40983,17 +40834,30 @@ index 000000000000..b6e0dde8a4ca + +void vm_cfg80211_indicate_connect(struct wlan_net_vif *wnet_vif) +{ -+ struct wireless_dev *pwdev = wnet_vif->vm_wdev; -+ struct vm_wdev_priv *pwdev_priv = wdev_to_priv(pwdev); -+ struct wifi_station *sta = wnet_vif->vm_mainsta; ++ struct wireless_dev *pwdev; ++ struct vm_wdev_priv *pwdev_priv; ++ struct wifi_station *sta; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)) + struct cfg80211_bss *bss = NULL; + struct ieee80211_channel *notify_channel = NULL; -+ unsigned short channel = wnet_vif->vm_curchan->chan_pri_num; ++ unsigned short channel; + unsigned int freq; ++#endif ++ ++ if (!wnet_vif) ++ return; + ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)) ++ if (!wnet_vif->vm_curchan) ++ return; ++ ++ channel = wnet_vif->vm_curchan->chan_pri_num; +#endif + ++ pwdev = wnet_vif->vm_wdev; ++ pwdev_priv = wdev_to_priv(pwdev); ++ sta = wnet_vif->vm_mainsta; ++ + DPRINTF(AML_DEBUG_CFG80211, "%s %d <%s>\n", __func__, __LINE__, VMAC_DEV_NAME(wnet_vif)); + + if ((pwdev->iftype != NL80211_IFTYPE_STATION) @@ -41011,6 +40875,10 @@ index 000000000000..b6e0dde8a4ca + __func__, __LINE__, wnet_vif->vm_state,pwdev->iftype); + pwdev_priv->connect_request = NULL; + ++ if (sta->connect_status == CONNECT_CONNECTED) { ++ DPRINTF(AML_DEBUG_CFG80211,"%s %d, already connected\n", __func__, __LINE__); ++ return; ++ } +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)) + if (channel <= AML_2G_CHANNELS_NUM) + freq = aml_ieee80211_chan_to_frq(channel, IEEE80211_BAND_2GHZ); @@ -41041,6 +40909,7 @@ index 000000000000..b6e0dde8a4ca + wnet_vif->assocrsp_ie.length, WLAN_STATUS_SUCCESS, GFP_ATOMIC); +#endif + ++ sta->connect_status = CONNECT_CONNECTED; + DPRINTF(AML_DEBUG_CFG80211, "%s %d wnet_vif->vm_state=%d\n", __func__, __LINE__, wnet_vif->vm_state); + return; +} @@ -41049,10 +40918,13 @@ index 000000000000..b6e0dde8a4ca +vm_cfg80211_connect_timeout_task(SYS_TYPE net) +{ + struct wlan_net_vif *wnet_vif = (struct wlan_net_vif*)net; -+ vm_cfg80211_indicate_disconnect(wnet_vif); -+ wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN, 0); ++ + wnet_vif->vm_des_nssid = 0; ++ wnet_vif->vm_curchan = WIFINET_CHAN_ERR; + memset(wnet_vif->vm_des_ssid, 0, IV_SSID_SCAN_AMOUNT*sizeof(struct wifi_mac_ScanSSID)); ++ vm_cfg80211_indicate_disconnect(wnet_vif); ++ wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN, 0); ++ + return; +} + @@ -41098,7 +40970,7 @@ index 000000000000..b6e0dde8a4ca +#endif +} + -+void vm_cfg80211_connect_result(struct wlan_net_vif *wnet_vif) ++static void vm_cfg80211_connect_result(struct wlan_net_vif *wnet_vif) +{ + wifi_mac_add_work_task(wnet_vif->vm_wmac, vm_cfg80211_connect_result_ex, NULL, (SYS_TYPE)wnet_vif, 0, 0, 0, 0); +} @@ -41107,9 +40979,16 @@ index 000000000000..b6e0dde8a4ca +{ + struct wireless_dev *pwdev = wnet_vif->vm_wdev; + struct vm_wdev_priv *pwdev_priv = wdev_to_priv(pwdev); ++ struct wifi_station *sta = wnet_vif->vm_mainsta; + struct wifi_mac *wifimac = wnet_vif->vm_wmac; ++ unsigned int status_code = WLAN_STATUS_UNSPECIFIED_FAILURE; ++ unsigned char report = 0; ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)) ++ struct cfg80211_bss *bss = NULL; ++#endif + -+ DPRINTF(AML_DEBUG_CFG80211, "%s %d <%s>\n", __func__, __LINE__, VMAC_DEV_NAME(wnet_vif)); ++ DPRINTF(AML_DEBUG_CFG80211, "%s %d <%s> vm_state:%d, disconnect_reason_code:%d\n", __func__, __LINE__, ++ VMAC_DEV_NAME(wnet_vif), wnet_vif->vm_state, wnet_vif->disconnect_reason_code); + + if ((pwdev->iftype != NL80211_IFTYPE_STATION) +#ifdef CONFIG_P2P @@ -41126,33 +41005,75 @@ index 000000000000..b6e0dde8a4ca + os_timer_ex_cancel(&pwdev_priv->connect_timeout, CANCEL_SLEEP); + } + -+ if (wnet_vif->vm_state == WIFINET_S_CONNECTING) { ++ if ((wnet_vif->vm_phase_flags & PHASE_DISCONNECTING) && (pwdev->iftype == NL80211_IFTYPE_STATION)) { ++ wnet_vif->vm_phase_flags &= PHASE_DISCONNECTING; ++ } else { ++ wnet_vif->vm_phase_flags = 0; ++ } ++ ++ if (sta->connect_status == CONNECT_DISCONNECTED) { ++ DPRINTF(AML_DEBUG_CFG80211, "%s %d already disconnected\n", __func__, __LINE__); ++ return; ++ } ++ ++ do { ++ if (((wnet_vif->vm_state > WIFINET_S_SCAN) ++ || ((wnet_vif->vm_state == WIFINET_S_SCAN) ++ && (wnet_vif->vm_state_pre > WIFINET_S_SCAN) ++ && (wnet_vif->vm_state_pre < WIFINET_S_CONNECTED))) ++ && (wnet_vif->vm_state_pre < WIFINET_S_CONNECTED)) { ++ if (wnet_vif->disconnect_reason_code) { ++ status_code = wnet_vif->disconnect_reason_code; ++ } +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)) -+ cfg80211_connect_bss(wnet_vif->vm_ndev, NULL, NULL, NULL, 0, NULL, ++ bss = cfg80211_get_bss(pwdev->wiphy, NULL, sta->sta_bssid, sta->sta_essid, sta->sta_esslen, ++ IEEE80211_BSS_TYPE_ANY, IEEE80211_PRIVACY_ANY); ++ ++ if (bss == NULL) { ++ DPRINTF(AML_DEBUG_CFG80211, "%s %d, bss entry has been released by the user\n", __func__, __LINE__); ++ break; ++ } ++ ++ cfg80211_connect_bss(wnet_vif->vm_ndev, sta->sta_bssid, bss, NULL, 0, NULL, +#if LINUX_VERSION_CODE <= KERNEL_VERSION(4, 12, 0) -+ 0, WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_KERNEL); ++ 0, status_code, GFP_ATOMIC); +#else -+ 0, WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_KERNEL,NL80211_TIMEOUT_UNSPECIFIED); ++ 0, status_code, GFP_ATOMIC,NL80211_TIMEOUT_UNSPECIFIED); +#endif +#else -+ cfg80211_connect_result(wnet_vif->vm_ndev, NULL, NULL, 0, NULL, 0, -+ WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_ATOMIC); ++ cfg80211_connect_result(wnet_vif->vm_ndev, sta->sta_bssid, NULL, 0, NULL, 0, ++ status_code, GFP_ATOMIC); +#endif ++ report = 1; ++ } ++ } while (0); ++ ++ if (report == 0 || sta->connect_status == CONNECT_DISCONNECTING) { ++ bool local_generated = false; + -+ } else { + #if LINUX_VERSION_CODE < KERNEL_VERSION(4,16,1) -+ if ((wnet_vif->vm_flags & WIFINET_F_PRIVACY) && !(wnet_vif->vm_flags & WIFINET_F_WPA)) { ++ if ((wnet_vif->vm_flags & WIFINET_F_PRIVACY) && !(wnet_vif->vm_flags & WIFINET_F_WPA) && report == 0) { ++ wnet_vif->vm_phase_flags |= PHASE_WAIT_DISCONNECT_RESULT; + vm_cfg80211_connect_result(wnet_vif); + } + #endif + ++ if (wnet_vif->disconnect_reason_code == DISCONNECT_SYSTEM) { ++ local_generated = true; ++ } ++ + #if LINUX_VERSION_CODE > KERNEL_VERSION(4,2,0) -+ cfg80211_disconnected(wnet_vif->vm_ndev, 0, NULL, 0, false, GFP_ATOMIC); ++ /* coverity[NESTING_INDENT_MISMATCH:SUPPRESS] */ ++ cfg80211_disconnected(wnet_vif->vm_ndev, wnet_vif->disconnect_reason_code, NULL, 0, local_generated, GFP_ATOMIC); + #else -+ cfg80211_disconnected(wnet_vif->vm_ndev, 0, NULL, 0, GFP_ATOMIC); ++ cfg80211_disconnected(wnet_vif->vm_ndev, wnet_vif->disconnect_reason_code, NULL, 0, GFP_ATOMIC); + #endif + } ++ + wnet_vif->vm_phase_flags = 0; ++ wnet_vif->disconnect_reason_code = 0; ++ wnet_vif->vm_des_channel = WIFINET_CHAN_ERR; ++ sta->connect_status = CONNECT_DISCONNECTED; + wifimac->recovery_stat = WIFINET_RECOVERY_END; + os_timer_ex_cancel(&wnet_vif->vm_mgtsend, CANCEL_SLEEP); + return; @@ -41163,103 +41084,16 @@ index 000000000000..b6e0dde8a4ca + struct wlan_net_vif *wnet_vif = sta->sta_wnet_vif; + struct net_device *dev = wnet_vif->vm_ndev; + struct station_info sinfo; -+ unsigned char *buf = NULL, *pbuf = NULL; -+ size_t len = 0; -+ int ielen = 0; -+ int index = 0; -+ DPRINTF(AML_DEBUG_CFG80211, "%s %d <%s>\n", __func__, __LINE__, VMAC_DEV_NAME(wnet_vif)); -+ memset(&sinfo, 0, sizeof(struct station_info)); -+ //sinfo.generation = 0; -+ //sinfo.filled = 0; -+ //sinfo.signal = 0; + -+ //sinfo.assoc_req_ies = NULL; //not ready for kernel=2.6.34 -+ //sinfo.assoc_req_ies_len = 0; //not ready for kernel=2.6.34 -+#ifndef KERNEL_VERSION_SPECIFIC_AML_ICS_308 -+ buf = ZMALLOC(AML_SCAN_IE_LEN_MAX,"buf", GFP_ATOMIC); -+ if (!buf) -+ { -+ DPRINTF(AML_DEBUG_CFG80211|AML_DEBUG_ERROR, "%s %d ERROR NOMEM\n", __func__, __LINE__); -+ goto exit; -+ } -+ -+ #if LINUX_VERSION_CODE > KERNEL_VERSION(3,14,29) -+ //sinfo.filled |= STATION_INFO_ASSOC_REQ_IES; -+ #else -+ sinfo.filled |= STATION_INFO_ASSOC_REQ_IES; -+ #endif -+ -+ pbuf = buf; -+ len = 0; -+ if (sta->sta_wpa_ie) -+ { -+ DPRINTF(AML_DEBUG_CFG80211, "%s %d cp sta_wpa_ie\n", __func__, __LINE__); -+ ielen = wifi_mac_copy_ie(pbuf, sta->sta_wpa_ie, SCANINFO_IE_DATA_LENGTH); -+ pbuf += ielen; -+ len += ielen; -+ } -+ if (sta->sta_rsn_ie) -+ { -+ DPRINTF(AML_DEBUG_CFG80211, "%s %d cp sta_rsn_ie\n", __func__, __LINE__); -+ ielen = wifi_mac_copy_ie(pbuf, sta->sta_rsn_ie, SCANINFO_IE_DATA_LENGTH); -+ pbuf += ielen; -+ len += ielen; -+ } -+ if (sta->sta_wps_ie) -+ { -+ DPRINTF(AML_DEBUG_CFG80211, "%s %d cp sta_wps_ie\n", __func__, __LINE__); -+ ielen = wifi_mac_copy_ie(pbuf, sta->sta_wps_ie, SCANINFO_IE_DATA_LENGTH); -+ pbuf += ielen; -+ len += ielen; -+ } -+ if (sta->sta_wme_ie) -+ { -+ DPRINTF(AML_DEBUG_CFG80211, "%s %d cp sta_wme_ie\n", __func__, __LINE__); -+ ielen = wifi_mac_copy_ie(pbuf, sta->sta_wme_ie, SCANINFO_IE_DATA_LENGTH); -+ pbuf += ielen; -+ len += ielen; -+ } -+#ifdef CONFIG_P2P -+ for (index = 0; index < MAX_P2PIE_NUM; index++) -+ { -+ if (sta->sta_p2p_ie[index]) -+ { -+ DPRINTF(AML_DEBUG_CFG80211, "%s %d cp sta_p2p_ie\n", __func__, __LINE__); -+ ielen = wifi_mac_copy_ie(pbuf, sta->sta_p2p_ie[index], SCANINFO_IE_DATA_LENGTH); -+ pbuf += ielen; -+ len += ielen; -+ } -+ } -+#endif//CONFIG_P2P -+#ifdef CONFIG_WFD -+ if (sta->sta_wfd_ie) -+ { -+ DPRINTF(AML_DEBUG_CFG80211, "%s %d cp sta_p2p_ie\n", __func__, __LINE__); -+ ielen = wifi_mac_copy_ie(pbuf, sta->sta_wfd_ie, SCANINFO_IE_DATA_LENGTH); -+ pbuf += ielen; -+ len += ielen; -+ } -+#endif//CONFIG_WFD -+#ifdef CONFIG_WAPI -+ if (sta->sta_wai_ie) -+ { -+ DPRINTF(AML_DEBUG_CFG80211, "%s %d cp sta_wai_ie\n", __func__, __LINE__); -+ ielen = wifi_mac_copy_ie(pbuf, sta->sta_wai_ie, SCANINFO_IE_DATA_LENGTH); -+ pbuf += ielen; -+ len += ielen; -+ } -+#endif -+ sinfo.assoc_req_ies = buf; -+ sinfo.assoc_req_ies_len = len; -+#endif -+ exit: ++ memset(&sinfo, 0, sizeof(struct station_info)); ++ sinfo.assoc_req_ies = sta->sta_assoc_req; ++ sinfo.assoc_req_ies_len = sta->sta_assoc_req_ielen; + cfg80211_new_sta(dev, sta->sta_macaddr, &sinfo, GFP_ATOMIC); + + //not ready for kernel=2.6.34 + //cfg80211_rx_mgmt(dev, freq, buf, len, gfp); + -+ FREE(buf,"buf"); -+ DPRINTF(AML_DEBUG_CFG80211, "%s %d\n", __func__, __LINE__); ++ DPRINTF(AML_DEBUG_CFG80211, "%s %d <%s>\n", __func__, __LINE__, VMAC_DEV_NAME(wnet_vif)); + return; +} +void @@ -41327,6 +41161,7 @@ index 000000000000..b6e0dde8a4ca + //p2p-p2p0-1 + // wifimac->wm_nops.wm_vmac_create(wifimac, name, 2, nl80211_iftype_2_drv_opmode(type), NULL); + vm_cfg80211_add_p2p_go_if(wnet_vif,name,type); ++ aml_wifi_set_con_mode(wnet_vif->vm_wmac); + break; + case NL80211_IFTYPE_AP: + DPRINTF(AML_DEBUG_CFG80211, "%s %d AP\n", __func__, __LINE__); @@ -41422,7 +41257,7 @@ index 000000000000..b6e0dde8a4ca + int ret = 0; + + if (!aml_insmod_flag) { -+ printk("%s %d, aml insmod not complete\n",__func__,__LINE__); ++ pr_err("%s %d, aml insmod not complete\n",__func__,__LINE__); + return -1; + } + @@ -41484,6 +41319,7 @@ index 000000000000..b6e0dde8a4ca + wait_for_ap_run(wnet_vif, 10000, 100); + DPRINTF(AML_DEBUG_CFG80211, "%s %d wait_for_ap_run over\n", __func__, __LINE__); + } ++ aml_wifi_set_con_mode(wnet_vif->vm_wmac); + } + +exit: @@ -41562,13 +41398,17 @@ index 000000000000..b6e0dde8a4ca + } +#endif + ++ if (wifimac->wm_flags & WIFINET_F_CHANSWITCH) { ++ DPRINTF(AML_DEBUG_WARNING, "%s(%d), rejected wlan0 scan due to channel switch\n",__func__,__LINE__); ++ return -EINVAL; ++ } ++ + /*need thinking more, maybe there are bugs happen*/ -+ /* -+ if (IS_APSTA_CONCURRENT(aml_wifi_get_con_mode()) && (wifimac->wm_nrunning == 2)) { ++ if (IS_APSTA_CONCURRENT(aml_wifi_get_con_mode()) && (wifimac->wm_nrunning == 2) && ++ !concurrent_check_is_vmac_same_pri_channel(wifimac)) { + DPRINTF(AML_DEBUG_WARNING, "%s(%d), rejected wlan0 scan due to softap working\n",__func__,__LINE__); + return -EINVAL; + } -+ */ + + if (wifimac->wm_flags & WIFINET_F_SCAN) { + if ((wnet_vif->wnet_vif_id != NET80211_MAIN_VMAC) || (pwdev_priv->scan_request == NULL)) { @@ -41687,7 +41527,7 @@ index 000000000000..b6e0dde8a4ca + unsigned short retry_short = 0; + unsigned short retry_long = 0; + -+ printk("enter %s, %d\n", __func__, __LINE__); ++ pr_debug("enter %s, %d\n", __func__, __LINE__); + retry_short = wiphy->retry_short; + retry_long = wiphy->retry_long; + if (changed & WIPHY_PARAM_RETRY_LONG || changed & WIPHY_PARAM_RETRY_SHORT) { @@ -41702,13 +41542,13 @@ index 000000000000..b6e0dde8a4ca + if (changed & WIPHY_PARAM_RTS_THRESHOLD && + wnet_vif->vm_rtsthreshold != wiphy->rts_threshold) { + wnet_vif->vm_rtsthreshold = wiphy->rts_threshold; -+ printk("vm_rtsthreshold:%d\n", wnet_vif->vm_rtsthreshold); ++ pr_debug("vm_rtsthreshold:%d\n", wnet_vif->vm_rtsthreshold); + } + + if (changed & WIPHY_PARAM_FRAG_THRESHOLD && + wnet_vif->vm_fragthreshold != wiphy->frag_threshold) { + wnet_vif->vm_fragthreshold = wiphy->frag_threshold; -+ printk("vm_fragthreshold: %d\n", wnet_vif->vm_fragthreshold); ++ pr_debug("vm_fragthreshold: %d\n", wnet_vif->vm_fragthreshold); + } + + DPRINTF(AML_DEBUG_CFG80211, "%s %d\n", __func__, __LINE__); @@ -41724,7 +41564,7 @@ index 000000000000..b6e0dde8a4ca + struct wireless_dev *vm_wdev; + + vm_wdev = wnet_vif->vm_wdev; -+ printk("vm_wdev:0x%p, %s, %d\n", vm_wdev, __func__, __LINE__); ++ pr_debug("vm_wdev:0x%p, %s, %d\n", vm_wdev, __func__, __LINE__); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,15,0) + chandef = &vm_wdev->preset_chandef; @@ -41785,7 +41625,7 @@ index 000000000000..b6e0dde8a4ca + break; + case NL80211_CHAN_WIDTH_80P80: + case NL80211_CHAN_WIDTH_160: -+ printk("%s:%d, not support bandwidth %d yet \n", ++ pr_warn("%s:%d, not support bandwidth %d yet \n", + __func__, __LINE__, params->chandef.width); + bw = WIFINET_BWC_WIDTH20; + center_chan = pri_chan; @@ -41834,7 +41674,7 @@ index 000000000000..b6e0dde8a4ca + struct wifi_mac *wifimac = wnet_vif->vm_wmac; + + DPRINTF(AML_DEBUG_CFG80211, "%s %d\n", __func__, __LINE__); -+ printk("---tx_power_setting: %d, dbm: %d\n", type, dbm); ++ pr_debug("---tx_power_setting: %d, dbm: %d\n", type, dbm); + + wifimac->drv_priv->drv_ops.drv_set_txPwrLimit(wifimac->drv_priv, type, dbm); + @@ -41849,7 +41689,7 @@ index 000000000000..b6e0dde8a4ca + struct wifi_mac *wifimac = wnet_vif->vm_wmac; + + DPRINTF(AML_DEBUG_CFG80211, "%s %d\n", __func__, __LINE__); -+ printk("---drv_curtxpower:%d\n", *dbm); ++ pr_debug("---drv_curtxpower:%d\n", *dbm); + *dbm = wifimac->drv_priv->drv_curtxpower; + + return 0; @@ -41899,7 +41739,7 @@ index 000000000000..b6e0dde8a4ca + memcpy(k->wk_key, key, key_len); + memset(k->wk_key + key_len, 0, WIFINET_KEYBUF_SIZE - key_len); + //if (aml_debug & AML_DEBUG_CFG80211) { -+ // dump_memory_internel(k->wk_key, WIFINET_KEYBUF_SIZE+16); ++ // dump_memory_internal(k->wk_key, WIFINET_KEYBUF_SIZE+16); + //} + if (!wifi_mac_security_setkey(wnet_vif, k, wnet_vif->vm_myaddr, NULL)) + { @@ -42094,7 +41934,7 @@ index 000000000000..b6e0dde8a4ca + if (kr.ik_type == WIFINET_CIPHER_AES_CMAC) { + wk->wk_valid = 1; + wk->wk_keyix = key_index; -+ printk("not set pmf key to fw\n"); ++ pr_debug("not set pmf key to fw\n"); + goto new_key_exit; + } + @@ -42178,10 +42018,19 @@ index 000000000000..b6e0dde8a4ca + goto exit; + } + -+ while (total_delay < 1000 && ((sta->connect_status != CONNECT_IDLE) -+ || (!drv_priv->hal_priv->hal_ops.hal_tx_empty()))) { -+ if (wnet_vif->vm_opmode == WIFINET_M_HOSTAP && sta->is_disconnecting == 0) ++ while (total_delay < 1000) { ++ if ((wnet_vif->vm_opmode == WIFINET_M_HOSTAP) ++ && ((sta->is_disconnecting == 0) || (drv_priv->hal_priv->hal_ops.hal_tx_empty()))) { + break; ++ } ++ ++ if ((wnet_vif->vm_opmode == WIFINET_M_STA) ++ && (drv_priv->hal_priv->hal_ops.hal_tx_empty()) ++ && ((sta->connect_status == CONNECT_IDLE) || (sta->connect_status == CONNECT_DISCONNECTED))) ++ { ++ break; ++ } ++ + msleep(10); + total_delay += 10; + } @@ -42289,13 +42138,15 @@ index 000000000000..b6e0dde8a4ca + struct wlan_net_vif *wnet_vif = wiphy_to_adapter(wiphy); + struct vm_wdev_priv *pwdev_priv = wdev_to_priv(wnet_vif->vm_wdev); + struct cfg80211_connect_params *lsme = sme; -+ ++ struct cfg80211_bss *bss = NULL; + int ret = 0; + unsigned char *rsn_ie = NULL; + unsigned int rsn_ie_len = 0; + struct wifi_mac *wifimac = wnet_vif->vm_wmac; + struct wifi_mac_scan_state *ss = wifimac->wm_scan; + struct drv_private* drv_priv = wifimac->drv_priv; ++ struct wlan_net_vif *p2p_vmac = drv_priv->drv_wnet_vif_table[NET80211_P2P_VMAC]; ++ unsigned int delay_ms = 0; + + DPRINTF(AML_DEBUG_CFG80211, "%s %d <%s> privacy=%d, key=%p, key_len=%d, key_idx=%d\n", + __func__, __LINE__, dev->name, lsme->privacy, lsme->key, lsme->key_len, lsme->key_idx); @@ -42340,6 +42191,18 @@ index 000000000000..b6e0dde8a4ca + return ret; + } + ++ while (wnet_vif->vm_mainsta->is_disconnecting || wnet_vif->vm_mainsta->connect_status == CONNECT_DISCONNECTING) ++ { ++ msleep(5); ++ delay_ms += 5; ++ ++ if (delay_ms >= 1000) { ++ ERROR_DEBUG_OUT("disconnecting process is not done, delay_ms:%d, connect_status:%d\n", delay_ms, wnet_vif->vm_mainsta->connect_status); ++ ret = -EBUSY; ++ goto exit; ++ } ++ } ++ + if (pwdev_priv->connect_request) { + DPRINTF(AML_DEBUG_WARNING, "%s %d multiple connect req, should not happen\n", __func__, __LINE__); + } @@ -42347,20 +42210,47 @@ index 000000000000..b6e0dde8a4ca + + memset(wnet_vif->vm_des_ssid, 0, IV_SSID_SCAN_AMOUNT * sizeof(struct wifi_mac_ScanSSID)); + memset(wnet_vif->vm_des_bssid, 0, WIFINET_ADDR_LEN); ++ wnet_vif->vm_des_channel = WIFINET_CHAN_ERR; + wnet_vif->vm_des_ssid[0].len= lsme->ssid_len; + memcpy(wnet_vif->vm_des_ssid[0].ssid, lsme->ssid, lsme->ssid_len); + wnet_vif->vm_des_nssid = 1; + wnet_vif->vm_flags &= ~WIFINET_F_IGNORE_SSID; + wnet_vif->vm_flags &= ~WIFINET_F_DESBSSID; ++ wnet_vif->disconnect_reason_code = 0; + + wifimac->wm_lastroaming = jiffies; + wnet_vif->vm_chan_roaming_scan_flag = 0; + g_auto_gain_base = 0; + ++ bss = cfg80211_get_bss(wiphy, NULL, sme->bssid,sme->ssid, sme->ssid_len, IEEE80211_BSS_TYPE_ANY, IEEE80211_PRIVACY_ANY); ++ ++ if (bss != NULL) { ++ unsigned int htcapie_len = 0; ++ unsigned int htinfoie_len = 0; ++ unsigned int vhtoptie_len = 0; ++ unsigned char *htcapie = NULL; ++ unsigned char *htinfoie = NULL; ++ unsigned char *vhtoptie = NULL; ++ const struct cfg80211_bss_ies *ies = rcu_dereference_protected(bss->ies, lockdep_is_held(&wiphy->mtx)); ++ ++ htcapie = vm_get_ie(ies->data, ies->len, NULL, (unsigned int *)&htcapie_len, WIFINET_ELEMID_HTCAP, 0); ++ htinfoie = vm_get_ie(ies->data, ies->len, NULL, (unsigned int *)&htinfoie_len, WIFINET_ELEMID_HTINFO, 0); ++ vhtoptie = vm_get_ie(ies->data, ies->len, NULL, (unsigned int *)&vhtoptie_len, WIFINET_ELEMID_VHTOP, 0); ++ ++ wnet_vif->vm_des_channel = wifi_mac_scan_sta_get_ap_channel(wnet_vif, lsme->channel->hw_value, htinfoie, htcapie, vhtoptie); ++ ++ if (wnet_vif->vm_des_channel != WIFINET_CHAN_ERR) { ++ AML_OUTPUT("pri_chan:%d, center_chan:%d, bw:%d\n",wnet_vif->vm_des_channel->chan_pri_num, ++ wifi_mac_Mhz2ieee(wnet_vif->vm_des_channel->chan_cfreq1,0), wnet_vif->vm_des_channel->chan_bw); ++ } ++ ++ cfg80211_put_bss(wiphy, bss); ++ } ++ + /*if change AP,change roaming_ssid and clean roaming candidate channel*/ + if(!wnet_vif->vm_wmac->wm_scan->roaming_ssid.len + || memcmp(wnet_vif->vm_wmac->wm_scan->roaming_ssid.ssid, lsme->ssid, wnet_vif->vm_wmac->wm_scan->roaming_ssid.len) != 0) { -+ printk("clean roaming candidate channels \n"); ++ pr_debug("clean roaming candidate channels \n"); + wnet_vif->vm_wmac->wm_scan->roaming_ssid.len = lsme->ssid_len; + memcpy(wnet_vif->vm_wmac->wm_scan->roaming_ssid.ssid, lsme->ssid, lsme->ssid_len); + @@ -42419,7 +42309,7 @@ index 000000000000..b6e0dde8a4ca + + wnet_vif->vm_mainsta->sta_authmode = sta_authmode; + } -+ printk("%s %d lsme->auth_type=%d, sta_authmode=%d\n", __func__, __LINE__, lsme->auth_type, wnet_vif->vm_mainsta->sta_authmode); ++ pr_debug("%s %d lsme->auth_type=%d, sta_authmode=%d\n", __func__, __LINE__, lsme->auth_type, wnet_vif->vm_mainsta->sta_authmode); + + if (lsme->crypto.wpa_versions) { + unsigned int wpa_versions = lsme->crypto.wpa_versions; @@ -42563,19 +42453,34 @@ index 000000000000..b6e0dde8a4ca + + DPRINTF(AML_DEBUG_CFG80211, "%s %d connect_timeout=%d ms\n", __func__, __LINE__, CFG80211_CONNECT_TIMER_OUT); + -+ if (wnet_vif->vm_state == WIFINET_S_CONNECTED) { -+ wifi_mac_top_sm(wnet_vif, WIFINET_S_ASSOC, 0); ++ if (IS_APSTA_CONCURRENT(aml_wifi_get_con_mode()) ++ && concurrent_check_vmac_is_AP(wifimac) ++ && (wnet_vif->vm_opmode == WIFINET_M_STA) ++ && (p2p_vmac->vm_state == WIFINET_S_CONNECTED)) { ++ unsigned int delay_ms = 0; ++ struct wifi_channel *switch_chan = NULL; + -+ } else { -+ wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN, 0); ++ switch_chan = wnet_vif->vm_des_channel; ++ channel_switch_announce_trigger(wifimac, switch_chan); ++ while ((wifimac->wm_flags & WIFINET_F_DOTH) && (wifimac->wm_flags & WIFINET_F_CHANSWITCH) && (delay_ms < 1000)) { ++ msleep(50); ++ delay_ms += 50; ++ } ++ DPRINTF(AML_DEBUG_CONNECT, "delay_ms:%d\n",delay_ms); + } + + OS_SPIN_LOCK_IRQ(&pwdev_priv->connect_req_lock,pwdev_priv->connect_req_lock_flags); -+ wnet_vif->vm_mainsta->connect_status = CONNECT_IDLE; ++ wnet_vif->vm_mainsta->connect_status = CONNECT_CONNECTING; + pwdev_priv->connect_request = sme; + os_timer_ex_start(&pwdev_priv->connect_timeout); + OS_SPIN_UNLOCK_IRQ(&pwdev_priv->connect_req_lock,pwdev_priv->connect_req_lock_flags); + ++ if (wnet_vif->vm_state == WIFINET_S_CONNECTED) { ++ wifi_mac_top_sm(wnet_vif, WIFINET_S_ASSOC, 0); ++ } else { ++ wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN, 0); ++ } ++ +exit: + DPRINTF(AML_DEBUG_CFG80211, "%s %d\n", __func__, __LINE__); + return ret; @@ -42624,18 +42529,32 @@ index 000000000000..b6e0dde8a4ca + } + } + ++ if (wnet_vif->vm_mainsta->connect_status >= CONNECT_DISCONNECTING) { ++ ERROR_DEBUG_OUT("already in disconnecting con_status:%d vm_state:%d\n", wnet_vif->vm_mainsta->connect_status, wnet_vif->vm_state); ++ return -EINVAL; ++ } ++ + switch (wnet_vif->vm_opmode) + { + case WIFINET_M_STA: -+ DPRINTF(AML_DEBUG_CFG80211, "%s %d sta mode\n", __func__, __LINE__); -+ mgmt_arg = WIFINET_REASON_AUTH_LEAVE; -+ wifi_mac_send_mgmt(wnet_vif->vm_mainsta, WIFINET_FC0_SUBTYPE_DEAUTH, (void *)&mgmt_arg); -+ if (wnet_vif->vm_p2p_support) { -+ wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN, 0); ++ DPRINTF(AML_DEBUG_CFG80211, "%s %d sta mode, vm_state:%d\n", __func__, __LINE__, wnet_vif->vm_state); ++ wnet_vif->vm_mainsta->connect_status = CONNECT_DISCONNECTING; ++ wnet_vif->disconnect_reason_code = reason_code; ++ if (wnet_vif->vm_state >= WIFINET_S_AUTH) { ++ mgmt_arg = WIFINET_REASON_AUTH_LEAVE; ++ wifi_mac_send_mgmt(wnet_vif->vm_mainsta, WIFINET_FC0_SUBTYPE_DEAUTH, (void *)&mgmt_arg); ++ if (wnet_vif->vm_p2p_support) { ++ wifi_mac_add_work_task(wnet_vif->vm_wmac, wifi_mac_sm_switch, NULL, (SYS_TYPE)wnet_vif, WIFINET_S_SCAN, 0, 0, 0); ++ } else { ++ os_timer_ex_start_period(&wnet_vif->vm_mgtsend, DEFAULT_DEAUTH_TOT); ++ } ++ } else { ++ wifi_mac_add_work_task(wnet_vif->vm_wmac, wifi_mac_sm_switch, NULL, (SYS_TYPE)wnet_vif, WIFINET_S_SCAN, 0, 0, 0); + } + + while (total_delay < 1000 && ((wifimac->wm_runningmask & BIT(wnet_vif->wnet_vif_id)) -+ || (!drv_priv->hal_priv->hal_ops.hal_tx_empty()))) { ++ || (!drv_priv->hal_priv->hal_ops.hal_tx_empty()) ++ || (wnet_vif->vm_mainsta->connect_status == CONNECT_DISCONNECTING))) { + msleep(10); + total_delay += 10; + } @@ -42763,7 +42682,7 @@ index 000000000000..b6e0dde8a4ca + case 128: + return 0x0b;//54M; + default: -+ //printk("Legacy 5G Warning: Not supported rate.\n"); ++ //pr_debug("Legacy 5G Warning: Not supported rate.\n"); + return 0; + } +} @@ -42790,7 +42709,7 @@ index 000000000000..b6e0dde8a4ca + case 128: + return 0x0087; + default: -+ //printk("HT Warning: Not supported rate: %d\n",kernel_rate); ++ //pr_debug("HT Warning: Not supported rate: %d\n",kernel_rate); + return 0; + } +} @@ -42821,7 +42740,7 @@ index 000000000000..b6e0dde8a4ca + case 512: + return 0x00c9; + default: -+ //printk("VHT Warning: Not supported rate: %d\n",kernel_rate); ++ //pr_debug("VHT Warning: Not supported rate: %d\n",kernel_rate); + return 0; + } +} @@ -42835,7 +42754,7 @@ index 000000000000..b6e0dde8a4ca + //For 11b: (0x82 -0x80) * 500K = 1M + //For 11g: 0xc * 500k = 6M + unsigned int ret = 0; -+ printk("rate 0x%x %s(%d)\n", kernel_rate, __func__, __LINE__); ++ pr_debug("rate 0x%x %s(%d)\n", kernel_rate, __func__, __LINE__); + switch (kernel_rate) + { + case BIT(0): @@ -43002,7 +42921,7 @@ index 000000000000..b6e0dde8a4ca + + if (aml_wifi_is_enable_rf_test()) { + gB2BTestCasePacket.data_rate = final_bit_rate; -+ printk("Cfg80211 B2B: %s %d, rate to be set:0x%04x\n", ++ pr_debug("Cfg80211 B2B: %s %d, rate to be set:0x%04x\n", + __func__,__LINE__,gB2BTestCasePacket.data_rate ); + return 0; + } @@ -43011,7 +42930,7 @@ index 000000000000..b6e0dde8a4ca + wnet_vif->vm_fixed_rate.rateinfo = final_bit_rate; + wnet_vif->vm_fixed_rate.mode = WIFINET_FIXED_RATE_MCS; + wnet_vif->vm_change_rate_enable = 0; -+ printk("Cfg80211: %s %d, rate to be set:0x%02x\n", ++ pr_debug("Cfg80211: %s %d, rate to be set:0x%02x\n", + __func__,__LINE__,wnet_vif->vm_fixed_rate.rateinfo ); + } + @@ -43130,6 +43049,13 @@ index 000000000000..b6e0dde8a4ca + unsigned short htcap_tmp = 0; + unsigned char *ht_op_ie = NULL; + unsigned int ht_op_ie_len = 0; ++ unsigned char *basic_rate_ie = NULL; ++ unsigned char *extend_rate_ie = NULL; ++ unsigned int basic_rate_ie_len = 0; ++ unsigned int extend_rate_ie_len = 0; ++ unsigned char rate_index; ++ unsigned char rate_count = 0; ++ struct wifi_mac_rateset rs = {0}; + + dsps_ie = vm_get_ie(iebuf, ielen, NULL, (unsigned int *)&dsps_ie_len, WIFINET_ELEMID_DSPARMS, 0); + if (!dsps_ie) { @@ -43146,7 +43072,7 @@ index 000000000000..b6e0dde8a4ca + } + } else { + pri_chan = dsps_ie[2]; -+ printk("%s(%d),pri_chan:%d\n\n",__func__,__LINE__,pri_chan); ++ pr_debug("%s(%d),pri_chan:%d\n\n",__func__,__LINE__,pri_chan); + + if (wifi_mac_if_dfs_channel(wifimac, (int)pri_chan) == 1) { + ERROR_DEBUG_OUT("Soft AP don't support in DFS channel \n"); @@ -43158,6 +43084,33 @@ index 000000000000..b6e0dde8a4ca + ht_cap_ie = vm_get_ie(iebuf, ielen, NULL, (unsigned int *)&ht_cap_ie_len, WIFINET_ELEMID_HTCAP, 0); + ht_op_ie = vm_get_ie(iebuf, ielen, NULL, (unsigned int *)&ht_op_ie_len, WIFINET_ELEMID_HTINFO, 0); + ++ basic_rate_ie = vm_get_ie(iebuf, ielen, NULL, (unsigned int *)&basic_rate_ie_len, WIFINET_ELEMID_RATES, 0); ++ extend_rate_ie = vm_get_ie(iebuf, ielen, NULL, (unsigned int *)&extend_rate_ie_len, WIFINET_ELEMID_XRATES, 0); ++ wnet_vif->vm_sae_h2e_only = 0; ++ ++ if (basic_rate_ie) { ++ memcpy(rs.dot11_rate + rs.dot11_rate_num, basic_rate_ie + 2, basic_rate_ie_len - 2); ++ rs.dot11_rate_num += basic_rate_ie_len - 2; ++ } ++ ++ if (extend_rate_ie) { ++ memcpy(rs.dot11_rate + rs.dot11_rate_num, extend_rate_ie + 2, extend_rate_ie_len - 2); ++ rs.dot11_rate_num += extend_rate_ie_len - 2; ++ } ++ ++ for (rate_index = 0; rate_index < rs.dot11_rate_num; rate_index++) { ++ if (wifi_mac_find_rate(rs.dot11_rate[rate_index], wifimac->wm_11b_rates) ++ || wifi_mac_find_rate(rs.dot11_rate[rate_index], wifimac->wm_11g_rates)) { ++ rate_count++; ++ } ++ ++ if (rs.dot11_rate[rate_index] == WIFINET_SAE_H2E_ONLY) { ++ AML_OUTPUT("find WIFINET_SAE_H2E_ONLY rate_num[%d]\n", rate_index); ++ wnet_vif->vm_sae_h2e_only = 1; ++ } ++ } ++ AML_OUTPUT("basic_len:%d, extend_len:%d, dot11_rate_num:%d, rate_count:%d\n", basic_rate_ie_len, extend_rate_ie_len, rs.dot11_rate_num, rate_count); ++ + if (ht_cap_ie) { + htcap_tmp = READ_16L(ht_cap_ie + sizeof(unsigned short)); + @@ -43199,23 +43152,13 @@ index 000000000000..b6e0dde8a4ca + } + + } else { -+ unsigned char *basic_rate_ie = NULL; -+ unsigned char *extend_rate_ie = NULL; -+ unsigned int basic_rate_ie_len = 0; -+ unsigned int extend_rate_ie_len = 0; -+ + DPRINTF(AML_DEBUG_ERROR, "%s(%d) no ht cap found, set to legacy mode.\n", __func__, __LINE__); + wnet_vif->vm_bandwidth = WIFINET_BWC_WIDTH20; + -+ basic_rate_ie = vm_get_ie(iebuf, ielen, NULL, (unsigned int *)&basic_rate_ie_len, WIFINET_ELEMID_RATES, 0); -+ extend_rate_ie = vm_get_ie(iebuf, ielen, NULL, (unsigned int *)&extend_rate_ie_len, WIFINET_ELEMID_XRATES, 0); -+ -+ if ((basic_rate_ie_len == 6) && (extend_rate_ie_len == 0)) { ++ if (rate_count == 4) { + wnet_vif->vm_mac_mode = WIFINET_MODE_11B; -+ -+ } else if ((basic_rate_ie_len == 10) && (extend_rate_ie_len == 6)) { ++ } else if (rate_count == 12) { + wnet_vif->vm_mac_mode = WIFINET_MODE_11BG; -+ + } else { + wnet_vif->vm_mac_mode = WIFINET_MODE_11G; + } @@ -43312,7 +43255,7 @@ index 000000000000..b6e0dde8a4ca + __func__,__LINE__,vht_op_ie_len, pri_chan, vht_op_ie->vht_op_ch_freq_seg1); + + /*bandwidth/mode/channel offset*/ -+ printk("%s(%d):chan %d, cntr_seg1 %d\n", __func__, __LINE__, pri_chan, vht_op_ie->vht_op_ch_freq_seg1); ++ pr_debug("%s(%d):chan %d, cntr_seg1 %d\n", __func__, __LINE__, pri_chan, vht_op_ie->vht_op_ch_freq_seg1); + center_chan = vht_op_ie->vht_op_ch_freq_seg1; + if (vht_op_ie->vht_op_chwidth == VHT_OPT_CHN_WD_80M) { + wnet_vif->vm_bandwidth = WIFINET_BWC_WIDTH80; @@ -43334,7 +43277,7 @@ index 000000000000..b6e0dde8a4ca + } + } + wnet_vif->vm_mainsta->sta_bssmode = wnet_vif->vm_mac_mode; -+ printk("%s vm_mac_mode %d, offset %d, vm_bandwidth:%d, center_chan:%d\n", __func__, ++ pr_debug("%s vm_mac_mode %d, offset %d, vm_bandwidth:%d, center_chan:%d\n", __func__, + wnet_vif->vm_mac_mode, wnet_vif->scnd_chn_offset, wnet_vif->vm_bandwidth, center_chan); + +#ifdef CONFIG_P2P @@ -43369,19 +43312,17 @@ index 000000000000..b6e0dde8a4ca + } +#endif +#endif /*#ifdef CONFIG_P2P*/ -+ + /*Forcely refresh */ + if (IS_APSTA_CONCURRENT(aml_wifi_get_con_mode()) && concurrent_set_channel) + { + struct wlan_net_vif *main_wnet_vif = wifi_mac_running_main_wnet_vif(wifimac); + if (main_wnet_vif != NULL) { + /*sta connect to 5G ap, softap need update channel/band/mac_mode as sta*/ -+ wnet_vif->vm_curchan = main_vmac_chan; + wnet_vif->vm_bandwidth = main_vmac_chan->chan_bw; + wnet_vif->vm_mac_mode = main_wnet_vif->vm_mac_mode; + wnet_vif->vm_mainsta->sta_bssmode = main_wnet_vif->vm_mac_mode; + -+ if (wnet_vif->vm_curchan->chan_bw >= WIFINET_BWC_WIDTH40) { ++ if (main_vmac_chan->chan_bw >= WIFINET_BWC_WIDTH40) { + wnet_vif->vm_htcap |= WIFINET_HTCAP_SUPPORTCBW40; + } + @@ -43389,20 +43330,35 @@ index 000000000000..b6e0dde8a4ca + wnet_vif->scnd_chn_offset = WIFINET_HTINFO_EXTOFFSET_ABOVE; + } else if (main_vmac_chan->chan_pri_num > wifi_mac_Mhz2ieee(main_vmac_chan->chan_cfreq1, 0)) { + wnet_vif->scnd_chn_offset = WIFINET_HTINFO_EXTOFFSET_BELOW; -+ } else{ ++ } else { + wnet_vif->scnd_chn_offset = WIFINET_HTINFO_EXTOFFSET_NA; + } -+ wifi_mac_set_wnet_vif_channel(wnet_vif, main_vmac_chan->chan_pri_num, main_vmac_chan->chan_bw, wifi_mac_Mhz2ieee(main_vmac_chan->chan_cfreq1, 0)); -+ DPRINTF(AML_DEBUG_CFG80211|AML_DEBUG_ERROR, "set ap %s(%d) chan %d, mac mode %d, band %d\n",__func__,__LINE__, -+ wnet_vif->vm_curchan->chan_pri_num, wnet_vif->vm_mac_mode, wnet_vif->vm_bandwidth); ++ ++ pri_chan = main_vmac_chan->chan_pri_num; ++ center_chan = wifi_mac_Mhz2ieee(main_vmac_chan->chan_cfreq1, 0); + } ++ } ++ ++ if (wnet_vif->vm_state == WIFINET_S_CONNECTED) { ++ struct wifi_channel *switch_chan = NULL; ++ ++ switch_chan = wifi_mac_find_chan(wifimac, pri_chan, wnet_vif->vm_bandwidth, center_chan); ++ channel_switch_announce_trigger(wifimac, switch_chan); + } else { -+ /*find channel info from channel list by primary channel & bandwidth & center channel */ -+ if (!wifi_mac_set_wnet_vif_channel(wnet_vif, pri_chan, wnet_vif->vm_bandwidth, center_chan)) { ++ struct wifi_channel *vmac_chan = wifi_mac_find_chan(wifimac, pri_chan, wnet_vif->vm_bandwidth, center_chan); ++ ++ if ((vmac_chan != WIFINET_CHAN_ERR) && vmac_chan != wnet_vif->vm_curchan) { ++ wifi_mac_add_work_task(wifimac, vm_cfg80211_chan_switch_notify_task, NULL, (SYS_TYPE)wifimac, (SYS_TYPE)wnet_vif, 0, (SYS_TYPE)vmac_chan, 0); ++ } ++ /* find channel info from channel list by primary channel & bandwidth & center channel */ ++ if (!wifi_mac_set_wnet_vif_channel(wnet_vif, pri_chan, wnet_vif->vm_bandwidth, center_chan, CHANNEL_CONNECT_FLAG | CHANNEL_RESTORE_FLAG)) { + ret = -EINVAL; + goto exit_malloc; + } + } ++ ++ DPRINTF(AML_DEBUG_CFG80211|AML_DEBUG_ERROR, "[%s]%d: current ap chan %d, mac mode %d, band %d\n",__func__,__LINE__, ++ wnet_vif->vm_curchan->chan_pri_num, wnet_vif->vm_mac_mode, wnet_vif->vm_bandwidth); + } + + { @@ -43421,10 +43377,10 @@ index 000000000000..b6e0dde8a4ca + ssidlen = ssid_ie_len - 2; + DPRINTF(AML_DEBUG_BEACON, "%s %d ssid=%s\n", __func__, __LINE__, ssid_sprintf(ssid, ssidlen)); + -+ if ((wnet_vif->vm_des_ssid[0].len != ssidlen) || (memcmp(wnet_vif->vm_des_ssid[0].ssid, ssid, ssidlen) != 0)) { ++ if (ssidlen && ((wnet_vif->vm_des_ssid[0].len != ssidlen) || (memcmp(wnet_vif->vm_des_ssid[0].ssid, ssid, ssidlen) != 0))) { + WIFINET_BEACON_LOCK(wifimac); + memset(wnet_vif->vm_des_ssid, 0, IV_SSID_SCAN_AMOUNT*sizeof(struct wifi_mac_ScanSSID)); -+ wnet_vif->vm_des_ssid[0].len= ssidlen; ++ wnet_vif->vm_des_ssid[0].len = ssidlen; + memcpy(wnet_vif->vm_des_ssid[0].ssid, ssid, ssidlen); + wnet_vif->vm_des_nssid = 1; + WIFINET_BEACON_UNLOCK(wifimac); @@ -43441,6 +43397,8 @@ index 000000000000..b6e0dde8a4ca + unsigned int rsnielen = 0; + struct wifi_mac_Rsnparms *vm_rsn = &(sta->sta_rsn); + unsigned int flags = 0; ++ unsigned char *rsnxe_ie = NULL; ++ unsigned int rsnxe_ie_len = 0; + + memset(&wparsn, 0, sizeof(struct wifi_mac_Rsnparms)); + memset(vm_rsn, 0, sizeof(struct wifi_mac_Rsnparms)); @@ -43453,6 +43411,15 @@ index 000000000000..b6e0dde8a4ca + __func__, __LINE__, wparsn.rsn_mcastcipher, wparsn.rsn_ucastcipherset, wparsn.rsn_keymgmtset, wparsn.rsn_caps); + } + ++ rsnxe_ie = vm_get_ie(iebuf, ielen, NULL, (unsigned int *)&rsnxe_ie_len, WIFINET_ELEMID_RSNX, 0); ++ if (rsnxe_ie) { ++ if (rsnxe_ie[2] & BIT(5)) { ++ wnet_vif->vm_flags |= WIFINET_F_H2E; ++ AML_OUTPUT("sap support h2e\n"); ++ } ++ ++ } ++ + rsnie = (const struct wifi_mac_ie_rsn *)vm_get_ie(iebuf, ielen, NULL, (unsigned int *)&rsnielen, WIFINET_ELEMID_RSN, 0); + if (rsnie && rsnielen) { + if (wifi_mac_parse_own_rsn(sta, (unsigned char *)rsnie)) { @@ -43461,7 +43428,7 @@ index 000000000000..b6e0dde8a4ca + + if (vm_rsn->rsn_caps & MFP_MASK) { + sta->sta_flags_ext |= WIFINET_NODE_MFP; -+ printk("%s disable hw mgmt decrypt\n", __func__); ++ pr_debug("%s disable hw mgmt decrypt\n", __func__); + wifi_mac_disable_hw_mgmt_decrypt(); + } + @@ -43559,7 +43526,7 @@ index 000000000000..b6e0dde8a4ca + struct wifi_mac_wme_state *wme = &wnet_vif->vm_wmac->wm_wme[wnet_vif->wnet_vif_id]; + DPRINTF(AML_DEBUG_BEACON, "%s %d found wmmie=%p wmmielen=%d\n", + __func__, __LINE__, wmmie, wmmielen); -+ // dump_memory_internel(wmmie,wmmielen); ++ // dump_memory_internal(wmmie,wmmielen); + if (wifimac->wm_caps & WIFINET_C_UAPSD) + { + WIFINET_BEACON_LOCK(wifimac); @@ -43640,7 +43607,7 @@ index 000000000000..b6e0dde8a4ca + } + } + -+ printk("%s set_beacon_flag %d, wm_flags_ext:%08x, wm_flags:%08x, sta_vhtcap:%08x\n", __func__, ++ pr_debug("%s set_beacon_flag %d, wm_flags_ext:%08x, wm_flags:%08x, sta_vhtcap:%08x\n", __func__, + set_beacon_flag, wifimac->wm_flags_ext, wifimac->wm_flags, sta->sta_vhtcap); + + if (set_beacon_flag) @@ -43679,7 +43646,7 @@ index 000000000000..b6e0dde8a4ca + settings->hidden_ssid, settings->auth_type); + + if (settings->chandef.chan) { -+ printk("chandef center_freq:%d, hw_value:%d band:%d, at %s, %d\n", ++ pr_debug("chandef center_freq:%d, hw_value:%d band:%d, at %s, %d\n", + settings->chandef.chan->center_freq, settings->chandef.chan->hw_value, + settings->chandef.chan->band, __func__, __LINE__); + if (wifi_mac_if_dfs_channel(wifimac, (int)settings->chandef.chan->hw_value) == 1) { @@ -43696,6 +43663,7 @@ index 000000000000..b6e0dde8a4ca + else + wnet_vif->vm_flags &= ~WIFINET_F_HIDESSID; + ++ wnet_vif->vm_p2p->go_hidden_mode = (wnet_vif->vm_flags & WIFINET_F_HIDESSID) >> WIFINET_F_HIDESSID_TO_BIT0_OFST; + ret = _iv_cfg80211_add_set_beacon(wiphy, ndev, &settings->beacon,settings->dtim_period) ; + tasklet_init(&drv_priv->forward_tasklet, drv_forward_tasklet, (unsigned long)(SYS_TYPE)wnet_vif); + WIFINET_SAVEQ_INIT(&(wnet_vif->vm_forward_buffer_queue), "wnet_vif_forward_buffer_queue"); @@ -43730,14 +43698,18 @@ index 000000000000..b6e0dde8a4ca + struct net_device *ndev, struct cfg80211_beacon_data *info) +#endif +{ -+ int ret = 0; ++ int ret = 0, time_delay = 0; + struct wlan_net_vif *wnet_vif = wiphy_to_adapter(wiphy); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,7,0) + struct cfg80211_beacon_data *info = &ap_update->beacon; +#endif + -+ DPRINTF(AML_DEBUG_CFG80211, " %s(%d): <%s>\n", __func__, __LINE__, ndev->name); ++ while ((wnet_vif->vm_wmac->wm_flags & WIFINET_F_CHANSWITCH) && (time_delay < 1000)) { ++ msleep(10); ++ time_delay += 10; ++ } + ++ DPRINTF(AML_DEBUG_CFG80211, " %s(%d): <%s>\n", __func__, __LINE__, ndev->name); + ret = _iv_cfg80211_add_set_beacon(wiphy, ndev, info,wnet_vif->vm_dtim_period); + + return ret; @@ -44062,7 +44034,7 @@ index 000000000000..b6e0dde8a4ca + struct wiphy *wiphy, struct net_device *ndev, + int idx, unsigned char *mac, struct station_info *sinfo) +{ -+ //DPRINTF(AML_DEBUG_CFG80211, "%s %d <%s>\n", __func__, __LINE__, ndev->name); ++ DPRINTF(AML_DEBUG_CFG80211, "%s %d <%s>\n", __func__, __LINE__, ndev->name); + return -ENOENT; +} + @@ -44110,13 +44082,13 @@ index 000000000000..b6e0dde8a4ca + if (temp_vif->wnet_vif_id == 1 && temp_vif->remain_on_channel) + { + vm_p2p_cancel_remain_channel(temp_vif->vm_p2p); -+ printk("remain_on_channel: <%s> line 4498\n",temp_vif->vm_ndev->name); ++ pr_debug("remain_on_channel: <%s> line 4498\n",temp_vif->vm_ndev->name); + temp_vif->remain_on_channel = 0; + } + else if (temp_vif->wnet_vif_id == 0 && temp_vif->remain_on_channel) + { + vm_cancel_remain_channel(temp_vif); -+ printk("remain_on_channel: <%s> line 4504\n",temp_vif->vm_ndev->name); ++ pr_debug("remain_on_channel: <%s> line 4504\n",temp_vif->vm_ndev->name); + temp_vif->remain_on_channel = 0; + } + } @@ -44173,7 +44145,7 @@ index 000000000000..b6e0dde8a4ca + } else { + wifi_mac_ChangeChannel(wifimac, p2p->work_channel, 0, wnet_vif->wnet_vif_id, wnet_vif->vm_opmode); + } -+ printk("p2p_case: duration %d\n", restore_duration * 100); ++ pr_debug("p2p_case: duration %d\n", restore_duration * 100); + cfg80211_ready_on_channel(p2p->wnet_vif->vm_wdev, *cookie, channel, + vm_p2p_discover_listen(p2p, target_channel, restore_duration * 100), GFP_KERNEL); + @@ -44286,11 +44258,24 @@ index 000000000000..b6e0dde8a4ca + struct wifi_mac *wifimac = wnet_vif->vm_wmac; + struct wifi_channel *main_vmac_chan = NULL; + unsigned char *p2p_noa; ++ bool is_dpp_frame = false; ++ + dev = wnet_vif->vm_ndev; + -+ //if (wnet_vif->vm_curchan && (channel != wnet_vif->vm_curchan->chan_pri_num)) { -+ //channel = wnet_vif->vm_curchan->chan_pri_num; -+ //} ++ if (WIFINET_IS_ACTION(wh)) { ++ p2p_pub_act = (struct wifi_mac_p2p_pub_act_frame *)((unsigned char *)data + sizeof(struct wifi_frame)); ++ p2p_act = (struct wifi_mac_p2p_action_frame *)((unsigned char *)data + sizeof(struct wifi_frame)); ++ pub_gas_act = (struct wifi_mac_pub_gas_act_frame *)((unsigned char *)data + sizeof(struct wifi_frame)); ++ if ((p2p_pub_act->category == AML_CATEGORY_PUBLIC) && (p2p_pub_act->action == WIFINET_ACT_PUBLIC_P2P) ++ && (p2p_pub_act->oui_type == OUI_TYPE_DPP)) { ++ is_dpp_frame = true; ++ } ++ } ++ ++ if (wnet_vif->vm_curchan && (channel != wnet_vif->vm_curchan->chan_pri_num) && !is_dpp_frame) { ++ AML_OUTPUT("channel_num:%d, vm_curchan->chan_pri_num:%d, frame_type:0x%x\n", channel, wnet_vif->vm_curchan->chan_pri_num, *((unsigned short *)wh->i_fc)); ++ channel = wnet_vif->vm_curchan->chan_pri_num; ++ } + + if (channel <= CFG_CH_MAX_2G_CHANNEL) + band = wdev->wiphy->bands[IEEE80211_BAND_2GHZ]; @@ -44381,7 +44366,7 @@ index 000000000000..b6e0dde8a4ca + && (*((char*)data + sizeof(struct wifi_frame) + 11) == 0x9a) + && (*((char*)data + sizeof(struct wifi_frame) + 12) == 0x1a) + && (*((char*)data + sizeof(struct wifi_frame) + 13) == 0x01)) { -+ printk("[DPP Configuration]\n"); ++ pr_debug("[DPP Configuration]\n"); + } + switch (pub_gas_act->action) + { @@ -44471,7 +44456,7 @@ index 000000000000..b6e0dde8a4ca + p2p_pub_act = (struct wifi_mac_p2p_pub_act_frame *)(params->buf + sizeof(struct wifi_frame)); + if (wnet_vif->vm_opmode != WIFINET_M_HOSTAP && wnet_vif->vm_state == WIFINET_S_CONNECTED) { + if (is_need_process_p2p_action((unsigned char*)params->buf)) { -+ printk("%s, Need to send action frame in the connected state, params->len=%d\n", __func__, params->len); ++ pr_debug("%s, Need to send action frame in the connected state, params->len=%d\n", __func__, params->len); + } else { + return 0;//no need to send mgmt after connected,if so, disconnect first + } @@ -44546,7 +44531,11 @@ index 000000000000..b6e0dde8a4ca + p2p->need_restore_bsschan = REASON_RESOTRE_BSSCHAN_TXMGNT; + wifi_mac_scan_notify_leave_or_back(wnet_vif, 1); + p2p->p2p_flag |= P2P_WAIT_SWITCH_CHANNEL; -+ ++ while (p2p->p2p_flag & P2P_WAIT_SWITCH_CHANNEL) { ++ msleep(1); ++ AML_OUTPUT("p2p->work_channel->chan_pri_num:%d, wifimac->wm_curchan->chan_pri_num:%d\n", ++ p2p->work_channel->chan_pri_num, wifimac->wm_curchan->chan_pri_num); ++ } + } else { + wifi_mac_ChangeChannel(wifimac, p2p->work_channel, 0, wnet_vif->wnet_vif_id, wnet_vif->vm_opmode); + } @@ -44629,17 +44618,25 @@ index 000000000000..b6e0dde8a4ca +#ifdef CTS_VERIFIER_GAS + if (p2p_pub_act->action == WIFINET_ACT_PUBLIC_GAS_REQ) { + wnet_vif->vm_p2p->p2p_flag &= (~P2P_GAS_RSP); -+ while (p2p->tx_status_flag != WIFINET_TX_STATUS_SUCC -+ && p2p->act_pkt_retry_count < DEFAULT_P2P_ACTION_RETRY_TIMES -+ && !(wnet_vif->vm_p2p->p2p_flag & P2P_GAS_RSP)) { -+ mdelay(20); -+ } + } +#endif ++ do { ++ msleep(5); ++ if ((p2p_pub_act->action == WIFINET_ACT_PUBLIC_GAS_REQ) ++ && (wnet_vif->vm_p2p->p2p_flag & P2P_GAS_RSP)) { ++ break; ++ } ++ } while (p2p->tx_status_flag != WIFINET_TX_STATUS_SUCC ++ && p2p->act_pkt_retry_count <= DEFAULT_P2P_ACTION_RETRY_TIMES ++ && !p2p->send_tx_status_flag); ++ ++ if (p2p->tx_status_flag != WIFINET_TX_STATUS_SUCC) { ++ ack = false; ++ } + chan_dbg(wifimac->wm_curchan, "X9", 4509); + +exit: -+ DPRINTF(AML_DEBUG_CFG80211,"%s %d, ack=%d\n", __func__,__LINE__, ack ); ++ DPRINTF(AML_DEBUG_CFG80211,"%s %d, ack=%d\n", __func__,__LINE__, ack); + cfg80211_mgmt_tx_status(p2p->wnet_vif->vm_wdev, *cookie, params->buf, params->len, ack, GFP_KERNEL); + return ret; +} @@ -44659,9 +44656,16 @@ index 000000000000..b6e0dde8a4ca + struct wifi_channel *auth_channel; + unsigned short seq = 0; + struct wifi_mac_pub_gas_act_frame *pub_gas_act = NULL; ++ unsigned int status = 0; ++ struct wifi_mac_p2p_pub_act_frame *p2p_pub_act = NULL; ++ struct wifi_mac_p2p *p2p = wiphy_to_p2p(wiphy); ++ unsigned int delay = 0; ++ unsigned int total_delay = 0; + + wh = (const struct wifi_frame*)params->buf; + pub_gas_act = (struct wifi_mac_pub_gas_act_frame *)(params->buf + sizeof(struct wifi_frame)); ++ p2p_pub_act = (struct wifi_mac_p2p_pub_act_frame *)((unsigned char *)params->buf + sizeof(struct wifi_frame)); ++ + DPRINTF(AML_DEBUG_CFG80211, "<%s>: %s:addr2 %s dev_addr %s\n", + ndev->name, __func__, ether_sprintf(wh->i_addr2), ether_sprintf(ndev->dev_addr)); + @@ -44672,11 +44676,37 @@ index 000000000000..b6e0dde8a4ca + auth_alg = AML_GET_LE16((unsigned char *)wh + sizeof(struct wifi_frame)); + seq = AML_GET_LE16((unsigned char *)wh + sizeof(struct wifi_frame) + 2); + ++ status = AML_GET_LE16((unsigned char *)wh + sizeof(struct wifi_frame) + 4); ++ ++ if ((status == WIFINET_STATUS_SAE_H2E) && (wnet_vif->vm_mainsta->sta_use_h2e == WIFINET_H2E_PEER_SUPPOR) ++ && (wnet_vif->vm_opmode == WIFINET_M_STA)) { ++ AML_OUTPUT("set h2e valid\n"); ++ wnet_vif->vm_mainsta->sta_use_h2e = WIFINET_H2E_VALID; ++ } ++ + if ((auth_alg != WLAN_AUTH_SAE) || (wnet_vif->vm_mainsta->sta_authmode != WIFINET_AUTH_SAE)) + goto exit; + -+ DPRINTF(AML_DEBUG_ANY,"auth_alg=%d, seq:%04x, status:%d\n", auth_alg, -+ seq, AML_GET_LE16((unsigned char *)wh + sizeof(struct wifi_frame) + 4)); ++ DPRINTF(AML_DEBUG_ANY,"auth_alg=%d, seq:%04x, status:%d\n", ++ auth_alg, seq, AML_GET_LE16((unsigned char *)wh + sizeof(struct wifi_frame) + 4)); ++ } ++ ++ if (params->len <= P2P_MAX_ACTION_LEN) { ++ p2p->cookie = *cookie; ++ p2p->action_pkt_len = params->len; ++ p2p->raw_action_pkt_len = params->len; ++ p2p->action_dialog_token = p2p_pub_act->dialog_token; ++ p2p->act_pkt_retry_count = 0; ++ p2p->tx_status_flag = WIFINET_TX_STATUS_NOSET; ++ p2p->send_tx_status_flag = 0; ++ memset(p2p->action_pkt, 0, P2P_MAX_ACTION_LEN); ++ memcpy(p2p->action_pkt, params->buf, params->len); ++ memset(p2p->raw_action_pkt, 0, P2P_MAX_ACTION_LEN); ++ memcpy(p2p->raw_action_pkt, params->buf, params->len); ++ ++ if (wnet_vif->vm_flags_ext2 & WIFINET_FEXT2_DPP_CONNECTION_STATUS_RETRY) { ++ wnet_vif->vm_flags_ext2 &= ~WIFINET_FEXT2_DPP_CONNECTION_STATUS_RETRY; ++ } + } + + os_timer_ex_cancel(&wnet_vif->vm_mgtsend, CANCEL_SLEEP); @@ -44693,7 +44723,6 @@ index 000000000000..b6e0dde8a4ca + center_chan = target_channel - 2; + else + center_chan = target_channel; -+ + } else if (wnet_vif->vm_bandwidth == WIFINET_BWC_WIDTH80) { + center_chan = target_channel + (wifimac->wm_curchan->chan_pri_num + - wifi_mac_Mhz2ieee(wifimac->wm_curchan->chan_cfreq1, 0)); @@ -44703,13 +44732,54 @@ index 000000000000..b6e0dde8a4ca + if (auth_channel == NULL) { + auth_channel = wifi_mac_find_chan(wifimac, target_channel, WIFINET_BWC_WIDTH20, target_channel); + } -+ wifi_mac_ChangeChannel(wifimac, auth_channel, 0, wnet_vif->wnet_vif_id, wnet_vif->vm_opmode); -+ + } else { + auth_channel = wifimac->wm_curchan; + } + } + ++ if (p2p_pub_act && (p2p_pub_act->category == AML_CATEGORY_PUBLIC)) { ++ if ((p2p_pub_act->action == WIFINET_ACT_PUBLIC_P2P && p2p_pub_act->oui_type == OUI_TYPE_DPP)) { ++ unsigned char dpp_action_subtype = *((char*)wh + sizeof(struct wifi_frame) + 7); ++ p2p->action_chan = auth_channel; ++ if ((wifi_mac_is_wm_running(wifimac) == true) ++ && wnet_vif->vm_curchan ++ && (auth_channel != wifimac->wm_curchan) ++ && (params->len <= P2P_MAX_ACTION_LEN)) { ++ wifi_mac_scan_notify_leave_or_back(wnet_vif, 1); ++ while ((!wifimac->drv_priv->hal_priv->hal_ops.hal_tx_empty()) && total_delay < 500) { ++ msleep(10); ++ total_delay += 10; ++ } ++ AML_OUTPUT("dpp wait pkt clear, total_delay:%d(ms)\n", total_delay); ++ } ++ wnet_vif->vm_flags_ext2 |= WIFINET_FEXT2_DPP_SEND; ++ if (dpp_action_subtype < 19) { ++ AML_OUTPUT("DPP->%s flags:0x%x\n", dpp_pub_action_str[dpp_action_subtype], wnet_vif->vm_flags_ext2); ++ } else { ++ AML_OUTPUT("subtype:%d\n", dpp_action_subtype); ++ } ++ } else if (((p2p_pub_act->action == WIFINET_ACT_PUBLIC_GAS_REQ) || (p2p_pub_act->action == WIFINET_ACT_PUBLIC_GAS_RSP))) { ++ p2p->action_chan = auth_channel; ++ if ((wifi_mac_is_wm_running(wifimac) == true) ++ && wnet_vif->vm_curchan ++ && (auth_channel != wifimac->wm_curchan) ++ && (params->len <= P2P_MAX_ACTION_LEN)) { ++ wifi_mac_scan_notify_leave_or_back(wnet_vif, 1); ++ while ((!wifimac->drv_priv->hal_priv->hal_ops.hal_tx_empty()) && total_delay < 500) { ++ msleep(10); ++ total_delay += 10; ++ } ++ AML_OUTPUT("gas wait pkt clear total_delay:%d ms\n", total_delay); ++ } ++ wnet_vif->vm_flags_ext2 |= WIFINET_FEXT2_DPP_SEND; ++ } ++ } ++ ++ if (auth_channel != wifimac->wm_curchan) { ++ wnet_vif->vm_flags_ext2 |= WIFINET_FEXT2_MGMT_RESTORE_CHANNEL; ++ wifi_mac_ChangeChannel(wifimac, auth_channel, 0, wnet_vif->wnet_vif_id, wnet_vif->vm_opmode); ++ } ++ + switch (pub_gas_act->action) + { + case WIFINET_ACT_PUBLIC_GAS_REQ: @@ -44726,9 +44796,22 @@ index 000000000000..b6e0dde8a4ca + goto exit; + } + ++ while ((wnet_vif->vm_flags_ext2 & WIFINET_FEXT2_DPP_SEND) && (delay < 500)) { ++ msleep(20); ++ delay += 20; ++ } ++ ++ if (wnet_vif->vm_flags_ext2 & WIFINET_FEXT2_DPP_SEND) { ++ wnet_vif->vm_flags_ext2 &= ~WIFINET_FEXT2_DPP_SEND; ++ } ++ ++ AML_OUTPUT("delay:%d ms, tx_status:%d\n", delay, wnet_vif->vm_p2p->send_tx_status_flag); ++ +exit: -+ DPRINTF(AML_DEBUG_CFG80211,"%s %d, ack=%d\n", __func__,__LINE__, ack ); -+ cfg80211_mgmt_tx_status(wnet_vif->vm_wdev, *cookie, params->buf, params->len, ack, GFP_KERNEL); ++ DPRINTF(AML_DEBUG_CFG80211,"%s %d, ack=%d\n", __func__,__LINE__, ack); ++ if (!wnet_vif->vm_p2p->send_tx_status_flag) { ++ cfg80211_mgmt_tx_status(wnet_vif->vm_wdev, *cookie, params->buf, params->len, ack, GFP_KERNEL); ++ } + return ret; +} + @@ -44746,7 +44829,7 @@ index 000000000000..b6e0dde8a4ca + ret = vm_cfg80211_mgmt_tx_sta(wiphy, wdev, params, cookie); + } + } -+ printk("vm_cfg80211_mgmt_tx: opmode %d, p2p_support %d, ret %d\n", wnet_vif->vm_opmode, wnet_vif->vm_p2p_support, ret); ++ pr_debug("vm_cfg80211_mgmt_tx: opmode %d, p2p_support %d, ret %d\n", wnet_vif->vm_opmode, wnet_vif->vm_p2p_support, ret); + + return ret; +} @@ -44795,7 +44878,7 @@ index 000000000000..b6e0dde8a4ca + wmep->wmep_logcwmin = WME_PARAM_LOGCWMAX_GET(params->cwmax); + wmep->wmep_txopLimit = params->txop; + -+ printk("%s(%d) aifs:%d, cwmax:%d, cwmin:%d, txop_lmt:%d\n", __func__, __LINE__, ++ pr_debug("%s(%d) aifs:%d, cwmax:%d, cwmin:%d, txop_lmt:%d\n", __func__, __LINE__, + wmep->wmep_aifsn, wmep->wmep_logcwmax, wmep->wmep_logcwmin, wmep->wmep_txopLimit); + + wme_update_ex(wifimac,wnet_vif); @@ -44823,7 +44906,7 @@ index 000000000000..b6e0dde8a4ca + struct wlan_net_vif *wnet_vif = NULL; + struct wifi_mac *wifimac = NULL; + struct wifi_channel *temp_chan = NULL; -+ printk("enter %s, no support yet\n", __func__); ++ pr_debug("enter %s, no support yet\n", __func__); + return -1; + if (!chandef || !wiphy) { + ERROR_DEBUG_OUT("chandef or wiphy null\n"); @@ -44848,7 +44931,7 @@ index 000000000000..b6e0dde8a4ca + } + if (temp_chan) { + if (chandef->chan) { -+ printk("enter %s, %d\n", __func__, __LINE__); ++ pr_debug("enter %s, %d\n", __func__, __LINE__); + } else { + ERROR_DEBUG_OUT("chandef->chan null \n"); + } @@ -44898,8 +44981,8 @@ index 000000000000..b6e0dde8a4ca + struct wlan_net_vif *wnet_vif = wiphy_to_adapter(wiphy); + struct wifi_mac *wifimac = wnet_vif->vm_wmac; + -+ printk("enter %s\n", __func__); -+ printk("---wiphy addr: 0x%p\n", wiphy); ++ pr_debug("enter %s\n", __func__); ++ pr_debug("---wiphy addr: 0x%p\n", wiphy); + + if (noack_map & BE_MAP) + wifimac->drv_priv->drv_txlist_table[HAL_WME_AC_BE].noack_flag = 1; @@ -44922,7 +45005,7 @@ index 000000000000..b6e0dde8a4ca + struct vm_wdev_priv *pwdev_priv = wdev_to_priv(wdev); + struct wifi_mac_p2p *p2p = &pwdev_priv->p2p; + -+ printk("%s(%d) \n", __func__, __LINE__); ++ pr_debug("%s(%d) \n", __func__, __LINE__); + if (!vm_p2p_enabled(p2p)) + { + vm_p2p_up(wnet_vif); @@ -44942,7 +45025,7 @@ index 000000000000..b6e0dde8a4ca + struct vm_wdev_priv *pwdev_priv = wdev_to_priv(wdev); + struct wifi_mac_p2p *p2p = &pwdev_priv->p2p; + -+ printk("enter %s\n", __func__); ++ pr_debug("enter %s\n", __func__); + if (vm_p2p_enabled(p2p)) + vm_p2p_down(wnet_vif); + wifi_mac_top_sm(wnet_vif, WIFINET_S_INIT,0); @@ -44962,7 +45045,7 @@ index 000000000000..b6e0dde8a4ca +vm_cfg80211_start_radar_detection(struct wiphy *wiphy, struct net_device *dev, + struct cfg80211_chan_def *chandef, unsigned int cac_time_ms) +{ -+ printk("no support yet %s\n", __func__); ++ pr_debug("no support yet %s\n", __func__); + return -1; +} +#endif @@ -44998,8 +45081,8 @@ index 000000000000..b6e0dde8a4ca + struct wlan_net_vif *wnet_vif = wiphy_to_adapter(wiphy); + struct wifi_mac *wifimac = wnet_vif->vm_wmac; + -+ printk("- %s %d\n",__func__,__LINE__); -+ printk("----auth_type:%d\n", req->auth_type); ++ pr_debug("- %s %d\n",__func__,__LINE__); ++ pr_debug("----auth_type:%d\n", req->auth_type); + switch (req->auth_type) + { + case NL80211_AUTHTYPE_OPEN_SYSTEM: @@ -45025,11 +45108,11 @@ index 000000000000..b6e0dde8a4ca + auth_value = WIFINET_AUTH_AUTO; + break; + default: -+ printk(" %s %d, unknown auth type\n",__func__,__LINE__); ++ pr_err(" %s %d, unknown auth type\n",__func__,__LINE__); + break; + } + wnet_vif->vm_mainsta->sta_authmode = auth_value; -+ printk("----sta_authmode:%d\n", wnet_vif->vm_mainsta->sta_authmode); ++ pr_debug("----sta_authmode:%d\n", wnet_vif->vm_mainsta->sta_authmode); + + return rc; +} @@ -45053,7 +45136,7 @@ index 000000000000..b6e0dde8a4ca + ERROR_DEBUG_OUT("chandef is null at\n"); + return -1; + } -+ printk("---enter %s\n", __func__); ++ pr_debug("---enter %s\n", __func__); + chan_dbg(wnet_vif->vm_wmac->wm_curchan, "x4", 4863); + return 0; +} @@ -45064,26 +45147,26 @@ index 000000000000..b6e0dde8a4ca +{ + struct wlan_net_vif *wnet_vif = wiphy_to_adapter(wiphy); + -+ printk("---enter %s\n", __func__); ++ pr_debug("---enter %s\n", __func__); + wnet_vif->vm_wmac->drv_priv->drv_config.cqm_rssi_thold = rssi_thold; + wnet_vif->vm_wmac->drv_priv->drv_config.cqm_rssi_hyst = rssi_hyst; -+ printk("---rssi_thold:%d, rssi_hyst:%d\n", rssi_thold, rssi_hyst); ++ pr_debug("---rssi_thold:%d, rssi_hyst:%d\n", rssi_thold, rssi_hyst); + + return 0; +} + +#if (KERNEL_VERSION(4, 17, 0) <= LINUX_VERSION_CODE) || (defined WPA3_PATCH) -+int vm_cfg80211_external_auth(struct wiphy *wiphy, struct net_device *dev, ++static int vm_cfg80211_external_auth(struct wiphy *wiphy, struct net_device *dev, + struct cfg80211_external_auth_params *params) +{ + struct wlan_net_vif *wnet_vif = wiphy_to_adapter(wiphy); + struct wifi_station *sta; + -+ printk("%s vid:%d, action:%d, status:%d\n", __func__, wnet_vif->wnet_vif_id, params->action, params->status); ++ pr_debug("%s vid:%d, action:%d, status:%d\n", __func__, wnet_vif->wnet_vif_id, params->action, params->status); + if (params->status == WLAN_STATUS_SUCCESS) { -+ printk("bssid: "MAC_FMT"", MAC_ARG(params->bssid)); -+ printk("SSID: [%s]\n", ((params->ssid.ssid_len == 0) ? "" : (char *)params->ssid.ssid)); -+ printk("suite: 0x%08x\n", params->key_mgmt_suite); ++ pr_debug("bssid: "MAC_FMT"", MAC_ARG(params->bssid)); ++ pr_debug("SSID: [%s]\n", ((params->ssid.ssid_len == 0) ? "" : (char *)params->ssid.ssid)); ++ pr_debug("suite: 0x%08x\n", params->key_mgmt_suite); + + if (wnet_vif->vm_opmode == WIFINET_M_STA) { + wifi_mac_top_sm(wnet_vif, WIFINET_S_ASSOC, 0); @@ -45091,7 +45174,7 @@ index 000000000000..b6e0dde8a4ca + } else { + sta = wifi_mac_get_sta(&wnet_vif->vm_sta_tbl, params->bssid, wnet_vif->wnet_vif_id); + if (sta != NULL) { -+ printk("auth sta:%p\n", sta); ++ pr_debug("auth sta:%p\n", sta); + wifi_mac_sta_auth(sta); + } + } @@ -45177,7 +45260,7 @@ index 000000000000..b6e0dde8a4ca +*/ +static void vm_cfg80211_init_vht_capab(struct ieee80211_sta_vht_cap *vht_cap, enum ieee80211_band band) +{ -+ printk("%s(%d)\n",__func__,__LINE__); ++ pr_debug("%s(%d)\n",__func__,__LINE__); + + vht_cap->vht_supported = true; + #if 0 /*Original added from RTL view, interpreted into kernel language*/ @@ -45219,7 +45302,7 @@ index 000000000000..b6e0dde8a4ca + +static void vm_cfg80211_init_ht_capab(struct ieee80211_sta_ht_cap *ht_cap, enum ieee80211_band band) +{ -+ printk("%s(%d)\n",__func__,__LINE__); ++ pr_debug("%s(%d)\n",__func__,__LINE__); + + ht_cap->ht_supported = true; + @@ -45290,7 +45373,7 @@ index 000000000000..b6e0dde8a4ca +char *rssi_result_path = "/lib/firmware/w1/rssi.tx"; +char *reg_result_path = "/lib/firmware/w1/reg.txt"; + -+void record_reg_value(unsigned int address, unsigned int value) ++static void record_reg_value(unsigned int address, unsigned int value) +{ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) + struct kstat stat; @@ -45378,18 +45461,21 @@ index 000000000000..b6e0dde8a4ca + unsigned int reg = 0; + unsigned int efuse_data = 0; + ++ if (!data) ++ return -EINVAL; ++ + vnd_cmd = (struct statistic_cmd *)data; + opt_data = (unsigned char *)data; + vnd_if = (union vendor_if *)data; + -+ printk("%s cmd 0x%x, addr 0x%x, data 0x%x\n", __func__, ++ pr_debug("%s cmd 0x%x, addr 0x%x, data 0x%x\n", __func__, + (vnd_if->vnd_reg_cmd.cmd), ntohl(vnd_if->vnd_reg_cmd.addr), ntohl(vnd_if->vnd_reg_cmd.data)); + + if (data_len > 0) { + opcode = iwVendorCmd->first_eight_byte & 0x000000ff; + switch(data_len) { + case 1: -+ printk("---Aml drv: only opcode.\n"); ++ pr_debug("---Aml drv: only opcode.\n"); + break; + + case 2: @@ -45455,7 +45541,7 @@ index 000000000000..b6e0dde8a4ca + wifimac->wm_flags_ext |= WIFINET_FEXT_AMSDU; + wifi_mac_config(wifimac, CHIP_PARAM_AMSDU_ENABLE, 1); + } -+ printk("Cfg80211: Set amsdu done:%d\n",usr_data); ++ pr_debug("Cfg80211: Set amsdu done:%d\n",usr_data); + break; + + case VM_NL80211_VENDER_SUBCMD_AMPDU: @@ -45476,68 +45562,68 @@ index 000000000000..b6e0dde8a4ca + if (IS_RUNNING(netdev)) { + wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN, 0); + } -+ printk("Cfg80211: Set ampdu done:%d\n",usr_data); ++ pr_debug("Cfg80211: Set ampdu done:%d\n",usr_data); + break; + + case VM_NL80211_VENDER_SUBCMD_B2BNCTYPE: -+ printk("Cfg80211: Set encryption type done:%d\n",usr_data); ++ pr_debug("Cfg80211: Set encryption type done:%d\n",usr_data); + gB2BTestCasePacket.encryp_type = usr_data; + break; + + case VM_NL80211_VENDER_SUBCMD_B2BTKIPMIC: -+ printk("Cfg80211: Set tkip mic done:%d\n",usr_data); ++ pr_debug("Cfg80211: Set tkip mic done:%d\n",usr_data); + gB2BTestCasePacket.tkip_mic = usr_data; + break; + + case VM_NL80211_VENDER_SUBCMD_B2BTCPCSUM: -+ printk("Cfg80211: Set tcp checksum done:%d\n",usr_data); ++ pr_debug("Cfg80211: Set tcp checksum done:%d\n",usr_data); + gB2BTestCasePacket.tcpip_csum = usr_data; + break; + + case VM_NL80211_VENDER_SUBCMD_B2BPKTSNUM: -+ printk("Cfg80211: Set send packets numbers done:%d\n",usr_data); ++ pr_debug("Cfg80211: Set send packets numbers done:%d\n",usr_data); + gB2BTestCasePacket.send_frame_num = usr_data; + break; + + case VM_NL80211_VENDER_SUBCMD_B2BTESTYPE: -+ printk("Cfg80211: To be send data packets and test type :%d\n",usr_data); -+ printk("Cfg80211: Please make sure set bssid mac address as the same with dest.\n"); ++ pr_debug("Cfg80211: To be send data packets and test type :%d\n",usr_data); ++ pr_debug("Cfg80211: Please make sure set bssid mac address as the same with dest.\n"); + gB2BTestCasePacket.packet_type = usr_data; -+ printk("Cfg80211: Before calling prepare_test_hal_layer_thr_init.\n"); ++ pr_debug("Cfg80211: Before calling prepare_test_hal_layer_thr_init.\n"); + prepare_test_hal_layer_thr_init(usr_data); + break; + + case VM_NL80211_VENDER_SUBCMD_DRV_B2B_SET_LOCAL_MAC_ADDR: + memcpy(TrcConfMib.the_mac_address,vmc_tmp_addr,6); + local_mac_addr_update(); -+ printk("Cfg80211: Set local mac addr done.\n"); ++ pr_debug("Cfg80211: Set local mac addr done.\n"); + break; + + case VM_NL80211_VENDER_SUBCMD_DRV_B2B_GET_LOCAL_MAC_ADDR: -+ printk("Cfg80211: local wnet_vif addr: "MAC_FMT"\n",MAC_ARG(TrcConfMib.the_mac_address)); ++ pr_debug("Cfg80211: local wnet_vif addr: "MAC_FMT"\n",MAC_ARG(TrcConfMib.the_mac_address)); + break; + + case VM_NL80211_VENDER_SUBCMD_DRV_B2B_SET_PEER_MAC_ADDR: + memcpy(TrcConfMib.the_desc_address,vmc_tmp_addr,6); + memcpy(TrcConfMib.the_connect_address,vmc_tmp_addr,6); + dst_mac_addr_update(); -+ printk("Cfg80211: Set peer mac addr done.\n"); ++ pr_debug("Cfg80211: Set peer mac addr done.\n"); + break; + + case VM_NL80211_VENDER_SUBCMD_DRV_B2B_GET_PEER_MAC_ADDR: -+ printk("Cfg80211: dest wnet_vif addr: "MAC_FMT"\n", MAC_ARG(TrcConfMib.the_desc_address)); ++ pr_debug("Cfg80211: dest wnet_vif addr: "MAC_FMT"\n", MAC_ARG(TrcConfMib.the_desc_address)); + break; + + case VM_NL80211_VENDER_SUBCMD_DRV_B2B_SET_BSSID_MAC_ADDR: + memcpy(TrcConfMib.the_bssid,vmc_tmp_addr,6); -+ printk("Cfg80211: Set bssid mac addr done.\n"); ++ pr_debug("Cfg80211: Set bssid mac addr done.\n"); + break; + + case VM_NL80211_VENDER_SUBCMD_DRV_B2B_GET_BSSID_MAC_ADDR: -+ printk("Cfg80211: local wnet_vif addr: "MAC_FMT"\n", MAC_ARG(TrcConfMib.the_mac_address)); -+ printk("Cfg80211: dest wnet_vif addr: "MAC_FMT"\n", MAC_ARG(TrcConfMib.the_desc_address)); -+ printk("Cfg80211: connect addr: "MAC_FMT"\n", MAC_ARG(TrcConfMib.the_connect_address)); -+ printk("Cfg80211: bssid : "MAC_FMT"\n", MAC_ARG(TrcConfMib.the_bssid)); ++ pr_debug("Cfg80211: local wnet_vif addr: "MAC_FMT"\n", MAC_ARG(TrcConfMib.the_mac_address)); ++ pr_debug("Cfg80211: dest wnet_vif addr: "MAC_FMT"\n", MAC_ARG(TrcConfMib.the_desc_address)); ++ pr_debug("Cfg80211: connect addr: "MAC_FMT"\n", MAC_ARG(TrcConfMib.the_connect_address)); ++ pr_debug("Cfg80211: bssid : "MAC_FMT"\n", MAC_ARG(TrcConfMib.the_bssid)); + break; + + case VM_NL80211_VENDER_SUBCMD_DRV_B2B_SET_CHL: @@ -45549,7 +45635,7 @@ index 000000000000..b6e0dde8a4ca + hchan.pchan_num = vnd_if->vnd_chn_bw_cmd.chn; + hchan.chan_bw = vnd_if->vnd_chn_bw_cmd.bw; + -+ printk("Cfg80211: set channel to %d. bw =%d\n",vnd_if->vnd_chn_bw_cmd.chn, vnd_if->vnd_chn_bw_cmd.bw); ++ pr_debug("Cfg80211: set channel to %d. bw =%d\n",vnd_if->vnd_chn_bw_cmd.chn, vnd_if->vnd_chn_bw_cmd.bw); + + phy_set_rf_chan(&hchan, 0, wnet_vif->wnet_vif_id, wnet_vif->vm_opmode); + break; @@ -45557,7 +45643,7 @@ index 000000000000..b6e0dde8a4ca + + case VM_NL80211_VENDER_SUBCMD_DRV_B2B_PKT_LENGTH: + gB2BTestCasePacket.pkt_length = usr_data; -+ printk("Cfg80211: set pkt_len(mpdu_len) = %d uninvolved (fcs,delimiter)\n",usr_data); ++ pr_debug("Cfg80211: set pkt_len(mpdu_len) = %d uninvolved (fcs,delimiter)\n",usr_data); + break; + + case VM_NL80211_VENDER_SUBCMD_DRV_SET_SHORT_GI: @@ -45566,30 +45652,30 @@ index 000000000000..b6e0dde8a4ca + + if (1 == usr_data) { + wifimac->wm_flags_ext |= WIFINET_FEXT_SHORTGI_ENABLE; -+ printk("Cfg80211: enable short GI done"); ++ pr_debug("Cfg80211: enable short GI done"); + + } else { + wifimac->wm_flags_ext &= ~WIFINET_FEXT_SHORTGI_ENABLE; -+ printk("Cfg80211: disable short GI done.\n"); ++ pr_debug("Cfg80211: disable short GI done.\n"); + } + + if (1 == usr_data) -+ printk("Cfg80211: enable short GI done.\n"); ++ pr_debug("Cfg80211: enable short GI done.\n"); + else -+ printk("Cfg80211: disable short GI done.\n"); ++ pr_debug("Cfg80211: disable short GI done.\n"); + break; + + case VM_NL80211_VENDER_SUBCMD_B2BCHLBW: -+ printk("Cfg80211: Set channel bandwidth done:%d\n",usr_data); ++ pr_debug("Cfg80211: Set channel bandwidth done:%d\n",usr_data); + if (aml_wifi_is_enable_rf_test()) + gB2BTestCasePacket.channel_bw = usr_data; + + if (usr_data == 2) { -+ printk("\n----: 80M bw\n"); ++ pr_debug("\n----: 80M bw\n"); + } else if (usr_data == 1) { -+ printk("\n----: 40M bw\n"); ++ pr_debug("\n----: 40M bw\n"); + } else { -+ printk("\n-----: 20M bw\n"); ++ pr_debug("\n-----: 20M bw\n"); + } + break; + @@ -45605,12 +45691,12 @@ index 000000000000..b6e0dde8a4ca + } else { + reg_val = wnet_vif->vif_ops.read_word(usr_data); + } -+ printk("Drv info: Reg data=&0x%08x\n",reg_val);//do not remove me!!!!! ++ pr_debug("Drv info: Reg data=&0x%08x\n",reg_val);//do not remove me!!!!! + record_reg_value(usr_data, reg_val); + break; + + case VM_NL80211_VENDER_SUBCMD_SETREG: -+ printk("Cfg80211: Reg addr: val:0x%08x,val:0x%08x\n",usr_data,usr_data_ext); ++ pr_debug("Cfg80211: Reg addr: val:0x%08x,val:0x%08x\n",usr_data,usr_data_ext); + if (((usr_data >> 24) & 0xff) == 0xff) { +#ifdef USE_T902X_RF + rf_i2c_write( usr_data & 0x00ffffff,usr_data_ext );//access t902x rf reg @@ -45630,7 +45716,7 @@ index 000000000000..b6e0dde8a4ca + reg_val = rf_i2c_read(usr_data); +#endif + -+ printk("[I2C read]: Reg data=&0x%08x\n",reg_val); ++ pr_debug("[I2C read]: Reg data=&0x%08x\n",reg_val); + break; + + case VM_NL80211_VENDER_I2C_SETREG: @@ -45638,7 +45724,7 @@ index 000000000000..b6e0dde8a4ca + rf_i2c_write(usr_data,usr_data_ext); +#endif + -+ printk("[I2C write] I2c addr: 0x%08x, data:0x%08x\n",usr_data,usr_data_ext); ++ pr_debug("[I2C write] I2c addr: 0x%08x, data:0x%08x\n",usr_data,usr_data_ext); + break; + + case VM_NL80211_T9026_DUMP_RXIRR_REG: @@ -45655,15 +45741,15 @@ index 000000000000..b6e0dde8a4ca + + case VM_NL80211_VENDER_DBG_INFO_ENABLE: + g_dbg_info_enable = (unsigned long long)usr_data; -+ printk("%s(%d)dbg_en=0x%08llx\n ", __func__, __LINE__, g_dbg_info_enable); ++ pr_debug("%s(%d)dbg_en=0x%08llx\n ", __func__, __LINE__, g_dbg_info_enable); + break; + case VM_NL80211_VENDER_DYNAMIC_BW_CFG: + if( usr_data != 0 ){ + wifi_mac_config(wifimac, CHIP_PARAM_DYNAMIC_BW, 1); -+ printk("enable dynamic bandwith\n"); ++ pr_debug("enable dynamic bandwidth\n"); + }else{ + wifi_mac_config(wifimac, CHIP_PARAM_DYNAMIC_BW, 0); -+ printk("disable dynamic bandwith\n"); ++ pr_debug("disable dynamic bandwidth\n"); + } + + break; @@ -45676,7 +45762,7 @@ index 000000000000..b6e0dde8a4ca + + if (bcn_intvl == 0) + bcn_intvl = WIFINET_BINTVAL_DEFAULT; -+ printk("%s:%d, bcn intvl %d\n", __func__, __LINE__, bcn_intvl); ++ pr_debug("%s:%d, bcn intvl %d\n", __func__, __LINE__, bcn_intvl); + wifimac->drv_priv->drv_ops.Phy_beaconinit(wifimac->drv_priv, + wnet_vif->wnet_vif_id, bcn_intvl); + @@ -45740,26 +45826,26 @@ index 000000000000..b6e0dde8a4ca + break; + + case VM_NL80211_VENDOR_UPDATE_WIPHY_PARAMS: -+ printk("Cfg80211: update_wiphy_params\n"); -+ printk("Cfg80211: wiphy addr: 0x%p----\n", wiphy); ++ pr_debug("Cfg80211: update_wiphy_params\n"); ++ pr_debug("Cfg80211: wiphy addr: 0x%p----\n", wiphy); + vm_cfg80211_update_wiphy_params(wiphy); + break; + case VM_NL80211_VENDOR_SET_PREAMBLE_TYPE: -+ printk("Cfg80211: set preamble type\n"); ++ pr_debug("Cfg80211: set preamble type\n"); + phy_set_preamble_type(usr_data); + break; + case VM_NL80211_VENDOR_SET_BURST: -+ printk("Cfg80211: set burst\n"); ++ pr_debug("Cfg80211: set burst\n"); + wifimac->drv_priv->drv_config.cfg_burst_ack = usr_data; + break; + case VM_NL80211_VENDOR_SET_ACK_POLICY: -+ printk("Cfg80211: set ack policy\n"); ++ pr_debug("Cfg80211: set ack policy\n"); + wifimac->drv_priv->drv_config.ack_policy = usr_data; + break; + case VM_NL80211_SENDTEST: + frame_num = usr_data >> 16; + frame_len = usr_data & 0xffff; -+ printk("Cfg80211: frame_num =%d,frame_len=%d\n", frame_num, frame_len); ++ pr_debug("Cfg80211: frame_num =%d,frame_len=%d\n", frame_num, frame_len); + do + { + wifi_mac_send_testdata(wnet_vif->vm_mainsta, frame_len); @@ -45770,12 +45856,12 @@ index 000000000000..b6e0dde8a4ca + + case VM_NL80211_BT_REG_READ: + reg_val = wnet_vif->vif_ops.bt_read_word(usr_data); -+ printk("Read BT Addr = 0x%x,data = 0x%x\n",usr_data,reg_val); ++ pr_debug("Read BT Addr = 0x%x,data = 0x%x\n",usr_data,reg_val); + break; + + case VM_NL80211_BT_REG_WRITE: + wnet_vif->vif_ops.bt_write_word(usr_data,usr_data_ext); -+ printk("Write BT Addr = 0x%x,data = 0x%x\n",usr_data,usr_data_ext); ++ pr_debug("Write BT Addr = 0x%x,data = 0x%x\n",usr_data,usr_data_ext); + break; + + case VM_NL80211_SET_LDPC: @@ -45783,23 +45869,23 @@ index 000000000000..b6e0dde8a4ca + { + if (aml_wifi_is_enable_rf_test()) { + gB2BTestCasePacket.ldpc_enable = 1; -+ printk("Enable tx ldpc\n"); ++ pr_debug("Enable tx ldpc\n"); + } + + wnet_vif->vm_mainsta->sta_vhtcap |= WIFINET_VHTCAP_RX_LDPC; + wifimac->wm_flags |=WIFINET_F_LDPC; -+ printk("Enable ldpc, if need change,the action must be excute before connect ap or create ap\n"); ++ pr_debug("Enable ldpc, if need change,the action must be excute before connect ap or create ap\n"); + } + else + { + if (aml_wifi_is_enable_rf_test()) { + gB2BTestCasePacket.ldpc_enable = 0; -+ printk("Disable tx ldpc\n"); ++ pr_debug("Disable tx ldpc\n"); + } + + wnet_vif->vm_mainsta->sta_vhtcap &= ~WIFINET_VHTCAP_RX_LDPC; + wifimac->wm_flags &=~WIFINET_F_LDPC; -+ printk("Disable ldpc, if need change,the action must be excute before connect ap or create ap\n"); ++ pr_debug("Disable ldpc, if need change,the action must be excute before connect ap or create ap\n"); + } + break; + @@ -45835,22 +45921,22 @@ index 000000000000..b6e0dde8a4ca + +#ifdef WIFI_CAPTURE + case VM_NL80211_SET_CAP_GAIN: -+ printk("set gain = 0x%08x\n",ntohl(vnd_if->vnd_com_cmd.data)); ++ pr_debug("set gain = 0x%08x\n",ntohl(vnd_if->vnd_com_cmd.data)); + dut_set_gain(ntohl(vnd_if->vnd_com_cmd.data)); + break; + + case VM_NL80211_SET_BCAP_NAME: -+ printk("bcap name = 0x%08x\n",ntohl(vnd_if->vnd_com_cmd.data)); ++ pr_debug("bcap name = 0x%08x\n",ntohl(vnd_if->vnd_com_cmd.data)); + dut_set_bcap_log_name(ntohl(vnd_if->vnd_com_cmd.data)); + break; + + case VM_NL80211_VDR_SUBCMD_START_CAPTURE: -+ printk("Drv info: Reg addr=0x%08x\n",ntohl(vnd_if->vnd_com_cmd.data)); ++ pr_debug("Drv info: Reg addr=0x%08x\n",ntohl(vnd_if->vnd_com_cmd.data)); + dut_start_capture(ntohl(vnd_if->vnd_com_cmd.data)); + break; + + case VM_NL80211_VDR_SUBCMD_STOP_CAPTURE: -+ printk("Drv info: Reg addr=0x%08x\n",usr_data); ++ pr_debug("Drv info: Reg addr=0x%08x\n",usr_data); + dut_stop_capture(); + break; +#endif @@ -45863,46 +45949,46 @@ index 000000000000..b6e0dde8a4ca + wnet_vif->vm_pwrsave.ips_inactivitytime = (unsigned int)usr_data; + + os_timer_ex_start_period(&wnet_vif->vm_pwrsave.ips_timer_presleep, wnet_vif->vm_pwrsave.ips_inactivitytime); -+ printk("%s(%d) set ips_inactivitytime = 0x%08x\n ", __func__, __LINE__, wnet_vif->vm_pwrsave.ips_inactivitytime); ++ pr_debug("%s(%d) set ips_inactivitytime = 0x%08x\n ", __func__, __LINE__, wnet_vif->vm_pwrsave.ips_inactivitytime); + break; + + case VM_NL80211_FETCH_PKT_METHOD: + wnet_vif->vm_mainsta->sta_fetch_pkt_method = (unsigned char)usr_data; -+ printk("%s(%d) set sta_fetch_pkt_method = %d\n ", __func__, __LINE__, wnet_vif->vm_mainsta->sta_fetch_pkt_method); ++ pr_debug("%s(%d) set sta_fetch_pkt_method = %d\n ", __func__, __LINE__, wnet_vif->vm_mainsta->sta_fetch_pkt_method); + break; + + case VM_NL80211_PKT_FRAGMENT_THRESHOLD: + if ((unsigned short)usr_data > 0) { + wnet_vif->vm_fragthreshold = (unsigned short)usr_data; + } -+ printk("%s(%d) set vm_fragthreshold = %d\n ", __func__, __LINE__, wnet_vif->vm_fragthreshold); ++ pr_debug("%s(%d) set vm_fragthreshold = %d\n ", __func__, __LINE__, wnet_vif->vm_fragthreshold); + break; + + case VM_NL80211_UAPSD_ENABLE: + if ((unsigned char)usr_data != 0) { + WIFINET_VMAC_UAPSD_ENABLE(wnet_vif); -+ printk("%s(%d) enable ap uapsd\n ", __func__, __LINE__); ++ pr_debug("%s(%d) enable ap uapsd\n ", __func__, __LINE__); + + } else { + WIFINET_VMAC_UAPSD_DISABLE(wnet_vif); -+ printk("%s(%d) disable ap uapsd\n ", __func__, __LINE__); ++ pr_debug("%s(%d) disable ap uapsd\n ", __func__, __LINE__); + } + break; + + case VM_NL80211_CLK_MEASURE: + host_clk_msr((unsigned char)(usr_data)); -+ printk("%s(%d) host_clk_msr: %d\n ", __func__, __LINE__, (unsigned char)(usr_data)); ++ pr_debug("%s(%d) host_clk_msr: %d\n ", __func__, __LINE__, (unsigned char)(usr_data)); + break; + + case VM_NL80211_AUTORATE_ENABLE: + wnet_vif->vm_fixed_rate.rateinfo = 0; + wnet_vif->vm_fixed_rate.mode = WIFINET_FIXED_RATE_NONE; + wnet_vif->vm_change_rate_enable = 1; -+ printk("%s %d, enable autorate\n", __func__,__LINE__); ++ pr_debug("%s %d, enable autorate\n", __func__,__LINE__); + break; + + case VM_NL80211_SDIO_DLY_ADJUST: -+ printk("sdio change timing %08x\n", usr_data); ++ pr_debug("sdio change timing %08x\n", usr_data); + hif->hif_ops.hi_write_reg8(0x2c0, 0); + + switch (usr_data) { @@ -45923,11 +46009,11 @@ index 000000000000..b6e0dde8a4ca + break; + } + -+ printk("debug reg:%08x, read:%08x\n", reg, (unsigned int)(hif->hif_ops.hi_read_reg8(reg))); ++ pr_debug("debug reg:%08x, read:%08x\n", reg, (unsigned int)(hif->hif_ops.hi_read_reg8(reg))); + for (i = 0; i < 32; ++i) { + hif->hif_ops.hi_write_reg8(reg, i); + -+ printk("0x0000b078 %08x, debug reg:%08x, i :%d, read:%08x\n", ++ pr_debug("0x0000b078 %08x, debug reg:%08x, i :%d, read:%08x\n", + (unsigned int)(hif->hif_ops.hi_read_word(0x0000b078)), reg, i, (unsigned int)(hif->hif_ops.hi_read_reg8(reg))); + hif->hif_ops.hi_write_word(0x0000b078, 0x00000701 + i); + } @@ -45939,50 +46025,50 @@ index 000000000000..b6e0dde8a4ca + + if ((usr_data & 0xFF) > 4) + { -+ printk("support max spatial is 4 !\n"); ++ pr_debug("support max spatial is 4 !\n"); + wifimac->max_spatial = 4; + } + else if ((usr_data & 0xFF) <= 0) + { -+ printk("min spatial is 1 !\n"); ++ pr_debug("min spatial is 1 !\n"); + wifimac->max_spatial = 1; + } + else + wifimac->max_spatial = usr_data & 0xFF; -+ printk("%s:%d, set spatial %d \n", __func__, __LINE__, wifimac->max_spatial); ++ pr_debug("%s:%d, set spatial %d \n", __func__, __LINE__, wifimac->max_spatial); + + if ((((usr_data >> 8) & 0xFF) & BIT(0)) == BIT(0)) + { + wifimac->wm_flags_ext2 |= WIFINET_VHTCAP_SU_BFMEE; -+ printk("%s:%d, enable su mimo\n", __func__, __LINE__); ++ pr_debug("%s:%d, enable su mimo\n", __func__, __LINE__); + } + else + { + wifimac->wm_flags_ext2 &= ~WIFINET_VHTCAP_SU_BFMEE; -+ printk("%s:%d, disable su mimo\n", __func__, __LINE__); ++ pr_debug("%s:%d, disable su mimo\n", __func__, __LINE__); + } + + if ((((usr_data >> 8) & 0xFF) & BIT(1)) == BIT(1)) + { + wifimac->wm_flags_ext2 |= WIFINET_VHTCAP_MU_BFMEE; -+ printk("%s:%d, enable mu mimo\n", __func__, __LINE__); ++ pr_debug("%s:%d, enable mu mimo\n", __func__, __LINE__); + } + else + { + wifimac->wm_flags_ext2 &= ~WIFINET_VHTCAP_MU_BFMEE; -+ printk("%s:%d, disable mu mimo\n", __func__, __LINE__); ++ pr_debug("%s:%d, disable mu mimo\n", __func__, __LINE__); + } + break; +#endif + +#ifdef WIFI_CAPTURE + case VM_NL80211_VDR_SUBCMD_BT_START_CAPTURE: -+ printk("Drv info: Reg addr=0x%08x\n",ntohl(vnd_if->vnd_com_cmd.data)); ++ pr_debug("Drv info: Reg addr=0x%08x\n",ntohl(vnd_if->vnd_com_cmd.data)); + dut_bt_start_capture(ntohl(vnd_if->vnd_com_cmd.data)); + break; + + case VM_NL80211_VDR_SUBCMD_BT_STOP_CAPTURE: -+ printk("Drv info: Reg addr=0x%08x\n",usr_data); ++ pr_debug("Drv info: Reg addr=0x%08x\n",usr_data); + dut_bt_stop_capture(); + break; +#endif @@ -45993,7 +46079,7 @@ index 000000000000..b6e0dde8a4ca + wifi_mac_set_scan_time(wnet_vif); + } + -+ printk("%s, vid:%d set scan_time_idle = %d\n ", __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_scan_time_idle); ++ pr_debug("%s, vid:%d set scan_time_idle = %d\n ", __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_scan_time_idle); + break; + + case VM_NL80211_SCAN_TIME_CONNECT: @@ -46002,37 +46088,37 @@ index 000000000000..b6e0dde8a4ca + wifi_mac_set_scan_time(wnet_vif); + } + -+ printk("%s, vid:%d set scan_time_connect = %d\n ", __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_scan_time_connect); ++ pr_debug("%s, vid:%d set scan_time_connect = %d\n ", __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_scan_time_connect); + break; + + case VM_NL80211_SCAN_HANG: + wnet_vif->vm_scan_hang = (unsigned char)usr_data; -+ printk("%s, vid:%d vm_scan_hang:%d\n ", __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_scan_hang); ++ pr_debug("%s, vid:%d vm_scan_hang:%d\n ", __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_scan_hang); + break; + + case VM_NL80211_PRINT_VERSION: + print_driver_version(); -+ printk("driver version: %s\n", DRIVERVERSION); ++ pr_debug("driver version: %s\n", DRIVERVERSION); + break; + + case VM_NL80211_SET_EN_COEX: -+ printk("%s, coexist en= %d\n ", __func__, usr_data); ++ pr_debug("%s, coexist en= %d\n ", __func__, usr_data); + wifimac->drv_priv->hal_priv->hal_ops.phy_set_coexist_en(usr_data); + break; + + case VM_NL80211_SET_COEXIST_MAX_MISS_BCN_CNT: -+ //printk("%s, set max bcn miss cnt= %d\n ", __func__, usr_data); ++ //pr_debug("%s, set max bcn miss cnt= %d\n ", __func__, usr_data); + wifimac->drv_priv->hal_priv->hal_ops.phy_set_coexist_max_miss_bcn(usr_data); + break; + + case VM_NL80211_SET_COEXIST_REQ_TIMEOUT: + wifimac->drv_priv->hal_priv->hal_ops.phy_set_coexist_req_timeslice_timeout_value(usr_data); -+ printk("%s, set req timeout value= %d\n ", __func__, usr_data); ++ pr_debug("%s, set req timeout value= %d\n ", __func__, usr_data); + break; + + case VM_NL80211_SET_COEXIST_NOT_GRANT_WEIGHT: + wifimac->drv_priv->hal_priv->hal_ops.phy_set_coexist_not_grant_weight(usr_data); -+ printk("%s, set coexist_not_grant_weight= %d\n ", __func__, usr_data); ++ pr_debug("%s, set coexist_not_grant_weight= %d\n ", __func__, usr_data); + break; + + case VM_NL80211_SET_COEXIST_CONFIG: @@ -46041,13 +46127,13 @@ index 000000000000..b6e0dde8a4ca + + case VM_NL80211_SET_COEXIST_MAX_NOT_GRANT_CNT: + wifimac->drv_priv->hal_priv->hal_ops.phy_set_coexist_max_not_grant_cnt(usr_data); -+ printk("%s, set coexist_max_not_grant_cnt= %d\n ", __func__, usr_data); ++ pr_debug("%s, set coexist_max_not_grant_cnt= %d\n ", __func__, usr_data); + break; + + case VM_NL80211_SET_COEXIST_IRQ_END_TIM: -+ printk("%s, set SET_COEXIST_IRQ_END_TIM= 0x%8x\n ", __func__, usr_data); -+ printk("%s, A2DP irq end time is = %d\n ", __func__, usr_data &0xffff); -+ printk("%s, other traffic irq end time is = %d\n ", __func__, usr_data>>16); ++ pr_debug("%s, set SET_COEXIST_IRQ_END_TIM= 0x%8x\n ", __func__, usr_data); ++ pr_debug("%s, A2DP irq end time is = %d\n ", __func__, usr_data &0xffff); ++ pr_debug("%s, other traffic irq end time is = %d\n ", __func__, usr_data>>16); + wnet_vif->vif_ops.write_word(RG_COEX_IRQ_END_TIME, usr_data); + break; + @@ -46077,7 +46163,7 @@ index 000000000000..b6e0dde8a4ca + break; + + default: -+ printk("Cfg80211 Warning:Vendor subcmd index out of range!!!\n"); ++ pr_err("Cfg80211 Warning:Vendor subcmd index out of range!!!\n"); + break; + } + return ret; @@ -46154,7 +46240,7 @@ index 000000000000..b6e0dde8a4ca + wiphy->flags |= WIPHY_FLAG_HAVE_AP_SME; + wiphy->flags |= WIPHY_FLAG_OFFCHAN_TX | WIPHY_FLAG_HAVE_AP_SME; + -+ printk("AML INFO:before register vendor cmd!!!\n "); ++ pr_debug("AML INFO:before register vendor cmd!!!\n "); + vm_register_cfg80211_vnd_cmd(wiphy); + return; +} @@ -46384,7 +46470,7 @@ index 000000000000..b6e0dde8a4ca + struct in_ifaddr *ifa_v4; + __be32 ipv4 = 0; + -+ printk(" %s %d cp->vm_param_opmode %x \n",__func__,__LINE__,cp->vm_param_opmode); ++ pr_debug(" %s %d cp->vm_param_opmode %x \n",__func__,__LINE__,cp->vm_param_opmode); + switch (cp->vm_param_opmode) + { + case WIFINET_M_STA: @@ -46400,7 +46486,7 @@ index 000000000000..b6e0dde8a4ca + netif_carrier_on(wnet_vif->vm_ndev); + break; + default: -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + return ; + } + @@ -46414,13 +46500,13 @@ index 000000000000..b6e0dde8a4ca + if (wifimac->drv_priv->drv_ops.change_interface(wifimac->drv_priv, + wnet_vif->wnet_vif_id,wnet_vif,vm_opmode, wnet_vif->vm_myaddr, ipv4)) + { -+ printk("Unable to add an interface for driver.\n"); ++ pr_err("Unable to add an interface for driver.\n"); + wifi_mac_free_vmac(wnet_vif); + return ; + } + vm_wlan_net_vif_setup_forchvif(wifimac, wnet_vif, NULL, vm_opmode); + wifi_mac_station_init(wnet_vif); -+ printk(" %s %d wnet_vif->vm_opmode =%d \n",__func__,__LINE__,wnet_vif->vm_opmode); ++ pr_debug(" %s %d wnet_vif->vm_opmode =%d \n",__func__,__LINE__,wnet_vif->vm_opmode); + wifi_mac_pwrsave_latevattach(wnet_vif); +} + @@ -46523,7 +46609,7 @@ index 000000000000..b6e0dde8a4ca + int total_delay = 0; + int canceled = 0, ready = 0; + -+ printk("%s %d try to preempt scan \n", __func__, __LINE__); ++ pr_debug("%s %d try to preempt scan \n", __func__, __LINE__); + + while (!ready && total_delay < max_grace + max_wait) + { @@ -46535,7 +46621,7 @@ index 000000000000..b6e0dde8a4ca + { + if (!canceled && total_delay > max_grace) + { -+ printk("%s: cancel pending scan request", __func__); ++ pr_warn("%s: cancel pending scan request", __func__); + (void) wifi_mac_cancel_scan(wifimac); + canceled = 1; + } @@ -46546,7 +46632,7 @@ index 000000000000..b6e0dde8a4ca + + if (!ready) + { -+ printk("%s: ","Timeout canceling current scan."); ++ pr_debug("%s: ","Timeout canceling current scan."); + } + + return ready; @@ -46596,19 +46682,111 @@ index 000000000000..b6e0dde8a4ca + reg_val = wnet_vif->vif_ops.read_word(addr[i]); + } + -+ printk("addr[%d] 0x%x data 0x%x\n", i, addr[i] , reg_val); ++ pr_debug("addr[%d] 0x%x data 0x%x\n", i, addr[i] , reg_val); + } + +} + ++/****************************************************************************** ++ * CFG80211 ++ *****************************************************************************/ ++#if defined(IEEE80211_MLD_MAX_NUM_LINKS) ++ #define CFG80211_SINGLE_NETDEV_MULTI_LINK_SUPPORT 1 ++#endif + ++static void aml_cfg80211_ch_switch_notify(struct net_device *dev, ++ struct cfg80211_chan_def *chandef, unsigned int link_id) ++{ ++#if ((defined (CONFIG_AMLOGIC_KERNEL_VERSION) && defined (AML_KERNEL_VERSION)) && (\ ++ (CONFIG_AMLOGIC_KERNEL_VERSION == 13515 && AML_KERNEL_VERSION >= 15)\ ++ || (CONFIG_AMLOGIC_KERNEL_VERSION == 14515 && AML_KERNEL_VERSION >= 12) ) )\ ++ || (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) && LINUX_VERSION_CODE < KERNEL_VERSION(6, 9, 0)) ++ return cfg80211_ch_switch_notify(dev, chandef, link_id, 0); ++#elif (defined (CFG80211_SINGLE_NETDEV_MULTI_LINK_SUPPORT)) || (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 2)) ++ return cfg80211_ch_switch_notify(dev, chandef, link_id); ++#else ++ return cfg80211_ch_switch_notify(dev, chandef); ++#endif ++} ++ ++static void aml_cfg80211_ch_switch_started_notify(struct net_device *dev, ++ struct cfg80211_chan_def *chandef, unsigned int link_id, u8 count, bool quiet) ++{ ++#if ((defined (CONFIG_AMLOGIC_KERNEL_VERSION) && defined (AML_KERNEL_VERSION)) && (\ ++ (CONFIG_AMLOGIC_KERNEL_VERSION == 13515 && AML_KERNEL_VERSION >= 15)\ ++ || (CONFIG_AMLOGIC_KERNEL_VERSION == 14515 && AML_KERNEL_VERSION >= 12) ) )\ ++ || (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) && LINUX_VERSION_CODE < KERNEL_VERSION(6, 9, 0)) ++ return cfg80211_ch_switch_started_notify(dev, chandef, link_id, count, quiet, 0); ++#elif (defined (CFG80211_SINGLE_NETDEV_MULTI_LINK_SUPPORT)) || (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)) ++ return cfg80211_ch_switch_started_notify(dev, chandef, link_id, count, quiet); ++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 11, 0)) ++ return cfg80211_ch_switch_started_notify(dev, chandef, count, quiet); ++#else ++ return cfg80211_ch_switch_started_notify(dev, chandef, count); ++#endif ++} ++ ++void vm_cfg80211_chan_switch_notify_task(SYS_TYPE param1,SYS_TYPE param2, SYS_TYPE param3,SYS_TYPE param4,SYS_TYPE param5) ++{ ++ struct wifi_mac *wifimac = (struct wifi_mac *)param1; ++ struct wlan_net_vif *wnet_vif = (struct wlan_net_vif *)param2; ++ unsigned char start = (unsigned char) param3; ++ struct net_device *ndev = wnet_vif->vm_ndev; ++ struct cfg80211_chan_def chandef = {0}; ++ struct wifi_channel *vmac_chan = (struct wifi_channel *)param4; ++ struct ieee80211_channel *notify_channel = NULL; ++ struct wiphy *wiphy = wnet_vif->vm_wdev->wiphy; ++ ++ if (vmac_chan == WIFINET_CHAN_ERR) ++ { ++ ERROR_DEBUG_OUT("main_vmac_chan is WIFINET_CHAN_ERR\n"); ++ return; ++ } ++ ++ notify_channel = ieee80211_get_channel(wiphy, wifi_mac_Ieee2mhz(vmac_chan->chan_pri_num, 0)); ++ if (notify_channel == NULL) { ++ ERROR_DEBUG_OUT("no such pri_chan:%d\n", vmac_chan->chan_pri_num); ++ return; ++ } else { ++ cfg80211_chandef_create(&chandef, notify_channel, NL80211_CHAN_NO_HT); ++ ++ if (vmac_chan->chan_bw == WIFINET_BWC_WIDTH20) { ++ chandef.width = NL80211_CHAN_WIDTH_20; ++ } else if (vmac_chan->chan_bw == WIFINET_BWC_WIDTH40) { ++ chandef.width = NL80211_CHAN_WIDTH_40; ++ } else if (vmac_chan->chan_bw == WIFINET_BWC_WIDTH80) { ++ chandef.width = NL80211_CHAN_WIDTH_80; ++ } else { ++ ERROR_DEBUG_OUT("station chan_bw do not support\n"); ++ } ++ chandef.center_freq1 = vmac_chan->chan_cfreq1; ++ } ++ ++ AML_OUTPUT("vid:%d notify new_chan:%d bw:%d freq:%d start:%d\n", wnet_vif->wnet_vif_id, vmac_chan->chan_pri_num, ++ vmac_chan->chan_bw, vmac_chan->chan_cfreq1, start); ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 1)) ++ wiphy_lock(wiphy); ++#endif ++ if (start) { ++ aml_cfg80211_ch_switch_started_notify(ndev, &chandef, 0, wnet_vif->vm_wmac->wm_doth_tbtt, 0);/*#define CSA_BLOCK_TX 1*/ ++ } else { ++ aml_cfg80211_ch_switch_notify(ndev, &chandef, 0); ++ memset(&(wnet_vif->csa_target.switch_chan) , 0, sizeof(struct wifi_channel)); ++ } ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 1)) ++ wiphy_unlock(wiphy); ++#endif ++ ++ return; ++} +#endif//CONFIG_AML_CFG80211 diff --git a/drivers/net/wireless/w1/vmac/wifi_cfg80211.h b/drivers/net/wireless/w1/vmac/wifi_cfg80211.h new file mode 100644 -index 000000000000..d2411ae12577 +index 0000000000000000000000000000000000000000..cf86244386580c9f3ef93c515ec34ec7a5a09da1 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_cfg80211.h -@@ -0,0 +1,381 @@ +@@ -0,0 +1,393 @@ +/* + **************************************************************************************** + * @@ -46987,12 +47165,24 @@ index 000000000000..d2411ae12577 +void batch_dump_reg(struct wiphy *wiphy,unsigned int addr[], unsigned int addr_num); +void wifi_softap_allsta_stopping(struct wlan_net_vif *wnet_vif, unsigned char is_disconnecting); +int softap_get_sta_num(struct wlan_net_vif *wnet_vif); -+ ++void vm_cfg80211_chan_switch_notify_task(SYS_TYPE param1,SYS_TYPE param2, SYS_TYPE param3,SYS_TYPE param4,SYS_TYPE param5); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5,15,0) ++int vm_cfg80211_set_bitrate_mask(struct wiphy *wiphy, ++ struct net_device *dev, ++ const unsigned char *peer, ++ const struct cfg80211_bitrate_mask *mask); ++#else ++int vm_cfg80211_set_bitrate_mask(struct wiphy *wiphy, ++ struct net_device *dev, ++ unsigned int link_id, ++ const unsigned char *peer, ++ const struct cfg80211_bitrate_mask *mask); ++#endif +#endif + diff --git a/drivers/net/wireless/w1/vmac/wifi_clock_measure.c b/drivers/net/wireless/w1/vmac/wifi_clock_measure.c new file mode 100644 -index 000000000000..a93c11ff5837 +index 0000000000000000000000000000000000000000..3fcb5daf07aa39ca7a1a08318bf4d9dbd81abc35 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_clock_measure.c @@ -0,0 +1,267 @@ @@ -47001,11 +47191,11 @@ index 000000000000..a93c11ff5837 +#include "wifi_hif.h" +#include "wifi_mac_com.h" + -+unsigned int clk_msr_time_set( unsigned int msr_freq) ++static unsigned int clk_msr_time_set( unsigned int msr_freq) +{ + unsigned int us_gate_time; + -+ if(msr_freq / 1000000 >= 160){ ++ if (msr_freq / 1000000 >= 160) { + us_gate_time = 1; + } else { + // if < 10Mhz, measure num is set about 320 @@ -47014,8 +47204,8 @@ index 000000000000..a93c11ff5837 + return us_gate_time; +} + -+// test the clock measurement -+unsigned int clk_msr_calc(unsigned int clk_mux, unsigned int exp_freq) ++// test the clock measurement ++static unsigned int clk_msr_calc(unsigned int clk_mux, unsigned int exp_freq) +{ + struct hw_interface* hif = hif_get_hw_interface(); + unsigned int measured_val; @@ -47024,18 +47214,18 @@ index 000000000000..a93c11ff5837 + + unsigned int us_gate_time = clk_msr_time_set(exp_freq); + -+ hif->hif_ops.hi_write_word(DF_REG_A18, (hif->hif_ops.hi_read_word(DF_REG_A18) & ~(0xFFFF << 0)) | ((us_gate_time-1) << 0)); ++ hif->hif_ops.hi_write_word(DF_REG_A18, (hif->hif_ops.hi_read_word(DF_REG_A18) & ~(0xFFFF << 0)) | ((us_gate_time-1) << 0)); + hif->hif_ops.hi_write_word(DF_REG_A18, (hif->hif_ops.hi_read_word(DF_REG_A18) & ~((1 << 18) | (1 << 17)))); -+ hif->hif_ops.hi_write_word(DF_REG_A18, (hif->hif_ops.hi_read_word(DF_REG_A18) & ~(0xff << 20)) -+ | ((clk_mux << 20) // Select MUX -+ | (1 << 19) //clk_to_msr_en ++ hif->hif_ops.hi_write_word(DF_REG_A18, (hif->hif_ops.hi_read_word(DF_REG_A18) & ~(0xff << 20)) ++ | ((clk_mux << 20) // Select MUX ++ | (1 << 19) //clk_to_msr_en + )); + + // enable measuring + hif->hif_ops.hi_write_word(DF_REG_A18, (hif->hif_ops.hi_read_word(DF_REG_A18) | (1 << 16)) ); + + // Wait for the measurement to be done -+ while( (hif->hif_ops.hi_read_word(DF_REG_A18) & (1 << 31)) ) {} ++ while ((hif->hif_ops.hi_read_word(DF_REG_A18) & (1 << 31))) {} + + // disable measuring + hif->hif_ops.hi_write_word(DF_REG_A18, (hif->hif_ops.hi_read_word(DF_REG_A18) & ~(1 << 16)) | (0 << 16)); @@ -47044,22 +47234,22 @@ index 000000000000..a93c11ff5837 + measured_val = (hif->hif_ops.hi_read_word(DF_REG_A20) & 0x000FFFFF); + measured_feq = (measured_val * 1000000) / (us_gate_time); + delt = exp_freq * 4 /100; -+ -+ printk("exp_freq = %d(MHz)\n", exp_freq / 1000000); -+ printk("measured_feq = %d(MHz)\n", measured_feq / 1000000); ++ ++ pr_debug("exp_freq = %d(MHz)\n", exp_freq / 1000000); ++ pr_debug("measured_feq = %d(MHz)\n", measured_feq / 1000000); + + if (measured_val == 0xFFFFF) { -+ printk("measured_val is 20 bits max\n"); ++ pr_warn("measured_val is 20 bits max\n"); + return 0; + } else if ((measured_feq < (exp_freq - delt)) || (measured_feq > (exp_freq + delt))) { -+ printk("clock measure failed, clock id : %d\n", clk_mux); ++ pr_err("clock measure failed, clock id : %d\n", clk_mux); + return 0; + } else { + return 1; + } +} + -+void clk_msr_adda(CLOCK_MUX clk_mux) ++static void clk_msr_adda(CLOCK_MUX clk_mux) +{ + unsigned int exp_val; + @@ -47069,7 +47259,7 @@ index 000000000000..a93c11ff5837 + unsigned int div3= 2; + unsigned int div4= 1; + -+ switch(clk_mux) { ++ switch (clk_mux) { + case CTS_CLK_ADDA_640M_POS: + exp_val = WF_BBP_CLK_640M / div; + break; @@ -47087,7 +47277,7 @@ index 000000000000..a93c11ff5837 + break; + + case CTS_CLK_XDAC_640M_POS: -+ exp_val = WF_BBP_CLK_640M / div4; ++ exp_val = WF_BBP_CLK_640M / div4; + break; + + case CTS_CLK_FEC_POS: @@ -47097,18 +47287,18 @@ index 000000000000..a93c11ff5837 + return; + } + -+ clk_msr_calc(clk_mux, exp_val); ++ clk_msr_calc(clk_mux, exp_val); +} + -+void clk_msr_cpu(void) ++static void clk_msr_cpu(void) +{ + unsigned int exp_val; + -+ exp_val = WF_BBP_CLK_640M / 8; ++ exp_val = WF_BBP_CLK_640M / 8; + clk_msr_calc(CTS_CLK_CPU_POS, exp_val); +} + -+void clk_msr_apb(void) ++static void clk_msr_apb(void) +{ + unsigned int exp_val; + @@ -47116,37 +47306,37 @@ index 000000000000..a93c11ff5837 + clk_msr_calc(CTS_CLK_APB_POS, exp_val); +} + -+void clk_msr_other(CLOCK_MUX clk_mux) ++static void clk_msr_other(CLOCK_MUX clk_mux) +{ + unsigned int exp_val; + -+ switch(clk_mux) { -+ case CTS_CLK_RADC_320M_POS: -+ exp_val = WF_ADC_CLK_320M; ++ switch (clk_mux) { ++ case CTS_CLK_RADC_320M_POS: ++ exp_val = WF_ADC_CLK_320M; + break; -+ case CTS_CLK_VIT_POS: -+ printk("not measure now\n"); ++ case CTS_CLK_VIT_POS: ++ pr_debug("not measure now\n"); + exp_val = BT_BBP_CLK_240M/2; + return; -+ case CTS_CLK_11BRX_POS: ++ case CTS_CLK_11BRX_POS: + exp_val = BT_BBP_CLK_240M/5; + break; + default: + return; + } + -+ clk_msr_calc(clk_mux, exp_val); ++ clk_msr_calc(clk_mux, exp_val); +} + -+void clk_msr_mac(void) ++static void clk_msr_mac(void) +{ + unsigned int exp_val; + -+ exp_val = WF_BBP_CLK_640M / 8; -+ clk_msr_calc(CTS_CLK_MAC_POS, exp_val); ++ exp_val = WF_BBP_CLK_640M / 8; ++ clk_msr_calc(CTS_CLK_MAC_POS, exp_val); +} + -+void clk_msr_xjtag(void) ++static void clk_msr_xjtag(void) +{ + unsigned int exp_val; + @@ -47154,7 +47344,7 @@ index 000000000000..a93c11ff5837 + clk_msr_calc(XJTAG_TCK_I_POS, exp_val); +} + -+void clk_msr_oscin(void) ++static void clk_msr_oscin(void) +{ + unsigned int exp_val; + @@ -47162,7 +47352,7 @@ index 000000000000..a93c11ff5837 + clk_msr_calc(SYS_OSCIN_I_POS, exp_val); +} + -+void clk_msr_wfdig(void) ++static void clk_msr_wfdig(void) +{ + unsigned int exp_val; + @@ -47170,14 +47360,14 @@ index 000000000000..a93c11ff5837 + clk_msr_calc(WF_DIG_OUT_POS, exp_val); +} + -+unsigned char * clk_mux_name(CLOCK_MUX clk_mux) ++static unsigned char * clk_mux_name(CLOCK_MUX clk_mux) +{ + unsigned char *clk_name; + -+ switch(clk_mux) { ++ switch (clk_mux) { + case CTS_CLK_11BRX_POS : clk_name = " cts_clk_11brx"; break; + case CTS_CLK_VIT_POS : clk_name = " cts_clk_vit"; break; -+ case CTS_CLK_RADC_320M_POS : clk_name = " cts_clk_radc_320M"; break; ++ case CTS_CLK_RADC_320M_POS : clk_name = " cts_clk_radc_320M"; break; + + case CTS_CLK_ADDA_320M_POS : clk_name = " cts_clk_adda_320M"; break; + case CTS_CLK_ADDA_80M_POS : clk_name = " cts_clk_adda_80M"; break; @@ -47202,32 +47392,32 @@ index 000000000000..a93c11ff5837 +//wire [127:0] clk_to_msr_in = { 109'h0, +// WF_DIG_OUT, +// sys_oscin_i, -+// cts_clk_fec , ++// cts_clk_fec, +// xjtag_tck_i, +// cts_clk_adda_640m, -+// cts_clk_cpu, -+// cts_clk_apb, -+// cts_clk_mac, -+// cts_clk_xdac_640m, -+// cts_clk_adda_160m, -+// cts_clk_radc_320m, -+// cts_clk_adda_80m, -+// 1'b0, -+// cts_clk_adda_320m, ++// cts_clk_cpu, ++// cts_clk_apb, ++// cts_clk_mac, ++// cts_clk_xdac_640m, ++// cts_clk_adda_160m, ++// cts_clk_radc_320m, ++// cts_clk_adda_80m, ++// 1'b0, ++// cts_clk_adda_320m, +// cts_clk_11brx +// }; -+void clk_msr(CLOCK_MUX clk_mux) ++static void clk_msr(CLOCK_MUX clk_mux) +{ + if (clk_mux != CTS_CLK_VIT_POS) { -+ printk("clk mux %s\n", clk_mux_name(clk_mux)); ++ pr_debug("clk mux %s\n", clk_mux_name(clk_mux)); + } + -+ switch(clk_mux) { ++ switch (clk_mux) { + case CTS_CLK_11BRX_POS : + //case CTS_CLK_VIT_POS : -+ case CTS_CLK_RADC_320M_POS : clk_msr_other(clk_mux); break; ++ case CTS_CLK_RADC_320M_POS : clk_msr_other(clk_mux); break; + -+ case CTS_CLK_ADDA_320M_POS : ++ case CTS_CLK_ADDA_320M_POS : + case CTS_CLK_ADDA_80M_POS : + case CTS_CLK_ADDA_160M_POS : + case CTS_CLK_XDAC_640M_POS : @@ -47245,7 +47435,7 @@ index 000000000000..a93c11ff5837 + } +} + -+void clk_msr_all(void) ++static void clk_msr_all(void) +{ + CLOCK_MUX i; + @@ -47265,76 +47455,76 @@ index 000000000000..a93c11ff5837 + diff --git a/drivers/net/wireless/w1/vmac/wifi_clock_measure.h b/drivers/net/wireless/w1/vmac/wifi_clock_measure.h new file mode 100644 -index 000000000000..f75e9c796971 +index 0000000000000000000000000000000000000000..a1d052cf170c7788fad8d630432785b0f2681a72 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_clock_measure.h @@ -0,0 +1,60 @@ -+#ifndef __CLOCK_MEASURE__ -+#define __CLOCK_MEASURE__ -+//clock mux -+typedef enum clock_mux { -+ -+ CTS_CLK_11BRX_POS = 0, -+ CTS_CLK_ADDA_320M_POS = 1, -+ CTS_CLK_VIT_POS = 2, -+ CTS_CLK_ADDA_80M_POS = 3, -+ CTS_CLK_RADC_320M_POS = 4, -+ CTS_CLK_ADDA_160M_POS = 5, -+ CTS_CLK_XDAC_640M_POS = 6, -+ CTS_CLK_MAC_POS = 7, -+ CTS_CLK_APB_POS = 8, -+ CTS_CLK_CPU_POS = 9, -+ CTS_CLK_ADDA_640M_POS = 10, -+ XJTAG_TCK_I_POS = 11, -+ CTS_CLK_FEC_POS = 12, -+ SYS_OSCIN_I_POS = 13, -+ WF_DIG_OUT_POS = 14, -+ -+ CLOCK_MUX_MAX = WF_DIG_OUT_POS + 1, -+} CLOCK_MUX; -+ -+#define SYS_OSCIN_I 40000000 -+//#define VIRTUAL_CLK_500M 500000000 -+#define CTS_RTC_CLK 32000 -+#define CTS_CLK_CPU 40000000 -+#define WF_ADC_CLK_320M 320000000 -+#define BT_BBP_CLK_240M 240000000 -+#define CTS_MSR_CLK 6000000 -+#define WF_BBP_CLK_640M 640000000 -+#define WF_BBP_CLK_320M 320000000 -+#define WF_BBP_CLK_240M 240000000 -+#define WF_DIG_OUT 1250000 -+ -+//reg addr -+#define INTF_BASE_ADDR 0xa0d000 -+ -+#define DF_REG_A18 (INTF_BASE_ADDR +0x048) -+#define DF_REG_A19 (INTF_BASE_ADDR +0x04c) -+#define DF_REG_A20 (INTF_BASE_ADDR +0x050) -+#define DF_REG_A21 (INTF_BASE_ADDR +0x054) -+#define DF_REG_A22 (INTF_BASE_ADDR +0x058) -+#define DF_REG_A23 (INTF_BASE_ADDR +0x05c) -+ -+#define DF_REG_A36 (INTF_BASE_ADDR +0x090) -+#define DF_REG_A38 (INTF_BASE_ADDR +0x098) -+#define DF_REG_A40 (INTF_BASE_ADDR +0x0a0) -+#define DF_REG_A41 (INTF_BASE_ADDR +0x0a4) -+#define DF_REG_A49 (INTF_BASE_ADDR +0x0c4) -+ -+#define CPU_CLOCK_RTC (0x4f070033) -+#define CPU_CLOCK_DPLL (0x4f0700f3) -+#define CPU_CLOCK_XOSC (0x4f070001) -+ -+void host_clk_msr(CLOCK_MUX clk_mux); -+ -+#endif -+ ++#ifndef __CLOCK_MEASURE__ ++#define __CLOCK_MEASURE__ ++//clock mux ++typedef enum clock_mux { ++ ++ CTS_CLK_11BRX_POS = 0, ++ CTS_CLK_ADDA_320M_POS = 1, ++ CTS_CLK_VIT_POS = 2, ++ CTS_CLK_ADDA_80M_POS = 3, ++ CTS_CLK_RADC_320M_POS = 4, ++ CTS_CLK_ADDA_160M_POS = 5, ++ CTS_CLK_XDAC_640M_POS = 6, ++ CTS_CLK_MAC_POS = 7, ++ CTS_CLK_APB_POS = 8, ++ CTS_CLK_CPU_POS = 9, ++ CTS_CLK_ADDA_640M_POS = 10, ++ XJTAG_TCK_I_POS = 11, ++ CTS_CLK_FEC_POS = 12, ++ SYS_OSCIN_I_POS = 13, ++ WF_DIG_OUT_POS = 14, ++ ++ CLOCK_MUX_MAX = WF_DIG_OUT_POS + 1, ++} CLOCK_MUX; ++ ++#define SYS_OSCIN_I 40000000 ++//#define VIRTUAL_CLK_500M 500000000 ++#define CTS_RTC_CLK 32000 ++#define CTS_CLK_CPU 40000000 ++#define WF_ADC_CLK_320M 320000000 ++#define BT_BBP_CLK_240M 240000000 ++#define CTS_MSR_CLK 6000000 ++#define WF_BBP_CLK_640M 640000000 ++#define WF_BBP_CLK_320M 320000000 ++#define WF_BBP_CLK_240M 240000000 ++#define WF_DIG_OUT 1250000 ++ ++//reg addr ++#define INTF_BASE_ADDR 0xa0d000 ++ ++#define DF_REG_A18 (INTF_BASE_ADDR +0x048) ++#define DF_REG_A19 (INTF_BASE_ADDR +0x04c) ++#define DF_REG_A20 (INTF_BASE_ADDR +0x050) ++#define DF_REG_A21 (INTF_BASE_ADDR +0x054) ++#define DF_REG_A22 (INTF_BASE_ADDR +0x058) ++#define DF_REG_A23 (INTF_BASE_ADDR +0x05c) ++ ++#define DF_REG_A36 (INTF_BASE_ADDR +0x090) ++#define DF_REG_A38 (INTF_BASE_ADDR +0x098) ++#define DF_REG_A40 (INTF_BASE_ADDR +0x0a0) ++#define DF_REG_A41 (INTF_BASE_ADDR +0x0a4) ++#define DF_REG_A49 (INTF_BASE_ADDR +0x0c4) ++ ++#define CPU_CLOCK_RTC (0x4f070033) ++#define CPU_CLOCK_DPLL (0x4f0700f3) ++#define CPU_CLOCK_XOSC (0x4f070001) ++ ++void host_clk_msr(CLOCK_MUX clk_mux); ++ ++#endif ++ diff --git a/drivers/net/wireless/w1/vmac/wifi_cmd_func.c b/drivers/net/wireless/w1/vmac/wifi_cmd_func.c new file mode 100644 -index 000000000000..5e487301c3c9 +index 0000000000000000000000000000000000000000..3b735db95bac348f8f2785a6a7b0ae6de9f0b87c --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_cmd_func.c -@@ -0,0 +1,2057 @@ +@@ -0,0 +1,2189 @@ +#include +#include +#include @@ -47380,7 +47570,7 @@ index 000000000000..5e487301c3c9 + {"set_aggr_thr", aml_set_aggr_thresh}, + {"set_hrt_intv", aml_set_hrtimer_interval}, + {"get_ap_ip", aml_get_ap_ip}, -+ {"set_roam_2gthr", aml_set_roaming_threshold_2g},//wpa_cli driver set_roam_thr_2g -80 ++ {"set_roam_2gthr", aml_set_roaming_threshold_2g}, /* wpa_cli driver set_roam_thr_2g -80 */ + {"set_roam_5gthr", aml_set_roaming_threshold_5g}, + {"get_roam_chan", aml_get_roaming_candidate_chans}, + {"set_roam_chan", aml_set_roaming_candidate_chans}, @@ -47438,8 +47628,8 @@ index 000000000000..5e487301c3c9 + {"", NULL}, +}; + -+//Returns a char * arr [] and size is the length of the returned array -+char **aml_cmd_char_prase(char sep, const char *str, int *size) ++/* Returns a char * arr [] and size is the length of the returned array */ ++char **aml_cmd_char_phrase(char sep, const char *str, int *size) +{ + int count = 0; + int i; @@ -47457,14 +47647,15 @@ index 000000000000..5e487301c3c9 + + for (i = 0; i < strlen(str); i++) { + if (str[i] == sep) { -+ // kzalloc the memory space of substring length + 1 ++ /* kzalloc the memory space of substring length + 1 */ + ret[j] = (char *)kzalloc((i - lastindex) * sizeof(char), GFP_KERNEL); + memcpy(ret[j], str + lastindex + 1, i - lastindex - 1); + j++; + lastindex = i; + } + } -+ //Processing the last substring ++ ++ /* Processing the last substring */ + if (lastindex <= strlen(str) - 1) { + ret[j] = (char *)kzalloc((strlen(str) - lastindex) * sizeof(char), GFP_KERNEL); + memcpy(ret[j], str + lastindex + 1, strlen(str) - 1 - lastindex); @@ -47477,40 +47668,46 @@ index 000000000000..5e487301c3c9 +} + +/* -+* cmd: sta_send_bareq 11:22:33:44:55:66 5 -+*/ -+int aml_sta_send_addba_req(struct wlan_net_vif *wnet_vif, char* buf, int len) ++ * cmd: sta_send_bareq 11:22:33:44:55:66 5 ++ */ ++int aml_sta_send_addba_req(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ int skip = 0; ++ int skip; + char mac[18]; + int tid = 0; + + skip = strlen("sta_send_bareq") + 1; + sscanf(buf + skip, "%s %d", mac, &tid); + wifi_mac_send_addba_req(buf + skip, tid); ++ + return 0; +} + -+int aml_set_chip_id(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_chip_id(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; -+ int i,cmd_arg; ++ int cmd_arg; + char sep = ' '; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg) { ++ int i; ++ + for (i = 0; i < 32; i++) { -+ if (simple_strtoul(arg[2],NULL,16) & (1 << i)) { ++ if (simple_strtoul(arg[2], NULL, 16) & (1 << i)) { + efuse_manual_write(i, 8); + } + } ++ + for (i = 0; i < 16; i++) { -+ if (simple_strtoul(arg[1],NULL,16) & (1 << i)) { ++ if (simple_strtoul(arg[1], NULL, 16) & (1 << i)) { + efuse_manual_write(i, 9); + } + } -+ printk("write chip_id is :%04x%08x\n", simple_strtoul(arg[1],NULL,16) & 0xffff, -+ simple_strtoul(arg[2],NULL,16)); ++ ++ pr_debug("write chip_id is :%04x%08x\n", ++ simple_strtoul(arg[1], NULL, 16) & 0xffff, ++ simple_strtoul(arg[2], NULL, 16)); + + FREE(arg, "cmd_arg"); + } @@ -47518,57 +47715,69 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_get_chip_id(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_get_chip_id(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + int cmd_arg; + char sep = ' '; -+ unsigned int efuse_data_l = 0; -+ unsigned int efuse_data_h = 0; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg) { -+ efuse_data_l = efuse_manual_read(simple_strtoul(arg[1],NULL,16)); -+ efuse_data_h = efuse_manual_read(simple_strtoul(arg[2],NULL,16)); ++ unsigned int efuse_data_l; ++ unsigned int efuse_data_h; ++ ++ efuse_data_l = efuse_manual_read(simple_strtoul(arg[1], NULL, 16)); ++ efuse_data_h = efuse_manual_read(simple_strtoul(arg[2], NULL, 16)); + -+ printk("efuse addr:%08x,%08x, chip_id is :%04x%08x\n", simple_strtoul(arg[1],NULL,16), -+ simple_strtoul(arg[2],NULL,16), efuse_data_h & 0xffff, efuse_data_l); ++ pr_debug("efuse addr:%08x,%08x, chip_id is :%04x%08x\n", ++ simple_strtoul(arg[1], NULL, 16), simple_strtoul(arg[2], NULL, 16), ++ efuse_data_h & 0xffff, efuse_data_l); + FREE(arg, "cmd_arg"); + } + + return 0; +} + -+int aml_set_mac_addr(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_mac_addr(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; -+ char **mac_cmd; -+ int i,cmd_arg; ++ int cmd_arg; + char sep = ' '; -+ unsigned int efuse_data_l = 0; -+ unsigned int efuse_data_h = 0; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg) { ++ char **mac_cmd; ++ + sep = ':'; -+ mac_cmd = aml_cmd_char_prase(sep, arg[1], &cmd_arg); ++ mac_cmd = aml_cmd_char_phrase(sep, arg[1], &cmd_arg); + if (mac_cmd) { -+ efuse_data_l = (simple_strtoul(mac_cmd[2],NULL,16) << 24) | (simple_strtoul(mac_cmd[3],NULL,16) << 16) -+ | (simple_strtoul(mac_cmd[4],NULL,16) << 8) | simple_strtoul(mac_cmd[5],NULL,16); -+ efuse_data_h = (simple_strtoul(mac_cmd[0],NULL,16) << 8) | (simple_strtoul(mac_cmd[1],NULL,16)); ++ unsigned int efuse_data_l; ++ unsigned int efuse_data_h; ++ int i; ++ ++ efuse_data_l = (simple_strtoul(mac_cmd[2], NULL, 16) << 24) | ++ (simple_strtoul(mac_cmd[3], NULL, 16) << 16) | ++ (simple_strtoul(mac_cmd[4], NULL, 16) << 8) | ++ simple_strtoul(mac_cmd[5], NULL, 16); ++ efuse_data_h = (simple_strtoul(mac_cmd[0], NULL, 16) << 8) | ++ (simple_strtoul(mac_cmd[1], NULL, 16)); ++ + for (i = 0; i < 32; i++) { + if (efuse_data_l & (1 << i)) { + efuse_manual_write(i, 1); + } + } ++ + for (i = 0; i < 16; i++) { + if (efuse_data_h & (1 << i)) { + efuse_manual_write(i, 2); + } + } -+ printk("write MAC addr is: %02x:%02x:%02x:%02x:%02x:%02x\n", -+ (efuse_data_h & 0xff00) >> 8,efuse_data_h & 0x00ff, (efuse_data_l & 0xff000000) >> 24, -+ (efuse_data_l & 0x00ff0000) >> 16,(efuse_data_l & 0xff00) >> 8,efuse_data_l & 0xff); ++ ++ pr_debug("write MAC addr is: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ (efuse_data_h & 0xff00) >> 8, efuse_data_h & 0x00ff, ++ (efuse_data_l & 0xff000000) >> 24, (efuse_data_l & 0x00ff0000) >> 16, ++ (efuse_data_l & 0xff00) >> 8, efuse_data_l & 0xff); + } + + kfree(mac_cmd); @@ -47578,64 +47787,76 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_get_mac_addr(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_get_mac_addr(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + int cmd_arg; + char sep = ' '; -+ unsigned int efuse_data_l = 0; -+ unsigned int efuse_data_h = 0; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg) { -+ efuse_data_l = efuse_manual_read(simple_strtoul(arg[1],NULL,16)); -+ efuse_data_h = efuse_manual_read(simple_strtoul(arg[2],NULL,16)); -+ printk("efuse addr:%08x,%08x, MAC addr is: %02x:%02x:%02x:%02x:%02x:%02x\n", -+ simple_strtoul(arg[1],NULL,16), simple_strtoul(arg[2],NULL,16), -+ (efuse_data_h & 0xff00) >> 8,efuse_data_h & 0x00ff, (efuse_data_l & 0xff000000) >> 24, -+ (efuse_data_l & 0x00ff0000) >> 16,(efuse_data_l & 0xff00) >> 8,efuse_data_l & 0xff); ++ unsigned int efuse_data_l; ++ unsigned int efuse_data_h; ++ ++ efuse_data_l = efuse_manual_read(simple_strtoul(arg[1], NULL, 16)); ++ efuse_data_h = efuse_manual_read(simple_strtoul(arg[2], NULL, 16)); ++ pr_debug("efuse addr:%08x,%08x, MAC addr is: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ simple_strtoul(arg[1], NULL, 16), simple_strtoul(arg[2], NULL, 16), ++ (efuse_data_h & 0xff00) >> 8, efuse_data_h & 0x00ff, ++ (efuse_data_l & 0xff000000) >> 24, (efuse_data_l & 0x00ff0000) >> 16, ++ (efuse_data_l & 0xff00) >> 8, efuse_data_l & 0xff); + FREE(arg, "cmd_arg"); + } + + return 0; +} -+int aml_get_wifi_mac_addr(struct wlan_net_vif *wnet_vif, char* buf, int len) ++ ++int aml_get_wifi_mac_addr(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ int bytes_written = 0; ++ int bytes_written; + + bytes_written = snprintf(buf, len, MAC_FMT, MAC_ARG(wnet_vif->vm_myaddr)); -+ printk("%s,buf: %s\n", __func__, buf); ++ pr_debug("%s,buf: %s\n", __func__, buf); ++ + return bytes_written; +} + -+int aml_set_bt_device_id(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_bt_device_id(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; -+ char **mac_cmd; -+ int i,cmd_arg; ++ int cmd_arg; + char sep = ' '; -+ unsigned int efuse_data_l = 0; -+ unsigned int efuse_data_h = 0; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg) { ++ char **mac_cmd; ++ + sep = ':'; -+ mac_cmd = aml_cmd_char_prase(sep, arg[1], &cmd_arg); ++ mac_cmd = aml_cmd_char_phrase(sep, arg[1], &cmd_arg); + if (mac_cmd) { -+ efuse_data_h = (simple_strtoul(mac_cmd[0],NULL,16) << 24) | (simple_strtoul(mac_cmd[1],NULL,16) << 16) -+ | (simple_strtoul(mac_cmd[2],NULL,16) << 8) | simple_strtoul(mac_cmd[3],NULL,16); -+ efuse_data_l = (simple_strtoul(mac_cmd[4],NULL,16) << 24) | (simple_strtoul(mac_cmd[5],NULL,16) << 16); ++ unsigned int efuse_data_l; ++ unsigned int efuse_data_h; ++ int i; ++ ++ efuse_data_h = (simple_strtoul(mac_cmd[0], NULL, 16) << 24) | ++ (simple_strtoul(mac_cmd[1], NULL, 16) << 16) | ++ (simple_strtoul(mac_cmd[2], NULL, 16) << 8) | ++ simple_strtoul(mac_cmd[3], NULL, 16); ++ efuse_data_l = (simple_strtoul(mac_cmd[4], NULL, 16) << 24) | ++ (simple_strtoul(mac_cmd[5], NULL, 16) << 16); ++ + for (i = 0; i < 32; i++) { + if (efuse_data_h & (1 << i)) { + efuse_manual_write(i, 3); + } + } ++ + for (i = 16; i < 32; i++) { + if (efuse_data_l & (1 << i)) { + efuse_manual_write(i, 2); + } + } -+ printk("write BT device id is: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ pr_debug("write BT device id is: %02x:%02x:%02x:%02x:%02x:%02x\n", + (efuse_data_h & 0xff000000) >> 24, (efuse_data_h & 0x00ff0000) >> 16, + (efuse_data_h & 0xff00) >> 8,efuse_data_h & 0xff, + (efuse_data_l & 0xff000000) >> 24,(efuse_data_l & 0x00ff0000) >> 16); @@ -47654,43 +47875,44 @@ index 000000000000..5e487301c3c9 + char **arg; + int cmd_arg; + char sep = ' '; -+ unsigned int efuse_data_l = 0; -+ unsigned int efuse_data_h = 0; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg) { -+ efuse_data_l = efuse_manual_read(simple_strtoul(arg[1],NULL,16)); -+ efuse_data_h = efuse_manual_read(simple_strtoul(arg[2],NULL,16)); -+ printk("efuse addr:%08x,%08x, get BT device id is: %02x:%02x:%02x:%02x:%02x:%02x\n", -+ simple_strtoul(arg[1],NULL,16), simple_strtoul(arg[2],NULL,16), ++ unsigned int efuse_data_l; ++ unsigned int efuse_data_h; ++ ++ efuse_data_l = efuse_manual_read(simple_strtoul(arg[1], NULL, 16)); ++ efuse_data_h = efuse_manual_read(simple_strtoul(arg[2], NULL, 16)); ++ pr_debug("efuse addr:%08x,%08x, get BT device id is: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ simple_strtoul(arg[1], NULL, 16), simple_strtoul(arg[2], NULL, 16), + (efuse_data_h & 0xff000000) >> 24, (efuse_data_h & 0x00ff0000) >> 16, -+ (efuse_data_h & 0xff00) >> 8,efuse_data_h & 0xff, -+ (efuse_data_l & 0xff000000) >> 24,(efuse_data_l & 0x00ff0000) >> 16); ++ (efuse_data_h & 0xff00) >> 8, efuse_data_h & 0xff, ++ (efuse_data_l & 0xff000000) >> 24, (efuse_data_l & 0x00ff0000) >> 16); + FREE(arg, "cmd_arg"); + } + + return 0; +} + -+ -+int aml_sta_send_coexist_mgmt(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_sta_send_coexist_mgmt(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ int skip = 0; ++ int skip; + + skip = strlen("send_bss_coex") + 1; + wifi_mac_send_coexist_mgmt(buf + skip); ++ + return 0; +} + -+int aml_wpa_get_txaggr_status(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_get_txaggr_status(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char* str[2] = {"all", "reset"}; + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; @@ -47699,7 +47921,7 @@ index 000000000000..5e487301c3c9 + data = simple_strtol(arg[1], NULL, 0); + len = strlen("get_txaggr_sta ") + strlen(str[data]) + 1; + snprintf(buf, len, "get_txaggr_sta %s", str[data]); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_get_drv_txaggr_status(wnet_vif, buf, len); + + FREE(arg, "cmd_arg"); @@ -47707,7 +47929,7 @@ index 000000000000..5e487301c3c9 +} + + -+int aml_get_drv_txaggr_status(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_get_drv_txaggr_status(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; @@ -47715,29 +47937,30 @@ index 000000000000..5e487301c3c9 + unsigned int nframes; + struct drv_private *drv_priv = drv_get_drv_priv(); + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + -+ //get queue-0 statistics ++ /* get queue-0 statistics */ + if (likely(!arg[1])) { + i = 0; ++ + for (j = 0; j < 16; j++) { + nframes = drv_priv->drv_txlist_table[i].tx_aggr_status[j]; -+ printk("Q:%d; aggr %d packets times: %d\n", i, j + 1, nframes); ++ pr_debug("Q:%d; aggr %d packets times: %d\n", i, j + 1, nframes); + } -+ printk("\n"); ++ pr_debug("\n"); + + } else { -+ //get all statistics ++ /* get all statistics */ + if (strnicmp(arg[1], "all", strlen("all")) == 0) { + for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { + for (j = 0; j < 16; j++) { + nframes = drv_priv->drv_txlist_table[i].tx_aggr_status[j]; -+ printk("Q:%d; aggr %d packets times: %d\n", i, j + 1, nframes); ++ pr_debug("Q:%d; aggr %d packets times: %d\n", i, j + 1, nframes); + } -+ printk("\n"); ++ pr_debug("\n"); + } + } -+ //reset ++ /* reset */ + if (strnicmp(arg[1], "reset", strlen("reset")) == 0) { + for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { + for (j = 0; j < 16; j++) { @@ -47751,122 +47974,125 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_sta_get_wfd_session(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_sta_get_wfd_session(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ printk("%s, wfd_session_id=%s\n", __func__, wnet_vif->vm_p2p->wfd_session_id); ++ pr_debug("%s, wfd_session_id=%s\n", __func__, wnet_vif->vm_p2p->wfd_session_id); + return 0; +} + -+int aml_get_p2p_device_addr(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_get_p2p_device_addr(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ int bytes_written = 0; ++ int bytes_written; + + memcpy(buf, wnet_vif->vm_ndev->dev_addr, ETH_ALEN); -+ printk("%s,p2p_device_addr= %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, *buf, *(buf + 1), *(buf + 2), -+ *(buf + 3), *(buf + 4), *(buf + 5)); ++ pr_debug("%s,p2p_device_addr= %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, ++ *buf, *(buf + 1), *(buf + 2), *(buf + 3), *(buf + 4), *(buf + 5)); + + bytes_written = ETH_ALEN; ++ + return bytes_written; + +} + -+ -+int aml_wmm_ac_addts(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wmm_ac_addts(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ int skip = 0, cmd_arg; ++ int skip, cmd_arg; + char **arg; + char sep = ' '; ++ + skip = strlen("wmm_ac_addts") + 1; + -+ arg = aml_cmd_char_prase(sep, buf + skip, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf + skip, &cmd_arg); + wifi_mac_send_wmm_ac_addts(arg); + + FREE(arg, "cmd_arg"); + return 0; +} + -+int aml_wmm_ac_delts(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wmm_ac_delts(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ int skip = 0; ++ int skip; ++ + skip = strlen("wmm_ac_delts") + 1; + wifi_mac_send_wmm_ac_delts(buf + skip); ++ + return 0; +} + -+void aml_set_mac_amsdu_switch_state(char* arg) ++void aml_set_mac_amsdu_switch_state(char *arg) +{ + struct drv_private *drv_priv = drv_get_drv_priv(); + + if (!arg) { + if (drv_priv->drv_config.cfg_txamsdu) { -+ printk("AMSDU is ON.\n"); ++ pr_debug("AMSDU is ON.\n"); + } + else { -+ printk("AMSDU is OFF.\n"); ++ pr_debug("AMSDU is OFF.\n"); + } + } + else { + if (strnicmp(arg, "on", strlen("on")) == 0) { + drv_priv->drv_config.cfg_txamsdu = 1; -+ printk("AMSDU set ON!\n"); ++ pr_debug("AMSDU set ON!\n"); + + } + else if (strnicmp(arg, "off", strlen("off")) == 0) { + drv_priv->drv_config.cfg_txamsdu = 0; -+ printk("AMSDU set OFF!\n"); ++ pr_debug("AMSDU set OFF!\n"); + + } + else { + if (drv_priv->drv_config.cfg_txamsdu) { -+ printk("AMSDU is ON.\n"); ++ pr_debug("AMSDU is ON.\n"); + } + else { -+ printk("AMSDU is OFF.\n"); ++ pr_debug("AMSDU is OFF.\n"); + } + } + } +} + -+void aml_set_drv_ampdu_switch_state(char* arg) ++void aml_set_drv_ampdu_switch_state(char *arg) +{ + struct drv_private *drv_priv = drv_get_drv_priv(); + + if (!arg) { + if (drv_priv->drv_config.cfg_txaggr) { -+ printk("AMPDU is ON.\n"); ++ pr_debug("AMPDU is ON.\n"); + } + else { -+ printk("AMPDU is OFF.\n"); ++ pr_debug("AMPDU is OFF.\n"); + } + } + else { + if (strnicmp(arg, "on", strlen("on")) == 0) { + drv_priv->drv_config.cfg_txaggr = 1; -+ printk("AMPDU set ON!\n"); ++ pr_debug("AMPDU set ON!\n"); + } + else if (strnicmp(arg, "off", strlen("off")) == 0) { + drv_priv->drv_config.cfg_txaggr = 0; -+ printk("AMPDU set OFF!\n"); ++ pr_debug("AMPDU set OFF!\n"); + + } + else { + if (drv_priv->drv_config.cfg_txaggr) { -+ printk("AMPDU is ON.\n"); ++ pr_debug("AMPDU is ON.\n"); + } + else { -+ printk("AMPDU is OFF.\n"); ++ pr_debug("AMPDU is OFF.\n"); + } + } + } +} + -+int aml_set_mac_amsdu(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_mac_amsdu(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + + aml_set_mac_amsdu_switch_state(arg[1]); + @@ -47874,25 +48100,31 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+static struct wifi_channel * wifi_mac_find_chan_unlock( struct wifi_mac *wifimac, unsigned short cur_chan, -+ enum wifi_mac_bwc_width cur_bw, unsigned short cur_freq) ++static struct wifi_channel *wifi_mac_find_chan_unlock(struct wifi_mac *wifimac, ++ unsigned short cur_chan, ++ enum wifi_mac_bwc_width cur_bw, ++ unsigned short cur_freq) +{ -+ struct wifi_channel *c = NULL; -+ int i = 0; ++ int i; + + for (i = 0; i < wifimac->wm_nchans; i++) { ++ struct wifi_channel *c; ++ + c = &wifimac->wm_channels[i]; -+ if ((c->chan_pri_num== cur_chan) && (c->chan_bw == cur_bw) && (c->chan_cfreq1 == cur_freq)) { -+ DPRINTF(AML_DEBUG_BWC, "%s(%d) !!!: find a chan=%d, bw=%d and freq=%d.\n", __func__, __LINE__, cur_chan, cur_bw, cur_freq); ++ if ((c->chan_pri_num== cur_chan) && (c->chan_bw == cur_bw) && ++ (c->chan_cfreq1 == cur_freq)) { ++ DPRINTF(AML_DEBUG_BWC, "%s(%d) !!!: find a chan=%d, bw=%d and freq=%d.\n", ++ __func__, __LINE__, cur_chan, cur_bw, cur_freq); + return c; + } + } + -+ DPRINTF(AML_DEBUG_BWC, "%s(%d) !!!: NOT find a chan=%d, bw=%d and freq=%d.\n", __func__, __LINE__, cur_chan, cur_bw, cur_freq); ++ DPRINTF(AML_DEBUG_BWC, "%s(%d) !!!: NOT find a chan=%d, bw=%d and freq=%d.\n", ++ __func__, __LINE__, cur_chan, cur_bw, cur_freq); + return NULL; +} + -+void wifi_mac_set_country_code(char* arg) ++void wifi_mac_set_country_code(char *arg) +{ + struct wifi_mac *wifimac = wifi_mac_get_mac_handle(); + struct drv_private* drv_priv = wifimac->drv_priv; @@ -47902,17 +48134,20 @@ index 000000000000..5e487301c3c9 + unsigned short cur_freq = 0; + unsigned char cur_txpwrplan = 0; + -+ if ((wifimac->wm_nrunning == 1) && (drv_priv->drv_wnet_vif_table[NET80211_P2P_VMAC]->vm_state == WIFINET_S_CONNECTED)) { ++ if ((wifimac->wm_nrunning == 1) && ++ (drv_priv->drv_wnet_vif_table[NET80211_P2P_VMAC]->vm_state == WIFINET_S_CONNECTED)) { + selected_wnet_vif = drv_priv->drv_wnet_vif_table[NET80211_P2P_VMAC]; + } + -+ if (wifimac->wm_nrunning > 1) { -+ printk("Setting country_code in this mode is not yet supported!\n"); ++ if (wifimac->wm_nrunning > 1) { ++ pr_debug("Setting country_code in this mode is not yet supported!\n"); + return ; + } + -+ printk("%s,%d, arg=%s\n", __func__, __LINE__, arg); -+ if (arg && (arg[0] == wifimac->wm_country.iso[0]) && (arg[1] == wifimac->wm_country.iso[1])) { ++ pr_debug("%s,%d, arg=%s\n", __func__, __LINE__, arg); ++ ++ if (arg && (arg[0] == wifimac->wm_country.iso[0]) && ++ (arg[1] == wifimac->wm_country.iso[1])) { + ERROR_DEBUG_OUT("no need to set country code due to the same country code\n"); + return; + } @@ -47926,20 +48161,23 @@ index 000000000000..5e487301c3c9 + cur_bw = selected_wnet_vif->vm_curchan->chan_bw; + cur_freq = selected_wnet_vif->vm_curchan->chan_cfreq1; + } ++ + cur_txpwrplan = drv_priv->drv_config.cfg_txpoweplan; + + wifi_mac_set_country(wifimac, arg); + + if (wifimac->wm_nrunning == 1) { -+ selected_wnet_vif->vm_curchan = wifi_mac_find_chan_unlock(wifimac,cur_chan, cur_bw, cur_freq); ++ selected_wnet_vif->vm_curchan = wifi_mac_find_chan_unlock(wifimac, cur_chan, ++ cur_bw, cur_freq); + + if (!selected_wnet_vif->vm_curchan) { -+ wifi_mac_top_sm(selected_wnet_vif, WIFINET_S_INIT,0); ++ wifi_mac_top_sm(selected_wnet_vif, WIFINET_S_INIT, 0); + } + } + -+ if( cur_txpwrplan != drv_priv->drv_config.cfg_txpoweplan) { -+ wifi_mac_set_tx_power_coefficient(drv_priv, selected_wnet_vif->vm_curchan ,drv_priv->drv_config.cfg_txpoweplan); ++ if (cur_txpwrplan != drv_priv->drv_config.cfg_txpoweplan) { ++ wifi_mac_set_tx_power_coefficient(drv_priv, selected_wnet_vif->vm_curchan, ++ drv_priv->drv_config.cfg_txpoweplan); + } + + WIFI_CHANNEL_UNLOCK(wifimac); @@ -47964,10 +48202,10 @@ index 000000000000..5e487301c3c9 + return; + } + -+ wifimac->wm_doth_tbtt = 255; //simple_strtoul(*buf, NULL, 0); -+ //wifimac->wm_doth_channel = simple_strtoul(*(buf + 1), NULL, 0); ++ wifimac->wm_doth_tbtt = 255; /* simple_strtoul(*buf, NULL, 0); */ ++ /* wifimac->wm_doth_channel = simple_strtoul(*(buf + 1), NULL, 0); */ + wifimac->wm_doth_channel = channel; -+ printk("%s, wm_dott_tbtt=%d, wm_doth_channel=%d\n", __func__, wifimac->wm_doth_tbtt, wifimac->wm_doth_channel); ++ pr_debug("%s, wm_dott_tbtt=%d, wm_doth_channel=%d\n", __func__, wifimac->wm_doth_tbtt, wifimac->wm_doth_channel); + wifimac->wm_flags |= WIFINET_F_CHANSWITCH; + wifimac->wm_flags |= WIFINET_F_DOTH; + selected_wnet_vif->vm_chanchange_count = 0; @@ -47993,58 +48231,67 @@ index 000000000000..5e487301c3c9 + return; + } + selected_wnet_vif->vm_arp_rx.src_mac_addr[0] = simple_strtoul(*buf, NULL, 0); -+ selected_wnet_vif->vm_arp_rx.src_mac_addr[1] = simple_strtoul(*(buf+1), NULL, 0); -+ selected_wnet_vif->vm_arp_rx.src_mac_addr[2] = simple_strtoul(*(buf+2), NULL, 0); -+ selected_wnet_vif->vm_arp_rx.src_mac_addr[3] = simple_strtoul(*(buf+3), NULL, 0); -+ selected_wnet_vif->vm_arp_rx.src_mac_addr[4] = simple_strtoul(*(buf+4), NULL, 0); -+ selected_wnet_vif->vm_arp_rx.src_mac_addr[5] = simple_strtoul(*(buf+5), NULL, 0); -+ selected_wnet_vif->vm_arp_rx.src_ip_addr[0] = simple_strtoul(*(buf+6), NULL, 0); -+ selected_wnet_vif->vm_arp_rx.src_ip_addr[1] = simple_strtoul(*(buf+7), NULL, 0); -+ selected_wnet_vif->vm_arp_rx.src_ip_addr[2] = simple_strtoul(*(buf+8), NULL, 0); -+ selected_wnet_vif->vm_arp_rx.src_ip_addr[3] = simple_strtoul(*(buf+9), NULL, 0); -+ selected_wnet_vif->vm_arp_rx.out = simple_strtoul(*(buf+10), NULL, 0); -+ printk("set mac=%02x:%02x:%02x:%02x:%02x:%02x\n", selected_wnet_vif->vm_arp_rx.src_mac_addr[0],selected_wnet_vif->vm_arp_rx.src_mac_addr[1], -+ selected_wnet_vif->vm_arp_rx.src_mac_addr[2], selected_wnet_vif->vm_arp_rx.src_mac_addr[3], selected_wnet_vif->vm_arp_rx.src_mac_addr[4], selected_wnet_vif->vm_arp_rx.src_mac_addr[5]); -+ printk("set ip=%d.%d.%d.%d\n", selected_wnet_vif->vm_arp_rx.src_ip_addr[0], selected_wnet_vif->vm_arp_rx.src_ip_addr[1], -+ selected_wnet_vif->vm_arp_rx.src_ip_addr[2],selected_wnet_vif->vm_arp_rx.src_ip_addr[3]); ++ selected_wnet_vif->vm_arp_rx.src_mac_addr[1] = simple_strtoul(*(buf + 1), NULL, 0); ++ selected_wnet_vif->vm_arp_rx.src_mac_addr[2] = simple_strtoul(*(buf + 2), NULL, 0); ++ selected_wnet_vif->vm_arp_rx.src_mac_addr[3] = simple_strtoul(*(buf + 3), NULL, 0); ++ selected_wnet_vif->vm_arp_rx.src_mac_addr[4] = simple_strtoul(*(buf + 4), NULL, 0); ++ selected_wnet_vif->vm_arp_rx.src_mac_addr[5] = simple_strtoul(*(buf + 5), NULL, 0); ++ selected_wnet_vif->vm_arp_rx.src_ip_addr[0] = simple_strtoul(*(buf + 6), NULL, 0); ++ selected_wnet_vif->vm_arp_rx.src_ip_addr[1] = simple_strtoul(*(buf + 7), NULL, 0); ++ selected_wnet_vif->vm_arp_rx.src_ip_addr[2] = simple_strtoul(*(buf + 8), NULL, 0); ++ selected_wnet_vif->vm_arp_rx.src_ip_addr[3] = simple_strtoul(*(buf + 9), NULL, 0); ++ selected_wnet_vif->vm_arp_rx.out = simple_strtoul(*(buf + 10), NULL, 0); ++ pr_debug("set mac=%02x:%02x:%02x:%02x:%02x:%02x\n", ++ selected_wnet_vif->vm_arp_rx.src_mac_addr[0], ++ selected_wnet_vif->vm_arp_rx.src_mac_addr[1], ++ selected_wnet_vif->vm_arp_rx.src_mac_addr[2], ++ selected_wnet_vif->vm_arp_rx.src_mac_addr[3], ++ selected_wnet_vif->vm_arp_rx.src_mac_addr[4], ++ selected_wnet_vif->vm_arp_rx.src_mac_addr[5]); ++ pr_debug("set ip=%d.%d.%d.%d\n", selected_wnet_vif->vm_arp_rx.src_ip_addr[0], ++ selected_wnet_vif->vm_arp_rx.src_ip_addr[1], ++ selected_wnet_vif->vm_arp_rx.src_ip_addr[2], ++ selected_wnet_vif->vm_arp_rx.src_ip_addr[3]); + wifi_mac_set_arp_rsp(selected_wnet_vif); + return; +} + -+ +int aml_set_drv_ampdu(struct wlan_net_vif *wnet_vif, char* buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + + aml_set_drv_ampdu_switch_state(arg[1]); + + FREE(arg, "cmd_arg"); + return 0; +} -+int aml_update_wmm_arg(struct wlan_net_vif *wnet_vif, char* buf, int len) ++ ++int aml_update_wmm_arg(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; -+ char **param; + int cmd_arg, cmd_param; + char sep = ' '; -+ int ac = 0; -+ int i = 0; + struct wifi_mac_wme_state *wme = &wnet_vif->vm_wmac->wm_wme[wnet_vif->wnet_vif_id]; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + + if ((wme != NULL) && (arg[1] != NULL)) { ++ int ac; ++ + ac = simple_strtoul(arg[1], NULL, 0); + if ((ac < WME_NUM_AC) && (arg[2] != NULL)) { + struct wmeParams *wmep = &wme->wme_wmeChanParams.cap_wmeParams[ac]; ++ int i; + + for (i = 2; i < cmd_arg; i++) { ++ char **param; ++ + sep = ':'; -+ param = aml_cmd_char_prase(sep, arg[i], &cmd_param); ++ param = aml_cmd_char_phrase(sep, arg[i], &cmd_param); + if (strnicmp(arg[i], "acm", strlen("acm")) == 0) { + wmep->wmep_acm = simple_strtoul(param[1], NULL, 0); + @@ -48081,7 +48328,7 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_wpa_set_dynamic_bw(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_dynamic_bw(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char* str[2] = {"off", "on"}; + char **arg; @@ -48089,39 +48336,40 @@ index 000000000000..5e487301c3c9 + int cmd_arg; + int data = 0; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + len = strlen("get_txaggr_sta ") + strlen(str[data]) + 1; + snprintf(buf, len, "get_txaggr_sta %s", str[data]); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_set_dynamic_bw(wnet_vif, buf, len); + + FREE(arg, "cmd_arg"); + return 0; +} + -+ -+int aml_set_dynamic_bw(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_dynamic_bw(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; + struct drv_private *drv_priv = drv_get_drv_priv(); + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if ((drv_priv != NULL) && (arg[1] != NULL)) { ++ int data; ++ + if (strnicmp(arg[1], "on", strlen("on")) == 0) { + data = 1; -+ printk("dynamic_bw set ON!\n"); ++ pr_debug("dynamic_bw set ON!\n"); + + } else if (strnicmp(arg[1], "off", strlen("off")) == 0) { + data = 0; -+ printk("dynamic_bw set OFF!\n"); ++ pr_debug("dynamic_bw set OFF!\n"); + + } else { + ERROR_DEBUG_OUT("Parameter is error,now cfg_dynamic_bw=%d.\n", drv_priv->drv_config.cfg_dynamic_bw); @@ -48138,55 +48386,55 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_wpa_set_short_gi(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_short_gi(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char* str[2] = {"off", "on"}; + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + len = strlen("get_txaggr_sta ") + strlen(str[data]) + 1; + snprintf(buf, len, "get_txaggr_sta %s", str[data]); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_set_short_gi(wnet_vif, buf, len); + + FREE(arg, "cmd_arg"); + return 0; +} + -+ -+int aml_set_short_gi(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_short_gi(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + int usr_data; + char **arg; + char sep = ' '; + int cmd_arg; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (!arg[1]) { + FREE(arg, "cmd_arg"); + ERROR_DEBUG_OUT("--Bad parameter\n"); + return 0; + } -+ printk("%s,cmd param: %s, %s\n", __func__, arg[0], arg[1]); ++ pr_debug("%s,cmd param: %s, %s\n", __func__, arg[0], arg[1]); + + if (strnicmp(arg[1], "on", strlen("on")) == 0) { + usr_data = 1; -+ printk("%s: enable short GI.\n", __func__); ++ pr_debug("%s: enable short GI.\n", __func__); + + } else if (strnicmp(arg[1], "off", strlen("off")) == 0) { + usr_data = 0; -+ printk("%s: disable short GI.\n", __func__); ++ pr_debug("%s: disable short GI.\n", __func__); + + } else { -+ printk("%s--Bad parameter\n", __func__); ++ pr_debug("%s--Bad parameter\n", __func__); + FREE(arg, "cmd_arg"); + return 0; + } @@ -48196,11 +48444,11 @@ index 000000000000..5e487301c3c9 + + if (1 == usr_data) { + wnet_vif->vm_wmac->wm_flags_ext |= WIFINET_FEXT_SHORTGI_ENABLE; -+ printk("%s: enable short GI done\n", __func__); ++ pr_debug("%s: enable short GI done\n", __func__); + + } else { + wnet_vif->vm_wmac->wm_flags_ext &= ~WIFINET_FEXT_SHORTGI_ENABLE; -+ printk("%s: disable short GI done.\n", __func__); ++ pr_debug("%s: disable short GI done.\n", __func__); + } + + @@ -48208,16 +48456,17 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_set_eat_count_max(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_eat_count_max(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; + struct drv_private *drv_priv = drv_get_drv_priv(); + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if ((drv_priv != NULL) && (arg[1] != NULL)) { ++ int data; ++ + data = simple_strtoul(arg[1], NULL, 0); + drv_set_config((void *)drv_priv, CHIP_PARAM_EAT_COUNT, data); + @@ -48229,19 +48478,19 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_set_aggr_thresh(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_aggr_thresh(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; + struct drv_private *drv_priv = drv_get_drv_priv(); + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if ((drv_priv != NULL) && (arg[1] != NULL)) { ++ int data; ++ + data = simple_strtoul(arg[1], NULL, 0); + drv_set_config((void *)drv_priv, CHIP_PARAM_AGGR_THRESH, data); -+ + } else { + ERROR_DEBUG_OUT("Parameter is error.\n"); + } @@ -48250,16 +48499,17 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_set_hrtimer_interval(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_hrtimer_interval(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; + struct drv_private *drv_priv = drv_get_drv_priv(); + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if ((drv_priv != NULL) && (arg[1] != NULL)) { ++ int data; ++ + data = simple_strtoul(arg[1], NULL, 0); + drv_set_config((void *)drv_priv, CHIP_PARAM_HRTIMER_INTERVAL, data); + @@ -48271,32 +48521,32 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_get_ap_ip(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_get_ap_ip(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + if (!(wnet_vif->vm_mainsta->sta_arp_flag & WIFI_ARP_GET_AP_IP)) { + wifi_mac_send_arp_req(wnet_vif); -+ + } else { -+ printk("ap ip is:%d:%d:%d:%d\n", wnet_vif->vm_mainsta->sta_ap_ip[0], -+ wnet_vif->vm_mainsta->sta_ap_ip[1], wnet_vif->vm_mainsta->sta_ap_ip[2], wnet_vif->vm_mainsta->sta_ap_ip[3]); ++ pr_debug("ap ip is:%d:%d:%d:%d\n", wnet_vif->vm_mainsta->sta_ap_ip[0], ++ wnet_vif->vm_mainsta->sta_ap_ip[1], wnet_vif->vm_mainsta->sta_ap_ip[2], ++ wnet_vif->vm_mainsta->sta_ap_ip[3]); + } + + return 0; +} + -+ -+int aml_set_roaming_threshold_2g(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_roaming_threshold_2g(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if ((wnet_vif != NULL)&& (wnet_vif->vm_wmac != NULL) && (arg[1] != NULL)) { ++ int data; ++ + data = simple_strtol(arg[1], NULL, 0); + wnet_vif->vm_wmac->roaming_threshold_2g = data; -+ printk("vm_wmac->roaming_threshold_2g:%d\n", wnet_vif->vm_wmac->roaming_threshold_2g); ++ pr_debug("vm_wmac->roaming_threshold_2g:%d\n", wnet_vif->vm_wmac->roaming_threshold_2g); + + } else { + ERROR_DEBUG_OUT("Parameter is error.\n"); @@ -48306,19 +48556,19 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_set_roaming_threshold_5g(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_roaming_threshold_5g(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if ((wnet_vif != NULL) && (wnet_vif->vm_wmac != NULL) && (arg[1] != NULL)) { ++ int data; ++ + data = simple_strtol(arg[1], NULL, 0); + wnet_vif->vm_wmac->roaming_threshold_5g = data; -+ printk("vm_wmac->roaming_threshold_5g:%d\n", wnet_vif->vm_wmac->roaming_threshold_5g); -+ ++ pr_debug("vm_wmac->roaming_threshold_5g:%d\n", wnet_vif->vm_wmac->roaming_threshold_5g); + } else { + ERROR_DEBUG_OUT("Parameter is error.\n"); + } @@ -48327,22 +48577,24 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_get_roaming_candidate_chans(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_get_roaming_candidate_chans(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ int i = 0; -+ struct wifi_channel * chan = NULL; ++ int i; + int chan_cnt = wnet_vif->vm_wmac->wm_scan->roaming_candidate_chans_cnt; + -+ printk("get roaming candidate chans [%d]:\n", chan_cnt); ++ pr_debug("get roaming candidate chans [%d]:\n", chan_cnt); + + for (i=0; i < chan_cnt; i++) { ++ struct wifi_channel * chan; ++ + chan = wnet_vif->vm_wmac->wm_scan->roaming_candidate_chans[i].channel; + + if (chan == NULL) { + ERROR_DEBUG_OUT("erro pointer \n"); + return 0; + } -+ printk("chan_cfreq1:%d chan_flags:%d chan_pri_num:%d chan_maxpower:%d chan_minpower:%d chan_bw:%d global_operating_class %d Rssi:%d\n", ++ ++ pr_debug("chan_cfreq1:%d chan_flags:%d chan_pri_num:%d chan_maxpower:%d chan_minpower:%d chan_bw:%d global_operating_class %d Rssi:%d\n", + chan->chan_cfreq1, chan->chan_flags, chan->chan_pri_num, chan->chan_maxpower, + chan->chan_minpower, chan->chan_bw, chan->global_operating_class, + (wnet_vif->vm_wmac->wm_scan->roaming_candidate_chans[i].avg_rssi - 256)); @@ -48351,36 +48603,43 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_set_roaming_candidate_chans(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_roaming_candidate_chans(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; -+ int i = 0; -+ int j = 0; -+ struct wifi_channel *c; -+ struct wifi_mac *wifimac = NULL; -+ struct wifi_mac_scan_state *ss = NULL; ++ int i; ++ struct wifi_mac *wifimac; ++ struct wifi_mac_scan_state *ss; + + if (wnet_vif == NULL) { + return 0; + } ++ + wifimac = wnet_vif->vm_wmac; + ss = wifimac->wm_scan; + + WIFI_ROAMING_CHANNLE_LOCK(wnet_vif->vm_wmac->wm_scan); + + wnet_vif->vm_wmac->wm_scan->roaming_candidate_chans_cnt = 0; -+ memset(wnet_vif->vm_wmac->wm_scan->roaming_candidate_chans, 0, sizeof(wnet_vif->vm_wmac->wm_scan->roaming_candidate_chans)); ++ memset(wnet_vif->vm_wmac->wm_scan->roaming_candidate_chans, 0, ++ sizeof(wnet_vif->vm_wmac->wm_scan->roaming_candidate_chans)); ++ ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); + for (i = 1; i < ROAMING_CANDIDATE_CHAN_MAX; i++) { + if (arg[i] != NULL) { ++ int data; ++ int j; ++ + data = simple_strtoul(arg[i], NULL, 0); -+ printk("get channel:%d \n",data); ++ pr_debug("get channel:%d \n",data); ++ + WIFI_CHANNEL_LOCK(wifimac); ++ + for (j = 0; j < wifimac->wm_nchans; j++) { ++ struct wifi_channel *c; ++ + c = &wifimac->wm_channels[j]; + if (c->chan_bw == WIFINET_BWC_WIDTH20 && c->chan_pri_num == data) { + ss->roaming_candidate_chans[ss->roaming_candidate_chans_cnt].channel = c; @@ -48388,33 +48647,34 @@ index 000000000000..5e487301c3c9 + ss->roaming_candidate_chans_cnt++; + } + } -+ WIFI_CHANNEL_UNLOCK(wifimac); + ++ WIFI_CHANNEL_UNLOCK(wifimac); + } else { + WIFI_ROAMING_CHANNLE_UNLOCK(wnet_vif->vm_wmac->wm_scan); + FREE(arg, "cmd_arg"); + return 0; + } + } ++ + WIFI_ROAMING_CHANNLE_UNLOCK(wnet_vif->vm_wmac->wm_scan); + + FREE(arg, "cmd_arg"); + return 0; +} + -+ -+int aml_set_roaming_mode(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_roaming_mode(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if ((wnet_vif != NULL) && (wnet_vif->vm_wmac != NULL) && (arg[1] != NULL)) { ++ int data; ++ + data = simple_strtoul(arg[1], NULL, 0); + wnet_vif->vm_wmac->wm_roaming = data; -+ printk("vm_wmac->wm_roaming:%d\n", wnet_vif->vm_wmac->wm_roaming); ++ pr_debug("vm_wmac->wm_roaming:%d\n", wnet_vif->vm_wmac->wm_roaming); + } else { + ERROR_DEBUG_OUT("Parameter is error.\n"); + } @@ -48423,12 +48683,13 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int wifi_mac_set_udp_info(char** buf) ++int wifi_mac_set_udp_info(char **buf) +{ + struct wifi_mac *wifimac = wifi_mac_get_mac_handle(); + struct drv_private* drv_priv = wifimac->drv_priv; + struct wlan_net_vif *selected_wnet_vif = NULL; + unsigned int param; ++ + if (wifimac->wm_nrunning == 1) { + if (drv_priv->drv_wnet_vif_table[NET80211_P2P_VMAC]->vm_state == WIFINET_S_CONNECTED) { + selected_wnet_vif = drv_priv->drv_wnet_vif_table[NET80211_P2P_VMAC]; @@ -48453,28 +48714,33 @@ index 000000000000..5e487301c3c9 + aml_udp_info[udp_cnt].tx = 0; + aml_udp_timer.udp_timer_stop = 0; + -+ DPRINTF(AML_DEBUG_WARNING,"dst_port=%04x, src_port=%04x, dst_ip=%08x, src_ip:%08x, pkt_len:%d, out:%d, streamid:%d, param=%d\n", -+ aml_udp_info[udp_cnt].dst_port, aml_udp_info[udp_cnt].src_port, aml_udp_info[udp_cnt].dst_ip, aml_udp_info[udp_cnt].src_ip, -+ aml_udp_info[udp_cnt].pkt_len, aml_udp_info[udp_cnt].out, aml_udp_info[udp_cnt].streamid, param); ++ DPRINTF(AML_DEBUG_WARNING, ++ "dst_port=%04x, src_port=%04x, dst_ip=%08x, src_ip:%08x, pkt_len:%d, out:%d, streamid:%d, param=%d\n", ++ aml_udp_info[udp_cnt].dst_port, aml_udp_info[udp_cnt].src_port, ++ aml_udp_info[udp_cnt].dst_ip, aml_udp_info[udp_cnt].src_ip, ++ aml_udp_info[udp_cnt].pkt_len, aml_udp_info[udp_cnt].out, ++ aml_udp_info[udp_cnt].streamid, param); + + if (aml_udp_info[udp_cnt].out && aml_udp_timer.run_flag == 0) { -+ os_timer_ex_initialize(&aml_udp_timer.udp_send_timeout, 0, wifi_mac_udp_send_timeout_ex, selected_wnet_vif); ++ os_timer_ex_initialize(&aml_udp_timer.udp_send_timeout, 0, ++ wifi_mac_udp_send_timeout_ex, selected_wnet_vif); + os_timer_ex_start_period(&aml_udp_timer.udp_send_timeout, 10); + aml_udp_timer.run_flag = 1; + } ++ + udp_cnt++; + return 0; +} + -+//set_udp_info dst_port src_port dst_ip in/out -+int aml_set_udp_info(struct wlan_net_vif *wnet_vif, char* buf, int len) ++/* set_udp_info dst_port src_port dst_ip in/out */ ++int aml_set_udp_info(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + int skip = 0, cmd_arg; + char **arg; + char sep = ' '; + skip = strlen("set_udp_info") + 1; + -+ arg = aml_cmd_char_prase(sep, buf + skip, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf + skip, &cmd_arg); + wifi_mac_set_udp_info(arg); + + FREE(arg, "cmd_arg"); @@ -48483,9 +48749,10 @@ index 000000000000..5e487301c3c9 + +int aml_get_udp_info(struct wlan_net_vif *wnet_vif, char* buf, int len) +{ -+ int i = 0; ++ int i; ++ + for (i = 0; i < udp_cnt; i++) { -+ printk("%s streamid=%d tx is %d, rx is %d\n", __func__, aml_udp_info[i].streamid, aml_udp_info[i].tx, aml_udp_info[i].rx); ++ pr_debug("%s streamid=%d tx is %d, rx is %d\n", __func__, aml_udp_info[i].streamid, aml_udp_info[i].tx, aml_udp_info[i].rx); + } + aml_udp_timer.udp_timer_stop = 1; + aml_udp_timer.run_flag = 0; @@ -48493,20 +48760,21 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_unmark_dfs_channel(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_unmark_dfs_channel(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if ((wnet_vif != NULL) && (wnet_vif->vm_wmac != NULL)) { ++ int data = 0; ++ + if (arg[1] != NULL) { + data = simple_strtoul(arg[1], NULL, 0); + } + -+ printk("unmarked dfs channel :%d\n",data); ++ pr_debug("unmarked dfs channel :%d\n",data); + wifi_mac_unmark_dfs_channel(wnet_vif, data); + + } else { @@ -48517,20 +48785,21 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_mark_dfs_channel(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_mark_dfs_channel(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if ((wnet_vif != NULL) && (wnet_vif->vm_wmac != NULL)) { ++ int data = 0; ++ + if (arg[1] != NULL) { + data = simple_strtoul(arg[1], NULL, 0); + } + -+ printk("marked dfs channel :%d\n",data); ++ pr_debug("marked dfs channel :%d\n",data); + wifi_mac_mark_dfs_channel(wnet_vif, data); + + } else { @@ -48544,24 +48813,30 @@ index 000000000000..5e487301c3c9 +int aml_set_device_sn(struct wlan_net_vif *wnet_vif, char* buf, int len) +{ + char **arg; -+ char **mac_cmd; -+ int i,cmd_arg; ++ int cmd_arg; + char sep = ' '; -+ unsigned int efuse_data = 0; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg) { ++ char **mac_cmd; ++ + sep = ':'; -+ mac_cmd = aml_cmd_char_prase(sep, arg[1], &cmd_arg); ++ mac_cmd = aml_cmd_char_phrase(sep, arg[1], &cmd_arg); + if (mac_cmd) { -+ efuse_data = (simple_strtoul(mac_cmd[0],NULL,16) << 8) | (simple_strtoul(mac_cmd[1],NULL,16)); ++ unsigned int efuse_data; ++ int i; ++ ++ efuse_data = (simple_strtoul(mac_cmd[0], NULL, 16) << 8) | ++ (simple_strtoul(mac_cmd[1], NULL, 16)); ++ + for (i = 0; i < 16; i++) { + if (efuse_data & (1 << i)) { -+ //printk("set_dev_sn ===>>> efuse_manual_write: %d 0xf\n", i); ++ /* pr_debug("set_dev_sn ===>>> efuse_manual_write: %d 0xf\n", i); */ + efuse_manual_write(i, 0xf); + } + } -+ printk("set_dev_sn ===>>> write SN/ID is: %02x %02x\n", ((efuse_data & 0xff00) >> 8), (efuse_data & 0x00ff)); ++ pr_debug("set_dev_sn ===>>> write SN/ID is: %02x %02x\n", ++ ((efuse_data & 0xff00) >> 8), (efuse_data & 0x00ff)); + } + kfree(mac_cmd); + } @@ -48570,36 +48845,42 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_get_device_sn(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_get_device_sn(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + int cmd_arg; + char sep = ' '; -+ unsigned int efuse_data = 0; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg) { -+ efuse_data = efuse_manual_read(simple_strtoul(arg[1],NULL,16)); -+ printk("get_dev_sn ===>>> efuse addr:%08x, get SN/ID is: %02x %02x\n", simple_strtoul(arg[1],NULL,16), ((efuse_data & 0xff00) >> 8), (efuse_data & 0x00ff)); ++ unsigned int efuse_data; ++ ++ efuse_data = efuse_manual_read(simple_strtoul(arg[1], NULL, 16)); ++ pr_debug("get_dev_sn ===>>> efuse addr:%08x, get SN/ID is: %02x %02x\n", ++ simple_strtoul(arg[1], NULL, 16), ((efuse_data & 0xff00) >> 8), ++ (efuse_data & 0x00ff)); ++ + FREE(arg, "cmd_arg"); + } + + return 0; +} + -+int aml_set_signal_power_weak_thresh_for_narrow_bandwidth(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_signal_power_weak_thresh_for_narrow_bandwidth(struct wlan_net_vif *wnet_vif, ++ char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if ((wnet_vif != NULL) && (wnet_vif->vm_wmac != NULL) && (arg[1] != NULL)) { ++ int data; ++ + data = simple_strtol(arg[1], NULL, 0); + wnet_vif->vm_wmac->wm_signal_power_weak_thresh_narrow = data; -+ printk("set signal power weak thresh to: %d\n", wnet_vif->vm_wmac->wm_signal_power_weak_thresh_narrow); -+ ++ pr_debug("set signal power weak thresh to: %d\n", ++ wnet_vif->vm_wmac->wm_signal_power_weak_thresh_narrow); + } else { + ERROR_DEBUG_OUT("Parameter is error.\n"); + } @@ -48608,19 +48889,20 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_set_signal_power_weak_thresh_for_wide_bandwidth(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_signal_power_weak_thresh_for_wide_bandwidth(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if ((wnet_vif != NULL) && (wnet_vif->vm_wmac != NULL) && (arg[1] != NULL)) { ++ int data; ++ + data = simple_strtol(arg[1], NULL, 0); + wnet_vif->vm_wmac->wm_signal_power_weak_thresh_wide = data; -+ printk("set signal power weak thresh to: %d\n", wnet_vif->vm_wmac->wm_signal_power_weak_thresh_wide); -+ ++ pr_debug("set signal power weak thresh to: %d\n", ++ wnet_vif->vm_wmac->wm_signal_power_weak_thresh_wide); + } else { + ERROR_DEBUG_OUT("Parameter is error.\n"); + } @@ -48630,18 +48912,19 @@ index 000000000000..5e487301c3c9 +} + +extern int aml_iwpriv_set_lagecy_bitrate_mask(struct net_device *dev, unsigned int set); -+int aml_set_lagecy_bitrate_mask(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_lagecy_bitrate_mask(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + aml_iwpriv_set_lagecy_bitrate_mask(wnet_vif->vm_ndev, data); + @@ -48650,18 +48933,19 @@ index 000000000000..5e487301c3c9 +} + +extern int aml_iwpriv_set_ht_bitrate_mask(struct net_device *dev, unsigned int set); -+int aml_set_ht_bitrate_mask(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_ht_bitrate_mask(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + aml_iwpriv_set_ht_bitrate_mask(wnet_vif->vm_ndev, data); + @@ -48669,20 +48953,20 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+ +extern int aml_iwpriv_set_vht_bitrate_mask(struct net_device *dev, unsigned int set); -+int aml_set_vht_bitrate_mask(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_vht_bitrate_mask(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + aml_iwpriv_set_vht_bitrate_mask(wnet_vif->vm_ndev, data); + @@ -48691,25 +48975,26 @@ index 000000000000..5e487301c3c9 +} + +extern void aml_iwpriv_set_rate_auto(struct wlan_net_vif *wnet_vif); -+int aml_set_rate_auto(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_rate_auto(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + aml_iwpriv_set_rate_auto(wnet_vif); + return 0; +} + -+int aml_set_coex_req_timeslice_timeout(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_coex_req_timeslice_timeout(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + struct wifi_mac *wifimac = NULL; + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + wifimac = wifi_mac_get_mac_handle(); + wifimac->drv_priv->hal_priv->hal_ops.phy_set_coexist_req_timeslice_timeout_value(data); @@ -48718,19 +49003,20 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_set_coex_max_miss_bcn(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_coex_max_miss_bcn(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + struct wifi_mac *wifimac = NULL; + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + wifimac = wifi_mac_get_mac_handle(); + wifimac->drv_priv->hal_priv->hal_ops.phy_set_coexist_max_miss_bcn(data); @@ -48739,81 +49025,87 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_set_scan_hang(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_scan_hang(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + wnet_vif->vm_scan_hang = (unsigned char)data; -+ printk("%s, vid:%d vm_scan_hang:%d\n ", __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_scan_hang); ++ pr_debug("%s, vid:%d vm_scan_hang:%d\n ", __func__, wnet_vif->wnet_vif_id, ++ wnet_vif->vm_scan_hang); + + FREE(arg, "cmd_arg"); + return 0; +} + -+int aml_set_scan_connect_time(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_scan_connect_time(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + wnet_vif->vm_scan_time_connect = (unsigned char)data; + wifi_mac_set_scan_time(wnet_vif); -+ printk("%s, vid:%d vm_scan_time_connect:%d\n ", __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_scan_time_connect); ++ pr_debug("%s, vid:%d vm_scan_time_connect:%d\n ", __func__, wnet_vif->wnet_vif_id, ++ wnet_vif->vm_scan_time_connect); + + FREE(arg, "cmd_arg"); + return 0; +} + -+int aml_set_scan_idle_time(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_set_scan_idle_time(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + wnet_vif->vm_scan_time_idle = (unsigned char)data; + wifi_mac_set_scan_time(wnet_vif); -+ printk("%s, vid:%d vm_scan_idle:%d\n ", __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_scan_time_idle); ++ pr_debug("%s, vid:%d vm_scan_idle:%d\n ", __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_scan_time_idle); + + FREE(arg, "cmd_arg"); + return 0; +} + +unsigned int get_reg(struct wlan_net_vif *wnet_vif, unsigned int set); -+int aml_wpa_get_reg(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_get_reg(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + get_reg(wnet_vif, data); + @@ -48822,19 +49114,20 @@ index 000000000000..5e487301c3c9 +} + +unsigned int set_reg(struct wlan_net_vif *wnet_vif, unsigned int set1, unsigned int set2); -+int aml_wpa_set_reg(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_reg(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data1 = 0; -+ int data2 = 0; ++ int data1; ++ int data2; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data1 = simple_strtol(arg[1], NULL, 0); + data2 = simple_strtol(arg[2], NULL, 0); + set_reg(wnet_vif, data1, data2); @@ -48843,9 +49136,9 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_wpa_get_cca_status(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_get_cca_status(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ struct wifi_mac *wifimac = NULL; ++ struct wifi_mac *wifimac; + + wifimac = wifi_mac_get_mac_handle(); + wifimac->drv_priv->drv_ops.cca_busy_check(); @@ -48853,9 +49146,9 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_wpa_get_agc_status(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_get_agc_status(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ struct wifi_mac *wifimac = NULL; ++ struct wifi_mac *wifimac; + + wifimac = wifi_mac_get_mac_handle(); + wifimac->drv_priv->drv_ops.phy_stc(); @@ -48864,9 +49157,9 @@ index 000000000000..5e487301c3c9 +} + +unsigned int get_latest_tx_status(struct wifi_mac *wifimac); -+int aml_wpa_get_latest_tx_status(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_get_latest_tx_status(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ struct wifi_mac *wifimac = NULL; ++ struct wifi_mac *wifimac; + + wifimac = wifi_mac_get_mac_handle(); + get_latest_tx_status(wifimac); @@ -48875,18 +49168,19 @@ index 000000000000..5e487301c3c9 +} + +extern void print_driver_version(void); -+int aml_wpa_get_drv_ver(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_get_drv_ver(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + print_driver_version(); + return 0; +} + -+int aml_wpa_set_country_code(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_country_code(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; @@ -48897,28 +49191,31 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_wpa_get_country_code(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_get_country_code(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ struct wifi_mac *wifimac = NULL; ++ struct wifi_mac *wifimac; ++ + wifimac = wifi_mac_get_mac_handle(); -+ printk("country code: %s\n", wifimac->wm_country.iso); ++ pr_debug("country code: %s\n", wifimac->wm_country.iso); + + return 0; +} + +extern void wifi_mac_pwrsave_set_inactime(struct wlan_net_vif *wnet_vif, unsigned int time); -+int aml_wpa_set_power(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_power(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ int data; ++ ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); -+ ERROR_DEBUG_OUT("char_prase fail\n"); ++ ERROR_DEBUG_OUT("char_phrase fail\n"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + wifi_mac_pwrsave_set_inactime(wnet_vif, data); + @@ -48926,20 +49223,21 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_wpa_set_channel_rssi(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_channel_rssi(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ struct wifi_mac *wifimac = NULL; ++ struct wifi_mac *wifimac; + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + + wifimac = wifi_mac_get_mac_handle(); -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + wifimac->drv_priv->drv_ops.set_channel_rssi(wifimac->drv_priv, data); + @@ -48947,66 +49245,69 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_wpa_set_burst(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_burst(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ struct wifi_mac *wifimac = NULL; ++ struct wifi_mac *wifimac; + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + + wifimac = wifi_mac_get_mac_handle(); -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + wifimac->drv_priv->drv_config.cfg_burst_ack = data; -+ printk("wpa cli set burst %d\n", data); ++ pr_debug("wpa cli set burst %d\n", data); + + FREE(arg, "cmd_arg"); + return 0; +} + +extern void aml_iwpriv_set_uapsd(struct wlan_net_vif *wnet_vif, unsigned int set); -+int aml_wpa_set_uapsd(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_uapsd(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ struct wifi_mac *wifimac = NULL; ++ struct wifi_mac *wifimac; + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + + wifimac = wifi_mac_get_mac_handle(); -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + aml_iwpriv_set_uapsd(wnet_vif, data); -+ printk("wpa cli set uapsd %d\n", data); ++ pr_debug("wpa cli set uapsd %d\n", data); + + FREE(arg, "cmd_arg"); + return 0; +} + -+int aml_wpa_set_pt_rxstart(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_pt_rxstart(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + wnet_vif->vif_ops.pt_rx_start(data); -+ printk("wpa cli set rxstart %d\n", data); ++ pr_debug("wpa cli set rxstart %d\n", data); + + FREE(arg, "cmd_arg"); + return 0; @@ -49018,88 +49319,92 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_wpa_set_scan_pri(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_scan_pri(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ struct wifi_mac *wifimac = NULL; ++ struct wifi_mac *wifimac; + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + + wifimac = wifi_mac_get_mac_handle(); -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + wifimac->drv_priv->hal_priv->hal_ops.phy_set_coexist_scan_priority_range(data); -+ printk("wpa cli set scan pri %d\n", data); ++ pr_debug("wpa cli set scan pri %d\n", data); + + FREE(arg, "cmd_arg"); + return 0; +} + -+int aml_wpa_set_bebk_pri(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_bebk_pri(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ struct wifi_mac *wifimac = NULL; ++ struct wifi_mac *wifimac; + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + + wifimac = wifi_mac_get_mac_handle(); -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + wifimac->drv_priv->hal_priv->hal_ops.phy_set_coexist_be_bk_noqos_priority_range(data); -+ printk("wpa cli set bebk noqos pri %d\n", data); ++ pr_debug("wpa cli set bebk noqos pri %d\n", data); + + FREE(arg, "cmd_arg"); + return 0; +} + -+int aml_wpa_set_coex_btwifi(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_coex_btwifi(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ struct wifi_mac *wifimac = NULL; ++ struct wifi_mac *wifimac; + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + + wifimac = wifi_mac_get_mac_handle(); -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); -+ printk("%s, coexist en= %d\n ", __func__, data); ++ pr_debug("%s, coexist en= %d\n ", __func__, data); + wifimac->drv_priv->hal_priv->hal_ops.phy_set_coexist_en(data); + + FREE(arg, "cmd_arg"); + return 0; +} + -+int aml_wpa_set_coex_bcnmis(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_coex_bcnmis(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ -+ struct wifi_mac *wifimac = NULL; ++ struct wifi_mac *wifimac; + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + + wifimac = wifi_mac_get_mac_handle(); -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); -+ printk("%s, coexist value=%d\n ", __func__, data); ++ pr_debug("%s, coexist value=%d\n ", __func__, data); + wifimac->drv_priv->hal_priv->hal_ops.phy_set_coexist_max_miss_bcn(data); + + FREE(arg, "cmd_arg"); @@ -49107,20 +49412,21 @@ index 000000000000..5e487301c3c9 +} + +extern int aml_beacon_intvl_set(struct wlan_net_vif *wnet_vif, unsigned int set); -+int aml_wpa_set_bcn_intv(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_bcn_intv(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); -+ printk("%s, coexist value=%d\n", __func__, data); ++ pr_debug("%s, coexist value=%d\n", __func__, data); + aml_beacon_intvl_set(wnet_vif, data); + + FREE(arg, "cmd_arg"); @@ -49128,38 +49434,44 @@ index 000000000000..5e487301c3c9 +} + +extern int aml_set_ldpc(struct wlan_net_vif *wnet_vif, unsigned int set); -+int aml_wpa_set_ldpc(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_ldpc(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); -+ printk("%s, coexist value=%d\n", __func__, data); ++ pr_debug("%s, coexist value=%d\n", __func__, data); + aml_set_ldpc(wnet_vif, data); + + FREE(arg, "cmd_arg"); + return 0; +} + -+int aml_wpa_get_chan_list(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_get_chan_list(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + struct wifi_mac *wifimac = NULL; -+ struct wifi_channel *c = NULL; -+ int i = 0; ++ int i; ++ + wifimac = wifi_mac_get_mac_handle(); + + WIFI_CHANNEL_LOCK(wifimac); ++ + for (i = 0; i < wifimac->wm_nchans; i++) { ++ struct wifi_channel *c; ++ + c = &wifimac->wm_channels[i]; -+ printk("channel:%d\t frequency:%d \t bandwidth:%dMHz \n", c->chan_pri_num, c->chan_cfreq1, ((1 << c->chan_bw) * 20)); ++ pr_debug("channel:%d\t frequency:%d \t bandwidth:%dMHz \n", ++ c->chan_pri_num, c->chan_cfreq1, ((1 << c->chan_bw) * 20)); + } ++ + WIFI_CHANNEL_UNLOCK(wifimac); + + return 0; @@ -49167,19 +49479,20 @@ index 000000000000..5e487301c3c9 + +#if defined(SU_BF) || defined(MU_BF) +extern int aml_set_beamforming(struct wlan_net_vif *wnet_vif, unsigned int set1,unsigned int set2); -+int aml_wpa_set_beamforming(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_beamforming(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data1 = 0; -+ int data2 = 0; ++ int data1; ++ int data2; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data1 = simple_strtol(arg[1], NULL, 0); + data2 = simple_strtol(arg[2], NULL, 0); + aml_set_beamforming(wnet_vif, data1,data1); @@ -49189,81 +49502,85 @@ index 000000000000..5e487301c3c9 +} +#endif + -+int aml_wpa_set_pkt_fetch(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_pkt_fetch(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; + int data = 0; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + wnet_vif->vm_mainsta->sta_fetch_pkt_method = (unsigned char)data; -+ printk("wpa cli set pkt fetch %d\n", data); ++ pr_debug("wpa cli set pkt fetch %d\n", data); + + FREE(arg, "cmd_arg"); + return 0; +} + -+int aml_wpa_set_frag_thr(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_frag_thr(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + if ((unsigned short)data > 0) { + wnet_vif->vm_fragthreshold = (unsigned short)data; + } -+ printk("wpa cli set frag thr %d\n", data); ++ pr_debug("wpa cli set frag thr %d\n", data); + + FREE(arg, "cmd_arg"); + return 0; +} + -+int aml_wpa_set_preamble(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_preamble(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + phy_set_preamble_type(data); -+ printk("wpa cli set preamble type %d\n", data); ++ pr_debug("wpa cli set preamble type %d\n", data); + + FREE(arg, "cmd_arg"); + return 0; +} + -+int aml_wpa_set_band(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_band(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + struct drv_private *drv_priv = drv_get_drv_priv(); + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + drv_priv->drv_config.cfg_band = data; + @@ -49271,19 +49588,20 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_wpa_set_mac_mode(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_mac_mode(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + struct drv_private *drv_priv = drv_get_drv_priv(); + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + drv_priv->drv_config.cfg_mac_mode = data; + @@ -49291,19 +49609,19 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+ -+int aml_wpa_set_initial_gain_change_hang(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_initial_gain_change_hang(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; ++ int data; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; + } ++ + data = simple_strtol(arg[1], NULL, 0); + g_initial_gain_change_disable = data; + @@ -49318,14 +49636,14 @@ index 000000000000..5e487301c3c9 + return 0; +} + -+int aml_wpa_set_tx_power_change_hang(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_tx_power_change_hang(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; + int data = 0; + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; @@ -49349,40 +49667,44 @@ index 000000000000..5e487301c3c9 + char **arg; + char sep = ' '; + int cmd_arg; -+ int data = 0; + + struct drv_private *drv_priv = drv_get_drv_priv(); + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if ((drv_priv != NULL) && (arg[1] != NULL)) { ++ int data; ++ + data = simple_strtoul(arg[1], NULL, 0); + wifimac_set_tx_pwr_plan(data); + } else { -+ printk("Parameter is error.\n"); ++ pr_err("Parameter is error.\n"); + } + + FREE(arg, "cmd_arg"); + return 0; +} + -+int aml_set_debug_switch(char *switch_str) ++static int aml_set_debug_switch(char *switch_str) +{ + int debug_switch = 0; ++ + if(strstr(switch_str,"_off")!=NULL) + debug_switch = AML_DBG_OFF; + else if(strstr(switch_str,"_on")!=NULL) + debug_switch = AML_DBG_ON; + else + ERROR_DEBUG_OUT("input error\n"); ++ + return debug_switch; +} + -+int aml_wpa_set_debug(struct wlan_net_vif *wnet_vif, char* buf, int len) ++int aml_wpa_set_debug(struct wlan_net_vif *wnet_vif, char *buf, int len) +{ + char **arg; + char sep = ' '; + int cmd_arg; -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + if (arg[1] == NULL) { + FREE(arg, "cmd_arg"); + return -EINVAL; @@ -49394,10 +49716,10 @@ index 000000000000..5e487301c3c9 +} diff --git a/drivers/net/wireless/w1/vmac/wifi_cmd_func.h b/drivers/net/wireless/w1/vmac/wifi_cmd_func.h new file mode 100644 -index 000000000000..a5bb858233ae +index 0000000000000000000000000000000000000000..c1f483e81f91c5c15af515e9504ce6f42846b9f9 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_cmd_func.h -@@ -0,0 +1,138 @@ +@@ -0,0 +1,140 @@ +/* + **************************************************************************************** + * @@ -49535,10 +49857,12 @@ index 000000000000..a5bb858233ae +extern int aml_wpa_set_tx_power_change_hang(struct wlan_net_vif *wnet_vif, char* buf, int len); +extern int aml_set_tx_power_plan(struct wlan_net_vif *wnet_vif, char* buf, int len); +extern int aml_wpa_set_debug(struct wlan_net_vif *wnet_vif, char* buf, int len); ++ ++char **aml_cmd_char_phrase(char sep, const char *str, int *size); +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_common.c b/drivers/net/wireless/w1/vmac/wifi_common.c new file mode 100644 -index 000000000000..be512ad71415 +index 0000000000000000000000000000000000000000..e94da7161aa8c770458906997abd94d892f1f454 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_common.c @@ -0,0 +1,380 @@ @@ -49719,7 +50043,7 @@ index 000000000000..be512ad71415 + if (path && buf) { + ret = openFile(&fp, path, O_RDONLY, 0); + if (0 == ret) { -+ printk("openFile path:%s fp=%p\n", path , fp); ++ pr_debug("openFile path:%s fp=%p\n", path , fp); + oldfs = get_fs(); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0)) + set_fs(KERNEL_DS); @@ -49730,7 +50054,7 @@ index 000000000000..be512ad71415 + set_fs(oldfs); + closeFile(fp); + -+ printk("readFile, ret:%d\n", ret); ++ pr_debug("readFile, ret:%d\n", ret); + } else { + ERROR_DEBUG_OUT("openFile path:%s Fail, ret:%d\n", path, ret); + } @@ -49761,7 +50085,7 @@ index 000000000000..be512ad71415 + if (path && buf) { + ret = openFile(&fp, path, O_CREAT | O_WRONLY, 0666); + if (0 == ret) { -+ printk("openFile path:%s fp=%p\n", path , fp); ++ pr_debug("openFile path:%s fp=%p\n", path , fp); + oldfs = get_fs(); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0)) + set_fs(KERNEL_DS); @@ -49771,7 +50095,7 @@ index 000000000000..be512ad71415 + ret = writeFile(fp, buf, sz); + set_fs(oldfs); + closeFile(fp); -+ printk("writeFile, ret:%d\n", ret); ++ pr_debug("writeFile, ret:%d\n", ret); + } else { + ERROR_DEBUG_OUT("openFile path:%s Fail, ret:%d\n", path, ret); + } @@ -49889,7 +50213,7 @@ index 000000000000..be512ad71415 + + read_size = aml_retrieve_from_file(path, file_data, FILE_DATA_LEN); + if (read_size != FILE_DATA_LEN) { -+ printk("%s read from %s fail\n", __func__, path); ++ pr_err("%s read from %s fail\n", __func__, path); + goto exit; + } + @@ -49898,19 +50222,19 @@ index 000000000000..be512ad71415 + for (i = 0 ; i < ETH_ALEN ; i++) { + if (aml_char_is_hex_digit(file_data[PARSE_DIGIT_BASE + i * 3]) == false + || aml_char_is_hex_digit(file_data[PARSE_DIGIT_BASE + i * 3 + 1]) == false) { -+ printk("%s invalid 8-bit hex format for address offset:%u\n", __func__, i); ++ pr_err("%s invalid 8-bit hex format for address offset:%u\n", __func__, i); + goto exit; + } + + if (i < ETH_ALEN - 1 && file_data[PARSE_DIGIT_BASE + i * 3 + 2] != ':') { -+ printk("%s invalid separator after address offset:%u\n", __func__, i); ++ pr_err("%s invalid separator after address offset:%u\n", __func__, i); + goto exit; + } + + temp[0] = file_data[PARSE_DIGIT_BASE + i * 3]; + temp[1] = file_data[PARSE_DIGIT_BASE + i * 3 + 1]; + if (sscanf(temp, "%hhx", &addr[i]) != 1) { -+ printk("%s sscanf fail for address offset:0x%03x\n", __func__, i); ++ pr_err("%s sscanf fail for address offset:0x%03x\n", __func__, i); + goto exit; + } + } @@ -49924,7 +50248,7 @@ index 000000000000..be512ad71415 +} diff --git a/drivers/net/wireless/w1/vmac/wifi_common.h b/drivers/net/wireless/w1/vmac/wifi_common.h new file mode 100644 -index 000000000000..61f27057b2a9 +index 0000000000000000000000000000000000000000..61f27057b2a918b466653f8c5d959f7b43da8744 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_common.h @@ -0,0 +1,32 @@ @@ -49962,7 +50286,7 @@ index 000000000000..61f27057b2a9 +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_csi.h b/drivers/net/wireless/w1/vmac/wifi_csi.h new file mode 100644 -index 000000000000..4ece3936d87e +index 0000000000000000000000000000000000000000..4ece3936d87eac8ae93ba67f857101b91eb0df82 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_csi.h @@ -0,0 +1,51 @@ @@ -50019,7 +50343,7 @@ index 000000000000..4ece3936d87e +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_debug.c b/drivers/net/wireless/w1/vmac/wifi_debug.c new file mode 100644 -index 000000000000..5518b4d835e4 +index 0000000000000000000000000000000000000000..073992910833b8a886f6728558978b41a978dc34 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_debug.c @@ -0,0 +1,192 @@ @@ -50056,38 +50380,38 @@ index 000000000000..5518b4d835e4 + PUTC('\n'); +} + -+ void dump_memory_internel(unsigned char *data,int len) ++ void dump_memory_internal(unsigned char *data,int len) +{ + + unsigned char *cursor=data; + char *xcursor = (char *)data; + int i,j; -+ printk("\n*********************************\n"); ++ pr_debug("\n*********************************\n"); + for ( i = 0; i < len; i++ ) + { + if (( i != 0)&&(( i & 0x0F ) == 0 )) + { + +#ifdef ASCII_IN -+ printk("|"); ++ pr_debug("|"); + for (j=0; j < len; j++) + { + if (((*xcursor)<' ')||((*xcursor)>'~')) + { -+ printk("."); ++ pr_debug("."); + xcursor++; + } + else + { -+ printk("%c",*xcursor++); ++ pr_debug("%c",*xcursor++); + } + } +#endif -+ printk( "\n"); ++ pr_debug( "\n"); + } + -+ printk( "%02x",*cursor++ ); -+ printk(" "); ++ pr_debug( "%02x",*cursor++ ); ++ pr_debug(" "); + } + +#ifdef ASCII_IN @@ -50095,25 +50419,25 @@ index 000000000000..5518b4d835e4 + { + for (i=0; i'~')) + { -+ printk("."); ++ pr_debug("."); + xcursor++; + } + else + { -+ printk("%c",*xcursor++); ++ pr_debug("%c",*xcursor++); + } + } + + } +#endif -+ printk("\n*********************************\n"); ++ pr_debug("\n*********************************\n"); +} + +void address_read( unsigned char* cursor, unsigned char* address ) @@ -50217,7 +50541,7 @@ index 000000000000..5518b4d835e4 + diff --git a/drivers/net/wireless/w1/vmac/wifi_debug.h b/drivers/net/wireless/w1/vmac/wifi_debug.h new file mode 100644 -index 000000000000..bc323abb3cae +index 0000000000000000000000000000000000000000..9ab6637253bb5e057c7aac343e381c513c45bc37 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_debug.h @@ -0,0 +1,230 @@ @@ -50285,8 +50609,8 @@ index 000000000000..bc323abb3cae + AML_DEBUG_CFG80211) + + -+#define DBG_HAL_THR_ENTER() //printk("---xman debug---:%s ++ \n",__FUNCTION__); -+#define DBG_HAL_THR_EXIT() //printk("---xman debug---:%s -- \n",__FUNCTION__); ++#define DBG_HAL_THR_ENTER() //pr_debug("---xman debug---:%s ++ \n",__FUNCTION__); ++#define DBG_HAL_THR_EXIT() //pr_debug("---xman debug---:%s -- \n",__FUNCTION__); + + +extern int aml_debug; @@ -50295,7 +50619,7 @@ index 000000000000..bc323abb3cae + +#define DPRINTF( _m, ...) do { \ + if (aml_debug& (_m)) \ -+ printk(__VA_ARGS__); \ ++ pr_debug(__VA_ARGS__); \ + } while (0) + +enum @@ -50319,24 +50643,24 @@ index 000000000000..bc323abb3cae + if (g_dbg_modules & (_m)) \ + { \ + if(_m == AML_DBG_MODULES_P2P) \ -+ printk("[p2p] <%s> %d "format"",__FUNCTION__, __LINE__, ##__VA_ARGS__); \ ++ pr_debug("[p2p] <%s> %d "format"",__FUNCTION__, __LINE__, ##__VA_ARGS__); \ + else if(_m == AML_DBG_MODULES_RATE_CTR) \ -+ printk("[mi_rate] <%s> %d "format"",__FUNCTION__, __LINE__, ##__VA_ARGS__); \ ++ pr_debug("[mi_rate] <%s> %d "format"",__FUNCTION__, __LINE__, ##__VA_ARGS__); \ + else if(_m == AML_DBG_MODULES_TX) \ -+ printk("[TX] <%s> %d "format"",__FUNCTION__, __LINE__, ##__VA_ARGS__); \ ++ pr_debug("[TX] <%s> %d "format"",__FUNCTION__, __LINE__, ##__VA_ARGS__); \ + else if(_m == AML_DBG_MODULES_TX_ERROR) \ -+ printk("[TX_ERROR] <%s> %d "format"",__FUNCTION__, __LINE__, ##__VA_ARGS__); \ ++ pr_debug("[TX_ERROR] <%s> %d "format"",__FUNCTION__, __LINE__, ##__VA_ARGS__); \ + else if(_m == AML_DBG_MODULES_SCAN) \ -+ printk("[SCAN] <%s> %d "format"",__FUNCTION__, __LINE__, ##__VA_ARGS__); \ ++ pr_debug("[SCAN] <%s> %d "format"",__FUNCTION__, __LINE__, ##__VA_ARGS__); \ + } \ + } while (0) + +#define ERROR_DEBUG_OUT(format,...) do { \ -+ printk("FUNCTION: %s LINE: %d:"format"",__FUNCTION__, __LINE__, ##__VA_ARGS__); \ ++ pr_err("FUNCTION: %s LINE: %d:"format"",__FUNCTION__, __LINE__, ##__VA_ARGS__); \ + } while (0) + +#define AML_OUTPUT(format,...) do { \ -+ printk("<%s> %d:"format"",__FUNCTION__, __LINE__, ##__VA_ARGS__); \ ++ pr_debug("<%s> %d:"format"",__FUNCTION__, __LINE__, ##__VA_ARGS__); \ + } while (0) + + @@ -50347,29 +50671,29 @@ index 000000000000..bc323abb3cae +#define DEBUG_LOCK + +#ifdef DEBUG_LOCK -+#define OS_SPIN_LOCK_IRQ(a, b) {if (aml_debug& (AML_DEBUG_LOCK)) printk("%s,%d,%p, #a ++\n",__func__,__LINE__,(a));spin_lock_irqsave((a), (b));} -+#define OS_SPIN_UNLOCK_IRQ(a, b) {if (aml_debug& (AML_DEBUG_LOCK)) printk("%s,%d,%p,#a --\n",__func__,__LINE__,(a));spin_unlock_irqrestore((a), (b));} ++#define OS_SPIN_LOCK_IRQ(a, b) {if (aml_debug& (AML_DEBUG_LOCK)) pr_debug("%s,%d,%p, #a ++\n",__func__,__LINE__,(a));spin_lock_irqsave((a), (b));} ++#define OS_SPIN_UNLOCK_IRQ(a, b) {if (aml_debug& (AML_DEBUG_LOCK)) pr_debug("%s,%d,%p,#a --\n",__func__,__LINE__,(a));spin_unlock_irqrestore((a), (b));} + + -+#define OS_SPIN_LOCK_BH(a) {if (aml_debug& (AML_DEBUG_LOCK)) printk("%s,%d,%p,#a ++\n",__func__,__LINE__,(a));spin_lock_bh((a));} -+#define OS_SPIN_UNLOCK_BH(a) {if (aml_debug& (AML_DEBUG_LOCK)) printk("%s,%d,%p,#a --\n",__func__,__LINE__,(a));spin_unlock_bh((a));} ++#define OS_SPIN_LOCK_BH(a) {if (aml_debug& (AML_DEBUG_LOCK)) pr_debug("%s,%d,%p,#a ++\n",__func__,__LINE__,(a));spin_lock_bh((a));} ++#define OS_SPIN_UNLOCK_BH(a) {if (aml_debug& (AML_DEBUG_LOCK)) pr_debug("%s,%d,%p,#a --\n",__func__,__LINE__,(a));spin_unlock_bh((a));} + + -+#define OS_SPIN_LOCK(a) {if (aml_debug& (AML_DEBUG_LOCK)) printk("%s,%d,%p,#a ++\n",__func__,__LINE__,(a));spin_lock((a));} -+#define OS_SPIN_UNLOCK(a) {if (aml_debug& (AML_DEBUG_LOCK)) printk("%s,%d,%p,#a --\n",__func__,__LINE__,(a));spin_unlock((a));} ++#define OS_SPIN_LOCK(a) {if (aml_debug& (AML_DEBUG_LOCK)) pr_debug("%s,%d,%p,#a ++\n",__func__,__LINE__,(a));spin_lock((a));} ++#define OS_SPIN_UNLOCK(a) {if (aml_debug& (AML_DEBUG_LOCK)) pr_debug("%s,%d,%p,#a --\n",__func__,__LINE__,(a));spin_unlock((a));} + + -+#define OS_WRITE_LOCK(a) {if (aml_debug& (AML_DEBUG_LOCK)) printk("%s,%d,%p,#a ++\n",__func__,__LINE__,(a));write_lock((a));} -+#define OS_WRITE_UNLOCK(a) {if (aml_debug& (AML_DEBUG_LOCK)) printk("%s,%d,%p,#a --\n",__func__,__LINE__,(a));write_unlock((a));} ++#define OS_WRITE_LOCK(a) {if (aml_debug& (AML_DEBUG_LOCK)) pr_debug("%s,%d,%p,#a ++\n",__func__,__LINE__,(a));write_lock((a));} ++#define OS_WRITE_UNLOCK(a) {if (aml_debug& (AML_DEBUG_LOCK)) pr_debug("%s,%d,%p,#a --\n",__func__,__LINE__,(a));write_unlock((a));} + -+#define OS_WRITE_LOCK_BH(a) {if (aml_debug& (AML_DEBUG_LOCK)) printk("%s,%d,%p,#a ++\n",__func__,__LINE__,(a));write_lock_bh((a));} -+#define OS_WRITE_UNLOCK_BH(a) {if (aml_debug& (AML_DEBUG_LOCK)) printk("%s,%d,%p,#a --\n",__func__,__LINE__,(a));write_unlock_bh((a));} ++#define OS_WRITE_LOCK_BH(a) {if (aml_debug& (AML_DEBUG_LOCK)) pr_debug("%s,%d,%p,#a ++\n",__func__,__LINE__,(a));write_lock_bh((a));} ++#define OS_WRITE_UNLOCK_BH(a) {if (aml_debug& (AML_DEBUG_LOCK)) pr_debug("%s,%d,%p,#a --\n",__func__,__LINE__,(a));write_unlock_bh((a));} + -+#define OS_WRITE_LOCK_IRQ(a, b) {if (aml_debug& (AML_DEBUG_LOCK)) printk("%s,%d,%p,#a ++\n",__func__,__LINE__,(a));write_lock_irqsave((a), (b));} -+#define OS_WRITE_UNLOCK_IRQ(a, b) {if (aml_debug& (AML_DEBUG_LOCK)) printk("%s,%d,%p,#a --\n",__func__,__LINE__,(a));write_unlock_irqrestore((a), (b));} ++#define OS_WRITE_LOCK_IRQ(a, b) {if (aml_debug& (AML_DEBUG_LOCK)) pr_debug("%s,%d,%p,#a ++\n",__func__,__LINE__,(a));write_lock_irqsave((a), (b));} ++#define OS_WRITE_UNLOCK_IRQ(a, b) {if (aml_debug& (AML_DEBUG_LOCK)) pr_debug("%s,%d,%p,#a --\n",__func__,__LINE__,(a));write_unlock_irqrestore((a), (b));} + -+#define OS_MUTEX_LOCK(a) {/*printk("%s,%d,%p, #a ++\n",__func__,__LINE__,(a));*/mutex_lock(a);} -+#define OS_MUTEX_UNLOCK(a) {/*printk("%s,%d,%p, #a --\n",__func__,__LINE__,(a));*/mutex_unlock(a);} ++#define OS_MUTEX_LOCK(a) {/*pr_debug("%s,%d,%p, #a ++\n",__func__,__LINE__,(a));*/mutex_lock(a);} ++#define OS_MUTEX_UNLOCK(a) {/*pr_debug("%s,%d,%p, #a --\n",__func__,__LINE__,(a));*/mutex_unlock(a);} + +#else +#define OS_SPIN_LOCK_IRQ(a, b) {spin_lock_irqsave((a), (b));} @@ -50400,22 +50724,22 @@ index 000000000000..bc323abb3cae +#endif + +#if defined (FPGA) ||defined (CHIP) -+#define PRINT(...) do {printk( __VA_ARGS__ );}while(0) -+#define PRINT_ERR(...) do {printk( __VA_ARGS__ );}while(0) -+#define PUTC( character ) printk("%c" ,character ) -+#define PUTX8(size, value) printk("%02x", value); -+#define PUTU8(value) printk("%u", value); -+#define PUTS( ... ) printk(__VA_ARGS__) -+#define PUTU( number) printk("%d\n",number) -+#define DBG_ENTER() //printk("--->%s ++ \n",__FUNCTION__); -+#define DBG_EXIT() //printk("--->%s -- \n",__FUNCTION__); ++#define PRINT(...) do {pr_debug( __VA_ARGS__ );}while(0) ++#define PRINT_ERR(...) do {pr_err( __VA_ARGS__ );}while(0) ++#define PUTC( character ) pr_debug("%c" ,character ) ++#define PUTX8(size, value) pr_debug("%02x", value); ++#define PUTU8(value) pr_debug("%u", value); ++#define PUTS( ... ) pr_debug(__VA_ARGS__) ++#define PUTU( number) pr_debug("%d\n",number) ++#define DBG_ENTER() //pr_debug("--->%s ++ \n",__FUNCTION__); ++#define DBG_EXIT() //pr_debug("--->%s -- \n",__FUNCTION__); +#endif + + +#ifndef ASSERT +#define ASSERT(exp) do{ \ + if (!(exp)) { \ -+ printk("=>=>=>=>=>assert %s,%d\n",__func__,__LINE__); \ ++ pr_err("=>=>=>=>=>assert %s,%d\n",__func__,__LINE__); \ + /*BUG(); while(1); */ \ + } \ + } while (0); @@ -50426,7 +50750,7 @@ index 000000000000..bc323abb3cae + +#define KASSERT(exp, msg) do { \ + if (unlikely(!(exp))) { \ -+ printk msg; \ ++ pr_err msg ; \ + BUG(); \ + } \ + } while (0) @@ -50435,7 +50759,7 @@ index 000000000000..bc323abb3cae + +void address_print( unsigned char* address ); +void IPv4_address_print( unsigned char* address ); -+void dump_memory_internel(unsigned char *data,int len); ++void dump_memory_internal(unsigned char *data,int len); +void address_read( unsigned char* cursor, unsigned char* address ); + + unsigned short READ_16L( const unsigned char* address ); @@ -50453,10 +50777,10 @@ index 000000000000..bc323abb3cae +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_capture.c b/drivers/net/wireless/w1/vmac/wifi_drv_capture.c new file mode 100644 -index 000000000000..e8eb8ec2fd08 +index 0000000000000000000000000000000000000000..cf2065c59dc0b0f90d7658bb6a022bd86d96a235 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_capture.c -@@ -0,0 +1,593 @@ +@@ -0,0 +1,591 @@ +#include "wifi_drv_capture.h" +#include + @@ -50475,33 +50799,30 @@ index 000000000000..e8eb8ec2fd08 +unsigned int dut_get_reg_frag(int address, int high_bit, int low_bit) +{ + unsigned int tmp = 0; -+ unsigned char error; + struct hw_interface* hif = hif_get_hw_interface(); -+ + int bitwidth = high_bit - low_bit + 1; + int mask = (bitwidth == 32) ? -1 : ((1 << (bitwidth)) - 1); ++ + if ((bitwidth < 1) || (low_bit > 31) || (high_bit > 31)) { -+ error = 1; -+ printk("get reg frag error!addr 0x%x high_bit %d low_bit %d\n", address, high_bit, low_bit); ++ pr_err("get reg frag error!addr 0x%x high_bit %d low_bit %d\n", ++ address, high_bit, low_bit); + } else { + tmp = hif->hif_ops.hi_read_word(address); + tmp >>= low_bit; + tmp &= mask; -+ error = 0; + } ++ + return (tmp); +} + +#define BASE_AHB_TESTBUS_CAPTURE 0x00b00000 +int dut_v32_tx(unsigned int *outbuffer, unsigned int *inbufer, const unsigned long long bitnum) +{ -+ int inoffset = 0; ++ int inoffset; + unsigned long long indata = inbufer[0]; + unsigned long long indatabitnum = 32; -+ int remainbitnum = 0; -+ int len = 0; -+ int outoffset = 0; -+ unsigned long long tmp = 0; ++ int len; ++ int outoffset; + uint64_t inbuffer_len_valid_bit = INBUFFER_LEN_VALID_BIT; + uint64_t inbuffer_len = INBUFFER_LEN; + @@ -50510,15 +50831,22 @@ index 000000000000..e8eb8ec2fd08 + outoffset = len - 1; + do_div(inbuffer_len, 4); + -+ //printk("bitnum111=%016llx\n", bitnum); ++ /* pr_debug("bitnum111=%016llx\n", bitnum); */ + for (inoffset = 0; inoffset < inbuffer_len; inoffset++) { ++ unsigned long long tmp; ++ int remainbitnum; ++ + for (;;) { -+ //printk("bit = %08x, indata=%016llx, ((1<> bitnum); + indatabitnum -= bitnum; + if (indatabitnum < bitnum) { @@ -50530,6 +50858,7 @@ index 000000000000..e8eb8ec2fd08 + indata = indata | (tmp << remainbitnum); + indatabitnum = 32 + remainbitnum; + } ++ + return len * 4; +} + @@ -50548,12 +50877,12 @@ index 000000000000..e8eb8ec2fd08 + ASSERT(len > 0); + + for (;;) { -+ //printk("%s(%d) read addr=0x%4x, data_len=%d\n", __func__, __LINE__,BASE_AHB_TESTBUS_CAPTURE+addr+ a_cnt, MAX_SDIO_ACCESS_LEN); ++ //pr_debug("%s(%d) read addr=0x%4x, data_len=%d\n", __func__, __LINE__,BASE_AHB_TESTBUS_CAPTURE+addr+ a_cnt, MAX_SDIO_ACCESS_LEN); + if (sdio_base != ((BASE_AHB_TESTBUS_CAPTURE + addr + a_cnt) & 0xffff0000)) { + sdio_base = (BASE_AHB_TESTBUS_CAPTURE + addr + a_cnt) & 0xffff0000; + hif->hif_ops.hi_write_reg32(RG_SCFG_FUNC5_BADDR_A, + (unsigned long)(BASE_AHB_TESTBUS_CAPTURE + addr + a_cnt) & 0xffff0000); -+ printk("sdio base addr change ,sdio base addr=0x%08x\n", sdio_base); ++ pr_debug("sdio base addr change ,sdio base addr=0x%08x\n", sdio_base); + } + + if (remain <= MAX_SDIO_ACCESS_LEN) { @@ -50572,19 +50901,19 @@ index 000000000000..e8eb8ec2fd08 + } + } +#if 0 -+ printk("print data start\n"); ++ pr_debug("print data start\n"); + for ( i = 0; i < len ; i++) { -+ printk("0x%02x ", data[i]); ++ pr_debug("0x%02x ", data[i]); + if ( i %16 == 0 ) { -+ printk("\n"); ++ pr_debug("\n"); + } + } -+ printk("\n"); ++ pr_debug("\n"); +#endif + return 0; +} + -+void dut_set_tbus(int trigger) ++static void dut_set_tbus(int trigger) +{ + unsigned int read_tmp = 0; + struct hw_interface* hif = hif_get_hw_interface(); @@ -50616,15 +50945,15 @@ index 000000000000..e8eb8ec2fd08 + stopaddr = hw_if->hif_ops.hi_read_word(TBC_OFFSET_120); + if ( tmp == stopaddr ) { + do_gettimeofday(&t_end); -+ printk("used time %dus stopaddr=0x%08x, =%d\n", ++ pr_debug("used time %dus stopaddr=0x%08x, =%d\n", + _get_tv_us(&t_end, &t_start), stopaddr, i ); + break; + } + tmp = stopaddr; -+ //printk("stopaddr=0x%0x\n", stopaddr); ++ //pr_debug("stopaddr=0x%0x\n", stopaddr); + //msleep(5); + } -+ printk("stopaddr=0x%0x\n", stopaddr); ++ pr_debug("stopaddr=0x%0x\n", stopaddr); +#endif +} + @@ -50659,7 +50988,7 @@ index 000000000000..e8eb8ec2fd08 + g_test_gain = value & 0x3ff; + + new_get_reg(0x00a0810c, &chk_value); -+ printk("check gain 0x%x\n", chk_value); ++ pr_debug("check gain 0x%x\n", chk_value); +} + +int dut_start_capture(unsigned int value) @@ -50697,7 +51026,7 @@ index 000000000000..e8eb8ec2fd08 + dut_set_reg_frag(TBC_OFFSET_114 , 16, 12, trigger); + dut_set_reg_frag(TBC_OFFSET_114 , 8, 8, 1);// enable + -+ printk("start_capture: \ntmode 0x%08x, trg 0x%08x, trigger_delay_time=%d, test_bus=0x%08x\nphy100=0x%08x, phy114=0x%08x\n", ++ pr_debug("start_capture: \ntmode 0x%08x, trg 0x%08x, trigger_delay_time=%d, test_bus=0x%08x\nphy100=0x%08x, phy114=0x%08x\n", + test_mode, trigger, trigger_delay_time, test_bus, + hif->hif_ops.hi_read_word(TBC_OFFSET_100), + hif->hif_ops.hi_read_word(TBC_OFFSET_114)); @@ -50723,11 +51052,11 @@ index 000000000000..e8eb8ec2fd08 + } + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) -+ printk("cap_log file %s\n", fp_path); ++ pr_debug("cap_log file %s\n", fp_path); + fp = filp_open(fp_path, O_RDWR | O_CREAT | O_APPEND | O_TRUNC, 0777); + + if (IS_ERR(fp)) { -+ printk("create file error/n"); ++ pr_err("create file error/n"); + return -1; + } +#endif @@ -50738,7 +51067,7 @@ index 000000000000..e8eb8ec2fd08 + + if (fp) { + filp_close(fp, NULL); -+ printk("close file and exit\n"); ++ pr_debug("close file and exit\n"); + } + + // return the capture buf to mac @@ -50784,16 +51113,16 @@ index 000000000000..e8eb8ec2fd08 +} + + -+//0:use sw stop 1:use hw stop ++/* 0:use sw stop 1:use hw stop */ +int dut_stop_tbus_to_get_sram(struct file *filep, int stop_ctrl, int save_file) +{ + #define HARDWARE_CONTROL 1 -+ unsigned int read_tmp = 0; -+ unsigned int stopaddr = 0; -+ unsigned int *pdata = 0; ++ unsigned int read_tmp; ++ unsigned int stopaddr; ++ unsigned int *pdata; + int len = 0; -+ unsigned int i = 0; -+ int cap_len = 0; ++ unsigned int i; ++ int cap_len; + int temp_addr = 0; + unsigned int stop_flag = 0; + int testbitwidth = 0; @@ -50809,7 +51138,7 @@ index 000000000000..e8eb8ec2fd08 + set_fs(KERNEL_DS); +#endif + -+ //cap_len = hif->hif_ops.hi_read_word(TBC_OFFSET_110); ++ /* cap_len = hif->hif_ops.hi_read_word(TBC_OFFSET_110); */ + cap_len = TBC_ADDR_END_OFFSET-TBC_ADDR_BEGIN_OFFSET; + read_tmp = hif->hif_ops.hi_read_word(TBC_OFFSET_114); + @@ -50852,8 +51181,6 @@ index 000000000000..e8eb8ec2fd08 + AML_OUTPUT("cap_len=0x%08x, stopaddr=0x%08x\n", cap_len, stopaddr); + dut_dump_data(TBC_ADDR_BEGIN_OFFSET, &readbuf[TBC_ADDR_END_OFFSET-stopaddr], stopaddr - TBC_ADDR_BEGIN_OFFSET); + -+ pdata = (unsigned int *)&readbuf[0]; -+ + AML_OUTPUT("testbitwidth=0x%08x\n", testbitwidth); + for (i = 0; i < (TBC_ADDR_END_OFFSET-TBC_ADDR_BEGIN_OFFSET); i += INBUFFER_LEN) { + len += dut_v32_tx((unsigned int *)&testbuf[len], (unsigned int *)&readbuf[i], testbitwidth); @@ -50888,18 +51215,17 @@ index 000000000000..e8eb8ec2fd08 + return 1; +} + -+//0:use sw stop 1:use hw stop ++/* 0:use sw stop 1:use hw stop */ +int iwp_stop_tbus_to_get_sram(unsigned char *buf) +{ -+ unsigned int read_tmp = 0; -+ unsigned int stopaddr = 0; -+ unsigned int *pdata = 0; ++ unsigned int read_tmp; ++ unsigned int stopaddr; ++ unsigned int *pdata; + int len = 0; -+ unsigned int i = 0; -+ int cap_len = 0; ++ unsigned int i; ++ int cap_len; + int temp_addr = 0; -+ int testbitwidth = 0; -+ ++ int testbitwidth; + struct hw_interface* hif = hif_get_hw_interface(); + + cap_len = TBC_ADDR_END_OFFSET-TBC_ADDR_BEGIN_OFFSET; @@ -50908,7 +51234,7 @@ index 000000000000..e8eb8ec2fd08 + testbitwidth = (read_tmp & 0x1f) + 1; + + read_tmp = hif->hif_ops.hi_read_word(TBC_OFFSET_114); -+ read_tmp = (read_tmp | (1 << 10) ); // tbc_stop ++ read_tmp = (read_tmp | (1 << 10) ); /* tbc_stop */ + hif->hif_ops.hi_write_word(TBC_OFFSET_114, read_tmp); + + stopaddr = hif->hif_ops.hi_read_word(TBC_OFFSET_120); @@ -50925,12 +51251,11 @@ index 000000000000..e8eb8ec2fd08 + return 0; + } + -+ hif->hif_ops.hi_write_word(TBC_RAM_SHARE, TBC_RAM_SHARE_MASK); //ram share enable -+ dut_dump_data(stopaddr, &readbuf[0], TBC_ADDR_END_OFFSET-stopaddr); ++ hif->hif_ops.hi_write_word(TBC_RAM_SHARE, TBC_RAM_SHARE_MASK); /* ram share enable */ ++ dut_dump_data(stopaddr, &readbuf[0], TBC_ADDR_END_OFFSET - stopaddr); + AML_OUTPUT("cap_len=0x%08x, stopaddr=0x%08x\n", cap_len, stopaddr); -+ dut_dump_data(TBC_ADDR_BEGIN_OFFSET, &readbuf[TBC_ADDR_END_OFFSET-stopaddr], stopaddr - TBC_ADDR_BEGIN_OFFSET); -+ -+ pdata = (unsigned int *)&readbuf[0]; ++ dut_dump_data(TBC_ADDR_BEGIN_OFFSET, &readbuf[TBC_ADDR_END_OFFSET - stopaddr], ++ stopaddr - TBC_ADDR_BEGIN_OFFSET); + + AML_OUTPUT("testbitwidth=0x%08x\n", testbitwidth); + for (i = 0; i < (TBC_ADDR_END_OFFSET-TBC_ADDR_BEGIN_OFFSET); i += INBUFFER_LEN) { @@ -50938,39 +51263,39 @@ index 000000000000..e8eb8ec2fd08 + } + + pdata = (unsigned int *)&testbuf[0]; -+ for (i = 0; i < 4096; i += 4) { -+ /*bit6:1 is csi data, 4096 can be changed as uplay buffer*/ ++ for (i = 0; i < 4096; i += 4) { ++ /* bit6:1 is csi data, 4096 can be changed as uplay buffer */ + *pdata = *pdata & 0x0000007e; + *buf = *pdata >> 1; + buf++; + pdata++; + } ++ + AML_OUTPUT("handle capture data complete\n"); + return 1; +} + -+ +unsigned char dut_set_reg_frag(int address, int bit_end, int bit_start, int value) +{ -+ unsigned int tmp = 0; ++ unsigned int tmp; + unsigned char error; -+ int bitwidth = bit_end-bit_start + 1; ++ int bitwidth = bit_end - bit_start + 1; + int max_value = (bitwidth == 32) ? -1 : ((1 << (bitwidth)) - 1); + + struct hw_interface* hif = hif_get_hw_interface(); + tmp = hif->hif_ops.hi_read_word(address); -+ //printk("tmp is 0x%x\n", tmp); ++ /* pr_debug("tmp is 0x%x\n", tmp); */ + + if ((bitwidth < 1) || (bit_start > 31) || (bit_end > 31)) { + while (1) { -+ printk("----------------->Set_RegFragment is halt.\n"); ++ pr_debug("----------------->Set_RegFragment is halt.\n"); + } + error = 1; + } else { + error = 0; -+ tmp &= ~(max_value << bit_start); // clear [bit_end: bit_start] ++ tmp &= ~(max_value << bit_start); /* clear [bit_end: bit_start] */ + tmp |= ((value&max_value) << bit_start); -+ //printk("addr 0x%x tmp2 is 0x%x\n", address, tmp); ++ /* pr_debug("addr 0x%x tmp2 is 0x%x\n", address, tmp); */ + hif->hif_ops.hi_write_word(address, tmp); + } + @@ -50979,32 +51304,30 @@ index 000000000000..e8eb8ec2fd08 + +int dut_bt_start_capture(unsigned int value) +{ -+ -+ unsigned int wf_bt_mode = 0; -+ struct hw_interface* hif = NULL; -+ ++ unsigned int wf_bt_mode; ++ struct hw_interface *hif; + int test_mode = value & 0x1; + int trigger = (value >> 4) & 0x1; + int test_bus = (value >> 8) & 0xff; + + wf_bt_mode = (value >> 31) & 0x1; + hif = hif_get_hw_interface(); -+ g_test_bus = test_bus; // for log file name ++ g_test_bus = test_bus; /* for log file name */ + -+ hif->hif_ops.hi_write_word(0x00a0b000, 0xffffffff); //phy clock mask ++ hif->hif_ops.hi_write_word(0x00a0b000, 0xffffffff); /* phy clock mask */ + test_bus = (0x01 << 24) | (test_bus << 16) | 0x0008; -+ hif->hif_ops.hi_write_word(TBC_OFFSET_100, test_bus);//test bus enable -+ hif->hif_ops.hi_write_word(TBC_OFFSET_108, 0x00000000);//valid -+ hif->hif_ops.hi_write_word(TBC_OFFSET_10C, 0x00020000);//config testbus capture address begin -+ hif->hif_ops.hi_write_word(TBC_OFFSET_110, TBC_ADDR_END_OFFSET);//config testbus capture address end -+ hif->hif_ops.hi_write_word(TBC_RAM_SHARE, 0xf000007f); //ram share enable ++ hif->hif_ops.hi_write_word(TBC_OFFSET_100, test_bus); /* test bus enable */ ++ hif->hif_ops.hi_write_word(TBC_OFFSET_108, 0x00000000); /* valid */ ++ hif->hif_ops.hi_write_word(TBC_OFFSET_10C, 0x00020000); /*config testbus capture address begin */ ++ hif->hif_ops.hi_write_word(TBC_OFFSET_110, TBC_ADDR_END_OFFSET); /* config testbus capture address end */ ++ hif->hif_ops.hi_write_word(TBC_RAM_SHARE, 0xf000007f); /* ram share enable */ + -+ hif->hif_ops.hi_write_word(TBC_OFFSET_114, 0x0000051c); //ram share enable ++ hif->hif_ops.hi_write_word(TBC_OFFSET_114, 0x0000051c); /* ram share enable */ + -+ printk("start_capture: \ntmode 0x%08x, trg 0x%08x, test_bus=0x%08x\nphy100=0x%08x, phy114=0x%08x\n", -+ test_mode, trigger, test_bus, -+ hif->hif_ops.hi_read_word(TBC_OFFSET_100), -+ hif->hif_ops.hi_read_word(TBC_OFFSET_114)); ++ pr_debug("start_capture: \ntmode 0x%08x, trg 0x%08x, test_bus=0x%08x\nphy100=0x%08x, phy114=0x%08x\n", ++ test_mode, trigger, test_bus, ++ hif->hif_ops.hi_read_word(TBC_OFFSET_100), ++ hif->hif_ops.hi_read_word(TBC_OFFSET_114)); + + return 0; +} @@ -51025,7 +51348,7 @@ index 000000000000..e8eb8ec2fd08 + } + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) -+ printk("cap_log file %s\n", fp_path); ++ pr_debug("cap_log file %s\n", fp_path); + fp = filp_open(fp_path,O_RDWR | O_CREAT | O_APPEND | O_TRUNC, 0777); + + if (IS_ERR(fp)) { @@ -51034,12 +51357,11 @@ index 000000000000..e8eb8ec2fd08 + } +#endif + -+ + dut_stop_tbus_to_get_sram(fp, 0, 1); + + if (fp) { + filp_close(fp, NULL); -+ printk("close file and exit\n"); ++ pr_debug("close file and exit\n"); + } + + g_test_bus = 0; @@ -51052,35 +51374,35 @@ index 000000000000..e8eb8ec2fd08 +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_capture.h b/drivers/net/wireless/w1/vmac/wifi_drv_capture.h new file mode 100644 -index 000000000000..e3ac3e35defe +index 0000000000000000000000000000000000000000..376eabdde7f328e24a23b62343f3cc7014116304 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_capture.h @@ -0,0 +1,22 @@ -+#ifndef __WIFI_DEV_CAPTURE_H -+#define __WIFI_DEV_CAPTURE_H -+#include "wifi_hal_com.h" -+ -+#define TESTBUSBUF_LEN 0x8000 -+ -+int dut_start_capture(unsigned int value); -+int dut_stop_capture(void); -+ -+//0:use sw stop 1:use hw stop -+int dut_stop_tbus_to_get_sram(struct file *filep, int stop_ctrl, int save_file); -+unsigned char dut_set_reg_frag(int address, int bit_end, int bit_start, int value); -+int dut_bt_start_capture(unsigned int value ); -+int dut_bt_stop_capture(void); -+unsigned int dut_get_reg_frag(int address, int high_bit, int low_bit); -+int dut_v32_tx(unsigned int *outbuffer, unsigned int *inbufer, const unsigned long long bitnum); -+int dut_dump_data(unsigned int addr, unsigned char *data, int len); -+void dut_set_bcap_log_name(unsigned int value); -+void dut_set_gain(unsigned int value); -+int iwp_stop_tbus_to_get_sram(unsigned char *buf); -+ -+#endif ++#ifndef __WIFI_DEV_CAPTURE_H ++#define __WIFI_DEV_CAPTURE_H ++#include "wifi_hal_com.h" ++ ++#define TESTBUSBUF_LEN 0x8000 ++ ++int dut_start_capture(unsigned int value); ++int dut_stop_capture(void); ++ ++//0:use sw stop 1:use hw stop ++int dut_stop_tbus_to_get_sram(struct file *filep, int stop_ctrl, int save_file); ++unsigned char dut_set_reg_frag(int address, int bit_end, int bit_start, int value); ++int dut_bt_start_capture(unsigned int value ); ++int dut_bt_stop_capture(void); ++unsigned int dut_get_reg_frag(int address, int high_bit, int low_bit); ++int dut_v32_tx(unsigned int *outbuffer, unsigned int *inbufer, const unsigned long long bitnum); ++int dut_dump_data(unsigned int addr, unsigned char *data, int len); ++void dut_set_bcap_log_name(unsigned int value); ++void dut_set_gain(unsigned int value); ++int iwp_stop_tbus_to_get_sram(unsigned char *buf); ++ ++#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_config.c b/drivers/net/wireless/w1/vmac/wifi_drv_config.c new file mode 100644 -index 000000000000..b6c89f7e239b +index 0000000000000000000000000000000000000000..1d7c624d23dda483b19cbeeff2da2481f81f50d5 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_config.c @@ -0,0 +1,449 @@ @@ -51111,7 +51433,7 @@ index 000000000000..b6c89f7e239b + struct drv_private *drv_priv = ( struct drv_private *)dev; + struct hal_private* hal_priv = hal_get_priv(); + -+ printk("%s(%d) id 0x%x data 0x%x\n", __func__, __LINE__, id, data); ++ pr_debug("%s(%d) id 0x%x data 0x%x\n", __func__, __LINE__, id, data); + + switch (id) { + case CHIP_PARAM_TXCHAINMASK: @@ -51135,28 +51457,28 @@ index 000000000000..b6c89f7e239b + break; + + case CHIP_PARAM_AMPDU: -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + drv_priv->drv_config.cfg_txaggr = data; + drv_priv->drv_config.cfg_rxaggr = data; + break; + + case CHIP_PARAM_AMPDU_RX: -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + drv_priv->drv_config.cfg_rxaggr = data; + break; + + case CHIP_PARAM_AMPDU_LIMIT: -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + drv_priv->drv_config.cfg_ampdu_limit = data; + break; + + case CHIP_PARAM_AMPDU_SUBFRAMES: -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + drv_priv->drv_config.cfg_ampdu_subframes = data; + break; + + case CHIP_PARAM_AGGR_PROT: -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + drv_priv->drv_config.cfg_aggr_prot = data; + break; + @@ -51165,12 +51487,12 @@ index 000000000000..b6c89f7e239b + break; + + case CHIP_PARAM_BURST_ACK: -+ printk(" %s %d CHIP_PARAM_BURST_ACK\n",__func__,__LINE__); ++ pr_debug(" %s %d CHIP_PARAM_BURST_ACK\n",__func__,__LINE__); + drv_priv->drv_config.cfg_burst_ack = data; + break; + + case CHIP_PARAM_ACK_POLICY: -+ printk(" %s %d CHIP_PARAM_ACK_POLICY\n",__func__,__LINE__); ++ pr_debug(" %s %d CHIP_PARAM_ACK_POLICY\n",__func__,__LINE__); + drv_priv->drv_config.cfg_ampduackpolicy= data; + break; + @@ -51233,7 +51555,7 @@ index 000000000000..b6c89f7e239b + break; + + case CHIP_PARAM_SHORTPREAMBLE: -+ printk("%s(%d),Before set short preamble.\n\n",__func__,__LINE__); ++ pr_debug("%s(%d),Before set short preamble.\n\n",__func__,__LINE__); + drv_priv->drv_config.cfg_shortpreamble = data; + break; + @@ -51287,27 +51609,27 @@ index 000000000000..b6c89f7e239b + break; + + case CHIP_PARAM_AMPDU: -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + supported = drv_priv->drv_config.cfg_txaggr; + break; + + case CHIP_PARAM_AMPDU_RX: -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + supported = drv_priv->drv_config.cfg_rxaggr; + break; + + case CHIP_PARAM_AMPDU_LIMIT: -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + supported = drv_priv->drv_config.cfg_ampdu_limit; + break; + + case CHIP_PARAM_AMPDU_SUBFRAMES: -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + supported = drv_priv->drv_config.cfg_ampdu_subframes; + break; + + case CHIP_PARAM_AGGR_PROT: -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + supported = drv_priv->drv_config.cfg_aggr_prot; + break; + @@ -51407,7 +51729,7 @@ index 000000000000..b6c89f7e239b + return supported; +} + -+unsigned int process_drv_cfg_content(char *varbuf, unsigned int len) ++static unsigned int process_drv_cfg_content(char *varbuf, unsigned int len) +{ + char *dp; + bool findNewline; @@ -51456,7 +51778,7 @@ index 000000000000..b6c89f7e239b + +extern unsigned char get_s16_item(char *varbuf, int len, char *item, short *item_value); +extern unsigned char get_s8_item(char *varbuf, int len, char *item, char *item_value); -+unsigned char parse_drv_cfg_param(char *varbuf, int len) ++static unsigned char parse_drv_cfg_param(char *varbuf, int len) +{ + struct drv_private *drv_priv = drv_get_drv_priv(); + @@ -51535,7 +51857,7 @@ index 000000000000..b6c89f7e239b +} diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_config.h b/drivers/net/wireless/w1/vmac/wifi_drv_config.h new file mode 100644 -index 000000000000..039ef3bebff5 +index 0000000000000000000000000000000000000000..039ef3bebff5d3380090fa56ca44cee3f9e1814f --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_config.h @@ -0,0 +1,169 @@ @@ -51710,10 +52032,10 @@ index 000000000000..039ef3bebff5 +#endif // _AUTO_CONFIG_H diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_if.c b/drivers/net/wireless/w1/vmac/wifi_drv_if.c new file mode 100644 -index 000000000000..b788eddb7e24 +index 0000000000000000000000000000000000000000..4e28aa3072838f6f07ce658151575262c5bcb131 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_if.c -@@ -0,0 +1,446 @@ +@@ -0,0 +1,451 @@ +/* + **************************************************************************************** + * @@ -51744,7 +52066,7 @@ index 000000000000..b788eddb7e24 + hal_priv->dhcp_offload = dhcp_offload; + hal_priv->hal_ops.hal_init(drv_priv); + drv_hal_workitem_inital(); -+ return ; ++ return; +} + +int drv_hal_detach(void) @@ -51753,7 +52075,7 @@ index 000000000000..b788eddb7e24 + + hal_priv->hal_ops.hal_exit(); + drv_hal_workitem_free(); -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + return 0; +} + @@ -51771,7 +52093,7 @@ index 000000000000..b788eddb7e24 +void drv_hal_setupratetable(struct drv_rate_table *rt) +{ + int i; -+ unsigned char code, cix; ++ unsigned char code; + + if (rt->dot11rate_to_idx[0] != 0) + { @@ -51782,6 +52104,8 @@ index 000000000000..b788eddb7e24 + memset( rt->dot11rate_to_idx, 0xff, sizeof(rt->dot11rate_to_idx)); + for (i = 0; i < rt->rateCount; i++) + { ++ unsigned char cix; ++ + if ((rt->info[i].phy == CCK) || (rt->info[i].phy == WOFDM)) + { + code = WIFINET_GET_RATE_VAL (rt->info[i].dot11Rate); @@ -51993,7 +52317,7 @@ index 000000000000..b788eddb7e24 + unsigned short rateix, + int shortPreamble) +{ -+ unsigned int bitsPerSymbol, numBits, numSymbols, phyTime, txTime; ++ unsigned int numBits, phyTime, txTime; + unsigned int kbps; + + kbps = rates->info[rateix].rateKbps; @@ -52015,6 +52339,8 @@ index 000000000000..b788eddb7e24 + + case WIFINET_T_OFDM: + { ++ unsigned int bitsPerSymbol, numSymbols; ++ + /* full rate channel */ + bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; + @@ -52048,13 +52374,14 @@ index 000000000000..b788eddb7e24 +drv_hal_workitem_task(SYS_TYPE iparam) +{ + struct hal_private *hal_priv = hal_get_priv(); -+ unsigned short STATUS; + unsigned char *EltPtr =NULL; + struct _CO_SHARED_FIFO* pWorkFifo = &hal_priv->WorkFifo; + struct hal_work_task *pWorkTask = NULL; + + while (CO_SharedFifoEmpty(pWorkFifo, CO_WORK_FREE)) + { ++ unsigned short STATUS; ++ + STATUS = CO_SharedFifoGet(pWorkFifo, CO_WORK_FREE, 1, &EltPtr); + ASSERT(STATUS == CO_STATUS_OK); + pWorkTask = (struct hal_work_task *)EltPtr; @@ -52107,7 +52434,7 @@ index 000000000000..b788eddb7e24 + task_repeat++; + + if ((task_repeat % 10) == 0) { -+ printk("task is %p\n", task); ++ pr_debug("task is %p\n", task); + task_repeat = 0; + } + @@ -52148,12 +52475,12 @@ index 000000000000..b788eddb7e24 + CO_SharedFifoInit(&hal_priv->WorkFifo, (SYS_TYPE)hal_priv->WorkFifoBuf, (void *)hal_priv->WorkFifoBuf, + WORK_ITEM_NUM, sizeof(struct hal_work_task), CO_SF_WORK_NBR); + -+ printk("%s hal_priv->WorkFifo:%p\n", __func__, &hal_priv->WorkFifo); ++ pr_debug("%s hal_priv->WorkFifo:%p\n", __func__, &hal_priv->WorkFifo); + res = (SYS_TYPE)hal_priv->hal_ops.hal_reg_task(drv_hal_workitem_task); + + if (res < 0) { + ASSERT(0); -+ printk("WorkFifo_task_id error !\n"); ++ pr_err("WorkFifo_task_id error !\n"); + } else { + hal_priv->WorkFifo_task_id = res; + } @@ -52162,7 +52489,7 @@ index 000000000000..b788eddb7e24 + diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_if.h b/drivers/net/wireless/w1/vmac/wifi_drv_if.h new file mode 100644 -index 000000000000..ec031a49edf6 +index 0000000000000000000000000000000000000000..4e3357e58bcb56e06e543822b43e5d2492e03b5e --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_if.h @@ -0,0 +1,528 @@ @@ -52205,7 +52532,7 @@ index 000000000000..ec031a49edf6 +#define HAL_RATECTRL_TX_SEND_SUCCESS 0X800 +#define HAL_RATECTRL_USE_SAMPLE_RATE 0X1000 + -+#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ ++#define HAL_BEACON_PERIOD 0x0001ffff /* beacon interval period */ +#define WLAN_CTRL_FRAME_SIZE 14 /* ACK+FCS */ +#define CO_WORK_GET 0 +#define CO_WORK_FREE 1 @@ -52491,8 +52818,8 @@ index 000000000000..ec031a49edf6 + struct hal_private* hal_priv = hal_get_priv(); + + if (hal_priv->dhcp_offload == 1) { -+ printk("NOTICE: DHCP OFFLOAD function is enabled, caller must ensure upper layer's dhcp module is closed.\n"); -+ printk("Because under this situation, the FW will handle the dhcp pkts and never transmit to driver.\n"); ++ pr_notice("NOTICE: DHCP OFFLOAD function is enabled, caller must ensure upper layer's dhcp module is closed.\n"); ++ pr_notice("Because under this situation, the FW will handle the dhcp pkts and never transmit to driver.\n"); + DPRINTF(AML_DEBUG_HAL, "%s %d: ip %03d.%03d.%03d.%03d\n",__func__,__LINE__, + (ip >> 24) & 0xff, (ip >> 16) & 0xff, (ip >> 8) & 0xff, ip & 0xff); + hal_priv->hal_ops.phy_set_dhcp(wnet_vif_id, ip); @@ -52696,10 +53023,10 @@ index 000000000000..ec031a49edf6 + diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_main.c b/drivers/net/wireless/w1/vmac/wifi_drv_main.c new file mode 100644 -index 000000000000..abeda5f1221a +index 0000000000000000000000000000000000000000..b7b169b3fa336ad88ad455884b83573319d65d40 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_main.c -@@ -0,0 +1,2483 @@ +@@ -0,0 +1,2544 @@ +/* + **************************************************************************************** + * @@ -52708,7 +53035,7 @@ index 000000000000..abeda5f1221a + * Project: 11N 80211 driver layer Software + * + * Description: -+ * This file contains the main implementation of the DRIVER layer. Most member ++ * This file contains the main implementation of the DRIVER layer. Most member + * functions of the DRIVER layer are defined here. + * + * @@ -52716,6 +53043,7 @@ index 000000000000..abeda5f1221a + */ +#include +#include ++#include +#include + +#include "wifi_drv_power.h" @@ -52736,11 +53064,10 @@ index 000000000000..abeda5f1221a +#include "wifi_mac_tx_reg.h" +#include "wifi_mac_xmit.h" + -+ +const unsigned char drv_bcast_mac[WIFINET_ADDR_LEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + -+static unsigned int drv_phy_reg_sta_id( struct drv_private *drv_priv, -+ unsigned char wnet_vif_id,unsigned short StaAid, unsigned char *pMac, unsigned char encrypt); ++static unsigned int drv_phy_reg_sta_id(struct drv_private *drv_priv, unsigned char wnet_vif_id, ++ unsigned short StaAid, unsigned char *pMac, unsigned char encrypt); + +static struct drv_private drv_priv; + @@ -52750,15 +53077,13 @@ index 000000000000..abeda5f1221a +extern int hal_tx_flush(unsigned char vid); +extern unsigned char wifi_hal_probe_done; + -+ -+struct drv_private* drv_get_drv_priv(void) ++struct drv_private *drv_get_drv_priv(void) +{ + return &drv_priv; +} + +int drv_rate_setup(struct drv_private *drv_priv, enum wifi_mac_macmode mode) +{ -+ + struct drv_rate_table *rt = drv_hal_get_rate_tbl(mode); + + if (rt == NULL) @@ -52767,13 +53092,13 @@ index 000000000000..abeda5f1221a + return 0; + } + -+ //do rate index and vendor_rate_code mapping. ++ /* do rate index and vendor_rate_code mapping. */ + drv_hal_setupratetable(rt); + DRV_MINSTREL_LOCK_INIT(drv_priv); + drv_priv->drv_currratetable = rt; -+ drv_priv->drv_protect_rateindex = 0; ++ drv_priv->drv_protect_rateindex = 0; + -+ //do rate index and dot11Code mapping. ++ /* do rate index and dot11Code mapping. */ + if (drv_priv->net_ops->wifi_mac_rate_init) + { + drv_priv->net_ops->wifi_mac_rate_init(drv_priv->wmac, mode, rt); @@ -52781,20 +53106,16 @@ index 000000000000..abeda5f1221a + return 1; +} + -+ -+ -+static void -+drv_set_cfg_tx_power_limit( struct drv_private *drv_priv, -+ unsigned short cfg_txpowlimit) ++static void drv_set_cfg_tx_power_limit(struct drv_private *drv_priv, ++ unsigned short cfg_txpowlimit) +{ -+ + drv_priv->drv_config.cfg_txpowlimit = cfg_txpowlimit; +} + +void +drv_update_tx_pwr(struct drv_private *drv_priv, unsigned short txpowerdb) +{ -+ unsigned int txpow = 0, cfg_txpowlimit = 0; ++ unsigned int txpow = 0, cfg_txpowlimit; + + cfg_txpowlimit = drv_priv->drv_config.cfg_txpowlimit; + @@ -52803,22 +53124,21 @@ index 000000000000..abeda5f1221a + drv_priv->drv_curtxpower = txpow; + } + -+ + txpow = IW_MAX_TXPOWER; + if (drv_priv->net_ops->wifi_mac_update_txpower) + drv_priv->net_ops->wifi_mac_update_txpower(drv_priv->wmac, + drv_priv->drv_curtxpower, txpow); +} + -+static void -+drv_assoc_proc( struct drv_private *drv_priv, -+ void * nsta, int isnew, int b_uapsd) ++static void drv_assoc_proc(struct drv_private *drv_priv, void *nsta, ++ int isnew, int b_uapsd) +{ + struct aml_driver_nsta *drv_sta = DRIVER_NODE(nsta); -+ int tid_index; + + if (!isnew) + { ++ int tid_index; ++ + for (tid_index = 0; tid_index < WME_NUM_TID; tid_index++) + { + if (drv_priv->drv_config.cfg_txaggr) @@ -52831,21 +53151,22 @@ index 000000000000..abeda5f1221a + } + } + } ++ + drv_sta->sta_cleanup = 0; + drv_sta->sta_powesave = 0; + drv_sta->sta_isuapsd = 0; -+ drv_sta->sta_isuapsd = b_uapsd ; ++ drv_sta->sta_isuapsd = b_uapsd ; +} + +int drv_channel_init(struct drv_private *drv_priv, unsigned int cc) +{ -+ unsigned int wMode; -+ -+ wMode = drv_priv->drv_config.cfg_modesupport; -+ printk("%s %d \n",__func__,__LINE__); ++ pr_debug("%s %d \n",__func__,__LINE__); + if (drv_priv->net_ops->wifi_mac_setup_channel_list) + { -+ drv_priv->net_ops->wifi_mac_setup_channel_list(drv_priv->wmac, wMode,cc); ++ unsigned int wMode; ++ ++ wMode = drv_priv->drv_config.cfg_modesupport; ++ drv_priv->net_ops->wifi_mac_setup_channel_list(drv_priv->wmac, wMode, cc); + } + + return 0; @@ -52866,73 +53187,75 @@ index 000000000000..abeda5f1221a + aml_enable_wifi(); +} + -+static void drv_scan_start_ex( SYS_TYPE param1,SYS_TYPE param2, -+ SYS_TYPE param3,SYS_TYPE param4,SYS_TYPE param5) ++static void drv_scan_start_ex(SYS_TYPE param1, SYS_TYPE param2, ++ SYS_TYPE param3, SYS_TYPE param4, ++ SYS_TYPE param5) +{ + struct drv_private *drv_priv = (struct drv_private *)param1; -+ unsigned int data = 0; ++ unsigned int data; + -+ if(drv_priv->drv_scanning == 0) ++ if (drv_priv->drv_scanning == 0) + { + driv_ps_wakeup(drv_priv); + } + drv_priv->drv_scanning = 1; + data = drv_priv->stop_noa_flag << 8 | drv_priv->drv_scanning; + drv_hal_scancmd(data); -+ //sleep at scan end -+ // driv_ps_sleep(drv_priv); -+ ++ /* sleep at scan end */ ++ /* driv_ps_sleep(drv_priv); */ +} + -+static void drv_scan_start( struct drv_private *drv_priv) ++static void drv_scan_start(struct drv_private *drv_priv) +{ -+ drv_hal_add_workitem((WorkHandler)drv_scan_start_ex, NULL, (SYS_TYPE)drv_priv, 0, 0, 0, 0); ++ drv_hal_add_workitem((WorkHandler)drv_scan_start_ex, NULL, ++ (SYS_TYPE)drv_priv, 0, 0, 0, 0); +} + -+static void drv_fw_recovery( struct drv_private *drv_priv) ++static void drv_fw_recovery(struct drv_private *drv_priv) +{ + aml_w1_fw_recovery(); +} + -+ +static void -+drv_scan_end_ex( SYS_TYPE param1,SYS_TYPE param2,SYS_TYPE param3, -+ SYS_TYPE param4,SYS_TYPE param5) ++drv_scan_end_ex(SYS_TYPE param1, SYS_TYPE param2, SYS_TYPE param3, ++ SYS_TYPE param4, SYS_TYPE param5) +{ + struct drv_private *drv_priv = (struct drv_private *)param1; + unsigned char prescanning = drv_priv->drv_scanning; -+ unsigned int data = 0; -+ //wakeup at scan start -+ // driv_ps_wakeup(drv_priv); ++ unsigned int data; ++ ++ /* wakeup at scan start */ ++ /* driv_ps_wakeup(drv_priv); */ + drv_priv->drv_scanning = 0; + data = drv_priv->stop_noa_flag << 8 | drv_priv->drv_scanning; + drv_hal_scancmd(data); -+ if(prescanning == 1) ++ ++ if (prescanning == 1) + { + driv_ps_sleep(drv_priv); + } +} + -+static void -+drv_scan_end( struct drv_private *drv_priv) ++static void drv_scan_end(struct drv_private *drv_priv) +{ + drv_hal_add_workitem((WorkHandler)drv_scan_end_ex, -+ NULL, (SYS_TYPE)drv_priv, 0, 0, 0, 0); ++ NULL, (SYS_TYPE)drv_priv, 0, 0, 0, 0); +} + +unsigned char print_ctl = 0; +extern unsigned char print_type; -+static void drv_print_fwlog_ex( SYS_TYPE param1,SYS_TYPE param2,SYS_TYPE param3, -+ SYS_TYPE param4,SYS_TYPE param5) ++ ++static void drv_print_fwlog_ex(SYS_TYPE param1, SYS_TYPE param2, SYS_TYPE param3, ++ SYS_TYPE param4, SYS_TYPE param5) +{ -+ unsigned char* logbuf_ptr = (unsigned char *)param1; ++ unsigned char *logbuf_ptr = (unsigned char *)param1; + int databyte = (int)param2; -+ unsigned char new_string[64] = {0}; ++ unsigned char new_string[64] = { 0 }; + int i = 0; + -+ if (print_type == 1) //auto ++ if (print_type == 1) /* auto */ + { -+ /*rotate print*/ ++ /* rotate print */ + print_ctl = print_ctl ^ 1; + databyte = databyte >> 1; + if (print_ctl == 0) @@ -52944,6 +53267,7 @@ index 000000000000..abeda5f1221a + /* print process */ + AML_OUTPUT("logbuf_ptr 0x%x\n", logbuf_ptr); + AML_OUTPUT("fw_log:\n"); ++ + while (databyte--) + { + if ((*logbuf_ptr == '\n') || (i == 63)) { @@ -52958,6 +53282,7 @@ index 000000000000..abeda5f1221a + + logbuf_ptr++; + } ++ + /* exit the loop and need to print the remaining characters */ + AML_OUTPUT("%s", new_string); + @@ -52967,12 +53292,13 @@ index 000000000000..abeda5f1221a +static void drv_print_fwlog(unsigned char *logbuf_ptr, int databyte) +{ + drv_hal_add_workitem((WorkHandler)drv_print_fwlog_ex, -+ NULL, (SYS_TYPE)logbuf_ptr, (SYS_TYPE)databyte, 0, 0, 0); ++ NULL, (SYS_TYPE)logbuf_ptr, (SYS_TYPE)databyte, ++ 0, 0, 0); +} + +static void -+drv_connect_start_ex( SYS_TYPE param1,SYS_TYPE param2, -+ SYS_TYPE param3,SYS_TYPE param4,SYS_TYPE param5) ++drv_connect_start_ex(SYS_TYPE param1, SYS_TYPE param2, ++ SYS_TYPE param3, SYS_TYPE param4, SYS_TYPE param5) +{ + struct drv_private *drv_priv = (struct drv_private *)param1; + @@ -52983,84 +53309,93 @@ index 000000000000..abeda5f1221a + drv_priv->drv_connetting = 1; +} + -+ -+ +static void -+drv_connect_end_ex( SYS_TYPE param1,SYS_TYPE param2, -+ SYS_TYPE param3,SYS_TYPE param4,SYS_TYPE param5) ++drv_connect_end_ex(SYS_TYPE param1, SYS_TYPE param2, ++ SYS_TYPE param3, SYS_TYPE param4, SYS_TYPE param5) +{ + struct drv_private *drv_priv = (struct drv_private *)param1; + -+ unsigned char preconnetting = drv_priv->drv_connetting ; ++ unsigned char preconnetting = drv_priv->drv_connetting; ++ ++ drv_priv->drv_connetting = 0; + -+ drv_priv->drv_connetting = 0 ; -+ if(preconnetting == 1) ++ if (preconnetting == 1) + { + driv_ps_sleep(drv_priv); + + } -+ +} ++ +static void -+drv_connect_start( struct drv_private *drv_priv) ++drv_connect_start(struct drv_private *drv_priv) +{ + drv_hal_add_workitem((WorkHandler)drv_connect_start_ex, -+ NULL, (SYS_TYPE)drv_priv, 0, 0, 0, 0); ++ NULL, (SYS_TYPE)drv_priv, 0, 0, 0, 0); +} + +static void -+drv_connect_end( struct drv_private *drv_priv) ++drv_connect_end(struct drv_private *drv_priv) +{ + drv_hal_add_workitem((WorkHandler)drv_connect_end_ex, -+ NULL, (SYS_TYPE)drv_priv, 0, 0, 0, 0); ++ NULL, (SYS_TYPE)drv_priv, 0, 0, 0, 0); +} + -+static void drv_set_channel_rssi_ex( SYS_TYPE param1,SYS_TYPE param2,SYS_TYPE param3, SYS_TYPE param4,SYS_TYPE param5) ++static void drv_set_channel_rssi_ex(SYS_TYPE param1, SYS_TYPE param2, ++ SYS_TYPE param3, SYS_TYPE param4, ++ SYS_TYPE param5) +{ -+ struct hal_private* hal_priv = hal_get_priv(); ++ struct hal_private *hal_priv = hal_get_priv(); + + hal_priv->hal_ops.phy_set_channel_rssi(param1); +} + -+ -+static void drv_set_channel_rssi( struct drv_private *drv_priv, unsigned char rssi) ++static void drv_set_channel_rssi(struct drv_private *drv_priv, unsigned char rssi) +{ + static unsigned char pre_rssi = 0; + + if (pre_rssi != rssi) { + pre_rssi = rssi; -+ drv_hal_add_workitem((WorkHandler)drv_set_channel_rssi_ex, NULL, (SYS_TYPE)rssi, 0, 0, 0, 0); ++ drv_hal_add_workitem((WorkHandler)drv_set_channel_rssi_ex, NULL, ++ (SYS_TYPE)rssi, 0, 0, 0, 0); + } +} + -+static void drv_set_tx_power_accord_rssi_ex( SYS_TYPE param1,SYS_TYPE param2,SYS_TYPE param3, SYS_TYPE param4,SYS_TYPE param5) ++static void drv_set_tx_power_accord_rssi_ex(SYS_TYPE param1, SYS_TYPE param2, ++ SYS_TYPE param3, SYS_TYPE param4, ++ SYS_TYPE param5) +{ -+ struct hal_private* hal_priv = hal_get_priv(); ++ struct hal_private *hal_priv = hal_get_priv(); + + hal_priv->hal_ops.phy_set_tx_power_accord_rssi(param1, param2, param3, param4); +} + -+ -+static void drv_set_tx_power_accord_rssi( struct drv_private *drv_priv, struct hal_channel *hchan, unsigned char rssi, unsigned char power_mode) ++static void drv_set_tx_power_accord_rssi(struct drv_private *drv_priv, ++ struct hal_channel *hchan, unsigned char rssi, ++ unsigned char power_mode) +{ -+ drv_hal_add_workitem((WorkHandler)drv_set_tx_power_accord_rssi_ex, NULL, (SYS_TYPE)hchan->chan_bw, (SYS_TYPE)hchan->channel, (SYS_TYPE)rssi, (SYS_TYPE)power_mode, 0); ++ drv_hal_add_workitem((WorkHandler)drv_set_tx_power_accord_rssi_ex, NULL, ++ (SYS_TYPE)hchan->chan_bw, (SYS_TYPE)hchan->channel, ++ (SYS_TYPE)rssi, (SYS_TYPE)power_mode, 0); +} + -+static void drv_cfg_txpwr_cffc_param_ex(SYS_TYPE param1,SYS_TYPE param2,SYS_TYPE param3, SYS_TYPE param4,SYS_TYPE param5) ++static void drv_cfg_txpwr_cffc_param_ex(SYS_TYPE param1, SYS_TYPE param2, ++ SYS_TYPE param3, SYS_TYPE param4, ++ SYS_TYPE param5) +{ -+ struct hal_private* hal_priv = hal_get_priv(); ++ struct hal_private *hal_priv = hal_get_priv(); + + hal_priv->hal_ops.hal_cfg_txpwr_cffc_param((void*)param1, (void*)param2); +} + -+static void drv_cfg_txpwr_cffc_param(struct wifi_channel * chan, struct tx_power_plan * txpwr_plan) ++static void drv_cfg_txpwr_cffc_param(struct wifi_channel *chan, ++ struct tx_power_plan *txpwr_plan) +{ -+ drv_hal_add_workitem((WorkHandler)drv_cfg_txpwr_cffc_param_ex, NULL, (SYS_TYPE)chan, (SYS_TYPE)txpwr_plan, 0, 0, 0); ++ drv_hal_add_workitem((WorkHandler)drv_cfg_txpwr_cffc_param_ex, NULL, ++ (SYS_TYPE)chan, (SYS_TYPE)txpwr_plan, 0, 0, 0); +} + -+ -+static void -+drv_set_channel( struct drv_private *drv_priv, struct hal_channel *hchan, unsigned char flag, unsigned char vid, unsigned char opmode) ++static void drv_set_channel(struct drv_private *drv_priv, struct hal_channel *hchan, ++ unsigned char flag, unsigned char vid, unsigned char opmode) +{ +#ifdef RF_T9026 + struct hal_private* hal_priv = hal_get_priv(); @@ -53081,7 +53416,7 @@ index 000000000000..abeda5f1221a + drv_priv->drv_curchannel = *hchan; + + DPRINTF(AML_DEBUG_SCAN, "%s (%d): channel_freq %d pchan_num %d cchan_num %d chan_bw %d\n", -+ __func__, __LINE__, hchan->channel, hchan->pchan_num, hchan->cchan_num, hchan->chan_bw); ++ __func__, __LINE__, hchan->channel, hchan->pchan_num, hchan->cchan_num, hchan->chan_bw); + } + driv_ps_sleep(drv_priv); +#ifdef RF_T9026 @@ -53089,7 +53424,8 @@ index 000000000000..abeda5f1221a +#endif +} + -+static int drv_set_bssid(struct drv_private *drv_priv, unsigned char wnet_vif_id,unsigned char *bssid) ++static int drv_set_bssid(struct drv_private *drv_priv, unsigned char wnet_vif_id, ++ unsigned char *bssid) +{ + int err; + struct hal_private* hal_priv = hal_get_priv(); @@ -53102,7 +53438,8 @@ index 000000000000..abeda5f1221a + return err; +} + -+static void drv_set_mac_addr( struct drv_private *drv_priv, unsigned char wnet_vif_id, unsigned char *macaddr) ++static void drv_set_mac_addr(struct drv_private *drv_priv, unsigned char wnet_vif_id, ++ unsigned char *macaddr) +{ + driv_ps_wakeup(drv_priv); + drv_hal_setmac(wnet_vif_id, macaddr); @@ -53113,7 +53450,7 @@ index 000000000000..abeda5f1221a +drv_bcn_init( struct drv_private *drv_priv, const unsigned char wnet_vif_id, + unsigned int _bperiod) +{ -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + driv_ps_wakeup(drv_priv); + drv_hal_beaconinit( wnet_vif_id, _bperiod); + driv_ps_sleep(drv_priv); @@ -53122,37 +53459,40 @@ index 000000000000..abeda5f1221a +drv_set_bcn_start( struct drv_private *drv_priv, unsigned char wnet_vif_id, + unsigned short intval, unsigned char dtim_count,unsigned short bsstype) +{ -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + driv_ps_wakeup(drv_priv); + drv_hal_set_bcn_start( wnet_vif_id, intval, dtim_count, bsstype); + driv_ps_sleep(drv_priv); +} + +static void -+drv_put_bcn_buf( struct drv_private *drv_priv, unsigned char wnet_vif_id, -+ unsigned char *pBeacon, unsigned short len,unsigned char Rate,unsigned short Flag) ++drv_put_bcn_buf(struct drv_private *drv_priv, unsigned char wnet_vif_id, ++ unsigned char *pBeacon, unsigned short len, ++ unsigned char Rate, unsigned short Flag) +{ -+ //printk(" %s %d \n",__func__,__LINE__); ++ /* pr_debug(" %s %d \n",__func__,__LINE__); */ + driv_ps_wakeup(drv_priv); -+ drv_hal_put_bcn_buf(wnet_vif_id,pBeacon, len, Rate, Flag); ++ drv_hal_put_bcn_buf(wnet_vif_id, pBeacon, len, Rate, Flag); + driv_ps_sleep(drv_priv); +} + +static int +drv_hal_set_p2p_opps_cwend_enable(struct drv_private *drv_priv, -+ unsigned char vid, unsigned char p2p_oppps_cw) ++ unsigned char vid, unsigned char p2p_oppps_cw) +{ -+ + DPRINTF(AML_DEBUG_HAL, "%s %d vid=%d p2p_oppps_cw=%xTU\n", -+ __func__,__LINE__,vid, p2p_oppps_cw); ++ __func__,__LINE__,vid, p2p_oppps_cw); + return drv_priv->hal_priv->hal_ops.phy_set_p2p_opps_cwend_enable(vid, p2p_oppps_cw); +} ++ +static int -+drv_hal_set_p2p_noa_enable(struct drv_private *drv_priv, -+ unsigned char vid,unsigned int duration, unsigned int interval, -+ unsigned int starttime, unsigned char count,unsigned char flag) ++drv_hal_set_p2p_noa_enable(struct drv_private *drv_priv, unsigned char vid, ++ unsigned int duration, unsigned int interval, ++ unsigned int starttime, unsigned char count, ++ unsigned char flag) +{ + unsigned char lflag = 0; ++ + DPRINTF(AML_DEBUG_HAL, "%s %d vid=%d count=%d\n", __func__,__LINE__, vid, count); + if (flag & P2P_NOA_START_MATCH_BEACON_HI) + { @@ -53163,7 +53503,8 @@ index 000000000000..abeda5f1221a + lflag |= P2P_NOA_END_MATCH_BEACON; + } + return drv_priv->hal_priv->hal_ops.phy_set_p2p_noa_enable(vid, duration, -+ interval, starttime, count, lflag); ++ interval, starttime, ++ count, lflag); +} +static unsigned long long +drv_hal_get_tsf(struct drv_private *drv_priv, unsigned char vid) @@ -53173,118 +53514,120 @@ index 000000000000..abeda5f1221a +} + +static int drv_send_null_data(struct drv_private *drv_priv, -+ struct NullDataCmd null_data , int len) ++ struct NullDataCmd null_data, int len) +{ + DPRINTF(AML_DEBUG_HAL, "%s %d vid=%d, ps=%d\n", __func__,__LINE__, -+ null_data.vid, null_data.pwr_save); ++ null_data.vid, null_data.pwr_save); + + return drv_priv->hal_priv->hal_ops.phy_send_null_data(null_data, len); +} + +static int drv_keep_alive(struct drv_private *drv_priv, -+ struct NullDataCmd null_data,int len, int enable, int period) ++ struct NullDataCmd null_data, int len, ++ int enable, int period) +{ + DPRINTF(AML_DEBUG_HAL, "%s %d enable=%d, vid=%d, period=%d\n", -+ __func__,__LINE__,enable, null_data.vid, period); ++ __func__, __LINE__, enable, null_data.vid, period); + + return drv_priv->hal_priv->hal_ops.phy_keep_alive(null_data, len, enable, period); +} + -+static int drv_set_beacon_miss(struct drv_private *drv_priv, -+ unsigned char wnet_vif_id,unsigned char enable, int period) ++static int drv_set_beacon_miss(struct drv_private *drv_priv, unsigned char wnet_vif_id, ++ unsigned char enable, int period) +{ + DPRINTF(AML_DEBUG_HAL, "%s %d vid=%d, enable=%d, period=%d\n", -+ __func__,__LINE__, wnet_vif_id, enable, period); ++ __func__,__LINE__, wnet_vif_id, enable, period); + return drv_priv->hal_priv->hal_ops.phy_set_beacon_miss(wnet_vif_id, enable, period); +} + -+static int drv_set_vsdb(struct drv_private *drv_priv, -+ unsigned char wnet_vif_id,unsigned char enable) ++static int drv_set_vsdb(struct drv_private *drv_priv, unsigned char wnet_vif_id, ++ unsigned char enable) +{ + DPRINTF(AML_DEBUG_HAL, "%s %d vid=%d, enable=%d\n", -+ __func__,__LINE__, wnet_vif_id, enable); ++ __func__,__LINE__, wnet_vif_id, enable); + return drv_priv->hal_priv->hal_ops.phy_set_vsdb(wnet_vif_id, enable); +} + +static int +drv_set_arp_agent(struct drv_private *drv_priv, unsigned char wnet_vif_id, -+ unsigned char enable, unsigned int ipv4, unsigned char *ipv6) ++ unsigned char enable, unsigned int ipv4, unsigned char *ipv6) +{ + DPRINTF(AML_DEBUG_HAL, "%s %d vid=%d, enable=%d, ipv4=0x%x\n", -+ __func__,__LINE__, wnet_vif_id, enable, ipv4); ++ __func__,__LINE__, wnet_vif_id, enable, ipv4); + return drv_priv->hal_priv->hal_ops.phy_set_arp_agent(wnet_vif_id, enable, ipv4, ipv6); +} + +static int +drv_set_pattern(struct drv_private *drv_priv, unsigned char vid, -+ unsigned char offset,unsigned char len, unsigned char id, -+ unsigned char *mask, unsigned char *pattern) ++ unsigned char offset,unsigned char len, unsigned char id, ++ unsigned char *mask, unsigned char *pattern) +{ + DPRINTF(AML_DEBUG_HAL, "%s %d vid=%d, pattern len=%d mask=0x%x\n", -+ __func__,__LINE__, vid, len, *(unsigned int*)mask); ++ __func__,__LINE__, vid, len, *(unsigned int*)mask); + return drv_priv->hal_priv->hal_ops.phy_set_pattern(vid, offset, len, id, mask, pattern); +} + -+static int drv_set_suspend(struct drv_private *drv_priv, -+ unsigned char vid, unsigned char enable, -+ unsigned char mode, unsigned int filters) ++static int drv_set_suspend(struct drv_private *drv_priv, unsigned char vid, ++ unsigned char enable, unsigned char mode, unsigned int filters) +{ + DPRINTF(AML_DEBUG_HAL, "%s %d vid=%d, enable=%d filters=0x%x\n", -+ __func__,__LINE__, vid, enable, filters); ++ __func__,__LINE__, vid, enable, filters); + + if (enable == 1) + drv_priv->dot11VmacPsState[vid] = DRV_PWRSAVE_FULL_SLEEP; + else + drv_priv->dot11VmacPsState[vid] = DRV_PWRSAVE_AWAKE; ++ + return drv_priv->hal_priv->hal_ops.phy_set_suspend(vid, enable, mode, filters); +} + -+int drv_hal_tx_frm_pause(struct drv_private *drv_priv, int pause) ++int drv_hal_tx_frm_pause(struct drv_private *drv_priv, int pause) +{ + DPRINTF(AML_DEBUG_HAL, "%s %d pause=%d\n", __func__,__LINE__, pause); + return drv_priv->hal_priv->hal_ops.hal_txframe_pause(pause); +} + +static void -+clear_staid_and_bssid_ex(SYS_TYPE param1, -+ SYS_TYPE param2, SYS_TYPE param3, -+ SYS_TYPE param4,SYS_TYPE param5) ++clear_staid_and_bssid_ex(SYS_TYPE param1, SYS_TYPE param2, SYS_TYPE param3, ++ SYS_TYPE param4,SYS_TYPE param5) +{ + struct drv_private *drv_priv = (void *)param1; + unsigned char wnet_vif_id = param2; + unsigned short sta_id = param3; -+ unsigned char bssid[6] = {0}; + struct wlan_net_vif *wnet_vif; + + wnet_vif = drv_priv->drv_wnet_vif_table[wnet_vif_id]; + if (wnet_vif == NULL) + { -+ return ; ++ return; + } + + driv_ps_wakeup(drv_priv); + hal_phy_unregister_sta_id(wnet_vif_id,sta_id); ++ + if (wnet_vif->vm_hal_opmode == WIFI_M_STA) { ++ unsigned char bssid[6] = { 0 }; ++ + drv_set_bssid(drv_priv, wnet_vif_id, bssid); + } ++ + driv_ps_sleep(drv_priv); -+ return ; ++ return; +} + +static int -+drv_clear_staid_and_bssid(struct drv_private *drv_priv, -+ unsigned char wnet_vif_id, unsigned short sta_id) ++drv_clear_staid_and_bssid(struct drv_private *drv_priv, unsigned char wnet_vif_id, ++ unsigned short sta_id) +{ -+ drv_hal_add_workitem((WorkHandler)clear_staid_and_bssid_ex,NULL, -+ (SYS_TYPE)drv_priv,(SYS_TYPE)wnet_vif_id, -+ (SYS_TYPE)sta_id,(SYS_TYPE)0, (SYS_TYPE)0); ++ drv_hal_add_workitem((WorkHandler)clear_staid_and_bssid_ex, NULL, ++ (SYS_TYPE)drv_priv,(SYS_TYPE)wnet_vif_id, ++ (SYS_TYPE)sta_id,(SYS_TYPE)0, (SYS_TYPE)0); + return 0; +} + +static void -+drv_wnet_vif_disconnect_ex(SYS_TYPE param1, -+ SYS_TYPE param2, SYS_TYPE param3, -+ SYS_TYPE param4,SYS_TYPE param5) ++drv_wnet_vif_disconnect_ex(SYS_TYPE param1, SYS_TYPE param2, SYS_TYPE param3, ++ SYS_TYPE param4, SYS_TYPE param5) +{ + struct drv_private *drv_priv = (void *)param1; + int wnet_vif_id = param2; @@ -53292,20 +53635,19 @@ index 000000000000..abeda5f1221a + driv_ps_wakeup(drv_priv); + drv_hal_wnet_vifdisconnect(wnet_vif_id); + driv_ps_sleep(drv_priv); -+ return ; ++ return; +} + +static int -+drv_wnet_vif_disconnect(struct drv_private *drv_priv, -+ int wnet_vif_id) ++drv_wnet_vif_disconnect(struct drv_private *drv_priv, int wnet_vif_id) +{ + drv_hal_add_workitem((WorkHandler)drv_wnet_vif_disconnect_ex, NULL, -+ (SYS_TYPE)drv_priv, (SYS_TYPE)wnet_vif_id, (SYS_TYPE)0, (SYS_TYPE)0, (SYS_TYPE)0); ++ (SYS_TYPE)drv_priv, (SYS_TYPE)wnet_vif_id, (SYS_TYPE)0, ++ (SYS_TYPE)0, (SYS_TYPE)0); + return 0; +} + -+static int -+drv_open( struct drv_private *drv_priv) ++static int drv_open(struct drv_private *drv_priv) +{ + struct wifi_mac *wifimac = NULL; + int error = 0; @@ -53331,80 +53673,87 @@ index 000000000000..abeda5f1221a +} + + -+static -+void drv_get_sts( struct drv_private *drv_priv, -+ unsigned int op_code, unsigned int ctrl_code) ++static void drv_get_sts(struct drv_private *drv_priv, unsigned int op_code, ++ unsigned int ctrl_code) +{ + int i; + struct wifi_mac *wifimac = wifi_mac_get_mac_handle(); -+ struct drv_txlist *txlist = NULL; -+ struct drv_tx_scoreboard *tid; -+ struct wifi_station *sta = NULL; -+ struct aml_driver_nsta *drv_sta = NULL; + struct wlan_net_vif *connect_wnet = wifi_mac_running_wnet_vif(wifimac); + -+ if(connect_wnet != NULL){ ++ if (connect_wnet != NULL) { ++ struct wifi_station *sta; ++ struct aml_driver_nsta *drv_sta; ++ + sta = connect_wnet->vm_mainsta; + drv_sta = sta->drv_sta; -+ printk("\n--------drv statistic--------\n"); -+ for(i=0; i< WME_NUM_AC;i++) ++ pr_debug("\n--------drv statistic--------\n"); ++ ++ for (i = 0; i < WME_NUM_AC; i++) + { -+ txlist = drv_txlist_initial(drv_priv,i); -+ printk("queen %d ac_queue_buffer_in_drv %d\n", i, txlist->txds_pending_cnt); ++ struct drv_txlist *txlist; ++ ++ txlist = drv_txlist_initial(drv_priv, i); ++ pr_debug("queen %d ac_queue_buffer_in_drv %d\n", i, txlist->txds_pending_cnt); + + } -+ for(i=0; i< WME_NUM_TID;i++) ++ ++ for (i = 0; i < WME_NUM_TID; i++) + { ++ struct drv_tx_scoreboard *tid; ++ + tid = &drv_sta->tx_agg_st.tid[i]; -+ printk("tid %d tid_queue_buffer_in_drv %d, msdu_count %d\n", i,WIFINET_SAVEQ_QLEN(&tid->tid_tx_buffer_queue), wifimac->msdu_cnt[i]); ++ pr_debug("tid %d tid_queue_buffer_in_drv %d, msdu_count %d\n", i, ++ WIFINET_SAVEQ_QLEN(&tid->tid_tx_buffer_queue), wifimac->msdu_cnt[i]); + + } -+ printk("tx_buffer_queue_in_drv %d\n",WIFINET_SAVEQ_QLEN(&connect_wnet->vm_tx_buffer_queue)); ++ pr_debug("tx_buffer_queue_in_drv %d\n", ++ WIFINET_SAVEQ_QLEN(&connect_wnet->vm_tx_buffer_queue)); + } + -+ if((ctrl_code & STS_MOD_DRV) == STS_MOD_DRV) ++ if ((ctrl_code & STS_MOD_DRV) == STS_MOD_DRV) + { + if ((ctrl_code & STS_TYP_TX) == STS_TYP_TX) + { + for(i = 0; i < HAL_NUM_TX_QUEUES; i++) + { -+ printk("txlist_idx %d, mpdu_to_hal %d,mpdu_pend %d, " -+ "mpdu_bkup %d,last_time %ld\n", -+ drv_priv->drv_txlist_table[i].txlist_qnum, -+ drv_priv->drv_txlist_table[i].txlist_qcnt, -+ drv_priv->drv_txlist_table[i].txds_pending_cnt, -+ drv_priv->drv_txlist_table[i].txlist_backup_qcnt, -+ drv_priv->drv_txlist_table[i].txlist_lasttime); ++ pr_debug("txlist_idx %d, mpdu_to_hal %d,mpdu_pend %d, " ++ "mpdu_bkup %d,last_time %ld\n", ++ drv_priv->drv_txlist_table[i].txlist_qnum, ++ drv_priv->drv_txlist_table[i].txlist_qcnt, ++ drv_priv->drv_txlist_table[i].txds_pending_cnt, ++ drv_priv->drv_txlist_table[i].txlist_backup_qcnt, ++ drv_priv->drv_txlist_table[i].txlist_lasttime); + } + -+ printk("--**--tx_retry_cnt %d\n", drv_priv->drv_stats.tx_retry_cnt); -+ printk("--**--tx_short_retry_cnt %d\n", drv_priv->drv_stats.tx_short_retry_cnt); -+ printk("tx_ampdu_mutil %d\n", drv_priv->drv_stats.tx_pkts_cnt); -+ printk("tx_ampdu_uniq %d\n", drv_priv->drv_stats.tx_ampdu_one_frame_cnt); -+ //printk("tx_ampdu pend %d\n", drv_priv->drv_stats.txds_pending_cnt); -+ printk("tx_normal mpdu %d\n", drv_priv->drv_stats.tx_normal_cnt); ++ pr_debug("--**--tx_retry_cnt %d\n", drv_priv->drv_stats.tx_retry_cnt); ++ pr_debug("--**--tx_short_retry_cnt %d\n", drv_priv->drv_stats.tx_short_retry_cnt); ++ pr_debug("tx_ampdu_mutil %d\n", drv_priv->drv_stats.tx_pkts_cnt); ++ pr_debug("tx_ampdu_uniq %d\n", drv_priv->drv_stats.tx_ampdu_one_frame_cnt); ++ //pr_debug("tx_ampdu pend %d\n", drv_priv->drv_stats.txds_pending_cnt); ++ pr_debug("tx_normal mpdu %d\n", drv_priv->drv_stats.tx_normal_cnt); + -+ printk("tx_ampdu_fail %d\n", drv_priv->drv_stats.tx_end_fail_cnt); -+ //printk("tx_drops %d\n", drv_priv->drv_stats.tx_drops_cnt); ++ pr_debug("tx_ampdu_fail %d\n", drv_priv->drv_stats.tx_end_fail_cnt); ++ //pr_debug("tx_drops %d\n", drv_priv->drv_stats.tx_drops_cnt); + -+ printk("tx_end_normal %d\n", drv_priv->drv_stats.tx_end_normal_cnt); -+ // printk("tx_end_ampdu %d\n", drv_priv->drv_stats.tx_end_ampdu_cnt); -+ // printk("tx_ampdu %d\n", drv_priv->drv_stats.tx_ampdu_cnt); ++ pr_debug("tx_end_normal %d\n", drv_priv->drv_stats.tx_end_normal_cnt); ++ // pr_debug("tx_end_ampdu %d\n", drv_priv->drv_stats.tx_end_ampdu_cnt); ++ // pr_debug("tx_ampdu %d\n", drv_priv->drv_stats.tx_ampdu_cnt); + } -+ /*drv rx */ ++ ++ /* drv rx */ + + if ((ctrl_code & STS_TYP_RX) == STS_TYP_RX) + { -+ printk("rx_indicate %d\n", drv_priv->drv_stats.rx_indicate_cnt); -+ printk("rx_free_skb %d\n", drv_priv->drv_stats.rx_free_skb_cnt); -+ printk("rx_ampdu %d\n", drv_priv->drv_stats.rx_ampdu_cnt); -+ printk("rx_bar %d\n", drv_priv->drv_stats.rx_bar_cnt); -+ printk("rx_nonqos %d\n", drv_priv->drv_stats.rx_nonqos_cnt); -+ printk("rx_dup %d\n", drv_priv->drv_stats.rx_dup_cnt); -+ printk("rx_ok %d\n", drv_priv->drv_stats.rx_ok_cnt); -+ printk("rx_bardrop %d\n", drv_priv->drv_stats.rx_bardrop_cnt); -+ printk("rx_skipped %d\n", drv_priv->drv_stats.rx_skipped_cnt); -+ printk("--**--rx_ack_rssi %d\n", drv_priv->drv_stats.rx_ack_rssi); ++ pr_debug("rx_indicate %d\n", drv_priv->drv_stats.rx_indicate_cnt); ++ pr_debug("rx_free_skb %d\n", drv_priv->drv_stats.rx_free_skb_cnt); ++ pr_debug("rx_ampdu %d\n", drv_priv->drv_stats.rx_ampdu_cnt); ++ pr_debug("rx_bar %d\n", drv_priv->drv_stats.rx_bar_cnt); ++ pr_debug("rx_nonqos %d\n", drv_priv->drv_stats.rx_nonqos_cnt); ++ pr_debug("rx_dup %d\n", drv_priv->drv_stats.rx_dup_cnt); ++ pr_debug("rx_ok %d\n", drv_priv->drv_stats.rx_ok_cnt); ++ pr_debug("rx_bardrop %d\n", drv_priv->drv_stats.rx_bardrop_cnt); ++ pr_debug("rx_skipped %d\n", drv_priv->drv_stats.rx_skipped_cnt); ++ pr_debug("--**--rx_ack_rssi %d\n", drv_priv->drv_stats.rx_ack_rssi); + } + + } @@ -53412,9 +53761,7 @@ index 000000000000..abeda5f1221a + drv_priv->hal_priv->hal_ops.hal_get_sts(op_code, ctrl_code); +} + -+ -+static int -+drv_stop( struct drv_private *drv_priv) ++static int drv_stop(struct drv_private *drv_priv) +{ + driv_ps_wakeup(drv_priv); + drv_priv->drv_config.cfg_rtcenable = 0; @@ -53422,9 +53769,9 @@ index 000000000000..abeda5f1221a + return 0; +} + -+int drv_reset( void * dev) ++int drv_reset(void * dev) +{ -+ struct drv_private *drv_priv = ( struct drv_private *) dev; ++ struct drv_private *drv_priv = (struct drv_private *)dev; + int error = 0; + + driv_ps_wakeup(drv_priv); @@ -53439,9 +53786,9 @@ index 000000000000..abeda5f1221a + return error; +} + -+static int drv_suspend( void * dev) ++static int drv_suspend(void *dev) +{ -+ struct drv_private *drv_priv = ( struct drv_private *) dev; ++ struct drv_private *drv_priv = (struct drv_private *)dev; + driv_ps_wakeup(drv_priv); + + drv_hal_disable(); @@ -53462,71 +53809,75 @@ index 000000000000..abeda5f1221a +} + +static void -+drv_set_chan_bw_mode_orig( SYS_TYPE param1, -+ SYS_TYPE param2,SYS_TYPE param3, -+ SYS_TYPE param4,SYS_TYPE param5) ++drv_set_chan_bw_mode_orig(SYS_TYPE param1, SYS_TYPE param2, ++ SYS_TYPE param3, SYS_TYPE param4, ++ SYS_TYPE param5) +{ -+ struct drv_private *drv_priv =(struct drv_private *)param1; -+ int chanbw = (int) param2; ++ struct drv_private *drv_priv = (struct drv_private *)param1; ++ int chanbw = (int)param2; ++ + driv_ps_wakeup(drv_priv); + drv_hal_set11nmac2040( chanbw); + driv_ps_sleep(drv_priv); +} + +static void -+drv_set_chan_bw_mode( struct drv_private *drv_priv, -+ enum wifi_mac_chanbw bw) ++drv_set_chan_bw_mode(struct drv_private *drv_priv, enum wifi_mac_chanbw bw) +{ -+ drv_hal_add_workitem((WorkHandler)drv_set_chan_bw_mode_orig, -+ NULL,(SYS_TYPE) drv_priv,(SYS_TYPE) bw,0,0,0); ++ drv_hal_add_workitem((WorkHandler)drv_set_chan_bw_mode_orig, NULL, ++ (SYS_TYPE)drv_priv, (SYS_TYPE)bw, 0, 0, 0); +} + +static int -+drv_get_scn_chan_busy( struct drv_private *drv_priv) ++drv_get_scn_chan_busy(struct drv_private *drv_priv) +{ + int ret; ++ + driv_ps_wakeup(drv_priv); + ret = drv_hal_get11nextbusy(); + driv_ps_sleep(drv_priv); ++ + return ret; +} + +static unsigned int -+drv_low_reg_behind_task( struct drv_private *drv_priv,void *func) ++drv_low_reg_behind_task(struct drv_private *drv_priv, void *func) +{ + return drv_low_register_behind_task(func); +} + +static unsigned int -+drv_low_call_task( struct drv_private *drv_priv, -+ SYS_TYPE taskid,SYS_TYPE param1) ++drv_low_call_task(struct drv_private *drv_priv, SYS_TYPE taskid, ++ SYS_TYPE param1) +{ -+ return drv_low_call_register_task(taskid,param1); ++ return drv_low_call_register_task(taskid, param1); +} + -+unsigned int drv_low_add_worktask( struct drv_private *drv_priv, -+ void *func,void *func_cb,SYS_TYPE param1,SYS_TYPE param2, -+ SYS_TYPE param3,SYS_TYPE param4,SYS_TYPE param5) ++unsigned int drv_low_add_worktask(struct drv_private *drv_priv, void *func, ++ void *func_cb, SYS_TYPE param1, SYS_TYPE param2, ++ SYS_TYPE param3, SYS_TYPE param4, SYS_TYPE param5) +{ -+ return drv_hal_add_workitem(func,func_cb,param1, param2,param3, param4,param5); ++ return drv_hal_add_workitem(func, func_cb, param1, param2, param3, param4, param5); +} + +static unsigned int -+drv_phy_reg_sta_id( struct drv_private *drv_priv, -+ unsigned char wnet_vif_id,unsigned short StaAid, -+ unsigned char *pMac, unsigned char encrypt) ++drv_phy_reg_sta_id(struct drv_private *drv_priv, unsigned char wnet_vif_id, ++ unsigned short StaAid, unsigned char *pMac, unsigned char encrypt) +{ + unsigned int ret; ++ + driv_ps_wakeup(drv_priv); -+ ret = hal_phy_register_sta_id(wnet_vif_id,StaAid,pMac, encrypt); ++ ret = hal_phy_register_sta_id(wnet_vif_id, StaAid, pMac, encrypt); + driv_ps_sleep(drv_priv); + + return ret; +} + -+static unsigned int drv_phy_unreg_all_sta_id(struct drv_private *drv_priv, unsigned char wnet_vif_id) ++static unsigned int drv_phy_unreg_all_sta_id(struct drv_private *drv_priv, ++ unsigned char wnet_vif_id) +{ + unsigned int ret; ++ + driv_ps_wakeup(drv_priv); + ret = hal_phy_unregister_all_sta_id(wnet_vif_id); + driv_ps_sleep(drv_priv); @@ -53534,24 +53885,25 @@ index 000000000000..abeda5f1221a + return ret; +} + -+int drv_add_wnet_vif(struct drv_private *drv_priv, -+ int wnet_vif_id, void * if_data, enum hal_op_mode vm_opmode, unsigned char *myaddr, unsigned int ip) ++int drv_add_wnet_vif(struct drv_private *drv_priv, int wnet_vif_id, ++ void *if_data, enum hal_op_mode vm_opmode, ++ unsigned char *myaddr, unsigned int ip) +{ + struct wlan_net_vif *wnet_vif; -+ int ret = 0; + + if (wnet_vif_id >= DEFAULT_MAX_VMAC) { + return -EINVAL; + } + -+ if ((drv_priv->drv_wnet_vif_table[wnet_vif_id] != NULL) -+ && (drv_priv->drv_wnet_vif_table[wnet_vif_id]->vm_wmac->recovery_stat == WIFINET_RECOVERY_END)) { -+ ERROR_DEBUG_OUT("Invalid interface id = %u, recovery %d \n", wnet_vif_id, drv_priv->drv_wnet_vif_table[wnet_vif_id]->vm_wmac->recovery_stat); ++ if ((drv_priv->drv_wnet_vif_table[wnet_vif_id] != NULL) && ++ (drv_priv->drv_wnet_vif_table[wnet_vif_id]->vm_wmac->recovery_stat == WIFINET_RECOVERY_END)) { ++ ERROR_DEBUG_OUT("Invalid interface id = %u, recovery %d \n", wnet_vif_id, ++ drv_priv->drv_wnet_vif_table[wnet_vif_id]->vm_wmac->recovery_stat); + return -EINVAL; + } + + driv_ps_wakeup(drv_priv); -+ printk("%s(%d) macaddr "MAC_FMT"\n",__func__, __LINE__, MAC_ARG(myaddr)); ++ pr_debug("%s(%d) macaddr "MAC_FMT"\n", __func__, __LINE__, MAC_ARG(myaddr)); + + if (vm_opmode == WIFI_M_HOSTAP) { + /* copy nostabeacons - for WDS client */ @@ -53575,15 +53927,16 @@ index 000000000000..abeda5f1221a + drv_hal_setopmode( wnet_vif_id, vm_opmode); + drv_hal_setdhcp(wnet_vif_id, ip); + driv_ps_sleep(drv_priv); -+ return ret; ++ ++ return 0; +} ++ +/* -+TxBufLock -+*/ -+static int drv_delete_wnet_vif(struct drv_private * drv_priv, int wnet_vif_id) ++ * TxBufLock ++ */ ++static int drv_delete_wnet_vif(struct drv_private *drv_priv, int wnet_vif_id) +{ + int flags; -+ int ret = 0; + + driv_ps_wakeup(drv_priv); + @@ -53603,21 +53956,23 @@ index 000000000000..abeda5f1221a + + drv_hal_wnet_vifStop(wnet_vif_id); + driv_ps_sleep(drv_priv); -+ return ret ; ++ ++ return 0; +} ++ +static int -+drv_change_wnet_vif(struct drv_private * drv_priv, int wnet_vif_id, -+ void * if_data, enum hal_op_mode vm_opmode, unsigned char *myaddr, unsigned int ip) ++drv_change_wnet_vif(struct drv_private *drv_priv, int wnet_vif_id, void *if_data, ++ enum hal_op_mode vm_opmode, unsigned char *myaddr, unsigned int ip) +{ + struct wlan_net_vif *wnet_vif; -+ int ret = 0; + -+ if (wnet_vif_id >= DEFAULT_MAX_VMAC -+ || drv_priv->drv_wnet_vif_table[wnet_vif_id] == NULL) ++ if (wnet_vif_id >= DEFAULT_MAX_VMAC || ++ drv_priv->drv_wnet_vif_table[wnet_vif_id] == NULL) + { + ERROR_DEBUG_OUT("Invalid interface id = %u\n", wnet_vif_id); + return -EINVAL; + } ++ + driv_ps_wakeup(drv_priv); + wnet_vif = drv_priv->drv_wnet_vif_table[wnet_vif_id]; + @@ -53630,16 +53985,17 @@ index 000000000000..abeda5f1221a + drv_hal_setopmode(wnet_vif_id, vm_opmode); + drv_hal_setdhcp(wnet_vif_id, ip); + driv_ps_sleep(drv_priv); -+ return ret ; -+} + ++ return 0; ++} + +static void * -+drv_nsta_attach( struct drv_private *drv_priv, int wnet_vif_id, void* sta) ++drv_nsta_attach( struct drv_private *drv_priv, int wnet_vif_id, void *sta) +{ + struct aml_driver_nsta *drv_sta; + -+ drv_sta = (struct aml_driver_nsta *)NET_MALLOC(sizeof(struct aml_driver_nsta), GFP_ATOMIC, "drv_nsta_attach.drv_sta"); ++ drv_sta = (struct aml_driver_nsta *)NET_MALLOC(sizeof(struct aml_driver_nsta), ++ GFP_ATOMIC, "drv_nsta_attach.drv_sta"); + if (drv_sta == NULL) + { + ERROR_DEBUG_OUT(" drv_sta is NULL \n"); @@ -53648,6 +54004,7 @@ index 000000000000..abeda5f1221a + + drv_sta->net_nsta = sta; + drv_sta->sta_drv_priv = drv_priv; ++ ERROR_DEBUG_OUT(" drv_priv->drv_ratectrl_size == %d\n",drv_priv->drv_ratectrl_size); + drv_sta->sta_rc_nsta = ZMALLOC(drv_priv->drv_ratectrl_size,"drv_sta->sta_rc_nsta", GFP_ATOMIC); + + if (drv_sta->sta_rc_nsta == NULL) @@ -53658,7 +54015,8 @@ index 000000000000..abeda5f1221a + } + + DPRINTF( AML_DEBUG_INFO, " %s %d drv_ratectrl_size = %d sta_rc_nsta = %p\n", -+ __func__,__LINE__,drv_priv->drv_ratectrl_size, drv_sta->sta_rc_nsta); ++ __func__, __LINE__, drv_priv->drv_ratectrl_size, ++ drv_sta->sta_rc_nsta); + + /* set up per-nsta tx/rx state */ + drv_txlist_init_for_sta(drv_priv, drv_sta, wnet_vif_id); @@ -53669,30 +54027,31 @@ index 000000000000..abeda5f1221a + drv_tx_withdraw_init(drv_priv, drv_sta); +#endif + -+ DPRINTF( AML_DEBUG_INFO, " %s %d \n",__func__,__LINE__); ++ DPRINTF(AML_DEBUG_INFO, " %s %d \n",__func__,__LINE__); + + return drv_sta; +} + +static void -+drv_nsta_detach(struct drv_private * drv_priv, void * nsta) ++drv_nsta_detach(struct drv_private *drv_priv, void *nsta) +{ + struct aml_driver_nsta *drv_sta = DRIVER_NODE(nsta); + + drv_txlist_free_for_sta(drv_priv, drv_sta); + drv_rx_nsta_free(drv_priv, drv_sta); + -+ printk("%s drv_sta:%p\n", __func__, drv_sta); ++ pr_debug("%s drv_sta:%p\n", __func__, drv_sta); + FREE(drv_sta->sta_rc_nsta, "drv_sta->sta_rc_nsta"); + FREE(drv_sta, "drv_nsta_attach.drv_sta"); +} + +static void -+drv_nsta_cleanup( struct drv_private *drv_priv, void * nsta) ++drv_nsta_cleanup( struct drv_private *drv_priv, void *nsta) +{ + struct aml_driver_nsta *drv_sta = DRIVER_NODE(nsta); + + drv_sta->sta_cleanup = 1; ++ + if (drv_sta->sta_isuapsd) + { + drv_sta->sta_isuapsd = 0; @@ -53709,55 +54068,56 @@ index 000000000000..abeda5f1221a + +static void +drv_nsta_update_pwrsave(struct drv_private *drv_priv, -+ void * nsta, int pwrsave) ++ void *nsta, int pwrsave) +{ + struct aml_driver_nsta *drv_sta = DRIVER_NODE(nsta); ++ + if (pwrsave) + { + drv_sta->sta_powesave = 1; -+ drv_txlist_pause_for_sta(drv_priv,drv_sta); ++ drv_txlist_pause_for_sta(drv_priv, drv_sta); + } + else + { + drv_sta->sta_powesave = 0; -+ drv_txlist_resume_for_sta(drv_priv,drv_sta); ++ drv_txlist_resume_for_sta(drv_priv, drv_sta); + } +} + +static void -+drv_key_rst_ex(SYS_TYPE param1,SYS_TYPE param2, -+ SYS_TYPE param3,SYS_TYPE param4,SYS_TYPE param5) ++drv_key_rst_ex(SYS_TYPE param1, SYS_TYPE param2, SYS_TYPE param3, ++ SYS_TYPE param4, SYS_TYPE param5) +{ + struct drv_private *drv_priv = (struct drv_private *)param1; + unsigned char wnet_vif_id = (unsigned char)param2; -+ unsigned short key_index = (unsigned short )param3; ++ unsigned short key_index = (unsigned short)param3; + int staid = (int)param4; + driv_ps_wakeup(drv_priv); + -+ printk(" %s %d wnet_vif_id=%d\n",__func__,__LINE__,wnet_vif_id); ++ pr_debug(" %s %d wnet_vif_id=%d\n",__func__,__LINE__,wnet_vif_id); + if (staid == 0) { + drv_hal_keyreset(wnet_vif_id, key_index); -+ + } else { + drv_hal_keyclear(wnet_vif_id, staid); + } ++ + driv_ps_sleep(drv_priv); +} + +static void -+drv_key_rst( struct drv_private * drv_priv,unsigned char wnet_vif_id, -+ unsigned short key_index, int staid) ++drv_key_rst(struct drv_private *drv_priv, unsigned char wnet_vif_id, ++ unsigned short key_index, int staid) +{ -+ drv_hal_add_workitem( (WorkHandler)drv_key_rst_ex,NULL, -+ (SYS_TYPE)drv_priv,(SYS_TYPE)wnet_vif_id, -+ (SYS_TYPE)key_index,(SYS_TYPE)staid, ++ drv_hal_add_workitem((WorkHandler)drv_key_rst_ex, NULL, ++ (SYS_TYPE)drv_priv, (SYS_TYPE)wnet_vif_id, ++ (SYS_TYPE)key_index, (SYS_TYPE)staid, + (SYS_TYPE)0); +} + +static int -+drv_key_set(struct drv_private * drv_priv, unsigned char wnet_vif_id, -+ unsigned short key_index, struct hal_key_val *hk, -+ const unsigned char mac[WIFINET_ADDR_LEN]) ++drv_key_set(struct drv_private *drv_priv, unsigned char wnet_vif_id, ++ unsigned short key_index, struct hal_key_val *hk, ++ const unsigned char mac[WIFINET_ADDR_LEN]) +{ + int status; + struct wlan_net_vif *wnet_vif = drv_priv->drv_wnet_vif_table[wnet_vif_id]; @@ -53770,23 +54130,26 @@ index 000000000000..abeda5f1221a + } + else + { -+ if (hk->kv_pad == WIFINET_M_HOSTAP) //ap mode , send staid ++ if (hk->kv_pad == WIFINET_M_HOSTAP) /* ap mode, send staid */ + { + sta = drv_priv->net_ops->wifi_mac_get_sta(&wnet_vif->vm_sta_tbl, mac,wnet_vif_id); -+ status = drv_hal_keyset(wnet_vif_id, key_index, hk, (unsigned char *)mac,sta->sta_associd); ++ status = drv_hal_keyset(wnet_vif_id, key_index, hk, ++ (unsigned char *)mac,sta->sta_associd); + } + else + { -+ status = drv_hal_keyset(wnet_vif_id,key_index, hk, (unsigned char *)mac,1); ++ status = drv_hal_keyset(wnet_vif_id,key_index, hk, ++ (unsigned char *)mac,1); + } + } ++ + driv_ps_sleep(drv_priv); + return (status != 0); +} + +static int -+drv_rekey_data_set(struct drv_private *drv_priv, -+ unsigned char wnet_vif_id, void *rekey_data) ++drv_rekey_data_set(struct drv_private *drv_priv, unsigned char wnet_vif_id, ++ void *rekey_data) +{ + int status; + @@ -53801,26 +54164,27 @@ index 000000000000..abeda5f1221a + * Set the 802.11D country + */ +static int -+drv_set_country(struct drv_private * drv_priv, char *isoName) ++drv_set_country(struct drv_private *drv_priv, char *isoName) +{ + unsigned int wMode; + int tmpi; + + tmpi = find_country_code((unsigned char *)isoName); + if (tmpi == 0xff) { -+// printk("%s can't find country code \n", __func__); ++ /* pr_debug("%s can't find country code \n", __func__); */ + tmpi = 0; + } + + drv_priv->drv_config.cfg_countrycode = tmpi; + drv_priv->drv_config.cfg_txpoweplan = wifimac_get_tx_pwr_plan(tmpi); + -+ printk(" %s %d %d\n",__func__,__LINE__, drv_priv->drv_config.cfg_countrycode ); ++ pr_debug(" %s %d %d\n",__func__,__LINE__, drv_priv->drv_config.cfg_countrycode ); + wMode = drv_priv->drv_config.cfg_modesupport; + + if (drv_priv->net_ops->wifi_mac_setup_channel_list) + { -+ drv_priv->net_ops->wifi_mac_setup_channel_list(drv_priv->wmac, wMode,drv_priv->drv_config.cfg_countrycode); ++ drv_priv->net_ops->wifi_mac_setup_channel_list(drv_priv->wmac, wMode, ++ drv_priv->drv_config.cfg_countrycode); + } + + return 0; @@ -53831,7 +54195,7 @@ index 000000000000..abeda5f1221a + */ +extern struct country_chan_mapping country_chan_mapping_list[]; +static void -+drv_get_curr_cntry( struct drv_private * drv_priv, unsigned char *iso_name) ++drv_get_curr_cntry(struct drv_private *drv_priv, unsigned char *iso_name) +{ + if (drv_priv->drv_config.cfg_countrycode != 0xff) + { @@ -53848,19 +54212,17 @@ index 000000000000..abeda5f1221a +} + +static int -+drv_set_quiet( struct drv_private *drv_priv, -+ unsigned short period, unsigned short duration, -+ unsigned short nextStart, unsigned short enabled) ++drv_set_quiet(struct drv_private *drv_priv, unsigned short period, ++ unsigned short duration, unsigned short nextStart, ++ unsigned short enabled) +{ -+// -+///we not support this -+// ++ /* we not support this */ + return 0; +} + +void -+drv_set_tx_pwr_limit(struct drv_private * drv_priv, -+ unsigned int limit, unsigned short txpowerdb) ++drv_set_tx_pwr_limit(struct drv_private *drv_priv, unsigned int limit, ++ unsigned short txpowerdb) +{ + drv_priv->drv_config.cfg_txpowlimit = (unsigned short)limit; + @@ -53868,156 +54230,158 @@ index 000000000000..abeda5f1221a +} + +static short -+drv_get_noise_floor(struct drv_private * drv_priv, -+ unsigned short freq, unsigned int chan_flags) ++drv_get_noise_floor(struct drv_private *drv_priv, ++ unsigned short freq, unsigned int chan_flags) +{ + return -85; +} + -+static void drv_write_word (unsigned int addr,unsigned int data) ++static void drv_write_word(unsigned int addr, unsigned int data) +{ -+ struct hal_private* hal_priv = hal_get_priv(); ++ struct hal_private* hal_priv = hal_get_priv(); + -+ hal_priv->hal_ops.hal_write_word(addr, data); ++ hal_priv->hal_ops.hal_write_word(addr, data); +} + +static unsigned int drv_read_word(unsigned int addr) +{ + struct hal_private* hal_priv = hal_get_priv(); ++ + return hal_priv->hal_ops.hal_read_word(addr); +} + -+ -+static void drv_bt_write_word (unsigned int addr,unsigned int data) ++static void drv_bt_write_word(unsigned int addr, unsigned int data) +{ -+ struct hal_private* hal_priv = hal_get_priv(); ++ struct hal_private* hal_priv = hal_get_priv(); + -+ hal_priv->hal_ops.hal_bt_write_word(addr, data); ++ hal_priv->hal_ops.hal_bt_write_word(addr, data); +} + +static unsigned int drv_bt_read_word(unsigned int addr) +{ + struct hal_private* hal_priv = hal_get_priv(); ++ + return hal_priv->hal_ops.hal_bt_read_word(addr); +} + -+ -+static void drv_pt_rx_start (unsigned int qos) ++static void drv_pt_rx_start(unsigned int qos) +{ -+ struct hal_private* hal_priv = hal_get_priv(); ++ struct hal_private* hal_priv = hal_get_priv(); + -+ hal_priv->hal_ops.hal_pt_rx_start(qos); ++ hal_priv->hal_ops.hal_pt_rx_start(qos); +} + +static void drv_pt_rx_stop(void) +{ + struct hal_private* hal_priv = hal_get_priv(); ++ + hal_priv->hal_ops.hal_pt_rx_stop(); +} + +static void drv_set_bmfm_info(struct drv_private *drv_priv, int wnet_vif_id, -+ unsigned char *group_id, unsigned char * user_position, unsigned char feedback_type) ++ unsigned char *group_id, unsigned char *user_position, ++ unsigned char feedback_type) +{ + drv_hal_set_bmfm_info(wnet_vif_id, group_id, user_position, feedback_type); +} + +static void drv_interface_enable(unsigned char enable, unsigned char vid) +{ -+ struct hal_private* hal_priv = hal_get_priv(); ++ struct hal_private *hal_priv = hal_get_priv(); + + hal_priv->hal_ops.phy_interface_enable(enable, vid); +} + +static void drv_cfg_cali_param(void) +{ -+ struct hal_private* hal_priv = hal_get_priv(); ++ struct hal_private *hal_priv = hal_get_priv(); + + hal_priv->hal_ops.hal_cfg_cali_param(); +} + +static void drv_init_ops(struct drv_private *drv_priv) +{ -+ drv_priv->drv_ops.drv_open = drv_open; /* drv_open */ -+ drv_priv->drv_ops.drv_stop = drv_suspend; /* drv_stop */ -+ drv_priv->drv_ops.add_interface = drv_add_wnet_vif; /* add_interface */ -+ drv_priv->drv_ops.remove_interface = drv_delete_wnet_vif; /* remove_interface */ -+ drv_priv->drv_ops.change_interface = drv_change_wnet_vif; /* change_interface */ -+ drv_priv->drv_ops.down_interface = drv_wnet_vif_disconnect; /* down_interface */ -+ drv_priv->drv_ops.alloc_nsta = drv_nsta_attach; /* alloc_nsta */ -+ drv_priv->drv_ops.free_nsta = drv_nsta_detach; /* free_nsta */ -+ drv_priv->drv_ops.cleanup_nsta = drv_nsta_cleanup; /* cleanup_nsta */ -+ drv_priv->drv_ops.update_nsta_pwrsave = drv_nsta_update_pwrsave; /* update_nsta_pwrsave */ -+ drv_priv->drv_ops.new_assoc = drv_assoc_proc; /* new_assoc */ -+ drv_priv->drv_ops.reset = drv_reset; /* reset */ -+ drv_priv->drv_ops.set_channel = drv_set_channel; /* set_channel */ -+ drv_priv->drv_ops.scan_start = drv_scan_start; /* scan_start */ -+ drv_priv->drv_ops.fw_repair = drv_fw_recovery; /* fw_repair */ -+ drv_priv->drv_ops.scan_end = drv_scan_end; /* scan_end */ -+ drv_priv->drv_ops.connect_start = drv_connect_start; /*connect_start */ -+ drv_priv->drv_ops.connect_end = drv_connect_end; /* connect_end */ -+ drv_priv->drv_ops.set_channel_rssi = drv_set_channel_rssi; /* set_channel_rssi */ -+ drv_priv->drv_ops.set_tx_power_accord_rssi = drv_set_tx_power_accord_rssi; /* set_tx_power_accord_rssi */ -+ drv_priv->drv_ops.tx_init = drv_tx_init; /* tx_init */ -+ drv_priv->drv_ops.tx_cleanup = drv_txlist_cleanup; /* tx_cleanup */ -+ drv_priv->drv_ops.tx_wmm_queue_update = drv_update_wmmq_param; /* tx_wmm_queue_update */ -+ drv_priv->drv_ops.tx_start = drv_tx_start; /* tx_start */ -+ drv_priv->drv_ops.txlist_qcnt_handle = drv_txlist_qcnt; /* txlist_qcnt */ -+ drv_priv->drv_ops.txlist_all_qcnt = drv_txlist_all_qcnt; /* txlist_all_qcnt */ -+ drv_priv->drv_ops.txlist_isfull = drv_txlist_isfull; /* txlist_isfull*/ -+ drv_priv->drv_ops.rx_init = drv_rx_init; /* rx_init */ -+ drv_priv->drv_ops.rx_proc_frame = drv_rx_input; /* rx_proc_frame */ -+ drv_priv->drv_ops.check_aggr = drv_aggr_check; /* check_aggr */ -+ drv_priv->drv_ops.aggr_tid_query = drv_aggr_tid; /* aggr_tid_query */ -+ drv_priv->drv_ops.check_aggr_allow_to_send = drv_aggr_allow_to_send; /* drv_aggr_allow_to_send */ -+ drv_priv->drv_ops.set_ampdu_params = drv_set_ampduparams; /* set_ampdu_params */ -+ drv_priv->drv_ops.addba_request_setup = drv_addba_req_setup; /* addba_request_setup */ -+ drv_priv->drv_ops.addba_response_setup = drv_rx_addbarsp; /* addba_response_setup */ -+ drv_priv->drv_ops.addba_request_process = drv_rx_addbareq; /* addba_request_process */ -+ drv_priv->drv_ops.addba_response_process = drv_addba_rsp_process; /* addba_response_process */ -+ drv_priv->drv_ops.addba_clear = drv_addba_clear; /* addba_clear */ -+ drv_priv->drv_ops.delba_process = drv_rx_delba; /* delba_process */ -+ drv_priv->drv_ops.addba_status = drv_addba_status; /* addba_status */ -+ drv_priv->drv_ops.drv_txrxampdu_del = drv_txrxampdu_del; /* drv_txrxampdu_del */ -+ drv_priv->drv_ops.set_addbaresponse = drv_set_addba_rsp; /* set_addbaresponse */ -+ drv_priv->drv_ops.clear_addbaresponsestatus = drv_clr_addba_rsp_status; /* clear_addbaresponsestatus */ -+ drv_priv->drv_ops.set_slottime = drv_update_slot; /* set_slottime */ -+ drv_priv->drv_ops.set_protmode = drv_set_protmode; /* set_protmode */ -+ drv_priv->drv_ops.set_cfg_txpowlimit = drv_set_cfg_tx_power_limit; /* set_cfg_txpowlimit */ -+ drv_priv->drv_ops.key_delete = drv_key_rst; /* key_delete */ -+ drv_priv->drv_ops.key_set = drv_key_set; /* key_set */ -+ drv_priv->drv_ops.rekey_data_set = drv_rekey_data_set; /* rekey_data_set */ -+ drv_priv->drv_ops.awake = drv_pwrsave_awake; /* awake */ -+ drv_priv->drv_ops.netsleep = drv_pwrsave_netsleep; /* netsleep */ -+ drv_priv->drv_ops.fullsleep = drv_pwrsave_fullsleep; /* fullsleep */ -+ drv_priv->drv_ops.set_country = drv_set_country; /* set_country */ -+ drv_priv->drv_ops.get_current_country = drv_get_curr_cntry; /* get_current_country */ -+ drv_priv->drv_ops.set_quiet = drv_set_quiet; /* set_quiet */ -+ drv_priv->drv_ops.set_bwmode = drv_set_chan_bw_mode; /* set_bwmode */ -+ drv_priv->drv_ops.GetSecondChanBusy = drv_get_scn_chan_busy; /* GetSecondChanBusy */ -+ drv_priv->drv_ops.drv_get_config_param = drv_get_config; /* drv_get_config_param */ -+ drv_priv->drv_ops.drv_set_config_param = drv_set_config; /* drv_set_config_param */ -+ drv_priv->drv_ops.get_noisefloor = drv_get_noise_floor; /* get_noisefloor */ -+ drv_priv->drv_ops.drv_set_txPwrLimit = drv_set_tx_pwr_limit; /* drv_set_txPwrLimit */ -+ drv_priv->drv_ops.get_amsdu_supported = drv_get_amsdu_supported; /* get_amsdu_supported */ -+ drv_priv->drv_ops.process_uapsd_trigger = drv_process_uapsd_nsta_trigger; /* process_uapsd_trigger */ -+ drv_priv->drv_ops.uapsd_qcnt = drv_tx_uapsd_nsta_qcnt; /* uapsd_qcnt */ -+ drv_priv->drv_ops.set_macaddr = drv_set_mac_addr; /* set_macaddr */ -+ drv_priv->drv_ops.Low_register_behindTask = drv_low_reg_behind_task; /* Low_register_behindTask */ -+ drv_priv->drv_ops.Low_callRegisteredTask = drv_low_call_task; /* Low_callRegisteredTask */ -+ drv_priv->drv_ops.Low_addDHWorkTask = drv_low_add_worktask; /* Low_addDHWorkTask */ -+ drv_priv->drv_ops.RegisterStationID = drv_phy_reg_sta_id; /*RegisterStationID */ -+ drv_priv->drv_ops.clear_staid_and_bssid = drv_clear_staid_and_bssid; /* clear_staid_and_bssid */ -+ drv_priv->drv_ops.UnRegisterAllStationID = drv_phy_unreg_all_sta_id; /* UnRegisterAllStationID */ -+ drv_priv->drv_ops.phy_setchannelsupport = NULL; /* drv_set_channelsupport */ -+ drv_priv->drv_ops.Phy_beaconinit = drv_bcn_init; /*Phy_beaconinit*/ -+ drv_priv->drv_ops.Phy_SetBeaconStart = drv_set_bcn_start; /*Phy_SetBeaconStart*/ -+ drv_priv->drv_ops.Phy_PutBeaconBuf = drv_put_bcn_buf; /*Phy_PutBeaconBuf*/ ++ drv_priv->drv_ops.drv_open = drv_open; /* drv_open */ ++ drv_priv->drv_ops.drv_stop = drv_suspend; /* drv_stop */ ++ drv_priv->drv_ops.add_interface = drv_add_wnet_vif; /* add_interface */ ++ drv_priv->drv_ops.remove_interface = drv_delete_wnet_vif; /* remove_interface */ ++ drv_priv->drv_ops.change_interface = drv_change_wnet_vif; /* change_interface */ ++ drv_priv->drv_ops.down_interface = drv_wnet_vif_disconnect; /* down_interface */ ++ drv_priv->drv_ops.alloc_nsta = drv_nsta_attach; /* alloc_nsta */ ++ drv_priv->drv_ops.free_nsta = drv_nsta_detach; /* free_nsta */ ++ drv_priv->drv_ops.cleanup_nsta = drv_nsta_cleanup; /* cleanup_nsta */ ++ drv_priv->drv_ops.update_nsta_pwrsave = drv_nsta_update_pwrsave; /* update_nsta_pwrsave */ ++ drv_priv->drv_ops.new_assoc = drv_assoc_proc; /* new_assoc */ ++ drv_priv->drv_ops.reset = drv_reset; /* reset */ ++ drv_priv->drv_ops.set_channel = drv_set_channel; /* set_channel */ ++ drv_priv->drv_ops.scan_start = drv_scan_start; /* scan_start */ ++ drv_priv->drv_ops.fw_repair = drv_fw_recovery; /* fw_repair */ ++ drv_priv->drv_ops.scan_end = drv_scan_end; /* scan_end */ ++ drv_priv->drv_ops.connect_start = drv_connect_start; /* connect_start */ ++ drv_priv->drv_ops.connect_end = drv_connect_end; /* connect_end */ ++ drv_priv->drv_ops.set_channel_rssi = drv_set_channel_rssi; /* set_channel_rssi */ ++ drv_priv->drv_ops.set_tx_power_accord_rssi = drv_set_tx_power_accord_rssi;/* set_tx_power_accord_rssi */ ++ drv_priv->drv_ops.tx_init = drv_tx_init; /* tx_init */ ++ drv_priv->drv_ops.tx_cleanup = drv_txlist_cleanup; /* tx_cleanup */ ++ drv_priv->drv_ops.tx_wmm_queue_update = drv_update_wmmq_param; /* tx_wmm_queue_update */ ++ drv_priv->drv_ops.tx_start = drv_tx_start; /* tx_start */ ++ drv_priv->drv_ops.txlist_qcnt_handle = drv_txlist_qcnt; /* txlist_qcnt */ ++ drv_priv->drv_ops.txlist_all_qcnt = drv_txlist_all_qcnt; /* txlist_all_qcnt */ ++ drv_priv->drv_ops.txlist_isfull = drv_txlist_isfull; /* txlist_isfull */ ++ drv_priv->drv_ops.rx_init = drv_rx_init; /* rx_init */ ++ drv_priv->drv_ops.rx_proc_frame = drv_rx_input; /* rx_proc_frame */ ++ drv_priv->drv_ops.check_aggr = drv_aggr_check; /* check_aggr */ ++ drv_priv->drv_ops.aggr_tid_query = drv_aggr_tid; /* aggr_tid_query */ ++ drv_priv->drv_ops.check_aggr_allow_to_send = drv_aggr_allow_to_send;/* drv_aggr_allow_to_send */ ++ drv_priv->drv_ops.set_ampdu_params = drv_set_ampduparams; /* set_ampdu_params */ ++ drv_priv->drv_ops.addba_request_setup = drv_addba_req_setup; /* addba_request_setup */ ++ drv_priv->drv_ops.addba_response_setup = drv_rx_addbarsp; /* addba_response_setup */ ++ drv_priv->drv_ops.addba_request_process = drv_rx_addbareq; /* addba_request_process */ ++ drv_priv->drv_ops.addba_response_process = drv_addba_rsp_process; /* addba_response_process */ ++ drv_priv->drv_ops.addba_clear = drv_addba_clear; /* addba_clear */ ++ drv_priv->drv_ops.delba_process = drv_rx_delba; /* delba_process */ ++ drv_priv->drv_ops.addba_status = drv_addba_status; /* addba_status */ ++ drv_priv->drv_ops.drv_txrxampdu_del = drv_txrxampdu_del; /* drv_txrxampdu_del */ ++ drv_priv->drv_ops.set_addbaresponse = drv_set_addba_rsp; /* set_addbaresponse */ ++ drv_priv->drv_ops.clear_addbaresponsestatus = drv_clr_addba_rsp_status;/* clear_addbaresponsestatus */ ++ drv_priv->drv_ops.set_slottime = drv_update_slot; /* set_slottime */ ++ drv_priv->drv_ops.set_protmode = drv_set_protmode; /* set_protmode */ ++ drv_priv->drv_ops.set_cfg_txpowlimit = drv_set_cfg_tx_power_limit; /* set_cfg_txpowlimit */ ++ drv_priv->drv_ops.key_delete = drv_key_rst; /* key_delete */ ++ drv_priv->drv_ops.key_set = drv_key_set; /* key_set */ ++ drv_priv->drv_ops.rekey_data_set = drv_rekey_data_set; /* rekey_data_set */ ++ drv_priv->drv_ops.awake = drv_pwrsave_awake; /* awake */ ++ drv_priv->drv_ops.netsleep = drv_pwrsave_netsleep; /* netsleep */ ++ drv_priv->drv_ops.fullsleep = drv_pwrsave_fullsleep; /* fullsleep */ ++ drv_priv->drv_ops.set_country = drv_set_country; /* set_country */ ++ drv_priv->drv_ops.get_current_country = drv_get_curr_cntry; /* get_current_country */ ++ drv_priv->drv_ops.set_quiet = drv_set_quiet; /* set_quiet */ ++ drv_priv->drv_ops.set_bwmode = drv_set_chan_bw_mode; /* set_bwmode */ ++ drv_priv->drv_ops.GetSecondChanBusy = drv_get_scn_chan_busy; /* GetSecondChanBusy */ ++ drv_priv->drv_ops.drv_get_config_param = drv_get_config; /* drv_get_config_param */ ++ drv_priv->drv_ops.drv_set_config_param = drv_set_config; /* drv_set_config_param */ ++ drv_priv->drv_ops.get_noisefloor = drv_get_noise_floor; /* get_noisefloor */ ++ drv_priv->drv_ops.drv_set_txPwrLimit = drv_set_tx_pwr_limit; /* drv_set_txPwrLimit */ ++ drv_priv->drv_ops.get_amsdu_supported = drv_get_amsdu_supported; /* get_amsdu_supported */ ++ drv_priv->drv_ops.process_uapsd_trigger = drv_process_uapsd_nsta_trigger;/* process_uapsd_trigger */ ++ drv_priv->drv_ops.uapsd_qcnt = drv_tx_uapsd_nsta_qcnt; /* uapsd_qcnt */ ++ drv_priv->drv_ops.set_macaddr = drv_set_mac_addr; /* set_macaddr */ ++ drv_priv->drv_ops.Low_register_behindTask = drv_low_reg_behind_task;/* Low_register_behindTask */ ++ drv_priv->drv_ops.Low_callRegisteredTask = drv_low_call_task; /* Low_callRegisteredTask */ ++ drv_priv->drv_ops.Low_addDHWorkTask = drv_low_add_worktask; /* Low_addDHWorkTask */ ++ drv_priv->drv_ops.RegisterStationID = drv_phy_reg_sta_id; /* RegisterStationID */ ++ drv_priv->drv_ops.clear_staid_and_bssid = drv_clear_staid_and_bssid;/* clear_staid_and_bssid */ ++ drv_priv->drv_ops.UnRegisterAllStationID = drv_phy_unreg_all_sta_id;/* UnRegisterAllStationID */ ++ drv_priv->drv_ops.phy_setchannelsupport = NULL; /* drv_set_channelsupport */ ++ drv_priv->drv_ops.Phy_beaconinit = drv_bcn_init; /* Phy_beaconinit */ ++ drv_priv->drv_ops.Phy_SetBeaconStart = drv_set_bcn_start; /* Phy_SetBeaconStart */ ++ drv_priv->drv_ops.Phy_PutBeaconBuf = drv_put_bcn_buf; /* Phy_PutBeaconBuf */ + /* drv_hal_set_p2p_opps_cwend_enable */ + drv_priv->drv_ops.drv_hal_set_p2p_opps_cwend_enable = drv_hal_set_p2p_opps_cwend_enable; + /* drv_hal_set_p2p_noa_enable */ + drv_priv->drv_ops.drv_hal_set_p2p_noa_enable = drv_hal_set_p2p_noa_enable; -+ drv_priv->drv_ops.drv_hal_get_tsf = drv_hal_get_tsf;/* drv_hal_get_tsf */ -+ drv_priv->drv_ops.drv_hal_tx_frm_pause = drv_hal_tx_frm_pause; /* drv_hal_tx_frm_pause */ ++ drv_priv->drv_ops.drv_hal_get_tsf = drv_hal_get_tsf; /* drv_hal_get_tsf */ ++ drv_priv->drv_ops.drv_hal_tx_frm_pause = drv_hal_tx_frm_pause; /* drv_hal_tx_frm_pause */ + drv_priv->drv_ops.drv_p2p_client_opps_cwend_may_sleep = drv_p2p_client_opps_cwend_may_sleep; + drv_priv->drv_ops.drv_txq_backup_send = drv_txq_backup_send; + drv_priv->drv_ops.phy_stc = phy_stc; @@ -54058,15 +54422,16 @@ index 000000000000..abeda5f1221a + +void aml_set_mac_control_register(void) +{ -+ unsigned int read_tmp = 0; ++ unsigned int read_tmp; ++ + read_tmp = drv_read_word(MAC_CONTROL); -+ read_tmp |= BIT(20); //enable qos null frame not update bitmap ++ read_tmp |= BIT(20); /* enable qos null frame not update bitmap */ + drv_write_word(MAC_CONTROL, read_tmp); +} + -+int aml_driv_attach( struct drv_private *drv_priv, struct wifi_mac* wmac) ++int aml_driv_attach( struct drv_private *drv_priv, struct wifi_mac *wmac) +{ -+ int i ; ++ int i; + int error; + char *country_code = NULL; + int country_index = DEFAULT_CONTRY; @@ -54077,17 +54442,17 @@ index 000000000000..abeda5f1221a + + drv_priv->wmac = wmac; + drv_priv->net_ops = &wmac->wmac_ops; -+ drv_priv->drv_not_init_flag = 1; ++ drv_priv->drv_not_init_flag = 1; + drv_priv->drv_connetting = 0; + drv_priv->drv_scanning = 0; + drv_priv->is_mother_channel[0] = 1; + drv_priv->is_mother_channel[1] = 1; -+ drv_priv->drv_config.cfg_cachelsz = DEFAULT_CACHESIZE; /* convert to bytes */ ++ drv_priv->drv_config.cfg_cachelsz = DEFAULT_CACHESIZE; /* convert to bytes */ + drv_priv->wait_mpdu_timeout = 1; + drv_priv->add_wakeup_work = 0; + drv_priv->stop_noa_flag = 0; + -+ drv_hal_attach(drv_priv, (void *)get_hal_call_back_table()); //attach hal ++ drv_hal_attach(drv_priv, (void *)get_hal_call_back_table()); /* attach hal */ + + drv_priv->hal_priv = hal_get_priv(); + @@ -54096,72 +54461,72 @@ index 000000000000..abeda5f1221a + + country_code = aml_wifi_get_country_code(); + -+ printk(" %s %d insmod country: %s\n", __func__, __LINE__,country_code); ++ pr_debug(" %s %d insmod country: %s\n", __func__, __LINE__, ++ country_code); + + country_index = find_country_code((unsigned char *)country_code); + if (country_index != 0xff) { + drv_priv->drv_config.cfg_countrycode = country_index; -+ + } else { + drv_priv->drv_config.cfg_countrycode = 0; + } + -+ drv_priv->drv_config.cfg_txpoweplan = wifimac_get_tx_pwr_plan(drv_priv->drv_config.cfg_countrycode); -+ drv_priv->drv_config.cfg_ampduackpolicy = DEFAULT_AMPDUACKPOLICY; -+ drv_priv->drv_config.cfg_htsupport = DEFAULT_HT_ENABLE; -+ drv_priv->drv_config.cfg_vhtsupport = DEFAULT_VHT_ENABLE; -+ drv_priv->drv_config.cfg_burst_ack = DEFAULT_BURST_ENABLE; -+ drv_priv->drv_config.cfg_txpowlimit = DEFAULT_TXPOWER; -+ drv_priv->drv_config.cfg_aggr_prot = DEFAULT_TXAGG_PROT; -+ drv_priv->drv_config.cfg_disratecontrol = DEFAULT_RATECONTROL_DIS; -+ drv_priv->drv_config.cfg_haswme = DEFAULT_WMMSUPPORT; -+ drv_priv->drv_config.cfg_dynamic_bw = ~DEFAULT_SUPPORT_DYNAMIC_BW; ++ drv_priv->drv_config.cfg_txpoweplan = wifimac_get_tx_pwr_plan(drv_priv->drv_config.cfg_countrycode); ++ drv_priv->drv_config.cfg_ampduackpolicy = DEFAULT_AMPDUACKPOLICY; ++ drv_priv->drv_config.cfg_htsupport = DEFAULT_HT_ENABLE; ++ drv_priv->drv_config.cfg_vhtsupport = DEFAULT_VHT_ENABLE; ++ drv_priv->drv_config.cfg_burst_ack = DEFAULT_BURST_ENABLE; ++ drv_priv->drv_config.cfg_txpowlimit = DEFAULT_TXPOWER; ++ drv_priv->drv_config.cfg_aggr_prot = DEFAULT_TXAGG_PROT; ++ drv_priv->drv_config.cfg_disratecontrol = DEFAULT_RATECONTROL_DIS; ++ drv_priv->drv_config.cfg_haswme = DEFAULT_WMMSUPPORT; ++ drv_priv->drv_config.cfg_dynamic_bw = ~DEFAULT_SUPPORT_DYNAMIC_BW; + drv_priv->drv_config.cfg_wifi_bt_coexist_support = DEFAULT_SUPPORT_WIFI_BT_COEXIST; + + /* 11n Capabilities */ + if (drv_priv->drv_config.cfg_htsupport) + { -+ drv_priv->drv_config.cfg_ampdu_limit = DEFAULT_TXAMPDU_LEN_MAX; -+ drv_priv->drv_config.cfg_txaggr = DEFAULT_TXAMPDU_EN; -+ drv_priv->drv_config.cfg_rxaggr = DEFAULT_RXAMPDU_EN; -+ drv_priv->drv_config.cfg_txamsdu = DEFAULT_TXAMSDU_EN; ++ drv_priv->drv_config.cfg_ampdu_limit = DEFAULT_TXAMPDU_LEN_MAX; ++ drv_priv->drv_config.cfg_txaggr = DEFAULT_TXAMPDU_EN; ++ drv_priv->drv_config.cfg_rxaggr = DEFAULT_RXAMPDU_EN; ++ drv_priv->drv_config.cfg_txamsdu = DEFAULT_TXAMSDU_EN; + drv_priv->drv_config.cfg_ampdu_subframes = DEFAULT_TXAMPDU_SUB_MAX; -+ drv_priv->drv_config.cfg_40Msupport = DEFAULT_11N40M_SUPPORT; ++ drv_priv->drv_config.cfg_40Msupport = DEFAULT_11N40M_SUPPORT; + drv_priv->drv_config.cfg_ampdu_oneframe = DEFAULT_TXAMPDU_ONEFRAME; -+ drv_priv->drv_config.cfg_ampdu_livetime = DEFAULT_TXAMPDU_ONEFRAME; ++ drv_priv->drv_config.cfg_ampdu_livetime = DEFAULT_TXAMPDU_ONEFRAME; + } + + /* set short retry 100, long retry 100, firmware try more times to send out */ + drv_set_config((void *)drv_priv, CHIP_PARAM_RETRY_LIMIT, 100 << 8 | 100); + -+ /*11AC capabilities*/ ++ /* 11AC capabilities */ + if (drv_priv->drv_config.cfg_vhtsupport) + { -+ // T.B.D -+ } -+ -+ drv_priv->drv_config.cfg_txchainmask = DEFAULT_TXCHAINMASK; //chainmask: not support yet -+ drv_priv->drv_config.cfg_rxchainmask = DEFAULT_RXCHAINMASK; -+ drv_priv->drv_config.cfg_txchainmasklegacy = DEFAULT_TXCHAINMASKLEGACY; -+ drv_priv->drv_config.cfg_rxchainmasklegacy = DEFAULT_RXCHAINMASKLEGACY; -+ drv_priv->drv_config.cfg_bw_ctrl = DEFAULT_BWC_ENABLE; -+ drv_priv->drv_config.cfg_aessupport = 1;/*aes support*/ -+ drv_priv->drv_config.cfg_tkipsupport = 1;/*tkip support*/ -+ drv_priv->drv_config.cfg_wepsupport = 1;/*wep support*/ -+ drv_priv->drv_config.cfg_wapisupport = 1;/*wapi support*/ -+ drv_priv->drv_config.cfg_tkipmicsupport = DEFAULT_HW_TKIP_MIC;/*tkip mic support*/ -+ drv_priv->drv_config.cfg_rtcenable = DEFAULT_RTC_ENABLE; -+ drv_priv->drv_config.cfg_retrynum = DEFAULT_TXRETRY_MAX; -+ drv_priv->drv_config.cfg_uapsdsupported = DEFAULT_UAPSU_EN; -+ drv_priv->drv_config.cfg_modesupport = DEFAULT_SELECT_MODE; -+ drv_priv->drv_config.cfg_checksumoffload = DEFAULT_HW_CSUM; ++ /* T.B.D */ ++ } ++ ++ drv_priv->drv_config.cfg_txchainmask = DEFAULT_TXCHAINMASK; /* chainmask: not support yet */ ++ drv_priv->drv_config.cfg_rxchainmask = DEFAULT_RXCHAINMASK; ++ drv_priv->drv_config.cfg_txchainmasklegacy = DEFAULT_TXCHAINMASKLEGACY; ++ drv_priv->drv_config.cfg_rxchainmasklegacy = DEFAULT_RXCHAINMASKLEGACY; ++ drv_priv->drv_config.cfg_bw_ctrl = DEFAULT_BWC_ENABLE; ++ drv_priv->drv_config.cfg_aessupport = 1;/* aes support */ ++ drv_priv->drv_config.cfg_tkipsupport = 1;/* tkip support */ ++ drv_priv->drv_config.cfg_wepsupport = 1;/* wep support */ ++ drv_priv->drv_config.cfg_wapisupport = 1;/* wapi support */ ++ drv_priv->drv_config.cfg_tkipmicsupport = DEFAULT_HW_TKIP_MIC; /* tkip mic support */ ++ drv_priv->drv_config.cfg_rtcenable = DEFAULT_RTC_ENABLE; ++ drv_priv->drv_config.cfg_retrynum = DEFAULT_TXRETRY_MAX; ++ drv_priv->drv_config.cfg_uapsdsupported = DEFAULT_UAPSU_EN; ++ drv_priv->drv_config.cfg_modesupport = DEFAULT_SELECT_MODE; ++ drv_priv->drv_config.cfg_checksumoffload = DEFAULT_HW_CSUM; + drv_priv->drv_config.cfg_eap_lowest_rate = DEFAULT_MCAST_EAPOL_NULLDATA_RATE_11G; -+ drv_priv->drv_config.cfg_dssupport = DEFAULT_DSSUPPORT; ++ drv_priv->drv_config.cfg_dssupport = DEFAULT_DSSUPPORT; + drv_priv->drv_config.cfg_eat_count_max = DEFAULT_EAT_COUNT_MAX; + drv_priv->drv_config.cfg_aggr_thresh = DEFAULT_AGGR_THRESH; + drv_priv->drv_config.cfg_no_aggr_thresh = DEFAULT_NO_AGGR_THRESH; + drv_priv->drv_config.cfg_hrtimer_interval = DEFAULT_HRTIMER_INTERVAL; -+ drv_priv->drv_config.cfg_mfp = DEFAULT_MFP_EN;//support mfp ++ drv_priv->drv_config.cfg_mfp = DEFAULT_MFP_EN; /* support mfp */ + drv_priv->drv_config.cfg_mac_mode = DEFAULT_AUTO; + drv_priv->drv_config.cfg_band = DEFAULT_BAND_ALL; + @@ -54179,15 +54544,16 @@ index 000000000000..abeda5f1221a + if (error != 0) + { + driv_ps_sleep(drv_priv); -+ ERROR_DEBUG_OUT(" error!!!\n"); ++ ERROR_DEBUG_OUT(" error!!!\n"); + goto bad; + } + -+ wifi_mac_set_tx_power_coefficient(drv_priv, NULL, drv_priv->drv_config.cfg_txpoweplan); ++ wifi_mac_set_tx_power_coefficient(drv_priv, NULL, ++ drv_priv->drv_config.cfg_txpoweplan); + + drv_priv->net_ops->wifi_mac_rate_ratmod_attach(drv_priv); -+ printk(" %s %d drv_priv->drv_ratectrl_size = %d\n", -+ __func__,__LINE__,drv_priv->drv_ratectrl_size); ++ pr_debug(" %s %d drv_priv->drv_ratectrl_size = %d\n", ++ __func__,__LINE__,drv_priv->drv_ratectrl_size); + + /* + * Setup rate tables for all potential media types. @@ -54206,7 +54572,7 @@ index 000000000000..abeda5f1221a + return -ENODEV; +} + -+void aml_driv_detach( struct drv_private * drv_priv) ++void aml_driv_detach( struct drv_private *drv_priv) +{ + int i; + @@ -54224,25 +54590,23 @@ index 000000000000..abeda5f1221a + drv_hal_detach(); +} + -+ -+static int drv_read_manu_cfg(void * drv_priv, void* cfg) ++static int drv_read_manu_cfg(void *drv_priv, void *cfg) +{ -+ printk("maybe involve nand/nor flash operating function,to get manufactory cfg\n"); ++ pr_debug("maybe involve nand/nor flash operating function,to get manufactory cfg\n"); + return 0; +} + -+static int drv_get_default_cfg(void * drv_priv, void* cfg) ++static int drv_get_default_cfg(void *drv_priv, void *cfg) +{ -+ return drv_read_manu_cfg(drv_priv,cfg); ++ return drv_read_manu_cfg(drv_priv, cfg); +} + -+ +static void -+drv_mic_error_event(void * dpriv,const void* frm, -+ unsigned char* sa,unsigned char wnet_vif_id) ++drv_mic_error_event(void *dpriv, const void *frm, unsigned char *sa, ++ unsigned char wnet_vif_id) +{ +#if 1 -+ struct wifi_station *sta = NULL; ++ struct wifi_station *sta; + struct wifi_frame *wh = (struct wifi_frame *)frm; + struct drv_private *drv_priv = (struct drv_private *)dpriv; + struct wlan_net_vif *wnet_vif = drv_priv->drv_wnet_vif_table[wnet_vif_id]; @@ -54252,7 +54616,7 @@ index 000000000000..abeda5f1221a + sta = drv_priv->net_ops->wifi_mac_get_sta(nt, sa, wnet_vif_id); + if (sta == NULL) + { -+ printk("mic_error_event find not error! \n"); ++ pr_err("mic_error_event find not error! \n"); + return ; + } + rsn = &sta->sta_rsn; @@ -54260,12 +54624,13 @@ index 000000000000..abeda5f1221a + if (WIFINET_IS_MULTICAST(wh->i_addr1)) + { + if(rsn->rsn_mcastcipher == WIFINET_CIPHER_TKIP) -+ drv_priv->net_ops->wifi_mac_notify_mic_fail(wnet_vif,wh, (int)wnet_vif->vm_def_txkey); ++ drv_priv->net_ops->wifi_mac_notify_mic_fail(wnet_vif, wh, ++ (int)wnet_vif->vm_def_txkey); + } + else + { + if(rsn->rsn_ucastcipher == WIFINET_CIPHER_TKIP) -+ drv_priv->net_ops->wifi_mac_notify_mic_fail(wnet_vif,wh, 0); ++ drv_priv->net_ops->wifi_mac_notify_mic_fail(wnet_vif, wh, 0); + } +#endif +} @@ -54277,9 +54642,11 @@ index 000000000000..abeda5f1221a + + if (drv_private != NULL) { + DRV_TX_TIMEOUT_LOCK(drv_private); ++ + if (!g_hr_lock_timer_valid) { + drv_private->wait_mpdu_timeout = 1; + } ++ + AML_PRINT(AML_DBG_MODULES_TX, "waiting_pkt_timeout:%d\n", drv_private->wait_mpdu_timeout); + DRV_TX_TIMEOUT_UNLOCK(drv_private); + } @@ -54295,20 +54662,20 @@ index 000000000000..abeda5f1221a +} + +static void -+drv_intr_rx_ok(void * dpriv,struct sk_buff *skb, unsigned char Rssi,unsigned char vendor_rate_code, -+ unsigned char bw, unsigned char channel, unsigned char aggr, unsigned char wnet_vif_id, unsigned char keyid) ++drv_intr_rx_ok(void *dpriv, struct sk_buff *skb, unsigned char Rssi, unsigned char vendor_rate_code, ++ unsigned char bw, unsigned char channel, unsigned char aggr, unsigned char wnet_vif_id, ++ unsigned char keyid) +{ + struct wifi_mac *wifimac; + struct drv_private *drv_priv = (struct drv_private *)dpriv; -+ + struct sk_buff *skbbuf = (struct sk_buff *)skb; + struct wifi_frame *wh; + struct wifi_mac_rx_status rxstatus; -+ int rate_index =0; ++ int rate_index; + + wifimac = drv_priv->wmac; + -+ rate_index= drv_rate_findindex_from_ratecode(drv_priv->drv_currratetable, vendor_rate_code); ++ rate_index = drv_rate_findindex_from_ratecode(drv_priv->drv_currratetable, vendor_rate_code); + + rxstatus.rs_flags = aggr; + rxstatus.rs_channel = channel; @@ -54320,7 +54687,6 @@ index 000000000000..abeda5f1221a + rxstatus.rs_wnet_vif_id = wnet_vif_id; + rxstatus.rs_keyid = keyid ; + -+ + wh = (struct wifi_frame *)os_skb_data(skb); + if (!list_empty(&wifimac->wm_wnet_vifs)) + { @@ -54335,15 +54701,16 @@ index 000000000000..abeda5f1221a +} + +static int pmf_encrypt_pkt_handle(void *dpriv, struct sk_buff *skb, unsigned char rssi, -+ unsigned char vendor_rate_code, unsigned char channel, unsigned char aggr, unsigned char wnet_vif_id, unsigned char keyid) ++ unsigned char vendor_rate_code, unsigned char channel, ++ unsigned char aggr, unsigned char wnet_vif_id, ++ unsigned char keyid) +{ -+ + struct wifi_mac *wifimac; -+ struct drv_private *drv_priv= (struct drv_private *)dpriv; -+ struct sk_buff *skbbuf = ( struct sk_buff *)skb; + struct wifi_frame *wh; ++ struct drv_private *drv_priv = (struct drv_private *)dpriv; ++ struct sk_buff *skbbuf = (struct sk_buff *)skb; + struct wifi_mac_rx_status rxstatus; -+ int rate_index = 0; ++ int rate_index; + unsigned char pkt_type; + unsigned char is_protect; + @@ -54357,11 +54724,11 @@ index 000000000000..abeda5f1221a + #if 0 + unsigned char i; + -+ printk("pmf pkt, not drop\n"); ++ pr_debug("pmf pkt, not drop\n"); + for (i = 0; i < 32; ++i) { -+ printk("%02x:", ((unsigned char *)wh)[i]); ++ pr_debug("%02x:", ((unsigned char *)wh)[i]); + } -+ printk("\n"); ++ pr_debug("\n"); + #endif + } + @@ -54379,7 +54746,6 @@ index 000000000000..abeda5f1221a + if (!list_empty(&wifimac->wm_wnet_vifs)) { + drv_priv->drv_stats.rx_indicate_cnt++; + drv_priv->net_ops->wifi_mac_rx_complete(wifimac, skbbuf, &rxstatus); -+ + } else { + drv_priv->drv_stats.rx_free_skb_cnt++; + os_skb_free(skb); @@ -54408,6 +54774,7 @@ index 000000000000..abeda5f1221a + if ((p2p->HiP2pNoaCountNow == 0) && (p2p->noa.count == NET80211_P2P_SCHED_REPEAT)) { + p2p->HiP2pNoaCountNow = (p2p->noa.count << 1); + } ++ + HiP2pNoaCountNow = p2p->HiP2pNoaCountNow; + + if (P2P_NoA_START_FLAG(HiP2pNoaCountNow)) { @@ -54415,15 +54782,16 @@ index 000000000000..abeda5f1221a + AML_PRINT(AML_DBG_MODULES_P2P, "noa start HiP2pNoaCountNow=%d\n", + HiP2pNoaCountNow); + /* -+ check power save precedence of GO as follow: -+ 1. Highest: Absence due to a non-periodic Notice of Absence (Count = 1). -+ 2. Presence from TBTT until the end of Beacon frame transmission. -+ 3. Presence during the CTWindow. -+ 4. Lowest: Absence for a periodic Notice of Absence (Count > 1). -+ */ -+ if ((p2p->noa.count > 1) && (p2p->p2p_flag & P2P_OPPPS_START_FLAG_HI) -+ && (!(p2p->p2p_flag & P2P_OPPPS_CWEND_FLAG_HI) || (wnet_vif->vm_pstxqueue_flags & WIFINET_PSQUEUE_OPPS))) { -+ /*noa count != 1, opps is already start and sleep, just return; */ ++ * check power save precedence of GO as follow: ++ * 1. Highest: Absence due to a non-periodic Notice of Absence (Count = 1). ++ * 2. Presence from TBTT until the end of Beacon frame transmission. ++ * 3. Presence during the CTWindow. ++ * 4. Lowest: Absence for a periodic Notice of Absence (Count > 1). ++ */ ++ if ((p2p->noa.count > 1) && (p2p->p2p_flag & P2P_OPPPS_START_FLAG_HI) && ++ (!(p2p->p2p_flag & P2P_OPPPS_CWEND_FLAG_HI) || ++ (wnet_vif->vm_pstxqueue_flags & WIFINET_PSQUEUE_OPPS))) { ++ /* noa count != 1, opps is already start and sleep, just return; */ + return; + } + wnet_vif->vm_pstxqueue_flags |= WIFINET_PSQUEUE_NOA; @@ -54446,7 +54814,7 @@ index 000000000000..abeda5f1221a + { + /* if noa end */ + DPRINTF(AML_DEBUG_PWR_SAVE, "%s %d noa end HiP2pNoaCountNow=%d\n", -+ __func__,__LINE__, HiP2pNoaCountNow); ++ __func__, __LINE__, HiP2pNoaCountNow); + + wnet_vif->vm_pstxqueue_flags &= (~WIFINET_PSQUEUE_NOA); + @@ -54474,9 +54842,10 @@ index 000000000000..abeda5f1221a + { + /* retry trigger. may drop response to last-time trigger */ + struct wifi_station *sta = wnet_vif->vm_mainsta; ++ + if (sta->sta_flags_ext & WIFINET_NODE_TRIGGER_WAIT_NOA_END) + { -+ drv_priv->net_ops->wifi_mac_pwrsave_sta_trigger(wnet_vif); ++ drv_priv->net_ops->wifi_mac_pwrsave_sta_trigger(wnet_vif); + sta->sta_flags_ext &= ~WIFINET_NODE_TRIGGER_WAIT_NOA_END; + } + } @@ -54511,7 +54880,9 @@ index 000000000000..abeda5f1221a + if (sta->sta_flags_ext & WIFINET_NODE_UAPSD_FLUSH_WAIT_NOA_END) + { + int uapsd_len = wifimac->drv_priv->drv_ops.process_uapsd_trigger(wifimac->drv_priv, -+ sta->drv_sta, WME_UAPSD_NODE_MAXQDEPTH, 0, 1); ++ sta->drv_sta, ++ WME_UAPSD_NODE_MAXQDEPTH, ++ 0, 1); + + if (uapsd_len <= 0) + { @@ -54527,27 +54898,26 @@ index 000000000000..abeda5f1221a + if (HiP2pNoaCountNow == 0) + { + /* noa need to be canceled */ -+ + if (wnet_vif->vm_opmode == WIFINET_M_HOSTAP) + { -+ vm_p2p_go_cancle_noa(p2p); ++ vm_p2p_go_cancel_noa(p2p); + } + else if (wnet_vif->vm_opmode == WIFINET_M_STA) + { -+ vm_p2p_client_cancle_noa(p2p); ++ vm_p2p_client_cancel_noa(p2p); + } + } + + if (drv_priv->net_ops->wifi_mac_pwrsave_is_sta_sleeping(wnet_vif) == 0) + { -+ drv_priv->net_ops->wifi_mac_pwrsave_fullsleep(wnet_vif, SLEEP_AFTER_NOA_END_DUMMY); ++ drv_priv->net_ops->wifi_mac_pwrsave_fullsleep(wnet_vif, SLEEP_AFTER_NOA_END_DUMMY); + } + } + while (0); + } +} + -+static void p2p_opps_ctw_start_irq (struct wifi_mac_p2p *p2p) ++static void p2p_opps_ctw_start_irq(struct wifi_mac_p2p *p2p) +{ + if (p2p->p2p_flag & P2P_OPPPS_START_FLAG_HI) + { @@ -54557,11 +54927,11 @@ index 000000000000..abeda5f1221a + /* wakeup and tx */ + p2p->wnet_vif->vm_pstxqueue_flags &= (~WIFINET_PSQUEUE_OPPS); + /* -+ if noa count == 1 and noa started, so we remain NoA ps state. -+ And we need clear flags of Opps for subsequent NoA (count == 1 or periodic). -+ if noa coun > 1 (periodically), the precedence of opps is higher than noa, so -+ we clear noa ps flag to send frames. -+ */ ++ * If noa count == 1 and noa started, so we remain NoA ps state. ++ * And we need clear flags of Opps for subsequent NoA (count == 1 or periodic). ++ * If noa coun > 1 (periodically), the precedence of opps is higher than noa, so ++ * we clear noa ps flag to send frames. ++ */ + if (p2p->wnet_vif->vm_p2p->noa.count > 1) + { + p2p->wnet_vif->vm_pstxqueue_flags &= (~WIFINET_PSQUEUE_NOA); @@ -54575,47 +54945,53 @@ index 000000000000..abeda5f1221a +static void drv_intr_bcn_send_ok(void * dpriv,unsigned char vma_id) +{ + struct drv_private *drv_priv = (struct drv_private *)dpriv; -+ struct wlan_net_vif *wnet_vif = NULL; ++ struct wlan_net_vif *wnet_vif; + struct wifi_mac *wifimac; + struct sk_buff *skb; -+ unsigned char rate = 0; + unsigned short flag; + -+ wnet_vif = drv_priv->drv_wnet_vif_table[vma_id]; -+ if((wnet_vif== NULL)||(wnet_vif->vm_state != WIFINET_S_CONNECTED)) ++ wnet_vif = drv_priv->drv_wnet_vif_table[vma_id]; ++ if ((wnet_vif == NULL) || (wnet_vif->vm_state != WIFINET_S_CONNECTED)) + return; ++ + wifimac = wnet_vif->vm_wmac; + + if ((wnet_vif->vm_opmode == WIFINET_M_HOSTAP)|| + (wnet_vif->vm_opmode == WIFINET_M_IBSS)) + { ++ unsigned char rate = 0; ++ + drv_tx_get_mgmt_frm_rate(drv_priv, wnet_vif, -+ WIFINET_FC0_TYPE_MGT | WIFINET_FC0_SUBTYPE_BEACON, &rate, &flag); ++ WIFINET_FC0_TYPE_MGT | WIFINET_FC0_SUBTYPE_BEACON, ++ &rate, &flag); + + WIFINET_BEACONBUF_LOCK(wifimac); ++ + skb = wnet_vif->vm_beaconbuf; + if(skb) + { -+ drv_priv->net_ops->wifi_mac_update_beacon(drv_priv->wmac, vma_id,skb, 0); -+ drv_hal_put_bcn_buf(vma_id, os_skb_data(skb), os_skb_get_pktlen(skb), rate, wnet_vif->vm_bandwidth); ++ drv_priv->net_ops->wifi_mac_update_beacon(drv_priv->wmac, vma_id, skb, 0); ++ drv_hal_put_bcn_buf(vma_id, os_skb_data(skb), os_skb_get_pktlen(skb), ++ rate, wnet_vif->vm_bandwidth); + } + else + { -+ printk("Enter %s Function ERROR \n",__func__); ++ pr_err("Enter %s Function ERROR \n",__func__); + } + WIFINET_BEACONBUF_UNLOCK(wifimac); + +#ifdef CONFIG_P2P -+ if ((drv_priv->net_ops->wifi_mac_pwrsave_is_wnet_vif_fullsleep(wnet_vif) == 0) -+ && (wnet_vif->vm_p2p->p2p_flag & P2P_OPPPS_START_FLAG_HI)) ++ if ((drv_priv->net_ops->wifi_mac_pwrsave_is_wnet_vif_fullsleep(wnet_vif) == 0) && ++ (wnet_vif->vm_p2p->p2p_flag & P2P_OPPPS_START_FLAG_HI)) + { -+ //drv_priv->net_ops->wifi_mac_pwrsave_networksleep(wnet_vif, NETSLEEP_AFTER_BEACON_SEND); ++ /* drv_priv->net_ops->wifi_mac_pwrsave_networksleep(wnet_vif, NETSLEEP_AFTER_BEACON_SEND); */ + } + + p2p_opps_ctw_start_irq(wnet_vif->vm_p2p); -+ if (wnet_vif->vm_p2p->p2p_flag & (P2P_NOA_START_MATCH_BEACON_HI|P2P_NOA_END_MATCH_BEACON_HI)) { -+ p2p_noa_start_irq(wnet_vif->vm_p2p, drv_priv); + ++ if (wnet_vif->vm_p2p->p2p_flag & ++ (P2P_NOA_START_MATCH_BEACON_HI | P2P_NOA_END_MATCH_BEACON_HI)) { ++ p2p_noa_start_irq(wnet_vif->vm_p2p, drv_priv); + } else if (wnet_vif->vm_pstxqueue_flags & WIFINET_PSQUEUE_NOA) { + drv_priv->net_ops->wifi_mac_pwrsave_fullsleep(wnet_vif, SLEEP_AFTER_NOA_START); + } @@ -54623,69 +54999,66 @@ index 000000000000..abeda5f1221a + } +} + -+ -+static void drv_intr_dtim_send_ok(void *drv_priv,unsigned char vma_id) ++static void drv_intr_dtim_send_ok(void *drv_priv, unsigned char vma_id) +{ + +} + -+ -+static void drv_intr_ba_recv_ok(void *drv_priv,unsigned char vma_id) ++static void drv_intr_ba_recv_ok(void *drv_priv, unsigned char vma_id) +{ -+ printk("Enter %s Function \n",__func__); ++ pr_debug("Enter %s Function \n",__func__); +} + +static int -+drv_get_sta_id(void * dpriv,unsigned char *mac, -+ unsigned char wnet_vif_id,int * staid) ++drv_get_sta_id(void *dpriv, unsigned char *mac, unsigned char wnet_vif_id, ++ int *staid) +{ -+ -+ struct wifi_station *sta = NULL; ++ struct wifi_station *sta; + struct wifi_station_tbl *nt; -+ struct drv_private *drv_priv= (struct drv_private *)dpriv; -+ struct wlan_net_vif *wnet_vif = NULL; ++ struct drv_private *drv_priv = (struct drv_private *)dpriv; ++ struct wlan_net_vif *wnet_vif; + + wnet_vif = drv_priv->drv_wnet_vif_table[wnet_vif_id]; + ASSERT(wnet_vif); + nt = &wnet_vif->vm_sta_tbl; + -+ sta = drv_priv->net_ops->wifi_mac_get_sta(nt, mac,wnet_vif_id); ++ sta = drv_priv->net_ops->wifi_mac_get_sta(nt, mac, wnet_vif_id); + if (sta == NULL) { + return -1; + } + + if (sta->sta_wnet_vif->vm_opmode == WIFINET_M_STA) { -+ *staid = 1; ++ *staid = 1; + } else { -+ *staid = sta->sta_associd&0xff; ++ *staid = sta->sta_associd & 0xff; + } + + return 0; +} + -+/*rtc tmp wakeup*/ ++/* rtc tmp wakeup */ +static void drv_goto_deep_sleep(void * dpriv) +{ + +} + -+static void drv_goto_wakeup(void * dpriv, unsigned char wnet_vif_id) ++static void drv_goto_wakeup(void *dpriv, unsigned char wnet_vif_id) +{ + struct drv_private *drv_priv = (struct drv_private *)dpriv; -+ struct wlan_net_vif *wnet_vif = NULL; ++ struct wlan_net_vif *wnet_vif; + + wnet_vif = drv_priv->drv_wnet_vif_table[wnet_vif_id]; + -+ //if vmac not exist, may sta irq mistake ++ /* if vmac not exist, may sta irq mistake */ + if (wnet_vif) + { -+ struct wifi_mac_pwrsave_t *ps = &wnet_vif->vm_pwrsave; ++ struct wifi_mac_pwrsave_t *ps = &wnet_vif->vm_pwrsave; + -+ //wifi_mac_pwrsave_show_state(wifimac); ++ /* wifi_mac_pwrsave_show_state(wifimac); */ + if (drv_priv->net_ops->wifi_mac_pwrsave_is_sta_fullsleep(wnet_vif) == 0) + { + WIFINET_PWRSAVE_LOCK(wnet_vif); -+ //wait for beacon timeout ++ /* wait for beacon timeout */ + ps->ips_sleep_wait_reason = SLEEP_AFTER_WAIT_BEACON_TIMEOUT; + os_timer_ex_start_period(&ps->ips_timer_sleep_wait, ps->ips_ps_waitbeacon_timeout); + ps->ips_flag_waitbeacon_timer_start = 1; @@ -54700,18 +55073,17 @@ index 000000000000..abeda5f1221a +} + +static void -+drv_p2p_opps_cwend_sleep (struct wlan_net_vif *wnet_vif, -+ struct drv_private *drv_priv) ++drv_p2p_opps_cwend_sleep(struct wlan_net_vif *wnet_vif, struct drv_private *drv_priv) +{ + wnet_vif->vm_pstxqueue_flags |= WIFINET_PSQUEUE_OPPS; + drv_priv->net_ops->wifi_mac_pwrsave_fullsleep(wnet_vif, SLEEP_AFTER_OPPS_END); +} + +int -+drv_p2p_go_opps_cwend_may_sleep (struct wlan_net_vif *wnet_vif) ++drv_p2p_go_opps_cwend_may_sleep(struct wlan_net_vif *wnet_vif) +{ + struct wifi_mac *wifimac = wnet_vif->vm_wmac; -+ struct drv_private * drv_priv = wifimac->drv_priv; ++ struct drv_private *drv_priv = wifimac->drv_priv; + int ret = -1; + + DPRINTF(AML_DEBUG_PWR_SAVE,"%s(%d) opmode %d vm_ps_sta %d " @@ -54722,13 +55094,13 @@ index 000000000000..abeda5f1221a + !drv_txlist_all_qcnt(drv_priv, HAL_WME_MCAST), + !drv_txlist_all_qcnt(drv_priv, HAL_WME_UAPSD)); + /* -+ * go goto sleep when no frames are going to send or are sent, -+ * all gc are in sleep state. -+ */ -+ if ((wifi_mac_pwrsave_if_ap_can_opps (wnet_vif) == 0) -+ && !drv_txlist_all_qcnt(drv_priv, HAL_WME_MCAST) -+ && !wnet_vif->vm_legacyps_txframes -+ && !drv_txlist_all_qcnt(drv_priv, HAL_WME_UAPSD)) ++ * go goto sleep when no frames are going to send or are sent, ++ * all gc are in sleep state. ++ */ ++ if ((wifi_mac_pwrsave_if_ap_can_opps (wnet_vif) == 0) && ++ !drv_txlist_all_qcnt(drv_priv, HAL_WME_MCAST) && ++ !wnet_vif->vm_legacyps_txframes && ++ !drv_txlist_all_qcnt(drv_priv, HAL_WME_UAPSD)) + { + drv_p2p_opps_cwend_sleep(wnet_vif, drv_priv); + ret = 0; @@ -54739,12 +55111,12 @@ index 000000000000..abeda5f1221a +int drv_p2p_client_opps_cwend_may_sleep (struct wlan_net_vif *wnet_vif) +{ + struct wifi_mac *wifimac = wnet_vif->vm_wmac; -+ struct drv_private * drv_priv = wifimac->drv_priv; ++ struct drv_private *drv_priv = wifimac->drv_priv; + int ret = -1; + -+ //for sta, if unicast trigger is in process, transfer to unicast -+ if ((wnet_vif->vm_opmode==WIFINET_M_STA) -+ && !wnet_vif->vm_pwrsave.ips_flag_send_ps_trigger) ++ /* for sta, if unicast trigger is in process, transfer to unicast */ ++ if ((wnet_vif->vm_opmode == WIFINET_M_STA) && ++ !wnet_vif->vm_pwrsave.ips_flag_send_ps_trigger) + { + drv_p2p_opps_cwend_sleep(wnet_vif, drv_priv); + ret = 0; @@ -54752,16 +55124,17 @@ index 000000000000..abeda5f1221a + return ret; +} + -+static void drv_intr_p2p_opps_cwend (void * dpriv,unsigned char wnet_vif_id) ++static void drv_intr_p2p_opps_cwend(void *dpriv,unsigned char wnet_vif_id) +{ + struct drv_private *drv_priv = (struct drv_private *)dpriv; -+ struct wlan_net_vif *wnet_vif = NULL; ++ struct wlan_net_vif *wnet_vif; + + wnet_vif = drv_priv->drv_wnet_vif_table[wnet_vif_id]; + if (wnet_vif) + { +#ifdef CONFIG_P2P + struct wifi_mac_p2p *p2p = wnet_vif->vm_p2p; ++ + if (p2p->p2p_flag & P2P_OPPPS_START_FLAG_HI) + { + wnet_vif->vm_p2p->p2p_flag |= P2P_OPPPS_CWEND_FLAG_HI; @@ -54775,12 +55148,12 @@ index 000000000000..abeda5f1221a + } + if (drv_p2p_client_opps_cwend_may_sleep(wnet_vif) == 0) + { -+ break;; ++ break; + } + if (wnet_vif->vm_pstxqueue_flags & WIFINET_PSQUEUE_NOA) + { -+ //if has trigger in process, just sleep. after noa end, trigger again -+ drv_priv->net_ops->wifi_mac_pwrsave_fullsleep(wnet_vif, SLEEP_AFTER_NOA_START); ++ /* if has trigger in process, just sleep. after noa end, trigger again */ ++ drv_priv->net_ops->wifi_mac_pwrsave_fullsleep(wnet_vif, SLEEP_AFTER_NOA_START); + break; + } + } @@ -54794,15 +55167,15 @@ index 000000000000..abeda5f1221a +drv_intr_p2p_noa_start (void *dpriv,unsigned char wnet_vif_id) +{ + struct drv_private *drv_priv = (struct drv_private *)dpriv; -+ struct wlan_net_vif *wnet_vif = NULL; ++ struct wlan_net_vif *wnet_vif; + + wnet_vif = drv_priv->drv_wnet_vif_table[wnet_vif_id]; + if (wnet_vif) + { +#ifdef CONFIG_P2P -+ if (drv_priv->net_ops->wifi_mac_pwrsave_is_wnet_vif_fullsleep(wnet_vif)==0) ++ if (drv_priv->net_ops->wifi_mac_pwrsave_is_wnet_vif_fullsleep(wnet_vif) == 0) + { -+ //drv_priv->net_ops->wifi_mac_pwrsave_networksleep(wnet_vif, NETSLEEP_AFTER_NOA); ++ /* drv_priv->net_ops->wifi_mac_pwrsave_networksleep(wnet_vif, NETSLEEP_AFTER_NOA); */ + } + p2p_noa_start_irq(wnet_vif->vm_p2p, drv_priv); +#endif @@ -54812,9 +55185,9 @@ index 000000000000..abeda5f1221a +static void drv_intr_fw_event(void *dpriv, void *event) +{ + struct drv_private *drv_priv = (struct drv_private *)dpriv; -+ struct wlan_net_vif *wnet_vif = NULL; ++ struct wlan_net_vif *wnet_vif; + struct fw_event_no_data *fw_event = (struct fw_event_no_data *)event; -+ struct wifi_mac *wifimac = NULL; ++ struct wifi_mac *wifimac; + + wnet_vif = drv_priv->drv_wnet_vif_table[fw_event->basic_info.vid]; + if (wnet_vif == NULL) { @@ -54822,7 +55195,7 @@ index 000000000000..abeda5f1221a + } + wifimac = wnet_vif->vm_wmac; + -+ //printk("%s, vid:%d, event:%d\n", __func__, fw_event->basic_info.vid, fw_event->basic_info.event); ++ //pr_debug("%s, vid:%d, event:%d\n", __func__, fw_event->basic_info.vid, fw_event->basic_info.event); + + switch (fw_event->basic_info.event) { + case DHCP_OFFLOAD_EVENT: @@ -54855,8 +55228,8 @@ index 000000000000..abeda5f1221a + { + struct tx_error_event *error_event = (struct tx_error_event *)fw_event; + -+ printk("%s:%d, frame type %x, error type %x \n", __func__, __LINE__, -+ error_event->frame_type, error_event->error_type); ++ pr_debug("%s:%d, frame type %x, error type %x \n", __func__, __LINE__, ++ error_event->frame_type, error_event->error_type); + +#if 0 + WIFINET_FW_STAT_LOCK(wifimac); @@ -54877,12 +55250,11 @@ index 000000000000..abeda5f1221a + case COEX_EVENT: + { + struct coex_info_event *coex_event = (struct coex_info_event *)fw_event; -+ AML_OUTPUT("coex state = %d\n",coex_event->coexist_state); ++ AML_OUTPUT("coex state = %d\n", coex_event->coexist_state); + + if (coex_event->coexist_state == TRUE_RSSI) { + wifimac->bt_lk = 1; + wifi_mac_set_channel_rssi(wifimac, (unsigned char)(wnet_vif->vm_mainsta->sta_avg_bcn_rssi)); -+ + } else if (coex_event->coexist_state == OPTIMIZE_RSSI) { + wifimac->bt_lk = 0; + wifi_mac_set_channel_rssi(wifimac, (unsigned char)(wnet_vif->vm_mainsta->sta_avg_bcn_rssi)); @@ -54891,77 +55263,66 @@ index 000000000000..abeda5f1221a + } + + case FWLOG_PRINT_EVENT: -+ drv_priv->hal_priv->hal_ops.hal_set_fwlog_cmd(3); //3: print fwlog ++ drv_priv->hal_priv->hal_ops.hal_set_fwlog_cmd(3); /* 3: print fwlog */ + break; + -+ + default: + break; + } +} + -+static void drv_intr_tx_null_data(void *dpriv, struct tx_nulldata_status * tx_null_status) ++static void drv_intr_tx_null_data(void *dpriv, struct tx_nulldata_status *tx_null_status) +{ + struct drv_private *drv_priv = (struct drv_private *)dpriv; -+ struct wlan_net_vif *wnet_vif = NULL; ++ struct wlan_net_vif *wnet_vif; + + wnet_vif = drv_priv->drv_wnet_vif_table[tx_null_status->wnet_vif_id]; + -+ //if send nulldata with ps=1 successfully, enter sleep -+ //else wakeup -+ //printk("%s pwr_flag:%d, status:%d\n", __func__, tx_null_status->pwr_flag, tx_null_status->txstatus); ++ /* if send nulldata with ps=1 successfully, enter sleep ++ * else wakeup ++ * pr_debug("%s pwr_flag:%d, status:%d\n", __func__, tx_null_status->pwr_flag, tx_null_status->txstatus); ++ */ + if (tx_null_status->pwr_flag == 0) + return; + + if ((tx_null_status->qos == 0) && (tx_null_status->ps == 1)) { + if (tx_null_status->txstatus== TX_DESCRIPTOR_STATUS_NULL_DATA_OK) { + if (!(wnet_vif->vm_wmac->wm_flags & WIFINET_F_SCAN)) { -+ drv_priv->net_ops->wifi_mac_pwrsave_fullsleep(wnet_vif, SLEEP_AFTER_TX_NULL_WITH_PS); ++ drv_priv->net_ops->wifi_mac_pwrsave_fullsleep(wnet_vif, ++ SLEEP_AFTER_TX_NULL_WITH_PS); + #ifdef USER_UAPSD_TRIGGER + os_timer_ex_start(&(wnet_vif->vm_pwrsave.ips_timer_uapsd_trigger)); + #endif + } + drv_priv->net_ops->wifi_mac_notify_ap_success(wnet_vif); -+ + } else if (tx_null_status->txstatus == TX_DESCRIPTOR_STATUS_NULL_DATA_FAIL) { + if (!(wnet_vif->vm_wmac->wm_flags & WIFINET_F_SCAN)) { -+ drv_priv->net_ops->wifi_mac_pwrsave_wkup_and_NtfyAp(wnet_vif, WKUP_FROM_PSNULL_FAIL); -+ ++ drv_priv->net_ops->wifi_mac_pwrsave_wkup_and_NtfyAp(wnet_vif, ++ WKUP_FROM_PSNULL_FAIL); + } + drv_priv->net_ops->wifi_mac_notify_ap_success(wnet_vif); + } + } +} + -+static void drv_intr_beacon_miss(void * dpriv, unsigned char wnet_vif_id) ++static void drv_intr_beacon_miss(void *dpriv, unsigned char wnet_vif_id) +{ + struct drv_private *drv_priv = (struct drv_private *)dpriv; ++ + drv_priv->net_ops->wifi_mac_beacon_miss(drv_priv->drv_wnet_vif_table[wnet_vif_id]); +} + -+ -+ -+static void drv_trigger_send_delba(SYS_TYPE param1, -+ SYS_TYPE param2,SYS_TYPE param3, SYS_TYPE param4,SYS_TYPE param5) ++static void drv_trigger_send_delba(SYS_TYPE param1, SYS_TYPE param2, ++ SYS_TYPE param3, SYS_TYPE param4, ++ SYS_TYPE param5) +{ + struct drv_private *drv_priv = drv_get_drv_priv(); + unsigned int vid = 0; -+ struct wlan_net_vif *wnet_vif = drv_priv->drv_wnet_vif_table[vid]; /*vmac 0*/ ++ struct wlan_net_vif *wnet_vif = drv_priv->drv_wnet_vif_table[vid]; /* vmac 0 */ + struct hw_interface* hif = hif_get_hw_interface(); -+ struct wifi_station* sta = NULL; -+ struct wifi_station* sta_next = NULL; -+ struct aml_driver_nsta *drv_sta = NULL; -+ unsigned int reg_val = 0; -+ struct wifi_mac_action_mgt_args actionargs; -+ //struct hal_private *hal_priv = hal_get_priv(); -+ struct wifi_mac* wifi_mac = wifi_mac_get_mac_handle(); -+ unsigned int tid_index = 0; -+ struct drv_rx_scoreboard *RxTidState = NULL; -+ struct wifi_station_tbl *vm_sta_tbl = &(wnet_vif->vm_sta_tbl); -+ unsigned int i = 0; -+ unsigned int j = 0; -+ -+ memset(&actionargs, 0, sizeof( struct wifi_mac_action_mgt_args)); ++ unsigned int reg_val; ++ struct wifi_mac* wifi_mac = wifi_mac_get_mac_handle(); ++ unsigned int j; + + reg_val = hif->hif_ops.hi_read_word(RG_COEX_BT_LOGIC_INFO); + if (reg_val & COEX_EN_ESCO) { @@ -54973,34 +55334,61 @@ index 000000000000..abeda5f1221a + wifi_mac->wm_esco_en = 0; + } + -+ /*two vid need consider*/ -+ for (j = 0; j < 2; ++j) { -+ vm_sta_tbl = &drv_priv->drv_wnet_vif_table[j]->vm_sta_tbl; ++ /* two vid need consider */ ++ for (j = 0; j < 2; ++j) { ++ struct wifi_station_tbl *vm_sta_tbl; ++ unsigned int i; ++ ++ vm_sta_tbl = &drv_priv->drv_wnet_vif_table[j]->vm_sta_tbl; ++ ++ /* traverse all hash value */ ++ for (i = 0; i < WIFINET_NODE_HASHSIZE; i++) { ++ struct wifi_station* sta = NULL; ++ struct wifi_station* sta_next = NULL; + -+ /*traverse all hash value*/ -+ for (i = 0; i < WIFINET_NODE_HASHSIZE; i++) { -+ /*traverse all staion in one hash value*/ ++ /* traverse all station in one hash value */ + WIFINET_NODE_LOCK(vm_sta_tbl); + list_for_each_entry_safe(sta, sta_next, &vm_sta_tbl->nt_nsta, sta_list) { ++ struct aml_driver_nsta *drv_sta; ++ unsigned int tid_index; ++ + drv_sta = DRIVER_NODE(sta->drv_sta); + -+ /*traverse all tid */ ++ /* traverse all tid */ + for (tid_index = 0; tid_index < WME_NUM_TID; tid_index++) { ++ struct drv_rx_scoreboard *RxTidState; ++ + RxTidState = &drv_sta->rx_scb[tid_index]; + + if (RxTidState->rx_addba_exchangecomplete) { ++ struct wifi_mac_action_mgt_args actionargs; ++ ++ memset(&actionargs, 0, sizeof(struct wifi_mac_action_mgt_args)); ++ + actionargs.category = AML_CATEGORY_BACK; + actionargs.action = WIFINET_ACTION_BA_DELBA; + actionargs.arg1 = tid_index; + /* -+ The Initiator subfield indicates if the originator or the recipient of the data is sending this frame. It is set to 1 -+ to indicate the originator and is set to 0 to indicate the recipient. The TID subfield indicates the TSID or the -+ UP for which the block ack has been originally set up. -+ */ -+ actionargs.arg2 = BA_INITIATOR; /*reference protocol 802.11-2016.pdf chapter 9.4.1.16 DELBA Parameter Set field*/ -+ actionargs.arg3 = 1; /* reference hornor v9 phone, reference protocol 802.11-2016.pdf chapter 9.4.1.9 Status Code field*/ ++ * The Initiator subfield indicates if the originator or the ++ * recipient of the data is sending this frame. It is set to 1 ++ * to indicate the originator and is set to 0 to indicate the ++ * recipient.The TID subfield indicates the TSID or the UP for ++ * which the block ack has been originally set up. ++ */ ++ ++ /* reference protocol 802.11-2016.pdf chapter 9.4.1.16 ++ * DELBA Parameter Set field ++ */ ++ actionargs.arg2 = BA_INITIATOR; ++ ++ ++ /* reference hornor v9 phone, reference protocol 802.11-2016.pdf ++ * chapter 9.4.1.9 Status Code field ++ */ ++ actionargs.arg3 = 1; + wifi_mac_send_action(sta, (void *)&actionargs); -+ printk("%s:%d, tid_index %d ->sta_macaddr=%s\n", __func__, __LINE__, tid_index, ether_sprintf(sta->sta_macaddr)); ++ pr_debug("%s:%d, tid_index %d ->sta_macaddr=%s\n", ++ __func__, __LINE__, tid_index, ether_sprintf(sta->sta_macaddr)); + } + } + } @@ -55009,47 +55397,48 @@ index 000000000000..abeda5f1221a + } +} + -+/*when BT logic link information change or BT alive status change -+WIFI need to change aggregate number -+and notify each other that our receiving window has become smaller -+*/ -+static void drv_intr_bt_info_change(void * dpriv, unsigned char wnet_vif_id,unsigned char bt_lk_change ) ++/* When BT logic link information change or BT alive status change ++ * WIFI need to change aggregate number and notify each other that ++ * our receiving window has become smaller. ++ */ ++static void drv_intr_bt_info_change(void *dpriv, unsigned char wnet_vif_id, unsigned char bt_lk_change) +{ + struct drv_private *drv_priv = (struct drv_private *)dpriv; -+ struct wlan_net_vif *wnet_vif = NULL; ++ struct wlan_net_vif *wnet_vif; + struct hw_interface* hif = hif_get_hw_interface(); -+ unsigned int reg_val = 0; -+ unsigned int reg_val2 = 0; -+ struct wifi_mac* p_wifi_mac = wifi_mac_get_mac_handle(); + + wnet_vif = drv_priv->drv_wnet_vif_table[wnet_vif_id]; -+ printk("%s:%d, vid %d \n", __func__, __LINE__, wnet_vif_id); ++ pr_debug("%s:%d, vid %d \n", __func__, __LINE__, wnet_vif_id); + -+ /*not open coexistence function*/ ++ /* Not open coexistence function. */ + if (drv_priv->drv_config.cfg_wifi_bt_coexist_support == 0) { + return; + } + -+ if ((wnet_vif->vm_opmode != WIFINET_M_STA) || ( drv_priv->drv_config.cfg_txaggr == 0)) { ++ if ((wnet_vif->vm_opmode != WIFINET_M_STA) || (drv_priv->drv_config.cfg_txaggr == 0)) { + return; + } + -+ if (bt_lk_change == 1) {/*BT link info change*/ ++ if (bt_lk_change == 1) { /* BT link info change */ + drv_trigger_send_delba(0, 0, 0, 0, 0); -+ + } else { ++ struct wifi_mac *p_wifi_mac = wifi_mac_get_mac_handle(); ++ unsigned int reg_val; ++ unsigned int reg_val2; ++ + reg_val = hif->hif_ops.hi_read_word(RG_BT_PMU_A16); + reg_val2 = hif->hif_ops.hi_read_word(RG_PMU_A16); -+ printk("drv_intr_bt_info_change reg addr=0x%x,value=0x%x reg addr=0x%x,value=0x%x ", RG_BT_PMU_A16, reg_val, RG_PMU_A16, reg_val2); ++ pr_debug("drv_intr_bt_info_change reg addr=0x%x,value=0x%x reg addr=0x%x,value=0x%x ", ++ RG_BT_PMU_A16, reg_val, RG_PMU_A16, reg_val2); ++ + if ((reg_val & BIT(31)) && (reg_val2 & BIT(31))) { /* coex is work */ + drv_priv->drv_config.cfg_ampdu_subframes = DEFAULT_TXAMPDU_SUB_MAX_COEX_ESCO; + p_wifi_mac->wm_bt_en = 1; -+ printk("coex change to work\n"); -+ ++ pr_debug("coex change to work\n"); + } else { /* coex is not work */ + drv_priv->drv_config.cfg_ampdu_subframes = DEFAULT_TXAMPDU_SUB_MAX; + p_wifi_mac->wm_bt_en = 0; -+ printk("coex change to not work\n"); ++ pr_debug("coex change to not work\n"); + } + } +} @@ -55057,17 +55446,17 @@ index 000000000000..abeda5f1221a +static int +drv_dev_probe(void) +{ -+ struct vm_wlan_net_vif_params vm_param; ++ struct vm_wlan_net_vif_params vm_param = { 0 }; + struct hal_private *hal_priv = hal_get_priv(); + struct drv_private *drv_priv = drv_get_drv_priv(); + struct wifi_mac *wm_mac = wifi_mac_get_mac_handle(); -+ int ret = 0; -+ int vif0opmode = -1; -+ int vif1opmode = -1; -+ char * vmac0 = NULL; -+ char * vmac1 = NULL; ++ int ret; ++ int vif0opmode; ++ int vif1opmode; ++ char *vmac0; ++ char *vmac1; + -+ /*2 init hal, download fw, host init */ ++ /* 2 init hal, download fw, host init. */ + if ((hal_priv->hal_ops.hal_probe != NULL) && (!hal_priv->hal_ops.hal_probe())) { + wifi_hal_probe_done = 0; + ERROR_DEBUG_OUT("init hal error\n"); @@ -55081,24 +55470,24 @@ index 000000000000..abeda5f1221a + wifi_mac_init_ops(wm_mac); + + aml_wifi_set_mac_addr(); -+ printk("%s(%d) mac_addr set done."MAC_FMT"", __func__,__LINE__, -+ mac_addr0,mac_addr1,mac_addr2, mac_addr3,mac_addr4,mac_addr5); ++ pr_debug("%s(%d) mac_addr set done."MAC_FMT"", __func__,__LINE__, ++ mac_addr0, mac_addr1, mac_addr2, mac_addr3, mac_addr4, mac_addr5); + -+ /*3 init driver */ ++ /* 3 init driver. */ + if(aml_driv_attach(drv_priv, wm_mac)) { + ERROR_DEBUG_OUT("init driver error\n"); + goto err_ret; + } + -+ /*4 init wifimac */ ++ /* 4 init wifimac. */ + if (wifi_mac_entry(wm_mac, drv_priv) != 0) { + ERROR_DEBUG_OUT( "init wifimac error\n"); + goto err_ret; + } + -+ /*5 create vmac 'wlan0' and 'p2p0' */ ++ /* 5 create vmac 'wlan0' and 'p2p0'. */ + vmac0 = aml_wifi_get_vif0_name(); -+ memcpy(&vm_param.vm_param_name, vmac0, IFNAMSIZ); ++ strscpy(vm_param.vm_param_name, vmac0, sizeof(vm_param.vm_param_name)); + + vif0opmode = aml_wifi_get_vif0_opmode(); + if ((vif0opmode >= WIFINET_M_IBSS) && (vif0opmode <= WIFINET_M_P2P_DEV)) { @@ -55106,10 +55495,10 @@ index 000000000000..abeda5f1221a + } else { + vm_param.vm_param_opmode = WIFINET_M_STA; + } -+ ret = drv_priv->net_ops->wifi_mac_create_vmac(wm_mac, &vm_param,0); ++ ret = drv_priv->net_ops->wifi_mac_create_vmac(wm_mac, &vm_param, 0); + + vmac1 = aml_wifi_get_vif1_name(); -+ memcpy(&vm_param.vm_param_name, vmac1, IFNAMSIZ); ++ strscpy(vm_param.vm_param_name, vmac1, sizeof(vm_param.vm_param_name)); + + vif1opmode = aml_wifi_get_vif1_opmode(); + if ((vif1opmode >= WIFINET_M_IBSS) && (vif1opmode <= WIFINET_M_P2P_DEV)) { @@ -55117,15 +55506,15 @@ index 000000000000..abeda5f1221a + } else { + vm_param.vm_param_opmode = WIFINET_M_P2P_DEV; + } -+ ret = drv_priv->net_ops->wifi_mac_create_vmac(wm_mac, &vm_param,0); ++ ret = drv_priv->net_ops->wifi_mac_create_vmac(wm_mac, &vm_param, 0); + -+ /*6 init station */ ++ /* 6 init station. */ + drv_priv->net_ops->wifi_mac_sta_attach(wm_mac); + ret = register_inetaddr_notifier(&aml_inetaddr_cb); + ret = register_inet6addr_notifier(&aml_inet6addr_cb); -+ //should not be here ++ /* should not be here. */ + drv_priv->drv_ops.drv_set_bmfm_info(drv_priv, 0, 0, 0, 0); -+ drv_hal_enable_coexist(drv_priv->drv_config.cfg_wifi_bt_coexist_support ); ++ drv_hal_enable_coexist(drv_priv->drv_config.cfg_wifi_bt_coexist_support); + + return ret; + @@ -55134,12 +55523,11 @@ index 000000000000..abeda5f1221a + return -ENODEV; +} + -+ +int drv_dev_remove(void) +{ + struct hal_private *hal_priv = hal_get_priv(); -+ struct drv_private* drv_priv = drv_get_drv_priv(); -+ struct wifi_mac* wm_mac = wifi_mac_get_mac_handle(); ++ struct drv_private *drv_priv = drv_get_drv_priv(); ++ struct wifi_mac *wm_mac = wifi_mac_get_mac_handle(); + + hal_priv->hi_task_stop = 1; + drv_priv->net_ops->wifi_mac_mac_exit(wm_mac); @@ -55185,10 +55573,10 @@ index 000000000000..abeda5f1221a +} diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_main.h b/drivers/net/wireless/w1/vmac/wifi_drv_main.h new file mode 100644 -index 000000000000..227dbda0a0e8 +index 0000000000000000000000000000000000000000..245fdd1408b465c27c496fe26a1785888130e61d --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_main.h -@@ -0,0 +1,616 @@ +@@ -0,0 +1,624 @@ +/* + **************************************************************************************** + * @@ -55241,6 +55629,8 @@ index 000000000000..227dbda0a0e8 +#define DRV_RXTID_UNLOCK(_rxtid) OS_SPIN_UNLOCK(&(_rxtid)->agg_tid_slock) +#define DRV_RXTID_LOCK_IRQ(_rxtid,flag) OS_SPIN_LOCK_IRQ(&(_rxtid)->agg_tid_slock,flag) +#define DRV_RXTID_UNLOCK_IRQ(_rxtid,flag) OS_SPIN_UNLOCK_IRQ(&(_rxtid)->agg_tid_slock,flag) ++#define DRV_RXTID_LOCK_BH(_rxtid) OS_SPIN_LOCK_BH(&(_rxtid)->agg_tid_slock) ++#define DRV_RXTID_UNLOCK_BH(_rxtid) OS_SPIN_UNLOCK_BH(&(_rxtid)->agg_tid_slock) + +#define DRV_TXQUEUE_VALUE(drv_priv, i) ((drv_priv)->drv_txqueue_map & (1<tid; + struct drv_rx_scoreboard *RxTidState = &drv_sta->rx_scb[tid_index]; + -+ DRV_RXTID_LOCK(RxTidState); ++ DRV_RXTID_LOCK_BH(RxTidState); + + if (!drv_priv->drv_config.cfg_rxaggr) + { @@ -56179,7 +56575,7 @@ index 000000000000..62e2b78d9694 + RxTidState->baparamset.amsdusupported = WIFINET_BA_AMSDU_SUPPORTED; + RxTidState->baparamset.tid = tid_index; + -+ DRV_RXTID_UNLOCK(RxTidState); ++ DRV_RXTID_UNLOCK_BH(RxTidState); + return 0; +} + @@ -56247,13 +56643,13 @@ index 000000000000..62e2b78d9694 + tid_index = (bar->i_ctl & WIFINET_BAR_CTL_TID_M) >> WIFINET_BAR_CTL_TID_S; + seqnum = le16toh(bar->i_seq) >> WIFINET_SEQ_SEQ_SHIFT; + RxTidState = &drv_sta->rx_scb[tid_index]; -+ DRV_RXTID_LOCK(RxTidState); ++ DRV_RXTID_LOCK_BH(RxTidState); + index = DRV_BA_INDEX(RxTidState->seq_next, seqnum); + + if ((index > RxTidState->baw_size) && + (index > (WIFINET_SEQ_MAX - (RxTidState->baw_size << 2)))) + { -+ DRV_RXTID_UNLOCK(RxTidState); ++ DRV_RXTID_UNLOCK_BH(RxTidState); + drv_priv->drv_stats.rx_bardrop_cnt++; + os_skb_free(skbbuf); + return WIFINET_FC0_TYPE_CTL; @@ -56288,7 +56684,7 @@ index 000000000000..62e2b78d9694 + CIRCLE_Add_One(RxTidState->baw_head, DRV_TID_MAX_BUFS); + CIRCLE_Add_One(RxTidState->seq_next, WIFINET_SEQ_MAX); + } -+ DRV_RXTID_UNLOCK(RxTidState); ++ DRV_RXTID_UNLOCK_BH(RxTidState); + os_skb_free(skbbuf); + return WIFINET_FC0_TYPE_CTL; +} @@ -56304,7 +56700,6 @@ index 000000000000..62e2b78d9694 + unsigned char type, subtype; + int b_mcast, tid, index, desc_id, rxdiff, is4addr; + unsigned short rxseq; -+ unsigned long lockflags; + struct aml_driver_nsta *drv_sta = (struct aml_driver_nsta *)nsta; + + wh = (struct wifi_frame *)os_skb_data(skbbuf); @@ -56349,10 +56744,10 @@ index 000000000000..62e2b78d9694 + } + RxTidState = &drv_sta->rx_scb[tid]; + -+ DRV_RXTID_LOCK_IRQ(RxTidState,lockflags); ++ DRV_RXTID_LOCK_BH(RxTidState); + if (!RxTidState->rx_addba_exchangecomplete) + { -+ DRV_RXTID_UNLOCK_IRQ(RxTidState,lockflags); ++ DRV_RXTID_UNLOCK_BH(RxTidState); + drv_priv->drv_stats.rx_nonqos_cnt++; + return drv_priv->net_ops->wifi_mac_input(drv_sta->net_nsta, skbbuf, rs); + } @@ -56368,7 +56763,7 @@ index 000000000000..62e2b78d9694 + + if (index > (WIFINET_SEQ_MAX - (RxTidState->baw_size << 2))) + { -+ DRV_RXTID_UNLOCK_IRQ(RxTidState,lockflags); ++ DRV_RXTID_UNLOCK_BH(RxTidState); + os_skb_free(skbbuf); + return WIFINET_FC0_TYPE_DATA; + } @@ -56397,7 +56792,7 @@ index 000000000000..62e2b78d9694 + + if (pRxDesc->rx_wbuf != NULL) + { -+ DRV_RXTID_UNLOCK_IRQ(RxTidState,lockflags); ++ DRV_RXTID_UNLOCK_BH(RxTidState); + drv_priv->drv_stats.rx_dup_cnt++; + + os_skb_free(skbbuf); @@ -56442,14 +56837,15 @@ index 000000000000..62e2b78d9694 + { + os_timer_ex_cancel(&RxTidState->timer, CANCEL_NO_SLEEP); + } -+ DRV_RXTID_UNLOCK_IRQ(RxTidState,lockflags); -+ ++ DRV_RXTID_UNLOCK_BH(RxTidState); + return WIFINET_FC0_TYPE_DATA; +} + -+static int drv_rx_sort_timer(void *context) ++static void drv_rx_sort_timer_ex(SYS_TYPE param1, SYS_TYPE param2, ++ SYS_TYPE param3, SYS_TYPE param4, ++ SYS_TYPE param5) +{ -+ struct drv_rx_scoreboard *RxTidState = (struct drv_rx_scoreboard *) context; ++ struct drv_rx_scoreboard *RxTidState = (struct drv_rx_scoreboard *) param1; + struct aml_driver_nsta *drv_sta = RxTidState->drv_sta; + struct drv_private *drv_priv = drv_sta->sta_drv_priv; + int nosched = OS_TIMER_NOT_REARMED; @@ -56457,9 +56853,8 @@ index 000000000000..62e2b78d9694 + int count = 0; + unsigned long diff; + int bawhead; -+ unsigned long lockflags; + -+ DRV_RXTID_LOCK_IRQ(RxTidState,lockflags); ++ DRV_RXTID_LOCK_BH(RxTidState); + bawhead = RxTidState->baw_head; + while (bawhead != RxTidState->baw_tail) + { @@ -56497,18 +56892,18 @@ index 000000000000..62e2b78d9694 + } + + if (RxTidState->baw_head != RxTidState->baw_tail) -+ { -+ nosched = OS_TIMER_REARMED; -+ } -+ else -+ { -+ nosched = OS_TIMER_NOT_REARMED; -+ } -+ DRV_RXTID_UNLOCK_IRQ(RxTidState,lockflags);; -+ -+ return nosched; ++ os_timer_ex_start(&RxTidState->timer); ++ DRV_RXTID_UNLOCK_BH(RxTidState); +} + ++static int drv_rx_sort_timer(void *context) ++{ ++ drv_hal_add_workitem((WorkHandler)drv_rx_sort_timer_ex, NULL, ++ (SYS_TYPE)context, (SYS_TYPE)0, (SYS_TYPE)0, ++ (SYS_TYPE)0,(SYS_TYPE)0); ++ ++ return OS_TIMER_NOT_REARMED; ++} + +static void +drv_rx_flush_tid(struct drv_private *drv_priv, struct drv_rx_scoreboard *RxTidState, int drop) @@ -56647,7 +57042,7 @@ index 000000000000..62e2b78d9694 +} diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_recv.h b/drivers/net/wireless/w1/vmac/wifi_drv_recv.h new file mode 100644 -index 000000000000..03e2e849ec7e +index 0000000000000000000000000000000000000000..03e2e849ec7eb0108126c6d7697bdee4e3e04b12 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_recv.h @@ -0,0 +1,24 @@ @@ -56677,7 +57072,7 @@ index 000000000000..03e2e849ec7e + diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_reg_ops.c b/drivers/net/wireless/w1/vmac/wifi_drv_reg_ops.c new file mode 100644 -index 000000000000..f5e3700a3b15 +index 0000000000000000000000000000000000000000..bafc3125538650cf2b20110de0d8239216c90e04 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_reg_ops.c @@ -0,0 +1,525 @@ @@ -56685,7 +57080,7 @@ index 000000000000..f5e3700a3b15 + +#define I2C_CLK_QTR 0x4 //old parameter 0x82 + -+void write_byte_8ba(unsigned char Bus, unsigned char SlaveAddr, ++static void write_byte_8ba(unsigned char Bus, unsigned char SlaveAddr, + unsigned char RegAddr, unsigned char Data) +{ + struct hw_interface* hif = hif_get_hw_interface(); @@ -56721,14 +57116,14 @@ index 000000000000..f5e3700a3b15 + + cnt++; + if (cnt == 1000) { -+ printk("-------[ERR]-----> i2c[W] err\n"); ++ pr_err("-------[ERR]-----> i2c[W] err\n"); + break; + } + } while (tmp & (1 << 2)); + +} + -+unsigned char read_byte_8ba(unsigned char Bus, unsigned char SlaveAddr, unsigned char RegAddr) ++static unsigned char read_byte_8ba(unsigned char Bus, unsigned char SlaveAddr, unsigned char RegAddr) +{ + struct hw_interface* hif = hif_get_hw_interface(); + unsigned int tmp,cnt = 0; @@ -56765,7 +57160,7 @@ index 000000000000..f5e3700a3b15 + + cnt++; + if (cnt == 1000) { -+ printk("-------[ERR]-----> i2c[W] err\n"); ++ pr_err("-------[ERR]-----> i2c[W] err\n"); + break; + } + } while (tmp & (1 << 2)); @@ -56776,13 +57171,13 @@ index 000000000000..f5e3700a3b15 + + +//void write_rdaddr_32ba(U8 Bus, U8 SlaveAddr, U32 TkData0, U32 TkData1) -+void write_word_32ba(unsigned char Bus, unsigned char SlaveAddr, ++static void write_word_32ba(unsigned char Bus, unsigned char SlaveAddr, + unsigned int StartToken, unsigned int Data) +{ + struct hw_interface* hif = hif_get_hw_interface(); + unsigned int tmp,cnt = 0; + -+ // printk("%s(%d) token 0x%x data 0x%x\n", __func__, __LINE__, StartToken,Data); ++ // pr_debug("%s(%d) token 0x%x data 0x%x\n", __func__, __LINE__, StartToken,Data); + + // Set the I2C bus to 100khz + tmp = hif->hif_ops.hi_read_word(I2C_CONTROL_REG); @@ -56825,7 +57220,7 @@ index 000000000000..f5e3700a3b15 + } while (tmp & (1 << 2)); +} + -+unsigned int read_word_32ba(unsigned int SlaveAddr, unsigned int RegAddr) ++static unsigned int read_word_32ba(unsigned int SlaveAddr, unsigned int RegAddr) +{ + struct hw_interface* hif = hif_get_hw_interface(); + unsigned int tmp,cnt = 0; @@ -56925,7 +57320,7 @@ index 000000000000..f5e3700a3b15 + } else if (((address >> 24) & 0xf0) == 0xf0 ) { +#ifdef USE_T902X_RF + rf_i2c_write( address & 0xffffffff,data );//access t902x rf reg -+ printk("%s(%d) 0x%x\n", __func__, __LINE__, data); ++ pr_debug("%s(%d) 0x%x\n", __func__, __LINE__, data); +#endif + } else { + HalPriv->hif->hif_ops.hi_write_word(address, data); @@ -56945,7 +57340,7 @@ index 000000000000..f5e3700a3b15 + } else if (((address >> 24) & 0xf0) == 0xf0 ) { +#ifdef USE_T902X_RF + *data = rf_i2c_read(address & 0xffffffff); //access t902x rf reg -+ printk("%s(%d) 0x%x\n", __func__, __LINE__, address); ++ pr_debug("%s(%d) 0x%x\n", __func__, __LINE__, address); +#endif + } else { + *data = HalPriv->hif->hif_ops.hi_read_word(address); @@ -57208,7 +57603,7 @@ index 000000000000..f5e3700a3b15 +} diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_reg_ops.h b/drivers/net/wireless/w1/vmac/wifi_drv_reg_ops.h new file mode 100644 -index 000000000000..b2b12665c2eb +index 0000000000000000000000000000000000000000..b2b12665c2eb040e9ddb24b575dee9251c8bad22 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_reg_ops.h @@ -0,0 +1,41 @@ @@ -57255,7 +57650,7 @@ index 000000000000..b2b12665c2eb +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_statistic.c b/drivers/net/wireless/w1/vmac/wifi_drv_statistic.c new file mode 100644 -index 000000000000..96c3323e7e28 +index 0000000000000000000000000000000000000000..e0c5449f25a4ff39b0bf5f8b13f0f3f6bc47155f --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_statistic.c @@ -0,0 +1,1259 @@ @@ -57333,10 +57728,10 @@ index 000000000000..96c3323e7e28 + + for (i = 0; i < sts_hst_sw_max_idx; i++) + { -+ //printk("idx[%d] -->val 0x%x \n", i, sts_sys_idx_val[i]); ++ //pr_debug("idx[%d] -->val 0x%x \n", i, sts_sys_idx_val[i]); + for (j = i+1; j < sts_hst_sw_max_idx; j++) + { -+ //printk("val1 0x%x, val2 0x%x \n", sts_sys_idx_val[i], sts_sys_idx_val[j]); ++ //pr_debug("val1 0x%x, val2 0x%x \n", sts_sys_idx_val[i], sts_sys_idx_val[j]); + if(idx_val[i] == idx_val[j]) + { + rpt = 1; @@ -57350,7 +57745,7 @@ index 000000000000..96c3323e7e28 + + if(rpt == 1) + { -+ printk("mapping err !the repeat val is 0x%x, i %d, j %d\n", idx_val[i], i, j); ++ pr_err("mapping err !the repeat val is 0x%x, i %d, j %d\n", idx_val[i], i, j); + break; + } + } @@ -57706,7 +58101,7 @@ index 000000000000..96c3323e7e28 + break; + + default: -+ printk("%s,%d, statistic address 0x%x not supported\n", __func__, __LINE__, addr); ++ pr_err("%s,%d, statistic address 0x%x not supported\n", __func__, __LINE__, addr); + break; + + } @@ -57732,7 +58127,7 @@ index 000000000000..96c3323e7e28 + if(idx_val[i] == val) + { + ret = i; -+ //printk("idx_val[%d] is 0x%x, val is 0x%x\n", i, idx_val[i], val); ++ //pr_debug("idx_val[%d] is 0x%x, val is 0x%x\n", i, idx_val[i], val); + break; + } + else @@ -57743,7 +58138,7 @@ index 000000000000..96c3323e7e28 + + if(i == sts_hst_sw_max_idx) + { -+ printk("%s,%d: no find the item in statistic system: val = 0x%x max i = %d \n", __func__, __LINE__, val, i); ++ pr_err("%s,%d: no find the item in statistic system: val = 0x%x max i = %d \n", __func__, __LINE__, val, i); + } + return ret; +} @@ -57798,13 +58193,13 @@ index 000000000000..96c3323e7e28 + + for(i = 0 ; i < sizeof(sts_man) / sizeof(char*) ; i++) + { -+ printk("%s\n",sts_man[i]); ++ pr_debug("%s\n",sts_man[i]); + } + -+ printk("-----------the default configuration is-----------\n"); ++ pr_debug("-----------the default configuration is-----------\n"); + for(i = 0; iaddr[i], + cfg_data->cfg_ie[i].x&0xff, (cfg_data->cfg_ie[i].x>>8)&0xff,(cfg_data->cfg_ie[i].x>>16)&0xff,(cfg_data->cfg_ie[i].x>>24)&0xff + ); @@ -57832,19 +58227,19 @@ index 000000000000..96c3323e7e28 + ASSERT(cfg_data) + ASSERT(len != 0); + -+ printk("input: \n"); ++ pr_debug("input: \n"); + for (i = 0; i< len; i++) + { -+ printk ("0x%x ",*(data+i)); ++ pr_debug ("0x%x ",*(data+i)); + } -+ printk(" \n"); ++ pr_debug(" \n"); + + iw_cfg_if = (struct sts_iw_if*)data; + + iw_cfg_if->addr = ntohs(iw_cfg_if->addr); + iw_cfg_if->val = ntohl(iw_cfg_if->val); + -+ printk("addr: 0x%4x val: 0x%x \n", iw_cfg_if->addr, iw_cfg_if->val); ++ pr_debug("addr: 0x%4x val: 0x%x \n", iw_cfg_if->addr, iw_cfg_if->val); + + /*avoid the error address to result in system crash*/ + for(i = 0; i < sizeof(sts_reg_chk_pool)/sizeof(sts_reg_chk_pool[0]); i++) @@ -57861,14 +58256,14 @@ index 000000000000..96c3323e7e28 + + if(i == sizeof(sts_reg_chk_pool)/sizeof(sts_reg_chk_pool[0])) + { -+ printk("%s,%d: the statistic address 0x%x error, check it please...\n", __func__, __LINE__, iw_cfg_if->addr); ++ pr_debug("%s,%d: the statistic address 0x%x error, check it please...\n", __func__, __LINE__, iw_cfg_if->addr); + return; + } + -+ printk("-----------the previous configuration is-----------\n"); ++ pr_debug("-----------the previous configuration is-----------\n"); + for(i = 0; iaddr[i], + cfg_data->cfg_ie[i].x&0xff,(cfg_data->cfg_ie[i].x>>8)&0xff,(cfg_data->cfg_ie[i].x>>16)&0xff,(cfg_data->cfg_ie[i].x>>24)&0xff + ); @@ -57894,10 +58289,10 @@ index 000000000000..96c3323e7e28 + cfg_data->cfg_num++; + } + -+ printk("-----------the current configuration is-----------\n"); ++ pr_debug("-----------the current configuration is-----------\n"); + for(i = 0; iaddr[i], + cfg_data->cfg_ie[i].x&0xff, + (cfg_data->cfg_ie[i].x>>8)&0xff, @@ -57994,7 +58389,7 @@ index 000000000000..96c3323e7e28 + break; + + default: -+ printk("%s,%d, statistic address 0x%x not supported\n", __func__, __LINE__, addr); ++ pr_err("%s,%d, statistic address 0x%x not supported\n", __func__, __LINE__, addr); + break; + } + @@ -58081,7 +58476,7 @@ index 000000000000..96c3323e7e28 + break; + + default: -+ printk("%s,%d: statistic address 0x%x not supported\n", __func__, __LINE__,addr); ++ pr_err("%s,%d: statistic address 0x%x not supported\n", __func__, __LINE__,addr); + break; + } + @@ -58189,10 +58584,10 @@ index 000000000000..96c3323e7e28 + prt_idx2 = val_to_idx(sts_sys_idx_val,addr << 16 | sts_cca_cnd23_cond3_idx); + break; + default: -+ printk("%s,%d agc addr 0x%x err:\n", __func__, __LINE__, addr); ++ pr_err("%s,%d agc addr 0x%x err:\n", __func__, __LINE__, addr); + return; + } -+ printk("[%s]: %s=%d, %s=%d\n", ++ pr_debug("[%s]: %s=%d, %s=%d\n", + func_code==SYS_STS_STOP ? sts_tag[SYS_STS_STOP]:sts_tag[SYS_STS_READ], + sts_info[prt_idx1], agc_rd1,sts_info[prt_idx2], agc_rd2); + @@ -58214,7 +58609,7 @@ index 000000000000..96c3323e7e28 + + if(sts_info[prt_idx] != NULL) + { -+ printk("[%s]: %s=%d \n", ++ pr_debug("[%s]: %s=%d \n", + func_code==SYS_STS_STOP ? sts_tag[SYS_STS_STOP]: sts_tag[SYS_STS_READ], + sts_info[prt_idx] ,hal_priv->sts_hst_sw[i].cnt); + } @@ -58277,7 +58672,7 @@ index 000000000000..96c3323e7e28 + sts_read_reg_array(&rd_data0,&rd_data1,&rd_data2,&rd_data3, + RG_MAC_IRQ_STATUS_CNT0,RG_MAC_IRQ_STATUS_CNT1,RG_MAC_IRQ_STATUS_CNT2,RG_MAC_IRQ_STATUS_CNT3); + -+ printk("[%s]: %s=%8d,%s=%8d,%s=%8d,%s=%8d\n", ++ pr_debug("[%s]: %s=%8d,%s=%8d,%s=%8d,%s=%8d\n", + func_code==SYS_STS_STOP ? sts_tag[SYS_STS_STOP]:sts_tag[SYS_STS_READ], + sts_info[prt_idx0],rd_data0, + sts_info[prt_idx1],rd_data1, @@ -58297,7 +58692,7 @@ index 000000000000..96c3323e7e28 + sts_read_reg_array(&rd_data0,&rd_data1,&rd_data2,&rd_data3, + RG_MAC_FRM_TYPE_CNT0,RG_MAC_FRM_TYPE_CNT1,RG_MAC_FRM_TYPE_CNT2,RG_MAC_FRM_TYPE_CNT3); + -+ printk("[%s]: %s=%8d,%s=%8d,%s=%8d,%s=%8d\n", ++ pr_debug("[%s]: %s=%8d,%s=%8d,%s=%8d,%s=%8d\n", + func_code==SYS_STS_STOP ? sts_tag[SYS_STS_STOP]:sts_tag[SYS_STS_READ], + sts_info[prt_idx0],rd_data0, + sts_info[prt_idx1],rd_data1, @@ -58316,7 +58711,7 @@ index 000000000000..96c3323e7e28 + + rd_data0 = hif->hif_ops.hi_read_word(addr); + -+ printk("[%s]: %s=%8d\n", ++ pr_debug("[%s]: %s=%8d\n", + func_code==SYS_STS_STOP ? sts_tag[SYS_STS_STOP]:sts_tag[SYS_STS_READ], + sts_info[prt_idx0 ],(rd_data0 << 6 ) >> 6); + break; @@ -58335,12 +58730,12 @@ index 000000000000..96c3323e7e28 + rd_show = (rd_data0 << 2 ) >> 2; + } + -+ printk("[%s]: %s=%8d\n", ++ pr_debug("[%s]: %s=%8d\n", + func_code==SYS_STS_STOP ? sts_tag[SYS_STS_STOP]:sts_tag[SYS_STS_READ], + sts_info[prt_idx0],rd_show); + break; + default: -+ printk("%s,%d, statistic address 0x%x not supported\n", __func__, __LINE__, addr); ++ pr_err("%s,%d, statistic address 0x%x not supported\n", __func__, __LINE__, addr); + break; + } + @@ -58421,7 +58816,7 @@ index 000000000000..96c3323e7e28 + break; + + default: -+ printk("%s,%d: statistic address 0x%x not supported\n", __func__, __LINE__, addr); ++ pr_err("%s,%d: statistic address 0x%x not supported\n", __func__, __LINE__, addr); + break; + + } @@ -58441,10 +58836,10 @@ index 000000000000..96c3323e7e28 +void sts_show_cfg( struct sts_cfg_data* cfg_data) +{ + int i = 0; -+ printk("-----------the current configuration is-----------\n"); ++ pr_debug("-----------the current configuration is-----------\n"); + for(i = 0; icfg_num; i++) + { -+ printk("addr 0x%4x: data_a 0x%x data_b 0x%x data_c 0x%x data_d 0x%x\n", ++ pr_debug("addr 0x%4x: data_a 0x%x data_b 0x%x data_c 0x%x data_d 0x%x\n", + cfg_data->addr[i], + cfg_data->cfg_ie[i].x&0xff,(cfg_data->cfg_ie[i].x>>8)&0xff,(cfg_data->cfg_ie[i].x>>16)&0xff,(cfg_data->cfg_ie[i].x>>24)&0xff + ); @@ -58462,7 +58857,7 @@ index 000000000000..96c3323e7e28 + unsigned int i = 0; + char **tag ; + char **info; -+ printk("%s\n--------function code is 0x%x--------\n", func_prt_info[func_code], func_code); ++ pr_debug("%s\n--------function code is 0x%x--------\n", func_prt_info[func_code], func_code); + + if(func_code == SYS_STS_SHOW_CFG ) + { @@ -58501,7 +58896,7 @@ index 000000000000..96c3323e7e28 + } + else + { -+ printk("%s, %d: ptr err: tag %p info %p\n", __func__, __LINE__, tag, info); ++ pr_err("%s, %d: ptr err: tag %p info %p\n", __func__, __LINE__, tag, info); + } + break; + default : @@ -58520,379 +58915,379 @@ index 000000000000..96c3323e7e28 + diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_statistic.h b/drivers/net/wireless/w1/vmac/wifi_drv_statistic.h new file mode 100644 -index 000000000000..9d4228ac5bf0 +index 0000000000000000000000000000000000000000..d306fffb868f14753da35c4b296ac172b54309d8 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_statistic.h @@ -0,0 +1,366 @@ -+#ifndef __DRV_STATISTIC_H -+#define __DRV_STATISTIC_H -+ -+/////////////////////////////// global statistic defination//////////////////////// -+ -+#define SYS_STS_CLEAR (0) -+#define SYS_STS_START (1) -+#define SYS_STS_READ (2) -+#define SYS_STS_STOP (3) -+#define SYS_STS_SHOW_CFG (4) -+ -+#define IDX_TXSTART_IT (0) -+#define IDX_TXEND_IT (1) -+#define IDX_TXENDERR (8) -+#define IDX_ACKTO_IT (9) -+#define IDX_TXCOL_FLAG (10) -+#define IDX_RXSTART_IT (11) -+#define IDX_RXEND_IT (12) -+#define IDX_RXMPDU_OK (13) -+#define IDX_UNICAST (14) -+#define IDX_SRAMBUF_FULL (18) -+#define IDX_SWIRQ (19) -+#define IDX_TX_FRAME_TYPE (20) -+#define IDX_ABSCOUNT_INTR (30) -+#define IDX_FIQ_ENABLE (31) -+ -+#define IDX_FIAC_FW_TIMEOUT_ERR (32+0) -+#define IDX_HW_TIMEOUT_ERR (32+1) -+#define IDX_TX_WD_TIMEOUT_ERR (32+2) -+#define IDX_TXINVALIDLEN_ERR (32+3) -+#define IDX_TX_KEYMISS (32+4) -+#define IDX_TXIMSTOP_ERR (32+5) -+#define IDX_TX_PHYERROR (32+6) -+#define IDX_TXCOL_QUEUE (32+10) -+#define IDX_TX_NOT_GRANT (32+19) -+#define IDX_SRAMBUF_FULL_ERR (32+22) -+#define IDX_FCSERR (32+23) -+#define IDX_RXFIFOOV (32+24) -+#define IDX_RX_WD_TIMEOUT_ERR (32+25) -+#define IDX_SHORT_LENGTH (32+26) -+#define IDX_LENGTH_ERROR (32+27) -+#define IDX_RX_PHYERROR (32+28) -+ -+#define IDX_QOS_DATA (0x28) -+#define IDX_RTS (0x1b) -+#define IDX_CTS (0x1c) -+#define IDX_ACK (0x1d) -+ -+ -+#define STS_MAX_CFG_FILE (0x40) -+#define SYS_STS_PRT_TAG (0x1) -+#define SYS_STS_PRT_INFO (0x0) -+ -+#define IS_MAC_STS(addr) (((addr) == RG_MAC_CNT_CTRL_FIQ) ||\ -+ ((addr) == RG_MAC_FRM_TYPE_CNT_CTRL) ||\ -+ ((addr) == RG_MAC_TX_STT_CHK) || \ -+ ((addr) == RG_MAC_TX_END_CHK) ||\ -+ ((addr) == RG_MAC_TX_EN_CHK) ||\ -+ ((addr) == RG_MAC_TX_ENWR_CHK) ||\ -+ ((addr) == RG_MAC_RX_DATA_LOCAL_CNT) ||\ -+ ((addr) == RG_MAC_RX_DATA_OTHER_CNT) ||\ -+ ((addr) == RG_MAC_RX_DATA_MUTIL_CNT) ) -+ -+ -+#define IS_AGC_STS(addr) ((addr ) == RG_AGC_STATE||\ -+ (addr ) == RG_AGC_OB_IC_GAIN||\ -+ (addr ) == RG_AGC_WATCH1||\ -+ (addr ) == RG_AGC_WATCH2||\ -+ (addr ) == RG_AGC_WATCH3||\ -+ (addr ) == RG_AGC_WATCH4||\ -+ (addr ) == RG_AGC_OB_ANT_NFLOOR||\ -+ (addr ) == RG_AGC_OB_CCA_RES||\ -+ (addr ) == RG_AGC_OB_CCA_COND01||\ -+ (addr ) == RG_AGC_OB_CCA_COND23) -+ -+#define IS_HOST_SW_STS(addr) ((addr & MOD_VADDR) == MOD_VADDR) -+ -+ -+enum sts_sys_idx{ -+ sts_mac_irq_txstart_idx, -+ sts_mac_irq_txend_idx, -+ sts_mac_irq_txenderr_idx, -+ sts_mac_irq_ackto_idx, -+ sts_mac_irq_txcol_flag_idx, -+ sts_mac_irq_rxstart_idx, -+ sts_mac_irq_mac_rxend_idx, -+ sts_mac_irq_mac_rxmpdu_ok_idx, -+ sts_mac_irq_unicast_idx, -+ sts_mac_irq_srambuf_full_idx, -+ sts_mac_irq_swirq_idx, -+ sts_mac_irq_tx_frame_type_idx, -+ sts_mac_irq_abscount_intr_idx, -+ sts_mac_irq_fiq_enable_idx, -+ sts_mac_irq_fiac_fw_timeout_err_idx, -+ sts_mac_irq_hw_timeout_err_idx, -+ sts_mac_irq_tx_wd_timeout_err_idx, -+ sts_mac_irq_txinvalidlen_err_idx, -+ sts_mac_irq_tx_keymiss_idx, -+ sts_mac_irq_tximstop_err_idx, -+ sts_mac_irq_tx_phyerror_idx, -+ sts_mac_irq_txcol_queue_idx, -+ sts_mac_irq_tx_not_grant_idx, -+ sts_mac_irq_srambuf_full_err_idx, -+ sts_mac_irq_fcserr_idx, -+ sts_mac_irq_rxfifoov_idx, -+ sts_mac_irq_rx_wd_timeout_err_idx, -+ sts_mac_irq_short_length_idx, -+ sts_mac_irq_length_error_idx, -+ sts_mac_irq_rx_phyerror_idx, -+ sts_frm_type_qos_data_idx, -+ sts_frm_type_rts_idx, -+ sts_frm_type_cts_idx, -+ sts_frm_type_ack_idx, -+ sts_mac_tx_start_chk_idx, -+ sts_mac_tx_end_chk_idx, -+ sts_mac_tx_en_chk_idx, -+ sts_mac_tx_enwr_chk_idx, -+ sts_mac_rx_data_local_cnt_idx, -+ sts_mac_rx_data_other_cnt_idx, -+ sts_mac_rx_data_mutil_cnt_idx, -+ sts_agc_st_idx, -+ sts_agc_gain_rx_ic_gain_idx, -+ sts_agc_gain_fine_db_idx, -+ sts_agc_wtc1_pw_sat_db_idx, -+ sts_agc_wtc1_prm20_db_idx, -+ sts_agc_wtc2_prm40_db_idx, -+ sts_agc_wtc2_prm80_db_idx, -+ sts_agc_wtc3_rssi0_db_idx, -+ sts_agc_wtc3_rssi1_db_idx, -+ sts_agc_wtc4_rssi2_db_idx, -+ sts_agc_wtc4_rssi3_db_idx, -+ sts_agc_ant_flr_snr_qdb_idx, -+ sts_agc_ant_flr_ant_flr_qdb_idx, -+ sts_cca_res_rdy_idx, -+ sts_cca_res_cond8_idx, -+ sts_cca_cnd01_cond0_idx, -+ sts_cca_cnd01_cond1_idx, -+ sts_cca_cnd23_cond2_idx, -+ sts_cca_cnd23_cond3_idx, -+ -+ sts_hst_irq_tx_error_idx, -+ sts_hst_irq_rx_error_idx, -+ sts_hst_irq_rx_ok_idx, -+ sts_hst_irq_tx_ok_idx, -+ sts_hst_irq_beacon_send_ok_vid0_idx , -+ sts_hst_irq_beacon_send_ok_vid1_idx , -+ sts_hst_irq_goto_wakeup_vid0_idx , -+ sts_hst_irq_goto_wakeup_vid1_idx , -+ sts_hst_irq_p2p_oppps_cwend_vid0_idx, -+ sts_hst_irq_p2p_oppps_cwend_vid1_idx, -+ sts_hst_irq_p2p_noa_start_vid0_idx , -+ sts_hst_irq_p2p_noa_start_vid1_idx , -+ sts_hst_irq_beacon_recv_ok_vid0_idx , -+ sts_hst_irq_beacon_recv_ok_vid1_idx , -+ sts_hst_irq_beacon_miss_vid0_idx , -+ sts_hst_irq_beacon_miss_vid1_idx , -+ -+ sts_hal_agg_start_tid0_idx, -+ sts_hal_agg_start_tid1_idx, -+ sts_hal_agg_start_tid2_idx, -+ sts_hal_agg_start_tid3_idx, -+ sts_hal_agg_start_tid4_idx, -+ sts_hal_agg_start_tid5_idx, -+ sts_hal_agg_start_tid6_idx, -+ sts_hal_agg_start_tid7_idx, -+ sts_hal_agg_start_tid8_idx, -+ sts_hal_agg_start_tid9_idx, -+ sts_hal_rx_fifo_full_idx, -+ sts_hal_rx_up_skb_idx, -+ sts_hal_rx_vif_id_err_idx, -+ sts_hal_rx_dcrypt_err_idx, -+ sts_hal_tx_num_idx, -+ sts_hal_tx_mpdus_idx, -+ sts_hal_tx_pages_idx, -+ sts_hal_dw_mpdu_idx, -+ sts_hal_cur_mpdu_idx, -+ sts_hal_cur_agg_page_idx, -+ sts_hal_allc_txds_idx, -+ sts_hal_free_txds_idx, -+ sts_hal_send_null_idx, -+ sts_hal_keep_alive_idx, -+ sts_hal_beacon_miss_idx, -+ sts_drv_tx_total_bytes_idx, -+ sts_drv_tx_pkts_idx, -+ sts_drv_tx_drops_idx, -+ sts_drv_tx_normal_idx, -+ sts_drv_tx_end_normal_idx, -+ sts_drv_tx_end_ampdu_idx, -+ sts_drv_tx_ampdu_idx, -+ sts_drv_tx_ampdu_on_frm_idx, -+ sts_drv_tx_end_fail_idx, -+ sts_drv_rx_ampdu_idx, -+ sts_drv_rx_bar_idx, -+ sts_drv_rx_no_qos_idx, -+ sts_drv_rx_dup_idx, -+ sts_drv_rx_ok_idx, -+ sts_drv_rx_flush_drop_idx, -+ sts_drv_rx_bar_drop_idx, -+ sts_drv_rx_skipped_idx, -+ sts_drv_txlist0_qcnt_idx, -+ sts_drv_txlist1_qcnt_idx, -+ sts_drv_txlist2_qcnt_idx, -+ sts_drv_txlist3_qcnt_idx, -+ sts_drv_txlist4_qcnt_idx, -+ sts_drv_txlist5_qcnt_idx, -+ sts_drv_txlist6_qcnt_idx, -+ sts_drv_txlist_qcnt_idx7, -+ sts_drv_txlist0_pend_qcnt_idx, -+ sts_drv_txlist1_pend_qcnt_idx, -+ sts_drv_txlist2_pend_qcnt_idx, -+ sts_drv_txlist3_pend_qcnt_idx, -+ sts_drv_txlist4_pend_qcnt_idx, -+ sts_drv_txlist5_pend_qcnt_idx, -+ sts_drv_txlist6_pend_qcnt_idx, -+ sts_drv_txlist7_pend_qcnt_idx, -+ sts_drv_send_skb_idx, -+ sts_vif_ip_pkt_total_idx, -+ sts_vif_ip_pkt_to_drv_idx, -+ sts_vif_ip_pkt_drop_idx, -+ sts_vif_tx_list_full_idx, -+ sts_vif_tx_ok_idx, -+ sts_vif_tx_cmp_idx, -+ sts_vif_tx_free_page_idx, -+ sts_vif_in_amsdu_idx, -+ sts_vif_out_amsdu_idx, -+ -+ -+ -+ -+ sts_hst_sw_max_idx, -+}; -+ -+/* -+ iw dev wlan0 vendor send 0xc3 0xc4 op_code func_code hw_addr obj_0, obj_1, obj_2,obj_3 -+*/ -+#pragma pack(push ,1) -+struct sts_cfg_data{ -+ unsigned short addr[STS_MAX_CFG_FILE]; -+ union sts_mac_reg_u cfg_ie[STS_MAX_CFG_FILE]; -+ unsigned char cfg_num; -+}; -+ -+struct statistic_cmd -+{ -+ unsigned char op_code; // 0x99 -+ -+ unsigned char iaddr_high; // hardware reg high part, -+ unsigned char iaddr_low; // hardware reg low part -+ unsigned char iobj_0; // obj_0 to work -+ unsigned char iobj_1; // obj_1 to work -+ unsigned char iobj_2; // obj_2 to work -+ unsigned char iobj_3; // obj_3 to work -+ -+ unsigned char faddr_high; // hardware reg high part, -+ unsigned char faddr_low; // hardware reg low part -+ unsigned char fobj_0; // obj_0 to work -+ unsigned char fobj_1; // obj_1 to work -+ unsigned char fobj_2; // obj_2 to work -+ unsigned char fobj_3; // obj_3 to work -+ -+ unsigned char func_code; //(0x0, stop); (0x1, start) ;(0x2, read) -+ -+}; -+ -+ -+struct sts_iw_if -+ { -+ unsigned char op_code; -+ unsigned short addr; -+ unsigned int val; -+ }; -+ -+#pragma pack(pop) -+ -+void sts_sw_probe(unsigned int sts_idx, unsigned int unit) ; -+void phy_stc(void); -+int get_snr(void); -+void get_phy_stc_info(unsigned int *arr); -+ -+unsigned int cca_busy_check(void); -+void sts_prt_info_map(void); -+void sts_default_cfg(struct sts_cfg_data* cfg_data, unsigned char sts_sys_type); -+void sts_update_cfg(struct sts_cfg_data* cfg_data, const char* data,unsigned int len); -+char** get_tag_info(unsigned short addr,unsigned int tag_info); -+void sts_clr_cnt(unsigned short addr); -+void sts_start_cnt(unsigned short addr, -+ char obj_0,char obj_1,char obj_2,char obj_3); -+ -+void sts_read_cnt(unsigned short addr, -+ unsigned char obj_0,unsigned char obj_1,unsigned char obj_2, unsigned char obj_3, -+ char* sts_tag[], char* sts_info[], unsigned int* idx_val, char func_code); -+ -+void sts_stop_cnt(unsigned short addr); -+void sts_show_cfg( struct sts_cfg_data* cfg_data); -+void sts_opt_by_cfg(struct sts_cfg_data* cfg_data, unsigned char func_code); -+void sts_prt_agc_field(unsigned short addr, -+ char* sts_tag[], char* sts_info[], char func_code); -+ -+unsigned int val_to_idx(unsigned int idx_val[], unsigned int val); -+ -+/////////////////////////////// layer statistic defination//////////////////////// -+/* -+ iw dev wlan0 vendor send 0xc3 0xc4 op_code(B) ctrl_msg3, ctrl_msg2, ctrl_msg1, ctrl_msg0 -+ bit31~bit28: sts module: bit31 wifi_mac layer; bit30 driver layer; bit29 hal layer; bit28 hw interface -+ bit27~bit24: sts type: bit27 tx; bit26 rx; bit25 allocate resource; bit24 free resource -+ bit23~bit0: the detail message by sts type and sts module -+*/ -+ -+#define STS_MOD_WMAC BIT(31) -+#define STS_MOD_DRV BIT(30) -+#define STS_MOD_HAL BIT(29) -+#define STS_MOD_HIF BIT(28) -+ -+#define STS_TYP_TX (BIT(27)) -+#define STS_TYP_RX (BIT(26)) -+ -+// RF capture -+ -+#define INBUFFER_LEN_VALID_BIT (256-2) -+#define INBUFFER_LEN (256/8) -+#define ADC_WIDTH 24 -+#define BLOCK_RAW_LEN INBUFFER_LEN -+#define BLOCK_REAL_LEN (INBUFFER_LEN_VALID_BIT/ADC_WIDTH*4) -+#define BLOCK_REAL_COUNT_WORD (BLOCK_REAL_LEN/4) -+ -+#define TESTBUSSRAM_LEN 0x200000 -+#define INBUFFER_LEN (256/8) -+#define INBUFFER_LEN_VALID_BIT (256-2) -+#define INBUFFER_LEN_VALID ((INBUFFER_LEN_VALID_BIT)/8) -+#define TESTBUFFER_LEN (256-8) -+ -+#define SELFTEST 1 //LG -+#define DA 0 //LG -+ -+#define SW 9 -+#define FCS_OK 6 -+#define FCS_ERR 3 -+#define FCS_ERR_OFDM 5 -+#define FCS_ERR_DSS 4 -+#define LSIG_PARITY_ERR 8 -+#define HTSIG_CRC_ERR 7 -+#define CCA_FSM_TRIG 2 -+#define AGC_FSM_TRIG 0 -+#define CCA_AGC_FSM_TRIG 1 -+ -+ -+#define SDIO_BASE_A 0x00a0b000 -+#define CAP_SRAM_SWITCH_BASE 0x00a0d000 -+ -+#define TBC_OFFSET_100 (0x100 + SDIO_BASE_A) //0x2d00 -+#define TBC_OFFSET_104 (0x104 + SDIO_BASE_A) //0x2d04 -+#define TBC_OFFSET_108 (0x108 + SDIO_BASE_A) //0x2d08 -+#define TBC_OFFSET_10C (0x10c + SDIO_BASE_A) //0x2d0C -+#define TBC_OFFSET_110 (0x110 + SDIO_BASE_A) //0x2d10 -+#define TBC_OFFSET_114 (0x114 + SDIO_BASE_A) //0x2d14 -+#define TBC_OFFSET_118 (0x118 + SDIO_BASE_A) //0x2d18 -+#define TBC_OFFSET_11C (0x11C + SDIO_BASE_A) //0x2d1C -+#define TBC_OFFSET_120 (0x120 + SDIO_BASE_A) //0x2d20 -+#define TBC_OFFSET_124 (0x124 + SDIO_BASE_A) //0x2d24 -+#define TBC_OFFSET_128 (0x128 + SDIO_BASE_A) //0x2d28 -+ -+#define TBC_RAM_SHARE (0xe4 + CAP_SRAM_SWITCH_BASE)//INTF SRAM SHARE ENABLE BIT31: 1-> CAPTURE BUF -+ -+void batch_dump_reg(struct wiphy *wiphy,unsigned int addr[], unsigned int addr_num); -+ -+#endif ++#ifndef __DRV_STATISTIC_H ++#define __DRV_STATISTIC_H ++ ++/////////////////////////////// global statistic defination//////////////////////// ++ ++#define SYS_STS_CLEAR (0) ++#define SYS_STS_START (1) ++#define SYS_STS_READ (2) ++#define SYS_STS_STOP (3) ++#define SYS_STS_SHOW_CFG (4) ++ ++#define IDX_TXSTART_IT (0) ++#define IDX_TXEND_IT (1) ++#define IDX_TXENDERR (8) ++#define IDX_ACKTO_IT (9) ++#define IDX_TXCOL_FLAG (10) ++#define IDX_RXSTART_IT (11) ++#define IDX_RXEND_IT (12) ++#define IDX_RXMPDU_OK (13) ++#define IDX_UNICAST (14) ++#define IDX_SRAMBUF_FULL (18) ++#define IDX_SWIRQ (19) ++#define IDX_TX_FRAME_TYPE (20) ++#define IDX_ABSCOUNT_INTR (30) ++#define IDX_FIQ_ENABLE (31) ++ ++#define IDX_FIAC_FW_TIMEOUT_ERR (32+0) ++#define IDX_HW_TIMEOUT_ERR (32+1) ++#define IDX_TX_WD_TIMEOUT_ERR (32+2) ++#define IDX_TXINVALIDLEN_ERR (32+3) ++#define IDX_TX_KEYMISS (32+4) ++#define IDX_TXIMSTOP_ERR (32+5) ++#define IDX_TX_PHYERROR (32+6) ++#define IDX_TXCOL_QUEUE (32+10) ++#define IDX_TX_NOT_GRANT (32+19) ++#define IDX_SRAMBUF_FULL_ERR (32+22) ++#define IDX_FCSERR (32+23) ++#define IDX_RXFIFOOV (32+24) ++#define IDX_RX_WD_TIMEOUT_ERR (32+25) ++#define IDX_SHORT_LENGTH (32+26) ++#define IDX_LENGTH_ERROR (32+27) ++#define IDX_RX_PHYERROR (32+28) ++ ++#define IDX_QOS_DATA (0x28) ++#define IDX_RTS (0x1b) ++#define IDX_CTS (0x1c) ++#define IDX_ACK (0x1d) ++ ++ ++#define STS_MAX_CFG_FILE (0x40) ++#define SYS_STS_PRT_TAG (0x1) ++#define SYS_STS_PRT_INFO (0x0) ++ ++#define IS_MAC_STS(addr) (((addr) == RG_MAC_CNT_CTRL_FIQ) ||\ ++ ((addr) == RG_MAC_FRM_TYPE_CNT_CTRL) ||\ ++ ((addr) == RG_MAC_TX_STT_CHK) || \ ++ ((addr) == RG_MAC_TX_END_CHK) ||\ ++ ((addr) == RG_MAC_TX_EN_CHK) ||\ ++ ((addr) == RG_MAC_TX_ENWR_CHK) ||\ ++ ((addr) == RG_MAC_RX_DATA_LOCAL_CNT) ||\ ++ ((addr) == RG_MAC_RX_DATA_OTHER_CNT) ||\ ++ ((addr) == RG_MAC_RX_DATA_MUTIL_CNT) ) ++ ++ ++#define IS_AGC_STS(addr) ((addr ) == RG_AGC_STATE||\ ++ (addr ) == RG_AGC_OB_IC_GAIN||\ ++ (addr ) == RG_AGC_WATCH1||\ ++ (addr ) == RG_AGC_WATCH2||\ ++ (addr ) == RG_AGC_WATCH3||\ ++ (addr ) == RG_AGC_WATCH4||\ ++ (addr ) == RG_AGC_OB_ANT_NFLOOR||\ ++ (addr ) == RG_AGC_OB_CCA_RES||\ ++ (addr ) == RG_AGC_OB_CCA_COND01||\ ++ (addr ) == RG_AGC_OB_CCA_COND23) ++ ++#define IS_HOST_SW_STS(addr) ((addr & MOD_VADDR) == MOD_VADDR) ++ ++ ++enum sts_sys_idx{ ++ sts_mac_irq_txstart_idx, ++ sts_mac_irq_txend_idx, ++ sts_mac_irq_txenderr_idx, ++ sts_mac_irq_ackto_idx, ++ sts_mac_irq_txcol_flag_idx, ++ sts_mac_irq_rxstart_idx, ++ sts_mac_irq_mac_rxend_idx, ++ sts_mac_irq_mac_rxmpdu_ok_idx, ++ sts_mac_irq_unicast_idx, ++ sts_mac_irq_srambuf_full_idx, ++ sts_mac_irq_swirq_idx, ++ sts_mac_irq_tx_frame_type_idx, ++ sts_mac_irq_abscount_intr_idx, ++ sts_mac_irq_fiq_enable_idx, ++ sts_mac_irq_fiac_fw_timeout_err_idx, ++ sts_mac_irq_hw_timeout_err_idx, ++ sts_mac_irq_tx_wd_timeout_err_idx, ++ sts_mac_irq_txinvalidlen_err_idx, ++ sts_mac_irq_tx_keymiss_idx, ++ sts_mac_irq_tximstop_err_idx, ++ sts_mac_irq_tx_phyerror_idx, ++ sts_mac_irq_txcol_queue_idx, ++ sts_mac_irq_tx_not_grant_idx, ++ sts_mac_irq_srambuf_full_err_idx, ++ sts_mac_irq_fcserr_idx, ++ sts_mac_irq_rxfifoov_idx, ++ sts_mac_irq_rx_wd_timeout_err_idx, ++ sts_mac_irq_short_length_idx, ++ sts_mac_irq_length_error_idx, ++ sts_mac_irq_rx_phyerror_idx, ++ sts_frm_type_qos_data_idx, ++ sts_frm_type_rts_idx, ++ sts_frm_type_cts_idx, ++ sts_frm_type_ack_idx, ++ sts_mac_tx_start_chk_idx, ++ sts_mac_tx_end_chk_idx, ++ sts_mac_tx_en_chk_idx, ++ sts_mac_tx_enwr_chk_idx, ++ sts_mac_rx_data_local_cnt_idx, ++ sts_mac_rx_data_other_cnt_idx, ++ sts_mac_rx_data_mutil_cnt_idx, ++ sts_agc_st_idx, ++ sts_agc_gain_rx_ic_gain_idx, ++ sts_agc_gain_fine_db_idx, ++ sts_agc_wtc1_pw_sat_db_idx, ++ sts_agc_wtc1_prm20_db_idx, ++ sts_agc_wtc2_prm40_db_idx, ++ sts_agc_wtc2_prm80_db_idx, ++ sts_agc_wtc3_rssi0_db_idx, ++ sts_agc_wtc3_rssi1_db_idx, ++ sts_agc_wtc4_rssi2_db_idx, ++ sts_agc_wtc4_rssi3_db_idx, ++ sts_agc_ant_flr_snr_qdb_idx, ++ sts_agc_ant_flr_ant_flr_qdb_idx, ++ sts_cca_res_rdy_idx, ++ sts_cca_res_cond8_idx, ++ sts_cca_cnd01_cond0_idx, ++ sts_cca_cnd01_cond1_idx, ++ sts_cca_cnd23_cond2_idx, ++ sts_cca_cnd23_cond3_idx, ++ ++ sts_hst_irq_tx_error_idx, ++ sts_hst_irq_rx_error_idx, ++ sts_hst_irq_rx_ok_idx, ++ sts_hst_irq_tx_ok_idx, ++ sts_hst_irq_beacon_send_ok_vid0_idx , ++ sts_hst_irq_beacon_send_ok_vid1_idx , ++ sts_hst_irq_goto_wakeup_vid0_idx , ++ sts_hst_irq_goto_wakeup_vid1_idx , ++ sts_hst_irq_p2p_oppps_cwend_vid0_idx, ++ sts_hst_irq_p2p_oppps_cwend_vid1_idx, ++ sts_hst_irq_p2p_noa_start_vid0_idx , ++ sts_hst_irq_p2p_noa_start_vid1_idx , ++ sts_hst_irq_beacon_recv_ok_vid0_idx , ++ sts_hst_irq_beacon_recv_ok_vid1_idx , ++ sts_hst_irq_beacon_miss_vid0_idx , ++ sts_hst_irq_beacon_miss_vid1_idx , ++ ++ sts_hal_agg_start_tid0_idx, ++ sts_hal_agg_start_tid1_idx, ++ sts_hal_agg_start_tid2_idx, ++ sts_hal_agg_start_tid3_idx, ++ sts_hal_agg_start_tid4_idx, ++ sts_hal_agg_start_tid5_idx, ++ sts_hal_agg_start_tid6_idx, ++ sts_hal_agg_start_tid7_idx, ++ sts_hal_agg_start_tid8_idx, ++ sts_hal_agg_start_tid9_idx, ++ sts_hal_rx_fifo_full_idx, ++ sts_hal_rx_up_skb_idx, ++ sts_hal_rx_vif_id_err_idx, ++ sts_hal_rx_dcrypt_err_idx, ++ sts_hal_tx_num_idx, ++ sts_hal_tx_mpdus_idx, ++ sts_hal_tx_pages_idx, ++ sts_hal_dw_mpdu_idx, ++ sts_hal_cur_mpdu_idx, ++ sts_hal_cur_agg_page_idx, ++ sts_hal_allc_txds_idx, ++ sts_hal_free_txds_idx, ++ sts_hal_send_null_idx, ++ sts_hal_keep_alive_idx, ++ sts_hal_beacon_miss_idx, ++ sts_drv_tx_total_bytes_idx, ++ sts_drv_tx_pkts_idx, ++ sts_drv_tx_drops_idx, ++ sts_drv_tx_normal_idx, ++ sts_drv_tx_end_normal_idx, ++ sts_drv_tx_end_ampdu_idx, ++ sts_drv_tx_ampdu_idx, ++ sts_drv_tx_ampdu_on_frm_idx, ++ sts_drv_tx_end_fail_idx, ++ sts_drv_rx_ampdu_idx, ++ sts_drv_rx_bar_idx, ++ sts_drv_rx_no_qos_idx, ++ sts_drv_rx_dup_idx, ++ sts_drv_rx_ok_idx, ++ sts_drv_rx_flush_drop_idx, ++ sts_drv_rx_bar_drop_idx, ++ sts_drv_rx_skipped_idx, ++ sts_drv_txlist0_qcnt_idx, ++ sts_drv_txlist1_qcnt_idx, ++ sts_drv_txlist2_qcnt_idx, ++ sts_drv_txlist3_qcnt_idx, ++ sts_drv_txlist4_qcnt_idx, ++ sts_drv_txlist5_qcnt_idx, ++ sts_drv_txlist6_qcnt_idx, ++ sts_drv_txlist_qcnt_idx7, ++ sts_drv_txlist0_pend_qcnt_idx, ++ sts_drv_txlist1_pend_qcnt_idx, ++ sts_drv_txlist2_pend_qcnt_idx, ++ sts_drv_txlist3_pend_qcnt_idx, ++ sts_drv_txlist4_pend_qcnt_idx, ++ sts_drv_txlist5_pend_qcnt_idx, ++ sts_drv_txlist6_pend_qcnt_idx, ++ sts_drv_txlist7_pend_qcnt_idx, ++ sts_drv_send_skb_idx, ++ sts_vif_ip_pkt_total_idx, ++ sts_vif_ip_pkt_to_drv_idx, ++ sts_vif_ip_pkt_drop_idx, ++ sts_vif_tx_list_full_idx, ++ sts_vif_tx_ok_idx, ++ sts_vif_tx_cmp_idx, ++ sts_vif_tx_free_page_idx, ++ sts_vif_in_amsdu_idx, ++ sts_vif_out_amsdu_idx, ++ ++ ++ ++ ++ sts_hst_sw_max_idx, ++}; ++ ++/* ++ iw dev wlan0 vendor send 0xc3 0xc4 op_code func_code hw_addr obj_0, obj_1, obj_2,obj_3 ++*/ ++#pragma pack(push ,1) ++struct sts_cfg_data{ ++ unsigned short addr[STS_MAX_CFG_FILE]; ++ union sts_mac_reg_u cfg_ie[STS_MAX_CFG_FILE]; ++ unsigned char cfg_num; ++}; ++ ++struct statistic_cmd ++{ ++ unsigned char op_code; // 0x99 ++ ++ unsigned char iaddr_high; // hardware reg high part, ++ unsigned char iaddr_low; // hardware reg low part ++ unsigned char iobj_0; // obj_0 to work ++ unsigned char iobj_1; // obj_1 to work ++ unsigned char iobj_2; // obj_2 to work ++ unsigned char iobj_3; // obj_3 to work ++ ++ unsigned char faddr_high; // hardware reg high part, ++ unsigned char faddr_low; // hardware reg low part ++ unsigned char fobj_0; // obj_0 to work ++ unsigned char fobj_1; // obj_1 to work ++ unsigned char fobj_2; // obj_2 to work ++ unsigned char fobj_3; // obj_3 to work ++ ++ unsigned char func_code; //(0x0, stop); (0x1, start) ;(0x2, read) ++ ++}; ++ ++ ++struct sts_iw_if ++ { ++ unsigned char op_code; ++ unsigned short addr; ++ unsigned int val; ++ }; ++ ++#pragma pack(pop) ++ ++void sts_sw_probe(unsigned int sts_idx, unsigned int unit) ; ++void phy_stc(void); ++int get_snr(void); ++void get_phy_stc_info(unsigned int *arr); ++ ++unsigned int cca_busy_check(void); ++void sts_prt_info_map(void); ++void sts_default_cfg(struct sts_cfg_data* cfg_data, unsigned char sts_sys_type); ++void sts_update_cfg(struct sts_cfg_data* cfg_data, const char* data,unsigned int len); ++char** get_tag_info(unsigned short addr,unsigned int tag_info); ++void sts_clr_cnt(unsigned short addr); ++void sts_start_cnt(unsigned short addr, ++ char obj_0,char obj_1,char obj_2,char obj_3); ++ ++void sts_read_cnt(unsigned short addr, ++ unsigned char obj_0,unsigned char obj_1,unsigned char obj_2, unsigned char obj_3, ++ char* sts_tag[], char* sts_info[], unsigned int* idx_val, char func_code); ++ ++void sts_stop_cnt(unsigned short addr); ++void sts_show_cfg( struct sts_cfg_data* cfg_data); ++void sts_opt_by_cfg(struct sts_cfg_data* cfg_data, unsigned char func_code); ++void sts_prt_agc_field(unsigned short addr, ++ char* sts_tag[], char* sts_info[], char func_code); ++ ++unsigned int val_to_idx(unsigned int idx_val[], unsigned int val); ++ ++/////////////////////////////// layer statistic defination//////////////////////// ++/* ++ iw dev wlan0 vendor send 0xc3 0xc4 op_code(B) ctrl_msg3, ctrl_msg2, ctrl_msg1, ctrl_msg0 ++ bit31~bit28: sts module: bit31 wifi_mac layer; bit30 driver layer; bit29 hal layer; bit28 hw interface ++ bit27~bit24: sts type: bit27 tx; bit26 rx; bit25 allocate resource; bit24 free resource ++ bit23~bit0: the detail message by sts type and sts module ++*/ ++ ++#define STS_MOD_WMAC BIT(31) ++#define STS_MOD_DRV BIT(30) ++#define STS_MOD_HAL BIT(29) ++#define STS_MOD_HIF BIT(28) ++ ++#define STS_TYP_TX (BIT(27)) ++#define STS_TYP_RX (BIT(26)) ++ ++// RF capture ++ ++#define INBUFFER_LEN_VALID_BIT (256-2) ++#define INBUFFER_LEN (256/8) ++#define ADC_WIDTH 24 ++#define BLOCK_RAW_LEN INBUFFER_LEN ++#define BLOCK_REAL_LEN (INBUFFER_LEN_VALID_BIT/ADC_WIDTH*4) ++#define BLOCK_REAL_COUNT_WORD (BLOCK_REAL_LEN/4) ++ ++#define TESTBUSSRAM_LEN 0x200000 ++#define INBUFFER_LEN (256/8) ++#define INBUFFER_LEN_VALID_BIT (256-2) ++#define INBUFFER_LEN_VALID ((INBUFFER_LEN_VALID_BIT)/8) ++#define TESTBUFFER_LEN (256-8) ++ ++#define SELFTEST 1 //LG ++#define DA 0 //LG ++ ++#define SW 9 ++#define FCS_OK 6 ++#define FCS_ERR 3 ++#define FCS_ERR_OFDM 5 ++#define FCS_ERR_DSS 4 ++#define LSIG_PARITY_ERR 8 ++#define HTSIG_CRC_ERR 7 ++#define CCA_FSM_TRIG 2 ++#define AGC_FSM_TRIG 0 ++#define CCA_AGC_FSM_TRIG 1 ++ ++ ++#define SDIO_BASE_A 0x00a0b000 ++#define CAP_SRAM_SWITCH_BASE 0x00a0d000 ++ ++#define TBC_OFFSET_100 (0x100 + SDIO_BASE_A) //0x2d00 ++#define TBC_OFFSET_104 (0x104 + SDIO_BASE_A) //0x2d04 ++#define TBC_OFFSET_108 (0x108 + SDIO_BASE_A) //0x2d08 ++#define TBC_OFFSET_10C (0x10c + SDIO_BASE_A) //0x2d0C ++#define TBC_OFFSET_110 (0x110 + SDIO_BASE_A) //0x2d10 ++#define TBC_OFFSET_114 (0x114 + SDIO_BASE_A) //0x2d14 ++#define TBC_OFFSET_118 (0x118 + SDIO_BASE_A) //0x2d18 ++#define TBC_OFFSET_11C (0x11C + SDIO_BASE_A) //0x2d1C ++#define TBC_OFFSET_120 (0x120 + SDIO_BASE_A) //0x2d20 ++#define TBC_OFFSET_124 (0x124 + SDIO_BASE_A) //0x2d24 ++#define TBC_OFFSET_128 (0x128 + SDIO_BASE_A) //0x2d28 ++ ++#define TBC_RAM_SHARE (0xe4 + CAP_SRAM_SWITCH_BASE)//INTF SRAM SHARE ENABLE BIT31: 1-> CAPTURE BUF ++ ++void batch_dump_reg(struct wiphy *wiphy,unsigned int addr[], unsigned int addr_num); ++ ++#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_timer.c b/drivers/net/wireless/w1/vmac/wifi_drv_timer.c new file mode 100644 -index 000000000000..1a2c330deb88 +index 0000000000000000000000000000000000000000..1a2c330deb88a0330429dbf459a66bad4b18c634 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_timer.c @@ -0,0 +1,180 @@ @@ -59078,7 +59473,7 @@ index 000000000000..1a2c330deb88 +} diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_timer.h b/drivers/net/wireless/w1/vmac/wifi_drv_timer.h new file mode 100644 -index 000000000000..8d1bd88a86e8 +index 0000000000000000000000000000000000000000..8d1bd88a86e89223a55f97cecd48309a48d64f64 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_timer.h @@ -0,0 +1,73 @@ @@ -59157,7 +59552,7 @@ index 000000000000..8d1bd88a86e8 +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_uapsd.c b/drivers/net/wireless/w1/vmac/wifi_drv_uapsd.c new file mode 100644 -index 000000000000..c52e9e64c3eb +index 0000000000000000000000000000000000000000..3939f92f57d4e5091361d4aebf1a0a712cf4a9dd --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_uapsd.c @@ -0,0 +1,611 @@ @@ -59175,7 +59570,7 @@ index 000000000000..c52e9e64c3eb + **************************************************************************************** + */ + -+ ++#include "wifi_drv_uapsd.h" +#include "wifi_mac_com.h" +#include "wifi_drv_xmit.h" +#include "wifi_pkt_desc.h" @@ -59466,12 +59861,12 @@ index 000000000000..c52e9e64c3eb + txn_real = maxsp; + } + -+ printk("before tx uapsd\n"); ++ pr_debug("before tx uapsd\n"); + DPRINTF(AML_DEBUG_PWR_SAVE, "%s %d flush=%d uapsd_qqcnt=%d\n", __func__,__LINE__, flush, uapsd_qqcnt); + for (count = txn_real; ((count > 0) && (eosp_flag==0)); count--) + { + -+ printk("tx=%d\n", count); ++ pr_debug("tx=%d\n", count); + +#ifdef DRV_SUPPORT_TX_WITHDRAW + if (drv_sta->sta_txwd_uapsd_qqcnt) @@ -59774,7 +60169,7 @@ index 000000000000..c52e9e64c3eb + diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_uapsd.h b/drivers/net/wireless/w1/vmac/wifi_drv_uapsd.h new file mode 100644 -index 000000000000..cacc7bb163df +index 0000000000000000000000000000000000000000..cacc7bb163dfecec70a591105e613db1fd25c352 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_uapsd.h @@ -0,0 +1,32 @@ @@ -59812,10 +60207,10 @@ index 000000000000..cacc7bb163df +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_xmit.c b/drivers/net/wireless/w1/vmac/wifi_drv_xmit.c new file mode 100644 -index 000000000000..30f30b0ecc6a +index 0000000000000000000000000000000000000000..8c48bf32c4b849b6226f4741ce7cabe0cafbae20 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_xmit.c -@@ -0,0 +1,3243 @@ +@@ -0,0 +1,3326 @@ +/* + **************************************************************************************** + * @@ -60048,7 +60443,7 @@ index 000000000000..30f30b0ecc6a + + } else { + if (print_cnt++ == 200) { -+ printk("%s, queue_id:%d full\n", __func__, queue_id); ++ pr_debug("%s, queue_id:%d full\n", __func__, queue_id); + } + } + @@ -60056,7 +60451,7 @@ index 000000000000..30f30b0ecc6a + return 1; +} + -+void aml_prepare_agg_tx_priv_param(struct drv_private *drv_priv, ++static void aml_prepare_agg_tx_priv_param(struct drv_private *drv_priv, + struct hi_agg_tx_desc *agg_content, struct drv_txdesc *ptxdesc, struct wifi_station *sta) +{ + struct wifi_mac *wifimac = drv_priv->wmac; @@ -60334,7 +60729,7 @@ index 000000000000..30f30b0ecc6a + } + + if (hal_priv->bhaltxdrop || hal_priv->bhalPowerSave) { -+ printk("%s hal_priv->bhaltxdrop:%d\n", __func__, hal_priv->bhaltxdrop); ++ pr_debug("%s hal_priv->bhaltxdrop:%d\n", __func__, hal_priv->bhaltxdrop); + } + return 0; +} @@ -60612,12 +61007,12 @@ index 000000000000..30f30b0ecc6a + + ptxdesc->rate_valid = 1; + txinfo->seqnum = *(unsigned short *)wh->i_seq >> WIFINET_SEQ_SEQ_SHIFT;//seqnum -+ //printk("%s ptxdesc:%p, skbbuf:%p, vid:%d, sta:%p, tid:%d, sn:%04x, ampdu:%d, qos:%d, rate_code:%02x, frame_control:%04x, mcast:%d, data:%d, dhcp:%d, eap:%d\n", ++ //pr_debug("%s ptxdesc:%p, skbbuf:%p, vid:%d, sta:%p, tid:%d, sn:%04x, ampdu:%d, qos:%d, rate_code:%02x, frame_control:%04x, mcast:%d, data:%d, dhcp:%d, eap:%d\n", + // __func__, ptxdesc, skbbuf, wnet_vif->wnet_vif_id, sta, txinfo->tid_index, txinfo->seqnum, txinfo->b_Ampdu, txinfo->b_qosdata, + // ratectrl->vendor_rate_code, *((unsigned short *)&(wh->i_fc[0])), txinfo->b_mcast, txinfo->b_datapkt, mac_pkt_info->b_dhcp, mac_pkt_info->b_eap); + + if (txinfo->b_pmf) { -+ printk("%s vid:%d, sta:%p, sn:%04x, frame_control:%04x, mcast:%d\n", ++ pr_debug("%s vid:%d, sta:%p, sn:%04x, frame_control:%04x, mcast:%d\n", + __func__, wnet_vif->wnet_vif_id, sta, txinfo->seqnum, *((unsigned short *)&(wh->i_fc[0])), txinfo->b_mcast); + } + @@ -60698,7 +61093,7 @@ index 000000000000..30f30b0ecc6a + //if p2p ps frame, backup + //if ps4quiet frame, backup; but if probereq, just send out + if ((wnet_vif->vm_pstxqueue_flags & WIFINET_PSQUEUE_MASK) && -+ !(((wnet_vif->vm_pstxqueue_flags & WIFINET_PSQUEUE_MASK) == WIFINET_PSQUEUE_PS4QUIET) && (WIFINET_IS_PROBEREQ(wh)))) ++ !(((wnet_vif->vm_pstxqueue_flags & WIFINET_PSQUEUE_MASK) == WIFINET_PSQUEUE_PS4QUIET) && (WIFINET_IS_PROBEREQ(wh) || txinfo->b_dpp))) + { + if (wnet_vif->vm_state != WIFINET_S_CONNECTED) + { @@ -60719,7 +61114,7 @@ index 000000000000..30f30b0ecc6a + //for ap/go, if peer sta is in powersave, backup + if (sta->sta_flags & WIFINET_NODE_PWR_MGT) + { -+ //printk("ap buffer queue\n"); ++ //pr_debug("ap buffer queue\n"); + drv_priv->net_ops->wifi_mac_pwrsave_psqueue_enqueue(sta, skbbuf); + error = 0; + break; @@ -60793,10 +61188,6 @@ index 000000000000..30f30b0ecc6a + && (p2p_pub_act->action == WIFINET_ACT_PUBLIC_P2P)) { + switch (p2p_pub_act->subtype) { + case P2P_GO_NEGO_REQ: -+ case P2P_GO_NEGO_CONF: -+ ret = TX_P2P_GO_NEGO_REQ_GO_NEGO_CONF; -+ break; -+ + case P2P_GO_NEGO_RESP: + case P2P_PROVISION_DISC_REQ: + case P2P_PROVISION_DISC_RESP: @@ -60804,7 +61195,9 @@ index 000000000000..30f30b0ecc6a + case P2P_INVITE_RESP: + ret = TX_P2P_OTHER_GO_NEGO_FRAME; + break; -+ ++ case P2P_GO_NEGO_CONF: ++ ret = TX_P2P_GO_NEGO_CONF; ++ break; + default: + break; + } @@ -60817,6 +61210,13 @@ index 000000000000..30f30b0ecc6a + ret = TX_P2P_GAS; + } +#endif ++ if (p2p_pub_act ++ && (p2p_pub_act->category == AML_CATEGORY_PUBLIC) ++ && (p2p_pub_act->action == WIFINET_ACT_PUBLIC_P2P)) { ++ if (p2p_pub_act->oui_type == OUI_TYPE_DPP) { ++ ret = TX_MGMT_DPP_STATUS; ++ } ++ } + + if (WIFINET_IS_PROBEREQ(wh)) { + ret = TX_MGMT_PROBE_REQ; @@ -60836,10 +61236,11 @@ index 000000000000..30f30b0ecc6a + } else if (WIFINET_IS_ACTION(wh)) { + if ((p2p_pub_act->category == AML_CATEGORY_BACK) && (p2p_pub_act->action == WIFINET_ACTION_BA_ADDBA_REQUEST)) { + ret = TX_MGMT_ADDBA_RSP; ++ } else if (p2p_pub_act->action == WIFINET_ACT_PUBLIC_CSA) { ++ ret = TX_MGMT_CSA_ACTION; + } + } else if (mac_pkt_info->b_eap) { + ret = TX_MGMT_EAPOL; -+ + } else if (mac_pkt_info->b_dhcp) { + ret = TX_MGMT_DHCP; + } @@ -60892,7 +61293,7 @@ index 000000000000..30f30b0ecc6a + if (txinfo->b_uapsd && (wh->i_fc[0] & (FRAME_TYPE_MASK | FRAME_SUBTYPE_MASK)) == MAC_FCTRL_QOS_DATA) { + drv_tx_queue_uapsd_nsta(drv_priv, &txdesc_list_head, drv_sta); + DRV_TXQ_UNLOCK(txlist); -+ printk("%s uapsd\n", __func__); ++ pr_debug("%s uapsd\n", __func__); + return 0; + } + @@ -60911,7 +61312,7 @@ index 000000000000..30f30b0ecc6a + //mcast backup also use txlist_backup_qcnt + if (txinfo->ps) { + drv_tx_mcastq_addbuf(drv_priv, &txdesc_list_head); -+ printk("%s mcastq\n", __func__); ++ pr_debug("%s mcastq\n", __func__); + return 0; + } +#endif @@ -61057,6 +61458,7 @@ index 000000000000..30f30b0ecc6a + sta->sta_inact_time = jiffies; +} + ++extern char dpp_pub_action_str[][50]; +static void drv_tx_complete_mgmt_handle(struct drv_private *drv_priv,struct drv_txdesc *ptxdesc, + unsigned char status, struct wifi_station *sta) +{ @@ -61064,14 +61466,17 @@ index 000000000000..30f30b0ecc6a + int txok = (status == TX_DESCRIPTOR_STATUS_SUCCESS); + int mgmt_arg; + static int deauth_fail_time = 0; ++ struct wifi_frame *wh = (struct wifi_frame *)ptxdesc->txdesc_ddraddr; ++ struct wifi_mac_p2p_pub_act_frame *p2p_pub_act = NULL; + ++ p2p_pub_act = (struct wifi_mac_p2p_pub_act_frame *)((unsigned char *)wh + sizeof(struct wifi_frame)); + wnet_vif = sta->sta_wnet_vif; + + if ((ptxdesc->txdesc_frame_flag == TX_P2P_OTHER_GO_NEGO_FRAME) -+ || (ptxdesc->txdesc_frame_flag == TX_P2P_GO_NEGO_REQ_GO_NEGO_CONF) ++ || (ptxdesc->txdesc_frame_flag == TX_P2P_GO_NEGO_CONF) + || (ptxdesc->txdesc_frame_flag == TX_P2P_PRESENCE_REQ)) { + -+ printk("%s, txdesc_frame_flag=%d, status=%d\n", __func__, ptxdesc->txdesc_frame_flag, status); ++ pr_debug("%s, txdesc_frame_flag=%d, status=%d\n", __func__, ptxdesc->txdesc_frame_flag, status); + if (txok) { + sta->sta_wnet_vif->vm_p2p->tx_status_flag = WIFINET_TX_STATUS_SUCC; + sta->sta_wnet_vif->vm_p2p->send_tx_status_flag = 1; @@ -61079,7 +61484,7 @@ index 000000000000..30f30b0ecc6a + sta->sta_wnet_vif->vm_p2p->raw_action_pkt, sta->sta_wnet_vif->vm_p2p->raw_action_pkt_len, txok, GFP_KERNEL); + + } else { -+ if (ptxdesc->txdesc_frame_flag == TX_P2P_GO_NEGO_REQ_GO_NEGO_CONF || ptxdesc->txdesc_frame_flag == TX_P2P_PRESENCE_REQ) { ++ if (ptxdesc->txdesc_frame_flag == TX_P2P_GO_NEGO_CONF || ptxdesc->txdesc_frame_flag == TX_P2P_PRESENCE_REQ) { + sta->sta_wnet_vif->vm_p2p->action_retry_time = DEFAULT_MGMT_RETRY_INTERVAL; + + } else { @@ -61092,7 +61497,7 @@ index 000000000000..30f30b0ecc6a + +#ifdef CTS_VERIFIER_GAS + if (ptxdesc->txdesc_frame_flag == TX_P2P_GAS) { -+ printk("%s, txdesc_frame_flag=%d, status=%d\n", __func__, ptxdesc->txdesc_frame_flag, status); ++ pr_debug("%s, txdesc_frame_flag=%d, status=%d\n", __func__, ptxdesc->txdesc_frame_flag, status); + + if ((sta->sta_wnet_vif->vm_p2p->action_code == WIFINET_ACT_PUBLIC_GAS_REQ && sta->sta_wnet_vif->vm_p2p->p2p_flag & P2P_GAS_RSP) || + (sta->sta_wnet_vif->vm_p2p->action_code == WIFINET_ACT_PUBLIC_GAS_RSP && txok) || @@ -61111,15 +61516,69 @@ index 000000000000..30f30b0ecc6a + } + } +#endif ++ ++ if (ptxdesc->txdesc_frame_flag == TX_MGMT_CSA_ACTION) { ++ AML_OUTPUT("channel switch announce action frm status=%d, channel:%d\n",status, sta->sta_wmac->wm_curchan->chan_pri_num); ++ } ++ + if ((ptxdesc->txdesc_frame_flag >= TX_MGMT_PROBE_REQ) && !txok) { + drv_priv->drv_ops.cca_busy_check(); -+ printk("%s, txdesc_frame_flag:%d, status=%d, rate:%02x\n", ++ pr_debug("%s, txdesc_frame_flag:%d, status=%d, rate:%02x\n", + __func__, ptxdesc->txdesc_frame_flag, status, ptxdesc->txdesc_rateinfo[0].vendor_rate_code); + + } else if (ptxdesc->txdesc_frame_flag == TX_MGMT_ADDBA_RSP) { + ; + } + ++ if (p2p_pub_act && (p2p_pub_act->category == AML_CATEGORY_PUBLIC)) { ++ if (p2p_pub_act->action == WIFINET_ACT_PUBLIC_P2P && p2p_pub_act->oui_type == OUI_TYPE_DPP) { ++ unsigned char dpp_action_subtype = *((char*)wh + sizeof(struct wifi_frame) + 7); ++ ++ if (dpp_action_subtype < 19) { ++ AML_OUTPUT("DPP->%s, tx_status:%d, vm_flags_ext2:0x%x, %d\n", dpp_pub_action_str[dpp_action_subtype], status, wnet_vif->vm_flags_ext2, sizeof(dpp_pub_action_str[0])); ++ } else { ++ AML_OUTPUT("subtype:%d\n", dpp_action_subtype); ++ } ++ ++ if (txok) { ++ sta->sta_wnet_vif->vm_p2p->send_tx_status_flag = 1; ++ sta->sta_wnet_vif->vm_wmac->wm_p2p_connection_protect = 0; ++ cfg80211_mgmt_tx_status(sta->sta_wnet_vif->vm_wdev, sta->sta_wnet_vif->vm_p2p->cookie, ++ sta->sta_wnet_vif->vm_p2p->raw_action_pkt, sta->sta_wnet_vif->vm_p2p->raw_action_pkt_len, txok, GFP_KERNEL); ++ if (wnet_vif->vm_flags_ext2 & WIFINET_FEXT2_DPP_CONNECTION_STATUS_RETRY) { ++ wnet_vif->vm_flags_ext2 &= ~WIFINET_FEXT2_DPP_CONNECTION_STATUS_RETRY; ++ } ++ } else { ++ if (dpp_action_subtype == 12) { ++ AML_OUTPUT("retry dpp connection status frame\n"); ++ wnet_vif->vm_flags_ext2 |= WIFINET_FEXT2_DPP_CONNECTION_STATUS_RETRY; ++ os_timer_ex_start_period(&sta->sta_wnet_vif->vm_actsend, 1000); ++ } else { ++ sta->sta_wnet_vif->vm_p2p->send_tx_status_flag = 1; ++ sta->sta_wnet_vif->vm_wmac->wm_p2p_connection_protect = 0; ++ cfg80211_mgmt_tx_status(sta->sta_wnet_vif->vm_wdev, sta->sta_wnet_vif->vm_p2p->cookie, ++ sta->sta_wnet_vif->vm_p2p->raw_action_pkt, sta->sta_wnet_vif->vm_p2p->raw_action_pkt_len, WIFINET_TX_STATUS_FAIL, GFP_KERNEL); ++ } ++ } ++ wnet_vif->vm_flags_ext2 &= ~WIFINET_FEXT2_DPP_SEND; ++ if (wnet_vif->vm_flags_ext2 & WIFINET_FEXT2_MGMT_RESTORE_CHANNEL) { ++ AML_OUTPUT("dpp frame restore chan\n"); ++ wnet_vif->vm_flags_ext2 &= ~WIFINET_FEXT2_MGMT_RESTORE_CHANNEL; ++ wifi_mac_restore_wnet_vif_channel_task(wnet_vif); ++ } ++ } else if (((p2p_pub_act->action == WIFINET_ACT_PUBLIC_GAS_REQ) || (p2p_pub_act->action == WIFINET_ACT_PUBLIC_GAS_RSP))) { ++ sta->sta_wnet_vif->vm_p2p->send_tx_status_flag = 1; ++ cfg80211_mgmt_tx_status(sta->sta_wnet_vif->vm_wdev, sta->sta_wnet_vif->vm_p2p->cookie, ++ sta->sta_wnet_vif->vm_p2p->raw_action_pkt, sta->sta_wnet_vif->vm_p2p->raw_action_pkt_len, txok, GFP_KERNEL); ++ wnet_vif->vm_flags_ext2 &= ~WIFINET_FEXT2_DPP_SEND; ++ if (wnet_vif->vm_flags_ext2 & WIFINET_FEXT2_MGMT_RESTORE_CHANNEL) { ++ AML_OUTPUT("gas frame restore chan\n"); ++ wnet_vif->vm_flags_ext2 &= ~WIFINET_FEXT2_MGMT_RESTORE_CHANNEL; ++ wifi_mac_restore_wnet_vif_channel_task(wnet_vif); ++ } ++ } ++ } ++ + if (ptxdesc->txdesc_frame_flag == TX_MGMT_DEAUTH && txok + && sta->sta_wnet_vif->vm_opmode == WIFINET_M_STA) { + wifi_mac_add_work_task(wnet_vif->vm_wmac, wifi_mac_sm_switch, NULL, (SYS_TYPE)wnet_vif, WIFINET_S_SCAN, 0, 0, 0); @@ -61402,7 +61861,7 @@ index 000000000000..30f30b0ecc6a +#endif + + if (ptxdesc == NULL) { -+ //printk("%s: callback txds is null\n", __func__); ++ //pr_err("%s: callback txds is null\n", __func__); + return; + } + @@ -61412,7 +61871,7 @@ index 000000000000..30f30b0ecc6a + + DRV_TXQ_LOCK(txlist); + if (ptxdesc->txdesc_sta == NULL) { -+ printk("%s pkt has already freed\n", __func__); ++ pr_warn("%s pkt has already freed\n", __func__); + DRV_TXQ_UNLOCK(txlist); + return; + } @@ -61491,9 +61950,11 @@ index 000000000000..30f30b0ecc6a + if (drv_priv->drv_config.cfg_txaggr) + { + drv_txlist_push_pending(drv_priv, txlist, vid); ++ DRV_TXQ_UNLOCK(txlist); + drv_priv->net_ops->wifi_mac_free_txamsdu_queue(drv_priv->wmac, vid); ++ } else { ++ DRV_TXQ_UNLOCK(txlist); + } -+ DRV_TXQ_UNLOCK(txlist); + + drv_txq_backup_drain(drv_priv, txlist, vid); +} @@ -61519,7 +61980,7 @@ index 000000000000..30f30b0ecc6a + txlist->txlist_qcnt--; + ptxdesc->txdesc_sta = NULL; + -+ printk("free qid:%d, drv_sta:%p\n", ptxdesc->txinfo->queue_id, drv_sta); ++ pr_debug("free qid:%d, drv_sta:%p\n", ptxdesc->txinfo->queue_id, drv_sta); + DRV_TXQ_UNLOCK(txlist); + drv_tx_complete(drv_priv, ptxdesc, 0); + DRV_TXQ_LOCK(txlist); @@ -61569,7 +62030,7 @@ index 000000000000..30f30b0ecc6a + +void drv_set_is_mother_channel(struct drv_private *drv_priv, unsigned char vid, unsigned char enable) +{ -+ //printk("vid:%d mother channel is:%d\n", vid, enable); ++ //pr_debug("vid:%d mother channel is:%d\n", vid, enable); + drv_priv->is_mother_channel[vid] = enable; +} + @@ -61583,7 +62044,7 @@ index 000000000000..30f30b0ecc6a + ptxdesc = list_first_entry(&drv_priv->drv_normal_buffer_queue[vid], struct drv_txdesc, txdesc_queue); + list_del_init(&ptxdesc->txdesc_queue); + drv_tx_complete(drv_priv, ptxdesc, 0); -+ //printk("%s\n", __func__); ++ //pr_debug("%s\n", __func__); + } + + drv_priv->drv_normal_buffer_count[vid] = 0; @@ -61598,50 +62059,66 @@ index 000000000000..30f30b0ecc6a + struct list_head txdesc_list_head; + struct aml_driver_nsta *drv_sta; + struct wlan_net_vif *wnet_vif = NULL; ++ signed char status = 0; + + INIT_LIST_HEAD(&txdesc_list_head); + -+ DRV_TX_NORMAL_BUF_LOCK(drv_priv); -+ while (!list_empty(&drv_priv->drv_normal_buffer_queue[vid])) ++ while (1) + { -+ ptxdesc = list_first_entry(&drv_priv->drv_normal_buffer_queue[vid], struct drv_txdesc, txdesc_queue); -+ list_del_init(&ptxdesc->txdesc_queue); -+ list_add_tail(&ptxdesc->txdesc_queue, &txdesc_list_head); ++ DRV_TX_NORMAL_BUF_LOCK(drv_priv); ++ do { ++ status = 0; ++ if (!list_empty(&drv_priv->drv_normal_buffer_queue[vid])) { ++ ptxdesc = list_first_entry(&drv_priv->drv_normal_buffer_queue[vid], struct drv_txdesc, txdesc_queue); ++ txlist = &drv_priv->drv_txlist_table[ptxdesc->txinfo->queue_id]; + -+ drv_sta = ptxdesc->txdesc_sta; -+ txlist = &drv_priv->drv_txlist_table[ptxdesc->txinfo->queue_id]; ++ ASSERT(txlist->txlist_qnum == ptxdesc->txinfo->queue_id); ++ if (aml_tx_hal_buffer_full(drv_priv,txlist->txlist_qnum, 1, 1) == 1) ++ { ++ status = -1; ++ break; ++ } + -+ ASSERT(txlist->txlist_qnum == ptxdesc->txinfo->queue_id); -+ if (aml_tx_hal_buffer_full(drv_priv,txlist->txlist_qnum, 1, 1) == 1) -+ { -+ list_add_tail(&ptxdesc->txdesc_queue, &drv_priv->drv_normal_buffer_queue[vid]); -+ DRV_TX_NORMAL_BUF_UNLOCK(drv_priv); -+ return; -+ } -+ DRV_TX_NORMAL_BUF_UNLOCK(drv_priv); ++ list_del_init(&ptxdesc->txdesc_queue); ++ drv_priv->drv_normal_buffer_count[vid]--; + -+ if (drv_sta == NULL) { -+ continue; -+ } ++ drv_sta = ptxdesc->txdesc_sta; ++ if (drv_sta == NULL || drv_sta->net_nsta == NULL) { ++ AML_OUTPUT("drv_sta:0x%x\n", drv_sta); ++ status = 1; ++ break; ++ } + -+ if (drv_sta->net_nsta != NULL) { -+ wnet_vif = ((struct wifi_station *)(drv_sta->net_nsta))->sta_wnet_vif; -+ } ++ wnet_vif = ((struct wifi_station *)(drv_sta->net_nsta))->sta_wnet_vif; ++ if (wnet_vif == NULL || wnet_vif->vm_state != WIFINET_S_CONNECTED) { ++ status = 2; ++ break; ++ } + -+ if ((wnet_vif != NULL) && (wnet_vif->vm_state == WIFINET_S_CONNECTED)) { -+ ptxdesc->txinfo->b_Ampdu = 0; -+ if (drv_tx_normal(drv_priv, txlist, &txdesc_list_head, vid)) -+ { -+ ASSERT(0); -+ return; ++ list_add_tail(&ptxdesc->txdesc_queue, &txdesc_list_head); ++ } else { ++ status = -1; ++ break; + } -+ } else { ++ } while(0); ++ DRV_TX_NORMAL_BUF_UNLOCK(drv_priv); ++ ++ if (status < 0) { ++ break; ++ } else if (status > 0) { ++ AML_OUTPUT("drop buffer txdesc, reason:%d\n", status); + drv_tx_complete(drv_priv, ptxdesc, 0); ++ continue; ++ } ++ ++ ptxdesc->txinfo->b_Ampdu = 0; ++ /* coverity[LOCK:SUPPRESS] */ ++ if (drv_tx_normal(drv_priv, txlist, &txdesc_list_head, vid)) ++ { ++ ASSERT(0); ++ return; + } -+ DRV_TX_NORMAL_BUF_LOCK(drv_priv); -+ drv_priv->drv_normal_buffer_count[vid]--; + } -+ DRV_TX_NORMAL_BUF_UNLOCK(drv_priv); +} + +unsigned short drv_tx_pending_pkt(struct drv_private *drv_priv) @@ -61742,7 +62219,7 @@ index 000000000000..30f30b0ecc6a + tid = DRV_GET_TIDTXINFO(drv_sta, tid_index); + + if (tid->cleanup_inprogress) { -+ printk(" %s %d \n", __func__, __LINE__); ++ pr_debug(" %s %d \n", __func__, __LINE__); + return 0; + } + @@ -62003,9 +62480,9 @@ index 000000000000..30f30b0ecc6a + desc_id = (tid->baw_head + index) & (DRV_TID_MAX_BUFS - 1); + + if (tid->tx_desc[desc_id] != NULL) { -+ printk("desc_id:%d, sta:%p\n", desc_id, tid->drv_sta->net_nsta); -+ printk("new seqnum=%d new tid_index=%d\n", ptxdesc->txinfo->seqnum, ptxdesc->txinfo->tid_index); -+ printk("tid->seq_start=%d", tid->seq_start); ++ pr_debug("desc_id:%d, sta:%p\n", desc_id, tid->drv_sta->net_nsta); ++ pr_debug("new seqnum=%d new tid_index=%d\n", ptxdesc->txinfo->seqnum, ptxdesc->txinfo->tid_index); ++ pr_debug("tid->seq_start=%d", tid->seq_start); + } + + tid->tx_desc[desc_id] = ptxdesc; @@ -62251,9 +62728,10 @@ index 000000000000..30f30b0ecc6a + ptxdesc = list_first_entry(txdesc_list_head, struct drv_txdesc, txdesc_queue); + wh = (struct wifi_frame *)os_skb_data(ptxdesc->txdesc_mpdu); + -+ if (!drv_priv->is_mother_channel[vid] && !WIFINET_IS_PROBEREQ(wh)) { -+ printk("%s vid:%d not mother channel, buffer\n", __func__, vid); ++ if (!drv_priv->is_mother_channel[vid] && !WIFINET_IS_PROBEREQ(wh) && (!ptxdesc->txinfo->b_dpp)) { ++ pr_debug("%s vid:%d not mother channel, buffer\n", __func__, vid); + ++ list_del_init(&ptxdesc->txdesc_queue); + DRV_TX_NORMAL_BUF_LOCK(drv_priv); + list_add_tail(&ptxdesc->txdesc_queue, &drv_priv->drv_normal_buffer_queue[vid]); + drv_priv->drv_normal_buffer_count[vid]++; @@ -62618,7 +63096,7 @@ index 000000000000..30f30b0ecc6a + unsigned char hal_co_get_cnt; + + if (!drv_priv->is_mother_channel[tid->vid]) { -+ //printk("%s not mother channel vid:%d\n", __func__, tid->vid); ++ //pr_debug("%s not mother channel vid:%d\n", __func__, tid->vid); + return; + } + @@ -62792,7 +63270,7 @@ index 000000000000..30f30b0ecc6a + + tid->seq_next = tid->seq_start; + tid->baw_tail = tid->baw_head; -+ printk("%s baw_head %x\n", __func__, tid->baw_head); ++ pr_warn("%s baw_head %x\n", __func__, tid->baw_head); +} + +static void @@ -63054,14 +63532,14 @@ index 000000000000..30f30b0ecc6a + break; + + default: -+ printk(" %s %d vm_mac_mode =%d ERROR\n",__func__,__LINE__, wnet_vif->vm_mac_mode); ++ pr_err(" %s %d vm_mac_mode =%d ERROR\n",__func__,__LINE__, wnet_vif->vm_mac_mode); + break; + } + return 0; +} diff --git a/drivers/net/wireless/w1/vmac/wifi_drv_xmit.h b/drivers/net/wireless/w1/vmac/wifi_drv_xmit.h new file mode 100644 -index 000000000000..af08e05786f7 +index 0000000000000000000000000000000000000000..af08e05786f7fd1790f10c06d32786693b8f834d --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_drv_xmit.h @@ -0,0 +1,101 @@ @@ -63168,10 +63646,10 @@ index 000000000000..af08e05786f7 +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_hal.c b/drivers/net/wireless/w1/vmac/wifi_hal.c new file mode 100644 -index 000000000000..8e11ef3dbdf0 +index 0000000000000000000000000000000000000000..52798e53bb066b6b7b3222d2c8c2effb4f7f8b2b --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_hal.c -@@ -0,0 +1,3540 @@ +@@ -0,0 +1,3590 @@ +#ifdef HAL_SIM_VER +#ifdef FW_NAME +namespace FW_NAME @@ -63222,12 +63700,13 @@ index 000000000000..8e11ef3dbdf0 + +unsigned char hal_set_pn_win(unsigned long long *pn_win) +{ -+ unsigned char i = 0, offset = 0; ++ unsigned char i, offset = 0; + unsigned long long win; + unsigned long long tmp; + + for (i = 0; i < 2; i++) { + win = *(pn_win + i); ++ + while(win > 0) { + if ((win & 1) == 0) { + break; @@ -63235,52 +63714,51 @@ index 000000000000..8e11ef3dbdf0 + win >>= 1; + offset++; + } -+ if (offset < MAX_PN_WINDOW/2) { ++ ++ if (offset < MAX_PN_WINDOW / 2) { + break; + } + } ++ + if (offset == 0) { + offset = 1; + } + -+ if (offset > 0 && offset < MAX_PN_WINDOW/2) { ++ if (offset > 0 && offset < MAX_PN_WINDOW / 2) { + pn_win[0] >>= offset; + tmp = pn_win[1] & ((1 << offset) - 1); -+ pn_win[0] |= (tmp << (MAX_PN_WINDOW/2 - offset)); ++ pn_win[0] |= (tmp << (MAX_PN_WINDOW / 2 - offset)); + pn_win[1] >>= offset; -+ -+ } else if (offset >= MAX_PN_WINDOW/2 && offset < MAX_PN_WINDOW) { -+ pn_win[0] = pn_win[1] >> (offset - MAX_PN_WINDOW/2); ++ } else if (offset >= MAX_PN_WINDOW / 2 && offset < MAX_PN_WINDOW) { ++ pn_win[0] = pn_win[1] >> (offset - MAX_PN_WINDOW / 2); + pn_win[1] = 0; -+ + } else { + pn_win[0] = 0; + pn_win[1] = 0; + } -+ return offset; -+} + ++ return offset; ++} + +unsigned long long hal_check_dup_pn(unsigned long long *pn_win, unsigned int repcnt_diff) +{ -+ if (repcnt_diff > 0 && repcnt_diff <= MAX_PN_WINDOW/2) { ++ if (repcnt_diff > 0 && repcnt_diff <= MAX_PN_WINDOW / 2) { + return pn_win[0] & (1 << (repcnt_diff - 1)); -+ } else if (repcnt_diff > MAX_PN_WINDOW/2 && repcnt_diff <= MAX_PN_WINDOW) { -+ return pn_win[1] & (1 << (repcnt_diff - MAX_PN_WINDOW/2 - 1)); ++ } else if (repcnt_diff > MAX_PN_WINDOW / 2 && repcnt_diff <= MAX_PN_WINDOW) { ++ return pn_win[1] & (1 << (repcnt_diff - MAX_PN_WINDOW / 2 - 1)); + } else { + return 0; + } +} + -+ -+unsigned char hal_chk_replay_cnt(struct hal_private *hal_priv,HW_RxDescripter_bit *RxPrivHdr) ++unsigned char hal_chk_replay_cnt(struct hal_private *hal_priv, HW_RxDescripter_bit *RxPrivHdr) +{ + int staid = 0; + unsigned char wnet_vif_id = 0; + unsigned char *PN = NULL; + unsigned long long *repcnt_my[2]; + unsigned long long *repcnt_rx ; -+ int ret =0; ++ int ret = 0; + struct aml_hal_call_backs *AmlmS_opt = hal_get_drv_func(); + HW_RxDescripter_bit *RxPrivHdr_bit = (HW_RxDescripter_bit *)RxPrivHdr; + struct drv_private *drv_priv = (struct drv_private *)hal_priv->drv_priv; @@ -63302,14 +63780,15 @@ index 000000000000..8e11ef3dbdf0 + return 1; + + ASSERT(AmlmS_opt->get_stationid != NULL); -+ wnet_vif_id = RxPrivHdr_bit->RxA1match_id;//address 1 always be rx_end's mac address. ++ wnet_vif_id = RxPrivHdr_bit->RxA1match_id; /* address 1 always be rx_end's mac address. */ + ret = AmlmS_opt->get_stationid(hal_priv->drv_priv, &RxPrivHdr->data[10], wnet_vif_id, &staid); + + if (ret < 0) + { -+ //dump_memory_internel(&RxPrivHdr->data[10],6); -+ //PRINT("staid %x error !\n", staid); -+ //if we are sta, we should disconnect from the counterpart. ++ /* dump_memory_internal(&RxPrivHdr->data[10],6); ++ * PRINT("staid %x error !\n", staid); ++ * if we are sta, we should disconnect from the counterpart. ++ */ + return false; + } + wnet_vif = drv_priv->drv_wnet_vif_table[wnet_vif_id]; @@ -63322,7 +63801,7 @@ index 000000000000..8e11ef3dbdf0 + case RX_PHY_CCMP: + repcnt_my[is_group] = (unsigned long long *)PN; + repcnt_rx = (unsigned long long *)RxPrivHdr->PN; -+ //not require "+1", just require increase ++ /* not require "+1", just require increase */ + if (*repcnt_my[is_group] < *repcnt_rx) { + if (*repcnt_my[is_group] == 0 && *repcnt_rx > 0) { + *repcnt_my[is_group] = *repcnt_rx - 1; @@ -63345,14 +63824,14 @@ index 000000000000..8e11ef3dbdf0 + repcnt_diff = (int)(*repcnt_rx - *repcnt_my[is_group]); + } + -+ if (repcnt_diff > 0 && repcnt_diff <= MAX_PN_WINDOW/2) { ++ if (repcnt_diff > 0 && repcnt_diff <= MAX_PN_WINDOW / 2) { + wnet_vif->pn_window[is_group][0] |= (1 << (repcnt_diff - 1)); + if (repcnt_diff == 1) { + offset = hal_set_pn_win(wnet_vif->pn_window[is_group]); + *repcnt_my[is_group] += offset; + } -+ } else if (repcnt_diff > MAX_PN_WINDOW/2 && repcnt_diff <= MAX_PN_WINDOW){ -+ wnet_vif->pn_window[is_group][1] |= (1 << (repcnt_diff - MAX_PN_WINDOW/2 - 1)); ++ } else if (repcnt_diff > MAX_PN_WINDOW / 2 && repcnt_diff <= MAX_PN_WINDOW){ ++ wnet_vif->pn_window[is_group][1] |= (1 << (repcnt_diff - MAX_PN_WINDOW / 2 - 1)); + } + } + @@ -63363,10 +63842,11 @@ index 000000000000..8e11ef3dbdf0 + } + break; + case RX_PHY_WAPI: -+ if (hal_wpi_chk_pn_increase(RxPrivHdr->PN,PN) == true) { -+ memcpy(PN,RxPrivHdr->PN,MAX_PN_LEN); ++ if (hal_wpi_chk_pn_increase(RxPrivHdr->PN, PN) == true) { ++ memcpy(PN, RxPrivHdr->PN, MAX_PN_LEN); + return true; + } ++ + return false; + break; + case RX_PHY_WEP64: @@ -63374,6 +63854,7 @@ index 000000000000..8e11ef3dbdf0 + default: + break; + } ++ + return true; +} + @@ -63381,7 +63862,7 @@ index 000000000000..8e11ef3dbdf0 +#if defined (HAL_FPGA_VER) +{ + HW_RxDescripter_bit *RxPrivHdr_bit; -+ unsigned char wnet_vif_id = 0; ++ unsigned char wnet_vif_id; + static unsigned char print_count = 0; + unsigned char pkt_drop = 0; + @@ -63396,23 +63877,31 @@ index 000000000000..8e11ef3dbdf0 + if (wnet_vif_id >= WIFI_MAX_VID) + { + PRINT("hal_soft_rx_cs wnet_vif_id %d \n", wnet_vif_id); -+ //dump_memory_internel(RxPrivHdr_bit->data, 32); ++ /* dump_memory_internal(RxPrivHdr_bit->data, 32); */ + os_skb_free(skb); + return; + } + -+ if ((RxPrivHdr_bit->mic_err) || (RxPrivHdr_bit->keymiss_err) || (RxPrivHdr_bit->icv_err) -+ || (hal_priv->hal_call_back->intr_rx_handle == NULL)) ++ if ((RxPrivHdr_bit->mic_err) || (RxPrivHdr_bit->keymiss_err) || ++ (RxPrivHdr_bit->icv_err) || (hal_priv->hal_call_back->intr_rx_handle == NULL)) + { + if (!(print_count++ % 100)) -+ PRINT("mic_err = %d, keymiss_err %d wnet_vif_id %d\n",RxPrivHdr_bit->mic_err, RxPrivHdr_bit->keymiss_err,wnet_vif_id); ++ PRINT("mic_err = %d, keymiss_err %d wnet_vif_id %d\n", ++ RxPrivHdr_bit->mic_err, RxPrivHdr_bit->keymiss_err, ++ wnet_vif_id); + + if (RxPrivHdr_bit->mic_err) { -+ pkt_drop = hal_priv->hal_call_back->pmf_encrypt_pkt_handle(hal_priv->drv_priv, skb, RxPrivHdr_bit->RxRSSI_ant0, -+ RxPrivHdr_bit->RxRate, RxPrivHdr_bit->RxChannel, RxPrivHdr_bit->aggregation, wnet_vif_id,RxPrivHdr_bit->key_id); -+ -+ hal_priv->hal_call_back->mic_error_event(hal_priv->drv_priv,RxPrivHdr_bit->data, -+ WIFI_ADDR2(RxPrivHdr_bit->data),wnet_vif_id); ++ pkt_drop = hal_priv->hal_call_back->pmf_encrypt_pkt_handle(hal_priv->drv_priv, ++ skb, RxPrivHdr_bit->RxRSSI_ant0, ++ RxPrivHdr_bit->RxRate, ++ RxPrivHdr_bit->RxChannel, ++ RxPrivHdr_bit->aggregation, ++ wnet_vif_id,RxPrivHdr_bit->key_id); ++ ++ hal_priv->hal_call_back->mic_error_event(hal_priv->drv_priv, ++ RxPrivHdr_bit->data, ++ WIFI_ADDR2(RxPrivHdr_bit->data), ++ wnet_vif_id); + } else { + pkt_drop = 1; + } @@ -63435,8 +63924,8 @@ index 000000000000..8e11ef3dbdf0 +#endif + } + -+ if (RxPrivHdr_bit->RxTcpCSUM_err && RxPrivHdr_bit->RxTcpCSUMCalculated -+ && RxPrivHdr_bit->RxIPCSUM_err && RxPrivHdr_bit->RxIPCSUMCalculated) ++ if (RxPrivHdr_bit->RxTcpCSUM_err && RxPrivHdr_bit->RxTcpCSUMCalculated && ++ RxPrivHdr_bit->RxIPCSUM_err && RxPrivHdr_bit->RxIPCSUMCalculated) + { + skb->ip_summed = CHECKSUM_UNNECESSARY; + } @@ -63445,50 +63934,58 @@ index 000000000000..8e11ef3dbdf0 + skb->ip_summed = CHECKSUM_NONE; + } + -+ // push to upper layer -+ hal_priv->hal_call_back->intr_rx_handle(hal_priv->drv_priv, skb, RxPrivHdr_bit->RxRSSI_ant0, -+ RxPrivHdr_bit->RxRate, RxPrivHdr_bit->Channel_BW, RxPrivHdr_bit->RxChannel, RxPrivHdr_bit->aggregation, wnet_vif_id,RxPrivHdr_bit->key_id); ++ /* push to upper layer */ ++ hal_priv->hal_call_back->intr_rx_handle(hal_priv->drv_priv, skb, ++ RxPrivHdr_bit->RxRSSI_ant0, ++ RxPrivHdr_bit->RxRate, ++ RxPrivHdr_bit->Channel_BW, ++ RxPrivHdr_bit->RxChannel, ++ RxPrivHdr_bit->aggregation, ++ wnet_vif_id,RxPrivHdr_bit->key_id); + } +} +#elif defined (HAL_SIM_VER) +{ + HW_RxDescripter_bit *RxPrivHdr_bit; + RxPrivHdr_bit = (HW_RxDescripter_bit *)OS_SKBBUF_DATA(skb); ++ + if (STA2_VMAC1_RX_FRAME_DUMP) { + hal_show_rxframe(RxPrivHdr_bit); + } ++ + OS_SKBBUF_PULL(skb,sizeof(HW_RxDescripter_bit)); -+ if ((RxPrivHdr_bit->mic_err) -+ ||(RxPrivHdr_bit->keymiss_err) -+ ||(RxPrivHdr_bit->icv_err) -+ ||(hal_priv->hal_call_back->intr_rx_handle == NULL)) { ++ ++ if ((RxPrivHdr_bit->mic_err) || ++ (RxPrivHdr_bit->keymiss_err) || ++ (RxPrivHdr_bit->icv_err) || ++ (hal_priv->hal_call_back->intr_rx_handle == NULL)) { + Test_Done(0); + + if (RxPrivHdr_bit->mic_err) { -+ PRINT("%s RxLength= 0x%x, mic_err, dump\n",__FUNCTION__,RxPrivHdr_bit->RxLength); -+ dump_memory_internel(RxPrivHdr_bit->data, RxPrivHdr_bit->RxLength); ++ PRINT("%s RxLength= 0x%x, mic_err, dump\n", ++ __FUNCTION__, RxPrivHdr_bit->RxLength); ++ dump_memory_internal(RxPrivHdr_bit->data, RxPrivHdr_bit->RxLength); + } + OS_SKBBUF_FREE(skb); + return; -+ } -+ else { ++ } else { + unsigned short frame_control = READ_16L((unsigned char *)RxPrivHdr_bit->data); +#ifdef BEACON_TX_TEST + if ((frame_control & 0xfc) == MAC_FCTRL_BEACON) + { -+ /*counter frames without beacon frame*/ ++ /* counter frames without beacon frame */ + PRINT("Host receive beacon!\n"); + } + else +#endif +#if (STA1_VMAC0_SEND_TYPE == TYPE_PS_NULLDATA_TX || STA1_VMAC0_SEND_TYPE == TYPE_PS_PSPOLL_TX) -+ /*STA1 acts as STA, so only STA1 can send ps-poll. */ ++ /* STA1 acts as STA, so only STA1 can send ps-poll. */ + if (hal_mac_frame_type(frame_control, MAC_FCTRL_PSPOLL)) + { + PRINT("Host receive ps poll++++\n"); + } -+ else if (hal_mac_frame_type(frame_control, MAC_FCTRL_NULL_FUNCTION) -+ || hal_mac_frame_type(frame_control, MAC_FCTRL_QOS_NULL)) ++ else if (hal_mac_frame_type(frame_control, MAC_FCTRL_NULL_FUNCTION) || ++ hal_mac_frame_type(frame_control, MAC_FCTRL_QOS_NULL)) + { +#ifdef DOT11_PS_TEST + if (frame_control & FRAME_CONTROL_POWER_MANAGEMENT) @@ -63509,16 +64006,16 @@ index 000000000000..8e11ef3dbdf0 + } + +#if (STA1_VMAC1_PARAM2 == 1) -+ if (((rxframenum == STA2_VMAC1_SEND_FRAME_NUM)) -+ &&(STA2_VMAC1_SEND_FRAME_NUM != 99999)) ++ if ((rxframenum == STA2_VMAC1_SEND_FRAME_NUM) && ++ (STA2_VMAC1_SEND_FRAME_NUM != 99999)) + +#else + if (STA2_VMAC1_SEND_FRAME_NUM < STA1_VMAC0_AGG_NUM) { + PRINT("frame num < agg frame num : frame num is not enough for agg frame num\n"); + Test_Done(0); + } -+ if (((rxframenum == STA2_VMAC1_SEND_FRAME_NUM)) -+ &&(STA2_VMAC1_SEND_FRAME_NUM != 99999)) ++ if ((rxframenum == STA2_VMAC1_SEND_FRAME_NUM) && ++ (STA2_VMAC1_SEND_FRAME_NUM != 99999)) +#endif + { + Test_Done(1); @@ -63529,55 +64026,56 @@ index 000000000000..8e11ef3dbdf0 + } +#endif + if (RxPrivHdr_bit->data[1]&IEEE80211_FC1_WEP) { -+ //dump_memory_internel(RxPrivHdr_bit->data, RxPrivHdr_bit->RxLength); ++ /* dump_memory_internal(RxPrivHdr_bit->data, RxPrivHdr_bit->RxLength); */ + RxPrivHdr_bit->data[1] &= ~IEEE80211_FC1_WEP; + } + if (RxPrivHdr_bit->RxDecryptType != RX_PHY_NOWEP) { + } -+ if (STA2_TCPIP_CHECKSUM ) { ++ if (STA2_TCPIP_CHECKSUM) { + if (RxPrivHdr_bit->RxTcpCSUM_err && RxPrivHdr_bit->RxTcpCSUMCalculated) { -+ PRINT(">RxStatus = TCPCHSUM ERROR !\n"); -+ Test_Done(0); -+ } -+ else { -+ PRINT(">RxStatus = 0x%x TCPCHSUM ok \n"); ++ PRINT(">RxStatus = TCPCHSUM ERROR !\n"); ++ Test_Done(0); ++ } else { ++ PRINT(">RxStatus = 0x%x TCPCHSUM ok \n"); + } + -+ if (RxPrivHdr_bit->RxIPCSUM_err && RxPrivHdr_bit->RxIPCSUMCalculated) { -+ PRINT(">RxStatus = 0x%x IPCHSUM ERROR \n"); -+ Test_Done(0); -+ } -+ else { -+ PRINT(">RxStatus = 0x%x IPCHSUM ok \n"); ++ if (RxPrivHdr_bit->RxIPCSUM_err && RxPrivHdr_bit->RxIPCSUMCalculated) { ++ PRINT(">RxStatus = 0x%x IPCHSUM ERROR \n"); ++ Test_Done(0); ++ } else { ++ PRINT(">RxStatus = 0x%x IPCHSUM ok \n"); + } + } -+ hal_priv->hal_call_back->intr_rx_handle( hal_priv->drv_priv, -+ skb,RxPrivHdr_bit->RxRSSI_ant0, -+ RxPrivHdr_bit->RxRate, -+ RxPrivHdr_bit->Channel_BW, -+ RxPrivHdr_bit->RxChannel, RxPrivHdr_bit->aggregation, -+ RxPrivHdr_bit->RxA1match_id,RxPrivHdr_bit->key_id ); ++ hal_priv->hal_call_back->intr_rx_handle(hal_priv->drv_priv, skb, ++ RxPrivHdr_bit->RxRSSI_ant0, ++ RxPrivHdr_bit->RxRate, ++ RxPrivHdr_bit->Channel_BW, ++ RxPrivHdr_bit->RxChannel, ++ RxPrivHdr_bit->aggregation, ++ RxPrivHdr_bit->RxA1match_id, ++ RxPrivHdr_bit->key_id ); + } +} +#endif + -+void hal_write_word(unsigned int addr,unsigned int data) ++static void hal_write_word(unsigned int addr,unsigned int data) +{ -+ struct hw_interface* hif = hif_get_hw_interface(); ++ struct hw_interface *hif = hif_get_hw_interface(); + +#if 1 + /* just for power save debug */ + if ((addr & 0xff000000) == 0x11000000) -+ hif->hif_ops.hi_bottom_write8(SDIO_FUNC1, (addr & ~0xff000000), (unsigned char)data); ++ hif->hif_ops.hi_bottom_write8(SDIO_FUNC1, (addr & ~0xff000000), ++ (unsigned char)data); + else +#endif + hif->hif_ops.hi_write_word(addr, data); +} + -+unsigned int hal_read_word(unsigned int addr) ++static unsigned int hal_read_word(unsigned int addr) +{ -+ struct hw_interface* hif = hif_get_hw_interface(); -+ unsigned int regdata = 0; ++ struct hw_interface *hif = hif_get_hw_interface(); ++ unsigned int regdata; + +#if 1 + /* just for power save debug */ @@ -63586,43 +64084,45 @@ index 000000000000..8e11ef3dbdf0 + else +#endif + regdata = hif->hif_ops.hi_read_word(addr); ++ + return regdata; +} + -+void hal_bt_write_word(unsigned int addr,unsigned int data) ++static void hal_bt_write_word(unsigned int addr,unsigned int data) +{ -+ struct hw_interface* hif = hif_get_hw_interface(); ++ struct hw_interface *hif = hif_get_hw_interface(); ++ + hif->hif_ops.bt_hi_write_word(addr, data); +} + -+unsigned int hal_bt_read_word(unsigned int addr) ++static unsigned int hal_bt_read_word(unsigned int addr) +{ -+ struct hw_interface* hif = hif_get_hw_interface(); ++ struct hw_interface *hif = hif_get_hw_interface(); ++ + return hif->hif_ops.bt_hi_read_word(addr); +} + -+ -+void hal_pt_rx_start(unsigned int qos) ++static void hal_pt_rx_start(unsigned int qos) +{ -+ struct hw_interface* hif = hif_get_hw_interface(); ++ struct hw_interface *hif = hif_get_hw_interface(); ++ + hif->hif_ops.hif_pt_rx_start(qos); +} + -+void hal_pt_rx_stop(void) ++static void hal_pt_rx_stop(void) +{ -+ struct hw_interface* hif = hif_get_hw_interface(); -+ hif->hif_ops.hif_pt_rx_stop(); ++ struct hw_interface *hif = hif_get_hw_interface(); ++ ++ hif->hif_ops.hif_pt_rx_stop(); +} + +unsigned char hal_wake_fw_req(void) +{ + struct hal_private * halpriv = hal_get_priv(); -+ unsigned char fw_ps_st = PMU_PWR_OFF; -+ unsigned char fw_sleep = 0, host_sleep_req = 0; ++ unsigned char host_sleep_req = 0; + unsigned int loop = 0, wake_flag = 0; +#ifdef PROJECT_W1 + struct hw_interface* hif = hif_get_hw_interface(); -+ unsigned char host_req_status = 0; +#endif + + POWER_BEGIN_LOCK(); @@ -63635,7 +64135,7 @@ index 000000000000..8e11ef3dbdf0 + if (atomic_read(&halpriv->drv_suspend_cnt) != 0) + { + POWER_END_LOCK(); -+ printk("%s:%d, suspending, does not wake, fw st %d\n", __func__, __LINE__, ++ pr_debug("%s:%d, suspending, does not wake, fw st %d\n", __func__, __LINE__, + halpriv->hal_fw_ps_status); + return 0; + } @@ -63643,12 +64143,17 @@ index 000000000000..8e11ef3dbdf0 + // check fw power save status + while (halpriv->hal_fw_ps_status != HAL_FW_IN_ACTIVE) + { ++ unsigned char host_req_status; ++ unsigned char host_sleep_req; ++ unsigned char fw_ps_st; ++ unsigned char fw_sleep; ++ + fw_ps_st = halpriv->hal_ops.hal_get_fw_ps_status(); + fw_sleep = ((fw_ps_st & FW_SLEEP) != 0) ? 1 : 0; + host_req_status = hif->hif_ops.hi_bottom_read8(SDIO_FUNC1, RG_SDIO_PMU_HOST_REQ); + host_sleep_req = ((host_req_status & HOST_SLEEP_REQ) != 0) ? 1 : 0; + -+ //printk("fw ps st 0x%x, fw_sleep 0x%x, host_sleep_req 0x%x\n", fw_ps_st, fw_sleep, host_sleep_req); ++ //pr_debug("fw ps st 0x%x, fw_sleep 0x%x, host_sleep_req 0x%x\n", fw_ps_st, fw_sleep, host_sleep_req); + // fw/pmu st + fw_ps_st = fw_ps_st & 0xF; + if (fw_ps_st != PMU_ACT_MODE) @@ -63697,7 +64202,7 @@ index 000000000000..8e11ef3dbdf0 + { + POWER_END_LOCK(); + host_wake_w1_fail_cnt++; -+ printk("fw ps st 0x%x, fw_sleep 0x%x, host_sleep_req 0x%x\n", fw_ps_st, fw_sleep, host_sleep_req); ++ pr_debug("fw ps st 0x%x, fw_sleep 0x%x, host_sleep_req 0x%x\n", fw_ps_st, fw_sleep, host_sleep_req); + return 0; + } + } @@ -63710,13 +64215,15 @@ index 000000000000..8e11ef3dbdf0 +{ + struct hal_private * halpriv = hal_get_priv(); + int loop_count = 0; -+ unsigned int fw_ps_st = 0; -+ unsigned int host_sleep_req = 0; -+ unsigned int fw_sleep = 0; + + POWER_BEGIN_LOCK(); ++ + while (halpriv->hal_fw_ps_status == HAL_FW_IN_SLEEP) + { ++ unsigned int fw_ps_st; ++ unsigned int fw_sleep; ++ unsigned int host_sleep_req; ++ + POWER_END_LOCK(); + fw_ps_st = halpriv->hal_ops.hal_get_fw_ps_status(); + fw_sleep = ((fw_ps_st & FW_SLEEP) != 0) ? 1 : 0; @@ -63731,7 +64238,7 @@ index 000000000000..8e11ef3dbdf0 +#endif + ) + { -+ //printk("%s:%d, fw is not active mode, st = 0x%x\n", __func__, __LINE__, fw_ps_st); ++ /* pr_debug("%s:%d, fw is not active mode, st = 0x%x\n", __func__, __LINE__, fw_ps_st); */ + } + else + { @@ -63743,6 +64250,7 @@ index 000000000000..8e11ef3dbdf0 + } + POWER_BEGIN_LOCK(); + } ++ + POWER_END_LOCK(); + return 1; +} @@ -63750,7 +64258,7 @@ index 000000000000..8e11ef3dbdf0 +unsigned char hal_get_fw_ps_status(void) +{ + struct hw_interface* hif = hif_get_hw_interface(); -+ unsigned char fw_ps_st = 0; ++ unsigned char fw_ps_st; + + fw_ps_st = hif->hif_ops.hi_bottom_read8(SDIO_FUNC1, RG_SDIO_PMU_STATUS) & 0xFF; + return fw_ps_st; @@ -63769,7 +64277,7 @@ index 000000000000..8e11ef3dbdf0 + struct hw_interface* hif = hif_get_hw_interface(); + unsigned char tmp = 0; + -+ // clear ++ /* clear */ + tmp = hif->hif_ops.hi_bottom_read8(SDIO_FUNC1, RG_SDIO_PMU_WAKE); + hif->hif_ops.hi_bottom_write8(SDIO_FUNC1, RG_SDIO_PMU_WAKE, (tmp & ~BIT(0))); + return 0; @@ -63862,10 +64370,10 @@ index 000000000000..8e11ef3dbdf0 + hal_priv->hal_ops.phy_get_rw_ptr = phy_get_rw_ptr; + hal_priv->hal_ops.phy_get_tsf = phy_get_tsf; + -+ // beamforming ++ /* beamforming */ + hal_priv->hal_ops.phy_set_bmfm_info = phy_set_bmfm_info; + /*enable or disable WIFI/BT coexist*/ -+ hal_priv->hal_ops.phy_set_coexist_en = phy_set_coexist_en; ++ hal_priv->hal_ops.phy_set_coexist_en = phy_set_coexist_en; + + hal_priv->hal_ops.phy_set_coexist_max_miss_bcn = phy_set_coexist_max_miss_bcn; + hal_priv->hal_ops.phy_set_coexist_req_timeslice_timeout_value = phy_set_coexist_req_timeslice_timeout_value; @@ -63961,12 +64469,11 @@ index 000000000000..8e11ef3dbdf0 + host_suspend_req = NULL; + host_resume_req = NULL; +#endif -+ +} + +int hal_set_suspend(unsigned char enable) +{ -+ struct hw_interface* hif = hif_get_hw_interface(); ++ struct hw_interface *hif = hif_get_hw_interface(); + + if (hif->hif_ops.hif_suspend != NULL) + return hif->hif_ops.hif_suspend(enable); @@ -63974,9 +64481,10 @@ index 000000000000..8e11ef3dbdf0 + return -1; +} + -+struct aml_hal_call_backs *hal_get_drv_func(void) ++struct aml_hal_call_backs *hal_get_drv_func(void) +{ + struct hal_private *hal_priv = hal_get_priv(); ++ + return hal_priv->hal_call_back; +} + @@ -64002,93 +64510,105 @@ index 000000000000..8e11ef3dbdf0 +void hal_pn_win_init(enum aml_key_type type, unsigned char wnet_vif_id) +{ + unsigned int LoopCnt; -+ struct hal_private * hal_priv =hal_get_priv(); ++ struct hal_private *hal_priv = hal_get_priv(); + struct drv_private *drv_priv = (struct drv_private *)hal_priv->drv_priv; + struct wlan_net_vif *wnet_vif = drv_priv->drv_wnet_vif_table[wnet_vif_id]; ++ + for (LoopCnt = 0; LoopCnt < 2; LoopCnt++) { + wnet_vif->pn_window[type][LoopCnt] = 0; + } +} + -+void hal_urep_cnt_init(struct unicastReplayCnt *RepCnt,unsigned char encryType) ++void hal_urep_cnt_init(struct unicastReplayCnt *RepCnt, unsigned char encryType) +{ + unsigned int LoopCnt; ++ + if (encryType == WIFI_WPI) + { -+ unsigned char AP_upn[MAX_PN_LEN] = {0x37, 0x5c, 0x36, 0x5c, 0x36, 0x5c, 0x36, 0x5c, 0x36,0x5c, 0x36, 0x5c, 0x36, 0x5c, 0x36, 0x5c }; -+ unsigned char STA_upn[MAX_PN_LEN] = {0x36, 0x5c, 0x36, 0x5c, 0x36, 0x5c, 0x36, 0x5c, 0x36,0x5c, 0x36, 0x5c, 0x36, 0x5c, 0x36, 0x5c }; ++ unsigned char AP_upn[MAX_PN_LEN] = {0x37, 0x5c, 0x36, 0x5c, 0x36, ++ 0x5c, 0x36, 0x5c, 0x36, 0x5c, ++ 0x36, 0x5c, 0x36, 0x5c, 0x36, ++ 0x5c}; ++ unsigned char STA_upn[MAX_PN_LEN] = {0x36, 0x5c, 0x36, 0x5c, 0x36, ++ 0x5c, 0x36, 0x5c, 0x36, 0x5c, ++ 0x36, 0x5c, 0x36, 0x5c, 0x36, ++ 0x5c}; + + /* Tx replay counter init value = 1*/ + if (wifi_conf_mib.dot11CamMode == MODE_STA) + { -+ memcpy(&RepCnt->txPN[TX_UNICAST_REPCNT_ID][0],STA_upn,MAX_PN_LEN); ++ memcpy(&RepCnt->txPN[TX_UNICAST_REPCNT_ID][0], STA_upn, MAX_PN_LEN); + } + else + { -+ memcpy(&RepCnt->txPN[TX_UNICAST_REPCNT_ID][0],AP_upn,MAX_PN_LEN); ++ memcpy(&RepCnt->txPN[TX_UNICAST_REPCNT_ID][0], AP_upn, MAX_PN_LEN); + } + } + else + { -+ /* Tx replay counter init value = 1*/ ++ /* Tx replay counter init value = 1 */ + for (LoopCnt = 0; LoopCnt < MAX_TX_QUEUE; LoopCnt++) + { -+ memset(&RepCnt->txPN[LoopCnt][0],0,MAX_PN_LEN); -+ RepCnt->txPN[LoopCnt][0] =1; ++ memset(&RepCnt->txPN[LoopCnt][0], 0, MAX_PN_LEN); ++ RepCnt->txPN[LoopCnt][0] = 1; + } + } + for (LoopCnt = 0; LoopCnt < MAX_RX_QUEUE; LoopCnt++) + { -+ /* Rx replay counter init value = 0*/ ++ /* Rx replay counter init value = 0 */ + memset(&RepCnt->rxPN[LoopCnt][0], 0, MAX_PN_LEN); + } + +} + -+void hal_mrep_cnt_init(struct hal_private *halpriv,unsigned char wnet_vif_id,unsigned char encryType) ++void hal_mrep_cnt_init(struct hal_private *halpriv, unsigned char wnet_vif_id, ++ unsigned char encryType) +{ -+ struct multicastReplayCnt *mRepCnt = &halpriv->mRepCnt[wnet_vif_id]; ++ struct multicastReplayCnt *mRepCnt = &halpriv->mRepCnt[wnet_vif_id]; ++ + if (encryType == WIFI_WPI) + { -+ unsigned char gpn[16]= {0x36, 0x5c, 0x36, 0x5c, 0x36, 0x5c, 0x36, 0x5c, 0x36, 0x5c, 0x36, 0x5c, 0x36, 0x5c, 0x36, 0x5c}; ++ unsigned char gpn[16]= {0x36, 0x5c, 0x36, 0x5c, 0x36, 0x5c, ++ 0x36, 0x5c, 0x36, 0x5c, 0x36, 0x5c, ++ 0x36, 0x5c, 0x36, 0x5c}; + /* Tx replay counter init value = 1 */ -+ memcpy(&mRepCnt->txPN[0],gpn,MAX_PN_LEN); ++ memcpy(&mRepCnt->txPN[0], gpn, MAX_PN_LEN); + } + else + { -+ /* Tx replay counter init value = 1*/ -+ memset(&mRepCnt->txPN[0],0,MAX_PN_LEN); -+ mRepCnt->txPN[0] =1; ++ /* Tx replay counter init value = 1 */ ++ memset(&mRepCnt->txPN[0], 0, MAX_PN_LEN); ++ mRepCnt->txPN[0] = 1; + } -+ /* Rx replay counter init value = 0*/ ++ /* Rx replay counter init value = 0 */ + memset(&mRepCnt->rxPN[0], 0, MAX_PN_LEN); +} + -+void hal_wpi_pn_self_plus( unsigned long long *WpiPN ) ++void hal_wpi_pn_self_plus(unsigned long long *WpiPN) +{ -+ if ( WpiPN[0] == 0xFFFFFFFFFFFFFFFFull ) ++ if (WpiPN[0] == 0xFFFFFFFFFFFFFFFFull) + { -+ WpiPN[0] =0x0ull; -+ WpiPN[1] +=0x1ull; ++ WpiPN[0] = 0x0ull; ++ WpiPN[1] += 0x1ull; + } + else + { -+ WpiPN[0] +=0x1ull; ++ WpiPN[0] += 0x1ull; + } +} + -+void hal_wpi_pn_self_plus_plus( unsigned long long *WpiPN ) ++void hal_wpi_pn_self_plus_plus(unsigned long long *WpiPN) +{ + -+ if ( WpiPN[0] == 0xFFFFFFFFFFFFFFFFull ) ++ if (WpiPN[0] == 0xFFFFFFFFFFFFFFFFull) + { -+ WpiPN[0] =0x1ull; -+ WpiPN[1] +=0x1ull; ++ WpiPN[0] = 0x1ull; ++ WpiPN[1] += 0x1ull; + } -+ else if ( WpiPN[0] == 0xFFFFFFFFFFFFFFFEull ) ++ else if (WpiPN[0] == 0xFFFFFFFFFFFFFFFEull) + { -+ WpiPN[0] =0x0ull; -+ WpiPN[1] +=0x1ull; ++ WpiPN[0] = 0x0ull; ++ WpiPN[1] += 0x1ull; + } + else + { @@ -64096,10 +64616,11 @@ index 000000000000..8e11ef3dbdf0 + } +} + -+unsigned char hal_wpi_chk_pn_increase( unsigned char *RcvPN, unsigned char *SavedPn ) ++unsigned char hal_wpi_chk_pn_increase(unsigned char *RcvPN, unsigned char *SavedPn) +{ -+ int i=0; -+ for (i=(MAX_PN_LEN-1); i>=0; i--) ++ int i; ++ ++ for (i= (MAX_PN_LEN - 1); i >= 0; i--) + { + if (RcvPN[i]>SavedPn[i]) + { @@ -64109,28 +64630,27 @@ index 000000000000..8e11ef3dbdf0 + { + return false; + } -+ else -+ { -+ -+ } + } ++ + return false; +} + +void hal_free_txcmp_buf(struct hal_private *hal_priv) +{ -+ +#if defined (HAL_FPGA_VER) -+ FREE(hal_priv->txcompletestatus,"hal_priv->txcompletestatus"); ++ FREE(hal_priv->txcompletestatus, "hal_priv->txcompletestatus"); +#elif defined (HAL_SIM_VER) + FREE(hal_priv->txcompletestatus); +#endif +} ++ +unsigned char hal_alloc_txcmp_buf( struct hal_private *hal_priv) +{ -+ //alloc tx agg descriptor ++ /* alloc tx agg descriptor */ +#if defined (HAL_FPGA_VER) -+ hal_priv->txcompletestatus = (struct tx_complete_status *)ZMALLOC(sizeof(struct tx_complete_status), "hal_priv->txcompletestatus", GFP_KERNEL); ++ hal_priv->txcompletestatus = (struct tx_complete_status *)ZMALLOC(sizeof(struct tx_complete_status), ++ "hal_priv->txcompletestatus", ++ GFP_KERNEL); + if (hal_priv->txcompletestatus == NULL) + { + ERROR_DEBUG_OUT("alloc_err\n"); @@ -64214,7 +64734,7 @@ index 000000000000..8e11ef3dbdf0 + return 0; +} + -+unsigned char hal_get_free_tx_id_num(struct hal_private * hal_priv) ++static unsigned char hal_get_free_tx_id_num(struct hal_private * hal_priv) +{ + unsigned char bit_num = 0; + unsigned char i; @@ -64265,7 +64785,7 @@ index 000000000000..8e11ef3dbdf0 + } + else + { -+ printk("free id:%d, %lx, %lx\n", id, hal_priv->tx_frames_map[0], hal_priv->tx_frames_map[1]); ++ pr_debug("free id:%d, %lx, %lx\n", id, hal_priv->tx_frames_map[0], hal_priv->tx_frames_map[1]); + ret = -1; + } + COMMON_UNLOCK(); @@ -64298,7 +64818,7 @@ index 000000000000..8e11ef3dbdf0 + COMMON_UNLOCK(); + + //if (id == TXID_INVALID) -+ //printk("%s alloc fail\n", __func__); ++ //pr_err("%s alloc fail\n", __func__); + return id; +} + @@ -64401,7 +64921,7 @@ index 000000000000..8e11ef3dbdf0 + } +} + -+void hal_tx_complete(struct sk_buff * skb_buf) ++static void hal_tx_complete(struct sk_buff * skb_buf) +{ + if (aml_wifi_is_enable_rf_test() && (skb_buf != NULL)) { + os_skb_free(skb_buf); @@ -64426,7 +64946,7 @@ index 000000000000..8e11ef3dbdf0 + + if (hal_priv->bhaltxdrop || hal_priv->bhalPowerSave) { + if (print_cnt++ == 200) { -+ printk("%s bhaltxdrop:%d, bhalPowerSave:%d\n", __func__, hal_priv->bhaltxdrop, hal_priv->bhalPowerSave); ++ pr_debug("%s bhaltxdrop:%d, bhalPowerSave:%d\n", __func__, hal_priv->bhaltxdrop, hal_priv->bhalPowerSave); + } + return; + } @@ -64438,7 +64958,7 @@ index 000000000000..8e11ef3dbdf0 + POWER_END_LOCK(); + AML_TXLOCK_LOCK(); + if (print_cnt++ == 200) { -+ printk("%s %d hal_drv_ps_status:%02x\n", __func__, __LINE__, hal_priv->hal_drv_ps_status); ++ pr_debug("%s %d hal_drv_ps_status:%02x\n", __func__, __LINE__, hal_priv->hal_drv_ps_status); + } + return; + } @@ -64453,7 +64973,7 @@ index 000000000000..8e11ef3dbdf0 + AML_TXLOCK_LOCK(); + + if (print_cnt++ == 200) { -+ printk("%s %d hal_drv_ps_status:%02x\n", __func__, __LINE__, hal_priv->hal_drv_ps_status); ++ pr_debug("%s %d hal_drv_ps_status:%02x\n", __func__, __LINE__, hal_priv->hal_drv_ps_status); + } + return; + } @@ -64656,7 +65176,7 @@ index 000000000000..8e11ef3dbdf0 + return howmanypage(mpdulen+FW_TXDESC_DATAOFFSET, PAGE_LEN); +} + -+int hal_calc_block_in_mpdu (int mpdulen) ++static int hal_calc_block_in_mpdu (int mpdulen) +{ + return (mpdulen + (PAGE_LEN - 1)) / PAGE_LEN; +} @@ -64748,7 +65268,7 @@ index 000000000000..8e11ef3dbdf0 + frame_control = *(unsigned short *)(&pTxDPape->txdata[0]);//(frame_control & 0xff) == 0x88 + if (g_dbg_modules & AML_DBG_MODULES_HAL_TX) + { -+ //printk("pTxDescFiFo->SN:%04x, frame_control:%04x\n", pTxDescFiFo->SN, frame_control); ++ //pr_debug("pTxDescFiFo->SN:%04x, frame_control:%04x\n", pTxDescFiFo->SN, frame_control); + hal_show_txframe(pTxDPape); + } +#endif @@ -64889,7 +65409,7 @@ index 000000000000..8e11ef3dbdf0 + + COMMON_LOCK(); + if (hal_is_empty_tx_id(hal_priv) < 0) { -+ printk("set bhaltxdrop to 1, tx_frames_map:%lx, %lx, page:%d\n", ++ pr_debug("set bhaltxdrop to 1, tx_frames_map:%lx, %lx, page:%d\n", + hal_priv->tx_frames_map[0], hal_priv->tx_frames_map[1], hal_priv->txPageFreeNum); + hal_priv->bhaltxdrop = 1; + } @@ -64905,7 +65425,7 @@ index 000000000000..8e11ef3dbdf0 + if (!((pTxDescFiFo->pTxDPape->TxPriv.vid == vid) || (vid == 3))) { + id = hal_alloc_tx_id(hal_priv,pTxDescFiFo); + if (id == TXID_INVALID) { -+ printk("%s warning, please handle this situation!!!\n", __func__); ++ pr_warn("%s warning, please handle this situation!!!\n", __func__); + break;//how to handle this situation + } + pTxDescFiFo->pTxDPape->TxPriv.hostcallbackid= (unsigned char)id; @@ -64951,7 +65471,7 @@ index 000000000000..8e11ef3dbdf0 + + if (hal_priv->bhaltxdrop == 1) { + hal_priv->bhaltxdrop = 0; -+ printk("recover bhaltxdrop to 0, tx_frames_map:%lx, %lx, page:%d, vid:%d\n", ++ pr_debug("recover bhaltxdrop to 0, tx_frames_map:%lx, %lx, page:%d, vid:%d\n", + hal_priv->tx_frames_map[0], hal_priv->tx_frames_map[1], hal_priv->txPageFreeNum, vid); + } + return 0; @@ -65025,27 +65545,27 @@ index 000000000000..8e11ef3dbdf0 + struct hw_interface* hif = hif_get_hw_interface(); + struct _CO_SHARED_FIFO * tx_share_fifo = NULL; + -+ printk("\n--------hal statistic--------\n"); ++ pr_debug("\n--------hal statistic--------\n"); + + if((ctrl_code & STS_MOD_HAL) == STS_MOD_HAL) + { + if ((ctrl_code & STS_TYP_TX) == STS_TYP_TX) + { -+ printk("en_beacon[0]=%d\nen_beacon[1]=%d\n", hal_priv->sts_en_bcn[0], hal_priv->sts_en_bcn[1]); -+ printk("dis_beacon[0]=%d\ndis_beacon[1]=%d\n", hal_priv->sts_dis_bcn[0], hal_priv->sts_dis_bcn[1]); ++ pr_debug("en_beacon[0]=%d\nen_beacon[1]=%d\n", hal_priv->sts_en_bcn[0], hal_priv->sts_en_bcn[1]); ++ pr_debug("dis_beacon[0]=%d\ndis_beacon[1]=%d\n", hal_priv->sts_dis_bcn[0], hal_priv->sts_dis_bcn[1]); + -+ printk("hal:tx_free_page %d \n", hal_priv->txPageFreeNum); -+ printk("hal:tx_ok_num:%d, tx_fail_num:%d\n", hif->HiStatus.tx_ok_num, hif->HiStatus.tx_fail_num); ++ pr_debug("hal:tx_free_page %d \n", hal_priv->txPageFreeNum); ++ pr_debug("hal:tx_ok_num:%d, tx_fail_num:%d\n", hif->HiStatus.tx_ok_num, hif->HiStatus.tx_fail_num); +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,15,0) && !defined (LINUX_PLATFORM) -+ printk("hal:send_frm:%d, done_frm:%d, free_frm:%d\n", hif->HiStatus.Tx_Send_num, hif->HiStatus.Tx_Done_num, hif->HiStatus.Tx_Free_num); ++ pr_debug("hal:send_frm:%d, done_frm:%d, free_frm:%d\n", hif->HiStatus.Tx_Send_num, hif->HiStatus.Tx_Done_num, hif->HiStatus.Tx_Free_num); +#else -+ printk("hal:send_frm:%d, done_frm:%d, free_frm:%d\n", ++ pr_debug("hal:send_frm:%d, done_frm:%d, free_frm:%d\n", + atomic_read(&hif->HiStatus.Tx_Send_num), + atomic_read(&hif->HiStatus.Tx_Done_num), + atomic_read(&hif->HiStatus.Tx_Free_num)); +#endif -+ printk("hal:gpio irq cnt %d \n", hal_priv->gpio_irq_cnt); -+ printk("tx_cmp: tx_done_frm %d, tx_mng_frm %d, tx_page %d\n", ++ pr_debug("hal:gpio irq cnt %d \n", hal_priv->gpio_irq_cnt); ++ pr_debug("tx_cmp: tx_done_frm %d, tx_mng_frm %d, tx_page %d\n", + hal_priv->txcompletestatus->txdoneframecounter, + hal_priv->txcompletestatus->txmanageframecounter, + hal_priv->txcompletestatus->txpagecounter); @@ -65053,7 +65573,7 @@ index 000000000000..8e11ef3dbdf0 + for(i = 0; i < HAL_NUM_TX_QUEUES; i++) + { + tx_share_fifo = &hal_priv->txds_trista_fifo[i]; -+ printk("txds_trista_fifo[%d]: make %d, set %d, get %d\n", ++ pr_debug("txds_trista_fifo[%d]: make %d, set %d, get %d\n", + i, + CO_SharedFifoNbElt(tx_share_fifo, CO_TX_BUFFER_MAKE), + CO_SharedFifoNbElt(tx_share_fifo, CO_TX_BUFFER_SET), @@ -65062,7 +65582,7 @@ index 000000000000..8e11ef3dbdf0 + + for(i = 0; i < hirq_max_idx; i++) + { -+ printk("%s, %d\n", hirq_prt_info[i], hal_priv->sts_hirq[i]); ++ pr_debug("%s, %d\n", hirq_prt_info[i], hal_priv->sts_hirq[i]); + } + } + } @@ -65079,7 +65599,7 @@ index 000000000000..8e11ef3dbdf0 + + to_sdio = 0x00000000; + hi_clear_irq_status(to_sdio); -+ printk("%s(%d) hal_priv->bhalOpen 0x%x\n", __func__, __LINE__, hal_priv->bhalOpen); ++ pr_debug("%s(%d) hal_priv->bhalOpen 0x%x\n", __func__, __LINE__, hal_priv->bhalOpen); + return 1; +} + @@ -65128,6 +65648,8 @@ index 000000000000..8e11ef3dbdf0 + + drv_set_config((void *)drv_priv, CHIP_PARAM_RETRY_LIMIT, 100 << 8 | 100); + wifi_mac_set_tx_power_coefficient(drv_priv, NULL, drv_priv->drv_config.cfg_txpoweplan); ++ ++ drv_priv->net_ops->wifi_mac_rate_ratmod_detach(drv_priv); + drv_priv->net_ops->wifi_mac_rate_ratmod_attach(drv_priv); + + drv_rate_setup(drv_priv, WIFINET_MODE_11GNAC); @@ -65173,7 +65695,7 @@ index 000000000000..8e11ef3dbdf0 + hal_priv->bhalProbelok = 1; + hal_priv->beaconaddr[0]=0; + hal_priv->beaconaddr[1]=0; -+ printk("%s(%d) hal_priv->bhalOpen 0x%x\n", __func__, __LINE__, hal_priv->bhalOpen); ++ pr_debug("%s(%d) hal_priv->bhalOpen 0x%x\n", __func__, __LINE__, hal_priv->bhalOpen); + return true; + +__exit_err: @@ -65230,13 +65752,13 @@ index 000000000000..8e11ef3dbdf0 + unsigned char chip_id_buf[23]; + + chip_id_l = efuse_manual_read(CHIP_ID_EFUASE_L); -+ printk("efuse addr:%08x, chip_id is :%08x\n", CHIP_ID_EFUASE_L, chip_id_l); ++ pr_debug("efuse addr:%08x, chip_id is :%08x\n", CHIP_ID_EFUASE_L, chip_id_l); + chip_id_h = efuse_manual_read(CHIP_ID_EFUASE_H); -+ printk("efuse addr:%08x, chip_id is :%08x\n", CHIP_ID_EFUASE_H, chip_id_h); ++ pr_debug("efuse addr:%08x, chip_id is :%08x\n", CHIP_ID_EFUASE_H, chip_id_h); + + sprintf(chip_id_buf, CHIP_ID_F, chip_id_h & 0xffff, chip_id_l); + if (aml_store_to_file(WIFIMAC_PATH, chip_id_buf, strlen(chip_id_buf)) > 0) { -+ printk("write the chip_id to wifimac.txt \n"); ++ pr_debug("write the chip_id to wifimac.txt \n"); + ret = true; + } +#endif @@ -65805,7 +66327,7 @@ index 000000000000..8e11ef3dbdf0 + /* free skb allocated by hal*/ + if (hal_free_tx_id(hal_priv, txstatus, &callback, &queue_id) < 0) + { -+ printk("free tx_id error \n"); ++ pr_err("free tx_id error \n"); + tx_status_node_free(txok_status_node,txok_status_list); + txok_status_node = NULL; + continue; @@ -65825,7 +66347,7 @@ index 000000000000..8e11ef3dbdf0 + } + } + -+ printk("%s(%d) =====> exit TXOK Thread <=====\n",__func__,__LINE__); ++ pr_debug("%s(%d) =====> exit TXOK Thread <=====\n",__func__,__LINE__); + WAKE_LOCK_DESTROY(hal_priv, WAKE_LOCK_TXOK); +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0) + complete_and_exit(&hal_priv->txok_thread_completion, 0); @@ -65863,7 +66385,7 @@ index 000000000000..8e11ef3dbdf0 + sched_set_fifo(current); +#endif + -+ printk("%s(%d) =====creat thread hal_rx_thread<=====\n",__func__,__LINE__); ++ pr_debug("%s(%d) =====creat thread hal_rx_thread<=====\n",__func__,__LINE__); + + WAKE_LOCK_INIT(hal_priv,WAKE_LOCK_RX,"rx_proc amlwifi"); + while (!hal_priv->rx_thread_quit) @@ -65910,7 +66432,7 @@ index 000000000000..8e11ef3dbdf0 + { + /*if RxLength error, discard all data in host rx fifo*/ + rx_fifo_fdh = rx_fifo_fdt; -+ printk("%s(%d)(RxLength:%d,rx_fifo_total_len%d)\n", __func__,__LINE__, ++ pr_debug("%s(%d)(RxLength:%d,rx_fifo_total_len%d)\n", __func__,__LINE__, + pVRxDesc->RxLength,rx_fifo_total_len); + continue; + } @@ -65926,7 +66448,7 @@ index 000000000000..8e11ef3dbdf0 + skb = os_skb_alloc(pVRxDesc->RxLength + RX_PRIV_HDR_LEN); + if (skb == NULL) + { -+ printk("Couldn't allocate RX frame"); ++ pr_err("Couldn't allocate RX frame"); + break; + } + @@ -65967,7 +66489,7 @@ index 000000000000..8e11ef3dbdf0 + WAKE_UNLOCK(hal_priv, WAKE_LOCK_RX); + } + -+ printk("%s(%d) =====> exit RX Thread <=====\n",__func__,__LINE__); ++ pr_debug("%s(%d) =====> exit RX Thread <=====\n",__func__,__LINE__); + WAKE_LOCK_DESTROY(hal_priv, WAKE_LOCK_RX); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) + kthread_complete_and_exit(&hal_priv->rx_thread_completion, 0); @@ -66046,7 +66568,6 @@ index 000000000000..8e11ef3dbdf0 + init_completion(&hal_priv->txok_thread_completion); + hal_priv->txok_thread_quit = 1; + up(&hal_priv->txok_thread_sem); -+ kthread_stop(hal_priv->txok_thread); + wait_for_completion(&hal_priv->txok_thread_completion); + hal_priv->txok_thread =0; + } @@ -66056,7 +66577,6 @@ index 000000000000..8e11ef3dbdf0 + init_completion(&hal_priv->rx_thread_completion); + hal_priv->rx_thread_quit = 1; + up(&hal_priv->rx_thread_sem); -+ kthread_stop(hal_priv->rx_thread); + wait_for_completion(&hal_priv->rx_thread_completion); + hal_priv->rx_thread =0; + } @@ -66066,7 +66586,6 @@ index 000000000000..8e11ef3dbdf0 + init_completion(&hal_priv->work_thread_completion); + hal_priv->work_thread_quit = 1; + up(&hal_priv->work_thread_sem); -+ kthread_stop(hal_priv->work_thread); + wait_for_completion(&hal_priv->work_thread_completion); + hal_priv->work_thread =0; + } @@ -66076,7 +66595,6 @@ index 000000000000..8e11ef3dbdf0 + init_completion(&hal_priv->hi_irq_thread_completion); + hal_priv->hi_irq_thread_quit = 1; + up(&hal_priv->hi_irq_thread_sem); -+ kthread_stop(hal_priv->hi_irq_thread); + wait_for_completion(&hal_priv->hi_irq_thread_completion); + hal_priv->hi_irq_thread =0; + } @@ -66148,7 +66666,7 @@ index 000000000000..8e11ef3dbdf0 +{ + PRINT("%s+++\n", __FUNCTION__); + PRINT("%s dump rx PN\n", __FUNCTION__); -+ dump_memory_internel((unsigned char *)RxPrivHdr->PN, 16); ++ dump_memory_internal((unsigned char *)RxPrivHdr->PN, 16); + PRINT("RxRSSI_ant0=%d RxRSSI_ant1=%d\n", + RxPrivHdr->RxRSSI_ant0, RxPrivHdr->RxRSSI_ant1); + PRINT("RxChannel=%d\n", RxPrivHdr->RxChannel); @@ -66183,11 +66701,11 @@ index 000000000000..8e11ef3dbdf0 + void hal_show_rxframe (HW_RxDescripter_bit *RxPrivHdr) +{ + PRINT("%s dump HW_RxDescripter_bit, len=%zd\n", __FUNCTION__, RX_PRIV_HDR_LEN); -+ dump_memory_internel((unsigned char*)RxPrivHdr, RX_PRIV_HDR_LEN); ++ dump_memory_internal((unsigned char*)RxPrivHdr, RX_PRIV_HDR_LEN); + show_rxvector(RxPrivHdr); + + PRINT("%s dump body, len=%d(0x%x)\n", __FUNCTION__, RxPrivHdr->RxLength, RxPrivHdr->RxLength); -+ dump_memory_internel((unsigned char*)RxPrivHdr->data, RxPrivHdr->RxLength); ++ dump_memory_internal((unsigned char*)RxPrivHdr->data, RxPrivHdr->RxLength); + show_macframe((unsigned char *)RxPrivHdr->data, RxPrivHdr->RxLength); +} + @@ -66321,12 +66839,12 @@ index 000000000000..8e11ef3dbdf0 + PRINT("%s---\n", __FUNCTION__); +} + -+void show_tx_option (struct HW_TxOption *TxOption) ++static void show_tx_option (struct HW_TxOption *TxOption) +{ + PRINT("%s+++\n", __FUNCTION__); + PRINT("KeyIdex=%d\n", TxOption->KeyIdex); + PRINT("%s dump tx PN\n", __FUNCTION__); -+ dump_memory_internel((unsigned char *)TxOption->PN, 16); ++ dump_memory_internal((unsigned char *)TxOption->PN, 16); + PRINT("%s---\n", __FUNCTION__); +} + @@ -66343,9 +66861,9 @@ index 000000000000..8e11ef3dbdf0 + PRINT("%s---\n", __FUNCTION__); +} + -+void show_macframe (unsigned char *start, unsigned char len) ++void show_macframe(unsigned char *start, unsigned char len) +{ -+ unsigned char* cursor = (unsigned char *)start; ++ unsigned char *cursor = (unsigned char *)start; + unsigned short frame_control; + unsigned short duration; + unsigned char ra_mac_address[6], ta_mac_address[6], bssid_mac_address[6]; @@ -66379,9 +66897,9 @@ index 000000000000..8e11ef3dbdf0 + sequence = READ_16L(cursor); + cursor += 2; + PRINT("fragment number=%d, sequence number=%d(0x%x)\n", -+ sequence&SEQUENCE_CONTROL_FRAGMENT_MASK, -+ (sequence&SEQUENCE_CONTROL_SEQUENCE_MASK)>>SEQUENCE_CONTROL_SEQUENCE_SHIFT, -+ (sequence&SEQUENCE_CONTROL_SEQUENCE_MASK)>>SEQUENCE_CONTROL_SEQUENCE_SHIFT); ++ sequence & SEQUENCE_CONTROL_FRAGMENT_MASK, ++ (sequence & SEQUENCE_CONTROL_SEQUENCE_MASK) >> SEQUENCE_CONTROL_SEQUENCE_SHIFT, ++ (sequence & SEQUENCE_CONTROL_SEQUENCE_MASK) >> SEQUENCE_CONTROL_SEQUENCE_SHIFT); + + if ((frame_control & MAC_FCTRL_QOS_DATA) == MAC_FCTRL_QOS_DATA) + { @@ -66392,16 +66910,17 @@ index 000000000000..8e11ef3dbdf0 + + if ((len - (cursor - start)) >= 8) + { -+ if ((cursor[0]==0xaa) && (cursor[1]==0xaa) && (cursor[2]==0x03)) ++ if ((cursor[0] == 0xaa) && (cursor[1]== 0xaa) && ++ (cursor[2] == 0x03)) + { + PRINT("LLC SNAP\n"); + } -+ PRINT("LLC type =0x%x\n", READ_16B(cursor+6)); -+ if ((cursor[6]==0x08) && (cursor[7]==0x06)) ++ PRINT("LLC type =0x%x\n", READ_16B(cursor + 6)); ++ if ((cursor[6] == 0x08) && (cursor[7] == 0x06)) + { + PRINT("ARP\n"); + } -+ if ((cursor[6]==0x08) && (cursor[7]==0x00)) ++ if ((cursor[6] == 0x08) && (cursor[7] == 0x00)) + { + PRINT("IP\n"); + llc_type_ip = 1; @@ -66411,21 +66930,24 @@ index 000000000000..8e11ef3dbdf0 + + if ((llc_type_ip==1) && ((len - (cursor - start)) >= 20)) + { -+ unsigned char ipv4 = 0; -+ unsigned char ip_header_len = 0; -+ unsigned short fragmentation = 0; ++ unsigned char ipv4 = 0; ++ unsigned char ip_header_len; ++ unsigned short fragmentation; ++ + if (((cursor[0] & 0xf0)>>4) == 4) + { + ipv4 = 1; + } ++ + PRINT("IPv%d\n", ((cursor[0] & 0xf0)>>4)); + ip_header_len = (cursor[0] & 0x0f)*4; -+ PRINT("IP Header Length=%dB\n", (cursor[0] & 0x0f)*4); ++ PRINT("IP Header Length=%dB\n", (cursor[0] & 0x0f) * 4); + PRINT("IP type of service =0x%x\n", cursor[1]); -+ PRINT("IP Total Length=%dB\n", READ_16B(cursor+2)); -+ PRINT("IP ID=%d\n", READ_16B(cursor+4)); -+ fragmentation = READ_16B(cursor+6); -+ PRINT("IP fragmentation flags=0x%x offset=%d\n", ((fragmentation & 0xe000)>>13), fragmentation&0x1fff); ++ PRINT("IP Total Length=%dB\n", READ_16B(cursor + 2)); ++ PRINT("IP ID=%d\n", READ_16B(cursor + 4)); ++ fragmentation = READ_16B(cursor + 6); ++ PRINT("IP fragmentation flags=0x%x offset=%d\n", ((fragmentation & 0xe000) >> 13), ++ fragmentation & 0x1fff); + PRINT("IP Time to live =%d\n", cursor[8]); + PRINT("IP transfer protocol type=%d\n", cursor[9]); + if (cursor[9] == 6) @@ -66438,13 +66960,13 @@ index 000000000000..8e11ef3dbdf0 + udp = 1; + PRINT("UDP\n"); + } -+ PRINT("IP Header checksum=0x%x\n", READ_16B(cursor+10)); ++ PRINT("IP Header checksum=0x%x\n", READ_16B(cursor + 10)); + if (ipv4 == 1) + { + PRINT("Source IP address\n"); -+ IPv4_address_print(cursor+12); ++ IPv4_address_print(cursor + 12); + PRINT("Dest IP address\n"); -+ IPv4_address_print(cursor+16); ++ IPv4_address_print(cursor + 16); + } + if ((len - (cursor - start)) >= ip_header_len) + { @@ -66457,24 +66979,24 @@ index 000000000000..8e11ef3dbdf0 + } + } + -+ if ((tcp==1) && ((len - (cursor - start)) >= 20)) ++ if ((tcp == 1) && ((len - (cursor - start)) >= 20)) + { -+ unsigned char tcp_header_len = 0; -+ unsigned short tcp_flags = 0; ++ unsigned char tcp_header_len; ++ unsigned short tcp_flags; + + PRINT("TCP source port=%d\n", READ_16B(cursor)); -+ PRINT("TCP dest port=%d\n", READ_16B(cursor+2)); -+ PRINT("TCP sequence number=%u\n", READ_32B(cursor+4)); -+ PRINT("TCP ack number=%u\n", READ_32B(cursor+8)); -+ tcp_flags = READ_16B(cursor+12); -+ tcp_header_len = ((tcp_flags & 0xf000) >> 12)*4; ++ PRINT("TCP dest port=%d\n", READ_16B(cursor + 2)); ++ PRINT("TCP sequence number=%u\n", READ_32B(cursor + 4)); ++ PRINT("TCP ack number=%u\n", READ_32B(cursor + 8)); ++ tcp_flags = READ_16B(cursor + 12); ++ tcp_header_len = ((tcp_flags & 0xf000) >> 12) * 4; + PRINT("TCP Header Length=%d\n", tcp_header_len); + PRINT("TCP flags URG=%d ACK=%d PSH=%d RST=%d SYN=%d FIN=%d\n", -+ !!(tcp_flags&0x20), !!(tcp_flags&0x10), !!(tcp_flags&0x08), -+ !!(tcp_flags&0x04), !!(tcp_flags&0x02), !!(tcp_flags&0x01)); -+ PRINT("TCP window size=%d\n", READ_16B(cursor+14)); -+ PRINT("TCP checksum of header and body=0x%x\n", READ_16B(cursor+16)); -+ PRINT("TCP urgent pointer=0x%x\n", READ_16B(cursor+18)); ++ !!(tcp_flags & 0x20), !!(tcp_flags & 0x10), !!(tcp_flags & 0x08), ++ !!(tcp_flags & 0x04), !!(tcp_flags & 0x02), !!(tcp_flags & 0x01)); ++ PRINT("TCP window size=%d\n", READ_16B(cursor + 14)); ++ PRINT("TCP checksum of header and body=0x%x\n", READ_16B(cursor + 16)); ++ PRINT("TCP urgent pointer=0x%x\n", READ_16B(cursor + 18)); + if ((len - (cursor - start)) >= tcp_header_len) + { + cursor += tcp_header_len; @@ -66522,19 +67044,18 @@ index 000000000000..8e11ef3dbdf0 + +} + -+ -+void hal_show_txagg_desc( struct hi_agg_tx_desc* HiTxDesc) ++void hal_show_txagg_desc(struct hi_agg_tx_desc *HiTxDesc) +{ + PRINT("HiTxDesc->RateTableMode %x\n", HiTxDesc->RateTableMode); + PRINT("HiTxDesc->TxPower %x\n", HiTxDesc->TxPower); + PRINT("HiTxDesc->StaId %x\n", HiTxDesc->StaId); + PRINT("HiTxDesc->KeyId %x\n", HiTxDesc->KeyId); + PRINT("HiTxDesc->EncryptType %x\n", HiTxDesc->EncryptType); -+ PRINT("HiTxDesc->TID %x\n", HiTxDesc->TID); ++ PRINT("HiTxDesc->TID %x\n", HiTxDesc->TID); + PRINT("HiTxDesc->CurrentRate %x\n", HiTxDesc->CurrentRate); + PRINT("HiTxDesc->TxTryRate1 %x\n", HiTxDesc->TxTryRate1); + -+ PRINT("HiTxDesc->TxTryNum0 %x\n", HiTxDesc->TxTryNum0); ++ PRINT("HiTxDesc->TxTryNum0 %x\n", HiTxDesc->TxTryNum0); + + PRINT("HiTxDesc->FLAG %x\n", HiTxDesc->FLAG); + PRINT("HiTxDesc->FLAG2 %x\n", HiTxDesc->FLAG2); @@ -66544,7 +67065,7 @@ index 000000000000..8e11ef3dbdf0 + PRINT("HiTxDesc->MpduNum %x\n", HiTxDesc->MpduNum); +} + -+void hal_tx_priv_desc_show(const struct hi_tx_priv_hdr* const HiTxPrivDesc) ++void hal_tx_priv_desc_show(const struct hi_tx_priv_hdr *const HiTxPrivDesc) +{ + PRINT("HiTxPrivDesc->DMALEN %x\n", HiTxPrivDesc->DMALEN); + PRINT("HiTxPrivDesc->MPDULEN %x\n", HiTxPrivDesc->MPDULEN); @@ -66560,49 +67081,55 @@ index 000000000000..8e11ef3dbdf0 +void hal_txinfo_show() +{ + struct hal_private *hal_priv = hal_get_priv(); -+ struct hw_interface* hif = hif_get_hw_interface(); ++ struct hw_interface *hif = hif_get_hw_interface(); ++ int i; + -+ struct _CO_SHARED_FIFO* pTxShareFifo =NULL;// -+ int i =0; + DBG_ENTER(); + -+ for(i=0; itxds_trista_fifo[i]; -+ PRINT("TID = %d,hal_get_priv_cnt %d\n", i,hal_get_priv_cnt(i)); -+ PRINT("TID = %d,CO_TX_BUFFER_MAKE= %d\n", i, CO_SharedFifoNbElt(&hal_priv->txds_trista_fifo[i],CO_TX_BUFFER_MAKE)) ; -+ PRINT("TID = %d,CO_TX_BUFFER_SET= %d\n", i, CO_SharedFifoNbElt(&hal_priv->txds_trista_fifo[i],CO_TX_BUFFER_SET)) ; -+ PRINT("pTxShareFifo->IdxTab[0] %d,%d,\n", pTxShareFifo->IdxTab[0].In,pTxShareFifo->IdxTab[0].Out); -+ PRINT("pTxShareFifo->IdxTab[1] %d,%d,\n", pTxShareFifo->IdxTab[1].In,pTxShareFifo->IdxTab[1].Out); -+ PRINT("pTxShareFifo->IdxTab[2] %d,%d,\n", pTxShareFifo->IdxTab[2].In,pTxShareFifo->IdxTab[2].Out); ++ PRINT("TID = %d,hal_get_priv_cnt %d\n", i, hal_get_priv_cnt(i)); ++ PRINT("TID = %d,CO_TX_BUFFER_MAKE= %d\n", i, ++ CO_SharedFifoNbElt(&hal_priv->txds_trista_fifo[i], CO_TX_BUFFER_MAKE)) ; ++ PRINT("TID = %d,CO_TX_BUFFER_SET= %d\n", i, ++ CO_SharedFifoNbElt(&hal_priv->txds_trista_fifo[i], CO_TX_BUFFER_SET)) ; ++ PRINT("pTxShareFifo->IdxTab[0] %d,%d,\n", pTxShareFifo->IdxTab[0].In, ++ pTxShareFifo->IdxTab[0].Out); ++ PRINT("pTxShareFifo->IdxTab[1] %d,%d,\n", pTxShareFifo->IdxTab[1].In, ++ pTxShareFifo->IdxTab[1].Out); ++ PRINT("pTxShareFifo->IdxTab[2] %d,%d,\n", pTxShareFifo->IdxTab[2].In, ++ pTxShareFifo->IdxTab[2].Out); + } + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,15,0) && !defined (LINUX_PLATFORM) -+ PRINT("HiStatus.Tx_Send_num %d \n",hif->HiStatus.Tx_Send_num); -+ PRINT("HiStatus.Tx_Free_num %d \n",hif->HiStatus.Tx_Free_num); -+ PRINT("HiStatus.Tx_Done_num %d \n",hif->HiStatus.Tx_Done_num); ++ PRINT("HiStatus.Tx_Send_num %d \n", hif->HiStatus.Tx_Send_num); ++ PRINT("HiStatus.Tx_Free_num %d \n", hif->HiStatus.Tx_Free_num); ++ PRINT("HiStatus.Tx_Done_num %d \n", hif->HiStatus.Tx_Done_num); +#else -+ PRINT("HiStatus.Tx_Send_num %d \n",atomic_read(&hif->HiStatus.Tx_Send_num)); -+ PRINT("HiStatus.Tx_Free_num %d \n",atomic_read(&hif->HiStatus.Tx_Free_num)); -+ PRINT("HiStatus.Tx_Done_num %d \n",atomic_read(&hif->HiStatus.Tx_Done_num)); ++ PRINT("HiStatus.Tx_Send_num %d \n", atomic_read(&hif->HiStatus.Tx_Send_num)); ++ PRINT("HiStatus.Tx_Free_num %d \n", atomic_read(&hif->HiStatus.Tx_Free_num)); ++ PRINT("HiStatus.Tx_Done_num %d \n", atomic_read(&hif->HiStatus.Tx_Done_num)); +#endif -+ PRINT(" hal_priv->txPageFreeNum%d,\n", hal_priv->txPageFreeNum); -+ PRINT(" hal_priv->bitmap[0]=%lx,\n", hal_priv->tx_frames_map[0]); -+ PRINT(" hal_priv->bitmap[1]=%lx,\n", hal_priv->tx_frames_map[1]); -+ PRINT(" hal_priv->HalTxPageDoneCounter=%d,\n", hal_priv->HalTxPageDoneCounter ); -+ PRINT(" hal_priv->HalTxFrameDoneCounter=%d,\n", hal_priv->HalTxFrameDoneCounter ); -+ PRINT(" hal_priv->txcompletestatus->txpagecounter=%d,\n", hal_priv->txcompletestatus->txpagecounter ); ++ PRINT(" hal_priv->txPageFreeNum%d,\n", hal_priv->txPageFreeNum); ++ PRINT(" hal_priv->bitmap[0]=%lx,\n", hal_priv->tx_frames_map[0]); ++ PRINT(" hal_priv->bitmap[1]=%lx,\n", hal_priv->tx_frames_map[1]); ++ PRINT(" hal_priv->HalTxPageDoneCounter=%d,\n", hal_priv->HalTxPageDoneCounter ); ++ PRINT(" hal_priv->HalTxFrameDoneCounter=%d,\n", hal_priv->HalTxFrameDoneCounter ); ++ PRINT(" hal_priv->txcompletestatus->txpagecounter=%d,\n", hal_priv->txcompletestatus->txpagecounter ); + -+ PRINT("HiStatus.Tx_Done_num-- %d \n",hif->HiStatus.Tx_Done_num); ++ PRINT("HiStatus.Tx_Done_num-- %d \n", hif->HiStatus.Tx_Done_num); +} + +void hal_dpd_memory_download(void) +{ + unsigned int reg_tmp; + struct hw_interface* hif = hif_get_hw_interface(); -+ unsigned char * d_ptr = NULL; ++ unsigned char *d_ptr; + unsigned int addr = DPD_MEMORY_ADDR; -+ int len = 0, offset = 0; ++ int len, offset = 0; + + d_ptr = (unsigned char *)MEMDATA; + /* 1024 words */ @@ -66611,7 +67138,7 @@ index 000000000000..8e11ef3dbdf0 + ASSERT(len > 0); + ASSERT(len <= DPD_MEMORY_LEN); + -+ //set ram share ++ /* set ram share */ + hif->hif_ops.hi_write_word(0x00a0d0e4, 0x8000007f); + + /* @@ -66625,7 +67152,7 @@ index 000000000000..8e11ef3dbdf0 + if (!(reg_tmp & BIT(23))) + { + reg_tmp |= BIT(23); -+ hif->hif_ops.hi_write_word(RG_SDIO_IF_MISC_CTRL , reg_tmp); ++ hif->hif_ops.hi_write_word(RG_SDIO_IF_MISC_CTRL, reg_tmp); + } + /*config msb 15 bit address in BaseAddr Register*/ + hif->hif_ops.hi_write_reg32(RG_SCFG_FUNC5_BADDR_A, addr & 0xfffe0000); @@ -66633,8 +67160,8 @@ index 000000000000..8e11ef3dbdf0 + /* len <= DPD_MEMORY_LEN, just for exception */ + do + { -+ unsigned char* sdio_kmm = NULL; -+ int databyte = 0; ++ unsigned char *sdio_kmm; ++ int databyte; + + databyte = (len > SRAM_MAX_LEN) ? SRAM_MAX_LEN : len; + @@ -66643,8 +67170,8 @@ index 000000000000..8e11ef3dbdf0 + + memcpy(sdio_kmm, d_ptr + offset, databyte); + -+ hif->hif_ops.bt_hi_write_sram(sdio_kmm, -+ (unsigned char*)(SYS_TYPE)((addr & 0x1ffff) + offset), databyte); ++ hif->hif_ops.bt_hi_write_sram(sdio_kmm, (unsigned char*)(SYS_TYPE)((addr & 0x1ffff) + offset), ++ databyte); + + len -= databyte; + offset += databyte; @@ -66674,7 +67201,7 @@ index 000000000000..8e11ef3dbdf0 +#endif +} + -+unsigned char fwlog_buf[SRAM_FWLOG_BUFFER_LEN] = {0}; ++unsigned char fwlog_buf[SRAM_FWLOG_BUFFER_LEN] = { 0 }; +void hal_get_fwlog(void) +{ + struct hw_interface *hif = hif_get_hw_interface(); @@ -66698,11 +67225,12 @@ index 000000000000..8e11ef3dbdf0 + reg_tmp |= BIT(23); + hif->hif_ops.hi_write_word(RG_SDIO_IF_MISC_CTRL , reg_tmp); + } -+ /*config msb 15 bit address in BaseAddr Register*/ ++ /* config msb 15 bit address in BaseAddr Register */ + hif->hif_ops.hi_write_reg32(RG_SCFG_FUNC5_BADDR_A, addr & 0xfffe0000); + + hif->hif_ops.bt_hi_read_sram((unsigned char*)fwlog_buf, -+ (unsigned char*)(SYS_TYPE)(addr & 0x1ffff), databyte); ++ (unsigned char*)(SYS_TYPE)(addr & 0x1ffff), ++ databyte); + + drv_priv->drv_ops.drv_print_fwlog(fwlog_buf, databyte); +} @@ -66714,7 +67242,7 @@ index 000000000000..8e11ef3dbdf0 +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_hal.h b/drivers/net/wireless/w1/vmac/wifi_hal.h new file mode 100644 -index 000000000000..314b377866db +index 0000000000000000000000000000000000000000..314b377866db377827014a5b4a56395a21d301d8 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_hal.h @@ -0,0 +1,123 @@ @@ -66843,10 +67371,10 @@ index 000000000000..314b377866db +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_hal_cmd.c b/drivers/net/wireless/w1/vmac/wifi_hal_cmd.c new file mode 100644 -index 000000000000..88e06181ef00 +index 0000000000000000000000000000000000000000..cacb769e8667e0a9e1a73a6667bca666ec6e3ea5 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_hal_cmd.c -@@ -0,0 +1,2225 @@ +@@ -0,0 +1,2223 @@ +/* + **************************************************************************************** + * @@ -67132,7 +67660,7 @@ index 000000000000..88e06181ef00 +unsigned int phy_set_preamble_type( unsigned char PreambleType) +{ + struct hal_private *hal_priv = hal_get_priv(); -+ printk("%s(%d) %x \n\n",__FUNCTION__, __LINE__,PreambleType); ++ pr_debug("%s(%d) %x \n\n",__FUNCTION__, __LINE__,PreambleType); + wifi_conf_mib.dot11PreambleType = PreambleType; + hal_priv->sta_con_msg.PreambleType = PreambleType; + return 1; @@ -67148,7 +67676,7 @@ index 000000000000..88e06181ef00 + unsigned int BcnAddr = hif->hw_config.beaconframeaddress; + struct TxDescPage *pbeacon_s = (struct TxDescPage *)buffer; + struct OtherTxPage *other_page = NULL; -+ int total_len = len + sizeof(struct TxDescPage) -1 + FCS_LEN; ++ int total_valid_len = len + sizeof(struct TxDescPage) - 1; /*not include fcs len*/ + /* beacon len per page */ + int firstpagelen = 0, otherpagelen = 0; + @@ -67161,7 +67689,7 @@ index 000000000000..88e06181ef00 + memcpy(pbeacon_s->txdata, pBeacon, len); + + /* build page flag */ -+ if (total_len <= PAGE_LEN) { ++ if (total_valid_len <= PAGE_LEN) { + /* set firstpagelen and otherpagelen to 0 to be flag */ + firstpagelen = otherpagelen = 0; + pbeacon_s->BufferInfo.MPDUBufFlag = 0; @@ -67288,7 +67816,7 @@ index 000000000000..88e06181ef00 + if (otherpagelen == 0) + { + hif->hif_ops.hi_write_sram((unsigned char*)(SYS_TYPE)buffer, -+ (unsigned char*)(SYS_TYPE)BcnAddr, total_len); ++ (unsigned char*)(SYS_TYPE)BcnAddr, total_valid_len); + } + else + { @@ -67307,7 +67835,7 @@ index 000000000000..88e06181ef00 + phy_set_param_cmd(Reset_Key_Cmd,wnet_vif_id,ALL_KEY_RST); + //life time + phy_set_param_cmd(MaxTxLifetime_Cmd,0,512); -+ printk("%s(%d)\n", __func__, __LINE__); ++ pr_debug("%s(%d)\n", __func__, __LINE__); + return 1; +} + @@ -67416,7 +67944,7 @@ index 000000000000..88e06181ef00 + hal_dpd_memory_download(); + } + -+ //printk("%s:%d, channel %d, bw %d, flag %d \n", __func__, __LINE__, channel, bw, flag); ++ //pr_debug("%s:%d, channel %d, bw %d, flag %d \n", __func__, __LINE__, channel, bw, flag); + HAL_BEGIN_LOCK(); + hi_set_cmd((unsigned char *)&channel_switch, sizeof(struct Channel_Switch)); + HAL_END_LOCK(); @@ -67480,7 +68008,7 @@ index 000000000000..88e06181ef00 + + to_set = 0; + to_set = hif->hif_ops.hi_read_word( RG_PHY_BW_REG); -+ //printk("%s(%d) check: reg_0x%x is 0x%x cchan_num %d, chan_bw %d, cchan %d\n", __func__, __LINE__, ++ //pr_debug("%s(%d) check: reg_0x%x is 0x%x cchan_num %d, chan_bw %d, cchan %d\n", __func__, __LINE__, + //RG_PHY_BW_REG, to_set, chan->cchan_num, chan->chan_bw, chan->cchan_num); + return 1; +#else @@ -67773,8 +68301,7 @@ index 000000000000..88e06181ef00 + struct hal_private * hal_priv =hal_get_priv(); + unsigned int wme_acparam = aifsn|(cwminmax<<8)|(txop<<16); + -+ /* Removed verbose AC param log to reduce noise */ -+ /* PRINT("%s-->wnet_vif_id:%d, aifsn:%d, cwminmax:%02x txop:%d\n",__func__, wnet_vif_id, aifsn, cwminmax, txop); */ ++ PRINT("%s-->wnet_vif_id:%d, aifsn:%d, cwminmax:%02x txop:%d\n",__func__, wnet_vif_id, aifsn, cwminmax, txop); + + if((cwminmax ==0)||(aifsn==0)) + { @@ -67839,7 +68366,7 @@ index 000000000000..88e06181ef00 + return phy_get_param_cmd_ull(GET_TSF_CMD, vid); +} + -+unsigned long long phy_get_pn(unsigned char vid) ++static unsigned long long phy_get_pn(unsigned char vid) +{ + return phy_get_param_cmd_ull(GET_PN_CMD, vid); +} @@ -67931,7 +68458,7 @@ index 000000000000..88e06181ef00 + if (ipv6 != NULL) + memcpy(arp_agent_cmd.ip6_addr, ipv6, IPV6_ADDR_BUF_LEN); + -+ printk("%s:%d, set arp agent, enable %d \n", __func__, __LINE__, enable); ++ pr_debug("%s:%d, set arp agent, enable %d \n", __func__, __LINE__, enable); + HAL_BEGIN_LOCK(); + hi_set_cmd((unsigned char *)&arp_agent_cmd, sizeof(struct ArpAgentCmd)); + HAL_END_LOCK(); @@ -67955,7 +68482,7 @@ index 000000000000..88e06181ef00 + memcpy(add_pattern_cmd.pattern, pattern, add_pattern_cmd.pattern_len); + memcpy(add_pattern_cmd.mask, mask, mask_len); + -+ printk("%s:%d, wow len %d, mask 0x%x, pattern 0x%lx\n", __func__, __LINE__, len, ++ pr_debug("%s:%d, wow len %d, mask 0x%x, pattern 0x%lx\n", __func__, __LINE__, len, + *(unsigned int *)mask, *(unsigned long*)pattern); + HAL_BEGIN_LOCK(); + hi_set_cmd((unsigned char *)&add_pattern_cmd, sizeof(struct AddPatternCmd)); @@ -67987,7 +68514,7 @@ index 000000000000..88e06181ef00 + cnt++; + if (cnt > 10) + { -+ printk("%s:%d, haltxdrop = 1 0x%lx, 0x%lx\n", __func__, __LINE__, ++ pr_debug("%s:%d, haltxdrop = 1 0x%lx, 0x%lx\n", __func__, __LINE__, + hal_priv->tx_frames_map[0], hal_priv->tx_frames_map[1]); + break; + } @@ -68001,7 +68528,7 @@ index 000000000000..88e06181ef00 + cnt++; + if (cnt > 10) + { -+ printk("%s:%d, no resume cnt 0x%x\n", __func__, __LINE__, ++ pr_debug("%s:%d, no resume cnt 0x%x\n", __func__, __LINE__, + atomic_read(&hal_priv->sdio_suspend_cnt)); + return -1; + } @@ -68009,7 +68536,7 @@ index 000000000000..88e06181ef00 + /* in case */ + if (hal_priv->bhaltxdrop == 1) + { -+ printk("%s:%d, haltxdrop = 1 0x%lx, 0x%lx, pagenum %d \n", __func__, __LINE__, ++ pr_debug("%s:%d, haltxdrop = 1 0x%lx, 0x%lx, pagenum %d \n", __func__, __LINE__, + hal_priv->tx_frames_map[0], hal_priv->tx_frames_map[1], hal_priv->txPageFreeNum); + hal_priv->bhaltxdrop = 0; + hal_priv->tx_frames_map[0] = 0; @@ -68123,7 +68650,7 @@ index 000000000000..88e06181ef00 + + if (hal_priv->HalTxFrameDoneCounter != hal_priv->txcompletestatus->txdoneframecounter) + { -+ printk("%s:%d, txdoneframecounter:%x, HalTxFrameDoneCounter:%x\n", __func__, __LINE__, ++ pr_debug("%s:%d, txdoneframecounter:%x, HalTxFrameDoneCounter:%x\n", __func__, __LINE__, + hal_priv->txcompletestatus->txdoneframecounter, hal_priv->HalTxFrameDoneCounter); + } +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,15,0) && !defined (LINUX_PLATFORM) @@ -68134,7 +68661,7 @@ index 000000000000..88e06181ef00 + || (atomic_read(&hif->HiStatus.Tx_Done_num) != atomic_read(&hif->HiStatus.Tx_Send_num))) +#endif + { -+ printk("%s:%d, free %d, done %d, send %d\n", __func__, __LINE__, ++ pr_debug("%s:%d, free %d, done %d, send %d\n", __func__, __LINE__, +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,15,0) && !defined (LINUX_PLATFORM) + hif->HiStatus.Tx_Free_num, hif->HiStatus.Tx_Done_num, hif->HiStatus.Tx_Send_num); +#else @@ -68153,7 +68680,7 @@ index 000000000000..88e06181ef00 + atomic_set(&hif->HiStatus.Tx_Done_num, atomic_read(&hif->HiStatus.Tx_Send_num)); +#endif + } -+ printk("%s end, wow enable %d, mode %d, filter 0x%x, ret %d\n", ++ pr_debug("%s end, wow enable %d, mode %d, filter 0x%x, ret %d\n", + ((enable == 1) ? "suspend" : "resume"), enable, mode, filters, ret); + return 0; +} @@ -68214,7 +68741,7 @@ index 000000000000..88e06181ef00 + coexist_cmd.coexist_id_bitmap = COEXIST_EN_CMD; + coexist_cmd.coexist_enable = enable; + -+ printk("%s:%d, phy_set_coexist_en, enable %d \n", __func__, __LINE__, enable); ++ pr_debug("%s:%d, phy_set_coexist_en, enable %d \n", __func__, __LINE__, enable); + HAL_BEGIN_LOCK(); + hi_set_cmd((unsigned char *)&coexist_cmd, sizeof(struct Coexist_Cmd)); + HAL_END_LOCK(); @@ -68232,7 +68759,7 @@ index 000000000000..88e06181ef00 + coexist_cmd.coexist_id_bitmap = COEXIST_MAX_MISS_BCN_CNT; + coexist_cmd.max_miss_bcn_cnt = miss_bcn_cnt; + -+ printk("%s:%d, miss_bcn_cnt, %d \n", __func__, __LINE__, miss_bcn_cnt); ++ pr_debug("%s:%d, miss_bcn_cnt, %d \n", __func__, __LINE__, miss_bcn_cnt); + HAL_BEGIN_LOCK(); + hi_set_cmd((unsigned char *)&coexist_cmd, sizeof(struct Coexist_Cmd)); + HAL_END_LOCK(); @@ -68249,7 +68776,7 @@ index 000000000000..88e06181ef00 + coexist_cmd.coexist_id_bitmap = COEXIST_REQ_TIMEOUT; + coexist_cmd.req_timeout_value = timeout_value; + -+ printk("%s:%d, req_timeslice_timeout_value %d \n", __func__, __LINE__, timeout_value); ++ pr_debug("%s:%d, req_timeslice_timeout_value %d \n", __func__, __LINE__, timeout_value); + HAL_BEGIN_LOCK(); + hi_set_cmd((unsigned char *)&coexist_cmd, sizeof(struct Coexist_Cmd)); + HAL_END_LOCK(); @@ -68269,7 +68796,7 @@ index 000000000000..88e06181ef00 + coexist_cmd.coexist_id_bitmap = COEXIST_NOT_GRANT_WEIGHT; + coexist_cmd.not_grant_weight = not_grant_weight; + -+ printk("%s:%d, not_grant_weight %d \n", __func__, __LINE__, not_grant_weight); ++ pr_debug("%s:%d, not_grant_weight %d \n", __func__, __LINE__, not_grant_weight); + HAL_BEGIN_LOCK(); + hi_set_cmd((unsigned char *)&coexist_cmd, sizeof(struct Coexist_Cmd)); + HAL_END_LOCK(); @@ -68289,7 +68816,7 @@ index 000000000000..88e06181ef00 + coexist_cmd.coexist_id_bitmap = COEXIST_MAX_NOT_GRANT_CNT; + coexist_cmd.max_not_grant_cnt = coexist_max_not_grant_cnt; + -+ printk("%s:%d, coexist_max_not_grant_cnt %d \n", __func__, __LINE__, coexist_max_not_grant_cnt); ++ pr_debug("%s:%d, coexist_max_not_grant_cnt %d \n", __func__, __LINE__, coexist_max_not_grant_cnt); + HAL_BEGIN_LOCK(); + hi_set_cmd((unsigned char *)&coexist_cmd, sizeof(struct Coexist_Cmd)); + HAL_END_LOCK(); @@ -68311,7 +68838,7 @@ index 000000000000..88e06181ef00 + coexist_cmd.coexist_id_bitmap = COEXIST_SCAN_PRIORITY_RANGE; + coexist_cmd.scan_priority_range = coexist_scan_priority_range; + -+ printk("%s:%d, coexist scan min priority is %d,max priority is %d\n", __func__, __LINE__, coexist_scan_priority_range&0xffff, coexist_scan_priority_range>>16); ++ pr_debug("%s:%d, coexist scan min priority is %d,max priority is %d\n", __func__, __LINE__, coexist_scan_priority_range&0xffff, coexist_scan_priority_range>>16); + HAL_BEGIN_LOCK(); + hi_set_cmd((unsigned char *)&coexist_cmd, sizeof(struct Coexist_Cmd)); + HAL_END_LOCK(); @@ -68334,7 +68861,7 @@ index 000000000000..88e06181ef00 + coexist_cmd.coexist_id_bitmap = COEXIST_BE_BK_NOQOS_PRI_RANGE; + coexist_cmd.be_bk_no_qos_priority_range = coexist_scan_priority_range; + -+ printk("%s:%d, coexist be/bk/noqos min priority is %d,max priority is %d\n", __func__, __LINE__, coexist_scan_priority_range&0xffff, coexist_scan_priority_range>>16); ++ pr_debug("%s:%d, coexist be/bk/noqos min priority is %d,max priority is %d\n", __func__, __LINE__, coexist_scan_priority_range&0xffff, coexist_scan_priority_range>>16); + HAL_BEGIN_LOCK(); + hi_set_cmd((unsigned char *)&coexist_cmd, sizeof(struct Coexist_Cmd)); + HAL_END_LOCK(); @@ -68362,7 +68889,7 @@ index 000000000000..88e06181ef00 + return -1; + } + -+ printk("%s:%d, coex cmd\n", __func__, __LINE__); ++ pr_debug("%s:%d, coex cmd\n", __func__, __LINE__); + HAL_BEGIN_LOCK(); + hi_set_cmd((unsigned char *)&coexist_cmd, sizeof(struct Coexist_Cmd)); + HAL_END_LOCK(); @@ -68397,7 +68924,7 @@ index 000000000000..88e06181ef00 + hif->hif_ops.hi_write_word(RG_AGC_EN, reg_data | BIT(28)); + } + reg_data = hif->hif_ops.hi_read_word(RG_AGC_EN); -+ printk("%s:%d, enable %d, agc 0x%x \n", __func__, __LINE__, enable, reg_data); ++ pr_debug("%s:%d, enable %d, agc 0x%x \n", __func__, __LINE__, enable, reg_data); +#endif + struct Phy_Interface_Param phy_interface; + memset(&phy_interface, 0, sizeof(struct Phy_Interface_Param)); @@ -68409,7 +68936,7 @@ index 000000000000..88e06181ef00 + HAL_BEGIN_LOCK(); + hi_set_cmd((unsigned char *)&phy_interface, sizeof(struct Phy_Interface_Param)); + HAL_END_LOCK(); -+ printk("%s:%d, vid %d, enable %d\n", __func__, __LINE__, vid, enable); ++ pr_debug("%s:%d, vid %d, enable %d\n", __func__, __LINE__, vid, enable); + + return 0; +} @@ -68420,7 +68947,7 @@ index 000000000000..88e06181ef00 + struct hw_interface* hif = hif_get_hw_interface(); + struct Fwlog_Mode_Control fwlog_mode; + memset(&fwlog_mode, 0, sizeof(struct Fwlog_Mode_Control)); -+ printk("%s:%d, mode %d \n", __func__, __LINE__, mode); ++ pr_debug("%s:%d, mode %d \n", __func__, __LINE__, mode); + + fwlog_mode.Cmd = FWLOG_MODE_CMD; + if (mode == 0) @@ -68459,7 +68986,7 @@ index 000000000000..88e06181ef00 + return 0; +} + -+unsigned int process_cali_content(char *varbuf, unsigned int len) ++static unsigned int process_cali_content(char *varbuf, unsigned int len) +{ + char *dp; + bool findNewline; @@ -68635,7 +69162,7 @@ index 000000000000..88e06181ef00 + return 1; +} + -+unsigned char parse_tx_power_coefficient(char *varbuf, int len, char str_pwr_coefficient[]) ++static unsigned char parse_tx_power_coefficient(char *varbuf, int len, char str_pwr_coefficient[]) +{ + unsigned short pwr_coefficient[57]; + memset(pwr_coefficient,0,sizeof(pwr_coefficient)); @@ -68667,14 +69194,14 @@ index 000000000000..88e06181ef00 + return 0; +} + -+unsigned char parse_tx_power_band(char *varbuf, int len, char str_pwr_plan[]) ++static unsigned char parse_tx_power_band(char *varbuf, int len, char str_pwr_plan[]) +{ + unsigned short band_pwr_table[4]; + memset(band_pwr_table,0,sizeof(band_pwr_table)); + + get_s16_item(varbuf, len, str_pwr_plan, &band_pwr_table[0]); + -+ printk("======>>>>>>%s: %d\n",str_pwr_plan, band_pwr_table[3]); ++ pr_debug("======>>>>>>%s: %d\n",str_pwr_plan, band_pwr_table[3]); + + if (memcmp(str_pwr_plan,"ce_band_pwr_tbl",strlen(str_pwr_plan)) == 0) { + update_tx_power_band(TX_POWER_CE, band_pwr_table); @@ -68683,7 +69210,7 @@ index 000000000000..88e06181ef00 + return 0; +} + -+unsigned char parse_cali_param(char *varbuf, int len, struct Cali_Param *cali_param) ++static unsigned char parse_cali_param(char *varbuf, int len, struct Cali_Param *cali_param) +{ + unsigned short platform_verid = 0; // default: 0 + unsigned short cali_config = 0; @@ -68725,24 +69252,24 @@ index 000000000000..88e06181ef00 +#endif + cali_param->platform_versionid = platform_verid; + -+ printk("======>>>>>> version = %ld\n", cali_param->version); -+ printk("======>>>>>> cali_config = %d\n", cali_param->cali_config); -+ printk("======>>>>>> freq_offset = %d\n", cali_param->freq_offset); -+ printk("======>>>>>> htemp_freq_offset = %d\n", cali_param->htemp_freq_offset); -+ printk("======>>>>>> cca_ed_det = %d\n", cali_param->cca_ed_det); -+ printk("======>>>>>> tssi_2g_offset = 0x%x\n", cali_param->tssi_2g_offset); -+ printk("======>>>>>> tssi_5g_offset_5200 = 0x%x\n", cali_param->tssi_5g_offset[0]); -+ printk("======>>>>>> tssi_5g_offset_5400 = 0x%x\n", cali_param->tssi_5g_offset[1]); -+ printk("======>>>>>> tssi_5g_offset_5600 = 0x%x\n", cali_param->tssi_5g_offset[2]); -+ printk("======>>>>>> tssi_5g_offset_5800 = 0x%x\n", cali_param->tssi_5g_offset[3]); -+ printk("======>>>>>> wf2g_spur_rmen = %d\n", cali_param->wf2g_spur_rmen); -+ printk("======>>>>>> spur_freq = %d\n", cali_param->spur_freq); -+ printk("======>>>>>> rf_count = %d\n", cali_param->rf_num); -+ printk("======>>>>>> wftx_pwrtbl_en = %d\n", cali_param->wftx_pwrtbl_en); -+ printk("======>>>>>> platform_versionid = %d\n", cali_param->platform_versionid); -+ printk("======>>>>>> wftx_power_change_disable = %d\n", g_tx_power_change_disable); -+ printk("======>>>>>> initial_gain_change_disable = %d\n", g_initial_gain_change_disable); -+ printk("======>>>>>> digital gain = %s min_2g:0x%x max_2g:0x%x min_5g:0x%x max_5g:0x%x\n", ++ pr_info("======>>>>>> version = %ld\n", cali_param->version); ++ pr_info("======>>>>>> cali_config = %d\n", cali_param->cali_config); ++ pr_info("======>>>>>> freq_offset = %d\n", cali_param->freq_offset); ++ pr_info("======>>>>>> htemp_freq_offset = %d\n", cali_param->htemp_freq_offset); ++ pr_info("======>>>>>> cca_ed_det = %d\n", cali_param->cca_ed_det); ++ pr_info("======>>>>>> tssi_2g_offset = 0x%x\n", cali_param->tssi_2g_offset); ++ pr_info("======>>>>>> tssi_5g_offset_5200 = 0x%x\n", cali_param->tssi_5g_offset[0]); ++ pr_info("======>>>>>> tssi_5g_offset_5400 = 0x%x\n", cali_param->tssi_5g_offset[1]); ++ pr_info("======>>>>>> tssi_5g_offset_5600 = 0x%x\n", cali_param->tssi_5g_offset[2]); ++ pr_info("======>>>>>> tssi_5g_offset_5800 = 0x%x\n", cali_param->tssi_5g_offset[3]); ++ pr_info("======>>>>>> wf2g_spur_rmen = %d\n", cali_param->wf2g_spur_rmen); ++ pr_info("======>>>>>> spur_freq = %d\n", cali_param->spur_freq); ++ pr_info("======>>>>>> rf_count = %d\n", cali_param->rf_num); ++ pr_info("======>>>>>> wftx_pwrtbl_en = %d\n", cali_param->wftx_pwrtbl_en); ++ pr_info("======>>>>>> platform_versionid = %d\n", cali_param->platform_versionid); ++ pr_info("======>>>>>> wftx_power_change_disable = %d\n", g_tx_power_change_disable); ++ pr_info("======>>>>>> initial_gain_change_disable = %d\n", g_initial_gain_change_disable); ++ pr_info("======>>>>>> digital gain = %s min_2g:0x%x max_2g:0x%x min_5g:0x%x max_5g:0x%x\n", + (cali_param->digital_gain_limit.enable == 1 ? "enable" : "disable"), + cali_param->digital_gain_limit.min_2g, cali_param->digital_gain_limit.max_2g, + cali_param->digital_gain_limit.min_5g, cali_param->digital_gain_limit.max_5g); @@ -68759,7 +69286,7 @@ index 000000000000..88e06181ef00 + return 0; +} + -+unsigned char set_tx_power_param_default(struct WF2G_Txpwr_Param *wf2g_txpwr_param, struct WF5G_Txpwr_Param *wf5g_txpwr_param) ++static unsigned char set_tx_power_param_default(struct WF2G_Txpwr_Param *wf2g_txpwr_param, struct WF5G_Txpwr_Param *wf5g_txpwr_param) +{ + unsigned char wf2g_pwr_tbl_dft[2][16] = {{0xBA,0xBA,0xCB,0xCB,0xB5,0xB5,0xC0,0xB5,0xA1,0xA1,0x84,0x7C,0x6C,0x6C,0x63,0x58}, + {0xBA,0xBA,0xCB,0xCB,0xB5,0xB5,0xA6,0xA1,0x94,0x94,0x7C,0x75,0x6C,0x66,0x5D,0x58}}; @@ -68771,7 +69298,7 @@ index 000000000000..88e06181ef00 + memcpy(&wf5g_txpwr_param->wf5g_pwr_tbl, wf5g_pwr_tbl_dft, sizeof(wf5g_txpwr_param->wf5g_pwr_tbl)); + return 0; +} -+unsigned char parse_tx_power_param(char *varbuf, int len, struct WF2G_Txpwr_Param *wf2g_txpwr_param, ++static unsigned char parse_tx_power_param(char *varbuf, int len, struct WF2G_Txpwr_Param *wf2g_txpwr_param, + struct WF5G_Txpwr_Param *wf5g_txpwr_param) +{ + get_s8_item(varbuf, len, "wf2g_20M_pwr_tbl", &wf2g_txpwr_param->wf2g_pwr_tbl[0][0]); @@ -68783,12 +69310,12 @@ index 000000000000..88e06181ef00 + memcpy(&g_wf2g_txpwr_param.wf2g_pwr_tbl, wf2g_txpwr_param->wf2g_pwr_tbl, sizeof(wf2g_txpwr_param->wf2g_pwr_tbl)); + memcpy(&g_wf5g_txpwr_param.wf5g_pwr_tbl, wf5g_txpwr_param->wf5g_pwr_tbl, sizeof(wf5g_txpwr_param->wf5g_pwr_tbl)); + -+ printk("======>>>>>> %s ===>>> aml_wifi_rf txt => 2g 20/40 5g 20/40/80\n", __func__); ++ pr_debug("======>>>>>> %s ===>>> aml_wifi_rf txt => 2g 20/40 5g 20/40/80\n", __func__); + + return 0; +} + -+unsigned char set_tx_power_param_enhance(struct WF2G_Txpwr_Param *wf2g_txpwr_param, struct WF5G_Txpwr_Param *wf5g_txpwr_param) ++static unsigned char set_tx_power_param_enhance(struct WF2G_Txpwr_Param *wf2g_txpwr_param, struct WF5G_Txpwr_Param *wf5g_txpwr_param) +{ + unsigned char wf2g_pwr_tbl_dft[2][16] = {{0xea,0xea,0xea,0xb6,0x9e,0x7e,0xea,0xae,0x9b,0x78,0x84,0x7C,0x6C,0x6C,0x63,0x58}, + {0xBA,0xBA,0xCB,0xCB,0xB5,0xB5,0xda,0xae,0x9b,0x78,0x7C,0x75,0x6C,0x66,0x5D,0x58}}; @@ -68863,7 +69390,7 @@ index 000000000000..88e06181ef00 + if (!g_tx_power_change_disable) { + + if (power_mode == 2) { -+ printk("\n*** %s, change power enhance,bw %d channel %d \n", __func__, channel_switch.bw, channel_switch.channel); ++ pr_debug("\n*** %s, change power enhance,bw %d channel %d \n", __func__, channel_switch.bw, channel_switch.channel); + set_tx_power_param_enhance(&wf2g_txpwr_param, &wf5g_txpwr_param); + memcpy(&wf5g_txpwr_param.wf5g_pwr_tbl, g_wf5g_txpwr_param.wf5g_pwr_tbl, 32); + @@ -68880,7 +69407,7 @@ index 000000000000..88e06181ef00 + + if (power_mode == 1) { + if (g_wftx_pwrtbl_en == 0) { -+ printk("\n*** %s, change power default,bw %d channel %d \n", __func__, channel_switch.bw, channel_switch.channel); ++ pr_debug("\n*** %s, change power default,bw %d channel %d \n", __func__, channel_switch.bw, channel_switch.channel); + set_tx_power_param_default(&wf2g_txpwr_param, &wf5g_txpwr_param); + + HAL_BEGIN_LOCK(); @@ -68889,8 +69416,8 @@ index 000000000000..88e06181ef00 + HAL_END_LOCK(); + + } else if (g_wftx_pwrtbl_en == 1){ -+ printk("\n*** %s, change power mode 1,bw %d channel %d \n", __func__, channel_switch.bw, channel_switch.channel); -+ printk("\n*** %s, change power mode 1,0x%x 0x%x \n", __func__, g_wf2g_txpwr_param.wf2g_pwr_tbl[0][0] , g_wf2g_txpwr_param.wf2g_pwr_tbl[0][1]); ++ pr_debug("\n*** %s, change power mode 1,bw %d channel %d \n", __func__, channel_switch.bw, channel_switch.channel); ++ pr_debug("\n*** %s, change power mode 1,0x%x 0x%x \n", __func__, g_wf2g_txpwr_param.wf2g_pwr_tbl[0][0] , g_wf2g_txpwr_param.wf2g_pwr_tbl[0][1]); + HAL_BEGIN_LOCK(); + hi_set_cmd((unsigned char *)&g_wf2g_txpwr_param, sizeof(struct WF2G_Txpwr_Param)); + hi_set_cmd((unsigned char *)&g_wf5g_txpwr_param, sizeof(struct WF5G_Txpwr_Param)); @@ -68910,7 +69437,7 @@ index 000000000000..88e06181ef00 + +} + -+unsigned char get_cali_param(struct Cali_Param *cali_param, struct WF2G_Txpwr_Param *wf2g_txpwr_param, ++static unsigned char get_cali_param(struct Cali_Param *cali_param, struct WF2G_Txpwr_Param *wf2g_txpwr_param, + struct WF5G_Txpwr_Param *wf5g_txpwr_param) +{ + @@ -68944,20 +69471,20 @@ index 000000000000..88e06181ef00 + default: + sprintf(file_name, "w1/aml_wifi_rf.txt"); + } -+ printk("aml wifi module SN:%04x sn txt not found, the rf config: %s\n", chip_id_l, chip_id_buf); ++ pr_info("aml wifi module SN:%04x sn txt not found, the rf config: %s\n", chip_id_l, file_name); + } else -+ printk("aml wifi module SN:%04x the rf config: %s\n", chip_id_l, chip_id_buf); ++ pr_info("aml wifi module SN:%04x the rf config: %s\n", chip_id_l, file_name); + + error = request_firmware(&fw, file_name, dev); + if (error) { + // sn txt not found, the rf set default config + memset(file_name, 0, 100); + sprintf(file_name, "w1/aml_wifi_rf.txt"); -+ printk("aml wifi module SN:%04x sn txt not found, the rf config: %s\n", chip_id_l, file_name); ++ pr_info("aml wifi module SN:%04x sn txt not found, the rf config: %s\n", chip_id_l, file_name); + error = request_firmware(&fw, file_name, dev); + if (error) { -+ printk("default txt not found again, Please ensure that txt file include in (vendor/)lib/firamware/w1 \n"); -+ printk("Is there a missing mandatory patch here, %s not used again, Please call Aml FAE\n",conf_path); ++ pr_info("default txt not found again, Please ensure that txt file include in (vendor/)lib/firamware/w1 \n"); ++ pr_info("Is there a missing mandatory patch here, %s not used again, Please call Aml FAE\n",conf_path); + goto err; + } + } @@ -68996,7 +69523,7 @@ index 000000000000..88e06181ef00 + cali_param->rf_num = 2; + else + cali_param->rf_num = 1; -+ printk("rf_cout is: %d\n", cali_param->rf_num); ++ pr_debug("rf_cout is: %d\n", cali_param->rf_num); + } + release_firmware(fw); + return 0; @@ -69046,12 +69573,12 @@ index 000000000000..88e06181ef00 + wf5g_txpwr_param.Cmd = WF5G_TXPWR_PARAM_CMD; + err = get_cali_param(&cali_param, &wf2g_txpwr_param, &wf5g_txpwr_param); + -+ printk("calibration parameter: version %d, config %d, freq_offset %d, tssi_2g %d, tssi_5g %d %d %d %d tx_en %d\n", ++ pr_debug("calibration parameter: version %d, config %d, freq_offset %d, tssi_2g %d, tssi_5g %d %d %d %d tx_en %d\n", + cali_param.version, cali_param.cali_config, cali_param.freq_offset, cali_param.tssi_2g_offset, + cali_param.tssi_5g_offset[0], cali_param.tssi_5g_offset[1], cali_param.tssi_5g_offset[2], cali_param.tssi_5g_offset[3], cali_param.wftx_pwrtbl_en); + + if (err == 0) { -+ printk("%s:%d, set calibration parameter \n", __func__, __LINE__); ++ pr_debug("%s:%d, set calibration parameter \n", __func__, __LINE__); + HAL_BEGIN_LOCK(); + hi_set_cmd((unsigned char *)&cali_param, sizeof(struct Cali_Param)); + hi_set_cmd((unsigned char *)&wf2g_txpwr_param, sizeof(struct WF2G_Txpwr_Param)); @@ -69066,7 +69593,6 @@ index 000000000000..88e06181ef00 + return true; +} + -+ +#ifdef HAL_SIM_VER +#ifdef FW_NAME +} @@ -69074,10 +69600,10 @@ index 000000000000..88e06181ef00 +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_hal_cmd.h b/drivers/net/wireless/w1/vmac/wifi_hal_cmd.h new file mode 100644 -index 000000000000..a456580b3e1b +index 0000000000000000000000000000000000000000..97b6cbc6191a30b533dfed779455fa54f802737e --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_hal_cmd.h -@@ -0,0 +1,91 @@ +@@ -0,0 +1,93 @@ +#ifndef __AML_PHY_H__ +#define __AML_PHY_H__ + @@ -69167,14 +69693,16 @@ index 000000000000..a456580b3e1b +unsigned int hal_cfg_cali_param(void); +unsigned int hal_cfg_txpwr_cffc_param(void * chan, void * txpwr_plan); + -+ ++unsigned char get_s8_item(char *varbuf, int len, char *item, char *item_value); ++unsigned char get_s16_item(char *varbuf, int len, char *item, short *item_value); ++unsigned char get_s32_item(char *varbuf, int len, char *item, unsigned int *item_value); +#endif //__AML_PHY_H__ diff --git a/drivers/net/wireless/w1/vmac/wifi_hal_com.h b/drivers/net/wireless/w1/vmac/wifi_hal_com.h new file mode 100644 -index 000000000000..4f8744ce7123 +index 0000000000000000000000000000000000000000..3dd045e7a0c758f4f82f8c4d5fe08edaad595af3 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_hal_com.h -@@ -0,0 +1,1372 @@ +@@ -0,0 +1,1376 @@ +#ifndef _TOTAL_H_ +#define _TOTAL_H_ +#define __INLINE __inline @@ -69205,7 +69733,7 @@ index 000000000000..4f8744ce7123 +#include +#include +#include -+#include /* printk() */ ++#include /* pr_debug() */ +#include +#include +#include @@ -69245,6 +69773,7 @@ index 000000000000..4f8744ce7123 +#include "fi_sdio.h" +#include "opt_all.h" +#include "fi_cmd.h" ++#include "patch_fi_cmd.h" + +struct hw_interface; + @@ -70270,7 +70799,7 @@ index 000000000000..4f8744ce7123 +#define TEST_WIFI_EFUSE BIT(16) + +#define HAL_TEST_DEFAULT (0) -+#define TEST_PRINT printk ++#define TEST_PRINT pr_debug + +#define INBUFFER_LEN_VALID_BIT (256-2) +#define INBUFFER_LEN (256/8) @@ -70546,13 +71075,16 @@ index 000000000000..4f8744ce7123 + +struct hal_private* hal_get_priv(void); +struct hw_interface* hif_get_hw_interface(void); ++ ++void print_driver_version(void); ++ +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_hal_platform.c b/drivers/net/wireless/w1/vmac/wifi_hal_platform.c new file mode 100644 -index 000000000000..395e351a1cf6 +index 0000000000000000000000000000000000000000..b260316b6c72061f3932d92d7f1b24a868f67036 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_hal_platform.c -@@ -0,0 +1,1083 @@ +@@ -0,0 +1,1111 @@ +#ifdef HAL_SIM_VER +#ifdef FW_NAME +namespace FW_NAME @@ -70599,15 +71131,15 @@ index 000000000000..395e351a1cf6 +extern int wifi_irq_num(void); +#if (USE_GPIO_IRQ==1) +#if LINUX_VERSION_CODE <= KERNEL_VERSION(3,14,29) -+int platform_wifi_request_gpio_irq (void *data) ++int platform_wifi_request_gpio_irq(void *data) +{ + unsigned int irq_num = wifi_irq_num(); + int ret = -1; -+ int irq_trigger_type, irq_flag; ++ int irq_trigger_type; + -+ irq_flag = IRQF_DISABLED; + amlhal_gpio.gpio_irq_mode = wifi_irq_trigger_level(); + amlhal_gpio.irq_num = irq_num; ++ + switch (amlhal_gpio.gpio_irq_mode) + { + case WIFI_GPIO_IRQ_FALLING: @@ -70628,10 +71160,13 @@ index 000000000000..395e351a1cf6 + } + do + { ++ int irq_flag; ++ + irq_flag = AML_GPIO_IRQ(irq_num, amlhal_gpio.filter_num, irq_trigger_type); + msleep(10); -+ printk("irq_num %d irq_trigger_type %d irq_flag 0x%08x\n",irq_num,irq_trigger_type,irq_flag); -+ ret = request_irq(irq_num, hal_irq_top, irq_flag, "WIFI_INT", data); ++ pr_debug("irq_num %d irq_trigger_type %d irq_flag 0x%08x\n", irq_num, ++ irq_trigger_type, irq_flag); ++ ret = request_irq(irq_num, hal_irq_top, irq_flag, "WIFI_INT", data); + if (ret < 0) + DPRINTF(AML_DEBUG_ERROR,"%s(%d) request_irq err, ret=%d\n",__func__,__LINE__, ret); + } @@ -70642,11 +71177,11 @@ index 000000000000..395e351a1cf6 + +#else + -+int platform_wifi_request_gpio_irq (void *data) ++int platform_wifi_request_gpio_irq(void *data) +{ -+ unsigned int irq_num = 0; ++ unsigned int irq_num; + int ret = -1; -+ unsigned int irq_flag = 0; ++ unsigned int irq_flag; + + irq_num = wifi_irq_num(); + @@ -70656,11 +71191,11 @@ index 000000000000..395e351a1cf6 + irq_flag = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL | IORESOURCE_IRQ_SHAREABLE; + + DPRINTF(AML_DEBUG_INFO, "%s(%d) irq_flag=0x%x irq=%d\n", -+ __func__, __LINE__, irq_flag, irq_num); ++ __func__, __LINE__, irq_flag, irq_num); + + do + { -+ ret = request_irq(irq_num, hal_irq_top, irq_flag, "WIFI_INT", data); ++ ret = request_irq(irq_num, hal_irq_top, irq_flag, "WIFI_INT", data); + if (ret < 0) + DPRINTF(AML_DEBUG_ERROR,"%s(%d) request_irq err, ret=%d\n",__func__,__LINE__, ret); + } @@ -70672,7 +71207,7 @@ index 000000000000..395e351a1cf6 +} +#endif + -+void platform_wifi_free_gpio_irq (void *data) ++void platform_wifi_free_gpio_irq(void *data) +{ + DPRINTF(AML_DEBUG_ANDROID,"%s(%d)\n", __func__, __LINE__); + @@ -70689,43 +71224,42 @@ index 000000000000..395e351a1cf6 +static void clk_source_select(int IS_SSV_CLK) +{ + int gpio_clk_sel = amlhal_gpio.clk_sel; -+ int ret = 0; -+ int gpio = 0; ++ int ret; ++ int gpio; + -+ ret = gpio_request(gpio_clk_sel, OWNER_NAME); ++ ret = gpio_request(gpio_clk_sel, OWNER_NAME); + if (ret < 0){ + gpio_free(gpio_clk_sel); -+ ret = gpio_request(gpio_clk_sel, OWNER_NAME); //retry -+ printk("%s(%d) again request gpio_clk_sel ret=%d\n", __func__, __LINE__, ret); ++ ret = gpio_request(gpio_clk_sel, OWNER_NAME); //retry ++ pr_debug("%s(%d) again request gpio_clk_sel ret=%d\n", __func__, __LINE__, ret); + } + + if(IS_SSV_CLK){ + ret = gpio_direction_output(gpio_clk_sel, 1); + gpio = gpio_get_value(gpio_clk_sel); -+ printk("%s(%d) gpio_clk_sel set 1, now=%d##########\n", __func__,__LINE__, gpio); ++ pr_debug("%s(%d) gpio_clk_sel set 1, now=%d##########\n", __func__,__LINE__, gpio); + } + else{ + ret = gpio_direction_output(gpio_clk_sel, 0); + gpio = gpio_get_value(gpio_clk_sel); -+ printk("%s(%d) gpio_clk_sel set 0, now=%d##########\n",__func__,__LINE__, gpio); ++ pr_debug("%s(%d) gpio_clk_sel set 0, now=%d##########\n",__func__,__LINE__, gpio); + } + + gpio_free(gpio_clk_sel); -+ +} + +#if LINUX_VERSION_CODE <= KERNEL_VERSION(3,14,29) -+static void reset_wifi (void) ++static void reset_wifi(void) +{ + /* use gpio reset */ -+ int ret = 0; ++ int ret; + int gpio_wifi_reset = amlhal_gpio.gpio_reset; -+ int gpio = 0; ++ int gpio; + -+ ret = gpio_request(gpio_wifi_reset, OWNER_NAME); ++ ret = gpio_request(gpio_wifi_reset, OWNER_NAME); + if (ret < 0){ + gpio_free(gpio_wifi_reset); -+ ret = gpio_request(gpio_wifi_reset, OWNER_NAME); //retry ++ ret = gpio_request(gpio_wifi_reset, OWNER_NAME); /* retry */ + ERROR_DEBUG_OUT("request gpio fail ret=%d\n", ret); + } + @@ -70735,11 +71269,11 @@ index 000000000000..395e351a1cf6 + ret = gpio_direction_output(gpio_wifi_reset, 0); + OS_MDELAY(20); + gpio = gpio_get_value(gpio_wifi_reset); -+ printk("######gpio_wifi_reset set 0, now=%d#########\n", gpio); ++ pr_debug("######gpio_wifi_reset set 0, now=%d#########\n", gpio); + + ret = gpio_direction_output(gpio_wifi_reset, 1); + gpio = gpio_get_value(gpio_wifi_reset); -+ printk("######gpio_wifi_reset set 1, now=%d#########\n", gpio); ++ pr_debug("######gpio_wifi_reset set 1, now=%d#########\n", gpio); + + gpio_free(gpio_wifi_reset); +} @@ -70783,12 +71317,14 @@ index 000000000000..395e351a1cf6 + +void hi_change_sram_concurrent_mode(void) +{ -+ unsigned int regdata = 0; ++ unsigned int regdata; + struct hw_interface* hif = hif_get_hw_interface(); + +#ifdef SRAM_CONCURRENT +#if (SRAM_16KMODE == 0) -+ //2014 3.4 later FPGA version,need to add the register,because SRAM is used both wifi mac and test bus ++ /* 2014 3.4 later FPGA version,need to add the register, ++ * because SRAM is used both wifi mac and test bus. ++ */ + + regdata = hif->hif_ops.hi_read_word(RG_INTF_RTC_CLK_CTRL); + regdata &= ~BIT(31); @@ -70806,21 +71342,21 @@ index 000000000000..395e351a1cf6 +#endif +} + -+void set_wifi_baudrate (unsigned int apb_clk) ++void set_wifi_baudrate(unsigned int apb_clk) +{ + unsigned int data, uart_div; + unsigned int wifi_dig_timebase; -+ struct hw_interface* hif = hif_get_hw_interface(); ++ struct hw_interface *hif = hif_get_hw_interface(); + -+ //set uart baudrate -+ uart_div = apb_clk/(UART_BAUD_RATE*4)-1; ++ /* set uart baudrate */ ++ uart_div = apb_clk / (UART_BAUD_RATE * 4) - 1; + PRINT("for uart baudrate0x%x\n",apb_clk); + + data = hif->hif_ops.hi_read_word(RG_UART_WORK_MODE); + wifi_dig_timebase = hif->hif_ops.hi_read_word(RG_INTF_CTRL_CLK); + + PRINT("uart mode 0x%x=0x%x\n", RG_UART_WORK_MODE, data); -+ data &= (~(0xfff<<0)); //baudrate, bit0~11 ++ data &= (~(0xfff << 0)); /* baudrate, bit0~11 */ + data |= uart_div; + hif->hif_ops.hi_write_word(RG_UART_WORK_MODE, data); + @@ -70829,14 +71365,14 @@ index 000000000000..395e351a1cf6 +} + +/* -+All valid bits are R/W, the default value is 32h8000_0003 -+[0]: soft reset0, which reset the whole MAC. Its set by software,auto cleaned by -+ hardware when soft reset timer0 times out. Active low. -+[1]: soft reset1, which reset MAC except sd2wifi sub-module. -+Its set by software, auto cleaned by hardware when soft reset timer1 times out. Active low. -+[30:2]: reserved -+[31]: soft_arc_reset, which reset ARC625 core and arc_11n_ram_loader sub-module. -+ Its set and cleaned both by software. Active low. ++ * All valid bits are R/W, the default value is 32h8000_0003 ++ * [0]: soft reset0, which reset the whole MAC. Its set by software,auto cleaned by ++ * hardware when soft reset timer0 times out. Active low. ++ * [1]: soft reset1, which reset MAC except sd2wifi sub-module. ++ * Its set by software, auto cleaned by hardware when soft reset timer1 times out. Active low. ++ * [30:2]: reserved ++ * [31]: soft_arc_reset, which reset ARC625 core and arc_11n_ram_loader sub-module. ++ * Its set and cleaned both by software. Active low. +*/ +int amlhal_resetmac(void) +{ @@ -70857,11 +71393,11 @@ index 000000000000..395e351a1cf6 + hif->hif_ops.hi_write_word(RG_WIFI_RST_CTRL, to_sdio); + + sdio_kptr_val = hif->hif_ops.hi_read_reg8(RG_SCFG_RX_EN); -+ printk("reg0x74 0x%x\n", sdio_kptr_val); ++ pr_debug("reg0x74 0x%x\n", sdio_kptr_val); + sdio_kptr_val &= ~(BIT(2) | BIT(3)); //keep pointer + hif->hif_ops.hi_write_reg8(RG_SCFG_RX_EN, sdio_kptr_val); + sdio_kptr_val =hif->hif_ops.hi_read_reg8(RG_SCFG_RX_EN); -+ printk("reg0x74 0x%x\n", sdio_kptr_val); ++ pr_debug("reg0x74 0x%x\n", sdio_kptr_val); + + hif->hif_ops.hi_write_reg8(RG_SCFG_SELECT_RST,1); + // reg_tmp = 0; @@ -70900,87 +71436,88 @@ index 000000000000..395e351a1cf6 +#if defined (HAL_SIM_VER) +unsigned char hal_set_sys_clk_Core(unsigned int addr, unsigned int value) +{ -+ unsigned int tmp,tmp1; -+//divide config for clock -+ tmp=MAC_RD_REG(addr); -+ tmp=(tmp&~(0xffffffff))|(value); -+ MAC_WR_REG(addr,tmp); ++ unsigned int tmp, tmp1; ++ ++ /* divide config for clock */ ++ tmp = MAC_RD_REG(addr); ++ tmp = (tmp & ~(0xffffffff)) | (value); ++ MAC_WR_REG(addr, tmp); + OS_MDELAY(10); -+//switch clock from osc to real ++ /* switch clock from osc to real */ + tmp=MAC_RD_REG(addr); -+ tmp1 = tmp |(1 << 4); -+ MAC_WR_REG(addr,tmp1); ++ tmp1 = tmp | (1 << 4); ++ MAC_WR_REG(addr, tmp1); + OS_MDELAY(10); +} + +unsigned char hal_set_sys_clk(int clockdiv) +{ -+ unsigned int tmp,tmp1,tmp2,tmp3; ++ unsigned int tmp, tmp1, tmp2, tmp3; + + PRINT("hal_set_sys_clk \n"); -+ /* reset bpll , write 1 for bit0 firstly, then write 0 again*/ ++ /* reset bpll , write 1 for bit0 firstly, then write 0 again*/ + tmp = AON_RD_REG(RG_DPLL_A3); -+ AON_WR_REG(RG_DPLL_A3, (tmp | BIT(0))); ++ AON_WR_REG(RG_DPLL_A3, (tmp | BIT(0))); + OS_MDELAY(10); -+ AON_WR_REG(RG_DPLL_A3, (tmp & ~BIT(0))); ++ AON_WR_REG(RG_DPLL_A3, (tmp & ~BIT(0))); + -+ //select CPU clock by digital divider for 80MHz ++ /* select CPU clock by digital divider for 80MHz */ +#ifdef TX_TIMEOUT_ERR -+ hal_set_sys_clk_Core(RG_INTF_CPU_CLK,TEST_CPU_CLOCK); ++ hal_set_sys_clk_Core(RG_INTF_CPU_CLK, TEST_CPU_CLOCK); +#else -+ //riscv -+ hal_set_sys_clk_Core(RG_INTF_CPU_CLK,0x4f670031); -+ //arc, cpu clock 0x4f070031 ++ /* riscv */ ++ hal_set_sys_clk_Core(RG_INTF_CPU_CLK, 0x4f670031); ++ /* arc, cpu clock 0x4f070031 */ +#endif -+ //select BTCPU clock by digital divider for 48MHz -+ hal_set_sys_clk_Core(RG_INTF_BTCPU_CLK,0x940011); ++ /* select BTCPU clock by digital divider for 48MHz */ ++ hal_set_sys_clk_Core(RG_INTF_BTCPU_CLK, 0x940011); + -+ //config mactxdelay -+ tmp=MAC_RD_REG(RG_MAC_COUNT1); -+ tmp= tmp | (0x7000000 ); -+ MAC_WR_REG(RG_MAC_COUNT1,tmp); ++ /* config mactxdelay */ ++ tmp = MAC_RD_REG(RG_MAC_COUNT1); ++ tmp = tmp | (0x7000000); ++ MAC_WR_REG(RG_MAC_COUNT1, tmp); + OS_MDELAY(10); -+ //config agc gain not use lut -+ tmp=MAC_RD_REG(RG_AGC_GAIN_SEL); -+ tmp= tmp & (~(1<< 24 )); -+ MAC_WR_REG(RG_AGC_GAIN_SEL,tmp); ++ /* config agc gain not use lut */ ++ tmp = MAC_RD_REG(RG_AGC_GAIN_SEL); ++ tmp = tmp & (~(1 << 24)); ++ MAC_WR_REG(RG_AGC_GAIN_SEL, tmp); + OS_MDELAY(10); -+ //switch share 64k ram to mac -+ tmp= 0x00000001; -+ MAC_WR_REG(RG_INTF_SHARE_64K_CAP,tmp); ++ /* switch share 64k ram to mac */ ++ tmp = 0x00000001; ++ MAC_WR_REG(RG_INTF_SHARE_64K_CAP, tmp); + OS_MDELAY(10); -+ //reset mac time rise pulse -+ tmp= 0x81080100; -+ MAC_WR_REG(RG_INTF_MAC_TIMER_CTRL1,tmp); ++ /* reset mac time rise pulse */ ++ tmp = 0x81080100; ++ MAC_WR_REG(RG_INTF_MAC_TIMER_CTRL1, tmp); + OS_MDELAY(10); -+ //gpioB pin mux input -+ tmp= 0xffdfffff; -+ MAC_WR_REG(RG_INTF_PIN_MUX_REG1,tmp); ++ /* gpioB pin mux input */ ++ tmp = 0xffdfffff; ++ MAC_WR_REG(RG_INTF_PIN_MUX_REG1, tmp); + OS_MDELAY(10); + +#ifdef B2B_TEST -+ //pin mux config for b2b -+ tmp= 0x9c03330a; -+ MAC_WR_REG(RG_PHY_BT_CTRL,tmp); ++ /* pin mux config for b2b */ ++ tmp = 0x9c03330a; ++ MAC_WR_REG(RG_PHY_BT_CTRL, tmp); + OS_MDELAY(10); -+ //tx out format -+ //tmp= 0x00000004; -+ tmp= 0x00000002; //bit[1] reg_tx_negate_msb is set to 1 in compliance with FPGA environment -+ //bit[0] reg_tx_iq_swap -+ //bit[1] reg_tx_negate_msb -+ //bit[2] reg_tx_rotate_en is not exist now -+ //bit[5:4] reg_tx_signal_sel -+ MAC_WR_REG(RG_PHY_TX_CTRL,tmp); ++ /* tx out format */ ++ /* tmp= 0x00000004; */ ++ tmp = 0x00000002; /* bit[1] reg_tx_negate_msb is set to 1 in compliance with FPGA environment */ ++ /* bit[0] reg_tx_iq_swap */ ++ /* bit[1] reg_tx_negate_msb */ ++ /* bit[2] reg_tx_rotate_en is not exist now */ ++ /* bit[5:4] reg_tx_signal_sel */ ++ MAC_WR_REG(RG_PHY_TX_CTRL, tmp); + OS_MDELAY(10); -+ //add config for rx enable -+ tmp= 0x00000001; -+ MAC_WR_REG(RG_OFDM_RX_FSM_EN,tmp); ++ /* add config for rx enable */ ++ tmp = 0x00000001; ++ MAC_WR_REG(RG_OFDM_RX_FSM_EN, tmp); + OS_MDELAY(10); + PRINT("B2B_TEST \n"); -+ //add ap/fs config,will delete sw ok -+ if(STA1_VMAC0_SEND_40M==2) ++ /* add ap/fs config,will delete sw ok */ ++ if (STA1_VMAC0_SEND_40M == 2) + { -+ tmp= 0xa1000000; ++ tmp = 0xa1000000; + MAC_WR_REG(RG_PHY_BW_REG, tmp); + OS_MDELAY(10); + } @@ -70995,7 +71532,7 @@ index 000000000000..395e351a1cf6 + return 1; +} + -+unsigned int bbpll_init(void) ++static unsigned int bbpll_init(void) +{ + RG_DPLL_A0_FIELD_T rg_dpll_a0; + RG_DPLL_A1_FIELD_T rg_dpll_a1; @@ -71029,29 +71566,29 @@ index 000000000000..395e351a1cf6 + return 0; +} + -+unsigned int bbpll_start (void) ++static unsigned int bbpll_start (void) +{ -+ //RG_DPLL_A0_FIELD_T rg_dpll_a0; -+ //RG_DPLL_A1_FIELD_T rg_dpll_a1; ++ /* RG_DPLL_A0_FIELD_T rg_dpll_a0; */ ++ /* RG_DPLL_A1_FIELD_T rg_dpll_a1; */ + RG_DPLL_A2_FIELD_T rg_dpll_a2; + RG_DPLL_A3_FIELD_T rg_dpll_a3; + RG_DPLL_A4_FIELD_T rg_dpll_a4; + RG_DPLL_A5_FIELD_T rg_dpll_a5; -+ //RG_DPLL_A6_FIELD_T rg_dpll_a6; ++ /* RG_DPLL_A6_FIELD_T rg_dpll_a6; */ + -+ printk("bbpll power on -------------->\n"); -+ printk("1, start inter Ido \n"); ++ pr_debug("bbpll power on -------------->\n"); ++ pr_debug("1, start inter Ido \n"); + + rg_dpll_a4.data = aml_aon_read_reg(RG_DPLL_A4); + rg_dpll_a4.b.rg_wifi_bb_bt_dac_clk_div = 0x1; -+ rg_dpll_a4.b.rg_wifi_bb_bt_adc_div = 0x5; //for bt adc clock ++ rg_dpll_a4.b.rg_wifi_bb_bt_adc_div = 0x5; /* for bt adc clock */ + aml_aon_write_reg(RG_DPLL_A4, rg_dpll_a4.data); + udelay(50); + rg_dpll_a4.b.rg_wifi_bb_bt_dac_clk_div = 0x3; + aml_aon_write_reg(RG_DPLL_A4, rg_dpll_a4.data); + udelay(10); + -+ printk("2, start pll core \n"); ++ pr_debug("2, start pll core \n"); + + rg_dpll_a3.data = aml_aon_read_reg(RG_DPLL_A3); + rg_dpll_a3.b.rg_wifi_bb_pll_bias_en = 1; @@ -71064,15 +71601,15 @@ index 000000000000..395e351a1cf6 + udelay(80); + rg_dpll_a2.data = aml_aon_read_reg(RG_DPLL_A2); + rg_dpll_a2.b.rg_wifi_bb_pll_reve |= BIT(6); -+ rg_dpll_a2.b.rg_wifi_bb_pll_reve |= BIT(4); //bit18 need pull up ++ rg_dpll_a2.b.rg_wifi_bb_pll_reve |= BIT(4); /* bit18 need pull up */ + aml_aon_write_reg(RG_DPLL_A2, rg_dpll_a2.data); + -+ printk("3, check \n"); ++ pr_debug("3, check \n"); + udelay(10); + rg_dpll_a5.data = aml_aon_read_reg(RG_DPLL_A5); + if (rg_dpll_a5.b.ro_wifi_bb_pll_done == 1) + { -+ printk("bbpll done !\n"); ++ pr_debug("bbpll done !\n"); + return 1; + } + else @@ -71082,13 +71619,12 @@ index 000000000000..395e351a1cf6 + } +} + -+unsigned int bbpll_stop(void) ++static unsigned int bbpll_stop(void) +{ -+ + RG_DPLL_A3_FIELD_T rg_dpll_a3; + RG_DPLL_A4_FIELD_T rg_dpll_a4; + -+ printk("bbpll power down -------------->\n"); ++ pr_debug("bbpll power down -------------->\n"); + rg_dpll_a3.data = aml_aon_read_reg(RG_DPLL_A3); + rg_dpll_a3.b.rg_wifi_bb_pll_bias_en = 0; + aml_aon_write_reg(RG_DPLL_A3, rg_dpll_a3.data); @@ -71107,14 +71643,15 @@ index 000000000000..395e351a1cf6 + return 0; +} + -+//0x4f070031: switch to bbp clk -+void wifi_cpu_clk_switch(unsigned int clk_cfg) ++/* 0x4f070031: switch to bbp clk */ ++static void wifi_cpu_clk_switch(unsigned int clk_cfg) +{ -+ struct hw_interface *hif = hif_get_hw_interface(); ++ struct hw_interface *hif = hif_get_hw_interface(); ++ + hif->hif_ops.hi_write_word(RG_INTF_CPU_CLK,clk_cfg); + -+ printk("%s(%d):cpu_clk_reg=0x%08x\n", __func__, __LINE__, -+ hif->hif_ops.hi_read_word(RG_INTF_CPU_CLK)); ++ pr_debug("%s(%d):cpu_clk_reg=0x%08x\n", __func__, __LINE__, ++ hif->hif_ops.hi_read_word(RG_INTF_CPU_CLK)); +} + +#endif @@ -71128,12 +71665,12 @@ index 000000000000..395e351a1cf6 +{ + unsigned char *bufferICCM; + unsigned char *bufferDCCM; -+ int len =0; -+ int offset =0; ++ int len; ++ int offset; + int offset_base = 0; + int rd_offset = 0; + SYS_TYPE databyte = 0; -+ unsigned int regdata =0; ++ unsigned int regdata; + struct hw_interface *hif = hif_get_hw_interface(); + unsigned int to_sdio = ~(0); + RG_PMU_A22_FIELD_T pmu_a22; @@ -71142,38 +71679,37 @@ index 000000000000..395e351a1cf6 + bufferICCM = fwICCM; + bufferDCCM = fwDCCM; + -+ hif->hif_ops.hi_write_reg32(RG_SCFG_SRAM_FUNC,MAC_REG_BASE); -+ hif->hif_ops.hi_write_reg32(RG_SCFG_SRAM_FUNC,MAC_ICCM_AHB_BASE); -+ hif->hif_ops.hi_write_reg32(RG_SCFG_REG_FUNC,MAC_REG_BASE); -+ hif->hif_ops.hi_write_reg32(RG_SCFG_EEPROM_FUNC,MAC_REG_BASE); ++ hif->hif_ops.hi_write_reg32(RG_SCFG_SRAM_FUNC, MAC_REG_BASE); ++ hif->hif_ops.hi_write_reg32(RG_SCFG_SRAM_FUNC, MAC_ICCM_AHB_BASE); ++ hif->hif_ops.hi_write_reg32(RG_SCFG_REG_FUNC, MAC_REG_BASE); ++ hif->hif_ops.hi_write_reg32(RG_SCFG_EEPROM_FUNC, MAC_REG_BASE); + -+ // close phy rest ++ /* close phy rest */ + hif->hif_ops.hi_write_word(RG_WIFI_RST_CTRL, to_sdio); -+ PRINT("RG_SCFG_SRAM_FUNC %lx \n",hif->hif_ops.hi_read_reg32(RG_SCFG_SRAM_FUNC)); ++ PRINT("RG_SCFG_SRAM_FUNC %lx \n", hif->hif_ops.hi_read_reg32(RG_SCFG_SRAM_FUNC)); + +#ifdef EFUSE_ENABLE + efuse_init(); -+ printk("%s(%d): called efuse init\n", __func__, __LINE__); ++ pr_debug("%s(%d): called efuse init\n", __func__, __LINE__); +#endif + +#ifdef HAL_FPGA_VER -+ hif->hif_ops.hi_write_reg32(RG_SCFG_SRAM_FUNC,MAC_REG_BASE); ++ hif->hif_ops.hi_write_reg32(RG_SCFG_SRAM_FUNC, MAC_REG_BASE); + + rg_dpll_a5.data = aml_aon_read_reg(RG_DPLL_A5); -+ /*bpll not init*/ ++ /* bpll not init */ + if (rg_dpll_a5.b.ro_wifi_bb_pll_done != 1) { + bbpll_init(); + bbpll_start(); -+ printk("bbpll init ok!\n"); -+ ++ pr_debug("bbpll init ok!\n"); + } else { + ERROR_DEBUG_OUT("bbpll already init,not need to init!\n"); + } + + hal_set_sys_clk_for_fpga(); -+ hif->hif_ops.hi_write_reg32(RG_SCFG_SRAM_FUNC,MAC_ICCM_AHB_BASE); -+ len = ALIGN(sizeof(fwICCM),4); -+ printk("%s(%d): img len 0x%x, start download fw\n", __func__, __LINE__, len); ++ hif->hif_ops.hi_write_reg32(RG_SCFG_SRAM_FUNC, MAC_ICCM_AHB_BASE); ++ len = ALIGN(sizeof(fwICCM), 4); ++ pr_debug("%s(%d): img len 0x%x, start download fw\n", __func__, __LINE__, len); +#else + hif->hif_ops.hi_write_reg32(RG_SCFG_SRAM_FUNC,MAC_REG_BASE); + hal_set_sys_clk(10); @@ -71201,18 +71737,19 @@ index 000000000000..395e351a1cf6 + } + + hif->hif_ops.hi_write_sram(bufferICCM + offset + offset_base, -+ (unsigned char*)(SYS_TYPE)(0 + offset), databyte); ++ (unsigned char*)(SYS_TYPE)offset, ++ databyte); + + offset += databyte; + len -= databyte; + } while(len > 0); + +#ifdef ICCM_CHECK -+ offset_base =0; ++ offset_base = 0; + offset = ICCM_ROM_LEN; + len = ICCM_CHECK_LEN; -+ hif->hif_ops.hi_write_reg32(RG_SCFG_SRAM_FUNC,MAC_ICCM_AHB_BASE); -+ //host rom read ++ hif->hif_ops.hi_write_reg32(RG_SCFG_SRAM_FUNC, MAC_ICCM_AHB_BASE); ++ /* host rom read */ + do { + databyte = (len > SRAM_MAX_LEN) ? SRAM_MAX_LEN : len; + @@ -71223,7 +71760,8 @@ index 000000000000..395e351a1cf6 + } + + hif->hif_ops.hi_read_sram(buf_iccm_rd + rd_offset, -+ (unsigned char*)(SYS_TYPE)(0 + offset) ,databyte); ++ (unsigned char*)(SYS_TYPE)offset, ++ databyte); + + offset += databyte; + rd_offset += databyte; @@ -71233,7 +71771,6 @@ index 000000000000..395e351a1cf6 + if (memcmp(buf_iccm_rd, (bufferICCM + ICCM_ROM_LEN), ICCM_CHECK_LEN)) { + ERROR_DEBUG_OUT("Host HAL: write ICCM ERROR!!!! \n"); + return false; -+ + } else { + PRINT("Host HAL: write ICCM SUCCESS!!!! \n"); + } @@ -71254,16 +71791,16 @@ index 000000000000..395e351a1cf6 + } while(len > 0); + + /* Starting run firmware */ -+ //set baseaddr to sram ++ /* set baseaddr to sram */ + hif->hif_ops.hi_write_reg32(RG_SCFG_SRAM_FUNC, MAC_REG_BASE); + len = SRAM_LEN; + memset(bufferDCCM, 0, len); + PRINT("set sram zero for simulation, total=0x%x\n", len); + hif->hif_ops.hi_write_sram(bufferDCCM, (unsigned char*)(SYS_TYPE)MAC_SRAM_BASE, len); + -+ //configure sram space ++ /* configure sram space */ + hi_cfg_firmware(); -+ //set func2 baseaddr ++ /* set func2 baseaddr */ + hif->hif_ops.hi_write_reg32(RG_SCFG_SRAM_FUNC, MAC_REG_BASE); + + regdata = hif->hif_ops.hi_read_reg32(RG_SCFG_REG_FUNC); @@ -71276,25 +71813,25 @@ index 000000000000..395e351a1cf6 + wifi_cpu_clk_switch(0x4f0700f3); +#endif + -+ /* arc cpu domain power save for t9026 */ ++ /* arc cpu domain power save for t9026 */ + if (0) { -+ //cpu select arc -+ //enable cpu ++ /* cpu select arc */ ++ /* enable cpu */ + regdata = hif->hif_ops.hi_read_word(RG_WIFI_MAC_ARC_CTRL); + /* start firmware chip cpu */ + regdata |= CPU_RUN; + hif->hif_ops.hi_write_word(RG_WIFI_MAC_ARC_CTRL, regdata); + } else { -+ //cpu select riscv -+ regdata = hif->hif_ops.hi_read_word(RG_WIFI_CPU_CTRL); -+ regdata |= 0x10000; -+ hif->hif_ops.hi_write_word(RG_WIFI_CPU_CTRL,regdata); -+ PRINT("RG_WIFI_CPU_CTRL = %x redata= %x \n",RG_WIFI_CPU_CTRL,regdata); -+ //enable cpu -+ pmu_a22.data = hif->hif_ops.bt_hi_read_word(RG_PMU_A22); -+ pmu_a22.b.rg_dev_reset_sw = 0x00; -+ hif->hif_ops.bt_hi_write_word(RG_PMU_A22,pmu_a22.data); -+ PRINT("RG_PMU_A22 = %x redata= %x \n",RG_PMU_A22,pmu_a22.data); ++ /* cpu select riscv */ ++ regdata = hif->hif_ops.hi_read_word(RG_WIFI_CPU_CTRL); ++ regdata |= 0x10000; ++ hif->hif_ops.hi_write_word(RG_WIFI_CPU_CTRL, regdata); ++ PRINT("RG_WIFI_CPU_CTRL = %x redata= %x \n", RG_WIFI_CPU_CTRL, regdata); ++ /* enable cpu */ ++ pmu_a22.data = hif->hif_ops.bt_hi_read_word(RG_PMU_A22); ++ pmu_a22.b.rg_dev_reset_sw = 0x00; ++ hif->hif_ops.bt_hi_write_word(RG_PMU_A22, pmu_a22.data); ++ PRINT("RG_PMU_A22 = %x redata= %x \n", RG_PMU_A22, pmu_a22.data); + } + +#elif defined (PROJECT_W1) @@ -71312,19 +71849,19 @@ index 000000000000..395e351a1cf6 + hif->hif_ops.hi_write_word(RG_WIFI_IF_RXPAGE_BUF_RDPTR, 0); + hif->hif_ops.hi_write_word(RG_WIFI_IF_MAC_TXTABLE_RD_ID, 0); + -+ //cpu select riscv ++ /* cpu select riscv */ + regdata = hif->hif_ops.hi_read_word(RG_WIFI_CPU_CTRL); + regdata |= 0x10000; -+ hif->hif_ops.hi_write_word(RG_WIFI_CPU_CTRL,regdata); -+ PRINT("RG_WIFI_CPU_CTRL = %x redata= %x \n",RG_WIFI_CPU_CTRL,regdata); -+ //enable cpu ++ hif->hif_ops.hi_write_word(RG_WIFI_CPU_CTRL, regdata); ++ PRINT("RG_WIFI_CPU_CTRL = %x redata= %x \n", RG_WIFI_CPU_CTRL, regdata); ++ /* enable cpu */ + pmu_a22.data = hif->hif_ops.bt_hi_read_word(RG_PMU_A22); + pmu_a22.b.rg_dev_reset_sw = 0x00; -+ hif->hif_ops.bt_hi_write_word(RG_PMU_A22,pmu_a22.data); -+ PRINT("RG_PMU_A22 = %x redata= %x \n",RG_PMU_A22,pmu_a22.data); ++ hif->hif_ops.bt_hi_write_word(RG_PMU_A22, pmu_a22.data); ++ PRINT("RG_PMU_A22 = %x redata= %x \n", RG_PMU_A22, pmu_a22.data); +#endif + -+ printk("fw download success!\n"); ++ pr_debug("fw download success!\n"); +#ifdef SDIO_BUILD_IN + wifi_in_insmod = 0; +#endif @@ -71332,7 +71869,6 @@ index 000000000000..395e351a1cf6 + return true; +} + -+ +#if defined (HAL_FPGA_VER) +int mac_addr0 = 0x00; +int mac_addr1 = 0x01; @@ -71343,12 +71879,12 @@ index 000000000000..395e351a1cf6 + +static int vif0opmode = -1; +static int vif1opmode = -1; -+static char * vmac0 = "wlan0"; -+static char * vmac1 = "p2p0"; ++static char *vmac0 = "wlan0"; ++static char *vmac1 = "p2p0"; +static unsigned int con_mode = ((1 << WIFINET_M_STA) | (1 << WIFINET_M_P2P_DEV)); +static int en_rf_test = 0; + -+static char * plt_ver = NULL; ++static char *plt_ver = NULL; +struct version_info version_map[] = { + {"gva", VERSION_GVA}, + {"gva_mrt", VERSION_GVA_MRT} @@ -71356,9 +71892,9 @@ index 000000000000..395e351a1cf6 +}; + +int aml_debug = AML_DEBUG_LEVEL; -+const unsigned char BROADCAST_ADDRESS[WIFINET_ADDR_LEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; -+static char * mac_addr = "00:01:02:58:00:CC"; -+static char * country_code = "WW"; ++const unsigned char BROADCAST_ADDRESS[WIFINET_ADDR_LEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; ++static char *mac_addr = "00:01:02:58:00:CC"; ++static char *country_code = "WW"; +unsigned short dhcp_offload = 0; +static int sdblksize = BLKSIZE; +unsigned char aml_insmod_flag = 0; @@ -71381,15 +71917,13 @@ index 000000000000..395e351a1cf6 +#ifdef CONFIG_MAC_SUPPORT + u8 addr[ETH_ALEN]; + u8 cbuf[50]; -+ unsigned int efuse_data_l = 0; -+ unsigned int efuse_data_h = 0; -+ +#if defined(NOT_AMLOGIC_PLATFORM) + memset(addr, 0xff, ETH_ALEN); +#else + memcpy(addr, wifi_get_mac(), ETH_ALEN); +#endif -+ if (addr[0] != 0xff || aml_read_macaddr_from_file(WIFIMAC_PATH, addr) == true) { ++ if (addr[0] != 0xff || ++ aml_read_macaddr_from_file(WIFIMAC_PATH, addr) == true) { + mac_addr0 = addr[0]; + mac_addr1 = addr[1]; + mac_addr2 = addr[2]; @@ -71397,8 +71931,12 @@ index 000000000000..395e351a1cf6 + mac_addr4 = addr[4]; + mac_addr5 = addr[5]; + } else { ++ unsigned int efuse_data_l; ++ unsigned int efuse_data_h; ++ + efuse_data_l = efuse_manual_read(0x1); + efuse_data_h = efuse_manual_read(0x2); ++ + if ((efuse_data_h != 0) && (efuse_data_l != 0)) { + mac_addr0 = (efuse_data_h & 0xff00) >> 8; + mac_addr1 = efuse_data_h & 0x00ff; @@ -71408,9 +71946,10 @@ index 000000000000..395e351a1cf6 + mac_addr5 = efuse_data_l & 0xff; + aml_retrieve_from_file(WIFIMAC_PATH, cbuf, 48); + -+ sprintf(cbuf + 21, MAC_FMT, mac_addr0, mac_addr1, mac_addr2, mac_addr3, mac_addr4, mac_addr5); ++ sprintf(cbuf + 21, MAC_FMT, mac_addr0, mac_addr1, mac_addr2, ++ mac_addr3, mac_addr4, mac_addr5); + if (aml_store_to_file(WIFIMAC_PATH, cbuf, strlen(cbuf)) > 0) { -+ printk("write the efuse mac to wifimac.txt\n"); ++ pr_debug("write the efuse mac to wifimac.txt\n"); + } + } else { +#endif @@ -71421,29 +71960,31 @@ index 000000000000..395e351a1cf6 +#ifdef CONFIG_MAC_SUPPORT + aml_retrieve_from_file(WIFIMAC_PATH, cbuf, 48); + -+ sprintf(cbuf + 21, MAC_FMT, mac_addr0, mac_addr1, mac_addr2, mac_addr3, mac_addr4, mac_addr5); ++ sprintf(cbuf + 21, MAC_FMT, mac_addr0, mac_addr1, mac_addr2, ++ mac_addr3, mac_addr4, mac_addr5); + if (aml_store_to_file(WIFIMAC_PATH, cbuf, strlen(cbuf)) > 0) -+ printk("write the random mac to wifimac.txt\n"); ++ pr_debug("write the random mac to wifimac.txt\n"); + } + } +#endif + + if (mac_addr0 & 0x3) { -+ printk("change the mac addr from [0x%x] ", mac_addr0); ++ pr_debug("change the mac addr from [0x%x] ", mac_addr0); + + mac_addr0 &= ~0x3; -+ printk("to [0x%x] \n", mac_addr0); ++ pr_debug("to [0x%x] \n", mac_addr0); +#ifdef CONFIG_MAC_SUPPORT + aml_retrieve_from_file(WIFIMAC_PATH, cbuf, 48); + -+ sprintf(cbuf + 21, MAC_FMT, mac_addr0, mac_addr1, mac_addr2, mac_addr3, mac_addr4, mac_addr5); ++ sprintf(cbuf + 21, MAC_FMT, mac_addr0, mac_addr1, mac_addr2, ++ mac_addr3, mac_addr4, mac_addr5); + if (aml_store_to_file(WIFIMAC_PATH, cbuf, strlen(cbuf)) > 0) -+ printk("write the random mac to wifimac.txt\n"); ++ pr_debug("write the random mac to wifimac.txt\n"); +#endif + } +} + -+char * aml_wifi_get_country_code(void) ++char *aml_wifi_get_country_code(void) +{ + return country_code; +} @@ -71458,12 +71999,12 @@ index 000000000000..395e351a1cf6 + return vif1opmode; +} + -+char * aml_wifi_get_vif0_name(void) ++char *aml_wifi_get_vif0_name(void) +{ + return vmac0; +} + -+char * aml_wifi_get_vif1_name(void) ++char *aml_wifi_get_vif1_name(void) +{ + return vmac1; +} @@ -71473,12 +72014,27 @@ index 000000000000..395e351a1cf6 + return con_mode; +} + -+char * aml_wifi_get_bus_type(void) ++void aml_wifi_set_con_mode(void *wifimac) ++{ ++ unsigned int concurrent_mode = 0; ++ struct drv_private *drv_priv = ((struct wifi_mac *)wifimac)->drv_priv; ++ struct wlan_net_vif *main_vmac = drv_priv->drv_wnet_vif_table[NET80211_MAIN_VMAC]; ++ struct wlan_net_vif *p2p_vmac = drv_priv->drv_wnet_vif_table[NET80211_P2P_VMAC]; ++ ++ concurrent_mode = BIT(main_vmac->vm_opmode) | BIT(p2p_vmac->vm_opmode); ++ if (con_mode != concurrent_mode) { ++ con_mode = concurrent_mode; ++ AML_OUTPUT("con_mode = 0x%02x",con_mode); ++ } ++ ++} ++ ++char *aml_wifi_get_bus_type(void) +{ + return hif_type; +} + -+char * aml_wifi_get_fw_type(void) ++char *aml_wifi_get_fw_type(void) +{ + unsigned int regdata = hi_get_fw_version(); + if (regdata == FW_VERSION_W1) { @@ -71496,15 +72052,17 @@ index 000000000000..395e351a1cf6 +unsigned int aml_wifi_get_platform_verid(void) +{ + int i; ++ + if (plt_ver == NULL) + { + return 0; + } ++ + for (i = 0; i < sizeof(version_map)/sizeof(struct version_info); ++i) + { + if (strcmp(version_map[i].version_name, plt_ver) == 0) + { -+ //printk("%s(%d) version name: %s\n", __func__, __LINE__, version_map[i].version_name); ++ /* pr_debug("%s(%d) version name: %s\n", __func__, __LINE__, version_map[i].version_name); */ + return version_map[i].version_id; + } + } @@ -71528,8 +72086,8 @@ index 000000000000..395e351a1cf6 +#endif + + print_driver_version(); -+ printk("driver version: %s\n", DRIVERVERSION); -+ printk("%s(%d) dhcp_offload %d set done.\n\n", ++ pr_info("driver version: %s\n", DRIVERVERSION); ++ pr_debug("%s(%d) dhcp_offload %d set done.\n\n", + __func__,__LINE__, dhcp_offload); + +#ifdef DEBUG_MALLOC @@ -71552,13 +72110,13 @@ index 000000000000..395e351a1cf6 + } + + if (aml_wifi_is_enable_rf_test()) { -+ printk("---Aml drv---:Before calling %s:(%d) \n",__func__,__LINE__); ++ pr_debug("---Aml drv---:Before calling %s:(%d) \n",__func__,__LINE__); + Init_B2B_Resource(); + } + + aml_insmod_flag = 1; + -+ printk("%s(%d) start...\n",__func__, __LINE__); ++ pr_debug("%s(%d) start...\n",__func__, __LINE__); + return 0; + +insmod_failed: @@ -71577,20 +72135,22 @@ index 000000000000..395e351a1cf6 +#ifdef SDIO_BUILD_IN + wifi_in_rmmod = 1; +#endif -+ printk("===================aml_rmmod start====================\n"); ++ pr_debug("===================aml_rmmod start====================\n"); + hal_exit_priv(); -+ printk("===================aml_rmmod end====================\n"); ++ pr_debug("===================aml_rmmod end====================\n"); + aml_insmod_flag = 0; + +#ifdef DEBUG_MALLOC -+ printk("kmalloc_count:%d\n", kmalloc_count); ++ pr_debug("kmalloc_count:%d\n", kmalloc_count); + for (i = 0; i < kmalloc_count; ++i) { -+ printk("malloc name:%s, count:%d\n", m_pn_buf[i].name, m_pn_buf[i].count); ++ pr_debug("malloc name:%s, count:%d\n", m_pn_buf[i].name, ++ m_pn_buf[i].count); + } + -+ printk("kfree_count:%d\n", kfree_count); ++ pr_debug("kfree_count:%d\n", kfree_count); + for (i = 0; i < kfree_count; ++i) { -+ printk("free name:%s, count:%d\n", f_pn_buf[i].name, f_pn_buf[i].count); ++ pr_debug("free name:%s, count:%d\n", f_pn_buf[i].name, ++ f_pn_buf[i].count); + } +#endif +#ifdef SDIO_BUILD_IN @@ -71613,19 +72173,19 @@ index 000000000000..395e351a1cf6 +module_param(en_rf_test, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); + + -+/*Added for pass mac address when load wifi driver -+ *Usage: insmod ***.ko mac_addr=xx:xx:xx:xx:xx:xx -+ *Default: 00:01:02:58:00:12 -+*/ -+module_param(mac_addr,charp,0644); -+MODULE_PARM_DESC(mac_addr,"A string variable to describe wifi mac address"); ++/* Added for pass mac address when load wifi driver ++ * Usage: insmod ***.ko mac_addr=xx:xx:xx:xx:xx:xx ++ * Default: 00:01:02:58:00:12 ++ */ ++module_param(mac_addr, charp, 0644); ++MODULE_PARM_DESC(mac_addr, "A string variable to describe wifi mac address"); + +module_param(dhcp_offload, ushort, S_IRUGO); -+MODULE_PARM_DESC(dhcp_offload,"A short variable to control dhcp offload function"); ++MODULE_PARM_DESC(dhcp_offload, "A short variable to control dhcp offload function"); + -+/*Usage: insmod ***.ko country_code=xx*/ ++/* Usage: insmod ***.ko country_code=xx */ + -+module_param(country_code,charp,0644); ++module_param(country_code, charp, 0644); +MODULE_PARM_DESC(country_code,"A string variable to describe country code"); + + @@ -71638,7 +72198,7 @@ index 000000000000..395e351a1cf6 +#endif //#ifdef CONFIG_GXL diff --git a/drivers/net/wireless/w1/vmac/wifi_hal_platform.h b/drivers/net/wireless/w1/vmac/wifi_hal_platform.h new file mode 100644 -index 000000000000..0cd4514c8a00 +index 0000000000000000000000000000000000000000..a8fb3f8de4b6a7a0c7afeec875697693343df03e --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_hal_platform.h @@ -0,0 +1,53 @@ @@ -71693,14 +72253,14 @@ index 000000000000..0cd4514c8a00 +extern char *aml_wifi_get_fw_type(void); +extern unsigned int aml_wifi_is_enable_rf_test(void); +extern void aml_w1_fw_recovery(void); -+ ++extern void aml_wifi_set_con_mode(void *wifimac); +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_hal_txdesc.c b/drivers/net/wireless/w1/vmac/wifi_hal_txdesc.c new file mode 100644 -index 000000000000..89c7df978490 +index 0000000000000000000000000000000000000000..6ea3f583cf2275b7baefc4767d4ab79db996be3d --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_hal_txdesc.c -@@ -0,0 +1,1129 @@ +@@ -0,0 +1,1130 @@ +/* + **************************************************************************************** + * @@ -71721,6 +72281,7 @@ index 000000000000..89c7df978490 +#endif +#endif + ++#include "wifi_hal_cmd.h" +#include "wifi_hal_com.h" +#include "wifi_hal.h" +#include "wifi_hal_txdesc.h" @@ -72082,7 +72643,7 @@ index 000000000000..89c7df978490 + return ( IS_OFMD_RATE(rate) ? 20: ((preambletype==PREAMBLE_SHORT)?96:192) ); +} + -+unsigned char Hal_TxDescriptor_GetAckRate( unsigned char data_rate ) ++static unsigned char Hal_TxDescriptor_GetAckRate( unsigned char data_rate ) +{ + if (IS_HT_RATE(data_rate) ) + { @@ -72103,7 +72664,7 @@ index 000000000000..89c7df978490 + } +} + -+unsigned char Hal_TxDescriptor_GetRtsRate( unsigned char data_rate ) ++static unsigned char Hal_TxDescriptor_GetRtsRate( unsigned char data_rate ) +{ + if (IS_HT_RATE(data_rate) ) + { @@ -72192,7 +72753,7 @@ index 000000000000..89c7df978490 +} + +/*get ht frame tx time ,don't contain Signal Extension*/ -+unsigned short hal_txdescriptor_ht_gettxTime(unsigned char mcs ,unsigned short pktlen, ++static unsigned short hal_txdescriptor_ht_gettxTime(unsigned char mcs ,unsigned short pktlen, + unsigned char shortGI,unsigned char bw,unsigned char green) +{ + unsigned int nbits = 0; @@ -72221,8 +72782,8 @@ index 000000000000..89c7df978490 +} + +/*get vht frame tx time ,don't contain Signal Extension*/ -+unsigned short Hal_TxDescriptor_VHT_GetTxTime(unsigned char mcs ,unsigned short pktlen, -+ unsigned char shortGI, unsigned char bandwith, unsigned char green) ++static unsigned short Hal_TxDescriptor_VHT_GetTxTime(unsigned char mcs ,unsigned short pktlen, ++ unsigned char shortGI, unsigned char bandwidth, unsigned char green) +{ + unsigned int nbits = 0; + unsigned short duration,nsymbits,nsymbols; @@ -72232,10 +72793,10 @@ index 000000000000..89c7df978490 + * find number of symbols: PLCP + data + */ + nbits = (pktlen << 3) + OFDM_PLCP_BITS; -+ nsymbits = vht_bits_per_symbol[mcs][bandwith]; ++ nsymbits = vht_bits_per_symbol[mcs][bandwidth]; + + if (nsymbits == 0) { -+ printk("Hal_TxDescriptor_VHT_GetTxTime warming nsymbits=%d, bw=%d, mcs=%d\n ", nsymbits, bandwith, mcs); ++ pr_debug("Hal_TxDescriptor_VHT_GetTxTime warming nsymbits=%d, bw=%d, mcs=%d\n ", nsymbits, bandwidth, mcs); + nsymbols = 1; + + } else { @@ -72275,7 +72836,7 @@ index 000000000000..89c7df978490 + return duration; +} + -+unsigned short Hal_TxDescriptor_GetDuration( unsigned char rate, unsigned short length ) ++static unsigned short Hal_TxDescriptor_GetDuration( unsigned char rate, unsigned short length ) +{ + unsigned short duration =0; + length *= 8; @@ -72295,7 +72856,7 @@ index 000000000000..89c7df978490 + return duration; +} +/*get legacy frame tx time*/ -+unsigned short Hal_TxDescriptor_GetLegacyTxTime(unsigned char data_rate, ++static unsigned short Hal_TxDescriptor_GetLegacyTxTime(unsigned char data_rate, + unsigned short pktlen,unsigned char preambletype ) +{ + return Hal_TxDescriptor_GetPreamble( data_rate,preambletype )// data frame @@ -72317,7 +72878,7 @@ index 000000000000..89c7df978490 + +} + -+unsigned short Hal_TxDescriptor_GetAckTimeout( unsigned char data_rate,unsigned char preambletype) ++static unsigned short Hal_TxDescriptor_GetAckTimeout( unsigned char data_rate,unsigned char preambletype) +{ + if (IS_HT_RATE(data_rate) || IS_VHT_RATE(data_rate)) { + return 80 + PHY_TEST; @@ -72328,7 +72889,7 @@ index 000000000000..89c7df978490 + + +/*+SIGNAL_EXTENSION_VALUE+TXTIME(pclp+data+signalextension)*/ -+unsigned short Hal_TxDescriptor_GetAckTime( ++static unsigned short Hal_TxDescriptor_GetAckTime( + unsigned char data_rate , + unsigned char preambletype, + unsigned char b_shortGI, @@ -72357,7 +72918,7 @@ index 000000000000..89c7df978490 + } +} + -+unsigned short Hal_TxDescriptor_GetBATime( ++static unsigned short Hal_TxDescriptor_GetBATime( + unsigned char data_rate, + unsigned char preambletype, + unsigned char b_shortGI, @@ -72391,7 +72952,7 @@ index 000000000000..89c7df978490 + } +} + -+unsigned int Hal_TxDescriptor_GetTxTime(struct hi_agg_tx_desc* HiTxDesc) ++static unsigned int Hal_TxDescriptor_GetTxTime(struct hi_agg_tx_desc* HiTxDesc) +{ + //fixme :need to add signal extern + if (IS_HT_RATE(DESC_RATE)) { @@ -72415,7 +72976,7 @@ index 000000000000..89c7df978490 + } +} + -+__INLINE unsigned int Hal_TxDescriptor_GetTxTimeBA(struct hi_agg_tx_desc* HiTxDesc) ++static __INLINE unsigned int Hal_TxDescriptor_GetTxTimeBA(struct hi_agg_tx_desc* HiTxDesc) +{ + return Hal_TxDescriptor_GetTxTime( HiTxDesc) + +Hal_TxDescriptor_GetBATime(DESC_RATE,DESC_PREMBLETYPE,DESC_IS_SHORTGI,DESC_RIFS, DESC_BANDWIDTH); @@ -72476,7 +73037,7 @@ index 000000000000..89c7df978490 + } else { + PN = (unsigned long long *)hal_priv->uRepCnt[vid][sta_id].txPN[TX_UNICAST_REPCNT_ID]; + } -+ //printk("zy:pn=0x%x\n",*PN); ++ //pr_debug("zy:pn=0x%x\n",*PN); + switch (encrypt_type) { + case WIFI_TKIP: + memcpy(&tx_page->TxOption.PN[0],(unsigned char *)PN, 8); @@ -72513,7 +73074,7 @@ index 000000000000..89c7df978490 + struct wifi_qos_frame *wh = NULL; + unsigned char is_bc; + -+ //printk("%s(%d) bw 0x%x\n", __func__, __LINE__, bw); ++ //pr_debug("%s(%d) bw 0x%x\n", __func__, __LINE__, bw); + + tmp_dot11_preamble_type = (DESC_RATE==WIFI_11B_1M) ? PREAMBLE_LONG:wifi_conf_mib.dot11PreambleType; + @@ -72765,7 +73326,7 @@ index 000000000000..89c7df978490 + } + + max_data_field_tx_time = 4095 - preamble_time; -+ // printk("preamble_time =%d\n", preamble_time); ++ // pr_debug("preamble_time =%d\n", preamble_time); + if( !short_gi ) + { + max_symbol_number = max_data_field_tx_time>>2; /*long gi every symbol time is 4 us*/ @@ -72775,7 +73336,7 @@ index 000000000000..89c7df978490 + max_symbol_number = max_data_field_tx_time*10/36; /*short gi every ofdm symbol time is 3.6us*/ + } + -+ //printk("max_symbol_number =%d\n", max_symbol_number); ++ //pr_debug("max_symbol_number =%d\n", max_symbol_number); + mcs = GET_MCS(rate); + if ((mcs > 9) || (bw > 2)) + { @@ -72785,7 +73346,7 @@ index 000000000000..89c7df978490 + + if ((mcs == 9) && (bw == 0)) + { -+ /*vht 20M bandwith have not mcs9 rate*/ ++ /*vht 20M bandwidth have not mcs9 rate*/ + mcs = 8; + } + @@ -72799,12 +73360,12 @@ index 000000000000..89c7df978490 + mcs = 7; + } + -+ //printk("mcs =%d, bw=%d, NDBPS=%d\n", mcs, bw,ht_bits_per_symbol[mcs][bw]); ++ //pr_debug("mcs =%d, bw=%d, NDBPS=%d\n", mcs, bw,ht_bits_per_symbol[mcs][bw]); + return ht_bits_per_symbol[mcs][bw]*max_symbol_number >> 3; + } + else + { -+ //printk("mcs =%d, bw=%d, NDBPS=%d\n", mcs, bw,vht_bits_per_symbol[mcs][bw]); ++ //pr_debug("mcs =%d, bw=%d, NDBPS=%d\n", mcs, bw,vht_bits_per_symbol[mcs][bw]); + return vht_bits_per_symbol[mcs][bw]*max_symbol_number>>3; + } +} @@ -72832,7 +73393,7 @@ index 000000000000..89c7df978490 +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_hal_txdesc.h b/drivers/net/wireless/w1/vmac/wifi_hal_txdesc.h new file mode 100644 -index 000000000000..4053c19a8cdd +index 0000000000000000000000000000000000000000..4053c19a8cdd8d9b2fac8778756ed2b8b90d15d2 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_hal_txdesc.h @@ -0,0 +1,25 @@ @@ -72863,10 +73424,10 @@ index 000000000000..4053c19a8cdd +#endif//_AML_TXDESC_H_ diff --git a/drivers/net/wireless/w1/vmac/wifi_hif.c b/drivers/net/wireless/w1/vmac/wifi_hif.c new file mode 100644 -index 000000000000..1727d4a3ea37 +index 0000000000000000000000000000000000000000..826e20a0b44d91f57b0b320079f9293678e3b1c9 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_hif.c -@@ -0,0 +1,1860 @@ +@@ -0,0 +1,1944 @@ +/* +* +* Copyright (C) 2008 Amlogic Inc. All Rights Reserved. @@ -72899,11 +73460,11 @@ index 000000000000..1727d4a3ea37 +#include +#include +#include -+ #endif ++#endif +#include "wifi_common.h" + +static struct hw_interface g_hw_interface; -+struct hw_interface* hif_get_hw_interface(void) ++struct hw_interface* hif_get_hw_interface(void) +{ + return &g_hw_interface; +} @@ -72912,7 +73473,8 @@ index 000000000000..1727d4a3ea37 +{ + struct amlw_hif_ops* ops = &g_hw_interface.hif_ops; +#ifdef SDIO_BUILD_IN -+ memcpy(&g_hw_interface.hif_ops, &g_w1_hif_ops, sizeof(struct amlw_hif_ops)); ++ memcpy(&g_hw_interface.hif_ops, &g_w1_hif_ops, ++ sizeof(struct amlw_hif_ops)); +#endif + +#ifndef SDIO_BUILD_IN @@ -72963,23 +73525,20 @@ index 000000000000..1727d4a3ea37 +#endif +void b2b_rx_throughput_calc(HW_RxDescripter_bit *RxPrivHdr) +{ -+ static int rx_count=0; -+ static unsigned long length_start=0; -+ static unsigned long length_end=0; -+ unsigned int throughput = 0; ++ static int rx_count = 0; ++ static unsigned long length_start = 0; ++ static unsigned long length_end = 0; + static long start = 0; -+ long end = 0; -+ long time_cost = 0; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)) + struct timeval t_start; -+ struct timeval t_end; ++ struct timeval t_end; +#endif + + /* + * Update with the dst mac address later to void broadcast or multicast, + * get from RxPrivHdr->data + */ -+ if ( RxPrivHdr->RxLength > DATA_PACKET_LENGTH_MIN ) ++ if (RxPrivHdr->RxLength > DATA_PACKET_LENGTH_MIN) + { + rx_count++; + if (rx_count == 1) @@ -72988,39 +73547,42 @@ index 000000000000..1727d4a3ea37 + start = ktime_to_ms(ktime_get_boottime()); +#else + do_gettimeofday(&t_start); -+ start = ((long)t_start.tv_sec)*1000+(long)t_start.tv_usec/1000; ++ start = ((long)t_start.tv_sec) * 1000 + (long)t_start.tv_usec / 1000; +#endif -+ printk("Rx side:Got the first packet and the start time is :%ld ms.\n",start); ++ pr_debug("Rx side:Got the first packet and the start time is :%ld ms.\n",start); + length_start += RxPrivHdr->RxLength; + length_end += RxPrivHdr->RxLength; + } + else + { ++ long time_cost; ++ long end; ++ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)) + end = ktime_to_ms(ktime_get_boottime()); +#else + do_gettimeofday(&t_end); -+ end = ((long)t_end.tv_sec)*1000+(long)t_end.tv_usec/1000; ++ end = ((long)t_end.tv_sec) * 1000+(long)t_end.tv_usec / 1000; +#endif + time_cost = end - start; + length_end += RxPrivHdr->RxLength; -+ if ( time_cost >= THROUGHPUT_GET_INTERVAL ) ++ if (time_cost >= THROUGHPUT_GET_INTERVAL) + { -+ throughput = (length_end-length_start)*8/time_cost; ++ unsigned int throughput; ++ ++ throughput = (length_end - length_start) * 8 / time_cost; + start = end; + length_start = length_end; -+ printk("---B2B debug---Rx side: Current throughput: %d kbps.\n\n",throughput); ++ pr_debug("---B2B debug---Rx side: Current throughput: %d kbps.\n\n",throughput); + } + } + } +} + -+ -+ +unsigned int hi_get_device_id(void) +{ + struct hw_interface* hif = hif_get_hw_interface(); -+ unsigned int regdata = 0; ++ unsigned int regdata; + + regdata = hif->hif_ops.hi_read_word(PRODUCT_AMLOGIC_ADDR); + @@ -73029,8 +73591,8 @@ index 000000000000..1727d4a3ea37 + +unsigned int hi_get_vendor_id(void) +{ -+ unsigned int regdata = 0; + struct hw_interface* hif = hif_get_hw_interface(); ++ unsigned int regdata; + + regdata = hif->hif_ops.hi_read_word(VENDOR_AMLOGIC_ADDR); + @@ -73039,8 +73601,8 @@ index 000000000000..1727d4a3ea37 + +unsigned int hi_get_fw_version(void) +{ -+ unsigned int regdata = 0; + struct hw_interface* hif = hif_get_hw_interface(); ++ unsigned int regdata; + + regdata = hif->hif_ops.hi_read_word(FIRMWARE_VERSION_ADDR); + @@ -73049,10 +73611,10 @@ index 000000000000..1727d4a3ea37 + +unsigned int hi_get_irq_status(void) +{ -+ unsigned int regdata = 0; + struct hw_interface* hif = hif_get_hw_interface(); ++ unsigned int regdata; + -+ regdata = hif->hif_ops.hi_read_word(RG_WIFI_IF_HOST_IRQ_ST ); ++ regdata = hif->hif_ops.hi_read_word(RG_WIFI_IF_HOST_IRQ_ST); + + return regdata; +} @@ -73066,9 +73628,10 @@ index 000000000000..1727d4a3ea37 +#ifdef HAL_FPGA_VER +#ifdef PROJECT_W1 + /* -+ * just sometimes, clearing host req by clearing irq status operation after sending ps -+ * cmd to firmware. add host req to avoid firmware can't power off. -+ */ ++ * Just sometimes, clearing host req by clearing irq status operation ++ * after sending ps cmd to firmware. add host req to avoid firmware ++ * can't power off. ++ */ + if (0) + { + struct hal_private * halpriv = hal_get_priv(); @@ -73079,11 +73642,11 @@ index 000000000000..1727d4a3ea37 + POWER_BEGIN_LOCK(); + if (halpriv->hal_fw_ps_status == HAL_FW_IN_SLEEP) + { -+ unsigned int tmpreg = 0; ++ unsigned int tmpreg; + + POWER_END_LOCK(); + tmpreg = hif->hif_ops.hi_bottom_read8(SDIO_FUNC1, RG_SDIO_PMU_HOST_REQ); -+ // set host sleep req ++ /* set host sleep req */ + tmpreg |= HOST_SLEEP_REQ; + hif->hif_ops.hi_bottom_write8(SDIO_FUNC1, RG_SDIO_PMU_HOST_REQ, tmpreg); + POWER_BEGIN_LOCK(); @@ -73094,36 +73657,30 @@ index 000000000000..1727d4a3ea37 +#endif +} + -+static SYS_TYPE hi_get_next_up_fifo(FIFO_SHARE_CTRL * pFifiShare) ++static SYS_TYPE hi_get_next_up_fifo(FIFO_SHARE_CTRL *pFifiShare) +{ -+ return (pFifiShare->FDB + pFifiShare->FDT*pFifiShare->FDL); ++ return (pFifiShare->FDB + pFifiShare->FDT * pFifiShare->FDL); +} + -+static unsigned char bFifoFull(FIFO_SHARE_CTRL * pFifiShare) ++static unsigned char bFifoFull(FIFO_SHARE_CTRL *pFifiShare) +{ + unsigned int FDH = pFifiShare->FDH; + + CIRCLE_Add_One(FDH,pFifiShare->FDN); -+ if (FDH == pFifiShare->FDT) -+ { -+ return true; -+ } -+ return false; ++ ++ return (FDH == pFifiShare->FDT); +} + -+static unsigned char bDownFifo_Up(FIFO_SHARE_CTRL * pFifiShare) ++static unsigned char bDownFifo_Up(FIFO_SHARE_CTRL *pFifiShare) +{ + unsigned int FDH = pFifiShare->FDH; -+ if (FDH == pFifiShare->FDT) -+ { -+ return true; -+ } -+ return false; ++ ++ return (FDH == pFifiShare->FDT); +} + -+static unsigned char hi_down_fifo_full_up(FIFO_SHARE_CTRL * pFifiShare) ++static unsigned char hi_down_fifo_full_up(FIFO_SHARE_CTRL *pFifiShare) +{ -+ //updata cmd down fifo fdt ++ /* updata cmd down fifo fdt */ + struct hw_interface* hif = hif_get_hw_interface(); + + pFifiShare->FDT = hif->hif_ops.hi_read_word(pFifiShare->FCB + 12); @@ -73132,9 +73689,9 @@ index 000000000000..1727d4a3ea37 +} + +/*if full return true,else false*/ -+static unsigned char hi_down_fifo_pull(FIFO_SHARE_CTRL * pFifiShare) ++static unsigned char hi_down_fifo_pull(FIFO_SHARE_CTRL *pFifiShare) +{ -+ //updata cmd down fifo fdt ++ /* updata cmd down fifo fdt */ + struct hw_interface* hif = hif_get_hw_interface(); + + pFifiShare->FDT = hif->hif_ops.hi_read_word(pFifiShare->FCB + 12); @@ -73142,54 +73699,56 @@ index 000000000000..1727d4a3ea37 + return bFifoFull(pFifiShare); +} + -+/*return next cmd down fifo address*/ -+static SYS_TYPE hi_get_next_down_fifo(FIFO_SHARE_CTRL * pFifiShare) ++/* return next cmd down fifo address */ ++static SYS_TYPE hi_get_next_down_fifo(FIFO_SHARE_CTRL *pFifiShare) +{ + return (pFifiShare->FDB + pFifiShare->FDH*pFifiShare->FDL); +} + -+static unsigned char hi_push_down_fifo(FIFO_SHARE_CTRL *pDownFifo, -+ unsigned char *pdata,unsigned int len) ++static unsigned char hi_push_down_fifo(FIFO_SHARE_CTRL *pDownFifo, ++ unsigned char *pdata, unsigned int len) +{ + struct hw_interface* hif = hif_get_hw_interface(); + + if (!hi_down_fifo_pull(pDownFifo)) + { + hif->hif_ops.hi_write_sram((unsigned char *)pdata, -+ (unsigned char*)hi_get_next_down_fifo(pDownFifo),len); -+ CIRCLE_Add_One( pDownFifo->FDH ,pDownFifo->FDN); -+ //trigger host cmd irq for firmware -+ hif->hif_ops.hi_write_sram((unsigned char*)(&(pDownFifo->FDH)), -+ (unsigned char *)(SYS_TYPE)((pDownFifo)->FCB + 8), 4); ++ (unsigned char *)hi_get_next_down_fifo(pDownFifo), ++ len); ++ CIRCLE_Add_One( pDownFifo->FDH, pDownFifo->FDN); ++ /* trigger host cmd irq for firmware */ ++ hif->hif_ops.hi_write_sram((unsigned char *)(&(pDownFifo->FDH)), ++ (unsigned char *)(SYS_TYPE)((pDownFifo)->FCB + 8), ++ 4); + return true; + } ++ + return false; +} + +static unsigned char hi_push_down_fifo_up(FIFO_SHARE_CTRL *pUpFifo, -+ unsigned char *pdata,unsigned int len) ++ unsigned char *pdata, unsigned int len) +{ -+ //insert data ++ /* insert data */ + struct hw_interface* hif = hif_get_hw_interface(); + -+ if (hi_down_fifo_full_up(pUpFifo)) //insert data ++ if (hi_down_fifo_full_up(pUpFifo)) /* insert data */ + { -+ CIRCLE_Sub_One(pUpFifo->FDT ,pUpFifo->FDN); //here back to the filled again ++ CIRCLE_Sub_One(pUpFifo->FDT ,pUpFifo->FDN); /* here back to the filled again */ + hif->hif_ops.hi_read_sram((unsigned char *)pdata, -+ (unsigned char *)hi_get_next_up_fifo(pUpFifo),len); -+ //updata cmd down fifo fdh -+ CIRCLE_Add_One( pUpFifo->FDT ,pUpFifo->FDN); ++ (unsigned char *)hi_get_next_up_fifo(pUpFifo), ++ len); ++ /* updata cmd down fifo fdh */ ++ CIRCLE_Add_One(pUpFifo->FDT, pUpFifo->FDN); + return true; + } + + return false; +} + -+ -+ +#if defined (HAL_FPGA_VER) + -+static struct tx_status_node tx_status[WIFI_MAX_TXFRAME*2]; ++static struct tx_status_node tx_status[WIFI_MAX_TXFRAME * 2]; +int tx_status_list_init(struct tx_status_list *tx_status_list, int num) +{ + int i = 0; @@ -73199,50 +73758,59 @@ index 000000000000..1727d4a3ea37 + INIT_LIST_HEAD(&(tx_status_list->free_list)); + spin_lock_init(&(tx_status_list->status_list_lock)); + -+ if (node_num > WIFI_MAX_TXFRAME*2) ++ if (node_num > WIFI_MAX_TXFRAME * 2) + { -+ node_num = WIFI_MAX_TXFRAME*2; ++ node_num = WIFI_MAX_TXFRAME * 2; + } ++ + while (i < node_num) + { + INIT_LIST_HEAD(&(tx_status[i].list_node)); + list_add_tail(&(tx_status[i].list_node), &(tx_status_list->free_list)); + i++; + } ++ + return node_num; +} + -+struct tx_status_node * tx_status_node_alloc(struct tx_status_list *tx_status_list) ++struct tx_status_node *tx_status_node_alloc(struct tx_status_list *tx_status_list) +{ + struct tx_status_node *txok_status_node = NULL; + + if (tx_status_list == NULL) + return NULL; ++ + spin_lock_bh(&tx_status_list->status_list_lock); ++ + if (!list_empty(&tx_status_list->free_list)) + { -+ txok_status_node = list_first_entry(&tx_status_list->free_list, struct tx_status_node, list_node); ++ txok_status_node = list_first_entry(&tx_status_list->free_list, ++ struct tx_status_node, ++ list_node); + list_del(&txok_status_node->list_node); + } + spin_unlock_bh(&tx_status_list->status_list_lock); ++ + return txok_status_node; +} + +void tx_status_node_enqueue(struct tx_status_node *txok_status_node, -+ struct tx_status_list *tx_status_list) ++ struct tx_status_list *tx_status_list) +{ + if (txok_status_node == NULL || tx_status_list == NULL) + return; ++ + spin_lock_bh(&tx_status_list->status_list_lock); + list_add_tail(&txok_status_node->list_node, &tx_status_list->status_list); + spin_unlock_bh(&tx_status_list->status_list_lock); +} + +void tx_status_node_free(struct tx_status_node *txok_status_node, -+ struct tx_status_list *tx_status_list) ++ struct tx_status_list *tx_status_list) +{ + if (txok_status_node == NULL || tx_status_list == NULL) + return; ++ + spin_lock_bh(&tx_status_list->status_list_lock); + list_add_tail(&txok_status_node->list_node, &tx_status_list->free_list); + spin_unlock_bh(&tx_status_list->status_list_lock); @@ -73254,27 +73822,31 @@ index 000000000000..1727d4a3ea37 + + if (tx_status_list == NULL) + return NULL; ++ + spin_lock_bh(&(tx_status_list->status_list_lock)); + if (!list_empty(&(tx_status_list->status_list))) + { -+ txok_status_node = list_first_entry(&(tx_status_list->status_list), struct tx_status_node, list_node); ++ txok_status_node = list_first_entry(&(tx_status_list->status_list), ++ struct tx_status_node, ++ list_node); + list_del(&(txok_status_node->list_node)); + } + spin_unlock_bh(&(tx_status_list->status_list_lock)); ++ + return txok_status_node; +} + -+ -+//static unsigned char g_rx_fifo[RX_FIFO_SIZE + 2 * FUNC6_BLKSIZE]; ++/* static unsigned char g_rx_fifo[RX_FIFO_SIZE + 2 * FUNC6_BLKSIZE]; */ +unsigned char *g_rx_fifo = NULL; +void hi_rx_fifo_init(void) +{ -+ struct hw_interface* hif = hif_get_hw_interface(); ++ struct hw_interface* hif = hif_get_hw_interface(); + +#ifdef CONFIG_AML_USE_STATIC_BUF + g_rx_fifo = wifi_mem_prealloc(AML_RX_FIFO, RX_FIFO_SIZE + 2 * FUNC6_BLKSIZE); +#else -+ g_rx_fifo = (unsigned char *)ZMALLOC(RX_FIFO_SIZE + 2 * FUNC6_BLKSIZE, "hi_rx_fifo_init", GFP_KERNEL); ++ g_rx_fifo = (unsigned char *)ZMALLOC(RX_FIFO_SIZE + 2 * FUNC6_BLKSIZE, ++ "hi_rx_fifo_init", GFP_KERNEL); +#endif + if (g_rx_fifo == NULL) + ERROR_DEBUG_OUT("rx fifo alloc failed\n"); @@ -73290,12 +73862,12 @@ index 000000000000..1727d4a3ea37 +/* page num after initializing sg list */ +static unsigned int send_page_num = 0; +int hi_sdio_setup_scat_data(struct scatterlist *sg_list, struct hi_tx_desc **pTxDPape, -+ unsigned int sg_num, unsigned char func_num) ++ unsigned int sg_num, unsigned char func_num) +{ -+ int i = 0; ++ int i; + struct sdio_func *func = aml_priv_to_func(func_num); + struct mmc_host *host = func->card->host; -+ unsigned int sg_data_size = 0, blkcnt = 0, sg_total_len = 0, page_tmp = 0; ++ unsigned int blkcnt, sg_total_len; + + /* we still check if total len in a mmc request is greater than max req len. */ + unsigned int max_sg_size = min(func->cur_blksize * SDIO_MAX_BLK_CNT, host->max_req_size); @@ -73309,9 +73881,13 @@ index 000000000000..1727d4a3ea37 + /*Init sg table with specific num. */ + sg_init_table(sg_list, sg_num); + remain_mpdu_num = sg_num; ++ blkcnt = 0; ++ sg_total_len = 0; + + for (i = 0; i < sg_num; i++) + { ++ unsigned int sg_data_size, page_tmp; ++ + /*every mpdu length.*/ + sg_data_size = HW_MPDU_LEN_GET(pTxDPape[i]->MPDUBufFlag) + HI_TXDESC_DATAOFFSET; + page_tmp = pTxDPape[i]->TxPriv.PageNum; @@ -73331,15 +73907,17 @@ index 000000000000..1727d4a3ea37 + sg_total_len += sg_data_size; + send_page_num += page_tmp; + -+ /*Init every sg with specific mpdu. */ ++ /* Init every sg with specific mpdu. */ + sg_set_buf(&sg_list[i], pTxDPape[i], sg_data_size); + remain_mpdu_num--; + } ++ + return blkcnt; +} + -+/* for fpga ver*/ -+int hi_tx_frame(struct hi_tx_desc **pTxDPape, unsigned int mpdu_num, unsigned int page_num) ++/* for fpga ver */ ++int hi_tx_frame(struct hi_tx_desc **pTxDPape, unsigned int mpdu_num, ++ unsigned int page_num) +{ + struct scatterlist sg_list[SG_NUM_MAX] = {{0}}; + unsigned int sg_remain = 0, sg_num = 0, offset = 0, blkcnt = 0; @@ -73351,7 +73929,7 @@ index 000000000000..1727d4a3ea37 + + do + { -+ /*Support wifi host fill many mpdus in sg_list. */ ++ /* Support wifi host fill many mpdus in sg_list. */ + if (sg_num > SG_NUM_MAX) + { + sg_remain = sg_num - SG_NUM_MAX; @@ -73362,9 +73940,12 @@ index 000000000000..1727d4a3ea37 + sg_remain = 0; + } + -+ /* one mpdu will fill in sg item, so mpdu_num is sg_num. But when mpdu len is greater than 'max_seg_size', -+ * there are many mpdus will be remained*/ -+ blkcnt = hi_sdio_setup_scat_data(sg_list, &pTxDPape[offset], sg_num, SDIO_FUNC4); ++ /* One mpdu will fill in sg item, so mpdu_num is sg_num. But when ++ * mpdu len is greater than 'max_seg_size', there are many mpdus ++ * will be remained. ++ */ ++ blkcnt = hi_sdio_setup_scat_data(sg_list, &pTxDPape[offset], sg_num, ++ SDIO_FUNC4); + if (remain_mpdu_num > 0) + { + sg_remain += remain_mpdu_num; @@ -73376,8 +73957,11 @@ index 000000000000..1727d4a3ea37 + ret = -1; + break; + } -+ /* addr (0x0) is flag for FUNC4 and addr is not a actual phy or virtual address. */ -+ while ((ret = hif->hif_ops.hi_scat_rw(sg_list, sg_num, blkcnt, SDIO_FUNC4, 0x0, SG_WRITE)) != 0) ++ /* addr (0x0) is flag for FUNC4 and addr is not a actual ++ * phy or virtual address. ++ */ ++ while ((ret = hif->hif_ops.hi_scat_rw(sg_list, sg_num, blkcnt, ++ SDIO_FUNC4, 0x0, SG_WRITE)) != 0) + { + if (loop > 4) + { @@ -73385,25 +73969,32 @@ index 000000000000..1727d4a3ea37 + break; + } + loop++; -+ } ++ } + + if (ret == 0) + { -+#if (SDIO_UPDATE_HOST_WRPTR == 0) //if enable host update sdio write pointer, we need set bit9 in SDIO MISC CTRL ++#if (SDIO_UPDATE_HOST_WRPTR == 0) ++ /* If enable host update sdio write pointer, we need set ++ * bit9 in SDIO MISC CTRL. ++ */ + unsigned int page_tmp = 0; -+ unsigned int reg_tmp = 0; ++ unsigned int reg_tmp; + struct hal_private * hal_priv = hal_get_priv(); + -+ /*sdio process success, update SDIO write pointer and interrupt FW to read data. */ ++ /* sdio process success, update SDIO write pointer and ++ * interrupt FW to read data. ++ */ + page_tmp += send_page_num; + if (page_tmp > page_num) + { -+ printk("%s:%d, update host wr ptr failed. page_tmp :%d, all page num%d\n", -+ __func__, __LINE__,page_tmp, page_num); ++ pr_err("%s:%d, update host wr ptr failed. page_tmp :%d, all page num%d\n", ++ __func__, __LINE__,page_tmp, page_num); + } -+ hal_priv->tx_page_offset = CIRCLE_Addition2(send_page_num, hal_priv->tx_page_offset, TX_ADDRESSTABLE_NUM); ++ hal_priv->tx_page_offset = CIRCLE_Addition2(send_page_num, ++ hal_priv->tx_page_offset, ++ TX_ADDRESSTABLE_NUM); + send_page_num = 0; -+ /*Bit30 enable TXPAGE TABLE REG flag. */ ++ /* Bit30 enable TXPAGE TABLE REG flag. */ + reg_tmp = hal_priv->tx_page_offset; + + hif->hif_ops.hi_write_word(RG_WIFI_IF_MAC_TXTABLE_RD_ID, reg_tmp); @@ -73412,43 +74003,42 @@ index 000000000000..1727d4a3ea37 + else + { + /* theoretically, sdio shall not transmit failed, if fail and fix it. */ -+ printk("%s(%d):SDIO try re-transmit %d times, but fail\n",__func__, __LINE__, loop); ++ pr_err("%s(%d):SDIO try re-transmit %d times, but fail\n",__func__, __LINE__, loop); + } -+ /*offset for mpdu in pTxDPape list and continue. */ ++ /* offset for mpdu in pTxDPape list and continue. */ + offset += sg_num; + sg_num = sg_remain; + } + while(sg_remain > 0); ++ + return ret; +} + +#elif defined (HAL_SIM_VER) + -+unsigned int print_cnt = 0; ++static unsigned int print_cnt = 0; +static unsigned int tx_page_offset = 0; + -+/* for simulation ver . */ -+int hi_tx_frame( struct hi_tx_desc * pTxDPape, unsigned int blk_num, unsigned int page_num) ++/* for simulation ver. */ ++int hi_tx_frame(struct hi_tx_desc *pTxDPape, unsigned int blk_num, unsigned int page_num) +{ -+ unsigned int tmpreg = 0; -+ -+ struct hw_interface* hif = hif_get_hw_interface(); ++ unsigned int tmpreg; ++ struct hw_interface *hif = hif_get_hw_interface(); + + if (0) + { + hal_show_txframe(pTxDPape); + } + print_cnt++; -+ if( print_cnt == 2000) ++ if (print_cnt == 2000) + { -+ PRINT("tv_tx_rate=0x%x \n", pTxDPape->TxVector.tv_ht.htbit.tv_tx_rate); ++ PRINT("tv_tx_rate=0x%x \n", pTxDPape->TxVector.tv_ht.htbit.tv_tx_rate); + PRINT("tv_Channel_BW=%d\n", pTxDPape->TxVector.tv_ht.htbit.tv_Channel_BW); + print_cnt = 0; + } + hif->hif_ops.hi_send_frame((unsigned char *)pTxDPape, 0, blk_num); +#if (SDIO_UPDATE_HOST_WRPTR == 0) -+ tmpreg = 0; -+ /*Update tx page table ptr. */ ++ /* Update tx page table ptr. */ + tx_page_offset = CIRCLE_Addition2(tx_page_offset, page_num, TX_ADDRESSTABLE_NUM); + tmpreg = tx_page_offset; + @@ -73461,30 +74051,32 @@ index 000000000000..1727d4a3ea37 + +void hi_cfg_firmware(void) +{ -+ struct hw_interface* hif = hif_get_hw_interface(); ++ struct hw_interface *hif = hif_get_hw_interface(); ++ + hif->hw_config.txpagenum = DEFAULT_TXPAGENUM; + hif->hw_config.rxpagenum = DEFAULT_RXPAGENUM; -+ hif->hw_config.bcn_page_num = DEFAULT_BCN_NUM; ++ hif->hw_config.bcn_page_num = DEFAULT_BCN_NUM; + + if (aml_wifi_is_enable_rf_test()) + hif->hw_config.flags = PT_MODE; + +#if defined (HAL_SIM_VER) -+ if( STA1_VMAC0_SEND_RATE <= WIFI_11B_11M) ++ if (STA1_VMAC0_SEND_RATE <= WIFI_11B_11M) + { + hif->hw_config.txpagenum = 16; + } +#endif -+ hif->hif_ops.hi_write_sram((unsigned char *)&hif->hw_config, -+ (unsigned char *)HW_CONFIG_ADDR,sizeof(HW_CONFIG)); ++ hif->hif_ops.hi_write_sram((unsigned char *)&hif->hw_config, ++ (unsigned char *)HW_CONFIG_ADDR, ++ sizeof(HW_CONFIG)); +} + -+//asynchronous -+extern unsigned char wifi_sdio_access; -+unsigned char hi_set_cmd(unsigned char *pdata,unsigned int len) ++/* asynchronous */ ++extern unsigned char wifi_sdio_access; ++unsigned char hi_set_cmd(unsigned char *pdata, unsigned int len) +{ -+ struct hal_private * hal_priv = hal_get_priv(); -+ struct hw_interface* hif = hif_get_hw_interface(); ++ struct hal_private *hal_priv = hal_get_priv(); ++ struct hw_interface *hif = hif_get_hw_interface(); + FIFO_SHARE_CTRL *pCmdDownFifo = &hif->CmdDownFifo; + unsigned int loop = 0; + PowerSaveCmd pscmd = *(PowerSaveCmd *)pdata; @@ -73501,8 +74093,8 @@ index 000000000000..1727d4a3ea37 + } + + POWER_BEGIN_LOCK(); -+ if (((hal_priv->hal_drv_ps_status & HAL_DRV_IN_SLEEPING) != 0) -+ && (pdata[0] != Power_Save_Cmd) && (pdata[0] != WoW_Enable_Cmd)) ++ if (((hal_priv->hal_drv_ps_status & HAL_DRV_IN_SLEEPING) != 0) && ++ (pdata[0] != Power_Save_Cmd) && (pdata[0] != WoW_Enable_Cmd)) + { + POWER_END_LOCK(); + return false; @@ -73521,7 +74113,8 @@ index 000000000000..1727d4a3ea37 + { + if (loop++>10000) + { -+ printk("err-> f_fdh: %d, f_fdt: %d, d_fdh %d \n", hif->hif_ops.hi_read_word(0x00a10038), ++ pr_err("err-> f_fdh: %d, f_fdt: %d, d_fdh %d \n", ++ hif->hif_ops.hi_read_word(0x00a10038), + hif->hif_ops.hi_read_word(0x00a1003c), pCmdDownFifo->FDH); + PRINT("hi_set_cmd err, cmd=0x%x, vid=0x%x\n", pdata[0], pdata[3]); + @@ -73530,17 +74123,20 @@ index 000000000000..1727d4a3ea37 + POWER_END_LOCK(); + return false; + } ++ + OS_UDELAY(20); + } + aml_wifi_sdio_power_lock(); + POWER_BEGIN_LOCK(); -+ if (((hal_priv->powersave_init_flag == 0) && (pscmd.Cmd == Power_Save_Cmd) && (pscmd.psmode == PS_DOZE)) -+ || ((hal_priv->powersave_init_flag == 0) && (suspend_cmd.Cmd == WoW_Enable_Cmd) && (suspend_cmd.enable == 1))) ++ if (((hal_priv->powersave_init_flag == 0) && (pscmd.Cmd == Power_Save_Cmd) && ++ (pscmd.psmode == PS_DOZE)) || ++ ((hal_priv->powersave_init_flag == 0) && ++ (suspend_cmd.Cmd == WoW_Enable_Cmd) && (suspend_cmd.enable == 1))) + { -+ unsigned int tmpreg = 0; ++ unsigned int tmpreg; + + tmpreg = hif->hif_ops.hi_bottom_read8(SDIO_FUNC1, RG_SDIO_PMU_HOST_REQ); -+ // set host sleep req ++ /* set host sleep req */ + tmpreg |= HOST_SLEEP_REQ; + hif->hif_ops.hi_bottom_write8(SDIO_FUNC1, RG_SDIO_PMU_HOST_REQ, tmpreg); + } @@ -73552,12 +74148,12 @@ index 000000000000..1727d4a3ea37 + return true; +} + -+//synchronous ++/* synchronous */ +unsigned char hi_get_cmd(unsigned char *pdata,unsigned int len) +{ -+ struct hw_interface* hif = hif_get_hw_interface(); ++ struct hw_interface *hif = hif_get_hw_interface(); + FIFO_SHARE_CTRL *pCmdDownFifo = &hif->CmdDownFifo; -+ unsigned int Cmd = pdata[0] ; ++ unsigned int Cmd = pdata[0]; + + if (!hi_set_cmd(pdata,len)) + { @@ -73565,8 +74161,8 @@ index 000000000000..1727d4a3ea37 + ASSERT(0); + return false; + } -+ //get return data -+ while (!hi_push_down_fifo_up(pCmdDownFifo,pdata,len)) ++ /* get return data */ ++ while (!hi_push_down_fifo_up(pCmdDownFifo, pdata, len)) + { + OS_UDELAY(20); + } @@ -73579,12 +74175,12 @@ index 000000000000..1727d4a3ea37 + +void hi_soft_tx_irq(void) +{ -+ struct hal_private * hal_priv = hal_get_priv(); -+ struct hw_interface* hif = hif_get_hw_interface(); -+ struct txdonestatus * txstatus = NULL; -+ unsigned int hw_txc_addr = 0; -+ struct tx_complete_status *txcompletestatus = NULL; -+ struct tx_nulldata_status* tx_null_status = NULL; ++ struct hal_private *hal_priv = hal_get_priv(); ++ struct hw_interface *hif = hif_get_hw_interface(); ++ struct txdonestatus *txstatus = NULL; ++ unsigned int hw_txc_addr; ++ struct tx_complete_status *txcompletestatus; ++ struct tx_nulldata_status *tx_null_status = NULL; + +#if defined (HAL_FPGA_VER) + struct tx_status_node *txok_status_node = NULL; @@ -73598,28 +74194,33 @@ index 000000000000..1727d4a3ea37 + txcompletestatus = hal_priv->txcompletestatus; + + hif->hif_ops.hi_read_sram((unsigned char *)txcompletestatus, -+ (unsigned char *)(SYS_TYPE)hw_txc_addr, (SYS_TYPE)sizeof(struct tx_complete_status)); ++ (unsigned char *)(SYS_TYPE)hw_txc_addr, ++ (SYS_TYPE)sizeof(struct tx_complete_status)); + -+ ASSERT(((hal_priv->txcompletestatus->txdoneframecounter - hal_priv->HalTxFrameDoneCounter)&0xff) ++ ASSERT(((hal_priv->txcompletestatus->txdoneframecounter - hal_priv->HalTxFrameDoneCounter) & 0xff) + <= WIFI_MAX_TXFRAME); ++ + AML_TXLOCK_LOCK(); + hal_priv->txPageFreeNum += + (hal_priv->txcompletestatus->txpagecounter - hal_priv->HalTxPageDoneCounter) & 0xff; + AML_TXLOCK_UNLOCK(); ++ + hal_priv->HalTxPageDoneCounter = hal_priv->txcompletestatus->txpagecounter; + + if (hal_priv->bhaltxdrop) { -+ printk("page:%d, txdoneframecounter:%d, HalTxFrameDoneCounter:%d\n", -+ hal_priv->txPageFreeNum, hal_priv->txcompletestatus->txdoneframecounter, hal_priv->HalTxFrameDoneCounter); ++ pr_debug("page:%d, txdoneframecounter:%d, HalTxFrameDoneCounter:%d\n", ++ hal_priv->txPageFreeNum, hal_priv->txcompletestatus->txdoneframecounter, ++ hal_priv->HalTxFrameDoneCounter); + } + +#if defined (HAL_FPGA_VER) -+ AML_PRINT(AML_DBG_MODULES_TX, "txPageFreeNum:%d, HalTxPageDoneCounter:%d\n", hal_priv->txPageFreeNum, hal_priv->HalTxPageDoneCounter); ++ AML_PRINT(AML_DBG_MODULES_TX, "txPageFreeNum:%d, HalTxPageDoneCounter:%d\n", ++ hal_priv->txPageFreeNum, hal_priv->HalTxPageDoneCounter); +#endif + -+ while (hal_priv->txcompletestatus->txdoneframecounter != hal_priv->HalTxFrameDoneCounter) ++ while (hal_priv->txcompletestatus->txdoneframecounter != hal_priv->HalTxFrameDoneCounter) + { -+ txstatus = &hal_priv->txcompletestatus->tx_status[hal_priv->HalTxFrameDoneCounter%WIFI_MAX_TXFRAME].txstatus; ++ txstatus = &hal_priv->txcompletestatus->tx_status[hal_priv->HalTxFrameDoneCounter % WIFI_MAX_TXFRAME].txstatus; + hal_priv->HalTxFrameDoneCounter++; + +#if defined (HAL_FPGA_VER) @@ -73627,39 +74228,43 @@ index 000000000000..1727d4a3ea37 + if (txok_status_node != NULL) + { + memcpy(&(txok_status_node->tx_status.txstatus), txstatus, sizeof(struct txdonestatus)); -+ /*enqueue status list to wait for txok analyse */ ++ /* enqueue status list to wait for txok analyse */ + tx_status_node_enqueue(txok_status_node, txok_status_list); + + tx_null_status = &(txok_status_node->tx_status.tx_null_status); -+ if (!((tx_null_status->txstatus == TX_DESCRIPTOR_STATUS_NULL_DATA_OK) -+ || (tx_null_status->txstatus == TX_DESCRIPTOR_STATUS_NULL_DATA_FAIL) -+ || (tx_null_status->txstatus == TX_DESCRIPTOR_STATUS_NEW))) ++ ++ if (!((tx_null_status->txstatus == TX_DESCRIPTOR_STATUS_NULL_DATA_OK) || ++ (tx_null_status->txstatus == TX_DESCRIPTOR_STATUS_NULL_DATA_FAIL) || ++ (tx_null_status->txstatus == TX_DESCRIPTOR_STATUS_NEW))) + { +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) && !defined (LINUX_PLATFORM) -+ __sync_fetch_and_add(&hif->HiStatus.Tx_Free_num,1); ++ __sync_fetch_and_add(&hif->HiStatus.Tx_Free_num, 1); +#else + atomic_add(1, &hif->HiStatus.Tx_Free_num); +#endif + } + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) && !defined (LINUX_PLATFORM) -+ if ((tx_null_status->txstatus == TX_DESCRIPTOR_STATUS_NEW) && (hif->HiStatus.Tx_Free_num < hif->HiStatus.Tx_Done_num)) { ++ if ((tx_null_status->txstatus == TX_DESCRIPTOR_STATUS_NEW) && ++ (hif->HiStatus.Tx_Free_num < hif->HiStatus.Tx_Done_num)) { + __sync_fetch_and_add(&hif->HiStatus.Tx_Free_num,1); +#else -+ if ((tx_null_status->txstatus == TX_DESCRIPTOR_STATUS_NEW) && (atomic_read(&hif->HiStatus.Tx_Free_num) < atomic_read(&hif->HiStatus.Tx_Done_num))) { ++ if ((tx_null_status->txstatus == TX_DESCRIPTOR_STATUS_NEW) && ++ (atomic_read(&hif->HiStatus.Tx_Free_num) < atomic_read(&hif->HiStatus.Tx_Done_num))) { + atomic_add(1, &hif->HiStatus.Tx_Free_num); +#endif + } + } +#elif defined (HAL_SIM_VER) -+ // free skb allocated by hal ++ /* free skb allocated by hal */ + if (hal_free_tx_id(hal_priv,txstatus,&callback, &queue_id) < 0) + { + continue; + } + -+ /*to processes drv_Intr_Txok*/ -+ hal_priv->hal_call_back->intr_tx_handle(hal_priv->drv_priv, txstatus, callback, queue_id); ++ /* to processes drv_Intr_Txok */ ++ hal_priv->hal_call_back->intr_tx_handle(hal_priv->drv_priv, txstatus, ++ callback, queue_id); +#endif + } + @@ -73669,31 +74274,32 @@ index 000000000000..1727d4a3ea37 + return; +} + -+void hi_soft_fw_event(void) ++static void hi_soft_fw_event(void) +{ + struct hal_private *hal_priv = hal_get_priv(); + struct hw_interface *hif = hif_get_hw_interface(); -+ struct fw_event_to_driver *event = NULL; -+ unsigned int hw_event_addr = 0; ++ struct fw_event_to_driver *event; ++ unsigned int hw_event_addr; + + hw_event_addr = hif->hw_config.fweventaddress; + event = hal_priv->fw_event; + -+ hif->hif_ops.hi_read_sram((unsigned char *)event, -+ (unsigned char *)(SYS_TYPE)hw_event_addr, (SYS_TYPE)sizeof(struct fw_event_to_driver)); ++ hif->hif_ops.hi_read_sram((unsigned char *)event, (unsigned char *)(SYS_TYPE)hw_event_addr, ++ (SYS_TYPE)sizeof(struct fw_event_to_driver)); + + if (aml_wifi_is_enable_rf_test()) + return; + -+ while (hal_priv->fw_event->event_counter != hal_priv->hal_fw_event_counter) ++ while (hal_priv->fw_event->event_counter != hal_priv->hal_fw_event_counter) + { -+ struct fw_event_no_data *normal_event = NULL; ++ struct fw_event_no_data *normal_event; + + normal_event = &hal_priv->fw_event->event_data[hal_priv->hal_fw_event_counter % WIFI_MAX_FW_EVENT].normal_event; + hal_priv->hal_call_back->intr_fw_event(hal_priv->drv_priv, normal_event); + event->event_data[0].data[28] = hal_priv->hal_fw_event_counter; + hif->hif_ops.hi_write_sram((unsigned char *)&event->event_data[0].data[28], -+ (unsigned char *)(SYS_TYPE)(hw_event_addr+32), (SYS_TYPE)(sizeof(unsigned char)*4)); ++ (unsigned char *)(SYS_TYPE)(hw_event_addr + 32), ++ (SYS_TYPE)(sizeof(unsigned char) * 4)); + hal_priv->hal_fw_event_counter++; + } + @@ -73702,76 +74308,79 @@ index 000000000000..1727d4a3ea37 + +void hi_soft_rx_bcn(struct hal_private *hal_priv, unsigned char vid) +{ -+ struct sk_buff *skb = NULL; -+ struct hw_interface *hif = hif_get_hw_interface(); -+ unsigned char bcnpage = hif->hw_config.bcn_page_num; -+ /*beacon buffer address in sram */ -+ unsigned int bcnaddr = hif->hw_config.beaconframeaddress -+ + (vid * (bcnpage/WIFI_MAX_VID) * PAGE_LEN); -+ unsigned int buflen = bcnpage / WIFI_MAX_VID * PAGE_LEN; -+ unsigned long bcnctl_reg = 0; -+ unsigned int rx_bcn_page = 0; -+ HW_RxDescripter_bit *RxDesc = NULL; -+ -+ /*Protect operation for receiving beacon by check bit31 is 1 in bcn ctrl register.*/ -+ -+ bcnctl_reg = hif->hif_ops.hi_read_word(RG_MAC_BCN_CTRL_REG); ++ struct sk_buff *skb; ++ struct hw_interface *hif = hif_get_hw_interface(); ++ unsigned char bcnpage = hif->hw_config.bcn_page_num; ++ /* beacon buffer address in sram */ ++ unsigned int bcnaddr = hif->hw_config.beaconframeaddress + ++ (vid * (bcnpage / WIFI_MAX_VID) * PAGE_LEN); ++ unsigned int buflen = bcnpage / WIFI_MAX_VID * PAGE_LEN; ++ unsigned long bcnctl_reg; ++ unsigned int rx_bcn_page; ++ HW_RxDescripter_bit *RxDesc; ++ ++ /* Protect operation for receiving beacon by check bit31 is 1 in ++ * bcn ctrl register. ++ */ ++ bcnctl_reg = hif->hif_ops.hi_read_word(RG_MAC_BCN_CTRL_REG); + -+ if ((bcnctl_reg & BCN_READABLE) == 0) -+ { -+ PRINT("RecvBcn: bcnctrl_reg = %lx\n", (SYS_TYPE)bcnctl_reg); -+ return; -+ } ++ if ((bcnctl_reg & BCN_READABLE) == 0) ++ { ++ PRINT("RecvBcn: bcnctrl_reg = %lx\n", (SYS_TYPE)bcnctl_reg); ++ return; ++ } + -+ skb = os_skb_alloc(buflen); -+ if (skb == NULL) -+ { -+ PRINT("RecvBcn: alloc skb failed\n"); -+ return; -+ } -+ /*Get received beacon page number. If beacon page number is 0 -+ * indicates to read whole beacon buffer. */ -+ rx_bcn_page = (bcnctl_reg & BCN_LEN_MASK) >> 17; -+ if (rx_bcn_page != 0) -+ buflen = rx_bcn_page * PAGE_LEN; ++ skb = os_skb_alloc(buflen); ++ if (skb == NULL) ++ { ++ PRINT("RecvBcn: alloc skb failed\n"); ++ return; ++ } ++ /* Get received beacon page number. If beacon page number is 0 ++ * indicates to read whole beacon buffer. ++ */ ++ rx_bcn_page = (bcnctl_reg & BCN_LEN_MASK) >> 17; ++ if (rx_bcn_page != 0) ++ buflen = rx_bcn_page * PAGE_LEN; + -+ hif->hif_ops.hi_read_sram((unsigned char *)os_skb_data(skb), -+ (unsigned char *)(SYS_TYPE)bcnaddr, (SYS_TYPE)buflen); ++ hif->hif_ops.hi_read_sram((unsigned char *)os_skb_data(skb), ++ (unsigned char *)(SYS_TYPE)bcnaddr, ++ (SYS_TYPE)buflen); + -+ RxDesc = (HW_RxDescripter_bit *)skb->data; ++ RxDesc = (HW_RxDescripter_bit *)skb->data; + -+ /*Discarding beacon frames when RxLength is greater than buflen.*/ -+ if ((RxDesc->RxLength + RX_PRIV_HDR_LEN) >= buflen) -+ { -+ PRINT("RecvBcn: RxLength =%lu\n", (SYS_TYPE)RxDesc->RxLength); -+ os_skb_free(skb); -+ return; -+ } -+ os_skb_put(skb, (RxDesc->RxLength + RX_PRIV_HDR_LEN)); /*beacon len and RXVector len */ ++ /* Discarding beacon frames when RxLength is greater than buflen. */ ++ if ((RxDesc->RxLength + RX_PRIV_HDR_LEN) >= buflen) ++ { ++ PRINT("RecvBcn: RxLength =%lu\n", (SYS_TYPE)RxDesc->RxLength); ++ os_skb_free(skb); ++ return; ++ } ++ os_skb_put(skb, (RxDesc->RxLength + RX_PRIV_HDR_LEN)); /* beacon len and RXVector len */ + +#if defined (HAL_FPGA_VER) -+ skb_queue_tail(&hif->bcn_list_head, skb); -+ up(&hal_priv->rx_thread_sem); ++ skb_queue_tail(&hif->bcn_list_head, skb); ++ up(&hal_priv->rx_thread_sem); +#elif defined (HAL_SIM_VER) -+ hal_soft_rx_cs(hal_priv, skb); ++ hal_soft_rx_cs(hal_priv, skb); +#endif +} + -+/*Rx packets to static FiFo */ ++/* Rx packets to static FiFo. */ +void hi_soft_rx_irq(struct hal_private *hal_priv, unsigned int rx_fw_ptr) +#if defined (HAL_FPGA_VER) +{ -+ unsigned int rx_total_len = 0, rxmax_offset = 0; -+ struct hw_interface* hif = NULL; -+ unsigned char hal_open = 0; -+ unsigned int rx_fifo_fw = 0; -+ int remain_len = 0, read_len = 0; ++ unsigned int rx_total_len, rxmax_offset; ++ struct hw_interface* hif; ++ unsigned char hal_open; ++ unsigned int rx_fifo_fw; ++ int remain_len, read_len; + int host_remain_len = 0; -+ unsigned int fifo_empty_size = 0; -+ unsigned int rx_fifo_fdt = 0; -+ unsigned int rx_fifo_fdh = 0; ++ unsigned int fifo_empty_size; ++ unsigned int rx_fifo_fdt; ++ unsigned int rx_fifo_fdh; +#if (SDIO_UPDATE_HOST_RDPTR != 0) -+ int host_wrapper_len = 0; ++ int host_wrapper_len; +#endif + static unsigned char print_cnt = 0; + @@ -73780,36 +74389,43 @@ index 000000000000..1727d4a3ea37 + rxmax_offset = hif->hw_config.rxpagenum * PAGE_LEN; + rx_fifo_fw = rx_fw_ptr * 4; + -+ /*if slave rx fifo is empty or hal not open*/ ++ /* if slave rx fifo is empty or hal not open */ + if ((hal_priv->rx_host_offset == rx_fifo_fw) || !hal_open) + { + if (print_cnt++ == 200) { -+ AML_OUTPUT("rx_host_offset:%d, rx_fifo_fw:%d, hal_open:%d\n", hal_priv->rx_host_offset, rx_fifo_fw, hal_open); ++ AML_OUTPUT("rx_host_offset:%d, rx_fifo_fw:%d, hal_open:%d\n", ++ hal_priv->rx_host_offset, rx_fifo_fw, hal_open); + } + return; + } + -+ rx_fifo_fdt = hif->rx_fifo.FDT; ++ rx_fifo_fdt = hif->rx_fifo.FDT; + rx_fifo_fdh = hif->rx_fifo.FDH; + -+ /* write packets to FDT, and rx process get mpdus from FDH. The buffer space from FDT to FDH is empty.*/ -+ fifo_empty_size = CIRCLE_Subtract2(rx_fifo_fdh, rx_fifo_fdt, hif->rx_fifo.FDN); -+ rx_total_len = CIRCLE_Subtract2(rx_fifo_fw, hal_priv->rx_host_offset, rxmax_offset); -+ /*pulse FUNC6_BLKSIZE is preventable_sdio_bottom_read over write rx fifo data that not handle*/ ++ /* Write packets to FDT, and rx process get mpdus from FDH. ++ * The buffer space from FDT to FDH is empty. ++ */ ++ fifo_empty_size = CIRCLE_Subtract2(rx_fifo_fdh, rx_fifo_fdt, ++ hif->rx_fifo.FDN); ++ rx_total_len = CIRCLE_Subtract2(rx_fifo_fw, hal_priv->rx_host_offset, ++ rxmax_offset); ++ /* pulse FUNC6_BLKSIZE is preventable_sdio_bottom_read over ++ * write rx fifo data that not handle. ++ */ + + if (fifo_empty_size <= rx_total_len + FUNC6_BLKSIZE) + { -+ //printk("host rx buf full\n"); ++ /* pr_debug("host rx buf full\n"); */ + up(&hal_priv->rx_thread_sem); + return ; + } + remain_len = rx_total_len; -+ /*HalPriv->rx_host_offset is host maintain pointer of sram and point to next frame. */ ++ /* HalPriv->rx_host_offset is host maintain pointer of sram and point to next frame. */ + do + { + read_len = (remain_len > (READ_LEN_PER_ONCE + READ_BUFFERABLE_LEN)) ? -+ READ_LEN_PER_ONCE : remain_len; -+ /*check if host rx_fifo wrapper around. if yes, just read remain of host rx fifo. */ ++ READ_LEN_PER_ONCE : remain_len; ++ /* check if host rx_fifo wrapper around. if yes, just read remain of host rx fifo. */ + host_remain_len = hif->rx_fifo.FDN - rx_fifo_fdt; + if (read_len >= host_remain_len) + { @@ -73822,9 +74438,10 @@ index 000000000000..1727d4a3ea37 + read_len = host_remain_len; +#endif + } -+ /*Read rx packets. but during suspend, we can't get packets by this function, ATTENTION */ ++ /* Read rx packets. but during suspend, we can't get packets by this function, ATTENTION */ + hif->hif_ops.hi_rcv_frame((hif->rx_fifo.FDB + rx_fifo_fdt), -+ (unsigned char *)(SYS_TYPE)hal_priv->rx_host_offset, read_len); ++ (unsigned char *)(SYS_TYPE)hal_priv->rx_host_offset, ++ read_len); + +#if (SDIO_UPDATE_HOST_RDPTR != 0) + if (host_wrapper_len > 0) @@ -73838,7 +74455,8 @@ index 000000000000..1727d4a3ea37 + if (host_wrapper_len > remain_len - read_len) + host_wrapper_len = remain_len - read_len; + -+ memcpy(hif->rx_fifo.FDB, (hif->rx_fifo.FDB + hif->rx_fifo.FDN), host_wrapper_len); ++ memcpy(hif->rx_fifo.FDB, (hif->rx_fifo.FDB + hif->rx_fifo.FDN), ++ host_wrapper_len); + read_len += host_wrapper_len; + + host_wrapper_len = 0; @@ -73847,17 +74465,18 @@ index 000000000000..1727d4a3ea37 + + rx_fifo_fdt = CIRCLE_Addition2(rx_fifo_fdt, read_len, hif->rx_fifo.FDN); + -+ /*Update host read pointer*/ -+ hal_priv->rx_host_offset = CIRCLE_Addition2(hal_priv->rx_host_offset, read_len, rxmax_offset); ++ /* Update host read pointer. */ ++ hal_priv->rx_host_offset = CIRCLE_Addition2(hal_priv->rx_host_offset, ++ read_len, rxmax_offset); + + remain_len -= read_len; + } + while (remain_len > 0); + +#if (SDIO_UPDATE_HOST_RDPTR == 0) -+ /*if 1, update host read pointer by sdio instead of host.*/ ++ /* if 1, update host read pointer by sdio instead of host. */ + { -+ unsigned int write_data = 0; ++ unsigned int write_data; + + write_data = BIT(31) | (hal_priv->rx_host_offset >> 2); + hif->hif_ops.hi_write_word(RG_WIFI_IF_RXPAGE_BUF_RDPTR, write_data); @@ -73866,14 +74485,15 @@ index 000000000000..1727d4a3ea37 + /* during suspend, we can't get pkt by sdio and just skip update rx_fifo.FDT */ + if (atomic_read(&hal_priv->drv_suspend_cnt) == 0) + { -+ hif->rx_fifo.FDT = CIRCLE_Addition2(hif->rx_fifo.FDT, rx_total_len, hif->rx_fifo.FDN); ++ hif->rx_fifo.FDT = CIRCLE_Addition2(hif->rx_fifo.FDT, rx_total_len, ++ hif->rx_fifo.FDN); + } + up(&hal_priv->rx_thread_sem); +} -+#elif defined (HAL_SIM_VER)/*End HAL_FPGA_VER*/ ++#elif defined (HAL_SIM_VER)/* End HAL_FPGA_VER */ +{ -+ static unsigned char rx_buffer[DEFAULT_RXPAGENUM * PAGE_LEN] = {0}; -+ /*shijie.chen add, test host recv block data via function2 one time. */ ++ static unsigned char rx_buffer[DEFAULT_RXPAGENUM * PAGE_LEN] = { 0 }; ++ /* shijie.chen add, test host recv block data via function2 one time. */ + HW_RxDescripter_bit *RxPrivHdr = NULL; + struct hw_interface *hif = NULL; + unsigned char hal_open = false; @@ -73893,36 +74513,45 @@ index 000000000000..1727d4a3ea37 + return; + } + -+ rx_total_len = CIRCLE_Subtract2(rx_fifo_fw, hal_priv->rx_host_offset, rxmax_offset); ++ rx_total_len = CIRCLE_Subtract2(rx_fifo_fw, hal_priv->rx_host_offset, ++ rxmax_offset); + remain_len = rx_total_len; -+ /*HalPriv->rx_host_offset is host maintain pointer of sram and point to next frame. */ ++ /* HalPriv->rx_host_offset is host maintain pointer of sram and ++ * point to next frame. ++ */ + do + { -+ read_len = (remain_len > READ_LEN_PER_ONCE) ? READ_LEN_PER_ONCE : remain_len; -+ /*check if wrapper around. if yes, just read remain of rx fifo. */ ++ read_len = (remain_len > READ_LEN_PER_ONCE) ? READ_LEN_PER_ONCE : ++ remain_len; ++ /* Check if wrapper around. if yes, just read remain of rx fifo. */ + if (hal_priv->rx_host_offset + read_len > rxmax_offset) + { -+ /*for stimulus, we may read X without initializing. And when rtl support wrapper around addr, -+ * we shall read by block mode to avoid sending cmd53 with a address beyond the rx buffer.Sdio -+ * rtl can't do wrapper around with this address automatically*/ ++ /* For stimulus, we may read X without initializing. And when ++ * rtl support wrapper around addr, we shall read by block mode ++ * to avoid sending cmd53 with a address beyond the rx buffer. Sdio ++ * rtl can't do wrapper around with this address automatically. ++ */ +#if (RTL_WRAPPER_AROUND_ADDR == 0) + read_len = rxmax_offset - hal_priv->rx_host_offset; +#endif + hif->hif_ops.hi_rcv_frame((unsigned char *)rx_buffer_tmp, -+ (unsigned char *)(SYS_TYPE)hal_priv->rx_host_offset, ALIGN(read_len, PAGE_LEN)); -+ /*herer, HalPriv->rx_host_offset will equal to 0 after CIRCLE_Addition*/ ++ (unsigned char *)(SYS_TYPE)hal_priv->rx_host_offset, ++ ALIGN(read_len, PAGE_LEN)); ++ /* Here, HalPriv->rx_host_offset will equal to 0 after CIRCLE_Addition. */ + } + else + { + hif->hif_ops.hi_rcv_frame((unsigned char *)rx_buffer_tmp, -+ (unsigned char *)(SYS_TYPE)hal_priv->rx_host_offset, read_len); ++ (unsigned char *)(SYS_TYPE)hal_priv->rx_host_offset, ++ read_len); + } -+ /*Update host read pointer*/ -+ hal_priv->rx_host_offset = CIRCLE_Addition2(hal_priv->rx_host_offset, read_len, rxmax_offset); ++ /* Update host read pointer. */ ++ hal_priv->rx_host_offset = CIRCLE_Addition2(hal_priv->rx_host_offset, ++ read_len, rxmax_offset); +#if (SDIO_UPDATE_HOST_RDPTR == 0) -+ /*if 1, update host read pointer by sdio instead of host.*/ ++ /* if 1, update host read pointer by sdio instead of host. */ + { -+ unsigned int write_data = 0; ++ unsigned int write_data; + + write_data = BIT(31) | (hal_priv->rx_host_offset >> 2); + hif->hif_ops.hi_write_word(RG_WIFI_IF_RXPAGE_BUF_RDPTR, write_data); @@ -73933,18 +74562,20 @@ index 000000000000..1727d4a3ea37 + } + while (remain_len > 0); + -+ /*Update host read pointer*/ ++ /* Update host read pointer. */ + while ((rx_buffer_tmp != rx_buffer) && (frame_offset != rx_total_len)) + { + RxPrivHdr = (HW_RxDescripter_bit *)&rx_buffer[frame_offset]; + framelen = RxPrivHdr->RxLength + sizeof(HW_RxDescripter_bit); ++ OS_SKBBUF * skb; + + if (RxPrivHdr->upload2host_flag != 1) + { + frame_offset += ALIGN(framelen, 4); + continue; + } -+ OS_SKBBUF * skb = OS_SKBBUF_ALLOC(framelen); ++ ++ skb = OS_SKBBUF_ALLOC(framelen); + if (skb == NULL) + { + PRINT("Couldn't allocate RX frame"); @@ -73955,11 +74586,11 @@ index 000000000000..1727d4a3ea37 + if (aml_wifi_is_enable_rf_test()) + b2b_rx_throughput_calc(RxPrivHdr); + -+ /*SKB PUT one by one */ ++ /* SKB PUT one by one. */ + OS_SKBBUF_PUT(skb, framelen); + hal_soft_rx_cs(hal_priv, skb); + -+ /*cursor for rx_buffer*/ ++ /* cursor for rx_buffer. */ + frame_offset += ALIGN(framelen, 4); + } + memset(rx_buffer, 0, frame_offset); @@ -73969,13 +74600,12 @@ index 000000000000..1727d4a3ea37 +void hi_irq_task(struct hal_private *hal_priv) +#if defined (HAL_FPGA_VER) +{ -+ unsigned int intr_status =0; ++ unsigned int intr_status; + unsigned char loop_count = 0; + unsigned char int_loop_num = 0; -+ unsigned int gpio_en = 0; -+// unsigned char i; -+// unsigned char rx_loop_num = 0; -+// unsigned int intr_status_tmp = 0; ++ //unsigned char i; ++ //unsigned char rx_loop_num = 0; ++ //unsigned int intr_status_tmp = 0; +#ifdef POWER_SAVE_NO_SDIO + unsigned int ptr = 0; +#endif @@ -74012,7 +74642,7 @@ index 000000000000..1727d4a3ea37 + if (hal_priv->hal_fw_ps_status == HAL_FW_IN_SLEEP) + hal_priv->hal_fw_ps_status = HAL_FW_IN_AWAKE; + POWER_END_LOCK(); -+ hal_priv->hal_call_back->intr_gotowakeup(hal_priv->drv_priv,1); ++ hal_priv->hal_call_back->intr_gotowakeup(hal_priv->drv_priv, 1); + } + + if (intr_status & GOTO_WAKEUP_VID0) @@ -74026,13 +74656,14 @@ index 000000000000..1727d4a3ea37 + if (hal_priv->hal_fw_ps_status == HAL_FW_IN_SLEEP) + hal_priv->hal_fw_ps_status = HAL_FW_IN_AWAKE; + POWER_END_LOCK(); -+ hal_priv->hal_call_back->intr_gotowakeup(hal_priv->drv_priv,0); ++ hal_priv->hal_call_back->intr_gotowakeup(hal_priv->drv_priv, 0); + } + + + if (intr_status & RX_OK) + { -+ unsigned int rx_fw_ptr = (intr_status & FW_RX_PTR_MASK) >> FW_RX_PTR_OFFSET; ++ unsigned int rx_fw_ptr = (intr_status & FW_RX_PTR_MASK) >> ++ FW_RX_PTR_OFFSET; + + hal_priv->sts_hirq[hirq_rx_ok_idx]++; + hi_soft_rx_irq(hal_priv, rx_fw_ptr); @@ -74066,12 +74697,12 @@ index 000000000000..1727d4a3ea37 + if (intr_status & BEACON_SEND_OK_VID1) + { + hal_priv->sts_hirq[hirq_bcn_send_ok_vid1_idx]++; -+ hal_priv->hal_call_back->intr_bcn_send(hal_priv->drv_priv,1); ++ hal_priv->hal_call_back->intr_bcn_send(hal_priv->drv_priv, 1); + } + else if (intr_status & BEACON_SEND_OK_VID0) + { + hal_priv->sts_hirq[hirq_bcn_send_ok_vid0_idx]++; -+ hal_priv->hal_call_back->intr_bcn_send(hal_priv->drv_priv,0); ++ hal_priv->hal_call_back->intr_bcn_send(hal_priv->drv_priv, 0); + } + + if (intr_status & P2P_OPPPS_CWEND_VID1) @@ -74082,7 +74713,7 @@ index 000000000000..1727d4a3ea37 + hal_priv->hal_fw_ps_status = HAL_FW_IN_SLEEP; + POWER_END_LOCK(); +#endif -+ hal_priv->hal_call_back->intr_p2p_opps_cwend(hal_priv->drv_priv,1); ++ hal_priv->hal_call_back->intr_p2p_opps_cwend(hal_priv->drv_priv, 1); + } + + if (intr_status & P2P_NoA_START_VID1) @@ -74093,7 +74724,7 @@ index 000000000000..1727d4a3ea37 + hal_priv->hal_fw_ps_status = HAL_FW_IN_SLEEP; + POWER_END_LOCK(); +#endif -+ hal_priv->hal_call_back->intr_p2p_noa_start(hal_priv->drv_priv,1); ++ hal_priv->hal_call_back->intr_p2p_noa_start(hal_priv->drv_priv, 1); + } + + if (intr_status & FW_EVENT) @@ -74130,7 +74761,7 @@ index 000000000000..1727d4a3ea37 + if (intr_status & COEX_INFO_BT_LK_INFO) + { + PRINT("--->BT link status change\n"); -+ hal_priv->hal_call_back->drv_intr_bt_info_change(hal_priv->drv_priv, 0, 1); ++ hal_priv->hal_call_back->drv_intr_bt_info_change(hal_priv->drv_priv, 0, 1); + } + + @@ -74150,28 +74781,35 @@ index 000000000000..1727d4a3ea37 + + if (loop_count > int_loop_num) + { -+ /*Enable Interrupt. */ ++ unsigned int gpio_en; ++ ++ /* Enable Interrupt. */ + gpio_en = SDIO_FW2HOST_GPIO_EN; + hi_clear_irq_status(SDIO_FW2HOST_EN); + return; + } -+// goto int_loop; ++ /* goto int_loop; */ +} +#elif defined (HAL_SIM_VER) +{ -+ unsigned int intr_status = 0; ++ struct hw_interface *hif; ++ unsigned int intr_status; ++ + intr_status = hi_get_irq_status(); -+ struct hw_interface* hif = hif_get_hw_interface(); + if (intr_status == 0) + { + return; + } + ++ hif = hif_get_hw_interface(); ++ +#ifdef STA1_VMAC0_PARAM2 -+ if(STA1_VMAC0_PARAM2 == 1){ -+ int loop=5; -+ while(loop-->0){ ++ if (STA1_VMAC0_PARAM2 == 1) { ++ int loop = 5; ++ ++ while (loop-- > 0) { + unsigned int data1, data2, data3; ++ + intr_status = hi_get_irq_status(); + + data1 = hif->hif_ops.hi_read_word(RG_MAC_RX_WPTR); @@ -74179,11 +74817,13 @@ index 000000000000..1727d4a3ea37 + data3 = hif->hif_ops.hi_read_word(RG_MAC_RX_HRPTR); + data2 = (intr_status & FW_RX_PTR_MASK) >> FW_RX_PTR_OFFSET; + hi_soft_rx_irq(hal_priv, data2); -+ PRINT("===1============>intr_status %x,%x,%x,%x\n",intr_status,data1,data2,data3); ++ PRINT("===1============>intr_status %x,%x,%x,%x\n", ++ intr_status, data1, data2, data3); + } -+ hi_clear_irq_status(SDIO_FW2HOST_EN|intr_status); ++ ++ hi_clear_irq_status(SDIO_FW2HOST_EN | intr_status); + intr_status = hi_get_irq_status(); -+ PRINT("===========********===>intr_status %x\n",intr_status); ++ PRINT("===========********===>intr_status %x\n", intr_status); + if(intr_status & BIT(1)){ + Test_Done(1); + } @@ -74197,16 +74837,16 @@ index 000000000000..1727d4a3ea37 + static int resettest = 0; + unsigned int to_sdio = 0; + -+ if (intr_status&RX_OK){ -+ if(resettest <1){ ++ if (intr_status & RX_OK) { ++ if (resettest < 1) { + resettest++; + } -+ else if(resettest == 100){ ++ else if (resettest == 100) { + } + else { + resettest = 100; -+ int loop=1; -+ unsigned int data1,data2,data3 ; ++ int loop = 1; ++ unsigned int data1, data2, data3 ; + struct hw_interface* hif = hif_get_hw_interface(); + /* while(loop-->0)*/ + { @@ -74356,73 +74996,72 @@ index 000000000000..1727d4a3ea37 +static void hif_get_mac_sts(void) +{ +#if defined (HAL_FPGA_VER) -+ unsigned int rd_data = 0; -+ int i = 0; ++ int i; + struct hw_interface* hif = hif_get_hw_interface(); + struct hif_reg_info rd_info[HIF_RD_MAC_REG_MAX]; +/* -+ char* irq_prt_info[IDX_TXSTART_IT] = "TXSTART"; -+ char* irq_prt_info[IDX_TXEND_IT] = "TXEND"; -+ char* irq_prt_info[IDX_TXENDERR] = "TXENDERR"; -+ char* irq_prt_info[IDX_ACKTO_IT] = "ACKTO_IT"; -+ char* irq_prt_info[IDX_TXCOL_FLAG] = "TXCOL"; -+ char* irq_prt_info[IDX_RXSTART_IT] = "RXSTART"; -+ char* irq_prt_info[IDX_RXEND_IT] = "RXEND"; -+ char* irq_prt_info[IDX_RXMPDU_OK] = "RXMPDU_OK"; -+ char* irq_prt_info[IDX_UNICAST] = "UNICAST"; -+ char* irq_prt_info[IDX_SRAMBUF_FULL] = "SRAMBUF_FULL"; -+ char* irq_prt_info[IDX_SWIRQ] = "SWIRQ"; -+ char* irq_prt_info[IDX_TX_FRAME_TYPE] = "TX_FRAME_TYPE"; -+ char* irq_prt_info[IDX_ABSCOUNT_INTR] = "ABSCOUNT_INTR"; -+ char* irq_prt_info[IDX_FIQ_ENABLE] = "FIQ_ENABLE"; -+ char* irq_prt_info[IDX_FIAC_FW_TIMEOUT_ERR] = "FIAC_FW_TIMEOUT_ERR"; -+ char* irq_prt_info[IDX_HW_TIMEOUT_ERR] = "HW_TIMEOUT_ERR"; -+ char* irq_prt_info[IDX_TX_WD_TIMEOUT_ERR] = "TX_WD_TIMEOUT_ERR"; -+ char* irq_prt_info[IDX_TXINVALIDLEN_ERR] = "TXINVALIDLEN_ERR"; -+ char* irq_prt_info[IDX_TX_KEYMISS] = "TX_KEYMISS"; -+ char* irq_prt_info[IDX_TXIMSTOP_ERR] = "TXIMSTOP_ERR"; -+ char* irq_prt_info[IDX_TX_PHYERROR] = "TX_PHYERROR"; -+ char* irq_prt_info[IDX_TXCOL_QUEUE] = "TXCOL_QUEUE"; -+ char* irq_prt_info[IDX_TX_NOT_GRANT] = "TX_NOT_GRANT"; -+ char* irq_prt_info[IDX_SRAMBUF_FULL_ERR] = "SRAMBUF_FULL_ERR"; -+ char* irq_prt_info[IDX_FCSERR] = "FCSERR"; -+ char* irq_prt_info[IDX_RXFIFOOV] = "RXFIFOOV"; -+ char* irq_prt_info[IDX_RX_WD_TIMEOUT_ERR] = "RX_WD_TIMEOUT_ERR"; -+ char* irq_prt_info[IDX_SHORT_LENGTH] = "SHORT_LENGTH "; -+ char* irq_prt_info[IDX_LENGTH_ERROR] = "LENGTH_ERROR"; -+ char* irq_prt_info[IDX_RX_PHYERROR] = "RX_PHYERROR"; ++ char* irq_prt_info[IDX_TXSTART_IT] = "TXSTART"; ++ char* irq_prt_info[IDX_TXEND_IT] = "TXEND"; ++ char* irq_prt_info[IDX_TXENDERR] = "TXENDERR"; ++ char* irq_prt_info[IDX_ACKTO_IT] = "ACKTO_IT"; ++ char* irq_prt_info[IDX_TXCOL_FLAG] = "TXCOL"; ++ char* irq_prt_info[IDX_RXSTART_IT] = "RXSTART"; ++ char* irq_prt_info[IDX_RXEND_IT] = "RXEND"; ++ char* irq_prt_info[IDX_RXMPDU_OK] = "RXMPDU_OK"; ++ char* irq_prt_info[IDX_UNICAST] = "UNICAST"; ++ char* irq_prt_info[IDX_SRAMBUF_FULL] = "SRAMBUF_FULL"; ++ char* irq_prt_info[IDX_SWIRQ] = "SWIRQ"; ++ char* irq_prt_info[IDX_TX_FRAME_TYPE] = "TX_FRAME_TYPE"; ++ char* irq_prt_info[IDX_ABSCOUNT_INTR] = "ABSCOUNT_INTR"; ++ char* irq_prt_info[IDX_FIQ_ENABLE] = "FIQ_ENABLE"; ++ char* irq_prt_info[IDX_FIAC_FW_TIMEOUT_ERR] = "FIAC_FW_TIMEOUT_ERR"; ++ char* irq_prt_info[IDX_HW_TIMEOUT_ERR] = "HW_TIMEOUT_ERR"; ++ char* irq_prt_info[IDX_TX_WD_TIMEOUT_ERR] = "TX_WD_TIMEOUT_ERR"; ++ char* irq_prt_info[IDX_TXINVALIDLEN_ERR] = "TXINVALIDLEN_ERR"; ++ char* irq_prt_info[IDX_TX_KEYMISS] = "TX_KEYMISS"; ++ char* irq_prt_info[IDX_TXIMSTOP_ERR] = "TXIMSTOP_ERR"; ++ char* irq_prt_info[IDX_TX_PHYERROR] = "TX_PHYERROR"; ++ char* irq_prt_info[IDX_TXCOL_QUEUE] = "TXCOL_QUEUE"; ++ char* irq_prt_info[IDX_TX_NOT_GRANT] = "TX_NOT_GRANT"; ++ char* irq_prt_info[IDX_SRAMBUF_FULL_ERR] = "SRAMBUF_FULL_ERR"; ++ char* irq_prt_info[IDX_FCSERR] = "FCSERR"; ++ char* irq_prt_info[IDX_RXFIFOOV] = "RXFIFOOV"; ++ char* irq_prt_info[IDX_RX_WD_TIMEOUT_ERR] = "RX_WD_TIMEOUT_ERR"; ++ char* irq_prt_info[IDX_SHORT_LENGTH] = "SHORT_LENGTH "; ++ char* irq_prt_info[IDX_LENGTH_ERROR] = "LENGTH_ERROR"; ++ char* irq_prt_info[IDX_RX_PHYERROR] = "RX_PHYERROR"; +*/ -+ rd_info[0].addr= RG_MAC_IRQ_STATUS_CNT0; -+ rd_info[1].addr= RG_MAC_IRQ_STATUS_CNT1; -+ rd_info[2].addr= RG_MAC_IRQ_STATUS_CNT2; -+ rd_info[3].addr= RG_MAC_IRQ_STATUS_CNT3; -+ -+ rd_info[4].addr= RG_MAC_FRM_TYPE_CNT0; -+ rd_info[5].addr= RG_MAC_FRM_TYPE_CNT1; -+ rd_info[6].addr= RG_MAC_FRM_TYPE_CNT2; -+ rd_info[7].addr= RG_MAC_FRM_TYPE_CNT3; -+ -+ rd_info[8].addr= RG_MAC_TX_STT_CHK; -+ rd_info[9].addr= RG_MAC_TX_END_CHK; -+ rd_info[10].addr= RG_MAC_TX_EN_CHK; -+ rd_info[11].addr= RG_MAC_TX_ENWR_CHK; -+ -+ rd_info[12].addr= RG_MAC_RX_DATA_LOCAL_CNT; -+ rd_info[13].addr= RG_MAC_RX_DATA_OTHER_CNT; -+ rd_info[14].addr= RG_MAC_RX_DATA_MUTIL_CNT; -+ -+ rd_info[0].prt= "irq_cnt_0"; -+ rd_info[1].prt= "irq_cnt_1"; -+ rd_info[2].prt= "irq_cnt_2"; -+ rd_info[3].prt= "irq_cnt_3"; -+ -+ rd_info[4].prt= "rx_rts"; -+ rd_info[5].prt= "rx_cts"; -+ rd_info[6].prt= "rx_ack"; -+ rd_info[7].prt= "rx_qos_data"; -+ -+ rd_info[8].prt= "tx_stt_chk"; -+ rd_info[9].prt= "tx_end_chk"; ++ rd_info[0].addr = RG_MAC_IRQ_STATUS_CNT0; ++ rd_info[1].addr = RG_MAC_IRQ_STATUS_CNT1; ++ rd_info[2].addr = RG_MAC_IRQ_STATUS_CNT2; ++ rd_info[3].addr = RG_MAC_IRQ_STATUS_CNT3; ++ ++ rd_info[4].addr = RG_MAC_FRM_TYPE_CNT0; ++ rd_info[5].addr = RG_MAC_FRM_TYPE_CNT1; ++ rd_info[6].addr = RG_MAC_FRM_TYPE_CNT2; ++ rd_info[7].addr = RG_MAC_FRM_TYPE_CNT3; ++ ++ rd_info[8].addr = RG_MAC_TX_STT_CHK; ++ rd_info[9].addr = RG_MAC_TX_END_CHK; ++ rd_info[10].addr = RG_MAC_TX_EN_CHK; ++ rd_info[11].addr = RG_MAC_TX_ENWR_CHK; ++ ++ rd_info[12].addr = RG_MAC_RX_DATA_LOCAL_CNT; ++ rd_info[13].addr = RG_MAC_RX_DATA_OTHER_CNT; ++ rd_info[14].addr = RG_MAC_RX_DATA_MUTIL_CNT; ++ ++ rd_info[0].prt = "irq_cnt_0"; ++ rd_info[1].prt = "irq_cnt_1"; ++ rd_info[2].prt = "irq_cnt_2"; ++ rd_info[3].prt = "irq_cnt_3"; ++ ++ rd_info[4].prt = "rx_rts"; ++ rd_info[5].prt = "rx_cts"; ++ rd_info[6].prt = "rx_ack"; ++ rd_info[7].prt = "rx_qos_data"; ++ ++ rd_info[8].prt = "tx_stt_chk"; ++ rd_info[9].prt = "tx_end_chk"; + rd_info[10].prt = "tx_en_chk"; + rd_info[11].prt = "tx_enwr_chk"; + @@ -74432,26 +75071,28 @@ index 000000000000..1727d4a3ea37 + + for (i = 0; i < HIF_RD_MAC_REG_MAX; i++) + { ++ unsigned int rd_data; ++ + rd_data = hif->hif_ops.hi_read_word(rd_info[i].addr); + + if(rd_info[i].addr == RG_MAC_RX_DATA_LOCAL_CNT) + { + rd_data = (rd_data << 3 ) >> 3; + } -+ else if(rd_info[i].addr == RG_MAC_RX_DATA_OTHER_CNT || ++ else if(rd_info[i].addr == RG_MAC_RX_DATA_OTHER_CNT || + rd_info[i].addr == RG_MAC_RX_DATA_MUTIL_CNT ) + { + rd_data = (rd_data << 2 ) >> 2; + } + else if (rd_info[i].addr == RG_MAC_TX_STT_CHK || -+ rd_info[i].addr == RG_MAC_TX_END_CHK|| -+ rd_info[i].addr == RG_MAC_TX_EN_CHK|| -+ rd_info[i].addr == RG_MAC_TX_ENWR_CHK) ++ rd_info[i].addr == RG_MAC_TX_END_CHK || ++ rd_info[i].addr == RG_MAC_TX_EN_CHK || ++ rd_info[i].addr == RG_MAC_TX_ENWR_CHK) + { + rd_data = (rd_data << 6 ) >> 6; + } + -+ printk("%s, %d\n", rd_info[i].prt, rd_data); ++ pr_debug("%s, %d\n", rd_info[i].prt, rd_data); + } +#endif +} @@ -74460,91 +75101,95 @@ index 000000000000..1727d4a3ea37 +{ +#if defined (HAL_FPGA_VER) + struct hif_reg_info rd_info[HIF_RD_PHY_REG_MAX]; -+ int i = 0; -+ unsigned int rd_data = 0; -+ struct hw_interface* hif = hif_get_hw_interface(); -+ -+ rd_info[0].addr= RG_AGC_STATE; -+ rd_info[1].addr= RG_AGC_OB_IC_GAIN; -+ rd_info[2].addr= RG_AGC_WATCH1; -+ rd_info[3].addr= RG_AGC_WATCH2; ++ int i; ++ struct hw_interface *hif = hif_get_hw_interface(); ++ ++ rd_info[0].addr = RG_AGC_STATE; ++ rd_info[1].addr = RG_AGC_OB_IC_GAIN; ++ rd_info[2].addr = RG_AGC_WATCH1; ++ rd_info[3].addr = RG_AGC_WATCH2; + -+ rd_info[4].addr= RG_AGC_WATCH3; -+ rd_info[5].addr= RG_AGC_WATCH4; -+ rd_info[6].addr= RG_AGC_OB_ANT_NFLOOR; -+ rd_info[7].addr= RG_AGC_OB_CCA_RES; ++ rd_info[4].addr = RG_AGC_WATCH3; ++ rd_info[5].addr = RG_AGC_WATCH4; ++ rd_info[6].addr = RG_AGC_OB_ANT_NFLOOR; ++ rd_info[7].addr = RG_AGC_OB_CCA_RES; + -+ rd_info[8].addr= RG_AGC_OB_CCA_COND01; -+ rd_info[9].addr= RG_AGC_OB_CCA_COND23; ++ rd_info[8].addr = RG_AGC_OB_CCA_COND01; ++ rd_info[9].addr = RG_AGC_OB_CCA_COND23; + + for (i = 0; i < HIF_RD_PHY_REG_MAX; i++) + { ++ unsigned int rd_data; ++ + rd_data = hif->hif_ops.hi_read_word(rd_info[i].addr); -+ if(rd_info[i].addr == RG_AGC_STATE) ++ if (rd_info[i].addr == RG_AGC_STATE) + { -+ struct sts_agc_state* agc_state = (struct sts_agc_state*) &rd_data; -+ printk("agc-state=0x%x,\n", agc_state->state); ++ struct sts_agc_state *agc_state = (struct sts_agc_state *)&rd_data; ++ pr_debug("agc-state=0x%x,\n", agc_state->state); + } + -+ if(rd_info[i].addr == RG_AGC_OB_IC_GAIN) ++ if (rd_info[i].addr == RG_AGC_OB_IC_GAIN) + { -+ struct sts_agc_ob_ic_gain* agc_ob_ic_gain =(struct sts_agc_ob_ic_gain*)&rd_data; -+ printk("r_agc_fine_db=0x%x, r_rx_ic_gain=0x%x,\n", ++ struct sts_agc_ob_ic_gain *agc_ob_ic_gain = (struct sts_agc_ob_ic_gain *)&rd_data; ++ pr_debug("r_agc_fine_db=0x%x, r_rx_ic_gain=0x%x,\n", + agc_ob_ic_gain->r_agc_fine_db, agc_ob_ic_gain->r_rx_ic_gain); + } + -+ if(rd_info[i].addr == RG_AGC_WATCH1) ++ if (rd_info[i].addr == RG_AGC_WATCH1) + { -+ struct sts_agc_watch1* agc_watch1 = (struct sts_agc_watch1*)&rd_data; -+ printk("r_pow_sat_db=0x%x, r_primary20_db=0x%x,\n", -+ agc_watch1->r_pow_sat_db, agc_watch1->r_primary20_db); ++ struct sts_agc_watch1 *agc_watch1 = (struct sts_agc_watch1 *)&rd_data; ++ pr_debug("r_pow_sat_db=0x%x, r_primary20_db=0x%x,\n", ++ agc_watch1->r_pow_sat_db, agc_watch1->r_primary20_db); + } + -+ if(rd_info[i].addr == RG_AGC_WATCH2) ++ if (rd_info[i].addr == RG_AGC_WATCH2) + { -+ struct sts_agc_watch2* agc_watch2 = (struct sts_agc_watch2*)&rd_data; -+ printk("r_primary40_db=0x%x, r_primary80_db=0x%x,\n", ++ struct sts_agc_watch2 *agc_watch2 = (struct sts_agc_watch2 *)&rd_data; ++ pr_debug("r_primary40_db=0x%x, r_primary80_db=0x%x,\n", + agc_watch2->r_primary40_db, agc_watch2->r_primary80_db); + } + -+ if(rd_info[i].addr == RG_AGC_WATCH3) ++ if (rd_info[i].addr == RG_AGC_WATCH3) + { -+ struct sts_agc_watch3*agc_watch3 = (struct sts_agc_watch3*)&rd_data; -+ printk("r_rssi0_db=0x%x, r_rssi1_db=0x%x,\n", ++ struct sts_agc_watch3 *agc_watch3 = (struct sts_agc_watch3 *)&rd_data; ++ pr_debug("r_rssi0_db=0x%x, r_rssi1_db=0x%x,\n", + agc_watch3->r_rssi0_db, agc_watch3->r_rssi1_db); + } + -+ if(rd_info[i].addr == RG_AGC_WATCH4) ++ if (rd_info[i].addr == RG_AGC_WATCH4) + { -+ struct sts_agc_watch4* agc_watch4 = (struct sts_agc_watch4*)&rd_data; ++ struct sts_agc_watch4 *agc_watch4 = (struct sts_agc_watch4 *)&rd_data; + -+ printk("r_rssi2_db=0x%x, r_rssi3_db=0x%x,\n", -+ agc_watch4->r_rssi2_db, agc_watch4->r_rssi3_db); ++ pr_debug("r_rssi2_db=0x%x, r_rssi3_db=0x%x,\n", ++ agc_watch4->r_rssi2_db, agc_watch4->r_rssi3_db); + } + -+ if(rd_info[i].addr == RG_AGC_OB_ANT_NFLOOR) ++ if (rd_info[i].addr == RG_AGC_OB_ANT_NFLOOR) + { -+ struct sts_ob_ant_nfloor* ob_ant_nfloor = (struct sts_ob_ant_nfloor*)&rd_data; -+ printk("r_ant_nfloor_qdb=0x%x, r_snr_qdb=0x%x,\n", ob_ant_nfloor->r_ant_nfloor_qdb, ob_ant_nfloor->r_snr_qdb); ++ struct sts_ob_ant_nfloor *ob_ant_nfloor = (struct sts_ob_ant_nfloor *)&rd_data; ++ pr_debug("r_ant_nfloor_qdb=0x%x, r_snr_qdb=0x%x,\n", ++ ob_ant_nfloor->r_ant_nfloor_qdb, ob_ant_nfloor->r_snr_qdb); + } + -+ if(rd_info[i].addr == RG_AGC_OB_CCA_RES) ++ if (rd_info[i].addr == RG_AGC_OB_CCA_RES) + { -+ struct sts_ob_cca_res* ob_cca_res = (struct sts_ob_cca_res*)&rd_data; -+ printk("cca_cond8=0x%x, cca_cond_rdy=0x%x,\n", ob_cca_res->cca_cond8, ob_cca_res->cca_cond_rdy); ++ struct sts_ob_cca_res *ob_cca_res = (struct sts_ob_cca_res *)&rd_data; ++ pr_debug("cca_cond8=0x%x, cca_cond_rdy=0x%x,\n", ++ ob_cca_res->cca_cond8, ob_cca_res->cca_cond_rdy); + } + -+ if(rd_info[i].addr == RG_AGC_OB_CCA_COND01) ++ if (rd_info[i].addr == RG_AGC_OB_CCA_COND01) + { -+ struct sts_ob_cca_cond01* ob_cca_cond01 = (struct sts_ob_cca_cond01*)&rd_data; -+ printk("cca_cond0=0x%x, cca_cond1=0x%x,\n", ++ struct sts_ob_cca_cond01 *ob_cca_cond01 = (struct sts_ob_cca_cond01 *)&rd_data; ++ pr_debug("cca_cond0=0x%x, cca_cond1=0x%x,\n", + ob_cca_cond01->cca_cond0, ob_cca_cond01->cca_cond1); + } + -+ if(rd_info[i].addr == RG_AGC_OB_CCA_COND23) ++ if (rd_info[i].addr == RG_AGC_OB_CCA_COND23) + { -+ struct sts_ob_cca_cond23* ob_cca_cond23 = (struct sts_ob_cca_cond23*)&rd_data; -+ printk("cca_cond2=0x%x, cca_cond3=0x%x,\n",ob_cca_cond23->cca_cond2, ob_cca_cond23->cca_cond3); ++ struct sts_ob_cca_cond23 *ob_cca_cond23 = (struct sts_ob_cca_cond23 *)&rd_data; ++ pr_debug("cca_cond2=0x%x, cca_cond3=0x%x,\n", ++ ob_cca_cond23->cca_cond2, ob_cca_cond23->cca_cond3); + } + } +#endif @@ -74555,27 +75200,29 @@ index 000000000000..1727d4a3ea37 +#define RG_MAC_RX_FRPTR (WIFI_MAC + 0x200) +#define RG_MAC_RX_HRPTR (WIFI_MAC + 0x204) + -+void hif_get_hst_int_status(void) ++static void hif_get_hst_int_status(void) +{ + struct hal_private *hal_prv = hal_get_priv(); + -+ printk("fw2hst_int_status 0x%x rx_dbuf_fw_rptr 0x%x\n", -+ (hal_prv->int_status_copy>> 16) & 0xffff, -+ hal_prv->int_status_copy & 0xffff); ++ pr_debug("fw2hst_int_status 0x%x rx_dbuf_fw_rptr 0x%x\n", ++ (hal_prv->int_status_copy>> 16) & 0xffff, ++ hal_prv->int_status_copy & 0xffff); + +} ++ +void hif_get_sts(unsigned int op_code, unsigned int ctrl_code) +{ +#if defined (HAL_FPGA_VER) -+ struct hw_interface* hif = hif_get_hw_interface(); -+ unsigned int buf_rd = 0; -+ unsigned int mac_wt = 0; -+ unsigned int fw_rd = 0; -+ unsigned int sdio_rd = 0; + -+ if((ctrl_code & STS_MOD_HIF) == STS_MOD_HIF) ++ if ((ctrl_code & STS_MOD_HIF) == STS_MOD_HIF) + { -+ printk("\n--------hif statistic--------\n"); ++ struct hw_interface *hif = hif_get_hw_interface(); ++ unsigned int buf_rd; ++ unsigned int mac_wt; ++ unsigned int fw_rd; ++ unsigned int sdio_rd; ++ ++ pr_debug("\n--------hif statistic--------\n"); + buf_rd = hif->hif_ops.hi_read_word(RG_WIFI_IF_RXPAGE_BUF_RDPTR) ; + mac_wt = hif->hif_ops.hi_read_word(RG_MAC_RX_WPTR); + fw_rd = hif->hif_ops.hi_read_word(RG_MAC_RX_FRPTR); @@ -74583,28 +75230,26 @@ index 000000000000..1727d4a3ea37 + + if ((ctrl_code & STS_TYP_RX) == STS_TYP_RX) + { -+ printk("rx_fifo: head %ld, tail %ld, total %ld\n", -+ hif->rx_fifo.FDH, hif->rx_fifo.FDT, hif->rx_fifo.FDN); ++ pr_debug("rx_fifo: head %ld, tail %ld, total %ld\n", ++ hif->rx_fifo.FDH, hif->rx_fifo.FDT, hif->rx_fifo.FDN); + -+ printk("rx by word: free %d, fw_to_do %d, sdio_to_mv %d, buf_rd_ptr 0x%x, mac_wt_ptr 0x%x, fw_rd_ptr 0x%x, sdio_rd_ptr 0x%x \n", -+ CIRCLE_Subtract2(sdio_rd, mac_wt, DEFAULT_RXPAGENUM*PAGE_LEN/4), -+ CIRCLE_Subtract2(mac_wt, fw_rd, DEFAULT_RXPAGENUM*PAGE_LEN/4), -+ CIRCLE_Subtract2( fw_rd, sdio_rd,DEFAULT_RXPAGENUM*PAGE_LEN/4), -+ buf_rd,mac_wt,fw_rd,sdio_rd); ++ pr_debug("rx by word: free %d, fw_to_do %d, sdio_to_mv %d, buf_rd_ptr 0x%x, mac_wt_ptr 0x%x, fw_rd_ptr 0x%x, sdio_rd_ptr 0x%x \n", ++ CIRCLE_Subtract2(sdio_rd, mac_wt, DEFAULT_RXPAGENUM * PAGE_LEN / 4), ++ CIRCLE_Subtract2(mac_wt, fw_rd, DEFAULT_RXPAGENUM * PAGE_LEN / 4), ++ CIRCLE_Subtract2( fw_rd, sdio_rd,DEFAULT_RXPAGENUM * PAGE_LEN / 4), ++ buf_rd, mac_wt, fw_rd, sdio_rd); + + } + -+ hif_get_hst_int_status(); -+ hif_get_mac_sts(); -+ hif_get_phy_sts(); ++ hif_get_hst_int_status(); ++ hif_get_mac_sts(); ++ hif_get_phy_sts(); + } +#endif +} + -+ +void hif_pt_rx_start(unsigned int qos) +{ -+ +#if defined (HAL_FPGA_VER) + unsigned int chg_data = 0; + struct data_rx_local_cnt_bits* data_rx_local_cnt =NULL; @@ -74689,7 +75334,7 @@ index 000000000000..1727d4a3ea37 + //hif->sts_snr.snr_run = 0; + //hif->sts_snr.snr_avr /=hif->sts_snr.snr_num; + -+ printk("rx_ucast=0x%x,rx_other=0x%x,rx_mcast=0x%x,rx_fcserr=0x%x,\n", ++ pr_debug("rx_ucast=0x%x,rx_other=0x%x,rx_mcast=0x%x,rx_fcserr=0x%x,\n", + (rx_ucast<<3)>>3, (rx_other<<2)>>2, (rx_mcast<<2)>>2,rx_fcserr); + + chg_data = hif->hif_ops.hi_read_word(RG_MAC_RX_DATA_LOCAL_CNT); @@ -74729,212 +75374,212 @@ index 000000000000..1727d4a3ea37 +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_hif.h b/drivers/net/wireless/w1/vmac/wifi_hif.h new file mode 100644 -index 000000000000..8f08e00371e6 +index 0000000000000000000000000000000000000000..8918c7e2782809b5259d10724f1ac0f71ed34273 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_hif.h @@ -0,0 +1,196 @@ -+#ifndef _HI_SDIO_H_ -+#define _HI_SDIO_H_ -+ -+#include "wifi_sdio.h" -+ -+#define HIF_RD_MAC_REG_MAX (15) -+#define HIF_RD_PHY_REG_MAX (10) -+ -+ -+//irq -+#define COEX_INFO_BT_LK_INFO BEACON_RECV_OK_VID0 -+#define COEX_BT_EXIST_INF0 BEACON_RECV_OK_VID1 -+ -+ -+/*shijie.chen add, need add to register define file */ -+#define BCN_READABLE BIT(31) -+#define BCN_LEN_MASK (BIT(17)|BIT(18)|BIT(19)) -+ -+struct hif_reg_info{ -+ unsigned int addr; -+ unsigned char* prt; -+}; -+ -+enum hif_suspend_state -+{ -+ HIF_SUSPEND_STATE_NONE, -+ HIF_SUSPEND_STATE_WOW, -+ HIF_SUSPEND_STATE_DEEPSLEEP, -+}; -+ -+/*1 is rtl support addr wrapper around, else 0 is not support. */ -+#define RTL_WRAPPER_AROUND_ADDR 1 -+/*sdio max block count when we use scatter/gather list.*/ -+#define SDIO_MAX_BLK_CNT 511 -+/*enable sdio update host rd/wr pointer by enable corresponding bit in -+ SDIO MISC CTRL or SDIO MISC CTRL2 */ -+/* when 1, wrptr is updated by sdio rtl(func4). when 0, is updated by host via send cmd53 */ -+#define SDIO_UPDATE_HOST_WRPTR 0 -+/* when 1, rdptr is updated by sdio rtl(func6). when 0, is updated by host via send cmd53 */ -+#define SDIO_UPDATE_HOST_RDPTR 1 -+ -+#define SG_NUM_MAX 16 -+#define SG_WRITE 1 //MMC_DATA_WRITE -+#define SG_FRAME_MAX (1 * SG_NUM_MAX) -+/* max page num while process a sdio write operation*/ -+#define SG_PAGE_MAX 80 -+#define FUNC4_BLKSIZE PAGE_LEN -+#define FUNC6_BLKSIZE PAGE_LEN -+#define BLKSIZE PAGE_LEN -+ -+#define HIF_READ 0x00000001 -+#define HIF_WRITE 0x00000002 -+#define HIF_SYNCHRONOUS 0x00000010 -+#define HIF_ASYNCHRONOUS 0x00000020 -+ -+#define SDIO_MAXSG_SIZE 32 -+#define SDIO_MAX_SG_ENTRIES (SDIO_MAXSG_SIZE+2) -+ -+#if defined (HAL_FPGA_VER) -+struct amlw_hif_scatter_item { -+ struct sk_buff * skbbuf; -+ int len; -+ int page_num; -+ void * packet; -+}; -+ -+struct amlw_hif_scatter_req { -+ -+ /* address for the read/write operation */ -+ unsigned int addr; -+ /* request flags */ -+ unsigned int req; -+ /* total length of entire transfer */ -+ unsigned int len; -+ -+ void (*complete) (struct sk_buff *); -+ -+ bool free; -+ int result; -+ int scat_count; -+ -+ struct scatterlist sgentries[SDIO_MAX_SG_ENTRIES]; -+ struct amlw_hif_scatter_item scat_list[SDIO_MAX_SG_ENTRIES]; -+}; -+#endif -+ -+struct amlw_hif_ops { -+ int (*hi_bottom_write8)(unsigned char func_num, int addr, unsigned char data); -+ unsigned char (*hi_bottom_read8)(unsigned char func_num, int addr); -+ int (*hi_bottom_read)(unsigned char func_num, int addr, void *buf, size_t len, int incr_addr); -+ int (*hi_bottom_write)(unsigned char func_num, int addr, void *buf, size_t len, int incr_addr); -+ -+ unsigned char (*hi_read8_func0)(unsigned long sram_addr); -+ void (*hi_write8_func0)(unsigned long sram_addr, unsigned char sramdata); -+ -+ unsigned long (*hi_read_reg8)(unsigned long sram_addr); -+ void (*hi_write_reg8)(unsigned long sram_addr, unsigned long sramdata); -+ unsigned long (*hi_read_reg32)(unsigned long sram_addr); -+ int (*hi_write_reg32)(unsigned long sram_addr, unsigned long sramdata); -+ -+ void (*hi_write_cmd)(unsigned long sram_addr, unsigned long sramdata); -+ void (*hi_write_sram)(unsigned char*buf, unsigned char* addr, SYS_TYPE len); -+ void (*hi_read_sram)(unsigned char* buf, unsigned char* addr, SYS_TYPE len); -+ void (*hi_write_word)(unsigned int addr,unsigned int data); -+ unsigned int (*hi_read_word)(unsigned int addr); -+ -+ void (*hi_rcv_frame)(unsigned char* buf, unsigned char* addr, SYS_TYPE len); -+#if defined (HAL_FPGA_VER) -+ int (*hi_enable_scat)(void); -+ void (*hi_cleanup_scat)(void); -+ struct amlw_hif_scatter_req * (*hi_get_scatreq)(void); -+ int (*hi_scat_rw)(struct scatterlist *sg_list, unsigned int sg_num, unsigned int blkcnt, -+ unsigned char func_num, unsigned int addr, unsigned char write); -+ int (*hi_send_frame)(struct amlw_hif_scatter_req *scat_req); -+#elif defined (HAL_SIM_VER) -+ void (*hi_send_frame)(unsigned char* buf, unsigned char* addr, SYS_TYPE len); -+#endif -+ -+ /*bt use*/ -+ void (*bt_hi_write_sram)(unsigned char* buf, unsigned char* addr, SYS_TYPE len); -+ void (*bt_hi_read_sram)(unsigned char* buf, unsigned char* addr, SYS_TYPE len); -+ void (*bt_hi_write_word)(unsigned int addr,unsigned int data); -+ unsigned int (*bt_hi_read_word)(unsigned int addr); -+ -+ void (*hif_get_sts)(unsigned int op_code, unsigned int ctrl_code); -+ void (*hif_pt_rx_start)(unsigned int qos); -+ void (*hif_pt_rx_stop)(void); -+ -+ int (*hif_suspend)(unsigned int suspend_enable); -+}; -+ -+void hi_clear_irq_status(unsigned int data); -+unsigned int hi_get_irq_status(void); -+unsigned char hi_set_cmd(unsigned char *pdata,unsigned int len); -+unsigned char hi_get_cmd(unsigned char *pdata,unsigned int len); -+ -+unsigned int hi_get_device_id(void); -+unsigned int hi_get_vendor_id(void); -+unsigned int hi_get_fw_version(void); -+ -+void hi_top_task( unsigned long data); -+void hi_soft_tx_irq(void); -+ -+ -+void hif_init_ops(void); -+ -+void hi_soft_rx_irq(struct hal_private *hal_priv, unsigned int rx_fw_ptr); -+void hi_soft_rx_bcn(struct hal_private *hal_priv, unsigned char vid); -+ -+void hi_cfg_firmware(void); -+void show_macframe (unsigned char *start, unsigned char len); -+void set_wifi_baudrate (unsigned int apb_clk); -+ -+void hif_pt_rx_start(unsigned int qos); -+void hif_pt_rx_stop(void); -+ -+#if defined (HAL_FPGA_VER) -+struct tx_status_list { -+ struct list_head status_list; -+ struct list_head free_list; -+ spinlock_t status_list_lock; -+}; -+ -+struct tx_status_node { -+ struct list_head list_node; -+ union -+ { -+ struct txdonestatus txstatus; -+ struct tx_nulldata_status tx_null_status; -+ }tx_status; -+}; -+int hi_tx_frame(struct hi_tx_desc **pTxDPape, unsigned int mpdu_num, unsigned int page_num); -+int hi_sdio_setup_scat_data(struct scatterlist *sg_list, struct hi_tx_desc **pTxDPape, -+ unsigned int sg_num, unsigned char func_num); -+ -+/*txok status process */ -+int tx_status_list_init(struct tx_status_list *tx_status_list, int num); -+void tx_status_node_free(struct tx_status_node *txok_status_node, -+ struct tx_status_list *tx_status_list); -+void tx_status_node_enqueue(struct tx_status_node *txok_status_node, -+ struct tx_status_list *tx_status_list); -+struct tx_status_node * tx_status_node_dequeue(struct tx_status_list *tx_status_list); -+struct tx_status_node * tx_status_node_alloc(struct tx_status_list *tx_status_list); -+void hi_irq_task(struct hal_private *hal_priv); -+void hi_rx_fifo_init(void); -+ -+#elif defined (HAL_SIM_VER) -+int hi_tx_frame( struct hi_tx_desc* pTxDPape, unsigned int blk_num, unsigned int page_num); -+int hal_calc_block_in_mpdu (int mpdulen); -+#endif -+unsigned int MAC_RD_REG(unsigned int addr); -+void MAC_WR_REG(unsigned int addr,unsigned int data); -+ -+void b2b_rx_throughput_calc(HW_RxDescripter_bit *RxPrivHdr); -+ -+#endif //_HI_SDIO_H_ ++#ifndef _HI_SDIO_H_ ++#define _HI_SDIO_H_ ++ ++#include "wifi_sdio.h" ++ ++#define HIF_RD_MAC_REG_MAX (15) ++#define HIF_RD_PHY_REG_MAX (10) ++ ++ ++//irq ++#define COEX_INFO_BT_LK_INFO BEACON_RECV_OK_VID0 ++#define COEX_BT_EXIST_INF0 BEACON_RECV_OK_VID1 ++ ++ ++/*shijie.chen add, need add to register define file */ ++#define BCN_READABLE BIT(31) ++#define BCN_LEN_MASK (BIT(17)|BIT(18)|BIT(19)) ++ ++struct hif_reg_info{ ++ unsigned int addr; ++ unsigned char* prt; ++}; ++ ++enum hif_suspend_state ++{ ++ HIF_SUSPEND_STATE_NONE, ++ HIF_SUSPEND_STATE_WOW, ++ HIF_SUSPEND_STATE_DEEPSLEEP, ++}; ++ ++/*1 is rtl support addr wrapper around, else 0 is not support. */ ++#define RTL_WRAPPER_AROUND_ADDR 1 ++/*sdio max block count when we use scatter/gather list.*/ ++#define SDIO_MAX_BLK_CNT 511 ++/*enable sdio update host rd/wr pointer by enable corresponding bit in ++ SDIO MISC CTRL or SDIO MISC CTRL2 */ ++/* when 1, wrptr is updated by sdio rtl(func4). when 0, is updated by host via send cmd53 */ ++#define SDIO_UPDATE_HOST_WRPTR 0 ++/* when 1, rdptr is updated by sdio rtl(func6). when 0, is updated by host via send cmd53 */ ++#define SDIO_UPDATE_HOST_RDPTR 1 ++ ++#define SG_NUM_MAX 16 ++#define SG_WRITE 1 //MMC_DATA_WRITE ++#define SG_FRAME_MAX (1 * SG_NUM_MAX) ++/* max page num while process a sdio write operation*/ ++#define SG_PAGE_MAX 80 ++#define FUNC4_BLKSIZE PAGE_LEN ++#define FUNC6_BLKSIZE PAGE_LEN ++#define BLKSIZE PAGE_LEN ++ ++#define HIF_READ 0x00000001 ++#define HIF_WRITE 0x00000002 ++#define HIF_SYNCHRONOUS 0x00000010 ++#define HIF_ASYNCHRONOUS 0x00000020 ++ ++#define SDIO_MAXSG_SIZE 32 ++#define SDIO_MAX_SG_ENTRIES (SDIO_MAXSG_SIZE+2) ++ ++#if defined (HAL_FPGA_VER) ++struct amlw_hif_scatter_item { ++ struct sk_buff * skbbuf; ++ int len; ++ int page_num; ++ void * packet; ++}; ++ ++struct amlw_hif_scatter_req { ++ ++ /* address for the read/write operation */ ++ unsigned int addr; ++ /* request flags */ ++ unsigned int req; ++ /* total length of entire transfer */ ++ unsigned int len; ++ ++ void (*complete) (struct sk_buff *); ++ ++ bool free; ++ int result; ++ int scat_count; ++ ++ struct scatterlist sgentries[SDIO_MAX_SG_ENTRIES]; ++ struct amlw_hif_scatter_item scat_list[SDIO_MAX_SG_ENTRIES]; ++}; ++#endif ++ ++struct amlw_hif_ops { ++ int (*hi_bottom_write8)(unsigned char func_num, int addr, unsigned char data); ++ unsigned char (*hi_bottom_read8)(unsigned char func_num, int addr); ++ int (*hi_bottom_read)(unsigned char func_num, int addr, void *buf, size_t len, int incr_addr); ++ int (*hi_bottom_write)(unsigned char func_num, int addr, void *buf, size_t len, int incr_addr); ++ ++ unsigned char (*hi_read8_func0)(unsigned long sram_addr); ++ void (*hi_write8_func0)(unsigned long sram_addr, unsigned char sramdata); ++ ++ unsigned long (*hi_read_reg8)(unsigned long sram_addr); ++ void (*hi_write_reg8)(unsigned long sram_addr, unsigned long sramdata); ++ unsigned long (*hi_read_reg32)(unsigned long sram_addr); ++ int (*hi_write_reg32)(unsigned long sram_addr, unsigned long sramdata); ++ ++ void (*hi_write_cmd)(unsigned long sram_addr, unsigned long sramdata); ++ void (*hi_write_sram)(unsigned char*buf, unsigned char* addr, SYS_TYPE len); ++ void (*hi_read_sram)(unsigned char* buf, unsigned char* addr, SYS_TYPE len); ++ void (*hi_write_word)(unsigned int addr,unsigned int data); ++ unsigned int (*hi_read_word)(unsigned int addr); ++ ++ void (*hi_rcv_frame)(unsigned char* buf, unsigned char* addr, SYS_TYPE len); ++#if defined (HAL_FPGA_VER) ++ int (*hi_enable_scat)(void); ++ void (*hi_cleanup_scat)(void); ++ struct amlw_hif_scatter_req * (*hi_get_scatreq)(void); ++ int (*hi_scat_rw)(struct scatterlist *sg_list, unsigned int sg_num, unsigned int blkcnt, ++ unsigned char func_num, unsigned int addr, unsigned char write); ++ int (*hi_send_frame)(struct amlw_hif_scatter_req *scat_req); ++#elif defined (HAL_SIM_VER) ++ void (*hi_send_frame)(unsigned char* buf, unsigned char* addr, SYS_TYPE len); ++#endif ++ ++ /*bt use*/ ++ void (*bt_hi_write_sram)(unsigned char* buf, unsigned char* addr, SYS_TYPE len); ++ void (*bt_hi_read_sram)(unsigned char* buf, unsigned char* addr, SYS_TYPE len); ++ void (*bt_hi_write_word)(unsigned int addr,unsigned int data); ++ unsigned int (*bt_hi_read_word)(unsigned int addr); ++ ++ void (*hif_get_sts)(unsigned int op_code, unsigned int ctrl_code); ++ void (*hif_pt_rx_start)(unsigned int qos); ++ void (*hif_pt_rx_stop)(void); ++ ++ int (*hif_suspend)(unsigned int suspend_enable); ++}; ++ ++void hi_clear_irq_status(unsigned int data); ++unsigned int hi_get_irq_status(void); ++unsigned char hi_set_cmd(unsigned char *pdata,unsigned int len); ++unsigned char hi_get_cmd(unsigned char *pdata,unsigned int len); ++ ++unsigned int hi_get_device_id(void); ++unsigned int hi_get_vendor_id(void); ++unsigned int hi_get_fw_version(void); ++ ++void hi_top_task( unsigned long data); ++void hi_soft_tx_irq(void); ++ ++ ++void hif_init_ops(void); ++ ++void hi_soft_rx_irq(struct hal_private *hal_priv, unsigned int rx_fw_ptr); ++void hi_soft_rx_bcn(struct hal_private *hal_priv, unsigned char vid); ++ ++void hi_cfg_firmware(void); ++void show_macframe (unsigned char *start, unsigned char len); ++void set_wifi_baudrate (unsigned int apb_clk); ++ ++void hif_pt_rx_start(unsigned int qos); ++void hif_pt_rx_stop(void); ++ ++#if defined (HAL_FPGA_VER) ++struct tx_status_list { ++ struct list_head status_list; ++ struct list_head free_list; ++ spinlock_t status_list_lock; ++}; ++ ++struct tx_status_node { ++ struct list_head list_node; ++ union ++ { ++ struct txdonestatus txstatus; ++ struct tx_nulldata_status tx_null_status; ++ }tx_status; ++}; ++int hi_tx_frame(struct hi_tx_desc **pTxDPape, unsigned int mpdu_num, unsigned int page_num); ++int hi_sdio_setup_scat_data(struct scatterlist *sg_list, struct hi_tx_desc **pTxDPape, ++ unsigned int sg_num, unsigned char func_num); ++ ++/*txok status process */ ++int tx_status_list_init(struct tx_status_list *tx_status_list, int num); ++void tx_status_node_free(struct tx_status_node *txok_status_node, ++ struct tx_status_list *tx_status_list); ++void tx_status_node_enqueue(struct tx_status_node *txok_status_node, ++ struct tx_status_list *tx_status_list); ++struct tx_status_node * tx_status_node_dequeue(struct tx_status_list *tx_status_list); ++struct tx_status_node * tx_status_node_alloc(struct tx_status_list *tx_status_list); ++void hi_irq_task(struct hal_private *hal_priv); ++void hi_rx_fifo_init(void); ++ ++#elif defined (HAL_SIM_VER) ++int hi_tx_frame( struct hi_tx_desc* pTxDPape, unsigned int blk_num, unsigned int page_num); ++int hal_calc_block_in_mpdu (int mpdulen); ++#endif ++unsigned int MAC_RD_REG(unsigned int addr); ++void MAC_WR_REG(unsigned int addr,unsigned int data); ++ ++void b2b_rx_throughput_calc(HW_RxDescripter_bit *RxPrivHdr); ++ ++#endif //_HI_SDIO_H_ diff --git a/drivers/net/wireless/w1/vmac/wifi_iwpriv_cmd.c b/drivers/net/wireless/w1/vmac/wifi_iwpriv_cmd.c new file mode 100644 -index 000000000000..ac86b467ebee +index 0000000000000000000000000000000000000000..4014bd213ad5b1fecfd4259151912b1659324dab --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_iwpriv_cmd.c -@@ -0,0 +1,2001 @@ +@@ -0,0 +1,2014 @@ +#include "wifi_mac_com.h" +#include "wifi_iwpriv_cmd.h" +#include "wifi_cmd_func.h" @@ -74946,7 +75591,7 @@ index 000000000000..ac86b467ebee + + +extern void print_driver_version(void); -+extern char **aml_cmd_char_prase(char sep, const char *str, int *size); ++extern char **aml_cmd_char_phrase(char sep, const char *str, int *size); +extern struct udp_info aml_udp_info[]; +extern struct udp_timer aml_udp_timer; +extern int udp_cnt; @@ -74966,7 +75611,7 @@ index 000000000000..ac86b467ebee + +void wifi_mac_pwrsave_set_inactime(struct wlan_net_vif *wnet_vif, unsigned int time); + -+struct wlan_net_vif *aml_iwpriv_get_vif(char *name) ++static struct wlan_net_vif *aml_iwpriv_get_vif(char *name) +{ + struct wlan_net_vif *wnet_vif = NULL; + struct drv_private *drv_priv = NULL; @@ -74979,7 +75624,7 @@ index 000000000000..ac86b467ebee + for (idx = 0; idx < 2; idx++) { + wnet_vif = drv_priv->drv_wnet_vif_table[idx]; + if (strncmp(wnet_vif->vm_ndev->name, name, sizeof(wnet_vif->vm_ndev->name)) == 0) { -+ printk("%s, %s, %s\n", __func__, wnet_vif->vm_ndev->name, name); ++ pr_debug("%s, %s, %s\n", __func__, wnet_vif->vm_ndev->name, name); + return wnet_vif; + } + } @@ -74990,7 +75635,7 @@ index 000000000000..ac86b467ebee +static int aml_ap_set_amsdu_state(struct net_device *dev, + struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ -+ printk("%s, %s\n", __func__,extra); ++ pr_debug("%s, %s\n", __func__,extra); + aml_set_mac_amsdu_switch_state(extra); + + return 0; @@ -74999,7 +75644,7 @@ index 000000000000..ac86b467ebee +static int aml_ap_set_ampdu_state(struct net_device *dev, + struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ -+ printk("%s, %s\n", __func__,extra); ++ pr_debug("%s, %s\n", __func__,extra); + aml_set_drv_ampdu_switch_state(extra); + + return 0; @@ -75008,14 +75653,14 @@ index 000000000000..ac86b467ebee + +static int aml_ap_get_amsdu_state(void) +{ -+ printk("%s\n", __func__); ++ pr_debug("%s\n", __func__); + aml_set_mac_amsdu_switch_state(NULL); + return 0; +} + +static int aml_ap_get_ampdu_state(void) +{ -+ printk("%s\n", __func__); ++ pr_debug("%s\n", __func__); + aml_set_drv_ampdu_switch_state(NULL); + return 0; +} @@ -75036,7 +75681,7 @@ index 000000000000..ac86b467ebee + int val = 0; + char addr[MAX_MAC_BUF_LEN]={0}; + -+ printk("%s(%d), %d, %d, %d, %d, %d, %d, %d\n", __func__, __LINE__, ++ pr_debug("%s(%d), %d, %d, %d, %d, %d, %d, %d\n", __func__, __LINE__, + param[0], param[1], param[2],param[3],param[4],param[5],param[6]); + + snprintf(addr, MAX_MAC_BUF_LEN, "%02d:%02d:%02d:%02d:%02d:%02d",param[0],param[1],param[2],param[3],param[4],param[5]); @@ -75054,7 +75699,7 @@ index 000000000000..ac86b467ebee + unsigned int reg_val = 0; + + usr_data = set; -+ printk("%s: Reg addr: 0x%08x\n", __func__, usr_data); ++ pr_debug("%s: Reg addr: 0x%08x\n", __func__, usr_data); + + if (((usr_data >> 24) & 0xff) == 0xff ) { +#ifdef USE_T902X_RF @@ -75068,7 +75713,7 @@ index 000000000000..ac86b467ebee + reg_val = wnet_vif->vif_ops.read_word(usr_data); + } + -+ printk("Drv info: Reg data=&0x%08x\n",reg_val); ++ pr_debug("Drv info: Reg data=&0x%08x\n",reg_val); + + return 0; +} @@ -75082,7 +75727,7 @@ index 000000000000..ac86b467ebee + usr_data = set1; + usr_data_ext = set2; + -+ printk("Cfg80211: Reg addr: val:0x%08x,val:0x%08x\n",usr_data,usr_data_ext); ++ pr_debug("Cfg80211: Reg addr: val:0x%08x,val:0x%08x\n",usr_data,usr_data_ext); + if (((usr_data >> 24) & 0xff) == 0xff) { +#ifdef USE_T902X_RF + rf_i2c_write( usr_data & 0x00ffffff,usr_data_ext );//access t902x rf reg @@ -75121,7 +75766,7 @@ index 000000000000..ac86b467ebee + if (bcn_intvl == 0) { + bcn_intvl = WIFINET_BINTVAL_DEFAULT; + } -+ printk("%s:%d, bcn intvl %d\n", __func__, __LINE__, bcn_intvl); ++ pr_debug("%s:%d, bcn intvl %d\n", __func__, __LINE__, bcn_intvl); + wnet_vif->vm_wmac->drv_priv->drv_ops.Phy_beaconinit(wnet_vif->vm_wmac->drv_priv, + wnet_vif->wnet_vif_id, bcn_intvl); + @@ -75138,7 +75783,7 @@ index 000000000000..ac86b467ebee + +static void aml_iwpriv_enable_fw_log(struct wlan_net_vif *wnet_vif) +{ -+ printk("%s: fw log enabled from iwpriv cmd\n", __func__); ++ pr_debug("%s: fw log enabled from iwpriv cmd\n", __func__); + set_reg(wnet_vif, 0x00f00004, 0x0ffbf0ff); + msleep(100); + set_reg(wnet_vif, 0x00f00008, 0x00040f00); @@ -75154,10 +75799,10 @@ index 000000000000..ac86b467ebee + if (aml_wifi_is_enable_rf_test()) { + if (1 == set) { + gB2BTestCasePacket.ldpc_enable = 1; -+ printk("Enable tx LDPC\n"); ++ pr_debug("Enable tx LDPC\n"); + } else if (0 == set){ + gB2BTestCasePacket.ldpc_enable = 0; -+ printk("Disable tx LDPC\n"); ++ pr_debug("Disable tx LDPC\n"); + } else { + ERROR_DEBUG_OUT("Invalid parameter\n"); + } @@ -75167,11 +75812,11 @@ index 000000000000..ac86b467ebee + if (1 == set) { + sta->sta_vhtcap |= WIFINET_VHTCAP_RX_LDPC; + wifimac->wm_flags |=WIFINET_F_LDPC; -+ printk("Enable LDPC, if need to change, the action must be executed before connecting to ap or creating ap\n"); ++ pr_debug("Enable LDPC, if need to change, the action must be executed before connecting to ap or creating ap\n"); + } else if (0 == set) { + sta->sta_vhtcap &= ~WIFINET_VHTCAP_RX_LDPC; + wifimac->wm_flags &=~WIFINET_F_LDPC; -+ printk("Disable LDPC, if need to change, the action must be executed before connecting to ap or creating ap\n"); ++ pr_debug("Disable LDPC, if need to change, the action must be executed before connecting to ap or creating ap\n"); + } else { + ERROR_DEBUG_OUT("Invalid parameter\n"); + } @@ -75189,31 +75834,31 @@ index 000000000000..ac86b467ebee + usr_data2 = set2; + + if (usr_data2 > 4) { -+ printk("support max spatial is 4 !\n"); ++ pr_debug("support max spatial is 4 !\n"); + wifimac->max_spatial = 4; + } else if (usr_data2 <= 0) { -+ printk("min spatial is 1 !\n"); ++ pr_debug("min spatial is 1 !\n"); + wifimac->max_spatial = 1; + } else { + wifimac->max_spatial = usr_data2; + } -+ printk("%s:%d, set spatial %d \n", __func__, __LINE__, wifimac->max_spatial); ++ pr_debug("%s:%d, set spatial %d \n", __func__, __LINE__, wifimac->max_spatial); + + if(usr_data1 < 4) { + if (((usr_data1 & 0xF) & BIT(0)) == BIT(0)) { + wifimac->wm_flags_ext2 |= WIFINET_VHTCAP_SU_BFMEE; -+ printk("%s:%d, enable su mimo\n", __func__, __LINE__); ++ pr_debug("%s:%d, enable su mimo\n", __func__, __LINE__); + } else { + wifimac->wm_flags_ext2 &= ~WIFINET_VHTCAP_SU_BFMEE; -+ printk("%s:%d, disable su mimo\n", __func__, __LINE__); ++ pr_debug("%s:%d, disable su mimo\n", __func__, __LINE__); + } + + if (((usr_data1 & 0xF) & BIT(1)) == BIT(1)) { + wifimac->wm_flags_ext2 |= WIFINET_VHTCAP_MU_BFMEE; -+ printk("%s:%d, enable mu mimo\n", __func__, __LINE__); ++ pr_debug("%s:%d, enable mu mimo\n", __func__, __LINE__); + } else { + wifimac->wm_flags_ext2 &= ~WIFINET_VHTCAP_MU_BFMEE; -+ printk("%s:%d, disable mu mimo\n", __func__, __LINE__); ++ pr_debug("%s:%d, disable mu mimo\n", __func__, __LINE__); + } + } else { + ERROR_DEBUG_OUT("initial parameter!\n"); @@ -75351,7 +75996,7 @@ index 000000000000..ac86b467ebee + struct wlan_net_vif *wnet_vif = netdev_priv(dev); + memset(&mask, 0, sizeof(struct cfg80211_bitrate_mask)); + mask.control[band].legacy = (1<vm_opmode, band); ++ pr_debug("%s %d, opmode %d, band %d\n", __func__, __LINE__, wnet_vif->vm_opmode, band); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,15,0) + vm_cfg80211_set_bitrate_mask(NULL, dev, NULL, &mask); @@ -75377,7 +76022,7 @@ index 000000000000..ac86b467ebee + band = NL80211_BAND_2GHZ; + } + -+ printk("%s %d, opmode %d, band %d\n", __func__, __LINE__, wnet_vif->vm_opmode, band); ++ pr_debug("%s %d, opmode %d, band %d\n", __func__, __LINE__, wnet_vif->vm_opmode, band); + mask.control[band].ht_mcs[0] = (1<vm_opmode, band); ++ pr_debug("%s %d, opmode %d, band %d\n", __func__, __LINE__, wnet_vif->vm_opmode, band); + mask.control[band].vht_mcs[0] = (1<vm_fixed_rate.rateinfo = 0; + wnet_vif->vm_fixed_rate.mode = WIFINET_FIXED_RATE_NONE; + wnet_vif->vm_change_rate_enable = 1; -+ printk("%s %d, enable autorate\n", __func__,__LINE__); ++ pr_debug("%s %d, enable autorate\n", __func__,__LINE__); +} + +void aml_iwpriv_set_uapsd(struct wlan_net_vif *wnet_vif, unsigned int set) +{ + if ((unsigned char)set != 0) { + WIFINET_VMAC_UAPSD_ENABLE(wnet_vif); -+ printk("%s(%d) enable ap uapsd\n ", __func__, __LINE__); ++ pr_debug("%s(%d) enable ap uapsd\n ", __func__, __LINE__); + + } else { + WIFINET_VMAC_UAPSD_DISABLE(wnet_vif); -+ printk("%s(%d) disable ap uapsd\n ", __func__, __LINE__); ++ pr_debug("%s(%d) disable ap uapsd\n ", __func__, __LINE__); + } + wnet_vif->vm_flags |= WIFINET_F_WMEUPDATE; +} @@ -75440,32 +76085,32 @@ index 000000000000..ac86b467ebee +{ + struct drv_private *drv_priv = drv_get_drv_priv(); + drv_priv->drv_config.cfg_band = set; -+ printk("%s(%d) band %d\n ", __func__, __LINE__, set); ++ pr_debug("%s(%d) band %d\n ", __func__, __LINE__, set); + return 0; +} + -+unsigned char aml_iwpriv_set_initial_gain_change_hang(unsigned int set) ++static unsigned char aml_iwpriv_set_initial_gain_change_hang(unsigned int set) +{ + g_initial_gain_change_disable = set; + + if (g_initial_gain_change_disable) { -+ printk("%s(%d) initial_gain_change invalid\n ", __func__, __LINE__); ++ pr_err("%s(%d) initial_gain_change invalid\n ", __func__, __LINE__); + + } else { -+ printk("%s(%d) initial_gain_change valid\n ", __func__, __LINE__); ++ pr_debug("%s(%d) initial_gain_change valid\n ", __func__, __LINE__); + } + return 0; +} + -+unsigned char aml_iwpriv_set_tx_power_change_hang(unsigned int set) ++static unsigned char aml_iwpriv_set_tx_power_change_hang(unsigned int set) +{ + g_tx_power_change_disable = set; + + if (g_tx_power_change_disable) { -+ printk("%s(%d) tx_power_change invalid\n ", __func__, __LINE__); ++ pr_err("%s(%d) tx_power_change invalid\n ", __func__, __LINE__); + + } else { -+ printk("%s(%d) tx_power_change valid\n ", __func__, __LINE__); ++ pr_debug("%s(%d) tx_power_change valid\n ", __func__, __LINE__); + } + return 0; +} @@ -75476,13 +76121,20 @@ index 000000000000..ac86b467ebee + return drv_priv->drv_config.cfg_band; +} + -+unsigned char aml_iwpriv_set_mac_mode(unsigned int set) ++static unsigned char aml_iwpriv_set_mac_mode(unsigned int set) +{ + struct drv_private *drv_priv = drv_get_drv_priv(); + drv_priv->drv_config.cfg_mac_mode = set; + return 0; +} + ++void aml_iwpriv_set_wfa_mode(struct wlan_net_vif *wnet_vif, unsigned char is_enable) ++{ ++ struct wifi_mac * wifimac = wnet_vif->vm_wmac; ++ wifimac->wm_wfa_enable = is_enable; ++ AML_OUTPUT("vid:%d, enable_wfa:%d\n", wnet_vif->wnet_vif_id, wifimac->wm_wfa_enable); ++} ++ +static int aml_iwpriv_send_para1(struct net_device *dev, + struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ @@ -75498,7 +76150,7 @@ index 000000000000..ac86b467ebee + int len = 0; + + -+ printk("%s, sub_cmd %d, value %d\n", __func__,param[0], param[1]); ++ pr_debug("%s, sub_cmd %d, value %d\n", __func__,param[0], param[1]); + + wifimac = wifi_mac_get_mac_handle(); + wnet_vif = aml_iwpriv_get_vif(dev->name); @@ -75515,7 +76167,7 @@ index 000000000000..ac86b467ebee + /*e.g '-80' need 3 char in string, added '\0', so need + 4 */ + len = strlen("set_roam_thr_2g ") + 4; + snprintf(buf, len, "set_roam_thr_2g %d", set); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_set_roaming_threshold_2g(wnet_vif, buf, len); + break; + @@ -75523,77 +76175,77 @@ index 000000000000..ac86b467ebee + /*e.g '-80' need 3 char in string, added '\0', so need + 4 */ + len = strlen("set_roam_thr_5g ") + 4; + snprintf(buf, len, "set_roam_thr_5g %d", set); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_set_roaming_threshold_5g(wnet_vif, buf, len); + break; + + case AML_IWP_ROAM_MODE: + len = strlen("set_roam_mode ") + 4; + snprintf(buf, len, "set_roam_mode %d", set); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_set_roaming_mode(wnet_vif, buf, len); + break; + + case AML_IWP_MARK_DFS_CHAN: + len = strlen("mark_dfs_chan ") + 4; + snprintf(buf, len, "mark_dfs_chan %d", set); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_mark_dfs_channel(wnet_vif, buf, len); + break; + + case AML_IWP_UNMARK_DFS_CHAN: + len = strlen("unmark_dfs_chan ") + 4; + snprintf(buf, len, "unmark_dfs_chan %d", set); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_unmark_dfs_channel(wnet_vif, buf, len); + break; + + case AML_IWP_WEAK_THR_NARROW: + len = strlen("set_weak_thr_nb ") + 4; + snprintf(buf, len, "set_weak_thr_nb %d", set); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_set_signal_power_weak_thresh_for_narrow_bandwidth(wnet_vif, buf, len); + break; + + case AML_IWP_WEAK_THR_WIDE: + len = strlen("set_weak_thr_wb ") + 4; + snprintf(buf, len, "set_weak_thr_wb %d", set); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_set_signal_power_weak_thresh_for_wide_bandwidth(wnet_vif, buf, len); + break; + + case AML_IWP_EAT_COUNT: + len = strlen("set_eat_count ") + 4; + snprintf(buf, len, "set_eat_count %d", set); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_set_eat_count_max(wnet_vif, buf, len); + break; + + case AML_IWP_AGGR_THRESH: + len = strlen("set_aggr_thresh ") + 4; + snprintf(buf, len, "set_aggr_thresh %d", set); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_set_aggr_thresh(wnet_vif, buf, len); + break; + + case AML_IWP_HEART_INTERVAL: + len = strlen("set_hrt_int ") + 4; + snprintf(buf, len, "set_hrt_int %d", set); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_set_hrtimer_interval(wnet_vif, buf, len); + break; + + case AML_IWP_BSS_COEX: + len = strlen("send_bss_coex"); + snprintf(buf, len, "send_bss_coex"); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_sta_send_coexist_mgmt(wnet_vif, buf, len); + break; + + case AML_IWP_WMM_AC_DELTS: + len = strlen("wmm_ac_delts ") + 4; + snprintf(buf, len, "wmm_ac_delts %d", set); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_wmm_ac_delts(wnet_vif, buf, len); + break; + @@ -75602,7 +76254,7 @@ index 000000000000..ac86b467ebee + str[1] = "on"; + len = strlen("set_short_gi ") + strlen(str[set]) + 1; + snprintf(buf, len, "set_short_gi %s", str[set]); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_set_short_gi(wnet_vif, buf, len); + break; + @@ -75611,7 +76263,7 @@ index 000000000000..ac86b467ebee + str[1] = "on"; + len = strlen("set_dynamic_bw ") + strlen(str[set]) + 1; + snprintf(buf, len, "set_dynamic_bw %s", str[set]); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_set_dynamic_bw(wnet_vif, buf, len); + break; + @@ -75620,16 +76272,16 @@ index 000000000000..ac86b467ebee + str[1] = "reset"; + len = strlen("get_txaggr_sta ") + strlen(str[set]) + 1; + snprintf(buf, len, "get_txaggr_sta %s", str[set]); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_get_drv_txaggr_status(wnet_vif, buf, len); + break; + + case AML_IWP_GET_REG: + if (set == 0x7fffffff) { -+ printk("******************************************************************************\n"); -+ printk("You are using a legacy iwpriv tool, strongly suggest using a latest iwpriv one\n"); -+ printk("You also can using the legacy tool as below:\n iwpriv wlan0 get_reg 0xff000c80 -> iwpriv wlan0 get_reg_legacy 0xff00 0x00c80\n"); -+ printk("******************************************************************************\n"); ++ pr_debug("******************************************************************************\n"); ++ pr_debug("You are using a legacy iwpriv tool, strongly suggest using a latest iwpriv one\n"); ++ pr_debug("You also can using the legacy tool as below:\n iwpriv wlan0 get_reg 0xff000c80 -> iwpriv wlan0 get_reg_legacy 0xff00 0x00c80\n"); ++ pr_debug("******************************************************************************\n"); + } + get_reg(wnet_vif, set); + break; @@ -75647,7 +76299,7 @@ index 000000000000..ac86b467ebee + wnet_vif->vm_scan_time_idle = (unsigned char)set; + wifi_mac_set_scan_time(wnet_vif); + } -+ printk("%s, vid:%d set scan_time_idle = %d\n ", __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_scan_time_idle); ++ pr_debug("%s, vid:%d set scan_time_idle = %d\n ", __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_scan_time_idle); + break; + + case AML_IWP_SET_SCAN_TIME_CONNECT: @@ -75655,16 +76307,16 @@ index 000000000000..ac86b467ebee + wnet_vif->vm_scan_time_connect = (unsigned char)set; + wifi_mac_set_scan_time(wnet_vif); + } -+ printk("%s, vid:%d set scan_time_connect = %d\n ", __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_scan_time_connect); ++ pr_debug("%s, vid:%d set scan_time_connect = %d\n ", __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_scan_time_connect); + break; + + case AML_IWP_SET_SCAN_HANG: + wnet_vif->vm_scan_hang = (unsigned char)set; -+ printk("%s, vid:%d vm_scan_hang:%d\n ", __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_scan_hang); ++ pr_debug("%s, vid:%d vm_scan_hang:%d\n ", __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_scan_hang); + break; + + case AML_IWP_EN_BTWIFI_COEX: -+ printk("%s, coexist en= %d\n ", __func__, set); ++ pr_debug("%s, coexist en= %d\n ", __func__, set); + wifimac->drv_priv->hal_priv->hal_ops.phy_set_coexist_en(set); + break; + @@ -75674,12 +76326,12 @@ index 000000000000..ac86b467ebee + + case AML_IWP_SET_COEXIST_REQ_TIMEOUT: + wifimac->drv_priv->hal_priv->hal_ops.phy_set_coexist_req_timeslice_timeout_value(set); -+ printk("%s, set req timeout value= %d\n ", __func__, set); ++ pr_debug("%s, set req timeout value= %d\n ", __func__, set); + break; + + case AML_IWP_SET_COEXIST_NOT_GRANT_WEIGHT: + wifimac->drv_priv->hal_priv->hal_ops.phy_set_coexist_not_grant_weight(set); -+ printk("%s, set coexist_not_grant_weight= %d\n ", __func__, set); ++ pr_debug("%s, set coexist_not_grant_weight= %d\n ", __func__, set); + break; + + case AML_IWP_SET_RATE_LEGACY: @@ -75704,7 +76356,7 @@ index 000000000000..ac86b467ebee + + case AML_IWP_SET_BURST: + wifimac->drv_priv->drv_config.cfg_burst_ack = set; -+ printk("iwpriv set burst %d\n", set); ++ pr_debug("iwpriv set burst %d\n", set); + break; + + case AML_IWP_SET_UAPSD: @@ -75729,19 +76381,19 @@ index 000000000000..ac86b467ebee + + case AML_IWP_SET_FETCH_PKT_METHOD: + wnet_vif->vm_mainsta->sta_fetch_pkt_method = (unsigned char)set; -+ printk("iwpriv set pkt method %d\n", set); ++ pr_debug("iwpriv set pkt method %d\n", set); + break; + + case AML_IWP_SET_FRAG_THRESHOLD: + if ((unsigned short)set > 0) { + wnet_vif->vm_fragthreshold = (unsigned short)set; + } -+ printk("iwpriv set frag thr %d\n", wnet_vif->vm_fragthreshold); ++ pr_debug("iwpriv set frag thr %d\n", wnet_vif->vm_fragthreshold); + break; + + case AML_IWP_SET_PREAMBLE_TYPE: + phy_set_preamble_type((unsigned char)set); -+ printk("iwpriv set preamble type %d\n", set); ++ pr_debug("iwpriv set preamble type %d\n", set); + break; + + case AML_IWP_SET_FIX_BAND: @@ -75763,6 +76415,9 @@ index 000000000000..ac86b467ebee + case AML_IWP_SET_MAC_MODE: + aml_iwpriv_set_mac_mode(set); + break; ++ case AML_IWP_SET_WFA_MODE: ++ aml_iwpriv_set_wfa_mode(wnet_vif, set); ++ break; + } + + return 0; @@ -75782,7 +76437,7 @@ index 000000000000..ac86b467ebee + int legacy_set = 0; + + -+ printk("%s, sub_cmd %d, value %d %d\n", __func__,param[0], param[1], param[2]); ++ pr_debug("%s, sub_cmd %d, value %d %d\n", __func__,param[0], param[1], param[2]); + + wifimac = wifi_mac_get_mac_handle(); + wnet_vif = aml_iwpriv_get_vif(dev->name); @@ -75790,10 +76445,10 @@ index 000000000000..ac86b467ebee + switch (sub_cmd) { + case AML_IWP_SET_REG: + if ((set1 == 0x7fffffff) || (set2 == 0x7fffffff)) { -+ printk("********************************************************************************************************\n"); -+ printk("You are using a legacy iwpriv tool, strongly suggest using a latest iwpriv tool\n"); -+ printk("You also can using the legacy tool as below:\n iwpriv wlan0 set_reg 0xff000c80 0xff000c80 -> iwpriv wlan0 set_reg_legacy 0xff00 0x00c80 0xff0 0x00c80\n"); -+ printk("********************************************************************************************************\n"); ++ pr_debug("********************************************************************************************************\n"); ++ pr_debug("You are using a legacy iwpriv tool, strongly suggest using a latest iwpriv tool\n"); ++ pr_debug("You also can using the legacy tool as below:\n iwpriv wlan0 set_reg 0xff000c80 0xff000c80 -> iwpriv wlan0 set_reg_legacy 0xff00 0x00c80 0xff0 0x00c80\n"); ++ pr_debug("********************************************************************************************************\n"); + } + set_reg(wnet_vif, set1, set2); + break; @@ -75830,7 +76485,7 @@ index 000000000000..ac86b467ebee + int legacy_set2 = 0; + + -+ printk("%s, sub_cmd %d, value1 %d, value2 %d, value3 %d\n", __func__,param[0], param[1], param[2], param[3]); ++ pr_debug("%s, sub_cmd %d, value1 %d, value2 %d, value3 %d\n", __func__,param[0], param[1], param[2], param[3]); + + wifimac = wifi_mac_get_mac_handle(); + wnet_vif = aml_iwpriv_get_vif(dev->name); @@ -75861,7 +76516,7 @@ index 000000000000..ac86b467ebee + unsigned int efuse_data_l = 0; + unsigned int efuse_data_h = 0; + -+ printk("%s, sub cmd %d\n", __func__, param[0]); ++ pr_debug("%s, sub cmd %d\n", __func__, param[0]); + + wifimac = wifi_mac_get_mac_handle(); + wnet_vif = aml_iwpriv_get_vif(dev->name); @@ -75882,7 +76537,7 @@ index 000000000000..ac86b467ebee + + case AML_IWP_UDP_INFO: + for (i = 0; i < udp_cnt; i++) { -+ printk("%s streamid=%d tx is %d, rx is %d\n", __func__, aml_udp_info[i].streamid, aml_udp_info[i].tx, aml_udp_info[i].rx); ++ pr_debug("%s streamid=%d tx is %d, rx is %d\n", __func__, aml_udp_info[i].streamid, aml_udp_info[i].tx, aml_udp_info[i].rx); + } + aml_udp_timer.udp_timer_stop = 1; + aml_udp_timer.run_flag = 0; @@ -75891,17 +76546,17 @@ index 000000000000..ac86b467ebee + break; + + case AML_IWP_COUNTRY: -+ printk("country code: %s\n", wifimac->wm_country.iso); ++ pr_debug("country code: %s\n", wifimac->wm_country.iso); + break; + + case AML_IWP_GET_DEV_SN: -+ printk("aml module SN is:%04x \n", efuse_manual_read(0xf)); ++ pr_debug("aml module SN is:%04x \n", efuse_manual_read(0xf)); + break; + + case AML_IWP_GET_WIFI_MAC: + efuse_data_l = efuse_manual_read(0x1); + efuse_data_h = efuse_manual_read(0x2); -+ printk("aml WIFI MAC addr is: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ pr_debug("aml WIFI MAC addr is: %02x:%02x:%02x:%02x:%02x:%02x\n", + (efuse_data_h & 0xff00) >> 8,efuse_data_h & 0x00ff, (efuse_data_l & 0xff000000) >> 24, + (efuse_data_l & 0x00ff0000) >> 16,(efuse_data_l & 0xff00) >> 8,efuse_data_l & 0xff); + break; @@ -75909,7 +76564,7 @@ index 000000000000..ac86b467ebee + case AML_IWP_GET_BT_MAC: + efuse_data_l = efuse_manual_read(0x2); + efuse_data_h = efuse_manual_read(0x3); -+ printk("aml BT MAC addr is: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ pr_debug("aml BT MAC addr is: %02x:%02x:%02x:%02x:%02x:%02x\n", + (efuse_data_h & 0xff000000) >> 24, (efuse_data_h & 0x00ff0000) >> 16, + (efuse_data_h & 0xff00) >> 8,efuse_data_h & 0xff, + (efuse_data_l & 0xff000000) >> 24,(efuse_data_l & 0x00ff0000) >> 16); @@ -75919,14 +76574,14 @@ index 000000000000..ac86b467ebee + WIFI_CHANNEL_LOCK(wifimac); + for (i = 0; i < wifimac->wm_nchans; i++) { + c = &wifimac->wm_channels[i]; -+ printk("channel:%d\t frequency:%d \t bandwidth:%dMHz \n", c->chan_pri_num, c->chan_cfreq1, ((1 << c->chan_bw) * 20)); ++ pr_debug("channel:%d\t frequency:%d \t bandwidth:%dMHz \n", c->chan_pri_num, c->chan_cfreq1, ((1 << c->chan_bw) * 20)); + } + WIFI_CHANNEL_UNLOCK(wifimac); + break; + + case AML_IWP_CHIP_ID: + snprintf(buf, 21, "get_chip_id 0x%x 0x%x",0x8, 0x9); -+ printk("%s: buf %s\n", __func__, buf); ++ pr_debug("%s: buf %s\n", __func__, buf); + aml_get_chip_id(NULL, buf, 0); + break; + @@ -75960,7 +76615,7 @@ index 000000000000..ac86b467ebee + + case AML_IWP_PRINT_VERSION: + print_driver_version(); -+ printk("driver version: %s\n", DRIVERVERSION); ++ pr_debug("driver version: %s\n", DRIVERVERSION); + AML_OUTPUT("=============bus type:%s fw_chip:%s=============\n",aml_wifi_get_bus_type(),aml_wifi_get_fw_type()); + break; + @@ -76108,9 +76763,9 @@ index 000000000000..ac86b467ebee + return -EFAULT; + } + buf[40] = '\0'; -+ printk("%s: %s\n", __func__, buf); ++ pr_debug("%s: %s\n", __func__, buf); + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + wifi_mac_set_udp_info(arg); + kfree(arg); + @@ -76124,7 +76779,7 @@ index 000000000000..ac86b467ebee + + int i = 0; + for (i = 0; i < udp_cnt; i++) { -+ printk("%s streamid=%d tx is %d, rx is %d\n", __func__, aml_udp_info[i].streamid, aml_udp_info[i].tx, aml_udp_info[i].rx); ++ pr_debug("%s streamid=%d tx is %d, rx is %d\n", __func__, aml_udp_info[i].streamid, aml_udp_info[i].tx, aml_udp_info[i].rx); + } + aml_udp_timer.udp_timer_stop = 1; + aml_udp_timer.run_flag = 0; @@ -76137,21 +76792,21 @@ index 000000000000..ac86b467ebee +static int aml_set_country_code(struct net_device *dev, + struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ -+ printk("%s, %s\n", __func__,extra); ++ pr_debug("%s, %s\n", __func__,extra); + wifi_mac_set_country_code(extra); + + return 0; + +} + -+void aml_iwpriv_set_dev_sn(char* arg_iw) ++static void aml_iwpriv_set_dev_sn(char* arg_iw) +{ + char **mac_cmd; + int i,cmd_arg; + char sep = ':'; + unsigned int efuse_data = 0; + -+ mac_cmd = aml_cmd_char_prase(sep, arg_iw, &cmd_arg); ++ mac_cmd = aml_cmd_char_phrase(sep, arg_iw, &cmd_arg); + if (mac_cmd) { + efuse_data = (simple_strtoul(mac_cmd[0],NULL,16) << 8) | (simple_strtoul(mac_cmd[1],NULL,16)); + for (i = 0; i < 16; i++) { @@ -76159,13 +76814,13 @@ index 000000000000..ac86b467ebee + efuse_manual_write(i, 0xf); + } + } -+ printk("iwpriv write module SN is: %02x %02x\n", ((efuse_data & 0xff00) >> 8), (efuse_data & 0x00ff)); ++ pr_debug("iwpriv write module SN is: %02x %02x\n", ((efuse_data & 0xff00) >> 8), (efuse_data & 0x00ff)); + } + kfree(mac_cmd); + +} + -+void aml_iwpriv_set_mac_addr(char* arg_iw) ++static void aml_iwpriv_set_mac_addr(char* arg_iw) +{ + char **mac_cmd; + int i,cmd_arg; @@ -76173,7 +76828,7 @@ index 000000000000..ac86b467ebee + unsigned int efuse_data_l = 0; + unsigned int efuse_data_h = 0; + -+ mac_cmd = aml_cmd_char_prase(sep, arg_iw, &cmd_arg); ++ mac_cmd = aml_cmd_char_phrase(sep, arg_iw, &cmd_arg); + if (mac_cmd) { + efuse_data_l = (simple_strtoul(mac_cmd[2],NULL,16) << 24) | (simple_strtoul(mac_cmd[3],NULL,16) << 16) + | (simple_strtoul(mac_cmd[4],NULL,16) << 8) | simple_strtoul(mac_cmd[5],NULL,16); @@ -76188,14 +76843,14 @@ index 000000000000..ac86b467ebee + efuse_manual_write(i, 2); + } + } -+ printk("iwpriv write WIFI MAC addr is: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ pr_debug("iwpriv write WIFI MAC addr is: %02x:%02x:%02x:%02x:%02x:%02x\n", + (efuse_data_h & 0xff00) >> 8,efuse_data_h & 0x00ff, (efuse_data_l & 0xff000000) >> 24, + (efuse_data_l & 0x00ff0000) >> 16,(efuse_data_l & 0xff00) >> 8,efuse_data_l & 0xff); + } + kfree(mac_cmd); +} + -+void aml_iwpriv_set_bt_dev_id(char* arg_iw) ++static void aml_iwpriv_set_bt_dev_id(char* arg_iw) +{ + char **mac_cmd; + int i,cmd_arg; @@ -76203,7 +76858,7 @@ index 000000000000..ac86b467ebee + unsigned int efuse_data_l = 0; + unsigned int efuse_data_h = 0; + -+ mac_cmd = aml_cmd_char_prase(sep, arg_iw, &cmd_arg); ++ mac_cmd = aml_cmd_char_phrase(sep, arg_iw, &cmd_arg); + if (mac_cmd) { + efuse_data_h = (simple_strtoul(mac_cmd[0],NULL,16) << 24) | (simple_strtoul(mac_cmd[1],NULL,16) << 16) + | (simple_strtoul(mac_cmd[2],NULL,16) << 8) | simple_strtoul(mac_cmd[3],NULL,16); @@ -76218,7 +76873,7 @@ index 000000000000..ac86b467ebee + efuse_manual_write(i, 2); + } + } -+ printk("iwpriv write BT MAC addr is: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ pr_debug("iwpriv write BT MAC addr is: %02x:%02x:%02x:%02x:%02x:%02x\n", + (efuse_data_h & 0xff000000) >> 24, (efuse_data_h & 0x00ff0000) >> 16, + (efuse_data_h & 0xff00) >> 8,efuse_data_h & 0xff, + (efuse_data_l & 0xff000000) >> 24,(efuse_data_l & 0x00ff0000) >> 16); @@ -76229,7 +76884,7 @@ index 000000000000..ac86b467ebee +static int aml_set_dev_sn(struct net_device *dev, + struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ -+ printk("%s, %s\n", __func__,extra); ++ pr_debug("%s, %s\n", __func__,extra); + aml_iwpriv_set_dev_sn(extra); + + return 0; @@ -76243,7 +76898,7 @@ index 000000000000..ac86b467ebee + return -EFAULT; + } + buf[18] = '\0'; -+ printk("%s: %s\n", __func__, buf); ++ pr_debug("%s: %s\n", __func__, buf); + aml_iwpriv_set_mac_addr(buf); + + return 0; @@ -76258,13 +76913,13 @@ index 000000000000..ac86b467ebee + return -EFAULT; + } + buf[18] = '\0'; -+ printk("%s: %s\n", __func__, buf); ++ pr_debug("%s: %s\n", __func__, buf); + aml_iwpriv_set_bt_dev_id(buf); + + return 0; +} + -+int aml_iwpriv_set_debug_switch(char *switch_str) ++static int aml_iwpriv_set_debug_switch(char *switch_str) +{ + int debug_switch = 0; + if(strstr(switch_str,"_off")!=NULL) @@ -76328,7 +76983,7 @@ index 000000000000..ac86b467ebee +static int aml_iwpriv_set_debug(struct net_device *dev, + struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ -+ printk("%s, %s\n", __func__,extra); ++ pr_debug("%s, %s\n", __func__,extra); + aml_set_debug_modules(extra); + return 0; + @@ -76338,7 +76993,7 @@ index 000000000000..ac86b467ebee + struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ + struct wifi_mac *wifimac = wifi_mac_get_mac_handle(); -+ printk("country code: %s\n", wifimac->wm_country.iso); ++ pr_debug("country code: %s\n", wifimac->wm_country.iso); + + return 0; +} @@ -76352,7 +77007,7 @@ index 000000000000..ac86b467ebee + WIFI_CHANNEL_LOCK(wifimac); + for (i = 0; i < wifimac->wm_nchans; i++) { + c = &wifimac->wm_channels[i]; -+ printk("channel:%d\t frequency:%d \t bandwidth:%dMHz \n", c->chan_pri_num, c->chan_cfreq1, ((1 << c->chan_bw) * 20)); ++ pr_debug("channel:%d\t frequency:%d \t bandwidth:%dMHz \n", c->chan_pri_num, c->chan_cfreq1, ((1 << c->chan_bw) * 20)); + } + WIFI_CHANNEL_UNLOCK(wifimac); + @@ -76371,23 +77026,23 @@ index 000000000000..ac86b467ebee + return -EFAULT; + } + buf[40] = '\0'; -+ printk("%s: %s\n", __func__, buf); ++ pr_debug("%s: %s\n", __func__, buf); + -+ arg = aml_cmd_char_prase(sep, buf, &cmd_arg); ++ arg = aml_cmd_char_phrase(sep, buf, &cmd_arg); + wifi_mac_ap_set_arp_rx(arg); + kfree(arg); + + return 0; +} + -+int iw_standard_get_stats(struct net_device *dev, struct iw_request_info *info, ++static int iw_standard_get_stats(struct net_device *dev, struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct wlan_net_vif *wnet_vif = NULL; + struct iw_statistics stats = {0}; + unsigned int arr[8] = {0}; + -+ printk("%s\n", __func__); ++ pr_debug("%s\n", __func__); + + wnet_vif = aml_iwpriv_get_vif(dev->name); + if ((wnet_vif->vm_opmode != WIFINET_M_STA) && (wnet_vif->vm_state != WIFINET_S_CONNECTED)) { @@ -76407,7 +77062,7 @@ index 000000000000..ac86b467ebee + return 0; +} + -+void sap_change_channel(struct wlan_net_vif *wnet_vif, unsigned int channel) ++static void sap_change_channel(struct wlan_net_vif *wnet_vif, unsigned int channel) +{ + struct wifi_mac *wifimac = wnet_vif->vm_wmac; + struct wifi_channel *c = NULL; @@ -76435,10 +77090,10 @@ index 000000000000..ac86b467ebee + WIFI_CHANNEL_UNLOCK(wifimac); + } + -+ wifi_mac_set_wnet_vif_channel(wnet_vif, channel, wnet_vif->vm_bandwidth, center_chan); ++ wifi_mac_set_wnet_vif_channel(wnet_vif, channel, wnet_vif->vm_bandwidth, center_chan, CHANNEL_CONNECT_FLAG | CHANNEL_RESTORE_FLAG); +} + -+int iw_standard_sap_set_freq(struct net_device *dev, struct iw_request_info *info, ++static int iw_standard_sap_set_freq(struct net_device *dev, struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct wlan_net_vif *wnet_vif = NULL; @@ -76446,7 +77101,7 @@ index 000000000000..ac86b467ebee + struct wifi_channel *c = NULL; + unsigned int set_chl = 0; + -+ printk("%s, freq.m:%d, freq.e:%d\n", __func__, wrqu->freq.m, wrqu->freq.e); ++ pr_debug("%s, freq.m:%d, freq.e:%d\n", __func__, wrqu->freq.m, wrqu->freq.e); + + wifimac = wifi_mac_get_mac_handle(); + @@ -76477,7 +77132,7 @@ index 000000000000..ac86b467ebee + set_chl = c->chan_pri_num; + wnet_vif = aml_iwpriv_get_vif(dev->name); + -+ printk("%s, opmode:%d, nrunning:%d\n", __func__, wnet_vif->vm_opmode, wifimac->wm_nrunning); ++ pr_debug("%s, opmode:%d, nrunning:%d\n", __func__, wnet_vif->vm_opmode, wifimac->wm_nrunning); + if ((wnet_vif->vm_opmode == WIFINET_M_HOSTAP) && (wifimac->wm_nrunning == 1)) { + sap_change_channel(wnet_vif, set_chl); + } @@ -76493,7 +77148,7 @@ index 000000000000..ac86b467ebee + return; + } + -+ printk(" %s %d, time %d\n",__func__,__LINE__, time); ++ pr_debug(" %s %d, time %d\n",__func__,__LINE__, time); + + if(time == 0) { + wifi_mac_pwrsave_set_mode(wnet_vif, WIFINET_PWRSAVE_NONE); @@ -76503,7 +77158,7 @@ index 000000000000..ac86b467ebee + wnet_vif->vm_pwrsave.ips_inactivitytime = time; + + if (wnet_vif->vm_state == WIFINET_S_CONNECTED && wifimac->wm_syncbeacon == 0) { -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + wifi_mac_beacon_sync(wifimac->drv_priv->wmac, wnet_vif->wnet_vif_id); + } + @@ -76516,14 +77171,14 @@ index 000000000000..ac86b467ebee +} + + -+int iw_standard_set_pwr(struct net_device *dev, struct iw_request_info *info, ++static int iw_standard_set_pwr(struct net_device *dev, struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct wlan_net_vif *wnet_vif = NULL; + unsigned int time = 0; + wnet_vif = aml_iwpriv_get_vif(dev->name); + -+ printk("%s, disable:%d\n", __func__, wrqu->power.disabled); ++ pr_debug("%s, disable:%d\n", __func__, wrqu->power.disabled); + if (wrqu->power.disabled) { + wifi_mac_pwrsave_set_mode(wnet_vif, WIFINET_PWRSAVE_NONE); + if (wnet_vif->vm_wdev) { @@ -76533,14 +77188,14 @@ index 000000000000..ac86b467ebee + } else { + if (wrqu->power.flags & IW_POWER_PERIOD) { + time = wrqu->power.value / 1000; -+ printk("%s, pwr perio value: %d\n", __func__, wrqu->power.value / 1000); ++ pr_debug("%s, pwr perio value: %d\n", __func__, wrqu->power.value / 1000); + } + + switch (wrqu->power.flags & IW_POWER_MODE) { + case IW_POWER_UNICAST_R: + case IW_POWER_MULTICAST_R: + case IW_POWER_ALL_R: -+ printk("%s, pwr mode value: %d\n", __func__, wrqu->power.value / 1000); ++ pr_debug("%s, pwr mode value: %d\n", __func__, wrqu->power.value / 1000); + break; + + case IW_POWER_ON: @@ -76781,6 +77436,9 @@ index 000000000000..ac86b467ebee + AML_IWP_SET_MAC_MODE, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "set_mac_mode"}, + ++{ ++ AML_IWP_SET_WFA_MODE, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "set_wfa"}, + +/*iwpriv get command*/ +{ @@ -76938,10 +77596,10 @@ index 000000000000..ac86b467ebee +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_iwpriv_cmd.h b/drivers/net/wireless/w1/vmac/wifi_iwpriv_cmd.h new file mode 100644 -index 000000000000..d914be608da6 +index 0000000000000000000000000000000000000000..fa426813e2956a98d7249980c1bec6f63a49def1 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_iwpriv_cmd.h -@@ -0,0 +1,88 @@ +@@ -0,0 +1,102 @@ +#ifndef __WIFI_IWPRIV_CMD_H +#define __WIFI_IWPRIV_CMD_H +#include @@ -77024,18 +77682,32 @@ index 000000000000..d914be608da6 + AML_IWP_GET_BT_MAC = 72, + AML_IWP_SET_TXPW_PLAN = 73, + AML_IWP_SET_MAC_MODE = 74, ++ AML_IWP_SET_WOW_TCPPORT = 75, ++ AML_IWP_SET_WFA_MODE = 76, +}; + +extern unsigned char aml_iwpriv_get_band(void); +int aml_set_debug_modules(char *debug_str); + ++unsigned int get_latest_tx_status(struct wifi_mac *wifimac); ++int aml_beacon_intvl_set(struct wlan_net_vif *wnet_vif, unsigned int set); ++int aml_set_ldpc(struct wlan_net_vif *wnet_vif, unsigned int set); ++int aml_iwpriv_set_lagecy_bitrate_mask(struct net_device *dev, unsigned int set); ++int aml_iwpriv_set_ht_bitrate_mask(struct net_device *dev, unsigned int set); ++void aml_iwpriv_set_rate_auto(struct wlan_net_vif *wnet_vif); ++void aml_iwpriv_set_uapsd(struct wlan_net_vif *wnet_vif, unsigned int set); ++int aml_iwpriv_set_vht_bitrate_mask(struct net_device *dev, unsigned int set); ++unsigned char aml_iwpriv_set_band(unsigned int set); ++unsigned int get_reg(struct wlan_net_vif *wnet_vif, unsigned int set); ++unsigned int set_reg(struct wlan_net_vif *wnet_vif, unsigned int set1, unsigned int set2); ++ +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_mac.h b/drivers/net/wireless/w1/vmac/wifi_mac.h new file mode 100644 -index 000000000000..575649add528 +index 0000000000000000000000000000000000000000..68f9a2d63dd2e1de87696b31219edf88709176bc --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac.h -@@ -0,0 +1,1660 @@ +@@ -0,0 +1,1689 @@ +/* + **************************************************************************************** + * @@ -77052,7 +77724,6 @@ index 000000000000..575649add528 +#ifndef _NET80211_IEEE80211_H_ +#define _NET80211_IEEE80211_H_ + -+ +enum wifi_mac_phytype +{ + WIFINET_T_DS=0, @@ -77061,14 +77732,14 @@ index 000000000000..575649add528 + WIFINET_T_VHT, + WIFINET_T_MAX +}; -+#define WIFINET_T_CCK WIFINET_T_DS ++#define WIFINET_T_CCK WIFINET_T_DS +/* XXX not really a mode; there are really multiple PHY's */ + +/* shorthands to compact tables for readability */ -+#define WOFDM WIFINET_T_OFDM -+#define CCK WIFINET_T_CCK -+#define HT WIFINET_T_HT -+#define VHT_PHY WIFINET_T_VHT ++#define WOFDM WIFINET_T_OFDM ++#define CCK WIFINET_T_CCK ++#define HT WIFINET_T_HT ++#define VHT_PHY WIFINET_T_VHT + +enum wifi_mac_macmode +{ @@ -77135,8 +77806,12 @@ index 000000000000..575649add528 +enum sta_connect_status +{ + CONNECT_IDLE, ++ CONNECT_CONNECTING, ++ CONNECT_CONNECTED, + CONNECT_FOUR_WAY_HANDSHAKE_COMPLETED, + CONNECT_DHCP_GET_ACK, ++ CONNECT_DISCONNECTING, ++ CONNECT_DISCONNECTED, +}; + +enum @@ -77218,13 +77893,13 @@ index 000000000000..575649add528 + +struct wifi_channel +{ -+ unsigned short chan_cfreq1; /* center frequency1 for 20/40/80/160, in Mhz */ ++ unsigned short chan_cfreq1; /* center frequency1 for 20/40/80/160, in Mhz */ + //unsigned short chan_cfreq2; /* center frequency2 for 80P80, in Mhz */ + unsigned short chan_flags; -+ unsigned short chan_pri_num; /* primary channel number */ -+ int8_t chan_maxpower; /* maximum tx power in dBm */ -+ int8_t chan_minpower; /* minimum tx power in dBm */ -+ enum wifi_mac_bwc_width chan_bw; /* bandwidth */ ++ unsigned short chan_pri_num; /* primary channel number */ ++ int8_t chan_maxpower; /* maximum tx power in dBm */ ++ int8_t chan_minpower; /* minimum tx power in dBm */ ++ enum wifi_mac_bwc_width chan_bw; /* bandwidth */ + unsigned char global_operating_class; +}; + @@ -77269,44 +77944,48 @@ index 000000000000..575649add528 + struct country_na_freq_info na_freq_info[10]; +}; + -+#define MAX_P2PIE_NUM 4 ++#define MAX_P2PIE_NUM 4 + -+#define WIFINET_CHAN_MAX 256 -+#define WIFINET_CHAN_MAX_NUM 165 -+#define WIFINET_CHAN_BYTES 32 -+#define WIFINET_CHAN_INVALUE 0 -+#define WIFINET_CHAN_ERR NULL -+#define WIFINET_MAX_SCAN_CHAN 64 ++#define WIFINET_CHAN_MAX 256 ++#define WIFINET_CHAN_MAX_NUM 165 ++#define WIFINET_CHAN_BYTES 32 ++#define WIFINET_CHAN_INVALUE 0 ++#define WIFINET_CHAN_ERR NULL ++#define WIFINET_MAX_SCAN_CHAN 64 + -+#define WIFINET_CHAN_2GHZ 0x4000 /* 2.4 GHz channel. */ -+#define WIFINET_CHAN_5GHZ 0x8000 /* 5 GHz channel */ -+#define WIFINET_CHAN_DFS 0x2000 /* DFS */ -+#define WIFINET_CHAN_AWARE 0x1000 /* chan aware */ ++#define WIFINET_CHAN_2GHZ 0x4000 /* 2.4 GHz channel. */ ++#define WIFINET_CHAN_5GHZ 0x8000 /* 5 GHz channel */ ++#define WIFINET_CHAN_DFS 0x2000 /* DFS */ ++#define WIFINET_CHAN_AWARE 0x1000 /* chan aware */ + -+#define WIFINET_CHAN_MODE_MASK 0xff ++#define WIFINET_CHAN_MODE_MASK 0xff ++ ++#define WIFINET_IS_CHAN_ERR(_c) ((_c) == WIFINET_CHAN_ERR) + +#define WIFINET_IS_CHAN_2GHZ(_c) \ -+ (((_c)->chan_flags & WIFINET_CHAN_2GHZ) != 0) ++ ((!WIFINET_IS_CHAN_ERR(_c)) && (((_c)->chan_flags & WIFINET_CHAN_2GHZ) != 0)) ++ +#define WIFINET_IS_CHAN_5GHZ(_c) \ -+ (((_c)->chan_flags & WIFINET_CHAN_5GHZ) != 0) ++ ((!WIFINET_IS_CHAN_ERR(_c)) && (((_c)->chan_flags & WIFINET_CHAN_5GHZ) != 0)) + +#define WIFINET_IS_CHAN_11N_HT40(_c) \ -+ (((_c)->chan_bw == WIFINET_BWC_WIDTH40)) -+ -+#define WIFINET_RATE_SIZE 8 -+#define WIFINET_RATE_MAXSIZE 57 -+#define WIFINET_HT_RATE_SIZE 77 -+#define WIFINET_RATE_BASIC 0x80 -+#define WIFINET_RATE_VAL 0x7f -+#define WIFINET_GET_RATE_VAL(_rate) ((_rate)&WIFINET_RATE_VAL) -+#define WIFINET_RATE_MCS 0x80 -+#define WIFINET_RATE_VHT_MCS 0xC0 -+#define WIFINET_AMPDU_LIMIT_MAX (32768)// (16 * 1024 - 1) ++ ((!WIFINET_IS_CHAN_ERR(_c)) && (((_c)->chan_bw == WIFINET_BWC_WIDTH40))) ++ ++#define WIFINET_RSNXE_SIZE 3 ++#define WIFINET_RATE_SIZE 8 ++#define WIFINET_RATE_MAXSIZE 57 ++#define WIFINET_HT_RATE_SIZE 77 ++#define WIFINET_RATE_BASIC 0x80 ++#define WIFINET_RATE_VAL 0x7f ++#define WIFINET_GET_RATE_VAL(_rate) ((_rate)&WIFINET_RATE_VAL) ++#define WIFINET_RATE_MCS 0x80 ++#define WIFINET_RATE_VHT_MCS 0xC0 ++#define WIFINET_AMPDU_LIMIT_MAX (32768) /* (16 * 1024 - 1) */ + +struct wifi_mac_rateset +{ + unsigned char dot11_rate_num; -+ unsigned char dot11_rate[WIFINET_HT_RATE_SIZE]; ++ unsigned char dot11_rate[WIFINET_HT_RATE_SIZE]; +}; + +enum wifi_mac_state @@ -77349,11 +78028,11 @@ index 000000000000..575649add528 + WIFINET_PUB_MAX, +}; + -+ -+#define PHASE_CONNECTING 1 -+#define PHASE_DISCONNECTING 2 -+#define PHASE_TX_BUFF_QUEUE 4 -+#define PHASE_DISCONNECT_DELAY 8 ++#define PHASE_CONNECTING 1 ++#define PHASE_DISCONNECTING 2 ++#define PHASE_TX_BUFF_QUEUE 4 ++#define PHASE_DISCONNECT_DELAY 8 ++#define PHASE_WAIT_DISCONNECT_RESULT 16 + +enum wifi_mac_recovery_state +{ @@ -77364,10 +78043,10 @@ index 000000000000..575649add528 + WIFINET_RECOVERY_END, +}; + -+#define WIFINET_F_DOSORT 0x00000001 -+#define WIFINET_F_DOFRATE 0x00000002 -+#define WIFINET_F_DOXSECT 0x00000004 -+#define WIFINET_F_DOBRS 0x00000008 ++#define WIFINET_F_DOSORT 0x00000001 ++#define WIFINET_F_DOFRATE 0x00000002 ++#define WIFINET_F_DOXSECT 0x00000004 ++#define WIFINET_F_DOBRS 0x00000008 + +struct wmeParams +{ @@ -77379,9 +78058,8 @@ index 000000000000..575649add528 + unsigned char wmep_noackPolicy; +}; + -+#define WME_NUM_AC 4 -+#define VENDOR_IE_MAX 3 -+ ++#define WME_NUM_AC 4 ++#define VENDOR_IE_MAX 3 + +struct chanAccParams +{ @@ -77402,13 +78080,14 @@ index 000000000000..575649add528 + struct chanAccParams wme_wmeBssChanParams; + struct chanAccParams wme_chanParams; /*this param is set to self chip*/ + struct chanAccParams wme_bssChanParams; /*this param is set beacon use to let sta set to it's chip*/ -+ unsigned char wme_nonAggressiveMode; ++ unsigned char wme_nonAggressiveMode; + + //int (*wme_update)(struct WIFINET_MAC *,struct WIFINET_VMAC *); +}; + +struct wifi_mac_beacon_offsets +{ ++ unsigned char *bo_ssid; + unsigned short *bo_caps; + unsigned char *bo_rates; + unsigned char *bo_channel; @@ -77429,9 +78108,11 @@ index 000000000000..575649add528 + unsigned char *bo_vhtcap; + unsigned char *bo_obss_scan; + unsigned char *bo_extcap; ++ unsigned char *bo_ch_sw_wrp; + unsigned char *bo_vendor_ie[VENDOR_IE_MAX]; + unsigned short bo_chanswitch_trailerlen; + unsigned short bo_extchanswitch_trailerlen; ++ unsigned short bo_chswwrp_trailerlen; + unsigned char bo_initial; + /* beacon sequence number */ + unsigned short bo_bcn_seq; @@ -77691,9 +78372,24 @@ index 000000000000..575649add528 + WIFINET_STATUS_REFUSED = 37, + WIFINET_STATUS_INVALID_PARAM = 38, + WIFINET_STATUS_INVALID_PMKID = 53, ++ WIFINET_STATUS_ANTI_TOKEN_REQUESTED = 76, ++ WIFINET_STATUS_SAE_H2E = 126, //0x7e + +}; + ++ ++enum wifi_mac_sae_message_type { ++ WIFINET_SAE_COMMIT = 0x1, ++ WIFINET_SAE_CONFIRM = 0x2, ++}; ++ ++#define WIFINET_SAE_H2E_ONLY 0xfb ++enum wifi_mac_h2e_status { ++ WIFINET_H2E_NONE, ++ WIFINET_H2E_PEER_SUPPOR, ++ WIFINET_H2E_VALID, ++}; ++ +#define WIFINET_COUNTRY_MAX_TRIPLETS (83) +struct wifi_mac_ie_country +{ @@ -78145,6 +78841,8 @@ index 000000000000..575649add528 +}; + +#define WIFINET_CHANSWITCHANN_BYTES 5 ++#define WIFINET_WIDEBANDCHANSW_BYTES 5 ++#define WIFINET_EXTCHANSWITCHANN_BYTES 6 + +struct wifi_mac_tim_ie +{ @@ -78455,7 +79153,10 @@ index 000000000000..575649add528 +/* + * 802.11ac Wide Bandwidth Channel Switch Element + */ -+ ++enum wifi_mac_new_channel_width { ++ NEW_CHANNEL_BANDWIDTH40 = 0, ++ NEW_CHANNEL_BANDWIDTH80 = 1, ++}; + +struct wifi_mac_ie_vht_wide_bw_switch { + unsigned char elem_id; @@ -78698,7 +79399,7 @@ index 000000000000..575649add528 +#endif /* _NET80211_IEEE80211_H_ */ diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_acl.c b/drivers/net/wireless/w1/vmac/wifi_mac_acl.c new file mode 100644 -index 000000000000..4dfd52fdf65a +index 0000000000000000000000000000000000000000..4dfd52fdf65ac3e98dbd45db363f911dc20d3c5b --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_acl.c @@ -0,0 +1,253 @@ @@ -78957,7 +79658,7 @@ index 000000000000..4dfd52fdf65a + diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_acl.h b/drivers/net/wireless/w1/vmac/wifi_mac_acl.h new file mode 100644 -index 000000000000..c05ea664c7ca +index 0000000000000000000000000000000000000000..c05ea664c7ca6adfc0ea447d807df67d39b1c149 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_acl.h @@ -0,0 +1,10 @@ @@ -78973,7 +79674,7 @@ index 000000000000..c05ea664c7ca +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_action.c b/drivers/net/wireless/w1/vmac/wifi_mac_action.c new file mode 100644 -index 000000000000..49276a7b0864 +index 0000000000000000000000000000000000000000..b896d536be22e52d83a102d27953373b5e8cc535 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_action.c @@ -0,0 +1,164 @@ @@ -78998,7 +79699,7 @@ index 000000000000..49276a7b0864 + selected_wnet_vif = drv_priv->drv_wnet_vif_table[NET80211_MAIN_VMAC]; + } + } else { -+ printk("%s, no sta connected\n", __func__); ++ pr_warn("%s, no sta connected\n", __func__); + return -1; + } + @@ -79015,17 +79716,17 @@ index 000000000000..49276a7b0864 + + for (i = 0 ; i < ETH_ALEN ; i++) { + if (aml_char_is_hex_digit(buf[i * 3]) == false || aml_char_is_hex_digit(buf[i * 3 + 1]) == false) { -+ printk("%s invalid 8-bit hex format for address offset:%u\n", __func__, i); ++ pr_err("%s invalid 8-bit hex format for address offset:%u\n", __func__, i); + } + + if (i < ETH_ALEN - 1 && buf[i * 3 + 2] != ':') { -+ printk("%s invalid separator after address offset:%u\n", __func__, i); ++ pr_err("%s invalid separator after address offset:%u\n", __func__, i); + } + + temp[0] = buf[i * 3]; + temp[1] = buf[i * 3 + 1]; + if (sscanf(temp, "%hhx", &selected_wnet_vif->vm_mainsta->sta_macaddr[i]) != 1) { -+ printk("%s sscanf fail for address offset:0x%03x\n", __func__, i); ++ pr_err("%s sscanf fail for address offset:0x%03x\n", __func__, i); + } + } + } @@ -79052,7 +79753,7 @@ index 000000000000..49276a7b0864 + selected_wnet_vif = drv_priv->drv_wnet_vif_table[NET80211_MAIN_VMAC]; + } + } else { -+ printk("%s, no sta connected\n", __func__); ++ pr_warn("%s, no sta connected\n", __func__); + return -1; + } + @@ -79082,7 +79783,7 @@ index 000000000000..49276a7b0864 + selected_wnet_vif = drv_priv->drv_wnet_vif_table[NET80211_MAIN_VMAC]; + } + } else { -+ printk("%s, no sta connected\n", __func__); ++ pr_warn("%s, no sta connected\n", __func__); + return -1; + } + @@ -79125,7 +79826,7 @@ index 000000000000..49276a7b0864 + selected_wnet_vif = drv_priv->drv_wnet_vif_table[NET80211_MAIN_VMAC]; + } + } else { -+ printk("%s, no sta connected\n", __func__); ++ pr_warn("%s, no sta connected\n", __func__); + return -1; + } + sscanf(buf, "%d", &tid); @@ -79143,10 +79844,10 @@ index 000000000000..49276a7b0864 + diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_action.h b/drivers/net/wireless/w1/vmac/wifi_mac_action.h new file mode 100644 -index 000000000000..7e4e9d44cb42 +index 0000000000000000000000000000000000000000..0e9bbcf4ab9ce2e5099ee1cf64c93f0e2afe499e --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_action.h -@@ -0,0 +1,320 @@ +@@ -0,0 +1,335 @@ +/* + **************************************************************************************** + * @@ -79290,12 +79991,27 @@ index 000000000000..7e4e9d44cb42 +enum WIFINET_PUBLIC_ACTION +{ + WIFINET_ACT_PUBLIC_BSSCOEXIST = 0, ++ WIFINET_ACT_PUBLIC_CSA = 4, + WIFINET_ACT_PUBLIC_MP = 7, + WIFINET_ACT_PUBLIC_P2P = 9, + WIFINET_ACT_PUBLIC_GAS_REQ = 10, + WIFINET_ACT_PUBLIC_GAS_RSP = 11, +}; + ++struct wifi_mac_ie_csa ++{ ++ unsigned char chan_switch_mode; ++ unsigned char new_operation_class; ++ unsigned char new_chan_num; ++ unsigned char chan_switch_count; ++}__packed; ++ ++struct wifi_mac_action_csa_frame ++{ ++ struct wifi_mac_action ac_header; ++ struct wifi_mac_ie_csa csa; ++} __packed; ++ +#define OUI_TYPE_P2P 0x09 +#define OUI_TYPE_DPP 0x1a + @@ -79469,7 +80185,7 @@ index 000000000000..7e4e9d44cb42 +#endif//_WIFI_MAC_ACTION_H_ diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_amsdu.c b/drivers/net/wireless/w1/vmac/wifi_mac_amsdu.c new file mode 100644 -index 000000000000..83633b1d39a9 +index 0000000000000000000000000000000000000000..5063025bf8f6f6d4d078f92696b3bf2e8e8e96f8 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_amsdu.c @@ -0,0 +1,689 @@ @@ -79495,7 +80211,7 @@ index 000000000000..83633b1d39a9 +/*avoid use kalloc to allocate mem. */ +static struct wifi_mac_msdu_node g_msdu_node [(MAX_MSDU_CNT + 4) * WME_NUM_TID]; + -+int wifi_mac_msdu_list_init(struct msdu_list * msdu_list, int num) ++static int wifi_mac_msdu_list_init(struct msdu_list * msdu_list, int num) +{ + int i = 0; + int node_num = num; @@ -79519,7 +80235,7 @@ index 000000000000..83633b1d39a9 + return node_num; +} + -+struct wifi_mac_msdu_node *wifi_mac_msdu_node_alloc(struct msdu_list *msdu_list) ++static struct wifi_mac_msdu_node *wifi_mac_msdu_node_alloc(struct msdu_list *msdu_list) +{ + struct wifi_mac_msdu_node *msdu_node = NULL; + @@ -79535,7 +80251,7 @@ index 000000000000..83633b1d39a9 + return msdu_node; +} + -+void wifi_mac_msdu_node_free(struct wifi_mac_msdu_node *msdu_node, struct msdu_list *msdu_list) ++static void wifi_mac_msdu_node_free(struct wifi_mac_msdu_node *msdu_node, struct msdu_list *msdu_list) +{ + if (msdu_node == NULL || msdu_list == NULL) + return; @@ -80146,7 +80862,7 @@ index 000000000000..83633b1d39a9 + sta->sta_amsdu->amsdu_max_length = MIN(sta->sta_amsdu->amsdu_max_length, AMSDU_SIZE_3839); + } + -+ printk(" %s (%d) amsdu_max_length=%d\n", __func__,__LINE__, sta->sta_amsdu->amsdu_max_length ); ++ pr_debug(" %s (%d) amsdu_max_length=%d\n", __func__,__LINE__, sta->sta_amsdu->amsdu_max_length ); + + for (tid = 0; tid < WME_NUM_TID; tid++) + { @@ -80164,7 +80880,7 @@ index 000000000000..83633b1d39a9 + diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_amsdu.h b/drivers/net/wireless/w1/vmac/wifi_mac_amsdu.h new file mode 100644 -index 000000000000..f25270d6f6b1 +index 0000000000000000000000000000000000000000..f25270d6f6b182ec1f4885985412e4237e1f2cd7 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_amsdu.h @@ -0,0 +1,84 @@ @@ -80254,78 +80970,78 @@ index 000000000000..f25270d6f6b1 +#endif /* _IEEE80211_AMSDU_H_ */ diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_arp.h b/drivers/net/wireless/w1/vmac/wifi_mac_arp.h new file mode 100644 -index 000000000000..7914aa34e188 +index 0000000000000000000000000000000000000000..8a48beb8fdb428b5382c9613c0c23fa693e9a70b --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_arp.h @@ -0,0 +1,62 @@ -+/* -+ **************************************************************************************** -+ * -+ * Copyright (C) Amlogic 2010-2014 -+ * -+ * Project: 11N 80211 mac layer Software -+ * -+ * Description: -+ * wifi_mac layer interface function/interface use by driver layer -+ * -+ * -+ **************************************************************************************** -+ */ -+ -+#ifndef _WIFI_MAC_ARP_H_ -+#define _WIFI_MAC_ARP_H_ -+ -+#define WIFI_ARP_GET_AP_IP BIT(0) -+ -+#define IPV4_LEN 4 -+#define ETHERNET_HW_TYPE 1 -+#define ARP_HW_ADDR_LEN 6 -+#define ARP_PROTO_ADDR_LEN 4 -+#define ARP_REQUEST 1 -+#define ARP_RESPONSE 2 -+ -+typedef struct wifi_arp_pkt { -+ unsigned short hw_type; -+ unsigned short proto_type; -+ unsigned char hw_len; -+ unsigned char proto_len; -+ unsigned short op; -+ unsigned char src_mac_addr[WIFINET_ADDR_LEN]; -+ unsigned char src_ip_addr[IPV4_LEN]; -+ unsigned char dst_mac_addr[WIFINET_ADDR_LEN]; -+ unsigned char dst_ip_addr[IPV4_LEN]; -+} wifi_arp_pkt; -+ -+typedef struct wifi_mac_iphdr { -+ unsigned char version; -+ unsigned char tos; -+ unsigned short tot_len; -+ unsigned short id; -+ unsigned short frag_off; -+ unsigned char ttl; -+ unsigned char protocol; -+ unsigned short check; -+ unsigned int saddr; -+ unsigned int daddr; -+} wifi_ip_header; -+ -+typedef struct wifi_udp_pkt { -+ unsigned short src_port; -+ unsigned short dst_port; -+ unsigned short len; -+ unsigned short checksum; -+ unsigned char data[0]; -+} wifi_udp_pkt; -+ -+ -+#endif//_WIFI_MAC_ARP_H_ -+ ++/* ++ **************************************************************************************** ++ * ++ * Copyright (C) Amlogic 2010-2014 ++ * ++ * Project: 11N 80211 mac layer Software ++ * ++ * Description: ++ * wifi_mac layer interface function/interface use by driver layer ++ * ++ * ++ **************************************************************************************** ++ */ ++ ++#ifndef _WIFI_MAC_ARP_H_ ++#define _WIFI_MAC_ARP_H_ ++ ++#define WIFI_ARP_GET_AP_IP BIT(0) ++ ++#define IPV4_LEN 4 ++#define ETHERNET_HW_TYPE 1 ++#define ARP_HW_ADDR_LEN 6 ++#define ARP_PROTO_ADDR_LEN 4 ++#define ARP_REQUEST 1 ++#define ARP_RESPONSE 2 ++ ++typedef struct wifi_arp_pkt { ++ unsigned short hw_type; ++ unsigned short proto_type; ++ unsigned char hw_len; ++ unsigned char proto_len; ++ unsigned short op; ++ unsigned char src_mac_addr[WIFINET_ADDR_LEN]; ++ unsigned char src_ip_addr[IPV4_LEN]; ++ unsigned char dst_mac_addr[WIFINET_ADDR_LEN]; ++ unsigned char dst_ip_addr[IPV4_LEN]; ++} wifi_arp_pkt; ++ ++typedef struct wifi_mac_iphdr { ++ unsigned char version; ++ unsigned char tos; ++ unsigned short tot_len; ++ unsigned short id; ++ unsigned short frag_off; ++ unsigned char ttl; ++ unsigned char protocol; ++ unsigned short check; ++ unsigned int saddr; ++ unsigned int daddr; ++} wifi_ip_header; ++ ++typedef struct wifi_udp_pkt { ++ unsigned short src_port; ++ unsigned short dst_port; ++ unsigned short len; ++ unsigned short checksum; ++ unsigned char data[0]; ++} wifi_udp_pkt; ++ ++ ++#endif//_WIFI_MAC_ARP_H_ ++ diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_beacon.c b/drivers/net/wireless/w1/vmac/wifi_mac_beacon.c new file mode 100644 -index 000000000000..40d5fbf94970 +index 0000000000000000000000000000000000000000..be831b1bb067092eab410a42dc51c5df1a32fe04 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_beacon.c -@@ -0,0 +1,917 @@ +@@ -0,0 +1,1112 @@ +/* + **************************************************************************************** + * @@ -80348,11 +81064,11 @@ index 000000000000..40d5fbf94970 + struct wlan_net_vif *wnet_vif = sta->sta_wnet_vif; + struct wifi_mac *wifimac = sta->sta_wmac; + unsigned short capinfo; -+ struct wifi_mac_rateset *rs = &sta->sta_rates; ++ struct wifi_mac_rateset rs = sta->sta_rates; + unsigned char index = 0; + + KASSERT(wnet_vif->vm_curchan != WIFINET_CHAN_ERR, ("no bss chan")); -+ printk("%s(%d)\n", __func__, __LINE__); ++ pr_debug("%s(%d)\n", __func__, __LINE__); + + memset(frm, 0, 8); + frm += 8; @@ -80380,6 +81096,7 @@ index 000000000000..40d5fbf94970 + *(unsigned short *)frm = htole16(capinfo); + + frm += 2; ++ bo->bo_ssid = frm; + *frm++ = WIFINET_ELEMID_SSID; + if ((wnet_vif->vm_flags & WIFINET_F_HIDESSID) == 0) { + *frm++ = sta->sta_esslen; @@ -80391,7 +81108,10 @@ index 000000000000..40d5fbf94970 + } + + bo->bo_rates = frm; -+ frm = wifi_mac_add_rates(frm, rs); ++ if (wnet_vif->vm_sae_h2e_only == 1) { ++ rs.dot11_rate[rs.dot11_rate_num++] = WIFINET_SAE_H2E_ONLY; ++ } ++ frm = wifi_mac_add_rates(frm, &rs); + + /*VHT mode ,non-support DSSS Parameter Set*/ + *frm++ = WIFINET_ELEMID_DSPARMS; @@ -80432,16 +81152,24 @@ index 000000000000..40d5fbf94970 + *frm++ = WIFINET_PWRCONSTRAINT_VAL(wnet_vif); + } + bo->bo_chanswitch = frm; ++ bo->bo_extchanswitch = frm; ++ bo->bo_erp = NULL; + -+ if (WIFINET_INCLUDE_11G(wnet_vif->vm_mac_mode)) { ++ if (WIFINET_INCLUDE_11G(wnet_vif->vm_mac_mode) ++ && (wnet_vif->vm_curchan->chan_pri_num >= 1 && wnet_vif->vm_curchan->chan_pri_num <= 14)) { + bo->bo_erp = frm; + frm = wifi_mac_add_erp(frm, wifimac); + } + -+ if (wnet_vif->vm_flags & WIFINET_F_WPA) ++ if (wnet_vif->vm_flags & WIFINET_F_WPA) { + frm = wifi_mac_add_wpa(frm, wnet_vif); ++ if (wnet_vif->vm_flags & WIFINET_F_H2E) { ++ frm = wifi_mac_add_rsnxe(frm, wnet_vif); ++ AML_OUTPUT("added rsnxe ie\n"); ++ } ++ } + -+ frm = wifi_mac_add_xrates(frm, rs); ++ frm = wifi_mac_add_xrates(frm, &rs); + if (wnet_vif->vm_flags & WIFINET_F_WME) { + bo->bo_wme = frm; + frm = wifi_mac_add_wme_param(frm, &wifimac->wm_wme[wnet_vif->wnet_vif_id], WIFINET_VMAC_UAPSD_ENABLED(wnet_vif)); @@ -80483,11 +81211,14 @@ index 000000000000..40d5fbf94970 + frm = wifi_mac_add_vendor_ie(frm, wifimac, index); + } + } ++ bo->bo_ch_sw_wrp = frm; + bo->bo_appie_buf = frm; + bo->bo_appie_buf_len = 0; + wnet_vif->vm_flags_ext |= WIFINET_FEXT_APPIE_UPDATE; + bo->bo_tim_trailerlen = frm - bo->bo_tim_trailer; + bo->bo_chanswitch_trailerlen = frm - bo->bo_chanswitch; ++ bo->bo_extchanswitch_trailerlen = frm - bo->bo_extchanswitch; ++ bo->bo_chswwrp_trailerlen = frm - bo->bo_ch_sw_wrp; + bo->bo_initial = 1; + bo->bo_bcn_seq = 0; + return frm; @@ -80549,21 +81280,59 @@ index 000000000000..40d5fbf94970 + struct wifi_mac *wifimac = sta->sta_wmac; + int len_changed = 0; + unsigned short capinfo; -+ struct wifi_channel *main_vmac_chan = NULL; ++ struct wifi_channel *switch_chan = NULL; + unsigned char concurrent_set_channel = 1; + + if (bo->bo_initial != 1) + { -+ printk(KERN_CRIT "%s %d, bug to fix\n",__func__,__LINE__); ++ pr_crit("%s %d, bug to fix\n",__func__,__LINE__); + return len_changed; + } + ++ if (wnet_vif->vm_p2p->go_hidden_mode != (wnet_vif->vm_flags & WIFINET_F_HIDESSID)>>WIFINET_F_HIDESSID_TO_BIT0_OFST) { ++ unsigned char *frm; ++ ++ DPRINTF(AML_DEBUG_BEACON, "%s(%d), GO_HIDDEN_MODE[%d], HIDESSID[%d], CHANNEL_SWITCH[%d]\n", ++ __func__, __LINE__, wnet_vif->vm_p2p->go_hidden_mode, ++ (wnet_vif->vm_flags & WIFINET_F_HIDESSID) >> 27,(wifimac->wm_flags & WIFINET_F_CHANSWITCH) >> 31); ++ ++ if (!((wifimac->wm_flags & WIFINET_F_DOTH) && (wifimac->wm_flags & WIFINET_F_CHANSWITCH))) { ++ if (wnet_vif->vm_p2p->go_hidden_mode) { ++ wnet_vif->vm_flags |= WIFINET_F_HIDESSID; ++ } else { ++ wnet_vif->vm_flags &= ~WIFINET_F_HIDESSID; ++ } ++ } ++ ++ WIFINET_BEACON_LOCK(wifimac); ++ os_skb_pull(skb, sizeof(struct wifi_frame)); ++ os_skb_trim(skb, 0); ++ frm = os_skb_data(skb); ++ if (frm == NULL) ++ { ++ WIFINET_BEACON_UNLOCK(wifimac); ++ ERROR_DEBUG_OUT(" ERROR\n"); ++ return 0; ++ } ++ os_skb_put(skb, wifi_mac_beacon_init(sta, bo, frm) - frm); ++ os_skb_push(skb, sizeof(struct wifi_frame)); ++ WIFINET_BEACON_UNLOCK(wifimac); ++ ++ if ((wifimac->wm_flags & WIFINET_F_DOTH) && (wifimac->wm_flags & WIFINET_F_CHANSWITCH)) { ++ if (wnet_vif->vm_p2p->go_hidden_mode) { ++ wnet_vif->vm_flags |= WIFINET_F_HIDESSID; ++ } else { ++ wnet_vif->vm_flags &= ~WIFINET_F_HIDESSID; ++ } ++ } ++ } ++ + if ((wifimac->wm_flags & WIFINET_F_DOTH) && (wnet_vif->vm_flags & WIFINET_F_CHANSWITCH) && + (wnet_vif->vm_chanchange_count == wifimac->wm_doth_tbtt)) + { + unsigned char *frm; -+ struct wifi_mac_ie_vht_opt *vhtop = (struct wifi_mac_ie_vht_opt *) bo->bo_vhtop; + int center_chan = 0; ++ unsigned char channel_switch_flag = CHANNEL_CONNECT_FLAG | CHANNEL_RESTORE_FLAG; + + if (wnet_vif->vm_bandwidth == WIFINET_BWC_WIDTH20) + { @@ -80571,7 +81340,7 @@ index 000000000000..40d5fbf94970 + } + else if (wnet_vif->vm_bandwidth == WIFINET_BWC_WIDTH40) + { -+ if (wnet_vif->scnd_chn_offset == WIFINET_HTINFO_EXTOFFSET_ABOVE) ++ if (wnet_vif->scnd_chn_offset == WIFINET_HTINFO_EXTOFFSET_BELOW) + center_chan = wifimac->wm_doth_channel + 2; + else if (wnet_vif->scnd_chn_offset == WIFINET_HTINFO_EXTOFFSET_ABOVE) + center_chan = wifimac->wm_doth_channel - 2; @@ -80580,7 +81349,9 @@ index 000000000000..40d5fbf94970 + } + else if (wnet_vif->vm_bandwidth == WIFINET_BWC_WIDTH80) + { -+ center_chan = vhtop->vht_op_ch_freq_seg1; ++ if (wnet_vif->vm_curchan != NULL) { ++ center_chan = wifi_mac_mhz2chan(wnet_vif->vm_curchan->chan_cfreq1); ++ } + } + else + { @@ -80588,67 +81359,123 @@ index 000000000000..40d5fbf94970 + } + + if (IS_APSTA_CONCURRENT(aml_wifi_get_con_mode())) { ++ if (wnet_vif->csa_target.switch_chan.chan_pri_num != 0) { ++ switch_chan = &(wnet_vif->csa_target.switch_chan); + -+ if (wifi_mac_is_others_wnet_vif_running(wnet_vif) == true) { -+ main_vmac_chan = wifi_mac_get_main_vmac_channel(wifimac); -+ -+ if ((main_vmac_chan) -+ && (main_vmac_chan->chan_pri_num == wnet_vif->vm_curchan->chan_pri_num) -+ && (main_vmac_chan->chan_bw == wnet_vif->vm_bandwidth) -+ && (center_chan == wifi_mac_Mhz2ieee(main_vmac_chan->chan_cfreq1, 0))) { -+ ++ if (wnet_vif->vm_curchan ++ && !memcmp(switch_chan, wnet_vif->vm_curchan, sizeof(struct wifi_channel))) { + concurrent_set_channel = 0;//no need set channel again due to bw ++ memset(&(wnet_vif->csa_target.switch_chan), 0, sizeof(struct wifi_channel)); + } + } else { + /*no other vmac running, no need set concurrent channel*/ + concurrent_set_channel = 0; + } + -+ + if (concurrent_set_channel) { /*need think if system want to change channel*/ -+ struct wlan_net_vif *main_wnet_vif = wifi_mac_running_main_wnet_vif(wifimac); ++ struct wifi_station *sta_entry = NULL, *next = NULL; ++ struct wifi_station_tbl *nt = &wnet_vif->vm_sta_tbl; ++ int update_band_to_2g = 0; ++ int update_band_to_5g = 0; ++ ++ /*sta connect to 5G ap, softap need update channel/band/mac_mode as sta*/ ++ if (switch_chan) { ++ if (wnet_vif->vm_curchan) { ++ if ((wnet_vif->vm_curchan->chan_pri_num >= 36) ++ && (switch_chan->chan_pri_num <= 14)) { ++ update_band_to_2g = 1; ++ } else if((wnet_vif->vm_curchan->chan_pri_num <= 14) ++ && (switch_chan->chan_pri_num > 36)) { ++ update_band_to_5g = 1; ++ } ++ } + -+ /*sta connect to 5G ap, softap need update channel/band/mac_mode as sta*/ -+ if (main_wnet_vif && main_vmac_chan) { -+ wnet_vif->vm_curchan = main_vmac_chan; -+ wnet_vif->vm_bandwidth = main_vmac_chan->chan_bw; -+ wnet_vif->vm_mac_mode = main_wnet_vif->vm_mac_mode; -+ sta->sta_chbw = main_vmac_chan->chan_bw; ++ wnet_vif->vm_curchan = switch_chan; ++ wnet_vif->vm_bandwidth = switch_chan->chan_bw; + + if (wnet_vif->vm_curchan->chan_bw >= WIFINET_BWC_WIDTH40) { + wnet_vif->vm_htcap |= WIFINET_HTCAP_SUPPORTCBW40; + } + -+ if (main_vmac_chan->chan_pri_num < wifi_mac_Mhz2ieee(main_vmac_chan->chan_cfreq1, 0)) { ++ if (switch_chan->chan_pri_num < wifi_mac_Mhz2ieee(switch_chan->chan_cfreq1, 0)) { + wnet_vif->scnd_chn_offset = WIFINET_HTINFO_EXTOFFSET_ABOVE; -+ } else if (main_vmac_chan->chan_pri_num > wifi_mac_Mhz2ieee(main_vmac_chan->chan_cfreq1, 0)) { ++ } else if (switch_chan->chan_pri_num > wifi_mac_Mhz2ieee(switch_chan->chan_cfreq1, 0)) { + wnet_vif->scnd_chn_offset = WIFINET_HTINFO_EXTOFFSET_BELOW; + } else{ + wnet_vif->scnd_chn_offset = WIFINET_HTINFO_EXTOFFSET_NA; + } + -+ wifi_mac_set_wnet_vif_channel(wnet_vif, main_vmac_chan->chan_pri_num, main_vmac_chan->chan_bw, wifi_mac_Mhz2ieee(main_vmac_chan->chan_cfreq1, 0)); -+ printk("set ap %s(%d) chan %d, mac mode %d, band %d\n",__func__,__LINE__, -+ wnet_vif->vm_curchan->chan_pri_num, wnet_vif->vm_mac_mode, wnet_vif->vm_bandwidth); ++ wifi_mac_set_wnet_vif_channel(wnet_vif, switch_chan->chan_pri_num, switch_chan->chan_bw, wifi_mac_Mhz2ieee(switch_chan->chan_cfreq1, 0), channel_switch_flag); ++ pr_debug("%s(%d) set ap chan %d, mac mode %d, band %d slot %d\n",__func__,__LINE__, ++ wnet_vif->vm_curchan->chan_pri_num, wnet_vif->vm_mac_mode, wnet_vif->vm_bandwidth, wifimac->wm_vsdb_slot); ++ ++ list_for_each_entry_safe(sta_entry, next, &nt->nt_nsta, sta_list) { ++ if (sta_entry->sta_associd != 0) { ++ if (sta_entry->sta_chbw > switch_chan->chan_bw) { ++ sta_entry->sta_chbw = switch_chan->chan_bw; ++ } ++ ++ if (update_band_to_2g) { ++ sta_entry->sta_flags &= ~WIFINET_NODE_VHT; ++ sta_entry->sta_vhtcap = 0; ++ } ++ } ++ } ++ ++ if (wifimac->wm_vsdb_slot != CONCURRENT_SLOT_NONE) { ++ wifi_mac_set_vsdb_task(wifimac, wnet_vif, DISABLE); ++ wifimac->wm_vsdb_slot = CONCURRENT_SLOT_NONE; ++ wifimac->vsdb_mode_set_noa_enable = 0; ++ ++ if (wifimac->wm_vsdb_slot == CONCURRENT_SLOT_P2P) { ++ /*sta need notify ap*/ ++ wifimac->wm_vsdb_flags = CONCURRENT_SWITCH_TO_STA_CHANNEL; ++ } else { ++ wifimac->wm_vsdb_flags = 0; ++ wifimac->wm_vsdb_slot = CONCURRENT_SLOT_NONE; ++ } ++ ++ if (wnet_vif->vm_wdev->iftype == NL80211_IFTYPE_P2P_GO) ++ { ++ if (wnet_vif->vm_p2p->p2p_flag & P2P_OPPPS_START_FLAG_HI) ++ { ++ vm_p2p_go_cancel_opps(wnet_vif->vm_p2p); ++ } ++ if (wnet_vif->vm_p2p->p2p_flag & P2P_NOA_START_FLAG_HI) ++ { ++ vm_p2p_go_cancel_noa(wnet_vif->vm_p2p); ++ } ++ } ++ } ++ wnet_vif->csa_target.start = 0; ++ wifi_mac_add_work_task(wifimac, vm_cfg80211_chan_switch_notify_task, NULL, (SYS_TYPE)wifimac, (SYS_TYPE)wnet_vif, 0, (SYS_TYPE)&(wnet_vif->csa_target.switch_chan), 0); + } + } + } else { -+ if (wifi_mac_set_wnet_vif_channel(wnet_vif, wifimac->wm_doth_channel, wnet_vif->vm_bandwidth, center_chan) == false) ++ if (wifi_mac_set_wnet_vif_channel(wnet_vif, wifimac->wm_doth_channel, wnet_vif->vm_bandwidth, center_chan, channel_switch_flag) == false) + { + return 0; + } + } + WIFINET_BEACON_LOCK(wifimac); ++ wifi_mac_ap_set_basic_rates(wnet_vif, wnet_vif->vm_mac_mode); ++ wifi_mac_set_legacy_rates(&wnet_vif->vm_legacy_rates, wnet_vif); ++ sta->sta_rates = wnet_vif->vm_legacy_rates; ++ sta->sta_htrates = wifimac->wm_sup_ht_rates; ++ sta->sta_vhtrates = wifimac->wm_sup_vht_rates; ++ wifi_mac_build_country_ie(wnet_vif); + wnet_vif->vm_chanchange_count = 0; + wnet_vif->vm_flags &= ~WIFINET_F_CHANSWITCH; + wifimac->wm_flags &= ~WIFINET_F_CHANSWITCH; ++ wnet_vif->vm_flags &= ~WIFINET_F_DOTH; ++ wifimac->wm_flags &= ~WIFINET_F_DOTH; + os_skb_pull(skb, sizeof(struct wifi_frame)); + os_skb_trim(skb, 0); + frm = os_skb_data(skb); + if (frm == NULL) + { + WIFINET_BEACON_UNLOCK(wifimac); -+ printk(" %s %d ERROR\n",__func__,__LINE__); ++ pr_err(" %s %d ERROR\n",__func__,__LINE__); + return 0; + } + os_skb_put(skb, wifi_mac_beacon_init(sta, bo, frm) - frm); @@ -80687,7 +81514,7 @@ index 000000000000..40d5fbf94970 + struct wifi_mac_wme_state *wme = &wifimac->wm_wme[wnet_vif->wnet_vif_id]; + if (wme == NULL) + { -+ printk(" %s %d ERROR!!\n",__func__,__LINE__); ++ pr_err(" %s %d ERROR!!\n",__func__,__LINE__); + } + + if (wnet_vif->vm_flags_ext & WIFINET_FEXT_WMETUN) @@ -80802,9 +81629,15 @@ index 000000000000..40d5fbf94970 + bo->bo_tim_trailerlen); + bo->bo_tim_trailer = tie->tim_bitmap+timlen; + bo->bo_chanswitch += trailer_adjust; ++ bo->bo_extchanswitch += trailer_adjust; ++ bo->bo_ch_sw_wrp += trailer_adjust; + bo->bo_wme += trailer_adjust; -+ bo->bo_erp += trailer_adjust; + bo->bo_appie_buf += trailer_adjust; ++ if (bo->bo_erp) ++ { ++ bo->bo_erp += trailer_adjust; ++ } ++ + if (timlen > bo->bo_tim_len) + os_skb_put(skb, timlen - bo->bo_tim_len); + else @@ -80868,33 +81701,40 @@ index 000000000000..40d5fbf94970 + WIFINET_BEACON_LOCK(wifimac); + if ((wifimac->wm_flags & WIFINET_F_DOTH) && (wifimac->wm_flags & WIFINET_F_CHANSWITCH)) + { ++ if (wnet_vif->csa_target.switch_chan.chan_pri_num == 0) { ++ ERROR_DEBUG_OUT("error primary channel number:%d\n",wnet_vif->csa_target.switch_chan.chan_pri_num); ++ } ++ switch_chan = &(wnet_vif->csa_target.switch_chan); ++ ++ if (((wifimac->wm_vsdb_slot == CONCURRENT_SLOT_P2P) || (wifimac->wm_vsdb_slot == CONCURRENT_SLOT_NONE)) ++ && !(wnet_vif->csa_target.start)) { ++ wnet_vif->csa_target.start = 1; ++ wnet_vif->csa_count = wifimac->wm_doth_tbtt; ++ DPRINTF(AML_DEBUG_BEACON, "%s(%d), channel switch announce start, vsdb_slot:%d\n", ++ __func__, __LINE__, wifimac->wm_vsdb_slot); ++ } + -+ if (!wnet_vif->vm_chanchange_count) ++ if (wnet_vif->csa_count > 0) { ++ static struct cfg80211_chan_def chan_def = {0}; ++ if (wifi_mac_get_chandef(switch_chan, &chan_def) == true) { ++ wifi_mac_add_work_task(wifimac, wifi_mac_csa_send_action_task, NULL, (SYS_TYPE) wifimac, (SYS_TYPE) wnet_vif, (SYS_TYPE) &chan_def, 0, 0); ++ } ++ } ++ ++ if (!wnet_vif->vm_chanchange_count && wnet_vif->csa_target.start) + { + wnet_vif->vm_flags |= WIFINET_F_CHANSWITCH; -+ -+ memmove(bo->bo_chanswitch + WIFINET_CHANSWITCHANN_BYTES, -+ bo->bo_chanswitch, bo->bo_chanswitch_trailerlen); -+ -+ bo->bo_chanswitch[0] = WIFINET_ELEMID_CHANSWITCHANN; -+ bo->bo_chanswitch[1] = 3; -+ bo->bo_chanswitch[2] = 1; -+ bo->bo_chanswitch[3] = wifimac->wm_doth_channel; -+ bo->bo_chanswitch[4] = wifimac->wm_doth_tbtt; -+ bo->bo_chanswitch_trailerlen += WIFINET_CHANSWITCHANN_BYTES; -+ bo->bo_tim_trailerlen += WIFINET_CHANSWITCHANN_BYTES; -+ bo->bo_wme += WIFINET_CHANSWITCHANN_BYTES; -+ bo->bo_erp += WIFINET_CHANSWITCHANN_BYTES; -+ bo->bo_appie_buf += WIFINET_CHANSWITCHANN_BYTES; -+ -+ os_skb_put(skb, WIFINET_CHANSWITCHANN_BYTES); ++ wifi_mac_beacon_update_csaie(sta, bo, skb, switch_chan); + len_changed = 1; ++ wifi_mac_add_work_task(wifimac, vm_cfg80211_chan_switch_notify_task, NULL, (SYS_TYPE)wifimac, (SYS_TYPE)wnet_vif, 1, (SYS_TYPE)&(wnet_vif->csa_target.switch_chan), 0); + } -+ else ++ else if (wnet_vif->vm_chanchange_count && wnet_vif->csa_target.start) + { + bo->bo_chanswitch[4]--; ++ if (switch_chan->chan_bw == WIFINET_BWC_WIDTH80) { ++ bo->bo_extchanswitch[5]--; ++ } + } -+ + } + if (((jiffies - wifimac->wm_time_nonerp_present) >= WIFINET_INACT_NONERP * HZ) + && wifimac->wm_nonerpsta == 0 && (wifimac->wm_flags & WIFINET_F_USEPROT)) @@ -80904,13 +81744,17 @@ index 000000000000..40d5fbf94970 + wifi_mac_update_protmode(wifimac); + wifi_mac_set_shortslottime(wifimac, 1); + } -+ if (wifimac->wm_flags_ext & WIFINET_FEXT_ERPUPDATE) ++ ++ if ((wifimac->wm_flags_ext & WIFINET_FEXT_ERPUPDATE) && ++ (wnet_vif->vm_curchan->chan_pri_num >= 1 && wnet_vif->vm_curchan->chan_pri_num <= 14)) + { -+ wifi_mac_add_erp(bo->bo_erp, wifimac); -+ wifimac->wm_flags_ext &= ~WIFINET_FEXT_ERPUPDATE; ++ if (bo->bo_erp) { ++ wifi_mac_add_erp(bo->bo_erp, wifimac); ++ wifimac->wm_flags_ext &= ~WIFINET_FEXT_ERPUPDATE; ++ } + } + -+ if ((wifimac->wm_flags & WIFINET_F_DOTH) && (wifimac->wm_flags & WIFINET_F_CHANSWITCH)) ++ if ((wifimac->wm_flags & WIFINET_F_DOTH) && (wifimac->wm_flags & WIFINET_F_CHANSWITCH) && wnet_vif->csa_target.start) + { + wnet_vif->vm_chanchange_count++; + if (wnet_vif->vm_chanchange_count == wifimac->wm_doth_tbtt) { @@ -80957,7 +81801,7 @@ index 000000000000..40d5fbf94970 + && (wnet_vif->vm_p2p->p2p_enable == 1) + && (wnet_vif->vm_p2p->p2p_flag & P2P_NOA_START_FLAG_HI)) + { -+ printk("%s(%d) noa_len %d\n",__func__,__LINE__, ++ pr_debug("%s(%d) noa_len %d\n",__func__,__LINE__, + wnet_vif->app_ie[WIFINET_APPIE_FRAME_BEACON].length); + vm_p2p_update_noa_count_start(wnet_vif->vm_p2p); + } @@ -80980,7 +81824,8 @@ index 000000000000..40d5fbf94970 + bo->bo_appie_buf_len = wnet_vif->app_ie[WIFINET_APPIE_FRAME_BEACON].length; + bo->bo_chanswitch_trailerlen += diff_len; + bo->bo_tim_trailerlen += diff_len; -+ ++ bo->bo_chswwrp_trailerlen += diff_len; ++ bo->bo_extchanswitch_trailerlen += diff_len; + len_changed = 1; + } + if (wnet_vif->app_ie[WIFINET_APPIE_FRAME_BEACON].ie != NULL) @@ -81051,7 +81896,7 @@ index 000000000000..40d5fbf94970 + return ; + } + -+ printk("%s %d \n",__func__,__LINE__); ++ pr_debug("%s %d \n",__func__,__LINE__); + wifi_mac_beacon_alloc(ieee, wnet_vif_id); +} + @@ -81123,7 +81968,7 @@ index 000000000000..40d5fbf94970 + { + /* FIXME: Remove, Beacon lock in drv_main.c bcn_tx_ok irq */ + WIFINET_BEACONBUF_UNLOCK(wifimac); -+ printk(" %s %d beacon_realloc\n",__func__,__LINE__); ++ pr_debug(" %s %d beacon_realloc\n",__func__,__LINE__); + wifi_mac_beacon_alloc(ieee, wnet_vif_id); + WIFINET_BEACONBUF_LOCK(wifimac); + } @@ -81135,8 +81980,7 @@ index 000000000000..40d5fbf94970 + struct wlan_net_vif *wnet_vif = (struct wlan_net_vif *)arg; + struct wifi_mac *wifimac = wnet_vif->vm_wmac; + -+ /* Keep beacon miss count log for debugging disconnects */ -+ printk("WiFi beacon miss: vid=%d, beacon_miss_count=%d\n", wnet_vif->wnet_vif_id, wnet_vif->vm_bmiss_count); ++ pr_debug("%s vid:%d, vm_bmiss_count:%d\n", __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_bmiss_count); + + if (wnet_vif->vm_opmode != WIFINET_M_STA || + wnet_vif->vm_state != WIFINET_S_CONNECTED) @@ -81154,7 +81998,7 @@ index 000000000000..40d5fbf94970 + /*if not in roaming mode, triger roaming */ + if ((wifimac->wm_roaming == WIFINET_ROAMING_BASIC) && (wnet_vif->vm_chan_roaming_scan_flag != 1) + && (wnet_vif->vm_bmiss_count >= 2)) { -+ printk("WiFi roaming triggered: beacon_miss_count=%d\n", wnet_vif->vm_bmiss_count); ++ pr_warn("Miss beacon trigger roaming\n"); + wifi_mac_roaming_trigger(wnet_vif); + } + return; @@ -81164,19 +82008,15 @@ index 000000000000..40d5fbf94970 + * when 2 beacons lost: 1) sta is in roaming, then do asso + * otherwise 2) sta lost ap totally then do scan again + */ -+ printk("WiFi disconnect: Beacon lost, max_miss_count=%d reached\n", WIFINET_BMISS_COUNT_MAX); + wnet_vif->vm_bmiss_count = 0; + if (wifimac->wm_roaming == WIFINET_ROAMING_FAST) { + DPRINTF(AML_DEBUG_WARNING,"roaming bcn lost...\n"); -+ printk("WiFi: Fast roaming mode, attempting reassociation\n"); + wifi_mac_top_sm(wnet_vif, WIFINET_S_ASSOC, 1); + } + else { + DPRINTF(AML_DEBUG_WARNING,"bcn lost...re-scan\n"); -+ printk("WiFi: Beacon lost, restarting scan\n"); -+ ++ wnet_vif->disconnect_reason_code = 4; + wnet_vif->vm_chan_roaming_scan_flag = 0; -+ + wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN, 0); + } +} @@ -81225,13 +82065,12 @@ index 000000000000..40d5fbf94970 + return; +} + -+int wifi_mac_set_vsdb_ex(struct wlan_net_vif *wnet_vif, unsigned char enable) ++static void wifi_mac_set_vsdb_ex(struct wlan_net_vif *wnet_vif, unsigned char enable) +{ + struct wifi_mac *wifimac = wnet_vif->vm_wmac; + -+ printk("%s, vid:%d, enable:%d\n", __func__, wnet_vif->wnet_vif_id, enable); ++ pr_debug("%s, vid:%d, enable:%d\n", __func__, wnet_vif->wnet_vif_id, enable); + wifimac->drv_priv->drv_ops.drv_set_vsdb(wifimac->drv_priv, wnet_vif->wnet_vif_id, enable); -+ return 0; +} + +void wifi_mac_set_vsdb(SYS_TYPE param1, SYS_TYPE param2,SYS_TYPE param3, @@ -81243,12 +82082,84 @@ index 000000000000..40d5fbf94970 + wifi_mac_set_vsdb_ex(wnet_vif, enable); +} + ++void wifi_mac_beacon_update_csaie(struct wifi_station *sta, ++ struct wifi_mac_beacon_offsets *bo, struct sk_buff *skb, struct wifi_channel *switch_chan) ++{ ++ memmove(bo->bo_chanswitch + WIFINET_CHANSWITCHANN_BYTES, ++ bo->bo_chanswitch, bo->bo_chanswitch_trailerlen); ++ ++ wifi_mac_add_chanswitch(bo->bo_chanswitch,sta); ++ bo->bo_chanswitch_trailerlen += WIFINET_CHANSWITCHANN_BYTES; ++ bo->bo_tim_trailerlen += WIFINET_CHANSWITCHANN_BYTES; ++ bo->bo_appie_buf += WIFINET_CHANSWITCHANN_BYTES; ++ bo->bo_ch_sw_wrp += WIFINET_CHANSWITCHANN_BYTES; ++ bo->bo_extchanswitch += WIFINET_CHANSWITCHANN_BYTES; ++ bo->bo_wme += WIFINET_CHANSWITCHANN_BYTES; ++ if (bo->bo_erp) ++ bo->bo_erp += WIFINET_CHANSWITCHANN_BYTES; ++ ++ os_skb_put(skb, WIFINET_CHANSWITCHANN_BYTES); ++ ++ if (switch_chan->chan_bw >= WIFINET_BWC_WIDTH40) { ++ int chswwrp_len = 0; ++ if (switch_chan->chan_bw == WIFINET_BWC_WIDTH80) { ++ /*add extend channel switch ie*/ ++ memmove(bo->bo_extchanswitch + WIFINET_EXTCHANSWITCHANN_BYTES, ++ bo->bo_extchanswitch, bo->bo_extchanswitch_trailerlen); ++ wifi_mac_add_extended_chanswitch(bo->bo_extchanswitch,sta); ++ bo->bo_chanswitch_trailerlen += WIFINET_EXTCHANSWITCHANN_BYTES; ++ bo->bo_tim_trailerlen += WIFINET_EXTCHANSWITCHANN_BYTES; ++ bo->bo_extchanswitch_trailerlen += WIFINET_EXTCHANSWITCHANN_BYTES; ++ bo->bo_appie_buf += WIFINET_EXTCHANSWITCHANN_BYTES; ++ bo->bo_ch_sw_wrp += WIFINET_EXTCHANSWITCHANN_BYTES; ++ bo->bo_wme += WIFINET_EXTCHANSWITCHANN_BYTES; ++ if (bo->bo_erp) ++ bo->bo_erp += WIFINET_EXTCHANSWITCHANN_BYTES; ++ ++ os_skb_put(skb, WIFINET_EXTCHANSWITCHANN_BYTES); ++ } ++ ++ /*add CHAN_SWITCH_WRAP ie*/ ++ chswwrp_len += (2 + WIFINET_WIDEBANDCHANSW_BYTES); ++ memmove(bo->bo_ch_sw_wrp + chswwrp_len, ++ bo->bo_ch_sw_wrp, bo->bo_chswwrp_trailerlen); ++ wifi_mac_add_chansw_wrapper(bo->bo_ch_sw_wrp,sta); ++ bo->bo_chanswitch_trailerlen += chswwrp_len; ++ bo->bo_tim_trailerlen += chswwrp_len; ++ bo->bo_chswwrp_trailerlen += chswwrp_len; ++ bo->bo_extchanswitch_trailerlen += chswwrp_len; ++ bo->bo_appie_buf += chswwrp_len; ++ os_skb_put(skb, chswwrp_len); ++ } ++} ++ ++void wifi_mac_set_vsdb_task(struct wifi_mac *wifimac, struct wlan_net_vif *wnet_vif, enum VsdbState state) ++{ ++ if (wifimac == NULL) { ++ ERROR_DEBUG_OUT("wifimac is null\n"); ++ return; ++ } ++ ++ if (wnet_vif == NULL) { ++ ERROR_DEBUG_OUT("wnet_vif is null\n"); ++ return; ++ } ++ ++ if ((state >= VSDB_STATE_MAX) || (state < 0) ) { ++ ERROR_DEBUG_OUT("state:%d error\n",state); ++ return; ++ } ++ ++ wifimac->wm_vsdb_sate = state; ++ AML_OUTPUT("vid:%d, enable:%d\n", wnet_vif->wnet_vif_id, state); ++ wifi_mac_add_work_task(wifimac, wifi_mac_set_vsdb, NULL,(SYS_TYPE)wifimac, 0, state, (SYS_TYPE)wnet_vif, 0); ++} diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_beacon.h b/drivers/net/wireless/w1/vmac/wifi_mac_beacon.h new file mode 100644 -index 000000000000..d4362c3c65c4 +index 0000000000000000000000000000000000000000..3955c1ba0694677a75b2505bf1a3b8ac8ededc5e --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_beacon.h -@@ -0,0 +1,30 @@ +@@ -0,0 +1,33 @@ +/* + **************************************************************************************** + * @@ -81277,14 +82188,17 @@ index 000000000000..d4362c3c65c4 +void wifi_mac_process_beacon_miss_ex(SYS_TYPE arg); +int wifi_mac_set_beacon_miss_ex(struct wlan_net_vif *wnet_vif, unsigned char enable, int period); +void wifi_mac_set_beacon_miss(SYS_TYPE param1, SYS_TYPE param2,SYS_TYPE param3, SYS_TYPE param4,SYS_TYPE param5); -+void wifi_mac_set_vsdb(SYS_TYPE param1, SYS_TYPE param2,SYS_TYPE param3, SYS_TYPE param4,SYS_TYPE param5); -+ ++void wifi_mac_set_vsdb(SYS_TYPE param1, SYS_TYPE param2, SYS_TYPE param3, SYS_TYPE param4, SYS_TYPE param5); ++void wifi_mac_beacon_update_csaie(struct wifi_station *sta, ++ struct wifi_mac_beacon_offsets *bo, struct sk_buff *skb, struct wifi_channel *switch_chan); ++void wifi_mac_set_vsdb_task(struct wifi_mac *wifimac, struct wlan_net_vif *wnet_vif, enum VsdbState state); ++void wifi_mac_set_vsdb_task(struct wifi_mac *wifimac, struct wlan_net_vif *wnet_vif, enum VsdbState state); diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_chan.c b/drivers/net/wireless/w1/vmac/wifi_mac_chan.c new file mode 100644 -index 000000000000..5b909b551fac +index 0000000000000000000000000000000000000000..08f9f30ebef168e85826bf6e2667c3158f5791e5 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_chan.c -@@ -0,0 +1,1493 @@ +@@ -0,0 +1,1697 @@ +#include "wifi_mac_com.h" +#include "wifi_hal_cmd.h" + @@ -81614,7 +82528,7 @@ index 000000000000..5b909b551fac +}; + +struct country_chan_plan country_chan_plan_list[] = { -+ /* 0x00 */ {17, {81,82,83,84,115,116,117,118,119,120,121,122,123,125,126,127,128}, 0xff, DFS_5G_B2|DFS_5G_B3|DFS_5G_B4|PASSIVE_2G_12_14, TX_POWER_DEFAULT}, //Worldwide ++ /* 0x00 */ {17, {81,82,83,84,115,116,117,118,119,120,121,122,123,125,126,127,128}, 0xff, DFS_5G_B2|DFS_5G_B3|PASSIVE_2G_12_14, TX_POWER_DEFAULT}, //Worldwide + /* 0x01 */ {13, {81,83,84,115,116,117,118,119,120,125,126,127,128,0,0,0,0}, 0x00, DFS_5G_B2, TX_POWER_SRRC}, //China + /* 0x02 */ {16, {81,83,84,115,116,117,118,119,120,121,122,123,125,126,127,128,0}, 0x01, DFS_5G_B2|DFS_5G_B3, TX_POWER_FCC}, //United States of America + /* 0x03 */ {14, {81,83,84,115,116,117,118,119,120,121,122,123,125,128,0,0,0}, 0x02, DFS_5G_B2|DFS_5G_B3, TX_POWER_CE}, //Europe @@ -81893,6 +82807,35 @@ index 000000000000..5b909b551fac + {"ZW", 0x16} /* Zimbabwe */ +}; + ++struct country_chan_mapping southamerica_country[] = { ++ {"AR", 0x14}, /* Argentina */ ++ {"BO", 0x0E}, /* Bolivia */ ++ {"BR", 0x0C}, /* Brazil */ ++ {"CL", 0x01}, /* Chile */ ++ {"CO", 0x07}, /* Colombia */ ++ {"EC", 0x0C}, /* Ecuador */ ++ {"FK", 0x04}, /* Falkland Islands (Islas Malvinas) (UK) */ ++ {"GF", 0x04}, /* French Guiana */ ++ {"GY", 0x00}, /* Guyana */ ++ {"PY", 0x02}, /* Paraguay */ ++ {"PE", 0x10}, /* Peru */ ++ {"SR", 0x00}, /* Suriname */ ++ {"UY", 0x0A}, /* Uruguay */ ++ {"VE", 0x0E}, /* Venezuela */ ++}; ++ ++unsigned char if_southamerica_country(unsigned char *countrycode) { ++ unsigned char index; ++ ++ for (index = 0; index < (sizeof(southamerica_country) / sizeof(southamerica_country[0])); index++) { ++ if ((southamerica_country[index].country[0] == countrycode[0]) ++ && (southamerica_country[index].country[1] == countrycode[1])) { ++ return index + 1; ++ } ++ } ++ ++ return 0; ++} + +static int wifi_mac_get_pos(struct wifi_channel in[], int a, int b) +{ @@ -81932,7 +82875,7 @@ index 000000000000..5b909b551fac + return i; +} + -+void wifi_mac_chan_order(struct wifi_channel in[], int a, int b) ++static void wifi_mac_chan_order(struct wifi_channel in[], int a, int b) +{ + int pos = 0; + if (a < b) @@ -81984,7 +82927,7 @@ index 000000000000..5b909b551fac + return 0; +} + -+void wifi_mac_select_chan_from_global(int country_code, int sub_set[], int num,struct wifi_mac *wifimac) ++static void wifi_mac_select_chan_from_global(int country_code, int sub_set[], int num,struct wifi_mac *wifimac) +{ + int i = 0; + int j = 0; @@ -82052,17 +82995,17 @@ index 000000000000..5b909b551fac + wifi_mac_chan_order(wifimac->wm_channels, 0, wifimac->wm_nchans - 1); + +#if 0 -+ printk("wifimac->wm_nchans:%d\n", wifimac->wm_nchans); ++ pr_debug("wifimac->wm_nchans:%d\n", wifimac->wm_nchans); + for (i = 0; i < wifimac->wm_nchans; ++i) { -+ //printk("chan_cfreq1:%d\n", wifimac->wm_channels[i].chan_cfreq1); -+ //printk("chan_bw:%d\n", wifimac->wm_channels[i].chan_bw); -+ printk("chan_pri_num:%d\n", wifimac->wm_channels[i].chan_pri_num); ++ //pr_debug("chan_cfreq1:%d\n", wifimac->wm_channels[i].chan_cfreq1); ++ //pr_debug("chan_bw:%d\n", wifimac->wm_channels[i].chan_bw); ++ pr_debug("chan_pri_num:%d\n", wifimac->wm_channels[i].chan_pri_num); + } -+ printk("i is %d\n", i); ++ pr_debug("i is %d\n", i); +#endif +} + -+void wifi_mac_mark_dfs_channel_ex(int country_code, struct wifi_mac *wifimac, int chan_num) ++static void wifi_mac_mark_dfs_channel_ex(int country_code, struct wifi_mac *wifimac, int chan_num) +{ + int i = 0; + int chan_pri_num = 0; @@ -82078,28 +83021,28 @@ index 000000000000..5b909b551fac + || ((IS_5G_BAND3(chan_pri_num)) && (dfs_chan_flag & DFS_5G_B3)) + || ((IS_5G_BAND4(chan_pri_num)) && (dfs_chan_flag & DFS_5G_B4)) + || ((chan_pri_num >= 12 && chan_pri_num <= 14) && (dfs_chan_flag & PASSIVE_2G_12_14))) { -+// printk("%s mark channel %d \n", __func__, chan_pri_num); ++// pr_debug("%s mark channel %d \n", __func__, chan_pri_num); + wifimac->wm_channels[i].chan_flags |= WIFINET_CHAN_DFS; + } + } + } else { + for (i = 0; i < wifimac->wm_nchans; i++) { + if (wifimac->wm_channels[i].chan_pri_num == chan_num) { -+// printk("%s mark channel %d \n", __func__,wifimac->wm_channels[i].chan_pri_num); ++// pr_debug("%s mark channel %d \n", __func__,wifimac->wm_channels[i].chan_pri_num); + wifimac->wm_channels[i].chan_flags |= WIFINET_CHAN_DFS; + } + } + } +} + -+void wifi_mac_unmark_dfs_channel_ex(int country_code, struct wifi_mac *wifimac, int chan_num) ++static void wifi_mac_unmark_dfs_channel_ex(int country_code, struct wifi_mac *wifimac, int chan_num) +{ + int i = 0; + + for (i = 0; i < wifimac->wm_nchans; i++) { + if (( chan_num == 0 && (wifimac->wm_channels[i].chan_flags & WIFINET_CHAN_DFS) ) + || (chan_num != 0 && (wifimac->wm_channels[i].chan_pri_num == chan_num)) ){ -+// printk("%s UNmark channel %d \n", __func__,wifimac->wm_channels[i].chan_pri_num); ++// pr_debug("%s UNmark channel %d \n", __func__,wifimac->wm_channels[i].chan_pri_num); + wifimac->wm_channels[i].chan_flags &= ~WIFINET_CHAN_DFS; + } + } @@ -82113,7 +83056,7 @@ index 000000000000..5b909b551fac + + for (i = 0; i < wifimac->wm_nchans; i++) { + if (wifimac->wm_channels[i].chan_pri_num == chan_num && (wifimac->wm_channels[i].chan_flags & WIFINET_CHAN_DFS)) { -+// printk("%s is dfs channel %d \n", __func__,wifimac->wm_channels[i].chan_pri_num); ++// pr_debug("%s is dfs channel %d \n", __func__,wifimac->wm_channels[i].chan_pri_num); + WIFI_CHANNEL_UNLOCK(wifimac); + return 1; + } @@ -82146,7 +83089,7 @@ index 000000000000..5b909b551fac + + if ((wnet_vif->vm_opmode == WIFINET_M_STA) && (wifimac->wm_nrunning == 1)) { + if (wifi_mac_if_dfs_channel(wifimac, wnet_vif->vm_curchan->chan_pri_num) == 1) { -+ printk("current channel %d is dfs channel \n", wnet_vif->vm_curchan->chan_pri_num); ++ pr_debug("current channel %d is dfs channel \n", wnet_vif->vm_curchan->chan_pri_num); + wnet_vif->vm_chan_roaming_scan_flag = 0; + wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN, 0); + } @@ -82333,20 +83276,20 @@ index 000000000000..5b909b551fac + return false; +} + -+struct wifi_channel * wifi_mac_scan_sta_get_ap_channel(struct wlan_net_vif *wnet_vif, struct wifi_mac_scan_param *sp) ++struct wifi_channel * wifi_mac_scan_sta_get_ap_channel(struct wlan_net_vif *wnet_vif, ++ unsigned char chan, unsigned char *htinfoie, unsigned char *htcapie, unsigned char *vht_optie) +{ -+ unsigned char *htinfoie = sp->htinfo; -+ unsigned char *htcapie = sp->htcap; -+ unsigned char chan = sp->chan; -+ struct wifi_mac_ie_htinfo *xhtinfo = (struct wifi_mac_ie_htinfo*)htinfoie; + struct wifi_mac_ie_htcap *xhtcap =(struct wifi_mac_ie_htcap *)htcapie; ++ struct wifi_mac_ie_htinfo *xhtinfo = (struct wifi_mac_ie_htinfo*)htinfoie; ++ struct wifi_mac_ie_vht_opt *vht_opt_ie = (struct wifi_mac_ie_vht_opt *)vht_optie; ++ + struct wifi_mac_ie_htcap_cmn *htcap = NULL; -+ int htcapval = 0; + struct wifi_mac_ie_htinfo_cmn *htinfo = NULL; -+ struct wifi_mac *wifimac = wnet_vif->vm_wmac; -+ struct wifi_mac_ie_vht_opt *vht_opt_ie = (struct wifi_mac_ie_vht_opt *)sp->vht_opt; ++ ++ int htcapval = 0; + int center_chan = 0, bw = 0; + static struct wifi_channel *apchan =NULL; ++ struct wifi_mac *wifimac = wnet_vif->vm_wmac; + + if (xhtinfo != NULL) + { @@ -82358,8 +83301,8 @@ index 000000000000..5b909b551fac + htcapval = le16toh(htcap->hc_cap); + } + -+ DPRINTF(AML_DEBUG_BWC, "%s(%d) %s, chan %d htinfo %p,chwidth %x, htcapval 0x%x \n", __func__, __LINE__, -+ ssidie_sprintf(sp->ssid), sp->chan, htinfo, htinfo?htinfo->hi_txchwidth : 0, htcapval); ++ DPRINTF(AML_DEBUG_BWC, "%s(%d), chan_num:%d, htinfo:%p, txchwidth:%d, htcapval:0x%x\n", ++ __func__, __LINE__, chan, htinfo, htinfo?htinfo->hi_txchwidth : 0, htcapval); + + if ((htinfo != NULL) && (htinfo->hi_txchwidth == WIFINET_HTINFO_TXWIDTH_2040)) + { @@ -82497,7 +83440,7 @@ index 000000000000..5b909b551fac + support_num = country_chan_plan_list[support_index].support_class_num; + support_ptr = country_chan_plan_list[support_index].support_class; + -+ printk("%s(%d) country code 0x%x, support num %d\n", __func__, __LINE__, countrycode_ex, support_num); ++ pr_debug("%s(%d) country code 0x%x, support num %d\n", __func__, __LINE__, countrycode_ex, support_num); + wifi_mac_update_chan_list_by_country(countrycode_ex,support_ptr, support_num, wifimac); + + for(i= 0; i < wifimac->wm_nchans; i++) { @@ -82538,8 +83481,9 @@ index 000000000000..5b909b551fac + struct wifi_mac *wifimac = (struct wifi_mac * )param1; + struct wifi_channel *wnet_vif_chan = (struct wifi_channel * )param2; + struct wlan_net_vif *wnet_vif = (struct wlan_net_vif *)param3; ++ unsigned char channel_switch_flag = (unsigned char)param4; + -+ wifi_mac_ChangeChannel(wifimac, wnet_vif_chan, 3, wnet_vif->wnet_vif_id, wnet_vif->vm_opmode); ++ wifi_mac_ChangeChannel(wifimac, wnet_vif_chan, channel_switch_flag, wnet_vif->wnet_vif_id, wnet_vif->vm_opmode); +} + +struct wifi_channel * wifi_mac_get_wm_chan (struct wifi_mac *wifimac) @@ -82555,12 +83499,13 @@ index 000000000000..5b909b551fac + } +} + -+int wifi_mac_set_wnet_vif_channel(struct wlan_net_vif *wnet_vif, int chan, int bw, int center_chan) ++int wifi_mac_set_wnet_vif_channel(struct wlan_net_vif *wnet_vif, int chan, ++ int bw, int center_chan, unsigned char switch_flag) +{ + struct wifi_mac *wifimac = wnet_vif->vm_wmac; + struct wifi_channel * c = NULL; + -+ printk("%s(%d)\n", __func__, __LINE__); ++ pr_debug("%s(%d)\n", __func__, __LINE__); + c = wifi_mac_find_chan(wifimac, chan, bw, center_chan); + + if (c == NULL) { @@ -82569,11 +83514,14 @@ index 000000000000..5b909b551fac + return false; + } + ++ wnet_vif->vm_curchan = c; ++ + DPRINTF(AML_DEBUG_ERROR, "%s(%d),chan_pri_num =%d, chan_cfreq1 =%d,chan_flags =0x%x\n", + __func__,__LINE__, c->chan_pri_num, c->chan_cfreq1, c->chan_flags); -+ wnet_vif->vm_curchan = c; ++ + wifi_mac_add_work_task(wnet_vif->vm_wmac, wifi_mac_set_wnet_vif_chan_ex, NULL, -+ (SYS_TYPE)(wnet_vif->vm_wmac), (SYS_TYPE)c, (SYS_TYPE)wnet_vif, 0, 0); ++ (SYS_TYPE)(wnet_vif->vm_wmac), (SYS_TYPE)c, (SYS_TYPE)wnet_vif, (SYS_TYPE)switch_flag, 0); ++ + return true; +} + @@ -82598,6 +83546,7 @@ index 000000000000..5b909b551fac + struct wifi_mac *wifimac = wnet_vif->vm_wmac; + struct drv_private* drv_priv = wifimac->drv_priv; + struct wlan_net_vif *selected_wnet_vif = NULL; ++ struct wlan_net_vif *p2p_vmac = wifimac->drv_priv->drv_wnet_vif_table[NET80211_P2P_VMAC]; + + if (wifimac->wm_nrunning > 1) + { @@ -82631,7 +83580,16 @@ index 000000000000..5b909b551fac + if ((selected_wnet_vif->vm_curchan != WIFINET_CHAN_ERR) && (wifimac->wm_curchan != selected_wnet_vif->vm_curchan)) { + DPRINTF(AML_DEBUG_SCAN, "%s vid:%d, prichan:%d, bw:%d\n", __func__, selected_wnet_vif->wnet_vif_id, + selected_wnet_vif->vm_curchan->chan_pri_num, selected_wnet_vif->vm_curchan->chan_bw); -+ wifi_mac_ChangeChannel(wifimac, selected_wnet_vif->vm_curchan, 1, selected_wnet_vif->wnet_vif_id, selected_wnet_vif->vm_opmode); ++ if (wifimac->wm_flags & WIFINET_F_SCAN ++ && IS_APSTA_CONCURRENT(aml_wifi_get_con_mode()) ++ && concurrent_check_vmac_is_AP(wifimac) ++ && (wnet_vif->vm_opmode == WIFINET_M_STA) ++ && (p2p_vmac->vm_state == WIFINET_S_CONNECTED) ++ && concurrent_check_is_vmac_same_pri_channel(wifimac)) { ++ wifi_mac_ChangeChannel(wifimac, selected_wnet_vif->vm_curchan, 1, selected_wnet_vif->wnet_vif_id, p2p_vmac->vm_opmode); ++ } else { ++ wifi_mac_ChangeChannel(wifimac, selected_wnet_vif->vm_curchan, 1, selected_wnet_vif->wnet_vif_id, selected_wnet_vif->vm_opmode); ++ } + } + + wifi_mac_set_channel_rssi(wifimac, (unsigned char)(selected_wnet_vif->vm_mainsta->sta_avg_bcn_rssi)); @@ -82651,9 +83609,10 @@ index 000000000000..5b909b551fac + tasklet_schedule(&wifimac->drv_priv->ampdu_tasklet); +} + -+void wifi_mac_restore_wnet_vif_channel_task_ex(void * data) ++static void wifi_mac_restore_wnet_vif_channel_task_ex(SYS_TYPE param1, SYS_TYPE param2, SYS_TYPE param3, ++ SYS_TYPE param4, SYS_TYPE param5) +{ -+ struct wlan_net_vif *wnet_vif = (struct wlan_net_vif *)data; ++ struct wlan_net_vif *wnet_vif = (struct wlan_net_vif *)param1; + wifi_mac_restore_wnet_vif_channel(wnet_vif); +} + @@ -82717,7 +83676,7 @@ index 000000000000..5b909b551fac + struct drv_private *drv_priv = drv_get_drv_priv(); + + if (txpoweplan == drv_priv->drv_config.cfg_txpoweplan) { -+ printk("not need to update tx power plan(%d)\n", txpoweplan); ++ pr_debug("not need to update tx power plan(%d)\n", txpoweplan); + } else { + drv_priv->drv_config.cfg_txpoweplan = txpoweplan; + wifi_mac_set_tx_power_coefficient(drv_priv, wifimac->wm_curchan, txpoweplan); @@ -82778,12 +83737,171 @@ index 000000000000..5b909b551fac + + return 0; +} ++ ++unsigned char wifi_mac_p2p_home_channel_enabled(struct wlan_net_vif *wnet_vif) ++{ ++ struct wifi_mac *wifimac = wnet_vif->vm_wmac; ++ ++ return ((wnet_vif->vm_p2p->p2p_role == NET80211_P2P_ROLE_GO) ++ && (wifimac->wm_p2p_home_channel != 0)); ++} ++ ++bool wifi_mac_get_chandef(struct wifi_channel *vmac_chan, struct cfg80211_chan_def *chandef) ++{ ++ unsigned int index = 0; ++ ++ if (vmac_chan == WIFINET_CHAN_ERR) ++ { ++ ERROR_DEBUG_OUT("vmac_chan is WIFINET_CHAN_ERR\n"); ++ return false; ++ } ++ ++ if (vmac_chan->chan_pri_num >= 1 && vmac_chan->chan_pri_num <= 14) { ++ chandef->chan = &aml_2ghz_channels[vmac_chan->chan_pri_num - 1]; ++ } else if (vmac_chan->chan_pri_num >= 36) { ++ for (index = 0; index < AML_5G_CHANNELS_NUM; index++) { ++ if (aml_5ghz_channels[index].hw_value == vmac_chan->chan_pri_num) { ++ chandef->chan = &aml_5ghz_channels[index]; ++ break; ++ } ++ } ++ } ++ ++ if (!chandef->chan) { ++ ERROR_DEBUG_OUT("not find ieee chan pri_num:%d\n", vmac_chan->chan_pri_num); ++ return false; ++ } ++ ++ if (vmac_chan->chan_bw == WIFINET_BWC_WIDTH20) { ++ chandef->width = NL80211_CHAN_WIDTH_20; ++ } else if (vmac_chan->chan_bw == WIFINET_BWC_WIDTH40) { ++ chandef->width = NL80211_CHAN_WIDTH_40; ++ } else if (vmac_chan->chan_bw == WIFINET_BWC_WIDTH80) { ++ chandef->width = NL80211_CHAN_WIDTH_80; ++ } else { ++ ERROR_DEBUG_OUT("station chan_bw do not support\n"); ++ } ++ ++ chandef->center_freq1 = vmac_chan->chan_cfreq1; ++ ++ return true; ++} ++ ++unsigned char wifi_mac_get_operation_class(struct cfg80211_chan_def chandef) ++{ ++ unsigned char vht_opclass = 0; ++ unsigned int freq = chandef.center_freq1; ++ unsigned char ret = 0; ++ ++ if (freq >= 2412 && freq <= 2472) { ++ if (chandef.width > NL80211_CHAN_WIDTH_40) ++ return ret; ++ ++ /* 2.407 GHz, channels 1..13 */ ++ if (chandef.width == NL80211_CHAN_WIDTH_40) { ++ if (freq > chandef.chan->center_freq) ++ ret = 83; /* HT40+ */ ++ else ++ ret = 84; /* HT40- */ ++ } else { ++ ret = 81; ++ } ++ ++ return ret; ++ } ++ ++ if (freq == 2484) { ++ /* channel 14 is only for IEEE 802.11b */ ++ if (chandef.width != NL80211_CHAN_WIDTH_20_NOHT) ++ return ret; ++ ret = 82; /* channel 14 */ ++ return ret; ++ } ++ ++ /* 5 GHz, channels 36..48 */ ++ if (freq >= 5180 && freq <= 5240) { ++ if (vht_opclass) { ++ ret = vht_opclass; ++ } else if (chandef.width == NL80211_CHAN_WIDTH_40) { ++ if (freq > chandef.chan->center_freq) ++ ret = 116; ++ else ++ ret = 117; ++ } else { ++ ret = 115; ++ } ++ ++ return ret; ++ } ++ ++ /* 5 GHz, channels 52..64 */ ++ if (freq >= 5260 && freq <= 5320) { ++ if (vht_opclass) { ++ ret = vht_opclass; ++ } else if (chandef.width == NL80211_CHAN_WIDTH_40) { ++ if (freq > chandef.chan->center_freq) ++ ret = 119; ++ else ++ ret = 120; ++ } else { ++ ret = 118; ++ } ++ ++ return ret; ++ } ++ ++ /* 5 GHz, channels 100..144 */ ++ if (freq >= 5500 && freq <= 5720) { ++ if (vht_opclass) { ++ ret = vht_opclass; ++ } else if (chandef.width == NL80211_CHAN_WIDTH_40) { ++ if (freq > chandef.chan->center_freq) ++ ret = 122; ++ else ++ ret = 123; ++ } else { ++ ret = 121; ++ } ++ ++ return ret; ++ } ++ ++ /* 5 GHz, channels 149..169 */ ++ if (freq >= 5745 && freq <= 5845) { ++ if (vht_opclass) { ++ ret = vht_opclass; ++ } else if (chandef.width == NL80211_CHAN_WIDTH_40) { ++ if (freq > chandef.chan->center_freq) ++ ret = 126; ++ else ++ ret = 127; ++ } else if (freq <= 5805) { ++ ret = 124; ++ } else { ++ ret = 125; ++ } ++ ++ return ret; ++ } ++ ++ /* 56.16 GHz, channel 1..4 */ ++ if (freq >= 56160 + 2160 * 1 && freq <= 56160 + 2160 * 6) { ++ if (chandef.width >= NL80211_CHAN_WIDTH_40) ++ return ret; ++ ++ ret = 180; ++ return ret; ++ } ++ ++ /* not supported yet */ ++ return ret; ++} diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_chan.h b/drivers/net/wireless/w1/vmac/wifi_mac_chan.h new file mode 100644 -index 000000000000..cd88cb392dbc +index 0000000000000000000000000000000000000000..6e0d710d9fda67f47db69a649d3ee5cbc0e51ba4 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_chan.h -@@ -0,0 +1,39 @@ +@@ -0,0 +1,43 @@ +#ifndef __NET80211_CHAN_H__ +#define __NET80211_CHAN_H__ + @@ -82796,10 +83914,11 @@ index 000000000000..cd88cb392dbc +int wifi_mac_chan_overlapping_map_init(struct wifi_mac *wifimac); +unsigned char wifi_mac_chan_num_avail (struct wifi_mac *wifimac, unsigned char channum); +int wifi_mac_recv_bss_intol_channelCheck(struct wifi_mac *wifimac, struct wifi_mac_ie_intolerant_report *intol_ie); -+struct wifi_channel * wifi_mac_scan_sta_get_ap_channel(struct wlan_net_vif *wnet_vif, struct wifi_mac_scan_param *sp); ++struct wifi_channel * wifi_mac_scan_sta_get_ap_channel(struct wlan_net_vif *wnet_vif, ++ unsigned char chan, unsigned char *htinfoie, unsigned char *htcapie, unsigned char *vht_optie); +unsigned int wifi_mac_mhz2chan(unsigned int freq); +struct wifi_channel * wifi_mac_find_chan(struct wifi_mac *wifimac, int chan, int bw, int center_chan); -+int wifi_mac_set_wnet_vif_channel(struct wlan_net_vif *wnet_vif, int chan, int bw, int center_chan); ++int wifi_mac_set_wnet_vif_channel(struct wlan_net_vif *wnet_vif, int chan, int bw, int center_chan,unsigned char switch_flag); +void wifi_mac_set_wnet_vif_chan_ex(SYS_TYPE param1,SYS_TYPE param2,SYS_TYPE param3, SYS_TYPE param4,SYS_TYPE param5); +struct wifi_channel * wifi_mac_get_wm_chan (struct wifi_mac *wifimac); +struct wifi_channel * wifi_mac_get_connect_wnet_vif_channel(struct wlan_net_vif *wnet_vif); @@ -82821,11 +83940,14 @@ index 000000000000..cd88cb392dbc +int update_tx_power_coefficient_plan(int tx_power_plan, unsigned short pwr_coefficient[]); +int update_tx_power_band(int tx_power_plan, unsigned short pwr_value[]); +int wifi_mac_find_80M_channel_center_chan(int chan); -+ ++unsigned char if_southamerica_country(unsigned char *countrycode); ++unsigned char wifi_mac_p2p_home_channel_enabled(struct wlan_net_vif *wnet_vif); ++bool wifi_mac_get_chandef(struct wifi_channel *vmac_chan, struct cfg80211_chan_def *chandef); ++unsigned char wifi_mac_get_operation_class(struct cfg80211_chan_def chandef); +#endif//__NET80211_CHAN_H__ diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_com.h b/drivers/net/wireless/w1/vmac/wifi_mac_com.h new file mode 100644 -index 000000000000..1b778634f583 +index 0000000000000000000000000000000000000000..aa63500e28683b47ea798f7c0315ed3dc9787530 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_com.h @@ -0,0 +1,91 @@ @@ -82908,24 +84030,24 @@ index 000000000000..1b778634f583 + +#define WIFINET_DPRINTF(_m, _fmt, ...) do { \ + if (wnet_vif->vm_debug & (_m)) \ -+ printk("<%s> %s %d "_fmt"\n", wnet_vif->vm_ndev->name ,__func__, __LINE__, __VA_ARGS__); \ ++ pr_debug("<%s> %s %d "_fmt"\n", wnet_vif->vm_ndev->name ,__func__, __LINE__, __VA_ARGS__); \ + } while (0) +#define WIFINET_DPRINTF_MACADDR( _m, _mac, _fmt, ...) do { \ + if (wnet_vif->vm_debug & (_m)) \ -+ printk("<%s> %s %d mac[%s] "_fmt"\n",wnet_vif->vm_ndev->name , __func__, __LINE__,ether_sprintf(_mac),__VA_ARGS__); \ ++ pr_debug("<%s> %s %d mac[%s] "_fmt"\n",wnet_vif->vm_ndev->name , __func__, __LINE__,ether_sprintf(_mac),__VA_ARGS__); \ + } while (0) +#define WIFINET_DPRINTF_STA( _m, _sta, _fmt, ...)do { \ + if ((_sta)->sta_wnet_vif->vm_debug & (_m)) \ -+ printk("<%s> %s %d mac[%s] "_fmt"\n", (_sta)->sta_wnet_vif->vm_ndev->name , __func__, __LINE__, ether_sprintf((_sta)->sta_macaddr),__VA_ARGS__); \ ++ pr_debug("<%s> %s %d mac[%s] "_fmt"\n", (_sta)->sta_wnet_vif->vm_ndev->name , __func__, __LINE__, ether_sprintf((_sta)->sta_macaddr),__VA_ARGS__); \ + } while (0) + +#endif //_NET80211_COMMON_H_ diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_concurrent.c b/drivers/net/wireless/w1/vmac/wifi_mac_concurrent.c new file mode 100644 -index 000000000000..09415c51cf04 +index 0000000000000000000000000000000000000000..b4d82d92c2a8548cf66256c351ff2ac4f9a6d438 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_concurrent.c -@@ -0,0 +1,263 @@ +@@ -0,0 +1,387 @@ +#include "wifi_mac_com.h" + +#ifdef CONFIG_CONCURRENT_MODE @@ -82934,6 +84056,7 @@ index 000000000000..09415c51cf04 + wifimac->wm_vsdb_slot = CONCURRENT_SLOT_NONE; + wifimac->wm_vsdb_flags = 0; + wifimac->vsdb_mode_set_noa_enable = 0; ++ os_timer_ex_initialize(&wifimac->wm_csa_trigger_timer, 10000, csa_trigger_timeout, wifimac); +} + +static void concurrent_change_channel_timeout_ex(SYS_TYPE param1, @@ -83038,7 +84161,13 @@ index 000000000000..09415c51cf04 +void concurrent_vsdb_do_channel_change(void * data) +{ + struct wifi_mac *wifimac = (struct wifi_mac *)data; -+ wifimac->wm_vsdb_flags &= ~CONCURRENT_NOTIFY_AP_SUCCESS; ++ ++ if (wifimac->wm_vsdb_flags & CONCURRENT_NOTIFY_AP_SUCCESS) { ++ wifimac->wm_vsdb_flags &= ~CONCURRENT_NOTIFY_AP_SUCCESS; ++ } ++ if (wifimac->wm_vsdb_flags & CONCURRENT_AP_SWITCH_CHANNEL) { ++ wifimac->wm_vsdb_flags &= ~CONCURRENT_AP_SWITCH_CHANNEL; ++ } + wifi_mac_add_work_task(wifimac, concurrent_vsdb_do_channel_change_ex,NULL,(SYS_TYPE)data,0,0,0,0); +} + @@ -83052,6 +84181,12 @@ index 000000000000..09415c51cf04 + + DPRINTF(AML_DEBUG_CONNECT, "%s, slot:%d\n", __func__, wifimac->wm_vsdb_slot); + ++ if (wifimac->wm_vsdb_sate == VSDB_STATE_DISABLE) { ++ DPRINTF(AML_DEBUG_CONNECT, "slot:%d flag:%x\n", wifimac->wm_vsdb_slot, wifimac->wm_vsdb_flags); ++ wifimac->wm_vsdb_flags &= ~CONCURRENT_CHANNEL_SWITCH; ++ return; ++ } ++ + if ((wifimac->wm_nrunning > 1) && (wifimac->wm_vsdb_flags & CONCURRENT_CHANNEL_SWITCH)) { + if (wifimac->wm_vsdb_slot == CONCURRENT_SLOT_STA) { + wifi_mac_scan_notify_leave_or_back(main_vmac, 1); @@ -83064,8 +84199,17 @@ index 000000000000..09415c51cf04 + wifimac->drv_priv->drv_ops.drv_set_is_mother_channel(wifimac->drv_priv, p2p_vmac->wnet_vif_id, 1); + wifimac->wm_vsdb_flags |= CONCURRENT_NOTIFY_AP; + } ++ else if (IS_APSTA_CONCURRENT(aml_wifi_get_con_mode()) && !concurrent_check_is_vmac_same_pri_channel(wifimac)) { ++ if (drv_priv->hal_priv->hal_ops.hal_tx_empty()) { ++ concurrent_vsdb_do_channel_change(wifimac); ++ } ++ else { ++ wifimac->wm_vsdb_flags |= CONCURRENT_AP_SWITCH_CHANNEL; ++ } ++ } ++ } else if (wifimac->wm_vsdb_slot == CONCURRENT_SLOT_NONE) { ++ wifimac->wm_vsdb_flags &= ~CONCURRENT_CHANNEL_SWITCH; + } -+ + } else if ((wifimac->wm_nrunning < 2) && (wifimac->wm_vsdb_flags & CONCURRENT_CHANNEL_SWITCH)) { + wifimac->wm_vsdb_flags = 0; + } @@ -83081,6 +84225,16 @@ index 000000000000..09415c51cf04 + struct wifi_mac_scan_state *ss = wifimac->wm_scan; + struct drv_private *drv_priv = wifimac->drv_priv; + struct wlan_net_vif *p2p_vmac = drv_priv->drv_wnet_vif_table[NET80211_P2P_VMAC]; ++ ++ AML_OUTPUT("vm_nruning:%d slot:%d vsdb_flag:%x p2p_role:%d noa_enable:%d nego_state:%d\n",wifimac->wm_nrunning, ++ wifimac->wm_vsdb_slot,wifimac->wm_vsdb_flags,p2p_vmac->vm_p2p->p2p_role,wifimac->vsdb_mode_set_noa_enable, ++ p2p_vmac->vm_p2p->p2p_negotiation_state); ++ ++ if (wifimac->wm_vsdb_sate == VSDB_STATE_DISABLE) { ++ DPRINTF(AML_DEBUG_CONNECT, "slot:%d flag:%x\n", wifimac->wm_vsdb_slot, wifimac->wm_vsdb_flags); ++ return; ++ } ++ + if ((wifimac->wm_nrunning > 1 && wifimac->wm_vsdb_slot == CONCURRENT_SLOT_P2P && p2p_vmac->vm_p2p->p2p_role == NET80211_P2P_ROLE_GO) || + (wifimac->wm_vsdb_slot == CONCURRENT_SLOT_STA && wifimac->vsdb_mode_set_noa_enable == 1)) { + if (p2p_vmac->vm_p2p->p2p_negotiation_state != NET80211_P2P_STATE_GO_COMPLETE) { @@ -83106,7 +84260,7 @@ index 000000000000..09415c51cf04 + return; + } + -+ //printk("%s\n", __func__); ++ //pr_debug("%s\n", __func__); + if ((wifimac->wm_nrunning > 1) + && (time_after(jiffies, wifimac->wm_vsdb_switch_time + (WIFINET_SCAN_DEFAULT_INTERVAL * HZ / 1000)) + || (wifimac->wm_vsdb_switch_time == 0))) { @@ -83116,7 +84270,7 @@ index 000000000000..09415c51cf04 + wifimac->wm_vsdb_switch_time = jiffies; + + } else { -+ //printk("not right time\n"); ++ //pr_debug("not right time\n"); + } + + if ((wifimac->wm_vsdb_slot == CONCURRENT_SLOT_P2P) @@ -83125,6 +84279,48 @@ index 000000000000..09415c51cf04 + } + } +} ++ ++//the func is not used yet ++int csa_trigger_timeout(void *data) ++{ ++#ifdef CONFIG_ROKU ++ struct drv_private *drv_priv = NULL; ++ struct wlan_net_vif *p2p_wnet_vif = NULL; ++ struct wlan_net_vif *main_wnet_vif = NULL; ++ struct wifi_mac *wifimac = (struct wifi_mac *)data; ++ struct wifi_channel *switch_chan = NULL; ++ ++ if (wifimac == NULL) { ++ ERROR_DEBUG_OUT("wifimac is NULL\n"); ++ return OS_TIMER_NOT_REARMED; ++ } ++ ++ drv_priv = wifimac->drv_priv; ++ p2p_wnet_vif = drv_priv->drv_wnet_vif_table[NET80211_P2P_VMAC]; ++ main_wnet_vif = drv_priv->drv_wnet_vif_table[NET80211_MAIN_VMAC]; ++ ++ if (IS_APSTA_CONCURRENT(aml_wifi_get_con_mode()) ++ && (main_wnet_vif->vm_state != WIFINET_S_CONNECTED) ++ && (p2p_wnet_vif->vm_opmode == WIFINET_M_HOSTAP) ++ && (p2p_wnet_vif->vm_state == WIFINET_S_CONNECTED)) { ++ AML_OUTPUT("channel switch to p2p_home_channel:%d\n",wifimac->wm_p2p_home_channel); ++ ++ if (wifi_mac_p2p_home_channel_enabled(p2p_wnet_vif)) { ++ switch_chan = wifi_mac_find_chan(wifimac, wifimac->wm_p2p_home_channel, WIFINET_BWC_WIDTH20, wifimac->wm_p2p_home_channel); ++ } else { ++ if (wifi_mac_if_dfs_channel(wifimac, p2p_wnet_vif->vm_curchan->chan_pri_num)) { ++ if (if_southamerica_country(wifimac->wm_country.iso)) { ++ switch_chan = wifi_mac_find_chan(wifimac,149, WIFINET_BWC_WIDTH20, 149); ++ } else { ++ switch_chan = wifi_mac_find_chan(wifimac,36, WIFINET_BWC_WIDTH20, 36); ++ } ++ } ++ } ++ channel_switch_announce_trigger(wifimac, switch_chan); ++ } ++#endif ++ return OS_TIMER_NOT_REARMED; ++} +#endif//CONFIG_CONCURRENT_MODE + +unsigned char concurrent_check_is_vmac_same_pri_channel(struct wifi_mac *wifimac) @@ -83189,12 +84385,62 @@ index 000000000000..09415c51cf04 + return NULL; +} + ++void channel_switch_announce_trigger(struct wifi_mac *wifimac, struct wifi_channel *switch_chan) ++{ ++ unsigned int delay_ms = 0, csa_count = 0; ++ struct drv_private *drv_priv = wifimac->drv_priv; ++ struct wlan_net_vif *p2p_wnet_vif = drv_priv->drv_wnet_vif_table[NET80211_P2P_VMAC]; ++ ++ if (switch_chan == NULL) { ++ ERROR_DEBUG_OUT("switch channel is null!\n"); ++ return; ++ } ++ ++ if (switch_chan->chan_pri_num == 0) { ++ ERROR_DEBUG_OUT("err chan_pri_num is zero!\n"); ++ return; ++ } ++ ++ while ((wifimac->wm_flags & WIFINET_F_DOTH) && (wifimac->wm_flags & WIFINET_F_CHANSWITCH) && (delay_ms < 1000)) { ++ mdelay(1); ++ delay_ms++; ++ } ++ ++ if (p2p_wnet_vif->vm_curchan ++ && (p2p_wnet_vif->vm_curchan->chan_pri_num == switch_chan->chan_pri_num) ++ && (p2p_wnet_vif->vm_curchan->chan_bw == switch_chan->chan_bw)) { ++ AML_OUTPUT("channel:%d, bw:%d, no need trigger csa!\n", switch_chan->chan_pri_num, switch_chan->chan_bw); ++ return; ++ } ++ ++ if ((p2p_wnet_vif->vm_dtim_period > 0) && (p2p_wnet_vif->vm_dtim_period < 5)) { ++ csa_count = p2p_wnet_vif->vm_dtim_period; ++ } else { ++ csa_count = CSA_COUNT; ++ } ++ ++ os_timer_ex_cancel(&wifimac->wm_csa_trigger_timer, CANCEL_NO_SLEEP); ++ ++ AML_OUTPUT("chan_pri_num:%d, bw:%d, csa_count:%d, delay_ms:%d\n", ++ switch_chan->chan_pri_num, switch_chan->chan_bw, csa_count, delay_ms); ++ ++ if (IS_APSTA_CONCURRENT(aml_wifi_get_con_mode()) && concurrent_check_vmac_is_AP(wifimac)) { ++ p2p_wnet_vif->vm_wmac->wm_flags |= WIFINET_F_DOTH; ++ p2p_wnet_vif->vm_wmac->wm_flags |= WIFINET_F_CHANSWITCH; ++ p2p_wnet_vif->vm_wmac->wm_doth_channel = switch_chan->chan_pri_num; ++ p2p_wnet_vif->vm_wmac->wm_doth_tbtt = csa_count; ++ p2p_wnet_vif->csa_target.switch_chan = *switch_chan; ++ if (p2p_wnet_vif->vm_p2p->go_hidden_mode) { ++ p2p_wnet_vif->vm_flags &= ~WIFINET_F_HIDESSID; ++ } ++ } ++} diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_concurrent.h b/drivers/net/wireless/w1/vmac/wifi_mac_concurrent.h new file mode 100644 -index 000000000000..8e9f9781de0c +index 0000000000000000000000000000000000000000..87e0d76a98a7c1bb76fb1512d3834b79d563f610 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_concurrent.h -@@ -0,0 +1,59 @@ +@@ -0,0 +1,60 @@ +#ifndef NET80211_CONCURRENT_H +#define NET80211_CONCURRENT_H + @@ -83247,16 +84493,17 @@ index 000000000000..8e9f9781de0c +void concurrent_vsdb_prepare_change_channel(struct wifi_mac *wifimac); +void concurrent_vsdb_do_channel_change(void * data); +void concurrent_vsdb_init(struct wifi_mac *wifimac); ++int csa_trigger_timeout(void *data); +#endif +unsigned char concurrent_check_is_vmac_same_pri_channel(struct wifi_mac *wifimac); +unsigned char concurrent_check_vmac_is_AP(struct wifi_mac *wifimac); +struct wlan_net_vif *wifi_mac_running_main_wnet_vif(struct wifi_mac *wifimac); +struct wlan_net_vif *wifi_mac_running_wnet_vif(struct wifi_mac *wifimac); -+ ++void channel_switch_announce_trigger(struct wifi_mac *wifimac, struct wifi_channel *switch_chan); +#endif //NET80211_CONCURRENT_H diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_encrypt.c b/drivers/net/wireless/w1/vmac/wifi_mac_encrypt.c new file mode 100644 -index 000000000000..87b40bc035da +index 0000000000000000000000000000000000000000..d2a45e78676b4b90d588ca1544c5bd9ce906af52 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_encrypt.c @@ -0,0 +1,1032 @@ @@ -83314,7 +84561,7 @@ index 000000000000..87b40bc035da + + if (cipher >= WIFINET_CIPHER_MAX) { + wnet_vif->vif_sts.sts_key_type_err++; -+ printk(" %s cipher:%d\n",__func__, cipher); ++ pr_debug(" %s cipher:%d\n",__func__, cipher); + return 0; + } + @@ -83397,13 +84644,13 @@ index 000000000000..87b40bc035da + + if (!cip->wm_setkey(key)) { + wnet_vif->vif_sts.sts_key_drop++; -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + return 0; + } + + if (key->wk_keyix == WIFINET_KEYIX_NONE) { + wnet_vif->vif_sts.sts_key_id_err++; -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + return 0; + } + @@ -83753,7 +85000,7 @@ index 000000000000..87b40bc035da + int hdrlen; + struct sk_buff *skb; + size_t data_len; -+ uint8_t mic[WIFINET_WEP_MICLEN]; ++ uint8_t mic[WIFINET_WEP_MICLEN] = { 0 }; + + wnet_vif->vif_sts.sts_tx_tkip_sw_mic_err++; + @@ -83824,8 +85071,8 @@ index 000000000000..87b40bc035da + wh = (struct wifi_frame *) skb0->data; + + wnet_vif->vif_sts.sts_rx_tkip_sw_mic_err++; -+ // printk(" %s %d \n",__func__,__LINE__); -+ //dump_memory_internel(k->wk_key, WIFINET_KEYBUF_SIZE+WIFINET_MICBUF_SIZE); ++ // pr_debug(" %s %d \n",__func__,__LINE__); ++ //dump_memory_internal(k->wk_key, WIFINET_KEYBUF_SIZE+WIFINET_MICBUF_SIZE); + michael_mic(k->wk_rxmic, + skb0, hdrlen, pktlen - (hdrlen + k->wk_cipher->wm_miclen), + mic); @@ -84294,7 +85541,7 @@ index 000000000000..87b40bc035da + diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_encrypt.h b/drivers/net/wireless/w1/vmac/wifi_mac_encrypt.h new file mode 100644 -index 000000000000..d854a154b4be +index 0000000000000000000000000000000000000000..d854a154b4bec51115ad284875328846b22a2311 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_encrypt.h @@ -0,0 +1,161 @@ @@ -84461,10 +85708,10 @@ index 000000000000..d854a154b4be +#endif /* _NET80211_IEEE80211_CRYPTO_H_ */ diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_if.c b/drivers/net/wireless/w1/vmac/wifi_mac_if.c new file mode 100644 -index 000000000000..76baca821132 +index 0000000000000000000000000000000000000000..ee39572d11457f078d4529bbb1f024cc97b9fbf2 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_if.c -@@ -0,0 +1,4444 @@ +@@ -0,0 +1,4603 @@ +/* + **************************************************************************************** + * @@ -84519,12 +85766,12 @@ index 000000000000..76baca821132 + return &wm_mac; +} + -+unsigned char wifi_mac_get_host_wake_status(void) ++static unsigned char wifi_mac_get_host_wake_status(void) +{ + return host_wake_w1_fail_cnt; +} + -+unsigned char wifi_mac_clear_host_wake_status(void) ++static unsigned char wifi_mac_clear_host_wake_status(void) +{ + host_wake_w1_fail_cnt = 0; + return 0; @@ -84664,7 +85911,7 @@ index 000000000000..76baca821132 + return chan; +} + -+void wifi_mac_rate_nsta_update(void* ieee, void* nsta, int isnew) ++static void wifi_mac_rate_nsta_update(void* ieee, void* nsta, int isnew) +{ + struct wifi_station *sta = (struct wifi_station *)nsta; + @@ -85206,6 +86453,10 @@ index 000000000000..76baca821132 + wh = (struct wifi_frame *)os_skb_data(skbbuf); + is_robust_mgmt = is_robust_management_frame(wh); + ++ if (wifi_mac_is_dpp_frame(skbbuf, sta) == true) { ++ txinfo->b_dpp = 1; ++ } ++ + if ((sta->sta_flags_ext & WIFINET_NODE_MFP) && is_robust_mgmt && sta->pmf_key.wk_keylen) { + if (WIFINET_IS_MULTICAST(wh->i_addr1)) { + if (sta->pmf_key.wk_key_type == WIFINET_CIPHER_AES_CMAC) { @@ -85507,7 +86758,7 @@ index 000000000000..76baca821132 + } +} + -+void wifi_mac_roaming_check( struct wifi_mac *wifimac, struct wifi_station *sta) ++static void wifi_mac_roaming_check( struct wifi_mac *wifimac, struct wifi_station *sta) +{ + static int roaming_cnt = 0; + int roaming_threshold = wifimac->roaming_threshold_5g; @@ -85518,7 +86769,7 @@ index 000000000000..76baca821132 + + if (sta->sta_avg_bcn_rssi < roaming_threshold) { + if (++roaming_cnt > ROAMING_TRIGER_COUNT && time_before((wifimac->wm_lastroaming + (5 * HZ)), jiffies)) { -+ printk("Rssi[%d] < Threshold[%d] trigger roaming \n", sta->sta_avg_bcn_rssi, roaming_threshold); ++ pr_debug("Rssi[%d] < Threshold[%d] trigger roaming \n", sta->sta_avg_bcn_rssi, roaming_threshold); + roaming_cnt = 0; + wifimac->wm_lastroaming = jiffies; + wifi_mac_roaming_trigger(sta->sta_wnet_vif); @@ -85615,7 +86866,7 @@ index 000000000000..76baca821132 + && !WIFINET_ADDR_EQ(sta->sta_bssid, wh->i_addr3)) + { + /*sta send auth to other ap, we shall free this sta buffer, if we have allocated. */ -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + return wifi_mac_input_all(wifimac, skbbuf, rs); + } + @@ -85805,7 +87056,7 @@ index 000000000000..76baca821132 + if (wifimac->wm_curchan != WIFINET_CHAN_ERR && wifimac->wm_curchanmaxpwr == 0) + wifimac->wm_curchanmaxpwr = wifimac->wm_curchan->chan_maxpower; + -+ printk("%s(%d) \n",__func__,__LINE__); ++ pr_debug("%s(%d) \n",__func__,__LINE__); + + chan_dbg(wifimac->wm_curchan, "X8",1332); + if (wifimac->drv_priv->drv_config.cfg_txamsdu) { @@ -85835,7 +87086,7 @@ index 000000000000..76baca821132 +#define AMLWL_IPV4 1 +#define AMLWL_IPV6 2 + -+int aml_notify_ip(struct wifi_station *sta, u8 vif_ctx_id, u8 ip_type, u8 *ip_addr) ++static int aml_notify_ip(struct wifi_station *sta, u8 vif_ctx_id, u8 ip_type, u8 *ip_addr) +{ + if (ip_type != AMLWL_IPV4 && ip_type != AMLWL_IPV6) + return -EINVAL; @@ -85901,7 +87152,7 @@ index 000000000000..76baca821132 + + + -+void wifi_mac_set_ipv6_addr(SYS_TYPE param1, SYS_TYPE param2,SYS_TYPE param3, SYS_TYPE param4,SYS_TYPE param5) ++static void wifi_mac_set_ipv6_addr(SYS_TYPE param1, SYS_TYPE param2,SYS_TYPE param3, SYS_TYPE param4,SYS_TYPE param5) +{ + struct wifi_station *sta = (struct wifi_station *)param1; + unsigned char vif_id = (unsigned char)param2; @@ -86249,7 +87500,7 @@ index 000000000000..76baca821132 +} + + -+unsigned char wifi_mac_tx_init(struct wifi_mac *wifimac) { ++static unsigned char wifi_mac_tx_init(struct wifi_mac *wifimac) { + struct list_head *head = &wifimac->txdesc_freequeue; + struct drv_txdesc *ptxdesc; + int i, bsize; @@ -86279,7 +87530,7 @@ index 000000000000..76baca821132 + return wifimac->drv_priv->drv_ops.tx_init(wifimac->drv_priv, DRV_TXDESC_NUM); +} + -+void wifi_mac_tx_cleanup(struct wifi_mac *wifimac) { ++static void wifi_mac_tx_cleanup(struct wifi_mac *wifimac) { + struct list_head *head = &wifimac->txdesc_freequeue; + + wifimac->drv_priv->drv_ops.tx_cleanup(wifimac->drv_priv); @@ -86335,79 +87586,79 @@ index 000000000000..76baca821132 + + if((ctrl_code & STS_MOD_WMAC) == STS_MOD_WMAC) + { -+ printk("\n--------mac_statistic--------\n"); ++ pr_debug("\n--------mac_statistic--------\n"); + /*vif tx path*/ + if ((ctrl_code & STS_TYP_TX) == STS_TYP_TX) + { + list_for_each_entry(wnet_vif,&wifimac->wm_wnet_vifs,vm_next) + { -+ printk("\n--------vif_id %d--------\n", wnet_vif->wnet_vif_id); ++ pr_debug("\n--------vif_id %d--------\n", wnet_vif->wnet_vif_id); + -+ printk("tx_total_msdu %d\n", wnet_vif->vif_sts.sts_tx_total_msdu); -+ printk("tx_total_out_msdu %d\n", wnet_vif->vif_sts.sts_tx_out_msdu); -+ printk("tx_total_drop_msdu %d\n", wnet_vif->vif_sts.sts_tx_drop_msdu); ++ pr_debug("tx_total_msdu %d\n", wnet_vif->vif_sts.sts_tx_total_msdu); ++ pr_debug("tx_total_out_msdu %d\n", wnet_vif->vif_sts.sts_tx_out_msdu); ++ pr_debug("tx_total_drop_msdu %d\n", wnet_vif->vif_sts.sts_tx_drop_msdu); + -+ printk("\ntx_total_tcp_msdu %d\n", wnet_vif->vif_sts.sts_tx_tcp_msdu); -+ printk("tx_total_udp_msdu %d\n", wnet_vif->vif_sts.sts_tx_udp_msdu ); -+ printk("tx_total_arp_msdu %d\n",wnet_vif->vif_sts.sts_tx_arp_msdu); -+ printk("tx_total_ns_msdu %d\n\n",wnet_vif->vif_sts.sts_tx_ns_msdu); ++ pr_debug("\ntx_total_tcp_msdu %d\n", wnet_vif->vif_sts.sts_tx_tcp_msdu); ++ pr_debug("tx_total_udp_msdu %d\n", wnet_vif->vif_sts.sts_tx_udp_msdu ); ++ pr_debug("tx_total_arp_msdu %d\n",wnet_vif->vif_sts.sts_tx_arp_msdu); ++ pr_debug("tx_total_ns_msdu %d\n\n",wnet_vif->vif_sts.sts_tx_ns_msdu); + + + for(i = 0; i < WME_NUM_TID; i++) + { -+ printk("tx_tid_in_msdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_tid_in_msdu[i]); ++ pr_debug("tx_tid_in_msdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_tid_in_msdu[i]); + } + + for(i = 0; i < WME_NUM_TID; i++) + { -+ printk("tx_tid_drop_msdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_tid_drop_msdu[i]); ++ pr_debug("tx_tid_drop_msdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_tid_drop_msdu[i]); + } + + for(i = 0; i < WME_NUM_TID; i++) + { -+ printk("tx_tid_out_msdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_tid_out_msdu[i]); ++ pr_debug("tx_tid_out_msdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_tid_out_msdu[i]); + } + + for(i = 0; i < WME_NUM_TID; i++) + { -+ printk("tx_tid_drop_bf_in_amsdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_tid_drop_bf_in_msdu[i]); ++ pr_debug("tx_tid_drop_bf_in_amsdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_tid_drop_bf_in_msdu[i]); + } + + + for(i = 0; i < WME_NUM_TID; i++) + { -+ printk("tx_amsdu_in_msdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_amsdu_in_msdu[i]); ++ pr_debug("tx_amsdu_in_msdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_amsdu_in_msdu[i]); + } + + for(i = 0; i < WME_NUM_TID; i++) + { -+ printk("tx_amsdu_drop_msdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_amsdu_drop_msdu[i]); ++ pr_debug("tx_amsdu_drop_msdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_amsdu_drop_msdu[i]); + } + + for(i = 0; i < WME_NUM_TID; i++) + { -+ printk("tx_asmdu_pend_msdu[%d] %d\n", i, wifimac->msdu_cnt[i]); ++ pr_debug("tx_asmdu_pend_msdu[%d] %d\n", i, wifimac->msdu_cnt[i]); + } + + for(i = 0; i < WME_NUM_TID; i++) + { -+ printk("tx_amsdu_out_msdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_amsdu_out_msdu[i]); ++ pr_debug("tx_amsdu_out_msdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_amsdu_out_msdu[i]); + } + + for(i = 0; i < WME_NUM_TID; i++) + { -+ printk("tx_non_amsdu_in_msdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_non_amsdu_in_msdu[i]); ++ pr_debug("tx_non_amsdu_in_msdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_non_amsdu_in_msdu[i]); + + } + + for(i = 0; i < WME_NUM_TID; i++) + { -+ printk("tx_non_amsdu_drop_msdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_non_amsdu_drop_msdu[i]); ++ pr_debug("tx_non_amsdu_drop_msdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_non_amsdu_drop_msdu[i]); + } + + for(i = 0; i < WME_NUM_TID; i++) + { -+ printk("tx_non_amsdu_out_msdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_non_amsdu_out_msdu[i]); ++ pr_debug("tx_non_amsdu_out_msdu[%d] %d\n", i,wnet_vif->vif_sts.sts_tx_non_amsdu_out_msdu[i]); + } + } + } @@ -86417,108 +87668,108 @@ index 000000000000..76baca821132 + { + list_for_each_entry(wnet_vif,&wifimac->wm_wnet_vifs,vm_next) + { -+ printk("\n--------vif_id %d--------\n", wnet_vif->wnet_vif_id); -+ printk("rx_bad_ver %d\n", wnet_vif->vif_sts.sts_rx_bad_ver); ++ pr_debug("\n--------vif_id %d--------\n", wnet_vif->wnet_vif_id); ++ pr_debug("rx_bad_ver %d\n", wnet_vif->vif_sts.sts_rx_bad_ver); + -+ printk("rx_too_short %d\n",wnet_vif->vif_sts.sts_rx_too_short); ++ pr_debug("rx_too_short %d\n",wnet_vif->vif_sts.sts_rx_too_short); + -+ printk("rx_wrong_bss %d\n",wnet_vif->vif_sts.sts_rx_wrong_bss); ++ pr_debug("rx_wrong_bss %d\n",wnet_vif->vif_sts.sts_rx_wrong_bss); + -+ printk("rx_dup %d\n",wnet_vif->vif_sts.sts_rx_dup); ++ pr_debug("rx_dup %d\n",wnet_vif->vif_sts.sts_rx_dup); + -+ printk("rx_wrong_dir %d\n",wnet_vif->vif_sts.sts_rx_wrong_dir); ++ pr_debug("rx_wrong_dir %d\n",wnet_vif->vif_sts.sts_rx_wrong_dir); + -+ printk("rx_mcast_echo %d\n",wnet_vif->vif_sts.sts_rx_mcast_echo); ++ pr_debug("rx_mcast_echo %d\n",wnet_vif->vif_sts.sts_rx_mcast_echo); + -+ printk("rx_not_assoc %d\n",wnet_vif->vif_sts.sts_rx_not_assoc); ++ pr_debug("rx_not_assoc %d\n",wnet_vif->vif_sts.sts_rx_not_assoc); + -+ printk("rx_no_priv_ac %d\n",wnet_vif->vif_sts.sts_no_priv_ac); ++ pr_debug("rx_no_priv_ac %d\n",wnet_vif->vif_sts.sts_no_priv_ac); + -+ printk("rx_uncrypted %d\n",wnet_vif->vif_sts.sts_rx_uncrypted); ++ pr_debug("rx_uncrypted %d\n",wnet_vif->vif_sts.sts_rx_uncrypted); + -+ printk("rx_decap %d\n",wnet_vif->vif_sts.sts_rx_decap); ++ pr_debug("rx_decap %d\n",wnet_vif->vif_sts.sts_rx_decap); + -+ printk("rx_mng_discard %d\n",wnet_vif->vif_sts.sts_mng_discard); ++ pr_debug("rx_mng_discard %d\n",wnet_vif->vif_sts.sts_mng_discard); + -+ printk("rx_ctrl %d\n",wnet_vif->vif_sts.sts_rx_ctrl); ++ pr_debug("rx_ctrl %d\n",wnet_vif->vif_sts.sts_rx_ctrl); + -+ printk("rx_bcn %d\n",wnet_vif->vif_sts.sts_rx_bcn); ++ pr_debug("rx_bcn %d\n",wnet_vif->vif_sts.sts_rx_bcn); + -+ printk("rx_elem_miss %d\n",wnet_vif->vif_sts.sts_rx_elem_miss); ++ pr_debug("rx_elem_miss %d\n",wnet_vif->vif_sts.sts_rx_elem_miss); + -+ printk("rx_elem_too_long %d\n",wnet_vif->vif_sts.sts_rx_elem_too_long); ++ pr_debug("rx_elem_too_long %d\n",wnet_vif->vif_sts.sts_rx_elem_too_long); + -+ printk("rx_elem_too_short %d\n",wnet_vif->vif_sts.sts_rx_elem_too_short); ++ pr_debug("rx_elem_too_short %d\n",wnet_vif->vif_sts.sts_rx_elem_too_short); + -+ printk("rx_elem_err %d\n",wnet_vif->vif_sts.sts_rx_elem_err); ++ pr_debug("rx_elem_err %d\n",wnet_vif->vif_sts.sts_rx_elem_err); + -+ printk("rx_sta_all_fail %d\n",wnet_vif->vif_sts.sts_rx_sta_all_fail); ++ pr_debug("rx_sta_all_fail %d\n",wnet_vif->vif_sts.sts_rx_sta_all_fail); + -+ printk("rx_ssid_mismatch %d\n", wnet_vif->vif_sts.sts_rx_ssid_mismatch); ++ pr_debug("rx_ssid_mismatch %d\n", wnet_vif->vif_sts.sts_rx_ssid_mismatch); + -+ printk("rx_auth_unsprt %d\n", wnet_vif->vif_sts.sts_auth_unsprt); ++ pr_debug("rx_auth_unsprt %d\n", wnet_vif->vif_sts.sts_auth_unsprt); + -+ printk("rx_auth_fail %d\n",wnet_vif->vif_sts.sts_rx_auth_fail); ++ pr_debug("rx_auth_fail %d\n",wnet_vif->vif_sts.sts_rx_auth_fail); + -+ printk("rx_ps_uncnnt %d\n", wnet_vif->vif_sts.sts_rx_ps_uncnnt); ++ pr_debug("rx_ps_uncnnt %d\n", wnet_vif->vif_sts.sts_rx_ps_uncnnt); + -+ printk("rx_ps_aid_err %d\n",wnet_vif->vif_sts.sts_rx_ps_aid_err); ++ pr_debug("rx_ps_aid_err %d\n",wnet_vif->vif_sts.sts_rx_ps_aid_err); + -+ printk("rx_assoc_err %d\n", wnet_vif->vif_sts.sts_rx_assoc_err); ++ pr_debug("rx_assoc_err %d\n", wnet_vif->vif_sts.sts_rx_assoc_err); + -+ printk("rx_assoc_unauth %d\n",wnet_vif->vif_sts.sts_rx_assoc_unauth); ++ pr_debug("rx_assoc_unauth %d\n",wnet_vif->vif_sts.sts_rx_assoc_unauth); + -+ printk("rx_assoc_cap_mismatch %d\n", wnet_vif->vif_sts.sts_rx_assoc_cap_mismatch); ++ pr_debug("rx_assoc_cap_mismatch %d\n", wnet_vif->vif_sts.sts_rx_assoc_cap_mismatch); + -+ printk("rx_assoc_rate_mismatch %d\n", wnet_vif->vif_sts.sts_rx_assoc_rate_mismatch); ++ pr_debug("rx_assoc_rate_mismatch %d\n", wnet_vif->vif_sts.sts_rx_assoc_rate_mismatch); + -+ printk("rx_assoc_wpa_mismatch %d\n",wnet_vif->vif_sts.sts_rx_assoc_wpa_mismatch); ++ pr_debug("rx_assoc_wpa_mismatch %d\n",wnet_vif->vif_sts.sts_rx_assoc_wpa_mismatch); + -+ printk("rx_deauth %d\n", wnet_vif->vif_sts.sts_rx_deauth); ++ pr_debug("rx_deauth %d\n", wnet_vif->vif_sts.sts_rx_deauth); + -+ printk("rx_dis_assoc %d\n",wnet_vif->vif_sts.sts_rx_dis_assoc); ++ pr_debug("rx_dis_assoc %d\n",wnet_vif->vif_sts.sts_rx_dis_assoc); + -+ printk("rx_action %d\n", wnet_vif->vif_sts.sts_rx_action); ++ pr_debug("rx_action %d\n", wnet_vif->vif_sts.sts_rx_action); + -+ printk("rx_buf_full %d\n",wnet_vif->vif_sts.sts_rx_buf_full); ++ pr_debug("rx_buf_full %d\n",wnet_vif->vif_sts.sts_rx_buf_full); + -+ printk("rx_decrypt_err %d\n", wnet_vif->vif_sts.sts_rx_decrypt_err); ++ pr_debug("rx_decrypt_err %d\n", wnet_vif->vif_sts.sts_rx_decrypt_err); + -+ printk("rx_auth_mismatch %d\n", wnet_vif->vif_sts.sts_rx_auth_mismatch); ++ pr_debug("rx_auth_mismatch %d\n", wnet_vif->vif_sts.sts_rx_auth_mismatch); + -+ printk("rx_unauth %d\n",wnet_vif->vif_sts.sts_rx_unauth); ++ pr_debug("rx_unauth %d\n",wnet_vif->vif_sts.sts_rx_unauth); + -+ printk("rx_tkip_mic_err %d\n", wnet_vif->vif_sts.sts_rx_tkip_mic_err); ++ pr_debug("rx_tkip_mic_err %d\n", wnet_vif->vif_sts.sts_rx_tkip_mic_err); + -+ printk("rx_acl_mismatch %d\n", wnet_vif->vif_sts.sts_rx_acl_mismatch); ++ pr_debug("rx_acl_mismatch %d\n", wnet_vif->vif_sts.sts_rx_acl_mismatch); + -+ printk("tx_no_buf %d\n", wnet_vif->vif_sts.sts_tx_no_buf); ++ pr_debug("tx_no_buf %d\n", wnet_vif->vif_sts.sts_tx_no_buf); + -+ printk("tx_no_sta %d\n", wnet_vif->vif_sts.sts_tx_no_sta); ++ pr_debug("tx_no_sta %d\n", wnet_vif->vif_sts.sts_tx_no_sta); + -+ printk("tx_unsprt_mngt %d\n",wnet_vif->vif_sts.sts_tx_unsprt_mngt); ++ pr_debug("tx_unsprt_mngt %d\n",wnet_vif->vif_sts.sts_tx_unsprt_mngt); + -+ printk("tx_key_err %d\n",wnet_vif->vif_sts.sts_tx_key_err); ++ pr_debug("tx_key_err %d\n",wnet_vif->vif_sts.sts_tx_key_err); + -+ printk("tx_headroom_err %d\n",wnet_vif->vif_sts.sts_headroom_err); ++ pr_debug("tx_headroom_err %d\n",wnet_vif->vif_sts.sts_headroom_err); + -+ printk("tx_sta_aged %d\n",wnet_vif->vif_sts.sts_tx_sta_aged); ++ pr_debug("tx_sta_aged %d\n",wnet_vif->vif_sts.sts_tx_sta_aged); + -+ printk("tx_tkip_sw_mic_err %d\n",wnet_vif->vif_sts.sts_tx_tkip_sw_mic_err); ++ pr_debug("tx_tkip_sw_mic_err %d\n",wnet_vif->vif_sts.sts_tx_tkip_sw_mic_err); + -+ printk("tx_ps_no_data %d\n",wnet_vif->vif_sts.sts_tx_ps_no_data); ++ pr_debug("tx_ps_no_data %d\n",wnet_vif->vif_sts.sts_tx_ps_no_data); + -+ printk("rx_tkip_sw_mic_err %d\n", wnet_vif->vif_sts.sts_rx_tkip_sw_mic_err); ++ pr_debug("rx_tkip_sw_mic_err %d\n", wnet_vif->vif_sts.sts_rx_tkip_sw_mic_err); + -+ printk("key_drop %d\n", wnet_vif->vif_sts.sts_key_drop); ++ pr_debug("key_drop %d\n", wnet_vif->vif_sts.sts_key_drop); + -+ printk("key_id_err %d\n", wnet_vif->vif_sts.sts_key_id_err); ++ pr_debug("key_id_err %d\n", wnet_vif->vif_sts.sts_key_id_err); + -+ printk("key_type_err %d\n",wnet_vif->vif_sts.sts_key_type_err); ++ pr_debug("key_type_err %d\n",wnet_vif->vif_sts.sts_key_type_err); + -+ printk("rx_msdu %d\n",wnet_vif->vif_sts.sts_rx_msdu); ++ pr_debug("rx_msdu %d\n",wnet_vif->vif_sts.sts_rx_msdu); + -+ printk("rx_msdu_time_stamp %ld\n",wnet_vif->vif_sts.sts_rx_msdu_time_stamp); ++ pr_debug("rx_msdu_time_stamp %ld\n",wnet_vif->vif_sts.sts_rx_msdu_time_stamp); + } + } + } @@ -86537,7 +87788,7 @@ index 000000000000..76baca821132 + return wifi_mac_cap_detach(wifimac); +} + -+void get_legacy_sta(void *arg, struct wifi_station *sta) ++static void get_legacy_sta(void *arg, struct wifi_station *sta) +{ + struct wifi_mac *wifimac = arg; + @@ -86551,7 +87802,7 @@ index 000000000000..76baca821132 + } +} + -+void get_ht20_sta(void *arg, struct wifi_station *sta) ++static void get_ht20_sta(void *arg, struct wifi_station *sta) +{ + struct wifi_mac *wifimac = arg; + @@ -86888,7 +88139,7 @@ index 000000000000..76baca821132 + } +} + -+int wifi_mac_check_main_sta(struct wlan_net_vif *wnet_vif) ++static int wifi_mac_check_main_sta(struct wlan_net_vif *wnet_vif) +{ + int return_val = 0; + if (!wnet_vif->vm_mainsta) { @@ -86990,7 +88241,7 @@ index 000000000000..76baca821132 + return -1; + } + -+ printk(" %s %d dev = %p\n",__func__,__LINE__,dev); ++ pr_debug(" %s %d dev = %p\n",__func__,__LINE__,dev); + return wifi_mac_initial(dev, 0); +} + @@ -87005,7 +88256,7 @@ index 000000000000..76baca821132 + return -1; + } + -+ printk("%s wm_nopened %d, wm_dev_flags:%08x\n", __func__, wifimac->wm_nopened, wifimac->wm_dev_flags); ++ pr_debug("%s wm_nopened %d, wm_dev_flags:%08x\n", __func__, wifimac->wm_nopened, wifimac->wm_dev_flags); + preempt_scan(dev, 100, 100); + cancel_work_sync(&wifimac->wm_scan->timeout_work); + @@ -87073,13 +88324,43 @@ index 000000000000..76baca821132 +{ + struct wlan_net_vif *wnet_vif = (struct wlan_net_vif *)param1; + struct wifi_mac *wifimac = wnet_vif->vm_wmac; -+ printk("%s vid:%d, act_pkt_retry_count:%d, token:%d\n", -+ __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_p2p->act_pkt_retry_count, wnet_vif->vm_p2p->action_dialog_token); ++ struct wifi_mac_p2p *p2p = wnet_vif->vm_p2p; ++ ++ pr_debug("%s vid:%d, act_pkt_retry_count:%d, token:%d\n", ++ __func__, wnet_vif->wnet_vif_id, wnet_vif->vm_p2p->act_pkt_retry_count, ++ wnet_vif->vm_p2p->action_dialog_token); + + if (wnet_vif->vm_p2p->tx_status_flag == WIFINET_TX_STATUS_SUCC) { + return; + } + ++ if ((wnet_vif->vm_flags_ext2 & WIFINET_FEXT2_DPP_CONNECTION_STATUS_RETRY)) { ++ if (wnet_vif->vm_p2p->act_pkt_retry_count < 10) { ++ int delay = 0; ++ ++ if (p2p->action_chan && (wifimac->wm_curchan != p2p->action_chan)) { ++ if (wifi_mac_is_wm_running(wifimac) == true) { ++ wifi_mac_scan_notify_leave_or_back(wnet_vif, 1); ++ while ((!wifimac->drv_priv->hal_priv->hal_ops.hal_tx_empty()) && delay < 500) { ++ msleep(10); ++ delay += 10; ++ } ++ wnet_vif->vm_flags_ext2 |= WIFINET_FEXT2_MGMT_RESTORE_CHANNEL; ++ } ++ wifi_mac_ChangeChannel(wifimac, p2p->action_chan, 0, wnet_vif->wnet_vif_id, wnet_vif->vm_opmode); ++ } ++ wnet_vif->vm_p2p->act_pkt_retry_count++; ++ AML_OUTPUT("dpp status retry pri_chan:%d delay:%d flag:%x retry_cnt:%d\n", wifimac->wm_curchan->chan_pri_num, ++ delay, wnet_vif->vm_flags_ext2, wnet_vif->vm_p2p->act_pkt_retry_count); ++ //need a lock ++ vm_cfg80211_send_mgmt(wnet_vif, wnet_vif->vm_p2p->action_pkt, wnet_vif->vm_p2p->action_pkt_len); ++ } else { ++ AML_OUTPUT("dpp connection send fail\n"); ++ wnet_vif->vm_flags_ext2 &= ~WIFINET_FEXT2_DPP_CONNECTION_STATUS_RETRY; ++ } ++ return; ++ } ++ + if ((wnet_vif->vm_p2p->tx_status_flag == WIFINET_TX_STATUS_FAIL && wnet_vif->vm_p2p->act_pkt_retry_count == DEFAULT_P2P_ACTION_RETRY_TIMES)) { + wnet_vif->vm_p2p->send_tx_status_flag = 1; + cfg80211_mgmt_tx_status(wnet_vif->vm_wdev, wnet_vif->vm_p2p->cookie, wnet_vif->vm_p2p->raw_action_pkt, wnet_vif->vm_p2p->raw_action_pkt_len, WIFINET_TX_STATUS_FAIL, GFP_KERNEL); @@ -87094,7 +88375,7 @@ index 000000000000..76baca821132 + || wnet_vif->vm_p2p->action_code == WIFINET_ACT_PUBLIC_GAS_REQ || wnet_vif->vm_p2p->action_code == WIFINET_ACT_PUBLIC_GAS_RSP +#endif + ) && (wnet_vif->vm_p2p->act_pkt_retry_count < DEFAULT_P2P_ACTION_RETRY_TIMES)) { -+ printk("%s p2p retry pri_chan:%d\n", __func__, wnet_vif->vm_p2p->work_channel->chan_pri_num); ++ pr_debug("%s p2p retry pri_chan:%d\n", __func__, wnet_vif->vm_p2p->work_channel->chan_pri_num); + //need a lock + wnet_vif->vm_p2p->act_pkt_retry_count++; + vm_cfg80211_send_mgmt(wnet_vif, wnet_vif->vm_p2p->action_pkt, wnet_vif->vm_p2p->action_pkt_len); @@ -87102,6 +88383,11 @@ index 000000000000..76baca821132 + return; + } + ++ if (wnet_vif->vm_p2p->tx_status_flag == WIFINET_TX_STATUS_FAIL) { ++ wnet_vif->vm_p2p->send_tx_status_flag = 1; ++ cfg80211_mgmt_tx_status(wnet_vif->vm_wdev, wnet_vif->vm_p2p->cookie, wnet_vif->vm_p2p->raw_action_pkt, wnet_vif->vm_p2p->raw_action_pkt_len, WIFINET_TX_STATUS_FAIL, GFP_KERNEL); ++ } ++ + if (wnet_vif->vm_state == WIFINET_S_SCAN) { + return; + } @@ -87113,39 +88399,37 @@ index 000000000000..76baca821132 +{ + struct wlan_net_vif *wnet_vif = (struct wlan_net_vif *)param1; + -+ printk("vid:%d, mgmt_pkt_retry_count:%d, token:%d\n", ++ pr_debug("vid:%d, mgmt_pkt_retry_count:%d, token:%d\n", + wnet_vif->wnet_vif_id, wnet_vif->mgmt_pkt_retry_count, wnet_vif->vm_p2p->action_dialog_token); + + if (wnet_vif->mgmt_pkt_retry_count++ < DEFAULT_MGMT_RETRY_TIMES) { + if (wnet_vif->vm_state == WIFINET_S_AUTH) { + /* swap the auth type between open and shared when auth timeout after sending auth frame to a wep AP */ -+ if (wnet_vif->mgmt_pkt_retry_count == DEFAULT_MGMT_RETRY_TIMES -1) { ++ if (wnet_vif->mgmt_pkt_retry_count == DEFAULT_MGMT_RETRY_TIMES - 1) { + if ((wnet_vif->vm_flags & WIFINET_F_PRIVACY) && !(wnet_vif->vm_flags & WIFINET_F_WPA)) { + if (wnet_vif->vm_mainsta->sta_authmode == WIFINET_AUTH_SHARED) { + wnet_vif->vm_mainsta->sta_authmode = WIFINET_AUTH_OPEN; -+ + } else { + wnet_vif->vm_mainsta->sta_authmode = WIFINET_AUTH_SHARED; + } + } + } + wifi_mac_top_sm(wnet_vif, WIFINET_S_AUTH, WIFINET_FC0_SUBTYPE_DEAUTH); -+ + } else if (wnet_vif->vm_state == WIFINET_S_ASSOC) { + wifi_mac_top_sm(wnet_vif, WIFINET_S_ASSOC, 0); -+ + } else { + wnet_vif->mgmt_pkt_retry_count = 0; + return; + } + -+ //printk("wifi_mac->mgmt_pkt_retry_count:%d\n", wifimac->mgmt_pkt_retry_count); ++ //pr_debug("wifi_mac->mgmt_pkt_retry_count:%d\n", wifimac->mgmt_pkt_retry_count); + os_timer_ex_start_period(&wnet_vif->vm_mgtsend, wnet_vif->mgmt_pkt_retry_count * DEFAULT_MGMT_RETRY_INTERVAL); + return; + } + + wnet_vif->mgmt_pkt_retry_count = 0; + if ((wnet_vif->vm_state == WIFINET_S_AUTH) || (wnet_vif->vm_state == WIFINET_S_ASSOC)) { ++ wnet_vif->disconnect_reason_code = WLAN_STATUS_UNSPECIFIED_FAILURE; + vm_cfg80211_indicate_disconnect(wnet_vif); + wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN, 0); + } @@ -87155,7 +88439,7 @@ index 000000000000..76baca821132 +{ + struct wlan_net_vif *wnet_vif = (struct wlan_net_vif *) arg; + -+ printk("%s vm_state %s, vid:%d", __func__, wifi_mac_state_name[wnet_vif->vm_state], wnet_vif->wnet_vif_id); ++ pr_debug("%s vm_state %s, vid:%d", __func__, wifi_mac_state_name[wnet_vif->vm_state], wnet_vif->wnet_vif_id); + if ((wnet_vif->vm_p2p_support == 1) || (wnet_vif->vm_state > WIFINET_S_CONNECTING)) { + wifi_mac_add_work_task(wnet_vif->vm_wmac,wifi_mac_tx_timeout_ex, NULL,(SYS_TYPE)arg,0,0,0, 0); + } @@ -87169,7 +88453,7 @@ index 000000000000..76baca821132 + struct wlan_net_vif *wnet_vif = (struct wlan_net_vif *)param1; + enum wifi_mac_state state = (enum wifi_mac_state)param2; + -+ printk("%s state:%d\n", __func__, state); ++ pr_debug("%s state:%d\n", __func__, state); + + if(state != WIFINET_S_INIT) { + wifi_mac_top_sm(wnet_vif, state, 0); @@ -87191,7 +88475,7 @@ index 000000000000..76baca821132 + struct wifi_station *sta = NULL; + struct wifi_station *sta_next = NULL; + -+ if (wnet_vif->vm_p2p_support == 1) { ++ if (wnet_vif->vm_p2p_support == 1 || (wnet_vif->vm_flags_ext2 & WIFINET_FEXT2_DPP_CONNECTION_STATUS_RETRY)) { + WIFINET_DPRINTF(AML_DEBUG_WARNING,"vm_state %s", wifi_mac_state_name[wnet_vif->vm_state]); + wifi_mac_add_work_task(wnet_vif->vm_wmac,wifi_mac_tx_act_timeout_ex, NULL,(SYS_TYPE)arg,0,0,0, 0); + } @@ -87204,7 +88488,7 @@ index 000000000000..76baca821132 + os_timer_ex_start_period(&wnet_vif->vm_actsend, 100); + + } else { -+ printk("sta not get pmf sa query rsp, just disconnect\n"); ++ pr_warn("sta not get pmf sa query rsp, just disconnect\n"); + wifi_mac_add_work_task(wnet_vif->vm_wmac, wifi_mac_sm_switch, NULL, (SYS_TYPE)wnet_vif, WIFINET_S_SCAN, 0, 0, 0); + } + @@ -87220,7 +88504,7 @@ index 000000000000..76baca821132 + os_timer_ex_start_period(&wnet_vif->vm_actsend, 100); + + } else { -+ printk("sta:%p not get pmf sa query rsp, just disconnect\n", sta); ++ pr_warn("sta:%p not get pmf sa query rsp, just disconnect\n", sta); + wifi_mac_sta_disconnect(sta); + wifi_mac_rm_sta_from_wds_by_addr(nt,sta->sta_macaddr); + list_del_init(&sta->sta_list); @@ -87240,7 +88524,7 @@ index 000000000000..76baca821132 +{ + struct wlan_net_vif *wnet_vif = (struct wlan_net_vif *)arg; + -+ printk("wifi_mac_RocTimeout\n"); ++ pr_debug("wifi_mac_RocTimeout\n"); + + cfg80211_remain_on_channel_expired(wnet_vif->vm_wdev, wnet_vif->remain_on_ch_cookie, + &wnet_vif->remain_on_ch_channel, GFP_KERNEL); @@ -87293,6 +88577,7 @@ index 000000000000..76baca821132 + int mgmt_arg; + + prestate = wnet_vif->vm_state; ++ wnet_vif->vm_state_pre = wnet_vif->vm_state; + wnet_vif->vm_state = nstate; + + if (prestate == WIFINET_S_CONNECTED && nstate != WIFINET_S_CONNECTED) @@ -87338,7 +88623,7 @@ index 000000000000..76baca821132 + break; + + case WIFINET_M_HOSTAP: -+ wifi_mac_func_to_task(&wnet_vif->vm_sta_tbl, wifi_mac_sta_disassoc, wnet_vif,1); ++ wifi_mac_sta_disassoc_in_task(wnet_vif); + goto reset; + + case WIFINET_M_IBSS: @@ -87377,7 +88662,7 @@ index 000000000000..76baca821132 + break; + + case WIFINET_S_MAX: -+ printk("need to check twice\n"); ++ pr_err("need to check twice\n"); + break; + } + break; @@ -87422,9 +88707,17 @@ index 000000000000..76baca821132 + case WIFINET_S_AUTH: + case WIFINET_S_ASSOC: + /* if (wifimac->wm_roaming == WIFINET_ROAMING_AUTO) */ -+ { -+ WIFINET_DPRINTF(AML_DEBUG_STATE,"%s(%d) sm:scan/connecting/auth/assoc:", __func__,__LINE__); -+ ++ if (sta->connect_status == CONNECT_DISCONNECTING) { ++ struct vm_wdev_priv *pwdev_priv = wdev_to_priv(wnet_vif->vm_wdev); ++ ++ pr_debug("%s, cancel connect and indicate disconnect\n", __func__); ++ os_timer_ex_cancel(&pwdev_priv->connect_timeout, CANCEL_SLEEP); ++ wifi_mac_notify_nsta_disconnect(sta, 0); ++ wnet_vif->vm_des_nssid = 0; ++ wnet_vif->vm_curchan = WIFINET_CHAN_ERR; ++ memset(wnet_vif->vm_des_ssid, 0, IV_SSID_SCAN_AMOUNT*sizeof(struct wifi_mac_ScanSSID)); ++ } else { ++ pr_debug("%s, sm:scan/connecting/auth/assoc:", __func__); + wifi_mac_chk_scan(wnet_vif, WIFINET_SCANCFG_ACTIVE| WIFINET_SCANCFG_FLUSH |arg, + wnet_vif->vm_des_nssid, wnet_vif->vm_des_ssid); + } @@ -87445,12 +88738,12 @@ index 000000000000..76baca821132 + } + else + { -+ wifi_mac_func_to_task(&wnet_vif->vm_sta_tbl, wifi_mac_sta_disassoc, wnet_vif,1); ++ wifi_mac_sta_disassoc_in_task(wnet_vif); + goto createibss; + } + break; + case WIFINET_S_MAX: -+ printk("need to check twice\n"); ++ pr_err("need to check twice\n"); + break; + } +#ifdef INTER_BEACON @@ -87475,6 +88768,11 @@ index 000000000000..76baca821132 + wnet_vif->mgmt_pkt_retry_count = 0; + } + ++ if (sta->connect_status >= CONNECT_DISCONNECTING) { ++ wifi_mac_add_work_task(wnet_vif->vm_wmac, wifi_mac_sm_switch, NULL, (SYS_TYPE)wnet_vif, WIFINET_S_SCAN, 0, 0, 0); ++ break; ++ } ++ + switch (prestate) { + case WIFINET_S_SCAN: + case WIFINET_S_CONNECTING: @@ -87546,6 +88844,11 @@ index 000000000000..76baca821132 + wnet_vif->mgmt_pkt_retry_count = 0; + } + ++ if (sta->connect_status >= CONNECT_DISCONNECTING) { ++ wifi_mac_add_work_task(wnet_vif->vm_wmac, wifi_mac_sm_switch, NULL, (SYS_TYPE)wnet_vif, WIFINET_S_SCAN, 0, 0, 0); ++ break; ++ } ++ + switch (prestate) + { + case WIFINET_S_AUTH: @@ -87563,7 +88866,7 @@ index 000000000000..76baca821132 + + default: + wifi_mac_add_work_task(wnet_vif->vm_wmac, wifi_mac_sm_switch, NULL, (SYS_TYPE)wnet_vif, WIFINET_S_SCAN, 0, 0, 0); -+ printk("need to check twice\n"); ++ pr_err("need to check twice\n"); + break; + } + break; @@ -87586,7 +88889,7 @@ index 000000000000..76baca821132 + } + break; + case WIFINET_S_MAX: -+ printk("need to check twice\n"); ++ pr_err("need to check twice\n"); + break; + default: + break; @@ -87617,22 +88920,20 @@ index 000000000000..76baca821132 + } + wifi_mac_set_channel_rssi(wifimac, (unsigned char)(wnet_vif->vm_mainsta->sta_avg_bcn_rssi)); + -+ printk("****************************************************\n"); -+ printk("sta connect ok!!! AP CHANNEL:%d, CENTER_CHAN:%d, BW:%d, SSID:%s, BSSID:%02x:%02x:%02x:%02x:%02x:%02x\n", ++ pr_debug("****************************************************\n"); ++ pr_debug("sta connect ok!!! AP CHANNEL:%d, CENTER_CHAN:%d, BW:%d, SSID:%s, BSSID:%02x:%02x:%02x:%02x:%02x:%02x\n", + wnet_vif->vm_curchan->chan_pri_num, wifi_mac_Mhz2ieee(wnet_vif->vm_curchan->chan_cfreq1, 0), sta->sta_chbw, + wnet_vif->vm_des_ssid[0].ssid, wnet_vif->vm_des_bssid[0], wnet_vif->vm_des_bssid[1], wnet_vif->vm_des_bssid[2], + wnet_vif->vm_des_bssid[3], wnet_vif->vm_des_bssid[4], wnet_vif->vm_des_bssid[5]); -+ printk("****************************************************\n"); -+ /* Reset statistics on new connection for tracking */ -+ wnet_vif->vm_devstats.tx_dropped = 0; -+ wnet_vif->vm_devstats.tx_errors = 0; ++ pr_debug("****************************************************\n"); + g_auto_gain_base = 0; ++ wnet_vif->disconnect_reason_code = 0; + } + + wifi_mac_sta_auth(sta); + break; + case WIFINET_S_MAX: -+ printk("-------------error: need to check twice-------------------\n"); ++ pr_err("-------------error: need to check twice-------------------\n"); + break; + + default: @@ -87647,17 +88948,25 @@ index 000000000000..76baca821132 + wifi_mac_set_scan_time(wnet_vif); + #ifdef CONFIG_CONCURRENT_MODE + if ((wifimac->wm_nrunning > 1) && !concurrent_check_is_vmac_same_pri_channel(wifimac)) { -+ if (wnet_vif->vm_p2p_support == 1) { ++ if ((wnet_vif->vm_p2p_support == 1) || (wnet_vif->vm_opmode == WIFINET_M_HOSTAP)) { + wifimac->wm_vsdb_slot = CONCURRENT_SLOT_P2P; + } else { + wifimac->wm_vsdb_slot = CONCURRENT_SLOT_STA; + } ++#if 0 + if (IS_APSTA_CONCURRENT(aml_wifi_get_con_mode()) && concurrent_check_vmac_is_AP(wifimac)) { + /*softap and sta concurrent as scc, no need vsdb*/ + wifimac->wm_vsdb_slot = CONCURRENT_SLOT_NONE; + } else { + wifi_mac_add_work_task(wifimac, wifi_mac_set_vsdb, NULL, (SYS_TYPE)wifimac, 0, ENABLE, (SYS_TYPE)wnet_vif, 0); + } ++#endif ++ if (IS_APSTA_CONCURRENT(aml_wifi_get_con_mode()) && concurrent_check_vmac_is_AP(wifimac)) { ++ struct wifi_channel *main_vmac_chan = wifi_mac_get_main_vmac_channel(wifimac); ++ ++ channel_switch_announce_trigger(wifimac, main_vmac_chan); ++ } ++ wifi_mac_set_vsdb_task(wifimac, wnet_vif, ENABLE); + } + #endif + } @@ -87670,8 +88979,7 @@ index 000000000000..76baca821132 + wifimac->wm_vsdb_flags = 0; + wifimac->vsdb_mode_set_noa_enable = 0; + wifi_mac_restore_wnet_vif_channel_task(wnet_vif); -+ -+ wifi_mac_add_work_task(wifimac, wifi_mac_set_vsdb, NULL,(SYS_TYPE)wifimac, 0, DISABLE, (SYS_TYPE)wnet_vif, 0); ++ wifi_mac_set_vsdb_task(wifimac, wnet_vif, ENABLE); + } + #endif + } @@ -87700,17 +89008,17 @@ index 000000000000..76baca821132 + wifi_mac_add_work_task(wifimac, wifi_mac_beacon_alloc_ex, NULL, (SYS_TYPE)wifimac, + (SYS_TYPE)wnet_vif->wnet_vif_id,0, (SYS_TYPE)wnet_vif, (SYS_TYPE)wnet_vif->wnet_vif_replaycounter); + -+ printk("****************************************************\n"); -+ printk("start bss ok!!! AP CHANNEL:%d, BW:%d, SSID:%s, BSSID:%02x:%02x:%02x:%02x:%02x:%02x\n", ++ pr_debug("****************************************************\n"); ++ pr_debug("start bss ok!!! AP CHANNEL:%d, BW:%d, SSID:%s, BSSID:%02x:%02x:%02x:%02x:%02x:%02x\n", + wnet_vif->vm_curchan->chan_pri_num, wnet_vif->vm_curchan->chan_bw, wnet_vif->vm_des_ssid[0].ssid, + wnet_vif->vm_des_bssid[0], wnet_vif->vm_des_bssid[1], wnet_vif->vm_des_bssid[2], + wnet_vif->vm_des_bssid[3], wnet_vif->vm_des_bssid[4], wnet_vif->vm_des_bssid[5]); -+ printk("****************************************************\n"); ++ pr_debug("****************************************************\n"); + + } + wifi_mac_sub_sm(wnet_vif, nstate, arg); + -+ printk("%s(%d) wm_running=%d, wnet_vif_mode %d vm_bandwidth:%d\n", ++ pr_debug("%s(%d) wm_running=%d, wnet_vif_mode %d vm_bandwidth:%d\n", + __func__, __LINE__, wifimac->wm_nrunning, wnet_vif->vm_mac_mode, wnet_vif->vm_bandwidth); + break; + @@ -87718,7 +89026,7 @@ index 000000000000..76baca821132 + wifi_mac_sub_sm(wnet_vif, nstate, arg); + wnet_vif->vm_des_nssid = 0; + if (opmode == WIFINET_M_HOSTAP) { -+ printk("%s(%d) interface down\n", __func__, __LINE__); ++ pr_debug("%s(%d) interface down\n", __func__, __LINE__); + wnet_vif->vm_curchan = WIFINET_CHAN_ERR; + memset(wnet_vif->vm_des_ssid, 0, IV_SSID_SCAN_AMOUNT*sizeof(struct wifi_mac_ScanSSID)); + wifimac->drv_priv->drv_ops.down_interface(wifimac->drv_priv, wnet_vif->wnet_vif_id); @@ -87752,18 +89060,13 @@ index 000000000000..76baca821132 + if (VM_WIFI_CONNECT_STATE(nstate) && !VM_WIFI_CONNECT_STATE(prestate)) { + wifi_mac_connect_start(wifimac); + if ((opmode == WIFINET_M_STA) || (opmode == WIFINET_M_P2P_CLIENT)) { -+ printk(" connect_start: %d\n",__LINE__); ++ pr_debug(" connect_start: %d\n",__LINE__); + } + + } else if (VM_WIFI_CONNECT_STATE(prestate) && !VM_WIFI_CONNECT_STATE(nstate)) { + wifi_mac_connect_end(wifimac); -+ printk("%s(%d): connect end =%d, wnet_vif_mode %d\n", __func__, ++ pr_debug("%s(%d): connect end =%d, wnet_vif_mode %d\n", __func__, + __LINE__, wifimac->wm_nrunning, wnet_vif->vm_mac_mode); -+ /* Log TX statistics on disconnect for debugging */ -+ printk("WiFi disconnect stats: tx_packets=%lu, tx_bytes=%lu, tx_failed=%lu, tx_dropped=%lu, tx_errors=%lu\n", -+ wnet_vif->vm_devstats.tx_packets, wnet_vif->vm_devstats.tx_bytes, -+ wnet_vif->vm_devstats.tx_dropped + wnet_vif->vm_devstats.tx_errors, -+ wnet_vif->vm_devstats.tx_dropped, wnet_vif->vm_devstats.tx_errors); + } + + return rc; @@ -87872,7 +89175,7 @@ index 000000000000..76baca821132 + wnet_vif->vm_wdev->wiphy->addresses = (struct mac_address *)(wnet_vif->vm_myaddr); + + wifimac->drv_priv->drv_ops.set_macaddr(wifimac->drv_priv, wnet_vif->wnet_vif_id, wnet_vif->vm_myaddr); -+ printk("%s change mac_addr to:%02x:%02x:%02x:%02x:%02x:%02x\n", __func__, wnet_vif->vm_myaddr[0], ++ pr_debug("%s change mac_addr to:%02x:%02x:%02x:%02x:%02x:%02x\n", __func__, wnet_vif->vm_myaddr[0], + wnet_vif->vm_myaddr[1], wnet_vif->vm_myaddr[2], wnet_vif->vm_myaddr[3], wnet_vif->vm_myaddr[4], wnet_vif->vm_myaddr[5]); + return ret; +} @@ -87895,7 +89198,7 @@ index 000000000000..76baca821132 + wnet_vif->vm_tx_stbc = GET_VHT_CAP_TX_STBC(wifimac->wm_flags_ext2); + wnet_vif->vm_rx_stbc = GET_VHT_CAP_RX_STBC(wifimac->wm_flags_ext2); + -+ printk("vht cap init: sgi 0x%x, ldpc 0x%x, tx_stbc 0x%x, rx_stbc 0x%x \n", ++ pr_debug("vht cap init: sgi 0x%x, ldpc 0x%x, tx_stbc 0x%x, rx_stbc 0x%x \n", + wnet_vif->vm_sgi, wnet_vif->vm_ldpc, wnet_vif->vm_tx_stbc, wnet_vif->vm_rx_stbc); + + if (wnet_vif->vm_opmode == WIFINET_M_HOSTAP) @@ -87937,7 +89240,7 @@ index 000000000000..76baca821132 + hw_if->hif_ops.hi_write_word(MAC_RXPKT_CONTROL45, reg_val | (bw << 17));//bit17 & bit18 set ap's bw + + } else { -+ printk("%s, No vaild reg addr\n", __func__); ++ pr_warn("%s, No valid reg addr\n", __func__); + } +} + @@ -87963,7 +89266,7 @@ index 000000000000..76baca821132 + wnet_vif->scnd_chn_offset = WIFINET_HTINFO_EXTOFFSET_NA; + wnet_vif->vm_bandwidth = WIFINET_BWC_WIDTH80; + -+ printk(" %s %d opmode=%d\n",__func__,__LINE__,opmode); ++ pr_debug(" %s %d opmode=%d\n",__func__,__LINE__,opmode); + switch (opmode) + { + case WIFINET_M_STA: @@ -88022,7 +89325,7 @@ index 000000000000..76baca821132 + wnet_vif->vm_flags_ext &= ~WIFINET_FEXT_SWBMISS; + wnet_vif->vm_flags = wifimac->wm_flags; + -+ printk(" %s %d opmode=%d\n",__func__,__LINE__,opmode); ++ pr_debug(" %s %d opmode=%d\n",__func__,__LINE__,opmode); + switch (opmode) + { + case WIFINET_M_STA: @@ -88056,10 +89359,21 @@ index 000000000000..76baca821132 + struct regulatory_request *request) +{ + struct wifi_mac *wifimac = wifi_mac_get_mac_handle(); ++ struct wlan_net_vif *wnet_vif = wiphy_to_adapter(wiphy); ++ unsigned char source_code[5][10] = {"core", "user", "driver", "countryie"}; ++ unsigned int delay_ms = 0; + + if (!request) + return; + ++ while ((wifimac->wm_flags & WIFINET_F_DOTH) && (wifimac->wm_flags & WIFINET_F_CHANSWITCH) && delay_ms < 1000) { ++ msleep(50); ++ delay_ms+=50; ++ } ++ ++ AML_OUTPUT("vid:%d, regdom set by %s, country <%s>, wiphy alpha2 %s\n", ++ wnet_vif->wnet_vif_id, source_code[request->initiator], request->alpha2, wiphy->regd->alpha2); ++ + switch (request->initiator) { + case NL80211_REGDOM_SET_BY_CORE: + break; @@ -88193,7 +89507,7 @@ index 000000000000..76baca821132 + return 0; +} + -+void ++static void +wifi_mac_build_country_ie_2G(struct wifi_mac *wifimac) +{ + struct wifi_channel *c; @@ -88222,7 +89536,7 @@ index 000000000000..76baca821132 + wifimac->wm_countryinfo.country_len += 3; +} + -+void ++static void +wifi_mac_build_country_ie_5G(struct wifi_mac *wifimac) +{ + struct wifi_channel *c; @@ -88244,27 +89558,72 @@ index 000000000000..76baca821132 +} + +void ++wifi_mac_build_country_ie_2G_and_5G(struct wifi_mac *wifimac) ++{ ++ struct wifi_channel *c; ++ int i = 0 ; ++ int channel_num = 0; ++ int first_channel = 0; ++ int max_power = 0; ++ int triplet_index = 0; ++ ++ WIFI_CHANNEL_LOCK(wifimac); ++ for (i = 0; i < wifimac->wm_nchans; i++) { ++ c = &wifimac->wm_channels[i]; ++ ++ if (WIFINET_IS_CHAN_2GHZ(c) && (c->chan_bw == WIFINET_BWC_WIDTH20)) { ++ if (!first_channel) { ++ first_channel = c->chan_pri_num; ++ max_power = c->chan_maxpower; ++ } ++ ++ if (max_power < c->chan_maxpower) { ++ max_power = c->chan_maxpower; ++ } ++ channel_num ++; ++ } ++ } ++ ++ if (channel_num != 0) { ++ wifimac->wm_countryinfo.country_triplet[triplet_index++] = first_channel; ++ wifimac->wm_countryinfo.country_triplet[triplet_index++] = channel_num; ++ wifimac->wm_countryinfo.country_triplet[triplet_index++] = max_power; ++ wifimac->wm_countryinfo.country_len += 4; ++ } ++ ++ for (i = 0; i < wifimac->wm_nchans; i++) { ++ c = &wifimac->wm_channels[i]; ++ ++ if (WIFINET_IS_CHAN_5GHZ(c) && (c->chan_bw == WIFINET_BWC_WIDTH20)) { ++ if (!(c->chan_flags & WIFINET_CHAN_DFS)) { ++ wifimac->wm_countryinfo.country_triplet[triplet_index++] = c->chan_pri_num; ++ wifimac->wm_countryinfo.country_triplet[triplet_index++] = 1; ++ wifimac->wm_countryinfo.country_triplet[triplet_index++] = c->chan_maxpower; ++ wifimac->wm_countryinfo.country_len += 3; ++ } ++ } ++ } ++ WIFI_CHANNEL_UNLOCK(wifimac); ++} ++ ++void +wifi_mac_build_country_ie(struct wlan_net_vif * wnet_vif) +{ + struct wifi_mac *wifimac = wnet_vif->vm_wmac; + struct _wifi_mac_country_iso country; ++ + memset(&wifimac->wm_countryinfo, 0, sizeof(wifimac->wm_countryinfo)); + wifimac->wm_countryinfo.country_id = WIFINET_ELEMID_COUNTRY; + wifimac->wm_countryinfo.country_len = 0; + -+ wifi_mac_get_country(wifimac,&country); ++ wifi_mac_get_country(wifimac, &country); + + wifimac->wm_countryinfo.country_str[0] = country.iso[0]; + wifimac->wm_countryinfo.country_str[1] = country.iso[1]; + wifimac->wm_countryinfo.country_str[2] = 0x20; //environment: Any + wifimac->wm_countryinfo.country_len += 3; + -+ if (WIFINET_IS_CHAN_2GHZ(wnet_vif->vm_curchan)) { -+ wifi_mac_build_country_ie_2G(wifimac); -+ -+ } else { -+ wifi_mac_build_country_ie_5G(wifimac); -+ } ++ wifi_mac_build_country_ie_2G_and_5G(wifimac); + + DPRINTF(AML_DEBUG_INFO,"INFO::Country ie is %c%c%c\n", wifimac->wm_countryinfo.country_str[0], + wifimac->wm_countryinfo.country_str[1], wifimac->wm_countryinfo.country_str[2]); @@ -88309,6 +89668,15 @@ index 000000000000..76baca821132 + if (!(wnet_vif->vm_pstxqueue_flags & WIFINET_PSQUEUE_NOA) ) { + wifimac->drv_priv->drv_ops.drv_hal_tx_frm_pause(wifimac->drv_priv, 0); + } ++ ++ if (wifimac->wm_vsdb_flags & CONCURRENT_SWITCH_TO_STA_CHANNEL) { ++ wifimac->wm_vsdb_slot = CONCURRENT_SLOT_NONE; ++ wifimac->wm_vsdb_flags &= ~CONCURRENT_SWITCH_TO_STA_CHANNEL; ++ /*switch to sta channel,we need notify ap*/ ++ wifi_mac_scan_notify_leave_or_back(wifimac->drv_priv->drv_wnet_vif_table[NET80211_MAIN_VMAC],0); ++ AML_OUTPUT("channel switch complete and sta notify ap back done\n"); ++ } ++ + WIFI_SCAN_LOCK(ss); + if (ss->scan_StateFlags & SCANSTATE_F_WAIT_CHANNEL_SWITCH) { + ss->scan_StateFlags &= ~SCANSTATE_F_WAIT_CHANNEL_SWITCH; @@ -88322,7 +89690,7 @@ index 000000000000..76baca821132 + return; +} + -+void wifi_mac_set_noa(struct wlan_net_vif *wnet_vif) ++static void wifi_mac_set_noa(struct wlan_net_vif *wnet_vif) +{ + struct wifi_mac *wifimac = wifi_mac_get_mac_handle(); + unsigned long long tsf; @@ -88367,7 +89735,7 @@ index 000000000000..76baca821132 + if (ss->scan_StateFlags & SCANSTATE_F_WAIT_TBTT) { + ss->scan_StateFlags &= ~SCANSTATE_F_WAIT_TBTT; + -+ //printk("%s start timer\n", __func__); ++ //pr_debug("%s start timer\n", __func__); + if (ss->scan_chan_wait <= 60) { + os_timer_ex_start_period(&ss->ss_scan_timer, + (WIFINET_SCAN_DEFAULT_INTERVAL - ss->scan_chan_wait - WIFINET_SCAN_CHANNEL_COST - WIFINET_SCAN_INTERVAL_LEFT)); @@ -88402,7 +89770,7 @@ index 000000000000..76baca821132 + WIFI_SCAN_LOCK(ss); + if (ss->scan_StateFlags & SCANSTATE_F_WAIT_TBTT) { + ss->scan_StateFlags &= ~SCANSTATE_F_WAIT_TBTT; -+ //printk("%s start timer\n", __func__); ++ //pr_debug("%s start timer\n", __func__); + os_timer_ex_start_period(&ss->ss_scan_timer, WIFINET_SCAN_MOTHER_CHANNEL_TIME); + } + WIFI_SCAN_UNLOCK(ss); @@ -88423,7 +89791,7 @@ index 000000000000..76baca821132 + ifa_v4 = in_dev->ifa_list; + if (ifa_v4 != NULL) { + ifa_v4->ifa_local = *(__be32 *)(&fw_event->local_ip); -+ printk("local ip: %08x\n", ifa_v4->ifa_local); ++ pr_debug("local ip: %08x\n", ifa_v4->ifa_local); + } + } + @@ -88460,7 +89828,7 @@ index 000000000000..76baca821132 + return -EIO; + } + -+ printk(" %s %d cp.vm_param_opmode=%d vm_param_name %s vid = %d \n", ++ pr_debug(" %s %d cp.vm_param_opmode=%d vm_param_name %s vid = %d \n", + __func__,__LINE__,vmparam.vm_param_opmode,vmparam.vm_param_name,vid); + + switch (vmparam.vm_param_opmode) { @@ -88580,7 +89948,7 @@ index 000000000000..76baca821132 + return out; +} + -+int wifi_mac_get_ap_mode(unsigned char rates[]) ++static int wifi_mac_get_ap_mode(unsigned char rates[]) +{ + int i = 0; + int j = 0; @@ -88778,7 +90146,7 @@ index 000000000000..76baca821132 + wifimac->recovery_stat |= WIFINET_RECOVERY_UNDER_CONNECT; + } + //hi_get_irq_status(); -+ //printk("get irq status done\n"); ++ //pr_debug("get irq status done\n"); + wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN, 0); + wifi_mac_fw_recovery(wnet_vif); + hi_get_irq_status(); @@ -88795,7 +90163,7 @@ index 000000000000..76baca821132 + return 0; +} + -+void wifi_mac_connect_repair_task(SYS_TYPE param1,SYS_TYPE param2, SYS_TYPE param3,SYS_TYPE param4,SYS_TYPE param5) ++static void wifi_mac_connect_repair_task(SYS_TYPE param1,SYS_TYPE param2, SYS_TYPE param3,SYS_TYPE param4,SYS_TYPE param5) +{ + struct wifi_mac *wifimac = (struct wifi_mac *) param1; + static unsigned int free_page = 0; @@ -88832,7 +90200,7 @@ index 000000000000..76baca821132 + count++; + if (count == 2) { + -+ AML_OUTPUT("last send %d, current send %d, last done %d, current done %d, last free %d, current free %d, count %d\n", ++ pr_emerg("last send %d, current send %d, last done %d, current done %d, last free %d, current free %d, count %d\n", +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,15,0) && !defined (LINUX_PLATFORM) + send, hif->HiStatus.Tx_Send_num, done, hif->HiStatus.Tx_Done_num, free, hif->HiStatus.Tx_Free_num, count); +#else @@ -88841,10 +90209,11 @@ index 000000000000..76baca821132 + free, atomic_read(&hif->HiStatus.Tx_Free_num), count); +#endif + -+ AML_OUTPUT("last free page %d, current free page %d, tx_ok %d, last tx_ok %d, tx_fail:%d, last_tx_fail:%d\n", ++ pr_emerg("last free page %d, current free page %d, tx_ok %d, last tx_ok %d, tx_fail:%d, last_tx_fail:%d host_wake %hhu\n", + free_page, hal_priv->txPageFreeNum, tx_ok_num, hif->HiStatus.tx_ok_num, tx_fail_num, hif->HiStatus.tx_fail_num); + + count = 0; ++ pr_emerg("will repair connection!\n"); + wifi_mac_connect_repair(wifimac); + } + @@ -88890,7 +90259,7 @@ index 000000000000..76baca821132 + + if (wifimac->recovery_stat & WIFINET_RECOVERY_UNDER_CONNECT) { + wifimac->recovery_stat = WIFINET_RECOVERY_VIF_UP; -+ ++ wnet_vif->vm_mainsta->connect_status = CONNECT_CONNECTING; + os_timer_ex_start(&pwdev_priv->connect_timeout); + wifi_mac_chk_scan(wnet_vif, WIFINET_SCANCFG_ACTIVE| WIFINET_SCANCFG_FLUSH, wnet_vif->vm_des_nssid, wnet_vif->vm_des_ssid); + @@ -88900,7 +90269,7 @@ index 000000000000..76baca821132 + +} + -+unsigned char is_in_recovery(struct wifi_mac *wifimac) ++static unsigned char is_in_recovery(struct wifi_mac *wifimac) +{ + if (wifimac->recovery_stat & WIFINET_RECOVERY_START) { + ; @@ -88909,12 +90278,49 @@ index 000000000000..76baca821132 + return 0; +} + ++extern char dpp_pub_action_str[][50]; ++unsigned char wifi_mac_is_dpp_frame(struct sk_buff *skb, struct wifi_station *sta) ++{ ++ struct wifi_mac_p2p_pub_act_frame *p2p_pub_act = NULL; ++ unsigned char *buf = (unsigned char *)os_skb_data(skb); ++ bool is_dpp_frame = false; ++ ++ p2p_pub_act = (struct wifi_mac_p2p_pub_act_frame *)(buf + sizeof(struct wifi_frame)); ++ ++ if (p2p_pub_act ++ && (p2p_pub_act->category == AML_CATEGORY_PUBLIC) ++ && (p2p_pub_act->action == WIFINET_ACT_PUBLIC_P2P)) { ++ if (p2p_pub_act->oui_type == OUI_TYPE_DPP) { ++ unsigned char dpp_action_subtype = *(buf + sizeof(struct wifi_frame) + 7); ++ if (dpp_action_subtype == 11) { ++ concurrent_channel_protection(sta->sta_wnet_vif, 2000); ++ } ++ ++ if (dpp_action_subtype < 19) { ++ AML_OUTPUT("DPP->%s %d\n", dpp_pub_action_str[dpp_action_subtype], dpp_action_subtype); ++ } else { ++ AML_OUTPUT("subtype:%d\n", dpp_action_subtype); ++ } ++ is_dpp_frame = true; ++ } ++ } ++ ++ if (p2p_pub_act ++ && (p2p_pub_act->category == AML_CATEGORY_PUBLIC) ++ && ((p2p_pub_act->action == WIFINET_ACT_PUBLIC_GAS_REQ) ++ || (p2p_pub_act->action == WIFINET_ACT_PUBLIC_GAS_RSP))) { ++ AML_OUTPUT("gas frame action:%d\n", p2p_pub_act->action); ++ is_dpp_frame = true; ++ } ++ ++ return is_dpp_frame; ++} diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_if.h b/drivers/net/wireless/w1/vmac/wifi_mac_if.h new file mode 100644 -index 000000000000..348c7ff4a8c8 +index 0000000000000000000000000000000000000000..1c06b3d017819ee53a49a646c838f77219f0bd09 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_if.h -@@ -0,0 +1,386 @@ +@@ -0,0 +1,390 @@ +/* + **************************************************************************************** + * @@ -89300,10 +90706,14 @@ index 000000000000..348c7ff4a8c8 +void wifi_mac_fw_recovery(struct wlan_net_vif *wnet_vif); +int wifi_mac_connect_repair(struct wifi_mac *wifimac); + ++void wifi_mac_tx_lock_timer_attach(void); ++void wifi_mac_tx_lock_timer_cancel(void); ++ ++unsigned char wifi_mac_is_dpp_frame(struct sk_buff *skb, struct wifi_station *sta); +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_monitor.c b/drivers/net/wireless/w1/vmac/wifi_mac_monitor.c new file mode 100644 -index 000000000000..24e3f0e9d97e +index 0000000000000000000000000000000000000000..07458e1572a2cef7564fad89847c8fab9ddb6474 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_monitor.c @@ -0,0 +1,448 @@ @@ -89436,7 +90846,7 @@ index 000000000000..24e3f0e9d97e + + DPRINTF(AML_DEBUG_ANY,"<%s>:<%s>:%s\n", wnet_vif->vm_ndev->name,ndev->name,__func__); + -+ dump_memory_internel(skb->data,32); ++ dump_memory_internal(skb->data,32); + return wifi_mac_hardstart(skb, wnet_vif->vm_ndev); +} + @@ -89757,7 +91167,7 @@ index 000000000000..24e3f0e9d97e + diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_monitor.h b/drivers/net/wireless/w1/vmac/wifi_mac_monitor.h new file mode 100644 -index 000000000000..a3ebe1b57218 +index 0000000000000000000000000000000000000000..a3ebe1b5721853c86879005b51bf5524a5b45af6 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_monitor.h @@ -0,0 +1,32 @@ @@ -89795,10 +91205,10 @@ index 000000000000..a3ebe1b57218 +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_p2p.c b/drivers/net/wireless/w1/vmac/wifi_mac_p2p.c new file mode 100644 -index 000000000000..41cc92dbb381 +index 0000000000000000000000000000000000000000..49574e1a9641a699b77c138a8317b61f80f15fa7 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_p2p.c -@@ -0,0 +1,2647 @@ +@@ -0,0 +1,2650 @@ +/* + **************************************************************************************** + * @@ -90085,7 +91495,7 @@ index 000000000000..41cc92dbb381 + return 0; +} + -+int vm_p2p_client_cancle_opps (struct wifi_mac_p2p *p2p) ++int vm_p2p_client_cancel_opps (struct wifi_mac_p2p *p2p) +{ + union type_ctw_opps_u ctw_opps_u; + @@ -90097,14 +91507,14 @@ index 000000000000..41cc92dbb381 +} + + -+int vm_p2p_go_cancle_opps (struct wifi_mac_p2p *p2p) ++int vm_p2p_go_cancel_opps (struct wifi_mac_p2p *p2p) +{ -+ vm_p2p_client_cancle_opps(p2p); ++ vm_p2p_client_cancel_opps(p2p); + vm_p2p_update_noa_ie(p2p); + return 0; +} + -+int vm_p2p_client_cancle_noa (struct wifi_mac_p2p *p2p) ++int vm_p2p_client_cancel_noa (struct wifi_mac_p2p *p2p) +{ + struct p2p_noa noa = {0}; + @@ -90114,9 +91524,9 @@ index 000000000000..41cc92dbb381 + return 0; +} + -+int vm_p2p_go_cancle_noa (struct wifi_mac_p2p *p2p) ++int vm_p2p_go_cancel_noa (struct wifi_mac_p2p *p2p) +{ -+ vm_p2p_client_cancle_noa(p2p); ++ vm_p2p_client_cancel_noa(p2p); + vm_p2p_update_noa_ie(p2p); + return 0; +} @@ -90237,10 +91647,10 @@ index 000000000000..41cc92dbb381 + } + else if (!(p2p->p2p_flag & P2P_NOA_INDEX_INIT_FLAG)) + { -+ AML_PRINT(AML_DBG_MODULES_P2P,"GO cancle noa ie\n"); ++ AML_PRINT(AML_DBG_MODULES_P2P,"GO cancel noa ie\n"); + p2p->p2p_flag |= P2P_NOA_INDEX_INIT_FLAG; -+ vm_p2p_client_cancle_opps(p2p); -+ vm_p2p_client_cancle_noa(p2p); ++ vm_p2p_client_cancel_opps(p2p); ++ vm_p2p_client_cancel_noa(p2p); + } + + return 0; @@ -90329,7 +91739,7 @@ index 000000000000..41cc92dbb381 + if (p2p_noa_start_time_cond(next_tbtt, p2p->noa.start+P2P_NOA_START_TIME_WRAP) + & P2P_NOA_START_IN_PAST) + { -+ printk("%s(%d) noa_len %d, count=%d\n",__func__,__LINE__, ++ pr_debug("%s(%d) noa_len %d, count=%d\n",__func__,__LINE__, + wnet_vif->app_ie[WIFINET_APPIE_FRAME_BEACON].length, p2p->noa.count); + wnet_vif->vm_p2p->noa_index ++; + p2p->noa.start += P2P_NOA_START_TIME_WRAP; @@ -90341,7 +91751,7 @@ index 000000000000..41cc92dbb381 + +#ifdef CONFIG_WFD + -+int vm_wfd_initial(struct wifi_mac_p2p *p2p) ++static int vm_wfd_initial(struct wifi_mac_p2p *p2p) +{ + int res = true; + struct wifi_mac_wfd_info *pwfdinfo = &p2p->wfd_info; @@ -91108,7 +92518,7 @@ index 000000000000..41cc92dbb381 + return false; +} + -+unsigned char vm_get_p2pie_oper_class(struct wifi_mac_p2p *p2p) ++static unsigned char vm_get_p2pie_oper_class(struct wifi_mac_p2p *p2p) +{ + int i = 0, j = 0, k = 0, index = 0, mark = 0; + struct wifi_mac *wifimac = p2p->wnet_vif->vm_wmac; @@ -91175,7 +92585,7 @@ index 000000000000..41cc92dbb381 + return 0; +} + -+void vm_get_p2pie_device_info_addr(struct wifi_mac_p2p *p2p , const unsigned char *frm, unsigned int *len) ++static void vm_get_p2pie_device_info_addr(struct wifi_mac_p2p *p2p , const unsigned char *frm, unsigned int *len) +{ + const unsigned char *p2p_ie; + unsigned int p2p_ielen; @@ -91202,7 +92612,7 @@ index 000000000000..41cc92dbb381 +} + + -+void vm_get_p2pie_listenchannel(struct wifi_mac_p2p *p2p , const unsigned char *frm, unsigned int *len) ++static void vm_get_p2pie_listenchannel(struct wifi_mac_p2p *p2p , const unsigned char *frm, unsigned int *len) +{ + const unsigned char *p2p_ie; + unsigned int p2p_ielen; @@ -91674,14 +93084,14 @@ index 000000000000..41cc92dbb381 + unsigned char *ie = (unsigned char *)frm; + for (i = 0; i < len; i++) + { -+ printk("%02x:", *(ie + i)); ++ pr_debug("%02x:", *(ie + i)); + if (i % 10 == 0) -+ printk("\n"); ++ pr_debug("\n"); + } +} +#endif + -+void vm_get_p2pie_channelList(struct wifi_mac_p2p *p2p, const unsigned char *frm, unsigned int *len, unsigned char tx) ++static void vm_get_p2pie_channelList(struct wifi_mac_p2p *p2p, const unsigned char *frm, unsigned int *len, unsigned char tx) +{ + const unsigned char *p2p_ie; + unsigned int p2p_ielen; @@ -91752,7 +93162,7 @@ index 000000000000..41cc92dbb381 + return; +} + -+int vm_check_p2pie_channelList(struct wifi_mac_p2p *p2p, const unsigned char *frm, unsigned int *len) ++static int vm_check_p2pie_channelList(struct wifi_mac_p2p *p2p, const unsigned char *frm, unsigned int *len) +{ + const unsigned char *p2p_ie; + unsigned int p2p_ielen; @@ -91809,7 +93219,7 @@ index 000000000000..41cc92dbb381 + return false; +} + -+unsigned int vm_get_p2pie_len(struct wifi_mac_p2p *p2p, const unsigned char *frm, unsigned int *len, enum p2p_attr_id id) ++static unsigned int vm_get_p2pie_len(struct wifi_mac_p2p *p2p, const unsigned char *frm, unsigned int *len, enum p2p_attr_id id) +{ + const unsigned char *p2p_ie; + unsigned int p2p_ielen; @@ -91842,7 +93252,7 @@ index 000000000000..41cc92dbb381 + if ((wnet_vif != NULL) && (wnet_vif->vm_p2p_support)) { + p2p = wnet_vif->vm_p2p; + p2p->p2p_negotiation_state = status; -+ printk("%s p2p_negotiation_state:%d\n", __func__, p2p->p2p_negotiation_state); ++ pr_debug("%s p2p_negotiation_state:%d\n", __func__, p2p->p2p_negotiation_state); + } +} + @@ -91858,7 +93268,7 @@ index 000000000000..41cc92dbb381 + && (p2p->p2p_negotiation_state < NET80211_P2P_STATE_GO_COMPLETE)) { + return 1; + } -+ printk("%s p2p_negotiation_state:%d\n", __func__, p2p->p2p_negotiation_state); ++ pr_debug("%s p2p_negotiation_state:%d\n", __func__, p2p->p2p_negotiation_state); + } + + return 0; @@ -91896,7 +93306,7 @@ index 000000000000..41cc92dbb381 +} + + -+void vm_p2p_switch_nego_state(struct wifi_mac_p2p *p2p, struct wifi_mac_p2p_pub_act_frame *frm, unsigned char tx, int *len) ++static void vm_p2p_switch_nego_state(struct wifi_mac_p2p *p2p, struct wifi_mac_p2p_pub_act_frame *frm, unsigned char tx, int *len) +{ + unsigned int chanList_len = vm_get_p2pie_len(p2p, (const unsigned char *)frm->elts, len, P2P_ATTR_CHANNEL_LIST); + struct wifi_mac *wifimac = p2p->wnet_vif->vm_wmac; @@ -91955,7 +93365,7 @@ index 000000000000..41cc92dbb381 + { + p2p->p2p_negotiation_state = NET80211_P2P_STATE_GONEGO_CONF; + if (vm_get_wfd_ie(frm->elts, *len - 8, NULL, &tmplen)) { -+ printk("invite rsp set is_miracast_connect 1\n"); ++ pr_debug("invite rsp set is_miracast_connect 1\n"); + wifimac->is_miracast_connect = 1; + } + }else { @@ -92037,7 +93447,7 @@ index 000000000000..41cc92dbb381 + memset(p2p->peer_dev_addr, 0 , MAX_MAC_BUF_LEN); + if (0 == *(frm->elts + 9)) { + if (vm_get_wfd_ie(frm->elts, *len - 8, NULL, &tmplen)) { -+ printk("conf set is_miracast_connect 1\n"); ++ pr_debug("conf set is_miracast_connect 1\n"); + wifimac->is_miracast_connect = 1; + } + } @@ -92076,7 +93486,7 @@ index 000000000000..41cc92dbb381 + is_p2p_frame = true; + buflen += sprintf(printbuf+buflen, "%s>%s dialog_token=%d", tx?"tx":"rx", + p2p_public_action_tmp[p2p_pub_act->subtype], p2p_pub_act->dialog_token); -+ printk("%s\n", printbuf); ++ pr_debug("%s\n", printbuf); + + } else { + AML_PRINT(AML_DBG_MODULES_P2P,"p2p_public_action not p2p action\n"); @@ -92291,7 +93701,7 @@ index 000000000000..41cc92dbb381 + cfg80211_remain_on_channel_expired(p2p->wnet_vif->vm_wdev, p2p->remain_on_ch_cookie, + &p2p->remain_on_ch_channel, GFP_KERNEL); + -+ DPRINTF(AML_DEBUG_CFG80211, "%s %d <%s> cancle WIFINET_F_NOSCAN\n", ++ DPRINTF(AML_DEBUG_CFG80211, "%s %d <%s> cancel WIFINET_F_NOSCAN\n", + __func__, __LINE__, VMAC_DEV_NAME(p2p->wnet_vif)); + } + @@ -92331,7 +93741,7 @@ index 000000000000..41cc92dbb381 + int index = 0; + struct wlan_net_vif *wnet_vif = p2p->wnet_vif; + -+ printk("%s\n", __func__); ++ pr_debug("%s\n", __func__); +#ifdef CONFIG_WFD + vm_wfd_initial(p2p); +#endif //CONFIG_WFD @@ -92430,6 +93840,9 @@ index 000000000000..41cc92dbb381 + if ((p2p->p2p_role == NET80211_P2P_ROLE_CLIENT) || (p2p->p2p_role == NET80211_P2P_ROLE_GO)) + { + vm_p2p_set_enable(p2p, 1); ++ if (p2p->p2p_role == NET80211_P2P_ROLE_GO) { ++ p2p->p2p_negotiation_state = NET80211_P2P_STATE_GO_COMPLETE; ++ } + } + return 0; +} @@ -92448,10 +93861,10 @@ index 000000000000..41cc92dbb381 +#endif //CONFIG_P2P diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_p2p.h b/drivers/net/wireless/w1/vmac/wifi_mac_p2p.h new file mode 100644 -index 000000000000..a2211c15700b +index 0000000000000000000000000000000000000000..866e7ee1a00fa0f6c0f1494366a9167758aa1627 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_p2p.h -@@ -0,0 +1,510 @@ +@@ -0,0 +1,512 @@ +/* + **************************************************************************************** + * @@ -92832,12 +94245,14 @@ index 000000000000..a2211c15700b + unsigned int raw_action_pkt_len; + enum wifi_mac_tx_status_mode tx_status_flag; + unsigned long long cookie; ++ struct wifi_channel *action_chan; + struct channel_list peer_chan_list; + struct channel_list self_chan_list; + unsigned char peer_listen_channel; + unsigned char peer_dev_addr[MAX_MAC_BUF_LEN]; + unsigned char ap_mode_set_noa_enable; + unsigned char wfd_session_id[MAC_WFD_SESSION_LEN]; ++ unsigned char go_hidden_mode; +}; + +static inline void vm_p2p_set_enable(struct wifi_mac_p2p *p2p, int enable) @@ -92918,14 +94333,14 @@ index 000000000000..a2211c15700b +} +#endif + -+int vm_p2p_go_cancle_opps (struct wifi_mac_p2p *p2p); -+int vm_p2p_go_cancle_noa (struct wifi_mac_p2p *p2p); -+int vm_p2p_client_cancle_opps (struct wifi_mac_p2p *p2p); ++int vm_p2p_go_cancel_opps (struct wifi_mac_p2p *p2p); ++int vm_p2p_go_cancel_noa (struct wifi_mac_p2p *p2p); ++int vm_p2p_client_cancel_opps (struct wifi_mac_p2p *p2p); +int vm_p2p_opps_start(struct wifi_mac_p2p *p2p, const union type_ctw_opps_u *ctw_opps_u); +int vm_p2p_noa_start(struct wifi_mac_p2p *p2p, const struct p2p_noa *noa); +unsigned char is_need_process_p2p_action(unsigned char* buf); +int vm_p2p_parse_negotiation_frames(struct wifi_mac_p2p *p2p, const unsigned char *frm, unsigned int *len, unsigned char tx); -+int vm_p2p_client_cancle_noa (struct wifi_mac_p2p *p2p); ++int vm_p2p_client_cancel_noa (struct wifi_mac_p2p *p2p); +void vm_change_p2pie_channel(struct wifi_mac_p2p *p2p , const unsigned char *frm, unsigned int *len); +int vm_p2p_update_noa_ie (struct wifi_mac_p2p *p2p); +void vm_change_p2pie_listenchannel(struct wifi_mac_p2p *p2p , const unsigned char *frm, unsigned int len); @@ -92964,7 +94379,7 @@ index 000000000000..a2211c15700b + diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_pmf.c b/drivers/net/wireless/w1/vmac/wifi_mac_pmf.c new file mode 100644 -index 000000000000..fc4665878dba +index 0000000000000000000000000000000000000000..e50ef8252c9a037a111a9bb534e3ce34187a9f9c --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_pmf.c @@ -0,0 +1,676 @@ @@ -92980,7 +94395,7 @@ index 000000000000..fc4665878dba +void wifi_mac_disable_hw_mgmt_decrypt(void) { + unsigned int reg_val; + -+ printk("%s\n", __func__); ++ pr_debug("%s\n", __func__); + reg_val = fi_ahb_read(0x0a000308); + fi_ahb_write(0x0a000308, reg_val | BIT(28)); + @@ -93003,7 +94418,7 @@ index 000000000000..fc4665878dba + fi_ahb_write(0x0a000354, reg_val | BIT(28)); +} + -+unsigned char _bip_ccmp_protect(const unsigned char *key, size_t key_len, ++static unsigned char _bip_ccmp_protect(const unsigned char *key, size_t key_len, + const unsigned char *data, size_t data_len, unsigned char *mic) +{ + unsigned char res = 1; @@ -93011,24 +94426,24 @@ index 000000000000..fc4665878dba + if (key_len == 16) { + if (omac1_aes_128(key, data, data_len, mic)) { + res = 0; -+ printk("%s : omac1_aes_128 fail!", __func__); ++ pr_err("%s : omac1_aes_128 fail!", __func__); + } + + } else if (key_len == 32) { + if (omac1_aes_256(key, data, data_len, mic)) { + res = 0; -+ printk("%s : omac1_aes_256 fail!", __func__); ++ pr_err("%s : omac1_aes_256 fail!", __func__); + } + + } else { -+ printk("%s : key_len not match!", __func__); ++ pr_warn("%s : key_len not match!", __func__); + res = 0; + } + + return res; +} + -+unsigned char aml_calculate_bip_mic(unsigned char gmcs, unsigned char *whdr_pos, int len, ++static unsigned char aml_calculate_bip_mic(unsigned char gmcs, unsigned char *whdr_pos, int len, + const unsigned char *key, const unsigned char *data, size_t data_len, unsigned char *mic) +{ + unsigned char res = 1; @@ -93036,40 +94451,40 @@ index 000000000000..fc4665878dba + if (gmcs == WIFINET_CIPHER_AES_CMAC) { + if (_bip_ccmp_protect(key, 16, data, data_len, mic) == 0) { + res = 0; -+ printk("%s : _bip_ccmp_protect(128) fail!", __func__); ++ pr_err("%s : _bip_ccmp_protect(128) fail!", __func__); + } + + } else { + res = 0; -+ printk("%s : unsupport dot11wCipher !\n", __func__); ++ pr_err("%s : unsupport dot11wCipher !\n", __func__); + } + + return res; +} + -+void wifi_mac_dump_pkt(void *pkt, unsigned short pkt_len) { ++static void wifi_mac_dump_pkt(void *pkt, unsigned short pkt_len) { + int pp; + int len = pkt_len; + unsigned char *frm = (unsigned char *)pkt; + -+ printk("pktlen = %d\n", pkt_len); ++ pr_debug("pktlen = %d\n", pkt_len); + for (pp = 0; pp < pkt_len; pp++) { + if ((len > 6) && (pp < 4)) { -+ printk("%02x:%02x:%02x:%02x", frm[pp], frm[pp + 1], frm[pp + 2], frm[pp + 3]); ++ pr_debug("%02x:%02x:%02x:%02x", frm[pp], frm[pp + 1], frm[pp + 2], frm[pp + 3]); + len -= 4; + pp += 3; + + } else if (len > 6) { -+ printk("%02x:%02x:%02x:%02x:%02x:%02x", ++ pr_debug("%02x:%02x:%02x:%02x:%02x:%02x", + frm[pp], frm[pp + 1], frm[pp + 2], frm[pp + 3], frm[pp + 4], frm[pp + 5]); + len -= 6; + pp += 5; + + } else { -+ printk("%02x ", frm[pp]); ++ pr_debug("%02x ", frm[pp]); + } + } -+ printk("\n"); ++ pr_debug("\n"); +} + +int wifi_mac_parse_mmie(struct wifi_station *sta, struct sk_buff *skb, unsigned char subtype) @@ -93102,7 +94517,7 @@ index 000000000000..fc4665878dba + + #ifdef PMF_PKT_PRINT + /* dump the packet content before decrypt */ -+ printk("before parse:%d\n", skb->len); ++ pr_debug("before parse:%d\n", skb->len); + wifi_mac_dump_pkt(frm, skb->len); + #endif + @@ -93158,11 +94573,11 @@ index 000000000000..fc4665878dba + memcpy(bip_aad + 8, wh->i_addr2, 6); + memcpy(bip_aad + 14, wh->i_addr3, 6); + -+ printk("%s bip_add before\n", __func__); ++ pr_debug("%s bip_add before\n", __func__); + for (i = 0; i < ori_len; ++i) { -+ printk("%02x", bip_aad[i]); ++ pr_debug("%02x", bip_aad[i]); + } -+ printk("\n"); ++ pr_debug("\n"); + + if (aml_calculate_bip_mic(sta->pmf_key.wk_key_type, frm, + pkt_len, sta->pmf_key.wk_key, bip_aad, ori_len, mic) == 0) @@ -93178,7 +94593,7 @@ index 000000000000..fc4665878dba + + #ifdef PMF_PKT_PRINT + /* dump the packet content before decrypt */ -+ printk("after parse:%d\n", skb->len); ++ pr_debug("after parse:%d\n", skb->len); + wifi_mac_dump_pkt(frm, skb->len); + #endif + @@ -93188,7 +94603,7 @@ index 000000000000..fc4665878dba + return res; +} + -+int aml_aes_decrypt(struct wifi_station *sta, struct sk_buff *skb, unsigned char key_index) ++static int aml_aes_decrypt(struct wifi_station *sta, struct sk_buff *skb, unsigned char key_index) +{ + unsigned char *frm; + unsigned char *key; @@ -93225,7 +94640,7 @@ index 000000000000..fc4665878dba + return 0; +} + -+int aml_pkt_decrypt(struct wifi_station *sta, struct sk_buff *skb) ++static int aml_pkt_decrypt(struct wifi_station *sta, struct sk_buff *skb) +{ + int res = 0; + unsigned char hdr_len = sizeof(struct wifi_frame); @@ -93287,7 +94702,7 @@ index 000000000000..fc4665878dba + frm = (unsigned char *)&wh[1]; + is_bmc = (WIFINET_IS_MULTICAST(wh->i_addr1)); + -+ //printk("%s recv :%d\n", __func__, subtype); ++ //pr_debug("%s recv :%d\n", __func__, subtype); + switch (wnet_vif->vm_opmode) { + case WIFINET_M_STA: + if ((is_bmc) && (subtype != WIFINET_FC0_SUBTYPE_BEACON)) { @@ -93297,7 +94712,7 @@ index 000000000000..fc4665878dba + if ((subtype == WIFINET_FC0_SUBTYPE_DEAUTH) || (subtype == WIFINET_FC0_SUBTYPE_DISASSOC)) { + if (!(sta->sta_flags_ext & WIFINET_NODE_MFP_CONFIRM_DEAUTH)) { + reason = le16toh(*(unsigned short *)frm); -+ printk("%s recv deauthenticate (reason %d)\n", __func__, reason); ++ pr_debug("%s recv deauthenticate (reason %d)\n", __func__, reason); + + wifi_mac_send_sa_query(sta, WIFINET_ACTION_SA_QUERY_REQ, sta->sa_query_seq++); + os_timer_ex_start_period(&wnet_vif->vm_actsend, 100); @@ -93388,7 +94803,7 @@ index 000000000000..fc4665878dba + + #ifdef PMF_PKT_PRINT + /* dump the packet content before decrypt */ -+ printk("rsn_ucastcipher:%d\n", sta->sta_rsn.rsn_ucastcipher); ++ pr_debug("rsn_ucastcipher:%d\n", sta->sta_rsn.rsn_ucastcipher); + wifi_mac_dump_pkt(frm, skb->len); + #endif + @@ -93408,12 +94823,12 @@ index 000000000000..fc4665878dba + + #ifdef PMF_PKT_PRINT + /* print packet content after decryption */ -+ printk("after decrypt\n"); ++ pr_debug("after decrypt\n"); + wifi_mac_dump_pkt(frm, skb->len); + #endif + + if (is_bmc) { -+ printk("parse mmie for broadcast mgmt pkt\n"); ++ pr_debug("parse mmie for broadcast mgmt pkt\n"); + if (wifi_mac_parse_mmie(sta, skb, subtype) != 1) { + goto fail; + } @@ -93447,7 +94862,7 @@ index 000000000000..fc4665878dba + ERROR_DEBUG_OUT("bip alloc fail\n"); + return 1; + } -+ printk("%s len:%d, frame_body_len:%d\n", __func__, skb->len, frame_body_len); ++ pr_debug("%s len:%d, frame_body_len:%d\n", __func__, skb->len, frame_body_len); + + { + /* broadcast robust mgmt frame, using BIP */ @@ -93471,7 +94886,7 @@ index 000000000000..fc4665878dba + + #ifdef PMF_PKT_PRINT + /* dump the packet content before decrypt */ -+ printk("before add aad:%d\n", skb->len); ++ pr_debug("before add aad:%d\n", skb->len); + wifi_mac_dump_pkt(frm, skb->len); + #endif + @@ -93501,7 +94916,7 @@ index 000000000000..fc4665878dba + + /* dump total packet include MME with zero MIC */ + #if 0 -+ printk("bip_aad:%d\n", ori_len); ++ pr_debug("bip_aad:%d\n", ori_len); + wifi_mac_dump_pkt(bip_add, ori_len); + #endif + @@ -93513,10 +94928,10 @@ index 000000000000..fc4665878dba + /* dump calculated mic result */ + if (0) { + int i; -+ printk("Calculated mic result: "); ++ pr_debug("Calculated mic result: "); + for (i = 0; i < 16; i++) -+ printk(" %02x ", mic[i]); -+ printk("\n"); ++ pr_debug(" %02x ", mic[i]); ++ pr_debug("\n"); + } + + frm_end = frm + skb->len; @@ -93527,7 +94942,7 @@ index 000000000000..fc4665878dba + memcpy(frm_end - 16, mic, 16); + + #ifdef PMF_PKT_PRINT -+ printk("after add mic:%d\n", skb->len); ++ pr_debug("after add mic:%d\n", skb->len); + wifi_mac_dump_pkt(frm, skb->len); + #endif + } @@ -93540,7 +94955,7 @@ index 000000000000..fc4665878dba + return 1; +} + -+int _aml_ccmp_encrypt(struct wifi_mac_key *key, unsigned char *pn, unsigned int hdrlen, unsigned char *frame, uint plen) ++static int _aml_ccmp_encrypt(struct wifi_mac_key *key, unsigned char *pn, unsigned int hdrlen, unsigned char *frame, uint plen) +{ + unsigned char *enc = NULL; + size_t enc_len = 0; @@ -93600,7 +95015,7 @@ index 000000000000..fc4665878dba + + #ifdef PMF_PKT_PRINT + /* dump the packet content before decrypt */ -+ printk("before encrypt rsn_ucastcipher:%d\n", sta->sta_rsn.rsn_ucastcipher); ++ pr_debug("before encrypt rsn_ucastcipher:%d\n", sta->sta_rsn.rsn_ucastcipher); + wifi_mac_dump_pkt(frm, skb->len); + #endif + @@ -93620,11 +95035,11 @@ index 000000000000..fc4665878dba + + PN = (unsigned long long *)pn; + (*PN)++; -+ //printk("PN is %016x, pn[0]:%02x, pn[7]:%02x\n", *PN, pn[0], pn[7]); ++ //pr_debug("PN is %016x, pn[0]:%02x, pn[7]:%02x\n", *PN, pn[0], pn[7]); + + #ifdef PMF_PKT_PRINT + /* dump the packet content before decrypt */ -+ printk("after encrypt:\n"); ++ pr_debug("after encrypt:\n"); + wifi_mac_dump_pkt(frm, skb->len); + #endif + @@ -93638,7 +95053,7 @@ index 000000000000..fc4665878dba + arg.action = action; + arg.arg1 = seq; + -+ printk("%s sta:%p, action:%d\n", __func__, sta, action); ++ pr_debug("%s sta:%p, action:%d\n", __func__, sta, action); + wifi_mac_send_actionframe(sta->sta_wnet_vif, sta, &arg); + return 0; +} @@ -93646,7 +95061,7 @@ index 000000000000..fc4665878dba +#endif//AML_WPA3 diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_pmf.h b/drivers/net/wireless/w1/vmac/wifi_mac_pmf.h new file mode 100644 -index 000000000000..9c051dc0dd93 +index 0000000000000000000000000000000000000000..9c051dc0dd93d5f37f0361ba0475685ea11a3f09 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_pmf.h @@ -0,0 +1,91 @@ @@ -93743,10 +95158,10 @@ index 000000000000..9c051dc0dd93 +#endif//_WIFI_MAC_PMF_H_ diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_power.c b/drivers/net/wireless/w1/vmac/wifi_mac_power.c new file mode 100644 -index 000000000000..65cbcf63b6d2 +index 0000000000000000000000000000000000000000..6c2fb338fc064daffaf48a3b60a2aa9e0a3c4951 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_power.c -@@ -0,0 +1,1861 @@ +@@ -0,0 +1,1903 @@ +/* + **************************************************************************************** + * @@ -93793,7 +95208,7 @@ index 000000000000..65cbcf63b6d2 + + if (wnet_vif->vm_mainsta == NULL) + { -+ printk("%s:%d, vm_mainsta is null, cancle sleep this time \n", __func__, __LINE__); ++ pr_err("%s:%d, vm_mainsta is null, cancel sleep this time \n", __func__, __LINE__); + os_timer_ex_start(&wnet_vif->vm_pwrsave.ips_timer_presleep); + return; + } @@ -93858,7 +95273,7 @@ index 000000000000..65cbcf63b6d2 +{ + struct wlan_net_vif *wnet_vif = (struct wlan_net_vif *)param1; + -+ wifi_mac_pwrsave_sleep_wait_cancle(wnet_vif); ++ wifi_mac_pwrsave_sleep_wait_cancel(wnet_vif); + wifi_mac_pwrsave_wakeup(wnet_vif, WKUP_FROM_TRANSMIT); + + if ((wnet_vif->vm_opmode == WIFINET_M_STA) && (wnet_vif->vm_state == WIFINET_S_CONNECTED)) @@ -93866,7 +95281,7 @@ index 000000000000..65cbcf63b6d2 +#ifdef CONFIG_P2P + if (wnet_vif->vm_p2p->p2p_flag & P2P_OPPPS_START_FLAG_HI) + { -+ vm_p2p_client_cancle_opps(wnet_vif->vm_p2p); ++ vm_p2p_client_cancel_opps(wnet_vif->vm_p2p); + } +#endif + } @@ -93964,7 +95379,7 @@ index 000000000000..65cbcf63b6d2 + return OS_TIMER_NOT_REARMED; +} + -+void wifi_mac_pwrsave_sleep_wait_cancle (struct wlan_net_vif *wnet_vif) ++void wifi_mac_pwrsave_sleep_wait_cancel (struct wlan_net_vif *wnet_vif) +{ + WIFINET_PWRSAVE_LOCK(wnet_vif); + if (wnet_vif->vm_pwrsave.ips_flag_waitbeacon_timer_start) @@ -94079,7 +95494,7 @@ index 000000000000..65cbcf63b6d2 +#ifdef CONFIG_P2P + if (wnet_vif->vm_p2p->p2p_flag & P2P_OPPPS_START_FLAG_HI) + { -+ vm_p2p_client_cancle_opps(wnet_vif->vm_p2p); ++ vm_p2p_client_cancel_opps(wnet_vif->vm_p2p); + } +#endif + } @@ -94123,7 +95538,7 @@ index 000000000000..65cbcf63b6d2 + + if (wnet_vif->vm_state == WIFINET_S_CONNECTED && wifimac->wm_syncbeacon == 0) + { -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + wifi_mac_beacon_sync(wifimac->drv_priv->wmac, wnet_vif->wnet_vif_id); + } + @@ -94456,7 +95871,7 @@ index 000000000000..65cbcf63b6d2 + unsigned int qlen_real = WIFINET_SAVEQ_QLEN(pstxqueue); + + if (qlen_real) { -+ printk("%s qlen_real:%d\n", __func__, qlen_real); ++ pr_debug("%s qlen_real:%d\n", __func__, qlen_real); + } + + while (qlen_real) @@ -94494,13 +95909,30 @@ index 000000000000..65cbcf63b6d2 + +int wifi_mac_buffer_txq_send(struct sk_buff_head *txqueue) +{ -+ struct sk_buff *skb = NULL; ++ struct sk_buff *skb = NULL, *tmp; + struct wifi_station *sta; + struct wifi_mac *wifimac; + unsigned int qlen_real = WIFINET_SAVEQ_QLEN(txqueue); + if (qlen_real == 0) { + return qlen_real; + } ++ ++ WIFINET_SAVEQ_LOCK(txqueue); ++ skb_queue_walk_safe(txqueue,skb,tmp) { ++ sta = os_skb_get_nsta(skb); ++ if (!sta_find_in_sta_tbl(sta)) { ++ AML_OUTPUT("not find sta: %p free skb\n",sta); ++ aml_skb_unlink(skb,txqueue); ++ wifi_mac_free_skb(skb); ++ } ++ } ++ ++ qlen_real = WIFINET_SAVEQ_QLEN(txqueue); ++ WIFINET_SAVEQ_UNLOCK(txqueue); ++ ++ if (qlen_real == 0) { ++ return qlen_real; ++ } +#ifdef CONFIG_CONCURRENT_MODE + skb = WIFINET_SAVEQ_GET_TAIL(txqueue); + if (skb) { @@ -94638,7 +96070,7 @@ index 000000000000..65cbcf63b6d2 + + if (send_trigger == 1) + { -+ printk("%s:%d, send uapsd trigger\n", __func__, __LINE__); ++ pr_debug("%s:%d, send uapsd trigger\n", __func__, __LINE__); + wifi_mac_send_qosnulldata_as_trigger(sta, qosinfo); + } + return OS_TIMER_REARMED; @@ -95066,7 +96498,7 @@ index 000000000000..65cbcf63b6d2 + { + wifi_mac_send_nulldata_for_ap(sta, 0, 0, 0, 0); + wnet_vif->vif_sts.sts_tx_ps_no_data++; -+ printk("tx null for pspoll\n"); ++ pr_debug("tx null for pspoll\n"); + } + qlen = 0; + break; @@ -95187,7 +96619,7 @@ index 000000000000..65cbcf63b6d2 + "ps-poll %s","unassociated station"); + wnet_vif->vif_sts.sts_rx_ps_uncnnt++; + arg = WIFINET_REASON_NOT_ASSOCED; -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + wifi_mac_send_mgmt(sta, WIFINET_FC0_SUBTYPE_DEAUTH, (void *)&arg); + return; + } @@ -95199,7 +96631,7 @@ index 000000000000..65cbcf63b6d2 + "ps-poll aid mismatch: sta aid 0x%x poll aid 0x%x", sta->sta_associd, aid); + wnet_vif->vif_sts.sts_rx_ps_aid_err++; + arg = WIFINET_REASON_NOT_ASSOCED; -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + wifi_mac_send_mgmt(sta, WIFINET_FC0_SUBTYPE_DEAUTH, (void *)&arg); + return; + } @@ -95290,7 +96722,7 @@ index 000000000000..65cbcf63b6d2 + DPRINTF(AML_DEBUG_PWR_SAVE, "%s %d rx nsta trigger tid=%d ac=%d\n", + __func__,__LINE__, tid, ac); + */ -+ printk("rx uapsd trigger\n"); ++ pr_debug("rx uapsd trigger\n"); + + frame_seq = le16toh(*(unsigned short *)qwh->i_seq); + if ((qwh->i_fc[1] & WIFINET_FC1_RETRY) && @@ -95404,7 +96836,7 @@ index 000000000000..65cbcf63b6d2 + return 0; +} + -+int wifi_mac_pwrsave_wow_suspend(SYS_TYPE param1, ++void wifi_mac_pwrsave_wow_suspend(SYS_TYPE param1, + SYS_TYPE param2,SYS_TYPE param3, + SYS_TYPE param4,SYS_TYPE param5) +{ @@ -95415,12 +96847,12 @@ index 000000000000..65cbcf63b6d2 + int listen_interval = 0, connect = 0; + unsigned int filter = 0, cnt = 0; + -+ printk("%s:%d\n", __func__, __LINE__); ++ pr_debug("%s:%d\n", __func__, __LINE__); + WIFINET_PWRSAVE_MUTEX_LOCK(wnet_vif); + if (wifimac->wm_suspend_mode == WIFI_SUSPEND_STATE_WOW) + { + WIFINET_PWRSAVE_MUTEX_UNLOCK(wnet_vif); -+ return 0; ++ return; + } + + DPRINTF(AML_DEBUG_PWR_SAVE, "<%s>:%s %d scan abort when host suspend \n", @@ -95437,7 +96869,7 @@ index 000000000000..65cbcf63b6d2 + wnet_vif->vm_ndev->name); + wnet_vif->vm_scan_hang = 0; + WIFINET_PWRSAVE_MUTEX_UNLOCK(wnet_vif); -+ return -1; ++ return; + } + } + @@ -95456,7 +96888,7 @@ index 000000000000..65cbcf63b6d2 + */ + wnet_vif->vm_scan_hang = 0; + WIFINET_PWRSAVE_MUTEX_UNLOCK(wnet_vif); -+ return -EINVAL; ++ return; + #endif + } + @@ -95485,7 +96917,7 @@ index 000000000000..65cbcf63b6d2 + listen_interval = wnet_vif_tmp->vm_bcn_intval * wnet_vif_tmp->vm_dtim_period; + else + listen_interval = wnet_vif_tmp->vm_bcn_intval; -+ wifimac->drv_priv->drv_ops.Phy_beaconinit(wifimac->drv_priv,wnet_vif_tmp->wnet_vif_id, listen_interval); ++ wifimac->drv_priv->drv_ops.Phy_beaconinit(wifimac->drv_priv,wnet_vif_tmp->wnet_vif_id, (1<<16) | listen_interval); + + /* change beacon miss timer period */ + wifi_mac_set_beacon_miss_ex(wnet_vif_tmp, ENABLE, WIFINET_BCNMISS_TIME/* period, ms*/); @@ -95505,7 +96937,7 @@ index 000000000000..65cbcf63b6d2 + if (wnet_vif->wnet_vif_id == 1) + { + WIFINET_PWRSAVE_MUTEX_UNLOCK(wnet_vif); -+ return 0; ++ return; + } + wifimac->drv_priv->drv_ops.drv_set_suspend(wifimac->drv_priv, wnet_vif->wnet_vif_id, ENABLE, + WIFI_SUSPEND_STATE_WOW, filter); @@ -95518,10 +96950,10 @@ index 000000000000..65cbcf63b6d2 + wifimac->wm_suspend_mode = WIFI_SUSPEND_STATE_WOW; + + WIFINET_PWRSAVE_MUTEX_UNLOCK(wnet_vif); -+ return 0; ++ return; +} + -+int wifi_mac_pwrsave_wow_resume(SYS_TYPE param1, ++void wifi_mac_pwrsave_wow_resume(SYS_TYPE param1, + SYS_TYPE param2,SYS_TYPE param3, + SYS_TYPE param4,SYS_TYPE param5) +{ @@ -95531,12 +96963,12 @@ index 000000000000..65cbcf63b6d2 + int connect = 0; + int ret = 0; + -+ printk("%s:%d\n", __func__, __LINE__); ++ pr_debug("%s:%d\n", __func__, __LINE__); + WIFINET_PWRSAVE_MUTEX_LOCK(wnet_vif); + if (wifimac->wm_suspend_mode == WIFI_SUSPEND_STATE_NONE) + { + WIFINET_PWRSAVE_MUTEX_UNLOCK(wnet_vif); -+ return 0; ++ return; + } + + list_for_each_entry_safe(wnet_vif_tmp, wnet_vif_next, &wifimac->wm_wnet_vifs, vm_next) @@ -95579,7 +97011,7 @@ index 000000000000..65cbcf63b6d2 + WIFINET_PWRSAVE_MUTEX_UNLOCK(wnet_vif); + wnet_vif->vm_scan_hang = 0; + netif_wake_queue(wnet_vif->vm_ndev); -+ return 0; ++ return ; + } + wifimac->drv_priv->drv_ops.drv_set_suspend(wifimac->drv_priv, wnet_vif->wnet_vif_id, DISABLE, + WIFI_SUSPEND_STATE_NONE, 0); @@ -95595,7 +97027,7 @@ index 000000000000..65cbcf63b6d2 + WIFINET_PWRSAVE_MUTEX_UNLOCK(wnet_vif); + wnet_vif->vm_scan_hang = 0; + netif_wake_queue(wnet_vif->vm_ndev); -+ return 0; ++ return ; +} + +int wifi_mac_pwrsave_wow_check(struct wlan_net_vif *wnet_vif) @@ -95608,12 +97040,37 @@ index 000000000000..65cbcf63b6d2 + } + return 0; +} ++ ++unsigned char sta_find_in_sta_tbl(struct wifi_station *find_sta) ++{ ++ unsigned char vid; ++ struct wifi_station *sta, *sta_next; ++ struct wifi_station_tbl *vm_sta_tbl = NULL; ++ struct drv_private *drv_priv = drv_get_drv_priv(); ++ ++ for (vid = 0; vid < WIFI_MAX_VID; ++vid) ++ { ++ vm_sta_tbl = &drv_priv->drv_wnet_vif_table[vid]->vm_sta_tbl; ++ WIFINET_NODE_LOCK(vm_sta_tbl); ++ list_for_each_entry_safe(sta, sta_next, &vm_sta_tbl->nt_nsta, sta_list) ++ { ++ if (find_sta == sta) ++ { ++ WIFINET_NODE_UNLOCK(vm_sta_tbl); ++ return 1; ++ } ++ } ++ WIFINET_NODE_UNLOCK(vm_sta_tbl); ++ } ++ ++ return 0; ++} diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_power.h b/drivers/net/wireless/w1/vmac/wifi_mac_power.h new file mode 100644 -index 000000000000..8e4b6ad3dc5a +index 0000000000000000000000000000000000000000..be4ef3db4c956b7db1a558333423572fbd188395 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_power.h -@@ -0,0 +1,252 @@ +@@ -0,0 +1,253 @@ +/* + **************************************************************************************** + * @@ -95819,7 +97276,7 @@ index 000000000000..8e4b6ad3dc5a + +void wifi_mac_pwrsave_set_tim(struct wifi_station *sta, int set); +void wifi_mac_pwrsave_restore_sleep(struct wlan_net_vif *wnet_vif); -+void wifi_mac_pwrsave_sleep_wait_cancle (struct wlan_net_vif *wnet_vif); ++void wifi_mac_pwrsave_sleep_wait_cancel (struct wlan_net_vif *wnet_vif); +int wifi_mac_pwrsave_wkup_and_NtfyAp (struct wlan_net_vif *wnet_vif, enum wifinet_ps_wk_reason reason); +int wifi_mac_pwrsave_fullsleep(struct wlan_net_vif *wnet_vif, enum wifinet_ps_sleep_reason reason); +int wifi_mac_pwrsave_wakeup(struct wlan_net_vif *wnet_vif, enum wifinet_ps_wk_reason reason); @@ -95850,10 +97307,10 @@ index 000000000000..8e4b6ad3dc5a +void wifi_mac_pwrsave_eosp_indicate(void* nsta, struct sk_buff * skbbuf, int txok); +void wifi_mac_pwrsave_send_pspoll(struct wifi_station *); + -+int wifi_mac_pwrsave_wow_suspend(SYS_TYPE param1, ++void wifi_mac_pwrsave_wow_suspend(SYS_TYPE param1, + SYS_TYPE param2,SYS_TYPE param3, + SYS_TYPE param4,SYS_TYPE param5); -+int wifi_mac_pwrsave_wow_resume(SYS_TYPE param1, ++void wifi_mac_pwrsave_wow_resume(SYS_TYPE param1, + SYS_TYPE param2,SYS_TYPE param3, + SYS_TYPE param4,SYS_TYPE param5); +int wifi_mac_pwrsave_wow_usr(struct wlan_net_vif *wnet_vif, @@ -95865,13 +97322,14 @@ index 000000000000..8e4b6ad3dc5a +void wifi_mac_pwrsave_sleep_wait_ex(SYS_TYPE param1, + SYS_TYPE param2,SYS_TYPE param3,SYS_TYPE param4,SYS_TYPE param5); +void wifi_mac_send_nulldata_retry(void * data); ++unsigned char sta_find_in_sta_tbl(struct wifi_station *find_sta); +#endif /* _NET80211_IEEE80211_POWER_H_ */ diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_rate.c b/drivers/net/wireless/w1/vmac/wifi_mac_rate.c new file mode 100644 -index 000000000000..b529c92bc06a +index 0000000000000000000000000000000000000000..b3fc8b7e59c72e6e0ae200258c54178fa2587be2 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_rate.c -@@ -0,0 +1,914 @@ +@@ -0,0 +1,929 @@ +#include "wifi_mac_com.h" + +void wifi_mac_ap_set_basic_rates(struct wlan_net_vif *wnet_vif, enum wifi_mac_macmode macmode) @@ -96229,7 +97687,7 @@ index 000000000000..b529c92bc06a + return 1; +} + -+int wifi_mac_mcs_to_numstreams(int mcs) ++static int wifi_mac_mcs_to_numstreams(int mcs) +{ + int numstreams = 0; + @@ -96786,9 +98244,24 @@ index 000000000000..b529c92bc06a + } + return 0; +} ++ ++unsigned char wifi_mac_find_rate(unsigned char rate_value, struct wifi_mac_rateset rate_table) ++{ ++ unsigned char i = 0; ++ ++ for (i = 0; i < rate_table.dot11_rate_num; i++) ++ { ++ if (WIFINET_GET_RATE_VAL(rate_value) == WIFINET_GET_RATE_VAL(rate_table.dot11_rate[i])) ++ { ++ return 1; ++ } ++ } ++ ++ return 0; ++} diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_rate.h b/drivers/net/wireless/w1/vmac/wifi_mac_rate.h new file mode 100644 -index 000000000000..8dd7675fa733 +index 0000000000000000000000000000000000000000..dabe2e7f243b470ed453f8c0fe241b0c0dc67f40 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_rate.h @@ -0,0 +1,57 @@ @@ -96847,14 +98320,14 @@ index 000000000000..8dd7675fa733 +void wifi_mac_set_legacy_rates(struct wifi_mac_rateset *rs, struct wlan_net_vif *wnet_vif); +void wifi_mac_sta_set_basic_rates(struct wlan_net_vif *wnet_vif, char *si_rates, char *si_exrates); +void wifi_mac_ap_set_basic_rates(struct wlan_net_vif *wnet_vif, enum wifi_mac_macmode macmode); -+ ++unsigned char wifi_mac_find_rate(unsigned char rate_value, struct wifi_mac_rateset rate_table); +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_recv.c b/drivers/net/wireless/w1/vmac/wifi_mac_recv.c new file mode 100644 -index 000000000000..541580dba475 +index 0000000000000000000000000000000000000000..9328efda8b64fa74ea9c60d0f69722b90293dc50 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_recv.c -@@ -0,0 +1,5041 @@ +@@ -0,0 +1,5180 @@ +/* + **************************************************************************************** + * @@ -96870,6 +98343,7 @@ index 000000000000..541580dba475 + */ + +#include "wifi_mac_com.h" ++#include "wifi_mac_scan.h" +#include "wifi_hal_com.h" +#include "wifi_mac_action.h" +#include "wifi_mac_sae.h" @@ -96999,7 +98473,7 @@ index 000000000000..541580dba475 + KASSERT(sta != NULL, ("null nsta")); + sta->sta_inact = sta->sta_inact_reload; + sta->sta_inact_time = jiffies; -+ //dump_memory_internel(os_skb_data(skb), os_skb_get_pktlen(skb)); ++ //dump_memory_internal(os_skb_data(skb), os_skb_get_pktlen(skb)); + KASSERT(os_skb_get_pktlen(skb) >= sizeof(struct wifi_mac_frame_min), + ("frame length too short: %u", os_skb_get_pktlen(skb))); + @@ -97057,7 +98531,7 @@ index 000000000000..541580dba475 + + if ((wnet_vif->vm_state == WIFINET_S_CONNECTED) && (!WIFINET_IS_PROBERSP(wh))) { + if (wnet_vif->vm_bmiss_count) { -+ printk("received pkt from ap, vid:%d\n", wnet_vif->wnet_vif_id); ++ pr_debug("received pkt from ap, vid:%d\n", wnet_vif->wnet_vif_id); + } + wnet_vif->vm_bmiss_count = 0; + } @@ -97155,7 +98629,7 @@ index 000000000000..541580dba475 + } + + if (wnet_vif->vm_bmiss_count) { -+ printk("%s, vid:%d vm_bmiss_count set to 0\n", __func__, wnet_vif->wnet_vif_id); ++ pr_warn("%s, vid:%d vm_bmiss_count set to 0\n", __func__, wnet_vif->wnet_vif_id); + } + wnet_vif->vm_bmiss_count = 0; + } @@ -97225,7 +98699,7 @@ index 000000000000..541580dba475 + } + else if (!WIFINET_ADDR_EQ(temp_nsta->sta_macaddr, wnet_vif->vm_myaddr)) + { -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + wifi_mac_sta_disconnect_from_ap(temp_nsta); + wifi_mac_add_wds_addr(&wnet_vif->vm_sta_tbl, sta, wh4->i_addr4); + } @@ -97248,7 +98722,7 @@ index 000000000000..541580dba475 + { + WIFINET_DPRINTF( AML_DEBUG_ANY,"data invalid dir 0x%x", dir); + wnet_vif->vif_sts.sts_rx_wrong_dir++; -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + goto out; + } + @@ -97257,7 +98731,7 @@ index 000000000000..541580dba475 + WIFINET_DPRINTF( AML_DEBUG_RECV,"data %s", "unknown src"); + if (wnet_vif->vm_state == WIFINET_S_CONNECTED) + { -+ // printk(" %s %d \n",__func__,__LINE__); ++ // pr_debug(" %s %d \n",__func__,__LINE__); + wifi_mac_send_error(sta, wh->i_addr2, WIFINET_FC0_SUBTYPE_DEAUTH, WIFINET_REASON_NOT_AUTHED); + } + wnet_vif->vif_sts.sts_rx_not_assoc++; @@ -97306,7 +98780,7 @@ index 000000000000..541580dba475 + temp_nsta = wifi_mac_get_sta(nt,wh4->i_addr4,wnet_vif->wnet_vif_id); + if (temp_nsta) + { -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + wifi_mac_sta_disconnect_from_ap(temp_nsta); + } + } @@ -97677,7 +99151,7 @@ index 000000000000..541580dba475 + return eth->h_proto; +} + -+void wifi_mac_tcp_pkt_retransmit(struct wifi_station *sta, struct tcphdr *th) ++static void wifi_mac_tcp_pkt_retransmit(struct wifi_station *sta, struct tcphdr *th) +{ + struct drv_txdesc *ptxdesc; + struct list_head *txdesc_queue; @@ -97725,7 +99199,7 @@ index 000000000000..541580dba475 + } +} + -+void wifi_mac_recv_pkt_parse(struct wifi_station *sta, struct sk_buff *skb) { ++static void wifi_mac_recv_pkt_parse(struct wifi_station *sta, struct sk_buff *skb) { + struct ether_header *eh = (struct ether_header *)((unsigned char *)os_skb_data(skb)); + struct iphdr *iphdrp = (struct iphdr *)((unsigned char *)eh + sizeof(struct ether_header)); + struct tcphdr *th = (struct tcphdr *)((unsigned char *)iphdrp + (iphdrp->ihl << 2)); @@ -97770,7 +99244,7 @@ index 000000000000..541580dba475 + } else if (iphdrp->protocol == IPPROTO_UDP) { + if (((uh->source == 0x4400) && (uh->dest == 0x4300)) + || ((uh->source == 0x4300) && (uh->dest == 0x4400))) { -+ //printk("%s source:%04x, dest:%04x\n", __func__, uh->source, uh->dest); ++ //pr_debug("%s source:%04x, dest:%04x\n", __func__, uh->source, uh->dest); + if (sta->connect_status == CONNECT_DHCP_GET_ACK) { + return; + } @@ -97994,7 +99468,7 @@ index 000000000000..541580dba475 + case WIFINET_M_STA: + if ((wnet_vif->vm_state != WIFINET_S_AUTH) || (seq != WIFINET_AUTH_OPEN_RESPONSE)) { + wnet_vif->vif_sts.sts_rx_auth_mismatch++; -+ printk(" %s %d seq0x%x \n",__func__,__LINE__, seq); ++ pr_debug(" %s %d seq0x%x \n",__func__,__LINE__, seq); + return; + } + @@ -98002,11 +99476,11 @@ index 000000000000..541580dba475 + if (status != 0) { + WIFINET_DPRINTF_STA(AML_DEBUG_DEBUG | AML_DEBUG_CONNECT, sta, "open auth failed (reason %d)", status); + wnet_vif->vif_sts.sts_rx_auth_fail++; -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); ++ wnet_vif->disconnect_reason_code = status; + wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN, 0); -+ + } else { -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + /*authentication success and change SM to send assoc req. */ + wifi_mac_top_sm(wnet_vif, WIFINET_S_ASSOC, 0); + } @@ -98029,8 +99503,10 @@ index 000000000000..541580dba475 + unsigned short seq, struct wifi_frame *wh, unsigned short status, unsigned int channel) +{ + struct wlan_net_vif *wnet_vif = sta->sta_wnet_vif; ++ unsigned char *frm = (unsigned char *)&wh[1]; ++ unsigned int msg_type = le16toh(*(unsigned short *)(frm + 2)); + -+ printk("%s WIFINET_AUTH_ALG_SAE\n", __func__); ++ pr_debug("%s WIFINET_AUTH_ALG_SAE status:%d\n", __func__, status); + + switch (wnet_vif->vm_opmode) { + case WIFINET_M_HOSTAP: @@ -98045,6 +99521,13 @@ index 000000000000..541580dba475 + return; + + } ++ ++ if ((wnet_vif->vm_flags & WIFINET_F_H2E) && (wnet_vif->vm_flags & WIFINET_F_WPA) ++ && (status == WIFINET_STATUS_SAE_H2E)) { ++ sta->sta_use_h2e = WIFINET_H2E_VALID; ++ AML_OUTPUT("sta:%x support h2e\n", sta); ++ } ++ + sta->sta_flags |= WIFINET_NODE_AREF; + memcpy(sta->sta_essid, wnet_vif->vm_mainsta->sta_essid, wnet_vif->vm_mainsta->sta_esslen); + sta->sta_authmode = WIFINET_AUTH_SAE; @@ -98058,10 +99541,21 @@ index 000000000000..541580dba475 + } + + if (status != 0) { -+ WIFINET_DPRINTF_STA(AML_DEBUG_WARNING, sta, "sae auth failed (reason %d)", status); ++ if ((sta->sta_use_h2e == WIFINET_H2E_VALID) ++ && (status == WIFINET_STATUS_SAE_H2E) ++ && (msg_type == WIFINET_SAE_COMMIT)) { ++ //h2e status notify uplyer ++ } else if ((status == WIFINET_STATUS_ANTI_TOKEN_REQUESTED) && (msg_type == WIFINET_SAE_COMMIT)) { ++ //Anti-Token-Requested ++ } else { ++ WIFINET_DPRINTF_STA(AML_DEBUG_WARNING, sta, "sae auth failed (reason %d)", status); ++ wnet_vif->disconnect_reason_code = status; ++ vm_cfg80211_indicate_disconnect(wnet_vif); ++ wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN, 0); ++ } + } + -+ vm_cfg80211_notify_mgmt_rx(wnet_vif, channel, os_skb_data(skb),os_skb_get_pktlen(skb)); ++ vm_cfg80211_notify_mgmt_rx(wnet_vif, channel, os_skb_data(skb), os_skb_get_pktlen(skb)); + break; + + default: @@ -98133,7 +99627,7 @@ index 000000000000..541580dba475 + WIFINET_DPRINTF_MACADDR( AML_DEBUG_CONNECT, + sta->sta_macaddr, "shared key auth %s", " PRIVACY is disabled"); + estatus = WIFINET_STATUS_ALG; -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + goto bad; + } + if (sta->sta_authmode != WIFINET_AUTH_SHARED) @@ -98142,7 +99636,7 @@ index 000000000000..541580dba475 + sta->sta_macaddr, "shared key auth bad sta auth mode %u", sta->sta_authmode); + wnet_vif->vif_sts.sts_rx_auth_mismatch++; + estatus = WIFINET_STATUS_ALG; -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + goto bad; + } + @@ -98162,7 +99656,7 @@ index 000000000000..541580dba475 + #endif + wnet_vif->vif_sts.sts_rx_auth_mismatch++; + estatus = WIFINET_STATUS_CHALLENGE; -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + goto bad; + } + if (*frm == WIFINET_ELEMID_CHALLENGE) @@ -98179,7 +99673,7 @@ index 000000000000..541580dba475 + sta->sta_macaddr, "shared key auth %s", "no challenge"); + wnet_vif->vif_sts.sts_rx_auth_mismatch++; + estatus = WIFINET_STATUS_CHALLENGE; -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + goto bad; + } + if (challenge[1] != WIFINET_CHALLENGE_LEN) @@ -98188,7 +99682,7 @@ index 000000000000..541580dba475 + sta->sta_macaddr, "shared key auth bad challenge len %d", challenge[1]); + wnet_vif->vif_sts.sts_rx_auth_mismatch++; + estatus = WIFINET_STATUS_CHALLENGE; -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + goto bad; + } + default: @@ -98201,7 +99695,7 @@ index 000000000000..541580dba475 + case WIFINET_M_WDS: + WIFINET_DPRINTF_MACADDR( AML_DEBUG_CONNECT, + sta->sta_macaddr, "shared key auth bad operating mode %u", wnet_vif->vm_opmode); -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + return; + case WIFINET_M_HOSTAP: + if (wnet_vif->vm_state != WIFINET_S_CONNECTED) @@ -98216,7 +99710,7 @@ index 000000000000..541580dba475 + case WIFINET_AUTH_SHARED_REQUEST: + if (sta == wnet_vif->vm_mainsta) + { -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + sta = wifi_mac_bup_bss(wnet_vif, wh->i_addr2); + if (sta == NULL) + { @@ -98275,7 +99769,7 @@ index 000000000000..541580dba475 + goto bad; + } + arg = seq + 1; -+ printk("%s(%d) tx_auth 8\n", __func__, __LINE__); ++ pr_debug("%s(%d) tx_auth 8\n", __func__, __LINE__); + wifi_mac_send_mgmt(sta, WIFINET_FC0_SUBTYPE_AUTH, (void *)&arg); + break; + @@ -98298,9 +99792,10 @@ index 000000000000..541580dba475 + "shared key auth failed (reason %d)", + status); + wnet_vif->vif_sts.sts_rx_auth_fail++; ++ wnet_vif->disconnect_reason_code = status; + goto bad; + } -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + wifi_mac_top_sm(wnet_vif, WIFINET_S_ASSOC, 0); + break; + case WIFINET_AUTH_SHARED_CHALLENGE: @@ -98308,8 +99803,8 @@ index 000000000000..541580dba475 + goto bad; + memcpy(sta->sta_challenge, &challenge[2], challenge[1]); + arg = seq + 1; -+ printk(" %s %d \n",__func__,__LINE__); -+printk("%s(%d) tx_auth 9\n", __func__, __LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); ++pr_debug("%s(%d) tx_auth 9\n", __func__, __LINE__); + wifi_mac_send_mgmt(sta, WIFINET_FC0_SUBTYPE_AUTH, (void *)&arg); + break; + default: @@ -98335,7 +99830,7 @@ index 000000000000..541580dba475 + { + if (wnet_vif->vm_state == WIFINET_S_AUTH) + { -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN, 0); + } + } @@ -98521,7 +100016,7 @@ index 000000000000..541580dba475 + } + + if (w != rsn->rsn_mcastcipher) { -+ printk("WPA mcast cipher mismatch; got %u, expected %u\n", w, rsn->rsn_mcastcipher); ++ pr_err("WPA mcast cipher mismatch; got %u, expected %u\n", w, rsn->rsn_mcastcipher); + return WIFINET_REASON_IE_INVALID; + } + frm += 4, len -= 4; @@ -98587,7 +100082,7 @@ index 000000000000..541580dba475 + rsn->sa_valid = 1; + rsn->gtksa = frm[0]; + rsn->ptksa = frm[1]; -+ printk("%s add gtk/ptk sa\n", __func__); ++ pr_debug("%s add gtk/ptk sa\n", __func__); + } + + return 0; @@ -98763,7 +100258,7 @@ index 000000000000..541580dba475 + } + + } else { -+ printk("not pmkid\n"); ++ pr_err("not pmkid\n"); + rsn->rsn_pmkid_offset = 0; + } + @@ -98784,7 +100279,7 @@ index 000000000000..541580dba475 + unsigned char pmkid_offset = frm[1]; + + if (len < 10) { -+ printk("RSN too short, len %u\n", len); ++ pr_err("RSN too short, len %u\n", len); + return WIFINET_REASON_IE_INVALID; + } + @@ -98812,7 +100307,9 @@ index 000000000000..541580dba475 + frm += 2, len -= 2; + if ((n <= 0) || (len < n * 4 + 2)) { + ERROR_DEBUG_OUT("RSN ucast cipher data too short; len %u, n %u\n", len, n); -+ return WIFINET_REASON_IE_INVALID; ++ if (is_judge) { ++ return WIFINET_REASON_IE_INVALID; ++ } + } + + w = 0; @@ -98834,7 +100331,9 @@ index 000000000000..541580dba475 + frm += 2, len -= 2; + if ((n <= 0) || (len < n * 4)) { + ERROR_DEBUG_OUT("RSN keymgmt data too short; len %u, n %u\n", len, n); -+ return WIFINET_REASON_IE_INVALID; ++ if (is_judge) { ++ return WIFINET_REASON_IE_INVALID; ++ } + } + + w = 0; @@ -98889,7 +100388,7 @@ index 000000000000..541580dba475 + } + + } else { -+ //printk("not pmkid\n"); ++ //pr_err("not pmkid\n"); + rsn->rsn_pmkid_count = 0; + rsn->rsn_pmkid_offset = 0; + } @@ -99027,11 +100526,11 @@ index 000000000000..541580dba475 + +static int +wifi_mac_parse_dothparams(struct wlan_net_vif *wnet_vif, unsigned char *frm, -+ struct wifi_mac_scan_param* sp) ++ struct wifi_mac_scan_param* sp, struct wifi_station *sta) +{ + struct wifi_mac *wifimac = wnet_vif->vm_wmac; + unsigned int len = frm[1]; -+ unsigned char chan, tbtt; ++ unsigned char chan, csa_cnt; + + if (len < 4-2) + { @@ -99041,69 +100540,32 @@ index 000000000000..541580dba475 + } + wnet_vif->vm_mainsta->sta_channel_switch_mode = frm[2]; + chan = frm[3]; ++ csa_cnt = frm[4]; ++ + if (wifi_mac_chan_num_avail(wifimac, chan)==false) + { + WIFINET_DPRINTF(AML_DEBUG_ELEMID | AML_DEBUG_DOTH, + "channel switch invalid channel %u", chan); + return -1; + } -+ tbtt = frm[4]; + -+ if (tbtt <= 1) ++ if (csa_cnt > 0) + { -+ struct wifi_mac_ie_htinfo *htinfo = (struct wifi_mac_ie_htinfo *)sp->htinfo; -+ struct wifi_mac_ie_htinfo_cmn *ie; -+ struct wifi_mac_ie_vht_opt *vhtop = (struct wifi_mac_ie_vht_opt *) sp->vht_opt; -+ int bw = 0, center_chan = 0, center_chan_vht = 0; -+ unsigned char ret_char = false; + int ret = -1; ++ unsigned char ret_char = false; + -+ if (!htinfo) -+ return ret; -+ -+ ie = &htinfo->hi_ie; ++ sta->sta_chan_switch_chan = chan; ++ os_timer_ex_cancel(&sta->csa_timer, CANCEL_SLEEP); ++ os_timer_ex_start_period(&sta->csa_timer, csa_cnt * wnet_vif->vm_bcn_intval); + -+ if (ie->hi_extchoff == WIFINET_HTINFO_EXTOFFSET_ABOVE) -+ { -+ center_chan = chan + 2; -+ bw = WIFINET_BWC_WIDTH40; -+ } -+ else if (ie->hi_extchoff == WIFINET_HTINFO_EXTOFFSET_BELOW) -+ { -+ center_chan = chan - 2; -+ bw = WIFINET_BWC_WIDTH40; -+ } -+ else -+ { -+ center_chan = chan; -+ bw = WIFINET_BWC_WIDTH20; -+ } -+ if (vhtop) { -+ if (vhtop->vht_op_chwidth == VHT_OPT_CHN_WD_80M) -+ { -+ center_chan_vht = wifi_mac_find_80M_channel_center_chan(chan); -+ if (center_chan_vht) { -+ center_chan = center_chan_vht; -+ bw = WIFINET_BWC_WIDTH80; -+ } -+ } -+ else if (vhtop->vht_op_chwidth > VHT_OPT_CHN_WD_80M) -+ { -+ ERROR_DEBUG_OUT("not support bandwidth %d yet \n", vhtop->vht_op_chwidth); -+ } -+ } -+ ret_char = wifi_mac_set_wnet_vif_channel(wnet_vif, chan, bw, center_chan); -+ -+ if ((wnet_vif->vm_mainsta->sta_channel_switch_mode == 1) && (ret_char == true)) { -+ wnet_vif->vm_switchchan = wifi_mac_find_chan(wifimac, chan, bw, center_chan); -+ wnet_vif->vm_chan_switch_scan_flag = 1; -+ wifi_mac_start_scan(wnet_vif, WIFINET_SCANCFG_USERREQ | WIFINET_SCANCFG_ACTIVE | WIFINET_SCANCFG_FLUSH | -+ WIFINET_SCANCFG_CREATE, wnet_vif->vm_des_nssid, wnet_vif->vm_des_ssid); ++ if (csa_cnt == 1) { ++ AML_OUTPUT("start_csa count:%d target_chan:%d\n", csa_cnt, chan); + } + + ret = ((ret_char==true)?0:-1); + return ret; + } ++ + return 0; +} + @@ -99546,6 +101008,7 @@ index 000000000000..541580dba475 + struct wifi_mac_ie_vht_ch_sw_wrp* vht_ch_sw_wrp = (struct wifi_mac_ie_vht_ch_sw_wrp*) ie; + unsigned char sub_ie_id = 0; + unsigned char sub_ie_len = 0; ++ unsigned char sub_ie_ofst = 2; + + if ((vht_ch_sw_wrp == NULL) || (sta == NULL)) { + return ; @@ -99555,31 +101018,30 @@ index 000000000000..541580dba475 + return; + } + -+ sub_ie_id = vht_ch_sw_wrp->new_country_sub_ie[0]; -+ sub_ie_len = vht_ch_sw_wrp->new_country_sub_ie[1]; -+ if ((sub_ie_id == WIFINET_ELEMID_COUNTRY) && (sub_ie_len <= SUB_IE_MAX_LEN - 2)) { -+ memcpy(sta->sta_new_country_sub_ie, vht_ch_sw_wrp->new_country_sub_ie, sub_ie_len + 2); ++ memset(sta->sta_new_country_sub_ie, 0, SUB_IE_MAX_LEN); ++ memset(sta->sta_wide_bw_ch_sw_sub_ie, 0, SUB_IE_MAX_LEN); ++ memset(sta->sta_new_vht_tx_pw_sub_ie, 0, SUB_IE_MAX_LEN); + -+ } else { -+ // nothing, just a tip -+ } ++ while (sub_ie_ofst < ie[1] + 2) { ++ sub_ie_id = ie[sub_ie_ofst]; ++ sub_ie_len = ie[sub_ie_ofst + 1]; + -+ sub_ie_id = vht_ch_sw_wrp->wide_bw_ch_sw_sub_ie[0]; -+ sub_ie_len = vht_ch_sw_wrp->wide_bw_ch_sw_sub_ie[1]; -+ if ((sub_ie_id == WIFINET_ELEMID_WIDE_BAND_CHAN_SWITCH) && (sub_ie_len <= SUB_IE_MAX_LEN - 2)) { -+ memcpy(sta->sta_wide_bw_ch_sw_sub_ie, vht_ch_sw_wrp->wide_bw_ch_sw_sub_ie, sub_ie_len + 2); ++ AML_OUTPUT("sub_ie_id = %d, sub_id_len = %d\n", sub_ie_id, sub_ie_len); + -+ } else { -+ // nothing, just a tip -+ } ++ if (!(sub_ie_len <= SUB_IE_MAX_LEN - 2)) { ++ ERROR_DEBUG_OUT("sub_ie_id[%d] : sub_ie_len[%d] is error\n",sub_ie_id,sub_ie_len); ++ break; ++ } + -+ sub_ie_id = vht_ch_sw_wrp->new_vht_tx_pw_sub_ie[0]; -+ sub_ie_len = vht_ch_sw_wrp->new_vht_tx_pw_sub_ie[1]; -+ if ((sub_ie_id == WIFINET_ELEMID_VHT_TX_PWR_ENVLP) && (sub_ie_len <= SUB_IE_MAX_LEN - 2)) { -+ memcpy(sta->sta_new_vht_tx_pw_sub_ie, vht_ch_sw_wrp->new_vht_tx_pw_sub_ie, sub_ie_len + 2); ++ if (sub_ie_id == WIFINET_ELEMID_COUNTRY) { ++ memcpy(sta->sta_new_country_sub_ie, &ie[sub_ie_ofst], sub_ie_len + 2); ++ } else if (sub_ie_id == WIFINET_ELEMID_WIDE_BAND_CHAN_SWITCH) { ++ memcpy(sta->sta_wide_bw_ch_sw_sub_ie, &ie[sub_ie_ofst], sub_ie_len + 2); ++ } else if (sub_ie_id == WIFINET_ELEMID_VHT_TX_PWR_ENVLP) { ++ memcpy(sta->sta_new_vht_tx_pw_sub_ie, &ie[sub_ie_ofst], sub_ie_len + 2); ++ } + -+ } else { -+ // nothing, just a tip ++ sub_ie_ofst += sub_ie_len + 2; + } +} + @@ -99636,7 +101098,7 @@ index 000000000000..541580dba475 + } +} + -+int wifi_mac_parse_timeout_ie(struct wifi_station *sta, unsigned char *timeout) { ++static int wifi_mac_parse_timeout_ie(struct wifi_station *sta, unsigned char *timeout) { + unsigned char ie; + unsigned char ie_len; + unsigned char timeout_type; @@ -99667,7 +101129,7 @@ index 000000000000..541580dba475 + return; + } + -+ //printk("parse vht cap ++\n"); ++ //pr_debug("parse vht cap ++\n"); + if (sp->vht_cap) { + wifi_mac_parse_vht_cap(sta, sp->vht_cap); + } @@ -99733,7 +101195,7 @@ index 000000000000..541580dba475 + return; +} + -+void wifi_mac_pkt_parse_element(struct wlan_net_vif *wnet_vif, ++static void wifi_mac_pkt_parse_element(struct wlan_net_vif *wnet_vif, + struct wifi_station *sta, struct sk_buff *skb, struct wifi_mac_scan_param *scan, unsigned char *invalid, unsigned char *drop) +{ + struct vm_wdev_priv *pwdev_priv = wdev_to_priv(wnet_vif->vm_wdev); @@ -99751,6 +101213,7 @@ index 000000000000..541580dba475 + wh = (struct wifi_frame *)os_skb_data(skb); + frm = (unsigned char *)&wh[1]; + efrm = os_skb_data(skb) + os_skb_get_pktlen(skb); ++ scan->frame_len = os_skb_get_pktlen(skb); + subtype = wh->i_fc[0] & WIFINET_FC0_SUBTYPE_MASK; + snprintf(sa, MAX_MAC_BUF_LEN, "%02x:%02x:%02x:%02x:%02x:%02x", + wh->i_addr2[0], wh->i_addr2[1], wh->i_addr2[2], wh->i_addr2[3], wh->i_addr2[4], wh->i_addr2[5]); @@ -100021,7 +101484,7 @@ index 000000000000..541580dba475 + } else if (wifimac->wm_curchan != NULL) { + //no channel info in beacon or probe rsp, use current channel.(wifi51_5G,tkip or wep) + scan.chan = channel; -+// printk("no channel info, use mac_chan:%d cur_chan:%d, rx channel:%d\n", wifimac->wm_curchan->chan_pri_num, scan.chan, channel); ++// pr_warn("no channel info, use mac_chan:%d cur_chan:%d, rx channel:%d\n", wifimac->wm_curchan->chan_pri_num, scan.chan, channel); + } + } + @@ -100049,8 +101512,15 @@ index 000000000000..541580dba475 + WIFI_SCAN_SE_LIST_LOCK(st); + list_for_each_entry_safe(se, si_next, &st->st_hash[hash], se_hash) { + if (WIFINET_ADDR_EQ(se->scaninfo.SI_macaddr, wh->i_addr2)) { -+ WIFI_SCAN_SE_LIST_UNLOCK(st); -+ return; ++ if (vm_p2p_is_state(wnet_vif->vm_p2p, NET80211_P2P_STATE_SCAN) ++ && (se->scaninfo.SI_frame_len < scan.frame_len)) { ++ list_del_init(&se->se_list); ++ list_del_init(&se->se_hash); ++ FREE(se,"sta_add.se"); ++ } else { ++ WIFI_SCAN_SE_LIST_UNLOCK(st); ++ return; ++ } + } + } + WIFI_SCAN_SE_LIST_UNLOCK(st); @@ -100058,7 +101528,7 @@ index 000000000000..541580dba475 + wifi_mac_scan_rx(wnet_vif, &scan, wh, rssi, NULL); + } + -+ //printk("%s %02x:%02x:%02x:%02x:%02x:%02x, assoc_id:%d\n", __func__, wh->i_addr2[0], wh->i_addr2[1], ++ //pr_debug("%s %02x:%02x:%02x:%02x:%02x:%02x, assoc_id:%d\n", __func__, wh->i_addr2[0], wh->i_addr2[1], + // wh->i_addr2[2], wh->i_addr2[3], wh->i_addr2[4], wh->i_addr2[5], sta->sta_associd); + + if ((wnet_vif->vm_opmode == WIFINET_M_STA) && (sta->sta_associd != 0) @@ -100124,9 +101594,9 @@ index 000000000000..541580dba475 + } + + if (scan.doth != NULL) { -+ wifi_mac_parse_dothparams(wnet_vif, scan.doth, &scan); ++ wifi_mac_parse_dothparams(wnet_vif, scan.doth, &scan, sta); + } -+ wifi_mac_pwrsave_sleep_wait_cancle(wnet_vif); ++ wifi_mac_pwrsave_sleep_wait_cancel(wnet_vif); + + if ((scan.tim != NULL) && (wifi_mac_pwrsave_is_sta_sleeping(wnet_vif) == 0) + && ((wnet_vif->vm_pstxqueue_flags & WIFINET_PSQUEUE_PS4QUIET) == 0)) { @@ -100267,7 +101737,7 @@ index 000000000000..541580dba475 + } else if (wifimac->wm_curchan != NULL) { + //no channel info in beacon or probe rsp, use current channel.(wifi51_5G,tkip or wep) + scan.chan = channel; -+// printk("no channel info, use mac_chan:%d cur_chan:%d, rx channel:%d\n", wifimac->wm_curchan->chan_pri_num, scan.chan, channel); ++// pr_debug("no channel info, use mac_chan:%d cur_chan:%d, rx channel:%d\n", wifimac->wm_curchan->chan_pri_num, scan.chan, channel); + } + } + @@ -100304,9 +101774,22 @@ index 000000000000..541580dba475 + } + } + } ++ ++ /* Need to update existing entry. List is locked, and as ++ * 'oldse' is not NULL, 'wifi_mac_scan_rx()' recognizes ++ * it as updating entry and won't take lock on list. ++ */ ++ if (oldse) ++ wifi_mac_scan_rx(wnet_vif, &scan, wh, rssi, oldse); ++ + WIFI_SCAN_SE_LIST_UNLOCK(st); + -+ wifi_mac_scan_rx(wnet_vif, &scan, wh, rssi, oldse); ++ /* This will add new entry. 'oldse' is NULL, we release ++ * lock on list, 'wifi_mac_scan_rx()' will allocate new ++ * entry, will lock this list to insert new entry. ++ */ ++ if (!oldse) ++ wifi_mac_scan_rx(wnet_vif, &scan, wh, rssi, oldse); +} + + @@ -100361,8 +101844,7 @@ index 000000000000..541580dba475 + } + + if (temp_wnet_vif != NULL && temp_wnet_vif->vm_curchan != NULL && temp_wnet_vif->vm_curchan->chan_pri_num != channel) { -+ DPRINTF(AML_DEBUG_WARNING, "%s %d ignore, probe req %d, %d\n",__func__,__LINE__, temp_wnet_vif->vm_curchan->chan_pri_num, channel); -+ return; ++ DPRINTF(AML_DEBUG_INFO, "%s %d ignore, probe req %d, %d\n",__func__,__LINE__, temp_wnet_vif->vm_curchan->chan_pri_num, channel); + } + if (WIFINET_IS_MULTICAST(wh->i_addr2)) + { @@ -100519,7 +102001,7 @@ index 000000000000..541580dba475 + } +} + -+void wifi_mac_status_code_handle(struct wifi_station *sta, unsigned char subtype, struct wifi_mac_scan_param *scan) ++static void wifi_mac_status_code_handle(struct wifi_station *sta, unsigned char subtype, struct wifi_mac_scan_param *scan) +{ + struct wlan_net_vif *wnet_vif = sta->sta_wnet_vif; + unsigned short timeout = 1000; @@ -100551,11 +102033,11 @@ index 000000000000..541580dba475 + timeout = wifi_mac_parse_timeout_ie(sta, scan->timeout_ie); + } + -+ printk("wait %d to reconnect\n", timeout); ++ pr_warn("wait %d to reconnect\n", timeout); + os_timer_ex_start_period(&wnet_vif->vm_sm_switch, timeout); + return; + } -+ ++ wnet_vif->disconnect_reason_code = scan->status_code; + wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN,0); + } + @@ -100596,6 +102078,13 @@ index 000000000000..541580dba475 + return; + } + ++ if ((wnet_vif->vm_opmode == WIFINET_M_STA) && (sta->connect_status >= CONNECT_DISCONNECTING)) { ++ pr_debug("%s, %d, ignor auth frm, connect_status:%d\n", __func__,__LINE__, sta->connect_status); ++ os_timer_ex_cancel(&wnet_vif->vm_mgtsend, CANCEL_NO_SLEEP); ++ wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN, 0); ++ return; ++ } ++ + if ((wnet_vif->vm_aclop != NULL) && !wnet_vif->vm_aclop->iac_check(wnet_vif, wh->i_addr2)) { + WIFINET_DPRINTF( AML_DEBUG_ACL, "auth %s", "disallowed by ACL"); + wnet_vif->vif_sts.sts_rx_acl_mismatch++; @@ -100625,6 +102114,7 @@ index 000000000000..541580dba475 + && status != WIFINET_STATUS_SUCCESS) { //maybe the password is wrong, not the auth type + AML_OUTPUT("auth reject:%d\n", status); + os_timer_ex_cancel(&wnet_vif->vm_mgtsend, CANCEL_NO_SLEEP); ++ wnet_vif->disconnect_reason_code = status; + vm_cfg80211_indicate_disconnect(wnet_vif); + wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN, 0); + return; @@ -100682,7 +102172,7 @@ index 000000000000..541580dba475 + int reassoc, resp; + struct wifi_mac_ie_vht_opt_md_ntf *vht_opt_md_ntf = NULL; + -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + + wh = (struct wifi_frame *) os_skb_data(skb); + frm = (unsigned char *)&wh[1]; @@ -100733,6 +102223,9 @@ index 000000000000..541580dba475 + if (reassoc) + frm += 6; + ++ sta->sta_assoc_req = frm; ++ sta->sta_assoc_req_ielen = efrm - frm; ++ + rsnie = NULL; + /*frm[1] is length field */ + while (((frm+1) < efrm ) && (frm + frm[1] + 1) < efrm ) @@ -100760,7 +102253,7 @@ index 000000000000..541580dba475 + break; + + case WIFINET_ELEMID_TIM_BROADCAST_REQ: -+ printk("ELEMID_TIM_BROADCAST_REQ, frm:%02x:%02x:%02x:%02x\n", frm[0], frm[1], frm[2], frm[3]); ++ pr_debug("ELEMID_TIM_BROADCAST_REQ, frm:%02x:%02x:%02x:%02x\n", frm[0], frm[1], frm[2], frm[3]); + break; + + case WIFINET_ELEMID_HTINFO: @@ -100803,9 +102296,9 @@ index 000000000000..541580dba475 +#ifdef CONFIG_WAPI + else if (iswaioui(frm)) + { -+ printk("ASSOC_REQ is waioui \n"); ++ pr_debug("ASSOC_REQ is waioui \n"); + wai = frm; -+ dump_memory_internel(wai, wai[1]+2); ++ dump_memory_internal(wai, wai[1]+2); + } +#endif //#ifdef CONFIG_WAPI + break; @@ -100815,8 +102308,8 @@ index 000000000000..541580dba475 + + case WIFINET_ELEMID_WAI: + wai = frm; -+ printk("ASSOC_REQ is WIFINET_ELEMID_WAI \n"); -+ dump_memory_internel(wai, wai[1]+2); ++ pr_debug("ASSOC_REQ is WIFINET_ELEMID_WAI \n"); ++ dump_memory_internal(wai, wai[1]+2); + break; + +#endif //#ifdef CONFIG_WAPI @@ -100857,11 +102350,11 @@ index 000000000000..541580dba475 + + if (wpa != NULL) { + if (wpa[0] != WIFINET_ELEMID_RSN) { -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + reason = wifi_mac_parse_wpa(&sta->sta_rsn, wpa, 0); + + } else { -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + reason = wifi_mac_parse_counterpart_rsn(&sta->sta_rsn, wpa, 1); + + if (wnet_vif->vm_mainsta->sta_flags_ext & WIFINET_NODE_MFP) { @@ -100871,14 +102364,14 @@ index 000000000000..541580dba475 + } + + if ((sta->sta_authmode == WIFINET_AUTH_SAE) && !(sta->sta_rsn.rsn_caps & MFP_MASK)) { -+ printk("sae auth, but no pmf\n"); ++ pr_warn("sae auth, but no pmf\n"); + reason = WIFINET_REASON_IE_INVALID; + } + } + + if (reason != 0) { + arg = reason; -+ printk(" %s %d reason=%d\n",__func__,__LINE__, reason); ++ pr_debug(" %s %d reason=%d\n",__func__,__LINE__, reason); + wifi_mac_send_mgmt(sta, WIFINET_FC0_SUBTYPE_DEAUTH, (void *)&arg); + wifi_mac_sta_disconnect_from_ap(sta); + wnet_vif->vif_sts.sts_rx_assoc_wpa_mismatch++; @@ -101030,7 +102523,7 @@ index 000000000000..541580dba475 + wnet_vif->vif_sts.sts_rx_assoc_cap_mismatch++; + return; + } -+ printk("%s warning:WIFINET_NODE_HT clear\n", __func__); ++ pr_warn("%s warning:WIFINET_NODE_HT clear\n", __func__); + sta->sta_flags &= ~WIFINET_NODE_HT; + sta->sta_htcap = 0; + } @@ -101058,7 +102551,7 @@ index 000000000000..541580dba475 + + if (vht_opt_md_ntf) { + wifi_mac_parse_vht_op_md_ntf(sta, vht_opt_md_ntf->opt_mode); -+ printk("****** %s--vm_bandwidth = %d, sta_chbw =%d\n", __func__, wnet_vif->vm_bandwidth, sta->sta_chbw); ++ pr_debug("****** %s--vm_bandwidth = %d, sta_chbw =%d\n", __func__, wnet_vif->vm_bandwidth, sta->sta_chbw); + } + + } @@ -101098,6 +102591,13 @@ index 000000000000..541580dba475 + return; + } + ++ if (sta->connect_status >= CONNECT_DISCONNECTING) { ++ ERROR_DEBUG_OUT("ignor assoc rsp frm, connect_status:%d\n", sta->connect_status); ++ os_timer_ex_cancel(&wnet_vif->vm_mgtsend, CANCEL_NO_SLEEP); ++ wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN, 0); ++ return; ++ } ++ + wifi_mac_pkt_parse_element(wnet_vif, sta, skb, &scan, &invalid, &drop); + AML_OUTPUT("%s assoc status code:%d\n", __func__, scan.status_code); + @@ -101249,14 +102749,13 @@ index 000000000000..541580dba475 + vm_cfg80211_notify_mgmt_rx(wnet_vif, channel, os_skb_data(skb),os_skb_get_pktlen(skb)); + + WIFINET_DPRINTF_STA(AML_DEBUG_WARNING, sta, "recv deauthenticate (reason %d)", reason); -+ /* Always log disconnect reason for debugging */ -+ printk("WiFi disconnect: Received DEAUTH from AP, reason_code=%d\n", reason); + + switch (wnet_vif->vm_opmode) { + case WIFINET_M_STA: + if (wnet_vif->vm_state != WIFINET_S_INIT) { + wnet_vif->vm_chan_roaming_scan_flag = 0; -+ ++ wnet_vif->disconnect_reason_code = reason; ++ sta->connect_status = CONNECT_DISCONNECTING; + wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN, 0); + } + break; @@ -101307,24 +102806,21 @@ index 000000000000..541580dba475 + vm_cfg80211_notify_mgmt_rx(wnet_vif, channel, os_skb_data(skb),os_skb_get_pktlen(skb)); + + WIFINET_DPRINTF_STA(AML_DEBUG_WARNING, sta, "recv disassociate (reason %d)", reason); -+ /* Always log disconnect reason for debugging */ -+ printk("WiFi disconnect: Received DISASSOC from AP %02x:%02x:%02x:%02x:%02x:%02x, reason_code=%d\n", -+ wh->i_addr2[0], wh->i_addr2[1], wh->i_addr2[2], -+ wh->i_addr2[3], wh->i_addr2[4], wh->i_addr2[5], reason); + -+ /* Removed redundant BSSID prints - already shown above */ -+ /*printk("%s %d source bssid: %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, __LINE__, ++ pr_debug("%s %d source bssid: %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, __LINE__, + wh->i_addr2[0], wh->i_addr2[1],wh->i_addr2[2], + wh->i_addr2[3], wh->i_addr2[4], wh->i_addr2[5]); + -+ printk("%s %d connect AP bssid:%02x:%02x:%02x:%02x:%02x:%02x\n", __func__, __LINE__, ++ pr_debug("%s %d connect AP bssid:%02x:%02x:%02x:%02x:%02x:%02x\n", __func__, __LINE__, + wnet_vif->vm_des_bssid[0], wnet_vif->vm_des_bssid[1], wnet_vif->vm_des_bssid[2], -+ wnet_vif->vm_des_bssid[3], wnet_vif->vm_des_bssid[4], wnet_vif->vm_des_bssid[5]);*/ ++ wnet_vif->vm_des_bssid[3], wnet_vif->vm_des_bssid[4], wnet_vif->vm_des_bssid[5]); + + switch (wnet_vif->vm_opmode) + { + case WIFINET_M_STA: + if (wnet_vif->vm_state == WIFINET_S_CONNECTED) { ++ wnet_vif->disconnect_reason_code = reason; ++ sta->connect_status = CONNECT_DISCONNECTING; + wifi_mac_top_sm(wnet_vif, WIFINET_S_SCAN, 0); + + } else { @@ -101367,7 +102863,7 @@ index 000000000000..541580dba475 + struct wifi_mac_action_mgt_args actionargs; + struct wifi_mac_action_sa_query *sa_query = NULL; + struct wifi_station *remote_sta = NULL; -+ ++ struct wifi_mac_action_csa_frame *csa_frame = NULL; + unsigned short statuscode; + unsigned short batimeout; + unsigned short reasoncode; @@ -101408,14 +102904,11 @@ index 000000000000..541580dba475 + mdelay(50); + } +#endif -+ /* Remove P2P action frame logs (category 127) to reduce log noise */ -+ if (ia->ia_category != 127) { -+ printk("recv_action_frame subtype 0x%x, category %d\n", subtype, ia->ia_category); -+ } ++ pr_debug("recv_action_frame subtype 0x%x, category %d\n", subtype, ia->ia_category); + + switch (ia->ia_category) { + case AML_CATEGORY_QOS: -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + WIFINET_DPRINTF_STA(AML_DEBUG_ACTION, sta, "%s: QoS action mgt frames not supported, vm_state %d \n", + __func__, wnet_vif->vm_state); + wnet_vif->vif_sts.sts_mng_discard++; @@ -101503,30 +102996,55 @@ index 000000000000..541580dba475 + switch (ia->ia_action) + { + case WIFINET_ACT_PUBLIC_BSSCOEXIST: -+ WIFINET_VERIFY_LENGTH(efrm - frm, sizeof(struct wifi_mac_action_bss_coex_frame)); ++ if ((wnet_vif->vm_state == WIFINET_S_CONNECTED) && WIFINET_ADDR_EQ(sta->sta_bssid, wh->i_addr2)) { ++ WIFINET_VERIFY_LENGTH(efrm - frm, sizeof(struct wifi_mac_action_bss_coex_frame)); + -+ iabsscoex = (struct wifi_mac_action_bss_coex_frame *) frm; -+ WIFINET_DPRINTF_STA(AML_DEBUG_ACTION, sta, "%s: Element 0 inf request = %d, 40 intolerant = %d " -+ "20 width req = %d, obss exempt req = %d, obss exempt grant = %d\n", __func__, iabsscoex->coex.inf_request, -+ iabsscoex->coex.ht40_intolerant, iabsscoex->coex.ht20_width_req, iabsscoex->coex.obss_exempt_req, iabsscoex->coex.obss_exempt_grant); ++ iabsscoex = (struct wifi_mac_action_bss_coex_frame *) frm; ++ WIFINET_DPRINTF_STA(AML_DEBUG_ACTION, sta, "%s: Element 0 inf request = %d, 40 intolerant = %d " ++ "20 width req = %d, obss exempt req = %d, obss exempt grant = %d\n", __func__, iabsscoex->coex.inf_request, ++ iabsscoex->coex.ht40_intolerant, iabsscoex->coex.ht20_width_req, iabsscoex->coex.obss_exempt_req, iabsscoex->coex.obss_exempt_grant); + -+ if (iabsscoex->coex.ht40_intolerant || iabsscoex->coex.ht20_width_req -+ || (((skb->data_len - sizeof(struct wifi_frame)) > (sizeof(struct wifi_mac_action_bss_coex_frame))) -+ && (wifi_mac_recv_bss_intol_channelCheck(wifimac, &iabsscoex->chan_report)==true))){ ++ if (iabsscoex->coex.ht40_intolerant || iabsscoex->coex.ht20_width_req ++ || (((skb->data_len - sizeof(struct wifi_frame)) > (sizeof(struct wifi_mac_action_bss_coex_frame))) ++ && (wifi_mac_recv_bss_intol_channelCheck(wifimac, &iabsscoex->chan_report)==true))){ + -+ sta->sta_flags_ext |= WIFINET_NODE_40_INTOLERANT; -+ sta->sta_chbw = WIFINET_BWC_WIDTH20; -+ sta->sta_htcap &= ~WIFINET_HTCAP_SUPPORTCBW40; ++ sta->sta_flags_ext |= WIFINET_NODE_40_INTOLERANT; ++ sta->sta_chbw = WIFINET_BWC_WIDTH20; ++ sta->sta_htcap &= ~WIFINET_HTCAP_SUPPORTCBW40; + -+ sta->sta_wnet_vif->vm_curchan->chan_bw = WIFINET_BWC_WIDTH20; -+ sta->sta_wnet_vif->vm_bandwidth = WIFINET_BWC_WIDTH20; -+ sta->sta_wnet_vif->scnd_chn_offset = WIFINET_HTINFO_EXTOFFSET_NA; -+ sta->sta_wnet_vif->vm_htcap &= ~WIFINET_HTCAP_SUPPORTCBW40; ++ if (sta->sta_wnet_vif->vm_curchan != NULL) ++ sta->sta_wnet_vif->vm_curchan->chan_bw = WIFINET_BWC_WIDTH20; + -+ wifi_mac_change_cbw(wifimac, 1); ++ sta->sta_wnet_vif->vm_bandwidth = WIFINET_BWC_WIDTH20; ++ sta->sta_wnet_vif->scnd_chn_offset = WIFINET_HTINFO_EXTOFFSET_NA; ++ sta->sta_wnet_vif->vm_htcap &= ~WIFINET_HTCAP_SUPPORTCBW40; ++ ++ wifi_mac_change_cbw(wifimac, 1); ++ } ++ } else { ++ AML_OUTPUT("addr1:%s\n", ether_sprintf(wh->i_addr1)); ++ AML_OUTPUT("addr2:%s\n", ether_sprintf(wh->i_addr2)); ++ AML_OUTPUT("addr3:%s\n", ether_sprintf(wh->i_addr3)); + } + break; + ++ case WIFINET_ACT_PUBLIC_CSA: ++ if ((wnet_vif->vm_opmode == WIFINET_M_STA) ++ && (wnet_vif->vm_state == WIFINET_S_CONNECTED) ++ && (WIFINET_ADDR_EQ(sta->sta_bssid, wh->i_addr2))) { ++ csa_frame = (struct wifi_mac_action_csa_frame *) frm; ++ sta->sta_channel_switch_mode = csa_frame->csa.chan_switch_mode; ++ sta->sta_chan_switch_chan = csa_frame->csa.new_chan_num; ++ AML_OUTPUT("csa action frame:0x%x 0x%x 0x%x 0x%x\n", csa_frame->csa.chan_switch_mode, csa_frame->csa.new_chan_num, ++ csa_frame->csa.new_operation_class, csa_frame->csa.chan_switch_count); ++ os_timer_ex_start_period(&sta->csa_timer, csa_frame->csa.chan_switch_count * wnet_vif->vm_bcn_intval); ++ } else { ++ AML_OUTPUT("addr1:%s\n", ether_sprintf(wh->i_addr1)); ++ AML_OUTPUT("addr2:%s\n", ether_sprintf(wh->i_addr2)); ++ AML_OUTPUT("addr3:%s\n", ether_sprintf(wh->i_addr3)); ++ } ++ break; ++ + default: + vm_cfg80211_notify_mgmt_rx(wnet_vif, channel, os_skb_data(skb),os_skb_get_pktlen(skb)); + break; @@ -101550,7 +103068,7 @@ index 000000000000..541580dba475 + break; + + case WIFINET_ACTION_HT_SMPOWERSAVE: -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + WIFINET_VERIFY_LENGTH(efrm - frm, sizeof(struct wifi_mac_action_ht_smpowersave)); + + iasmpowersave = (struct wifi_mac_action_ht_smpowersave *) frm; @@ -101841,6 +103359,11 @@ index 000000000000..541580dba475 + } + + skb_subfrm = skb_clone(skb, GFP_ATOMIC); ++ ++ if (!skb_subfrm) { ++ pr_warn("AMSDU: failed to clone sub frame\n"); ++ goto err_amsdu; ++ } + os_skb_pull(skb, roundup(subfrm_len, 4)); + + wifi_mac_amsdu_subframe_decap(skb_subfrm); @@ -101896,12 +103419,101 @@ index 000000000000..541580dba475 + return; +} + ++void wifi_mac_csa_wait_task(SYS_TYPE param1,SYS_TYPE param2, SYS_TYPE param3,SYS_TYPE param4,SYS_TYPE param5) ++{ ++ struct wifi_mac *wifimac = (struct wifi_mac *)param1; ++ struct wlan_net_vif *wnet_vif = (struct wlan_net_vif *)param2; ++ unsigned char ret_char = (unsigned char)param3; ++ struct wifi_channel *vmac_chan = (struct wifi_channel *)param4; ++ ++ /* ++ unsigned int delay_ms = 0; ++ while ((wifimac->wm_flags & WIFINET_F_DOTH) && (wifimac->wm_flags & WIFINET_F_CHANSWITCH) && delay_ms < 1000) { ++ msleep(10); ++ delay_ms += 10; ++ } ++ AML_OUTPUT("delay time [%d]\n", delay_ms); ++ */ ++ ++ if ((wnet_vif->vm_mainsta->sta_channel_switch_mode == 1) && (ret_char == true) && concurrent_check_is_vmac_same_pri_channel(wifimac)) { ++ wnet_vif->vm_switchchan = vmac_chan; ++ wnet_vif->vm_chan_switch_scan_flag = 1; ++ wifi_mac_start_scan(wnet_vif, WIFINET_SCANCFG_USERREQ | WIFINET_SCANCFG_ACTIVE | WIFINET_SCANCFG_FLUSH | ++ WIFINET_SCANCFG_CREATE, wnet_vif->vm_des_nssid, wnet_vif->vm_des_ssid); ++ } else { ++ wnet_vif->vm_mainsta->sta_channel_switch_mode = 0; ++ } ++} ++ ++ ++int wifi_mac_handle_csa(struct wlan_net_vif *wnet_vif, struct wifi_station *sta, int chan) ++{ ++ struct wifi_mac *wifimac = wnet_vif->vm_wmac; ++ struct wifi_mac_ie_vht_wide_bw_switch *bw_chan_switch = (struct wifi_mac_ie_vht_wide_bw_switch *)sta->sta_wide_bw_ch_sw_sub_ie; ++ struct wifi_channel *vmac_chan = NULL; ++ int bw = 0, center_chan = 0; ++ unsigned char ret_char = false; ++ ++ center_chan = chan; ++ ++ if (bw_chan_switch->elem_len != 0) { ++ center_chan = bw_chan_switch->new_ch_freq_seg1; ++ if (bw_chan_switch->new_ch_width == NEW_CHANNEL_BANDWIDTH40) { ++ bw = WIFINET_BWC_WIDTH40; ++ } else if (bw_chan_switch->new_ch_width == NEW_CHANNEL_BANDWIDTH80) { ++ bw = WIFINET_BWC_WIDTH80; ++ } else { ++ ERROR_DEBUG_OUT("not support new_ch_width %d \n",bw_chan_switch->new_ch_width); ++ } ++ AML_OUTPUT("station channel switch chan:%d bw:%d center_chan:%d \n", chan, bw, center_chan); ++ } ++ ++ sta->sta_chbw = bw; ++ ++ vmac_chan = wifi_mac_find_chan(wifimac, chan, bw, center_chan); ++ if ((vmac_chan == WIFINET_CHAN_ERR) || (vmac_chan == wnet_vif->vm_curchan)) { ++ if (vmac_chan == WIFINET_CHAN_ERR) { ++ ERROR_DEBUG_OUT("null chan:%d bw:%d center_chan:%d\n", chan, bw, center_chan); ++ return ret_char; ++ } else { ++ wnet_vif->vm_mainsta->sta_channel_switch_mode = 0; ++ } ++ } else { ++ ret_char = wifi_mac_set_wnet_vif_channel(wnet_vif, chan, bw, center_chan,CHANNEL_CONNECT_FLAG | CHANNEL_RESTORE_FLAG); ++ wifi_mac_add_work_task(wifimac, vm_cfg80211_chan_switch_notify_task, NULL, (SYS_TYPE)wifimac, (SYS_TYPE)wnet_vif, 0, (SYS_TYPE)vmac_chan, 0); ++ } ++ ++ if ((wifimac->wm_nrunning > 1) && !concurrent_check_is_vmac_same_pri_channel(wifimac)) { ++ if (wifimac->wm_vsdb_slot == CONCURRENT_SLOT_NONE) { ++ if ((wnet_vif->vm_p2p_support == 1) || (wnet_vif->vm_opmode == WIFINET_M_HOSTAP)) { ++ wifimac->wm_vsdb_slot = CONCURRENT_SLOT_P2P; ++ } else { ++ wifimac->wm_vsdb_slot = CONCURRENT_SLOT_STA; ++ } ++ wifi_mac_set_vsdb_task(wifimac, wnet_vif, ENABLE); ++ } ++ ++ if (IS_APSTA_CONCURRENT(aml_wifi_get_con_mode()) && concurrent_check_vmac_is_AP(wifimac)) { ++ channel_switch_announce_trigger(wifimac, wnet_vif->vm_curchan); ++ } ++ } ++ ++ wifi_mac_add_work_task(wifimac, wifi_mac_csa_wait_task, NULL, (SYS_TYPE)wifimac, (SYS_TYPE)wnet_vif, (SYS_TYPE)ret_char, (SYS_TYPE)vmac_chan, 0); ++ return ret_char; ++} ++ ++int wifi_mac_csa_handle_timeout(void *arg) ++{ ++ struct wifi_station *sta = (struct wifi_station *)arg; ++ wifi_mac_handle_csa(sta->sta_wnet_vif, sta, sta->sta_chan_switch_chan); ++ return OS_TIMER_NOT_REARMED; ++} diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_recv.h b/drivers/net/wireless/w1/vmac/wifi_mac_recv.h new file mode 100644 -index 000000000000..85ff9f94bd9a +index 0000000000000000000000000000000000000000..109dcf46621516702e0e0eafae6172915d8487b7 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_recv.h -@@ -0,0 +1,93 @@ +@@ -0,0 +1,97 @@ +#ifndef __VMAC_WIFI_INPUT_H__ +#define __VMAC_WIFI_INPUT_H__ + @@ -101994,10 +103606,14 @@ index 000000000000..85ff9f94bd9a +int wifi_mac_send_arp_req(struct wlan_net_vif *wnet_vif); +int wifi_mac_set_arp_rsp(struct wlan_net_vif *wnet_vif) ; + ++unsigned short wifi_mac_eth_type_trans(struct sk_buff *skb, struct net_device *dev); ++int wifi_mac_handle_csa(struct wlan_net_vif *wnet_vif, struct wifi_station *sta, int chan); ++int wifi_mac_csa_handle_timeout(void *arg); ++void wifi_mac_csa_wait_task(SYS_TYPE param1,SYS_TYPE param2, SYS_TYPE param3,SYS_TYPE param4,SYS_TYPE param5); +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_rx_status.h b/drivers/net/wireless/w1/vmac/wifi_mac_rx_status.h new file mode 100644 -index 000000000000..761e53224e6f +index 0000000000000000000000000000000000000000..761e53224e6f6e8ccc61ae74cd4db633d58e1101 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_rx_status.h @@ -0,0 +1,22 @@ @@ -102025,7 +103641,7 @@ index 000000000000..761e53224e6f +#endif//__WIFI_MAC_RX_STATUS_H__ diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_sae.c b/drivers/net/wireless/w1/vmac/wifi_mac_sae.c new file mode 100644 -index 000000000000..16e05117cc59 +index 0000000000000000000000000000000000000000..c9935373fff3877223ff9e7f9765419c157f6b5a --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_sae.c @@ -0,0 +1,198 @@ @@ -102211,7 +103827,7 @@ index 000000000000..16e05117cc59 +{ + struct cfg80211_external_auth_params params = {0}; + -+ printk("%s\n", __func__); ++ pr_debug("%s\n", __func__); + params.key_mgmt_suite = 0x00; + params.key_mgmt_suite |= 0x0F << 8; + params.key_mgmt_suite |= 0xAC << 16; @@ -102229,64 +103845,65 @@ index 000000000000..16e05117cc59 +#endif//AML_WPA3 diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_sae.h b/drivers/net/wireless/w1/vmac/wifi_mac_sae.h new file mode 100644 -index 000000000000..09c730e54d84 +index 0000000000000000000000000000000000000000..135cd7a5dfb2c6fe6aa3a81224a37813b7f096e8 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_sae.h @@ -0,0 +1,47 @@ -+/* -+ **************************************************************************************** -+ * -+ * Copyright (C) Amlogic 2010-2014 -+ * -+ * Project: 11N 80211 mac layer Software -+ * -+ * Description: -+ * wifi_mac layer interface function/interface use by driver layer -+ * -+ * -+ **************************************************************************************** -+ */ -+ -+#ifndef _WIFI_MAC_SAE_H_ -+#define _WIFI_MAC_SAE_H_ -+ -+#include "wifi_mac_if.h" -+ -+#define MAXPMKID 16/* max # PMKID cache entries NDIS */ -+#define WL_NUM_PMKIDS_MAX MAXPMKID -+ -+typedef struct _aml_pmkid_cache { -+ unsigned char in_use; -+ unsigned char bssid[6]; -+ unsigned char pmkid[16]; -+ unsigned char ssid[33]; -+ unsigned char *ssid_octet; -+ unsigned short ssid_length; -+} aml_pmkid_cache; -+ -+struct aml_pmk_list { -+ unsigned char pmkid_count; -+ aml_pmkid_cache pmkid_cache[MAXPMKID]; -+}; -+ -+unsigned char wifi_mac_pmkid_vattach(struct wlan_net_vif *wnet_vif); -+void wifi_mac_pmkid_detach(struct wlan_net_vif *wnet_vif); -+int aml_cfg80211_set_pmksa(struct wiphy *wiphy, struct net_device *dev, struct cfg80211_pmksa *pmksa); -+int aml_pmkid_cache_index(struct wlan_net_vif *wnet_vif, const unsigned char *bssid); -+int aml_cfg80211_del_pmksa(struct wiphy *wiphy, struct net_device *dev, struct cfg80211_pmksa *pmksa); -+void aml_del_pmksa_by_index(struct wlan_net_vif *wnet_vif, const unsigned char *bssid); -+int aml_cfg80211_flush_pmksa(struct wiphy *wiphy, struct net_device *dev); -+void wifi_mac_trigger_sae(struct wifi_station *sta); -+ -+#endif//_WIFI_MAC_SAE_H_ -+ ++/* ++ **************************************************************************************** ++ * ++ * Copyright (C) Amlogic 2010-2014 ++ * ++ * Project: 11N 80211 mac layer Software ++ * ++ * Description: ++ * wifi_mac layer interface function/interface use by driver layer ++ * ++ * ++ **************************************************************************************** ++ */ ++ ++#ifndef _WIFI_MAC_SAE_H_ ++#define _WIFI_MAC_SAE_H_ ++ ++#include "wifi_mac_if.h" ++ ++#define MAXPMKID 16/* max # PMKID cache entries NDIS */ ++#define WL_NUM_PMKIDS_MAX MAXPMKID ++ ++typedef struct _aml_pmkid_cache { ++ unsigned char in_use; ++ unsigned char bssid[6]; ++ unsigned char pmkid[16]; ++ unsigned char ssid[33]; ++ unsigned char *ssid_octet; ++ unsigned short ssid_length; ++} aml_pmkid_cache; ++ ++struct aml_pmk_list { ++ unsigned char pmkid_count; ++ aml_pmkid_cache pmkid_cache[MAXPMKID]; ++}; ++ ++unsigned char wifi_mac_pmkid_vattach(struct wlan_net_vif *wnet_vif); ++void wifi_mac_pmkid_detach(struct wlan_net_vif *wnet_vif); ++int aml_cfg80211_set_pmksa(struct wiphy *wiphy, struct net_device *dev, struct cfg80211_pmksa *pmksa); ++int aml_pmkid_cache_index(struct wlan_net_vif *wnet_vif, const unsigned char *bssid); ++int aml_cfg80211_del_pmksa(struct wiphy *wiphy, struct net_device *dev, struct cfg80211_pmksa *pmksa); ++void aml_del_pmksa_by_index(struct wlan_net_vif *wnet_vif, const unsigned char *bssid); ++int aml_cfg80211_flush_pmksa(struct wiphy *wiphy, struct net_device *dev); ++void wifi_mac_trigger_sae(struct wifi_station *sta); ++ ++#endif//_WIFI_MAC_SAE_H_ ++ diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_scan.c b/drivers/net/wireless/w1/vmac/wifi_mac_scan.c new file mode 100644 -index 000000000000..e53232e88420 +index 0000000000000000000000000000000000000000..d4d5e9ba835d96bdf003fa1e3d96e03183a6af2d --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_scan.c -@@ -0,0 +1,2290 @@ +@@ -0,0 +1,2353 @@ +#include "wifi_mac_com.h" ++#include "wifi_mac_scan.h" +#include "wifi_mac_rate.h" +#include "wifi_iwpriv_cmd.h" + @@ -102352,45 +103969,45 @@ index 000000000000..e53232e88420 + fail = 0; + if (wifi_mac_chan_num_avail(wifimac, wifi_mac_chan2ieee(wifimac, scaninfo->SI_chan)) == false) { + fail |= STA_MATCH_ERR_CHAN; -+ //printk("%s(%d) fail 0x%x\n", __func__, __LINE__, fail); ++ //pr_err("%s(%d) fail 0x%x\n", __func__, __LINE__, fail); + } + + if (wnet_vif->vm_opmode == WIFINET_M_IBSS) { + if ((scaninfo->SI_capinfo & WIFINET_CAPINFO_IBSS) == 0) { + fail |= STA_MATCH_ERR_BSS; -+ //printk("%s(%d) fail 0x%x\n", __func__, __LINE__, fail); ++ //pr_err("%s(%d) fail 0x%x\n", __func__, __LINE__, fail); + } + + } else { + if ((scaninfo->SI_capinfo & WIFINET_CAPINFO_ESS) == 0) { + fail |= STA_MATCH_ERR_BSS; -+ //printk("%s(%d) fail 0x%x\n", __func__, __LINE__, fail); ++ //pr_err("%s(%d) fail 0x%x\n", __func__, __LINE__, fail); + } + } + + if (wnet_vif->vm_flags & WIFINET_F_PRIVACY) { + if ((scaninfo->SI_capinfo & WIFINET_CAPINFO_PRIVACY) == 0) { + fail |= STA_MATCH_ERR_PRIVACY; -+ //printk("%s(%d) fail 0x%x\n", __func__, __LINE__, fail); ++ //pr_err("%s(%d) fail 0x%x\n", __func__, __LINE__, fail); + } + + } else { + if (scaninfo->SI_capinfo & WIFINET_CAPINFO_PRIVACY) { + fail |= STA_MATCH_ERR_PRIVACY; -+ //printk("%s(%d) fail 0x%x\n", __func__, __LINE__, fail); ++ //pr_err("%s(%d) fail 0x%x\n", __func__, __LINE__, fail); + } + } + + if (!check_rate(wnet_vif, scaninfo)) { + fail |= STA_MATCH_ERR_RATE; -+ //printk("%s(%d) fail 0x%x\n", __func__, __LINE__, fail); ++ //pr_err("%s(%d) fail 0x%x\n", __func__, __LINE__, fail); + } + + if ((wnet_vif->vm_fixed_rate.mode == WIFINET_FIXED_RATE_NONE) + || (wnet_vif->vm_fixed_rate.rateinfo & WIFINET_RATE_MCS)) { + if (!check_ht_rate(wnet_vif, scaninfo)) { + fail |= STA_MATCH_ERR_HTRATE; -+ //printk("%s(%d) fail 0x%x\n", __func__, __LINE__, fail); ++ //pr_err("%s(%d) fail 0x%x\n", __func__, __LINE__, fail); + } + } + @@ -102398,18 +104015,18 @@ index 000000000000..e53232e88420 + if (!(wnet_vif->vm_flags & WIFINET_F_IGNORE_SSID) + && ((ss->ss_nssid == 0) || (match_ssid(scaninfo->SI_ssid, ss->ss_nssid, ss->ss_ssid) == 0))) { + fail |= STA_MATCH_ERR_SSID; -+ //printk("%s(%d) fail 0x%x, ss->ss_nssid:%d\n", __func__, __LINE__, fail, ss->ss_nssid); ++ //pr_err("%s(%d) fail 0x%x, ss->ss_nssid:%d\n", __func__, __LINE__, fail, ss->ss_nssid); + } + + if ((wnet_vif->vm_flags & WIFINET_F_DESBSSID) + && !WIFINET_ADDR_EQ(wnet_vif->vm_des_bssid, scaninfo->SI_bssid)) { + fail |= STA_MATCH_ERR_BSSID; -+ //printk("%s(%d) fail 0x%x\n", __func__, __LINE__, fail); ++ //pr_err("%s(%d) fail 0x%x\n", __func__, __LINE__, fail); + } + + if (se->connectcnt >= WIFINET_CONNECT_FAILS) { + fail |= STA_MATCH_ERR_STA_FAILS_MAX; -+ //printk("%s(%d) fail 0x%x\n", __func__, __LINE__, fail); ++ //pr_err("%s(%d) fail 0x%x\n", __func__, __LINE__, fail); + } + + if (!(fail & STA_MATCH_ERR_SSID)) { @@ -102568,6 +104185,11 @@ index 000000000000..e53232e88420 + return 0; + } + ++ if (wnet_vif->vm_mainsta && (wnet_vif->vm_mainsta->connect_status != CONNECT_CONNECTING)) { ++ ERROR_DEBUG_OUT("connection stop, connect_status:%d\n", wnet_vif->vm_mainsta->connect_status); ++ return 0; ++ } ++ + KASSERT((wnet_vif->vm_opmode == WIFINET_M_IBSS) + ||(wnet_vif->vm_opmode == WIFINET_M_STA) + ||(wnet_vif->vm_opmode == WIFINET_M_P2P_DEV) @@ -102662,7 +104284,7 @@ index 000000000000..e53232e88420 + return 0; +} + -+void get_ovlapping_chan_index(struct wifi_mac *wifimac, unsigned char center_chan, unsigned char bw, ++static void get_ovlapping_chan_index(struct wifi_mac *wifimac, unsigned char center_chan, unsigned char bw, + unsigned char *low, unsigned char *up) { + unsigned char step = 0; + unsigned char is_2g = 0; @@ -102741,7 +104363,7 @@ index 000000000000..e53232e88420 + +} + -+void wifi_mac_update_chan_overlapping_map(struct wlan_net_vif *wnet_vif) { ++static void wifi_mac_update_chan_overlapping_map(struct wlan_net_vif *wnet_vif) { + struct wifi_mac *wifimac = wnet_vif->vm_wmac; + struct wifi_mac_scan_state *ss = wifimac->wm_scan; + struct scaninfo_table *st = ss->ScanTablePriv; @@ -102841,17 +104463,14 @@ index 000000000000..e53232e88420 + + if (wifi_mac_is_in_noisy_environment(wifimac)) { + wifimac->scan_noisy_status = WIFINET_S_SCAN_ENV_NOISE; -+ printk("WiFi channel status: NOISY environment detected\n"); + + } else if (wifi_mac_is_in_clear_environment(wifimac)) { + //clear environment, set to max gain + wifimac->drv_priv->drv_ops.set_channel_rssi(wifimac->drv_priv, 174); + wifimac->scan_noisy_status = WIFINET_S_SCAN_ENV_CLEAR; -+ printk("WiFi channel status: CLEAR environment detected\n"); + + } else { + wifimac->scan_noisy_status = WIFINET_S_SCAN_ENV_MID; -+ printk("WiFi channel status: MODERATE environment\n"); + } + } + @@ -102879,7 +104498,7 @@ index 000000000000..e53232e88420 + WIFI_SCAN_SE_LIST_UNLOCK(st); +} + -+void update_roaming_candidate_chan(struct wifi_mac_scan_state *ss, struct wifi_channel *apchan, int rssi) ++static void update_roaming_candidate_chan(struct wifi_mac_scan_state *ss, struct wifi_channel *apchan, int rssi) +{ + int i =0; + struct wifi_candidate_channel * worst_chan = NULL; @@ -102926,7 +104545,7 @@ index 000000000000..e53232e88420 + int nssid = sp->ssid[1]; + static struct wifi_channel * apchan = NULL; + -+ apchan= wifi_mac_scan_sta_get_ap_channel(wnet_vif, (struct wifi_mac_scan_param *)sp); ++ apchan = wifi_mac_scan_sta_get_ap_channel(wnet_vif, sp->chan, sp->htinfo, sp->htcap, sp->vht_opt); + if (apchan == NULL) { + DPRINTF(AML_DEBUG_INFO, "%s(%d) apchan = %p\n", __func__,__LINE__,apchan); + return; @@ -102935,7 +104554,7 @@ index 000000000000..e53232e88420 + if ((sp->ssid[2] != 0) && ss->ss_ssid->len && nssid + && !(memcmp(sp->ssid+2, ss->roaming_ssid.ssid, nssid))) { + update_roaming_candidate_chan(ss, apchan, rssi); -+// printk("\n\n[Roaming ssid:%s] len:%d chan:%d\n\n", ssidie_sprintf(sp->ssid), nssid, apchan->chan_pri_num); ++// pr_debug("\n\n[Roaming ssid:%s] len:%d chan:%d\n\n", ssidie_sprintf(sp->ssid), nssid, apchan->chan_pri_num); + } + +} @@ -102965,7 +104584,7 @@ index 000000000000..e53232e88420 + AML_PRINT(AML_DBG_MODULES_SCAN, " %d %s chan %d \n", sp->ssid[1], ssidie_sprintf(sp->ssid), sp->chan); + } + -+ apchan = wifi_mac_scan_sta_get_ap_channel(wnet_vif, (struct wifi_mac_scan_param *)sp); ++ apchan = wifi_mac_scan_sta_get_ap_channel(wnet_vif, sp->chan, sp->htinfo, sp->htcap, sp->vht_opt); + if (apchan == NULL) { + AML_PRINT(AML_DBG_MODULES_SCAN, "ssid %s ,apchan = %p\n", ssidie_sprintf(sp->ssid), apchan); + return; @@ -102982,6 +104601,7 @@ index 000000000000..e53232e88420 + } + + ise = &se->scaninfo; ++ ise->SI_frame_len = sp->frame_len; + if (sp->rsn != NULL) { + saveie(&ise->SI_rsn_ie[0], sp->rsn); + @@ -103065,7 +104685,9 @@ index 000000000000..e53232e88420 + saveie(&ise->SI_htinfo_ie[0], sp->htinfo); + saveie(&ise->SI_country_ie[0], sp->country); + saveie(&ise->SI_wpa_ie[0], sp->wpa); -+ saveie(&ise->SI_wps_ie[0], sp->wps); ++ if (sp->wps != NULL) { ++ saveie(&ise->SI_wps_ie[0], sp->wps); ++ } + + if (se->connectcnt && ((jiffies - se->ConnectTime) > WIFINET_CONNECT_CNT_AGE*HZ)) { + se->connectcnt = 0; @@ -103087,12 +104709,15 @@ index 000000000000..e53232e88420 + + hash = STA_HASH(macaddr); + -+ WIFI_SCAN_SE_LIST_LOCK(st); + if (oldse == NULL) { ++ /* Need lock here, because when 'olsde' is NULL, this ++ * function was called with unlocked list. ++ */ ++ WIFI_SCAN_SE_LIST_LOCK(st); + list_add(&se->se_hash, &st->st_hash[hash]); + list_add_tail(&se->se_list, &st->st_entry); ++ WIFI_SCAN_SE_LIST_UNLOCK(st); + } -+ WIFI_SCAN_SE_LIST_UNLOCK(st); + + for (i=0; iss_nssid; i++) { + if (sp->ssid && sp->ssid[1] > 0 && sp->ssid[1] <= WIFINET_NWID_LEN) { @@ -103110,15 +104735,16 @@ index 000000000000..e53232e88420 + return; + +fail: -+ WIFI_SCAN_SE_LIST_LOCK(st); -+ if (WIFINET_ADDR_EQ(se, oldse)) { -+ list_del_init(&se->se_list); -+ list_del_init(&se->se_hash); -+ printk("[Micro]%s_%d,delete oldse\n", __func__, __LINE__); -+ } -+ WIFI_SCAN_SE_LIST_UNLOCK(st); ++ if (oldse) { ++ /* We failed to update some existing entry. Remove it from ++ * list before freeing memory. We don't need lock here, ++ * because list is locked by caller! ++ */ ++ list_del_init(&se->se_list); ++ list_del_init(&se->se_hash); ++ } + FREE(se,"sta_add.se"); -+ printk("[Micro]%s_%d\n", __func__, __LINE__); ++ pr_debug("[Micro]%s_%d\n", __func__, __LINE__); + return; +} + @@ -103192,7 +104818,7 @@ index 000000000000..e53232e88420 + if (wnet_vif->vm_chan_switch_scan_flag) { + ss->scan_chan_wait = wnet_vif->vm_scan_time_chan_switch; + } -+ //printk("%s change scan time to:%d\n", __func__, ss->scan_chan_wait); ++ //pr_debug("%s change scan time to:%d\n", __func__, ss->scan_chan_wait); + return; +} + @@ -103246,11 +104872,11 @@ index 000000000000..e53232e88420 + ss->ss_chans[i] = wnet_vif->vm_connchan.conn_chan[i]; + ss->ss_chans[i + wnet_vif->vm_connchan.num] = wnet_vif->vm_connchan.conn_chan[i]; + ss->ss_chans[i + (wnet_vif->vm_connchan.num * 2)] = wnet_vif->vm_connchan.conn_chan[i]; -+ printk("add scan connect chans:%d\n", wnet_vif->vm_connchan.conn_chan[i]->chan_pri_num); ++ pr_debug("add scan connect chans:%d\n", wnet_vif->vm_connchan.conn_chan[i]->chan_pri_num); + } + + } else if (wnet_vif->vm_chan_roaming_scan_flag && !wnet_vif->vm_wmac->wm_scan->roaming_full_scan) { -+ printk("scan roaming_candidate_chans \n"); ++ pr_debug("scan roaming_candidate_chans \n"); + WIFI_ROAMING_CHANNLE_LOCK(ss); + ss->scan_last_chan_index = wnet_vif->vm_wmac->wm_scan->roaming_candidate_chans_cnt; + @@ -103264,8 +104890,7 @@ index 000000000000..e53232e88420 + ss->ss_chans[0] = wnet_vif->vm_switchchan; + + } else { -+ /* Removed verbose scan log to reduce noise */ -+ /* printk("scan all chans \n"); */ ++ pr_debug("scan all chans \n"); + + /*clean roamin candidate channel*/ + WIFI_ROAMING_CHANNLE_LOCK(wnet_vif->vm_wmac->wm_scan); @@ -103343,7 +104968,7 @@ index 000000000000..e53232e88420 + unsigned char j; + + os_timer_ex_cancel(&ss->ss_probe_timer, CANCEL_SLEEP); -+ //printk("%s, ss->scan_StateFlags:%08x, ss->ss_nssid:%d\n", __func__, ss->scan_StateFlags, ss->ss_nssid); ++ //pr_debug("%s, ss->scan_StateFlags:%08x, ss->ss_nssid:%d\n", __func__, ss->scan_StateFlags, ss->ss_nssid); + + if (ss->scan_CfgFlags & WIFINET_SCANCFG_ACTIVE) + { @@ -103361,13 +104986,13 @@ index 000000000000..e53232e88420 + } +} + -+int wifi_mac_scan_send_probe_timeout_ex(void *arg) ++static int wifi_mac_scan_send_probe_timeout_ex(void *arg) +{ + struct wifi_mac_scan_state *ss = (struct wifi_mac_scan_state *) arg; + struct wlan_net_vif *wnet_vif = ss->VMacPriv; + struct wifi_mac *wifimac = wnet_vif->vm_wmac; + -+ //printk("%s, ss->scan_StateFlags:%08x\n", __func__, ss->scan_StateFlags); ++ //pr_debug("%s, ss->scan_StateFlags:%08x\n", __func__, ss->scan_StateFlags); + + WIFI_SCAN_LOCK(ss); + if (ss->scan_StateFlags & SCANSTATE_F_SEND_PROBEREQ_AGAIN) { @@ -103413,20 +105038,20 @@ index 000000000000..e53232e88420 +} + + -+void wifi_mac_scan_chk_leakap_hrtimer_attach(struct wifi_mac *wifimac) ++static void wifi_mac_scan_chk_leakap_hrtimer_attach(struct wifi_mac *wifimac) +{ + hrtimer_init(&wifimac->wm_scan->scan_hr_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + wifimac->wm_scan->scan_hr_timer.function = wifi_mac_scan_chk_leakap_done_process; +} + + -+void wifi_mac_scan_chk_leakap_hrtimer_start(struct wifi_mac *wifimac) ++static void wifi_mac_scan_chk_leakap_hrtimer_start(struct wifi_mac *wifimac) +{ + wifimac->wm_scan->scan_kt = ktime_set(0, 2000000); + hrtimer_start(&wifimac->wm_scan->scan_hr_timer, wifimac->wm_scan->scan_kt, HRTIMER_MODE_REL); +} + -+void wifi_mac_scan_chk_leakap_hrtimer_cancel(struct wifi_mac *wifimac) ++static void wifi_mac_scan_chk_leakap_hrtimer_cancel(struct wifi_mac *wifimac) +{ + hrtimer_cancel(&wifimac->wm_scan->scan_hr_timer); +} @@ -103446,7 +105071,7 @@ index 000000000000..e53232e88420 +} + + -+void wifi_mac_scan_channel(struct wifi_mac *wifimac) ++static void wifi_mac_scan_channel(struct wifi_mac *wifimac) +{ + struct wifi_mac_scan_state *ss = wifimac->wm_scan; + struct wlan_net_vif *wnet_vif = ss->VMacPriv; @@ -103454,7 +105079,7 @@ index 000000000000..e53232e88420 + struct wifi_channel *chan; + enum wifi_mac_macmode last_mac_mode; + -+ //printk("%s, ss->scan_StateFlags:%08x\n", __func__, ss->scan_StateFlags); ++ //pr_debug("%s, ss->scan_StateFlags:%08x\n", __func__, ss->scan_StateFlags); + if (!(ss->scan_StateFlags & SCANSTATE_F_CHANNEL_SWITCH_COMPLETE)) { + return; + } @@ -103535,13 +105160,13 @@ index 000000000000..e53232e88420 + DPRINTF(AML_DEBUG_SCAN, "%s OS_SET_TIMER = %d next_chn\n", __func__, ss->scan_chan_wait); +} + -+void wifi_mac_switch_scan_channel(struct wifi_mac *wifimac) ++static void wifi_mac_switch_scan_channel(struct wifi_mac *wifimac) +{ + struct wifi_mac_scan_state *ss = wifimac->wm_scan; + struct wifi_channel *chan; + struct wlan_net_vif *wnet_vif = ss->VMacPriv; + -+ //printk("%s, ss->scan_StateFlags:%08x\n", __func__, ss->scan_StateFlags); ++ //pr_debug("%s, ss->scan_StateFlags:%08x\n", __func__, ss->scan_StateFlags); + if (ss->scan_next_chan_index >= ss->scan_last_chan_index) { + DPRINTF(AML_DEBUG_ERROR, " %s (scan_next_chan_index >= scan_last_chan_index) drop!!!\n", __func__); + return; @@ -103577,7 +105202,7 @@ index 000000000000..e53232e88420 + } + + if (!((wifimac->wm_nrunning == 2) && (!concurrent_check_is_vmac_same_pri_channel(wifimac)))) { -+ //printk("%s\n", __func__); ++ //pr_debug("%s\n", __func__); + os_timer_ex_start_period(&ss->ss_scan_timer, ss->scan_chan_wait); + } + @@ -103631,7 +105256,7 @@ index 000000000000..e53232e88420 +} + + -+int wifi_mac_scan_buff_and_chk_tx(struct wifi_mac *wifimac) ++static int wifi_mac_scan_buff_and_chk_tx(struct wifi_mac *wifimac) +{ + struct wlan_net_vif *tmpwnet_vif = NULL, *tmpwnet_vif_next = NULL; + struct wifi_mac_scan_state *ss = wifimac->wm_scan; @@ -103656,7 +105281,7 @@ index 000000000000..e53232e88420 +} + + -+void wifi_mac_scan_notify_ap(struct wifi_mac *wifimac) ++static void wifi_mac_scan_notify_ap(struct wifi_mac *wifimac) +{ + struct wlan_net_vif *tmpwnet_vif = NULL, *tmpwnet_vif_next = NULL; + struct wifi_mac_scan_state *ss = wifimac->wm_scan; @@ -103670,7 +105295,7 @@ index 000000000000..e53232e88420 +} + + -+void wifi_mac_scan_timeout(SYS_TYPE param1,SYS_TYPE param2, ++static void wifi_mac_scan_timeout(SYS_TYPE param1,SYS_TYPE param2, + SYS_TYPE param3,SYS_TYPE param4,SYS_TYPE param5) +{ + struct wifi_mac_scan_state *ss = (struct wifi_mac_scan_state *) param1; @@ -103727,7 +105352,7 @@ index 000000000000..e53232e88420 + } + } + -+ //printk("%s, ss->scan_StateFlags:%08x, scandone:%d, need_notify_ap:%d\n", __func__, ss->scan_StateFlags, scandone, need_notify_ap); ++ //pr_debug("%s, ss->scan_StateFlags:%08x, scandone:%d, need_notify_ap:%d\n", __func__, ss->scan_StateFlags, scandone, need_notify_ap); + if (wifimac->wm_nrunning != 0) { + if (ss->scan_StateFlags & SCANSTATE_F_RESTORE) { + wifi_mac_restore_wnet_vif_channel(wnet_vif); @@ -103811,7 +105436,7 @@ index 000000000000..e53232e88420 + struct wlan_net_vif *wnet_vif = ss->VMacPriv; + struct wifi_mac *wifimac = wnet_vif->vm_wmac; + -+ //printk("%s, ss->scan_StateFlags:%08x\n", __func__, ss->scan_StateFlags); ++ //pr_debug("%s, ss->scan_StateFlags:%08x\n", __func__, ss->scan_StateFlags); + + WIFI_SCAN_LOCK(ss); + if (ss->scan_StateFlags & SCANSTATE_F_WAIT_TBTT) { @@ -103890,7 +105515,7 @@ index 000000000000..e53232e88420 + WIFI_SCAN_LOCK(ss); + if ((wnet_vif->wnet_vif_replaycounter != (int)param5) || (wifimac->wm_scanplayercnt != (unsigned long)param3) + || (ss->scan_StateFlags & SCANSTATE_F_START) || !(wifimac->wm_flags & WIFINET_F_SCAN)) { -+ printk("%s scan_StateFlags:%04x, wm_scanplayercnt:%ld\n", __func__, ss->scan_StateFlags, wifimac->wm_scanplayercnt); ++ pr_debug("%s scan_StateFlags:%04x, wm_scanplayercnt:%ld\n", __func__, ss->scan_StateFlags, wifimac->wm_scanplayercnt); + WIFI_SCAN_UNLOCK(ss); + return; + } @@ -103910,7 +105535,7 @@ index 000000000000..e53232e88420 + + //set up scan channel index to 0 + ss->scan_next_chan_index = 0; -+ printk("%s wm_nrunning:%d\n", __func__, wifimac->wm_nrunning); ++ pr_debug("%s wm_nrunning:%d\n", __func__, wifimac->wm_nrunning); + os_timer_ex_start_period(&ss->ss_scan_abort_timer, WIFINET_SCAN_ABORT_TIME); + + if (wifimac->wm_nrunning == 0) { @@ -103959,6 +105584,7 @@ index 000000000000..e53232e88420 + struct wifi_mac *wifimac = wnet_vif->vm_wmac; + int find_roaming_node = 0; + static int before_conn_scan_times = 0; ++ unsigned char vm_scan_before_connect_flag = 0; + + if (!(wifimac->wm_flags & WIFINET_F_SCAN)) { + ERROR_DEBUG_OUT("not in scan status\n"); @@ -103975,7 +105601,7 @@ index 000000000000..e53232e88420 + if (connect_wnet->vm_opmode == WIFINET_M_HOSTAP && + connect_wnet->vm_p2p->noa_app_ie[WIFINET_APPIE_FRAME_BEACON].length && + connect_wnet->vm_p2p->p2p_enable == 1) { -+ printk("%s,%d, clear noa ie\n", __func__, __LINE__); ++ pr_debug("%s,%d, clear noa ie\n", __func__, __LINE__); + connect_wnet->vm_p2p->ap_mode_set_noa_enable = 0; + wifi_mac_rm_app_ie(&connect_wnet->vm_p2p->noa_app_ie[WIFINET_APPIE_FRAME_BEACON]); + vm_p2p_update_beacon_app_ie(connect_wnet); @@ -103983,6 +105609,7 @@ index 000000000000..e53232e88420 + if (P2P_NoA_START_FLAG(connect_wnet->vm_p2p->HiP2pNoaCountNow)) { + p2p_noa_start_irq(connect_wnet->vm_p2p, wifimac->drv_priv); + } ++ connect_wnet->vm_p2p->HiP2pNoaCountNow = 0; + } + } else { + wifimac->drv_priv->stop_noa_flag = 0; @@ -104023,8 +105650,11 @@ index 000000000000..e53232e88420 + before_conn_scan_times = 0; + + } else { -+ if (wnet_vif->vm_scan_before_connect_flag) { ++ if (wnet_vif->vm_scan_before_connect_flag || (ss->scan_CfgFlags & WIFINET_SCANCFG_CONNECT)) { + before_conn_scan_times++; ++ vm_scan_before_connect_flag = wnet_vif->vm_scan_before_connect_flag; ++ } else { ++ before_conn_scan_times = 0; + } + } + } else if ((wnet_vif->vm_opmode == WIFINET_M_HOSTAP) @@ -104093,7 +105723,7 @@ index 000000000000..e53232e88420 + } + + if (before_conn_scan_times == 1) { -+ wnet_vif->vm_scan_before_connect_flag = 1; ++ wnet_vif->vm_scan_before_connect_flag = vm_scan_before_connect_flag; + wifi_mac_start_scan(wnet_vif, WIFINET_SCANCFG_USERREQ | WIFINET_SCANCFG_ACTIVE | WIFINET_SCANCFG_FLUSH | + WIFINET_SCANCFG_CREATE, wnet_vif->vm_des_nssid, wnet_vif->vm_des_ssid); + @@ -104107,7 +105737,7 @@ index 000000000000..e53232e88420 + before_conn_scan_times = 0; + } + -+ printk("%s---> scan finish, vid:%d, clean vm_flags 0x%x\n", __func__, wnet_vif->wnet_vif_id, wifimac->wm_flags); ++ pr_debug("%s---> scan finish, vid:%d, clean vm_flags 0x%x\n", __func__, wnet_vif->wnet_vif_id, wifimac->wm_flags); + os_timer_ex_start_period(&wnet_vif->vm_pwrsave.ips_timer_presleep, wnet_vif->vm_pwrsave.ips_inactivitytime); +} + @@ -104137,7 +105767,7 @@ index 000000000000..e53232e88420 + wifi_mac_ChangeChannel(wifimac, p2p_vmac->vm_p2p->work_channel, 0, p2p_vmac->wnet_vif_id, p2p_vmac->vm_opmode); + p2p_vmac->vm_p2p->p2p_flag &= ~P2P_WAIT_SWITCH_CHANNEL; + } else { -+ //printk("still have pkt in hal, wait\n"); ++ //pr_debug("still have pkt in hal, wait\n"); + p2p_vmac->vm_p2p->p2p_flag &= ~P2P_WAIT_SWITCH_CHANNEL; + p2p_vmac->vm_p2p->p2p_flag |= P2P_ALLOW_SWITCH_CHANNEL; + } @@ -104149,7 +105779,7 @@ index 000000000000..e53232e88420 + wifi_mac_ChangeChannel(wifimac, sta_vmac->vm_remainonchan, 0, sta_vmac->wnet_vif_id, sta_vmac->vm_opmode); + sta_vmac->vm_flags_ext2 &= ~WIFINET_FEXT2_SWITCH_CHANNEL; + } else { -+ //printk("still have pkt in hal, wait\n"); ++ //pr_debug("still have pkt in hal, wait\n"); + sta_vmac->vm_flags_ext2 &= ~WIFINET_FEXT2_SWITCH_CHANNEL; + sta_vmac->vm_flags_ext2 |= WIFINET_FEXT2_ALLOW_SWITCH_CHANNEL; + } @@ -104163,7 +105793,7 @@ index 000000000000..e53232e88420 + if (drv_priv->hal_priv->hal_ops.hal_tx_empty()) { + concurrent_vsdb_do_channel_change(wifimac); + } else { -+ //printk("still have pkt in hal, wait\n"); ++ //pr_debug("still have pkt in hal, wait\n"); + wifimac->wm_vsdb_flags |= CONCURRENT_NOTIFY_AP_SUCCESS; + } + } @@ -104207,7 +105837,8 @@ index 000000000000..e53232e88420 + + if (wifimac->wm_nrunning == 2) { + #ifdef CONFIG_CONCURRENT_MODE -+ if (wifimac->wm_vsdb_flags & CONCURRENT_NOTIFY_AP_SUCCESS) { ++ if ((wifimac->wm_vsdb_flags & CONCURRENT_NOTIFY_AP_SUCCESS) ++ || (wifimac->wm_vsdb_flags & CONCURRENT_AP_SWITCH_CHANNEL)) { + if (drv_priv->hal_priv->hal_ops.hal_tx_empty()) { + concurrent_vsdb_do_channel_change(wifimac); + } @@ -104225,7 +105856,7 @@ index 000000000000..e53232e88420 + if (wifimac->wm_flags & WIFINET_F_SCAN) + { + ss->scan_StateFlags |= SCANSTATE_F_CANCEL; -+// printk(" %s %d wnet_vif_id = %d\n",__func__,__LINE__,wnet_vif->wnet_vif_id); ++// pr_debug(" %s %d wnet_vif_id = %d\n",__func__,__LINE__,wnet_vif->wnet_vif_id); + if (ss->scan_StateFlags & SCANSTATE_F_START) + { + os_timer_ex_cancel(&wifimac->wm_scan->ss_scan_timer, 1); @@ -104269,7 +105900,7 @@ index 000000000000..e53232e88420 + } + } + -+ if (c->chan_cfreq1 != request->channels[j]->center_freq && !vm_is_p2p_connect_scan(wnet_vif, request)) { ++ if (c->chan_cfreq1 != request->channels[j]->center_freq) { + continue; + } + @@ -104295,7 +105926,7 @@ index 000000000000..e53232e88420 + return 0; +} + -+int wifi_mac_scan_before_connect(struct wifi_mac_scan_state *ss, struct wlan_net_vif *wnet_vif, int flags) ++static int wifi_mac_scan_before_connect(struct wifi_mac_scan_state *ss, struct wlan_net_vif *wnet_vif, int flags) +{ + /* if roaming find node to connect ,don't scan*/ + if (wnet_vif->vm_connect_scan_entry.se_valid) { @@ -104305,8 +105936,15 @@ index 000000000000..e53232e88420 + } + + if (wifi_mac_scan_get_match_node(ss, wnet_vif) == 0) { -+ printk("%s not found bss in former scan results\n", __func__); -+ ++ if (wnet_vif->vm_des_channel != NULL) { ++ wnet_vif->vm_scan_before_connect_flag = 1; ++ wnet_vif->vm_connchan.conn_chan[wnet_vif->vm_connchan.num++] = wnet_vif->vm_des_channel; ++ WIFINET_ADDR_COPY(wnet_vif->vm_connchan.da, wnet_vif->vm_des_bssid); ++ WIFINET_ADDR_COPY(wnet_vif->vm_connchan.bssid, wnet_vif->vm_des_bssid); ++ AML_OUTPUT("add connet scan, chan_pri_num:%d, count:%d \n",wnet_vif->vm_des_channel->chan_pri_num, wnet_vif->vm_connchan.num); ++ } else { ++ AML_OUTPUT("no connect bss in former scan list, vm_des_channel is null\n"); ++ } + } else { + wnet_vif->vm_scan_before_connect_flag = 1; + } @@ -104357,7 +105995,7 @@ index 000000000000..e53232e88420 + wifimac->wm_flags |= WIFINET_F_SCAN; + + if (wnet_vif->vm_opmode == WIFINET_M_STA) { -+ printk("%s vm_scanchan_rssi:%d \n", __func__, wnet_vif->vm_scanchan_rssi); ++ pr_debug("%s vm_scanchan_rssi:%d \n", __func__, wnet_vif->vm_scanchan_rssi); + if (wnet_vif->vm_scan_before_connect_flag) { + if (wnet_vif->vm_scanchan_rssi > MAC_MIN_GAIN) { + wnet_vif->vm_scanchan_rssi = MAC_MIN_GAIN; @@ -104384,7 +106022,7 @@ index 000000000000..e53232e88420 + + ss->VMacPriv = wnet_vif; + -+ printk("%s vid:%d---> scan start, CfgFlags is:%08x, ss->ss_nssid:%d\n", __func__, wnet_vif->wnet_vif_id, ss->scan_CfgFlags, ss->ss_nssid); ++ pr_debug("%s vid:%d---> scan start, CfgFlags is:%08x, ss->ss_nssid:%d\n", __func__, wnet_vif->wnet_vif_id, ss->scan_CfgFlags, ss->ss_nssid); + wifimac->wm_scanplayercnt++; + wifi_mac_add_work_task(wifimac, scan_start_task, NULL, (SYS_TYPE)ss, 0, (SYS_TYPE)wifimac->wm_scanplayercnt, + (SYS_TYPE)wnet_vif, (SYS_TYPE)wnet_vif->wnet_vif_replaycounter); @@ -104403,13 +106041,23 @@ index 000000000000..e53232e88420 + AML_OUTPUT("vid:%d, wm_flags:0x%08x, scan_CfgFlags:0x%08x, ss_flag:0x%08x, next_chn:%d, last_chn:%d\n", + wnet_vif->wnet_vif_id, wifimac->wm_flags, ss->scan_CfgFlags, ss->scan_StateFlags, + ss->scan_next_chan_index, ss->scan_last_chan_index); -+ ss->scan_StateFlags |= SCANSTATE_F_CANCEL; -+ wifi_mac_scan_timeout((SYS_TYPE)wifimac->wm_scan, (SYS_TYPE)ss->VMacPriv, 0, 0, (SYS_TYPE)wifimac->wm_scanplayercnt); -+ ss->scan_StateFlags = 0; ++ return 0; ++ } ++ ++ if (wnet_vif->vm_opmode == WIFINET_M_STA) { ++ if (wnet_vif->vm_des_nssid == 0) { ++ ERROR_DEBUG_OUT("scan not trigger as vm_des_bssid is empty\n"); ++ return 0; ++ } ++ ++ if ((wnet_vif->vm_mainsta != NULL) && (wnet_vif->vm_mainsta->connect_status != CONNECT_CONNECTING)) { ++ ERROR_DEBUG_OUT("scan not trigger as connect_status:%d\n", wnet_vif->vm_mainsta->connect_status); ++ return 0; ++ } + } + + ss->scan_CfgFlags |= WIFINET_SCANCFG_CONNECT; -+ printk("%s flags:%08x\n", __func__, flags); ++ pr_debug("%s flags:%08x\n", __func__, flags); + return wifi_mac_start_scan(wnet_vif, flags, nssid, ssids); +} + @@ -104437,7 +106085,7 @@ index 000000000000..e53232e88420 + { + os_timer_ex_cancel(&ss->ss_scan_timer, CANCEL_SLEEP); + wifimac->wm_flags &= ~WIFINET_F_SCAN; -+ printk("%s(%d):-->clean vm_flags 0x%x\n", __func__, __LINE__, wifimac->wm_flags); ++ pr_debug("%s(%d):-->clean vm_flags 0x%x\n", __func__, __LINE__, wifimac->wm_flags); + } + wifi_mac_scan_flush(wifimac); + } @@ -104453,7 +106101,7 @@ index 000000000000..e53232e88420 + wifimac->roaming_threshold_2g = DEFAULT_ROAMING_THRESHOLD_2G; + wifimac->roaming_threshold_5g = DEFAULT_ROAMING_THRESHOLD_5G; + -+ printk("wifi_mac_scan_timeout is %p\n", wifi_mac_scan_timeout); ++ pr_debug("wifi_mac_scan_timeout is %p\n", wifi_mac_scan_timeout); + ss = (struct wifi_mac_scan_state *)NET_MALLOC(sizeof(struct wifi_mac_scan_state), + GFP_KERNEL, "wifi_mac_scan_attach.ss"); + if (ss != NULL) @@ -104518,7 +106166,7 @@ index 000000000000..e53232e88420 + } + + wifimac->wm_flags &= ~WIFINET_F_SCAN; -+ printk("%s(%d):-->clean vm_flags 0x%x\n", __func__, __LINE__, wifimac->wm_flags); ++ pr_debug("%s(%d):-->clean vm_flags 0x%x\n", __func__, __LINE__, wifimac->wm_flags); + + FREE(wifimac->wm_scan,"wifi_mac_scan_attach.ss"); + wifimac->wm_scan = NULL; @@ -104576,12 +106224,43 @@ index 000000000000..e53232e88420 + AML_OUTPUT("simulate scan end\n"); + } +} ++ ++struct wifi_channel* ++wifi_mac_connect_get_target_chan(struct wifi_mac_scan_state *ss, struct wlan_net_vif *wnet_vif) ++{ ++ struct scaninfo_table *st = ss->ScanTablePriv; ++ struct scaninfo_entry *se = NULL; ++ struct scaninfo_entry *se_next = NULL; ++ struct wifi_channel* target_chan = NULL; ++ ++ WIFI_SCAN_SE_LIST_LOCK(st); ++ list_for_each_entry_safe(se, se_next, &st->st_entry, se_list) ++ { ++ DPRINTF(AML_DEBUG_CONNECT, "se:0x%p, st_entry:0x%p\n", se, &st->st_entry); ++ ++ if (WIFINET_ADDR_EQ(wnet_vif->vm_des_bssid, se->scaninfo.SI_bssid) ++ && match_ssid(se->scaninfo.SI_ssid, 1, wnet_vif->vm_des_ssid)) ++ { ++ target_chan = se->scaninfo.SI_chan; ++ ++ if (target_chan != NULL) { ++ AML_OUTPUT("pri_chan_num:%d, center_chan_num:%d, bw:%d",target_chan->chan_pri_num, ++ wifi_mac_Mhz2ieee(target_chan->chan_cfreq1, 0), target_chan->chan_bw); ++ WIFI_SCAN_SE_LIST_UNLOCK(st); ++ return target_chan; ++ } ++ } ++ } ++ WIFI_SCAN_SE_LIST_UNLOCK(st); ++ ++ return target_chan; ++} diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_scan.h b/drivers/net/wireless/w1/vmac/wifi_mac_scan.h new file mode 100644 -index 000000000000..9c76ba2f7765 +index 0000000000000000000000000000000000000000..ac893c46919f9477169fb1d4b4cfbf28fc887e2b --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_scan.h -@@ -0,0 +1,304 @@ +@@ -0,0 +1,305 @@ +/* + **************************************************************************************** + * @@ -104749,6 +106428,7 @@ index 000000000000..9c76ba2f7765 + unsigned char *vht_ext_bss_ld; + unsigned char *vht_quiet_ch; + unsigned char *vht_opt_md_ntf; ++ unsigned int frame_len; +}; + +#define SCANINFO_IE_LENGTH 260 @@ -104803,6 +106483,7 @@ index 000000000000..9c76ba2f7765 + unsigned char ie_vht_ext_bss_ld[sizeof(struct wifi_mac_ie_vht_ext_bss_ld)]; + unsigned char ie_vht_quiet_ch[sizeof(struct wifi_mac_ie_vht_quiet_chn)]; + unsigned char ie_vht_opt_md_ntf[sizeof(struct wifi_mac_ie_vht_opt_md_ntf)]; ++ unsigned int SI_frame_len; +}; + +#define WIFINET_SCAN_AGE_NUM 3 @@ -104883,15 +106564,14 @@ index 000000000000..9c76ba2f7765 +int wifi_mac_scan_chk_11g_bss(struct wifi_mac_scan_state *ss, struct wlan_net_vif *wnet_vif); +void is_connect_need_set_gain(struct wlan_net_vif *wnet_vif); +void wifi_mac_scan_chking_leakap(void * station, struct wifi_frame *wh); -+ -+ ++struct wifi_channel* wifi_mac_connect_get_target_chan(struct wifi_mac_scan_state *ss, struct wlan_net_vif *wnet_vif); +#endif /* _WIFI_NET_SCAN_H_ */ diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_sta.c b/drivers/net/wireless/w1/vmac/wifi_mac_sta.c new file mode 100644 -index 000000000000..a603026f0e19 +index 0000000000000000000000000000000000000000..9b93e5a2b4ba51c2c0f04cdadd590ccbc193a70e --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_sta.c -@@ -0,0 +1,2330 @@ +@@ -0,0 +1,2460 @@ +/* + **************************************************************************************** + * @@ -104909,6 +106589,7 @@ index 000000000000..a603026f0e19 +#include "wifi_mac_com.h" +#include +#include ++#include "wifi_mac_rate.h" + +void wifi_mac_station_init(struct wlan_net_vif *wnet_vif) +{ @@ -104982,6 +106663,7 @@ index 000000000000..a603026f0e19 + struct wifi_station *obss; + int canreassoc, cnt = 0; + struct hal_private * hal_priv = hal_get_priv(); ++ struct wlan_net_vif *p2p_vmac = wifimac->drv_priv->drv_wnet_vif_table[NET80211_P2P_VMAC]; + + WIFINET_VMACS_LOCK(wifimac); + @@ -105010,9 +106692,10 @@ index 000000000000..a603026f0e19 + memcpy(wnet_vif->vm_mainsta->sta_txseqs, obss->sta_txseqs, sizeof(obss->sta_txseqs)); + } + ++ wnet_vif->vm_mainsta->connect_status = obss->connect_status; + wifi_mac_rm_sta_from_wds_by_sta(&wnet_vif->vm_sta_tbl, obss); + -+ printk("%s, obss:%p\n", __func__, obss); ++ pr_debug("%s, obss:%p\n", __func__, obss); + WIFINET_VMACS_UNLOCK(wifimac); + wifi_mac_free_sta_from_list(obss); + WIFINET_VMACS_LOCK(wifimac); @@ -105031,7 +106714,15 @@ index 000000000000..a603026f0e19 + } + DPRINTF(AML_DEBUG_CONNECT,"%s bhalPowerSave %d, cnt %d\n",__func__, hal_priv->bhalPowerSave, cnt); + -+ wifi_mac_ChangeChannel(wifimac, wnet_vif->vm_curchan, 3, wnet_vif->wnet_vif_id, wnet_vif->vm_opmode); ++ if (IS_APSTA_CONCURRENT(aml_wifi_get_con_mode()) ++ && concurrent_check_vmac_is_AP(wifimac) ++ && (wnet_vif->vm_opmode == WIFINET_M_STA) ++ && (p2p_vmac->vm_state == WIFINET_S_CONNECTED) ++ && concurrent_check_is_vmac_same_pri_channel(wifimac)) { ++ wifi_mac_ChangeChannel(wifimac, wnet_vif->vm_curchan, 3, wnet_vif->wnet_vif_id, p2p_vmac->vm_opmode); ++ } else { ++ wifi_mac_ChangeChannel(wifimac, wnet_vif->vm_curchan, 3, wnet_vif->wnet_vif_id, wnet_vif->vm_opmode); ++ } + + is_connect_need_set_gain(wnet_vif); + if (wnet_vif->vm_opmode == WIFINET_M_STA) { @@ -105129,7 +106820,7 @@ index 000000000000..a603026f0e19 + is_forbidden = 0; + } + } -+ //printk("chris wpa count:%d, id:%02x, len:%02x, version:%04x\n", count, ap_wpa_ie->wpa_id, ap_wpa_ie->wpa_len, ap_wpa_ie->wpa_version); ++ //pr_debug("chris wpa count:%d, id:%02x, len:%02x, version:%04x\n", count, ap_wpa_ie->wpa_id, ap_wpa_ie->wpa_len, ap_wpa_ie->wpa_version); + } + + if (ap_rsn_ie != NULL) { @@ -105143,7 +106834,7 @@ index 000000000000..a603026f0e19 + is_forbidden = 0; + } + } -+ //printk("chris rsn count:%d, id:%02x, len:%02x, version:%02x\n", count, ap_rsn_ie->rsn_id, ap_rsn_ie->rsn_len, ap_rsn_ie->rsn_version); ++ //pr_debug("chris rsn count:%d, id:%02x, len:%02x, version:%02x\n", count, ap_rsn_ie->rsn_id, ap_rsn_ie->rsn_len, ap_rsn_ie->rsn_version); + } + + if ((ap_wpa_ie == NULL) && (ap_rsn_ie == NULL)) { @@ -105172,6 +106863,7 @@ index 000000000000..a603026f0e19 + } + + AML_OUTPUT("%s sta:%p\n",__func__, sta); ++#if 0 + if (IS_APSTA_CONCURRENT(aml_wifi_get_con_mode())) { + struct drv_private *drv_priv = wifimac->drv_priv; + struct wlan_net_vif *p2p_wnet_vif = drv_priv->drv_wnet_vif_table[NET80211_P2P_VMAC]; @@ -105186,13 +106878,13 @@ index 000000000000..a603026f0e19 + p2p_wnet_vif->vm_wmac->wm_doth_tbtt = 10; + } + } -+ ++#endif + wifi_mac_connect_start(wifimac); + + if(aml_wifi_get_platform_verid() == 2) { -+ /*this is for gva_mrt version, fix 2.4G on 20M bandwith*/ ++ /*this is for gva_mrt version, fix 2.4G on 20M bandwidth*/ + if (WIFINET_IS_CHAN_2GHZ(se->SI_chan)) { -+ printk("%s %d set bw 20M\n", __func__, __LINE__); ++ pr_debug("%s %d set bw 20M\n", __func__, __LINE__); + work_channel = wifi_mac_find_chan(wifimac, se->SI_chan->chan_pri_num, + WIFINET_BWC_WIDTH20, se->SI_chan->chan_pri_num); + } else { @@ -105214,9 +106906,9 @@ index 000000000000..a603026f0e19 + + /*then, sta != vm_mainsta */ + if(aml_wifi_get_platform_verid() == 2) { -+ /*this is for gva_mrt version, fix 2.4G on 20M bandwith*/ ++ /*this is for gva_mrt version, fix 2.4G on 20M bandwidth*/ + if (WIFINET_IS_CHAN_2GHZ(se->SI_chan)) { -+ printk("%s %d set bw 20M\n", __func__, __LINE__); ++ pr_debug("%s %d set bw 20M\n", __func__, __LINE__); + sta->sta_chbw = WIFINET_BWC_WIDTH20; + } else { + sta->sta_chbw = se->SI_chan->chan_bw; @@ -105240,10 +106932,12 @@ index 000000000000..a603026f0e19 + +#ifdef AML_WPA3 + if (wnet_vif->vm_mainsta->sta_flags_ext & WIFINET_NODE_MFP) { -+ printk("ap pmf:%04x, before set rsn_caps:%04x ", se->si_rsn_capa, wnet_vif->vm_opt_ie[sta->sta_rsn.rsn_caps_offset]); -+ wnet_vif->vm_opt_ie[sta->sta_rsn.rsn_caps_offset] |= (unsigned char)(se->si_rsn_capa & 0xc0); ++ if (!wifimac->wm_wfa_enable) { ++ pr_debug("ap pmf:%04x, before set rsn_caps:%04x ", se->si_rsn_capa, wnet_vif->vm_opt_ie[sta->sta_rsn.rsn_caps_offset]); ++ wnet_vif->vm_opt_ie[sta->sta_rsn.rsn_caps_offset] |= (unsigned char)(se->si_rsn_capa & 0xc0); ++ pr_debug("after set rsn_caps:%04x\n", wnet_vif->vm_opt_ie[sta->sta_rsn.rsn_caps_offset]); ++ } + -+ printk("after set rsn_caps:%04x\n", wnet_vif->vm_opt_ie[sta->sta_rsn.rsn_caps_offset]); + if ((se->si_rsn_capa & 0xc0) != 0) { + sta->sta_flags_ext = (wnet_vif->vm_mainsta->sta_flags_ext & WIFINET_NODE_MFP); + if (sta->sta_flags_ext & WIFINET_NODE_MFP) { @@ -105306,6 +107000,13 @@ index 000000000000..a603026f0e19 + { + wifi_mac_saveie(&sta->sta_wps_ie, se->SI_wps_ie, "sta->sta_wps_ie"); + } ++ if (se->SI_rsnx_ie[1] != 0 && (sta->sta_use_h2e == WIFINET_H2E_NONE)) ++ { ++ if ((se->SI_rsnx_ie[2] & BIT(5))) { ++ sta->sta_use_h2e = WIFINET_H2E_PEER_SUPPOR; ++ AML_OUTPUT("connect ap support H2E\n"); ++ } ++ } + + wifi_mac_reset_vmac(wnet_vif); + wnet_vif->vm_bcn_intval = se->SI_intval; @@ -105320,7 +107021,7 @@ index 000000000000..a603026f0e19 + else + wifimac->wm_11dinfo = NULL; + -+ printk("%s start connect to ssid:%s, pri_channel:%d, center_chan:%d, bw:%d, BSSID:%02x:%02x:%02x:%02x:%02x:%02x, mode:%d\n", ++ pr_debug("%s start connect to ssid:%s, pri_channel:%d, center_chan:%d, bw:%d, BSSID:%02x:%02x:%02x:%02x:%02x:%02x, mode:%d\n", + __func__, se->SI_ssid+2, se->SI_chan->chan_pri_num, se->SI_chan->chan_cfreq1, se->SI_chan->chan_bw, sta->sta_bssid[0], + sta->sta_bssid[1], sta->sta_bssid[2], sta->sta_bssid[3], sta->sta_bssid[4], sta->sta_bssid[5], sta->sta_bssmode); + wnet_vif->vm_phase_flags |= PHASE_CONNECTING; @@ -105364,7 +107065,7 @@ index 000000000000..a603026f0e19 + wnet_vif->vm_curchan = work_channel; + sta->sta_chbw = chan->chan_bw; + -+ printk("%s(%d): pri_chan %d, bw %d, chan_cfreq1 %d\n", __func__, __LINE__, ++ pr_debug("%s(%d): pri_chan %d, bw %d, chan_cfreq1 %d\n", __func__, __LINE__, + chan->chan_pri_num, chan->chan_bw, wifi_mac_Mhz2ieee(chan->chan_cfreq1, 0)); + + WIFINET_ADDR_COPY(sta->sta_bssid, wnet_vif->vm_myaddr); @@ -105408,7 +107109,7 @@ index 000000000000..a603026f0e19 + } + wifi_mac_build_country_ie(wnet_vif); + wifi_mac_start_bss(sta); -+ printk("<%s> L:%d, mac mode %d dot11_rate_num %d\n", ++ pr_debug("<%s> L:%d, mac mode %d dot11_rate_num %d\n", + __func__,__LINE__,sta->sta_bssmode,sta->sta_htrates.dot11_rate_num); +} + @@ -105437,11 +107138,12 @@ index 000000000000..a603026f0e19 + } + + sta->sta_flags &= ~WIFINET_NODE_AREF; ++ os_timer_ex_del(&sta->csa_timer, CANCEL_SLEEP); + + if (wifi_mac_pwrsave_psqueue_clean(sta) != 0 && wnet_vif->vif_ops.vm_set_tim != NULL) + wnet_vif->vif_ops.vm_set_tim(sta, 0); + -+ printk("----------%d assoc id \n",sta->sta_associd); ++ pr_debug("----------%d assoc id \n",sta->sta_associd); + if (sta->sta_challenge != NULL) + { + FREE(sta->sta_challenge,"sta->sta_challenge"); @@ -105489,9 +107191,10 @@ index 000000000000..a603026f0e19 + wnet_vif->vm_change_rate_enable = 1; + wnet_vif->vm_scanchan_rssi = MAC_MIN_GAIN; + -+ printk("wifi_mac_sta_leave:%d, sta:%p, main_sta:%p\n", wnet_vif->wnet_vif_id, sta, wnet_vif->vm_mainsta); ++ pr_debug("wifi_mac_sta_leave:%d, sta:%p, main_sta:%p\n", wnet_vif->wnet_vif_id, sta, wnet_vif->vm_mainsta); + if (wnet_vif->vm_opmode == WIFINET_M_STA) + { ++ sta->is_disconnecting = 1; + wifimac->drv_priv->drv_ops.drv_set_pkt_drop(wifimac->drv_priv, wnet_vif->wnet_vif_id, 1); + wnet_vif->vm_curchan = WIFINET_CHAN_ERR; + if (wnet_vif->vm_flags_ext & WIFINET_FEXT_SWBMISS) { @@ -105531,11 +107234,13 @@ index 000000000000..a603026f0e19 + wifimac->is_connect_set_gain = 1; + wifimac->drv_priv->drv_ops.set_channel_rssi(wifimac->drv_priv, 174); + ++ os_timer_ex_start_period(&wifimac->wm_csa_trigger_timer, 10000); ++ + if (wifimac->recovery_stat == WIFINET_RECOVERY_END) { + wnet_vif->vm_des_nssid = 0; + memset(wnet_vif->vm_des_ssid, 0, IV_SSID_SCAN_AMOUNT*sizeof(struct wifi_mac_ScanSSID)); + } -+ ++ sta->is_disconnecting = 0; + } + wnet_vif->vm_phase_flags &= ~PHASE_DISCONNECTING; + @@ -105569,20 +107274,26 @@ index 000000000000..a603026f0e19 +nsta_free(struct wifi_station *sta) +{ + int index = 0; ++ struct sk_buff *skb = NULL, *tmp = NULL; + struct wlan_net_vif *wnet_vif = NULL; ++ struct sk_buff_head *txqueue = NULL; ++ struct wifi_station *txqueue_sta = NULL; ++ + ASSERT(sta); + + if (sta) { + wnet_vif = sta->sta_wnet_vif; + -+ if (sta == wnet_vif->vm_mainsta) { -+ printk("free vm_mainsta:%p\n", sta); ++ if (wnet_vif && sta == wnet_vif->vm_mainsta) { ++ pr_debug("free vm_mainsta:%p\n", sta); + wnet_vif->vm_mainsta = NULL; + } + } else { + return ; + } + ++ wifi_mac_rate_disassoc(sta); ++ + wifi_mac_sta_free(sta); + if (sta->sta_wpa_ie != NULL) + FREE(sta->sta_wpa_ie,"sta->sta_wpa_ie"); @@ -105614,8 +107325,21 @@ index 000000000000..a603026f0e19 + FREE(sta->sta_wai_ie,"sta->sta_wai_ie"); +#endif /*CONFIG_WAPI*/ + ++ txqueue = &wnet_vif->vm_tx_buffer_queue; ++ WIFINET_SAVEQ_LOCK(txqueue); ++ skb_queue_walk_safe(txqueue,skb,tmp) { ++ txqueue_sta = os_skb_get_nsta(skb); ++ if (txqueue_sta == sta) { ++ AML_OUTPUT("as free sta: %p so free skb\n",txqueue_sta); ++ aml_skb_unlink(skb,txqueue); ++ wifi_mac_free_skb(skb); ++ ++ } ++ } ++ WIFINET_SAVEQ_UNLOCK(txqueue); ++ + WIFINET_SAVEQ_DESTROY(&(sta->sta_pstxqueue)); -+ printk("%s free %p\n", __func__, sta); ++ pr_debug("%s free %p\n", __func__, sta); + FREE(sta,"alloc_sta_node.sta"); +} + @@ -105649,7 +107373,7 @@ index 000000000000..a603026f0e19 + } + + wifi_mac_alloc_amsdu_node(wifimac, wnet_vif->wnet_vif_id, sta); -+ printk("%s vid:%d, sta:%p\n", __func__, wnet_vif->wnet_vif_id, sta); ++ pr_debug("%s vid:%d, sta:%p\n", __func__, wnet_vif->wnet_vif_id, sta); + return sta; +} + @@ -105669,9 +107393,10 @@ index 000000000000..a603026f0e19 + return NULL; + } + sta->sta_tmp_nsta = 0; ++ os_timer_ex_initialize(&sta->csa_timer, 0, wifi_mac_csa_handle_timeout, sta); + + WIFINET_ADDR_COPY(sta->sta_macaddr, macaddr); -+ //dump_memory_internel(macaddr, 6); ++ //dump_memory_internal(macaddr, 6); + hash = WIFINET_NODE_HASH(macaddr); + sta->sta_authmode = WIFINET_AUTH_OPEN; + sta->sta_txpower = wifimac->wm_txpowlimit; @@ -105843,7 +107568,7 @@ index 000000000000..a603026f0e19 +{ + struct wifi_station *sta; + -+ printk("%s\n", __func__); ++ pr_debug("%s\n", __func__); + + sta = alloc_sta_node(NULL ,wnet_vif); + if (sta != NULL) { @@ -105926,11 +107651,11 @@ index 000000000000..a603026f0e19 + const unsigned char *macaddr) +{ + struct wifi_station *sta; -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + sta = wifi_mac_bup_bss(wnet_vif, macaddr); + if (sta != NULL) + { -+ printk(" %s %d NI_RATE....................\n",__func__,__LINE__); ++ pr_debug(" %s %d NI_RATE....................\n",__func__,__LINE__); + sta->sta_rates = wnet_vif->vm_mainsta->sta_rates; + wifi_mac_new_assoc(sta, 1); + wifi_mac_sta_auth(sta); @@ -105976,12 +107701,14 @@ index 000000000000..a603026f0e19 + } + else if (vhtop->vht_op_chwidth > VHT_OPT_CHN_WD_80M) + { -+ printk("%s:%d, not support bandwidth %d yet \n", __func__, __LINE__, vhtop->vht_op_chwidth); ++ pr_debug("%s:%d, not support bandwidth %d yet \n", __func__, __LINE__, vhtop->vht_op_chwidth); + } + } + -+ if (wifi_mac_set_wnet_vif_channel(wnet_vif, sp->chan, bw, center_chan) == false) ++ if (wifi_mac_set_wnet_vif_channel(wnet_vif, sp->chan, bw, center_chan, CHANNEL_CONNECT_FLAG | CHANNEL_RESTORE_FLAG) == false) ++ { + return NULL; ++ } + + sta = wifi_mac_bup_bss(wnet_vif, wh->i_addr2); + if (sta != NULL) @@ -106176,6 +107903,11 @@ index 000000000000..a603026f0e19 + WIFINET_NODE_FREE_UNLOCK(wifimac); + + sta = del_nsta->nsta; ++ /* Clear 'sta_wnet_vif', since this function is called ++ * only during driver unload and both interfaces are ++ * released, so we can't touch them in 'nsta_free()'. ++ */ ++ sta->sta_wnet_vif = NULL; + nsta_free(sta); + FREE(del_nsta,"del_nsta"); + @@ -106223,10 +107955,10 @@ index 000000000000..a603026f0e19 + } + WIFINET_NODE_FREE_UNLOCK(wifimac); + -+ printk("%s sta:%p, new:%d\n", __func__, sta, new_delete); ++ pr_debug("%s sta:%p, new:%d\n", __func__, sta, new_delete); + if (new_delete) { + if (sta == wnet_vif->vm_mainsta) { -+ printk("free vm_mainsta:%p\n", sta); ++ pr_debug("free vm_mainsta:%p\n", sta); + wnet_vif->vm_mainsta = NULL; + } + @@ -106249,7 +107981,8 @@ index 000000000000..a603026f0e19 + wifi_mac_free_sta(sta); +} + -+static void wifi_mac_sta_table_rst(struct wifi_station_tbl *nt, struct wlan_net_vif *match) ++static void wifi_mac_sta_table_rst(struct wifi_station_tbl *nt, struct wlan_net_vif *match, ++ bool rst_mainsta) +{ + struct wifi_station *sta = NULL, *next = NULL; + @@ -106260,11 +107993,11 @@ index 000000000000..a603026f0e19 + if ((match != NULL) && (wnet_vif != match)) + continue; + -+ if (sta->sta_associd != 0) { ++ if ((wnet_vif->vm_opmode == WIFINET_M_HOSTAP) && (sta->sta_associd != 0)) { + vm_StaClearAid(wnet_vif, sta->sta_associd); + } + -+ if (sta != wnet_vif->vm_mainsta) { ++ if (sta != wnet_vif->vm_mainsta || rst_mainsta) { + wifi_mac_rm_sta_from_wds_by_addr(nt,sta->sta_macaddr); + list_del_init(&sta->sta_list); + @@ -106282,7 +108015,7 @@ index 000000000000..a603026f0e19 + + WIFINET_NODE_LOCK(nt); + list_for_each_entry_safe(sta, next, &nt->nt_nsta, sta_list) { -+ if (sta->sta_associd != 0) { ++ if ((sta->sta_wnet_vif->vm_opmode == WIFINET_M_HOSTAP) && (sta->sta_associd != 0)) { + vm_StaClearAid(sta->sta_wnet_vif, sta->sta_associd); + } + @@ -106302,7 +108035,7 @@ index 000000000000..a603026f0e19 + struct wifi_station *sta = NULL; + struct wifi_station *next = NULL; + -+ printk("station list==========>: \n"); ++ pr_debug("station list==========>: \n"); + WIFINET_NODE_LOCK(nt); + list_for_each_entry_safe(sta, next, &nt->nt_nsta, sta_list) { + if (wnet_vif != sta->sta_wnet_vif) { @@ -106310,13 +108043,13 @@ index 000000000000..a603026f0e19 + } + + if(sta->sta_associd != 0) { -+ printk("station staid %d, ",sta->sta_associd&0xff); -+ printk("mac addr %s \n",ether_sprintf(sta->sta_macaddr)); ++ pr_debug("station staid %d, ",sta->sta_associd&0xff); ++ pr_debug("mac addr %s \n",ether_sprintf(sta->sta_macaddr)); + wifi_mac_dump_sta(nt,sta); + } + } + WIFINET_NODE_UNLOCK(nt); -+ printk("=========end================\n"); ++ pr_debug("=========end================\n"); +} + +static void wifi_mac_TimeoutStations(struct wifi_station_tbl *nt) @@ -106596,7 +108329,7 @@ index 000000000000..a603026f0e19 + + if ((sta->sta_wnet_vif == wnet_vif) && (sta->sta_associd != 0)) { + wifi_mac_send_mgmt(sta, WIFINET_FC0_SUBTYPE_DISASSOC, (void *)&mgmt_arg); -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + + wifi_mac_sta_disconnect(sta); + wifi_mac_rm_sta_from_wds_by_addr(nt, sta->sta_macaddr); @@ -106612,11 +108345,52 @@ index 000000000000..a603026f0e19 + + if (sta->sta_wnet_vif == wnet_vif) + { -+ printk(" %s %d \n",__func__,__LINE__); ++ pr_debug(" %s %d \n",__func__,__LINE__); + wifi_mac_send_mgmt(sta, WIFINET_FC0_SUBTYPE_DEAUTH, (void *)&mgmt_arg); + } +} + ++static void wifi_mac_disassoc_cb(SYS_TYPE param1, SYS_TYPE param2, SYS_TYPE param3, ++ SYS_TYPE param4, SYS_TYPE param5) ++{ ++ struct wlan_net_vif *wnet_vif = (struct wlan_net_vif *)param1; ++ struct wifi_station *sta = (struct wifi_station *)param2; ++ struct wifi_station_tbl *nt = &(wnet_vif->vm_sta_tbl); ++ int mgmt_arg = WIFINET_REASON_ASSOC_LEAVE; ++ ++ wifi_mac_send_mgmt(sta, WIFINET_FC0_SUBTYPE_DISASSOC, (void *)&mgmt_arg); ++ pr_debug(" %s %d \n",__func__,__LINE__); ++ ++ wifi_mac_sta_disconnect(sta); ++ wifi_mac_rm_sta_from_wds_by_addr(nt, sta->sta_macaddr); ++ ++ wifi_mac_free_sta(sta); ++} ++ ++void wifi_mac_sta_disassoc_in_task(struct wlan_net_vif *wnet_vif) ++{ ++ struct wifi_station *sta = NULL, *sta_next = NULL; ++ struct wifi_station_tbl *nt = &(wnet_vif->vm_sta_tbl); ++ ++ WIFINET_NODE_LOCK(nt); ++ ++ list_for_each_entry_safe(sta, sta_next, &nt->nt_nsta, sta_list) { ++ if ((sta->sta_wnet_vif == wnet_vif) && sta->sta_associd) { ++ /* Remove 'sta' with lock from global list here. So ++ * nobody can access it later. 'wifi_mac_disassoc_cb()' ++ * will free it later. ++ */ ++ list_del_init(&sta->sta_list); ++ ++ wifi_mac_add_work_task(nt->nt_wmac, wifi_mac_disassoc_cb, NULL, ++ (SYS_TYPE)wnet_vif, (SYS_TYPE)sta, NULL, ++ NULL, NULL); ++ } ++ } ++ ++ WIFINET_NODE_UNLOCK(nt); ++} ++ +void wifi_mac_func_to_task(struct wifi_station_tbl *nt, wifi_mac_IterFunc *f, void *arg,unsigned char btask) +{ + struct wifi_station *sta = NULL, *sta_next = NULL; @@ -106814,11 +108588,11 @@ index 000000000000..a603026f0e19 + { + if (wnet_vif->vm_p2p->p2p_flag & P2P_OPPPS_START_FLAG_HI) + { -+ vm_p2p_go_cancle_opps(wnet_vif->vm_p2p); ++ vm_p2p_go_cancel_opps(wnet_vif->vm_p2p); + } + if (wnet_vif->vm_p2p->p2p_flag & P2P_NOA_START_FLAG_HI) + { -+ vm_p2p_go_cancle_noa(wnet_vif->vm_p2p); ++ vm_p2p_go_cancel_noa(wnet_vif->vm_p2p); + } + } +#endif @@ -106884,7 +108658,7 @@ index 000000000000..a603026f0e19 + wnet_vif->vm_curchan->chan_pri_num, sta->sta_chbw, sta->sta_essid, + sta->sta_macaddr[0], sta->sta_macaddr[1], sta->sta_macaddr[2], + sta->sta_macaddr[3], sta->sta_macaddr[4], sta->sta_macaddr[5]); -+ printk("****************************************************\n"); ++ pr_debug("****************************************************\n"); +} + +void @@ -106953,16 +108727,16 @@ index 000000000000..a603026f0e19 +{ + struct wifi_mac *wifimac = wnet_vif->vm_wmac; + -+ printk("%s, wnet_vif->wnet_vif_id= %d\n", __func__, wnet_vif->wnet_vif_id); ++ pr_debug("%s, wnet_vif->wnet_vif_id= %d\n", __func__, wnet_vif->wnet_vif_id); + -+ wifi_mac_sta_table_rst(&wnet_vif->vm_sta_tbl, wnet_vif); ++ wifi_mac_sta_table_rst(&wnet_vif->vm_sta_tbl, wnet_vif, false); + wifi_mac_reset_erp(wifimac, wnet_vif->vm_mac_mode); + wifi_mac_reset_ht(wifimac); + + if (!wnet_vif->vm_mainsta) { + wnet_vif->vm_mainsta = wifi_mac_get_sta_node(&wnet_vif->vm_sta_tbl, wnet_vif, wnet_vif->vm_myaddr); + KASSERT(wnet_vif->vm_mainsta != NULL, ("unable to create vm_mainsta")); -+ printk("%s add vm_mainsta:%p\n", __func__, wnet_vif->vm_mainsta); ++ pr_debug("%s add vm_mainsta:%p\n", __func__, wnet_vif->vm_mainsta); + } + + wnet_vif->vm_ps_sta = 0; @@ -106972,7 +108746,7 @@ index 000000000000..a603026f0e19 +{ + struct wifi_station *sta = wnet_vif->vm_mainsta; + -+ printk("%s, wnet_vif_id= %d, main_sta:%p\n", __func__, wnet_vif->wnet_vif_id, sta); ++ pr_debug("%s, wnet_vif_id= %d, main_sta:%p\n", __func__, wnet_vif->wnet_vif_id, sta); + + if (sta) { + sta->sta_associd = 0; @@ -107013,8 +108787,8 @@ index 000000000000..a603026f0e19 + +void wifi_mac_sta_vdetach(struct wlan_net_vif *wnet_vif) +{ -+ printk("%s, vm_mainsta:%p\n", __func__, wnet_vif->vm_mainsta); -+ wifi_mac_sta_table_rst(&wnet_vif->vm_sta_tbl, wnet_vif); ++ pr_debug("%s, vm_mainsta:%p\n", __func__, wnet_vif->vm_mainsta); ++ wifi_mac_sta_table_rst(&wnet_vif->vm_sta_tbl, wnet_vif, true); +} + +void wifi_mac_sta_attach(struct wifi_mac *wifimac) @@ -107134,8 +108908,34 @@ index 000000000000..a603026f0e19 + +void wifi_mac_notify_scan_done(struct wlan_net_vif *wnet_vif) +{ -+ vm_cfg80211_inform_bss(wnet_vif); -+ vm_cfg80211_indicate_scan_done(wdev_to_priv(wnet_vif->vm_wdev), false); ++ bool scan_abort = true; ++ struct wifi_mac* wifimac = NULL; ++ struct wifi_mac_scan_state *scan_state = NULL; ++ ++ if (wnet_vif == NULL) { ++ ERROR_DEBUG_OUT("wnet_vif is null !\n"); ++ return; ++ } ++ ++ if (wnet_vif->vm_wmac == NULL) { ++ ERROR_DEBUG_OUT("wifimac is null !\n"); ++ return; ++ } ++ ++ if (wnet_vif->vm_wmac->wm_scan == NULL) { ++ ERROR_DEBUG_OUT("wm_scan is null !\n"); ++ return; ++ } ++ ++ wifimac = wnet_vif->vm_wmac; ++ scan_state = wifimac->wm_scan; ++ ++ if (!(scan_state->scan_StateFlags & SCANSTATE_F_CANCEL)) { ++ scan_abort = false; ++ vm_cfg80211_inform_bss(wnet_vif); ++ } ++ ++ vm_cfg80211_indicate_scan_done(wdev_to_priv(wnet_vif->vm_wdev), scan_abort); +} + +void wifi_mac_notify_mic_fail(struct wlan_net_vif *wnet_vif, const struct wifi_frame *wh, unsigned int key_index) @@ -107222,12 +109022,22 @@ index 000000000000..a603026f0e19 + return 0; +} + ++void aml_skb_unlink(struct sk_buff *skb, struct sk_buff_head *list) ++{ ++ struct sk_buff *next, *prev; ++ ++ next = skb->next; ++ prev = skb->prev; ++ skb->next = skb->prev = NULL; ++ next->prev = prev; ++ prev->next = next; ++} diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_sta.h b/drivers/net/wireless/w1/vmac/wifi_mac_sta.h new file mode 100644 -index 000000000000..9a6a50762bf3 +index 0000000000000000000000000000000000000000..00c0da965443230b70997ab71ce57b952a1ccc16 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_sta.h -@@ -0,0 +1,587 @@ +@@ -0,0 +1,594 @@ +/* + **************************************************************************************** + * @@ -107417,6 +109227,8 @@ index 000000000000..9a6a50762bf3 + unsigned short sta_flags; + unsigned short sta_flags_ext; + ++ unsigned char *sta_assoc_req; ++ unsigned int sta_assoc_req_ielen; + unsigned short sta_associd; + unsigned char sta_txpower; + unsigned short sta_vlan; @@ -107461,6 +109273,8 @@ index 000000000000..9a6a50762bf3 + unsigned char sta_uapsd_ac_delivena[WME_NUM_AC]; + + unsigned char *sta_rsn_ie; ++ unsigned char *sta_rsnxe_ie; ++ unsigned char sta_use_h2e; + struct wifi_mac_Rsnparms sta_rsn; + struct wifi_mac_key sta_ucastkey; + struct wifi_mac_key pmf_key; @@ -107497,6 +109311,8 @@ index 000000000000..9a6a50762bf3 + unsigned char sta_wide_bw_ch_sw_sub_ie[SUB_IE_MAX_LEN]; + unsigned char sta_new_vht_tx_pw_sub_ie[SUB_IE_MAX_LEN]; + unsigned char sta_channel_switch_mode; ++ int sta_chan_switch_chan; ++ struct os_timer_ext csa_timer; + + //ext bss ld element + unsigned short sta_mu_mimo_sta_cnt; @@ -107655,6 +109471,7 @@ index 000000000000..9a6a50762bf3 +void wifi_mac_sta_disconnect_from_ap(struct wifi_station *); +void wifi_mac_sta_deauth(void *arg, struct wifi_station *sta); +void wifi_mac_sta_disassoc(void *arg, struct wifi_station *sta); ++void wifi_mac_sta_disassoc_in_task(struct wlan_net_vif *wnet_vif); +struct wifi_station *wifi_mac_find_mgmt_tx_sta(struct wlan_net_vif *wnet_vif, const unsigned char *mac); + +void wifi_mac_list_sta( struct wlan_net_vif *wnet_vif); @@ -107779,7 +109596,7 @@ index 000000000000..9a6a50762bf3 + +#define MY_MOD_INC_USE(_m, _err) do{\ + if (my_mod_use>2) {\ -+ printk(KERN_WARNING "%s: try_module_get failed\n",__func__); \ ++ pr_warn("%s: try_module_get failed\n",__func__); \ + _err;\ + }\ + my_mod_use= 1;\ @@ -107813,14 +109630,14 @@ index 000000000000..9a6a50762bf3 +void os_skb_set_amsdu(struct sk_buff *skb); +int os_skb_is_amsdu(struct sk_buff *skb); +int os_skb_is_uapsd(struct sk_buff *skb); -+ ++void aml_skb_unlink(struct sk_buff *skb, struct sk_buff_head *list); +#endif /* _NET80211_IEEE80211_NODE_H_ */ diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_var.h b/drivers/net/wireless/w1/vmac/wifi_mac_var.h new file mode 100644 -index 000000000000..58c774685641 +index 0000000000000000000000000000000000000000..8b85c145551bf60d4de8cb767bbd5c5cdeb68cd5 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_var.h -@@ -0,0 +1,973 @@ +@@ -0,0 +1,1016 @@ +/* + **************************************************************************************** + * @@ -107954,10 +109771,11 @@ index 000000000000..58c774685641 + +#define WIFINET_BINTVAL_DEFAULT 100 +#define DEFAULT_MGMT_RETRY_TIMES 3 -+#define DEFAULT_P2P_ACTION_RETRY_TIMES 5 ++#define DEFAULT_P2P_ACTION_RETRY_TIMES 3 +#define DEFAULT_MGMT_RETRY_INTERVAL 512 +#define DEFAULT_P2P_ACTION_RETRY_INTERVAL 50 +#define DEFAULT_AUTH_RETRY_INTERVAL 512 ++#define DEFAULT_DEAUTH_TOT 5000 + +#define WIFINET_PS_MAX_QUEUE 100 + @@ -108149,6 +109967,27 @@ index 000000000000..58c774685641 + CONCURRENT_CHANNEL_SWITCH = BIT(0), + CONCURRENT_NOTIFY_AP = BIT(1), + CONCURRENT_NOTIFY_AP_SUCCESS = BIT(2), ++ CONCURRENT_AP_SWITCH_CHANNEL = BIT(3), ++ CONCURRENT_SWITCH_TO_STA_CHANNEL = BIT(4), ++}; ++ ++enum DisconnectionReasonCode { ++ DISCONNECT_SYSTEM, ///< Disconnection initiated by higher layer. ++ DISCONNECT_DRVINIT, ///< Generic Disconnection initiated by Driver. ++ DISCONNECT_NETDEVDOWN, ///< Disconnection initiated by driver when the network interface is down. ++ DISCONNECT_DFSDETECTION, ///< Disconnection by Driver when DFS is detected on the serving channel. ++ DISCONNECT_UNSUPCHAN, ///< Disconnection by Driver when AP switched to an unsupported channel. ++ DISCONNECT_DFSCHAN, ///< Disconnection by Driver when AP switched to a DFS channel. ++ DISCONNECT_APLEAVE, ///< Disconnection by Driver when connection to AP is lost. ++ DISCONNECT_APROAMFAIL, ///< Disconnection by Driver when Roaming Failed. ++ DISCONNECT_RCVDEAUTH, ///< Disconnection initiated by AP and Deauth Received. ++ DISCONNECT_RCVDISASSOC, ///< Disconnection initiated by AP and Disassoc Received. ++ DISCONNECT_GENERIC ///< Uncategorized Disconnection Reasons. ++}; ++ ++struct chan_switch_target_t { ++ unsigned char start; ++ struct wifi_channel switch_chan; +}; + +struct wifi_mac_chan_overlapping { @@ -108156,6 +109995,12 @@ index 000000000000..58c774685641 + unsigned short overlapping; +}; + ++enum VsdbState { ++ VSDB_STATE_DISABLE, ++ VSDB_STATE_ENABLE, ++ VSDB_STATE_MAX, ++}; ++ +struct wifi_mac +{ + unsigned char wm_mac_exit; @@ -108234,10 +110079,12 @@ index 000000000000..58c774685641 + +#ifdef CONFIG_CONCURRENT_MODE + struct os_timer_ext wm_concurrenttimer; ++ unsigned char wm_vsdb_sate; + unsigned char wm_vsdb_slot; + unsigned short wm_vsdb_flags; + unsigned long wm_vsdb_switch_time; +#endif //CONFIG_CONCURRENT_MODE ++ struct os_timer_ext wm_csa_trigger_timer; + + enum wifi_mac_protmode wm_protmode; + unsigned short wm_nonerpsta; @@ -108272,6 +110119,7 @@ index 000000000000..58c774685641 + int msdu_cnt[WME_NUM_TID ]; + struct msdu_list msdu_node_list; + ++ unsigned short wm_p2p_home_channel; + unsigned char wm_p2p_connection_protect; + unsigned long wm_p2p_connection_protect_period; + unsigned char is_miracast_connect; @@ -108296,6 +110144,7 @@ index 000000000000..58c774685641 + enum wifi_mac_recovery_state recovery_stat; + struct os_timer_ext wm_monitor_fw; + spinlock_t fw_stat_lock; ++ unsigned char wm_wfa_enable; + +#if defined(SU_BF) || defined(MU_BF) + int max_spatial; @@ -108383,6 +110232,7 @@ index 000000000000..58c774685641 + unsigned char wnet_vif_id; + enum wifi_mac_opmode vm_opmode; + enum wifi_mac_state vm_state; ++ enum wifi_mac_state vm_state_pre; + unsigned char remain_on_channel; + struct ieee80211_channel remain_on_ch_channel; + unsigned long long remain_on_ch_cookie; @@ -108459,6 +110309,8 @@ index 000000000000..58c774685641 + unsigned char vm_chanchange_count; + unsigned char vm_bmiss_count; + struct wifi_mac_rateset vm_legacy_rates; ++ struct chan_switch_target_t csa_target; ++ unsigned char csa_count; + + struct wifi_mac_wmm_ac_params vm_wmm_ac_params; + struct wifi_mac_wmm_tspec_element tspecs[WME_AC_NUM][TS_DIR_IDX_COUNT]; @@ -108523,6 +110375,9 @@ index 000000000000..58c774685641 + struct wifi_mac_p2p* vm_p2p; + int vm_p2p_support; +#endif ++ unsigned int disconnect_reason_code; ++ unsigned char vm_sae_h2e_only; ++ struct wifi_channel *vm_des_channel; +}; + +#define WIFINET_PSQUEUE_PS4QUIET 0x0001 @@ -108556,8 +110411,10 @@ index 000000000000..58c774685641 +#define WIFINET_F_WPA1 0x00800000 +#define WIFINET_F_WPA2 0x01000000 +#define WIFINET_F_WPA 0x01800000 ++#define WIFINET_F_H2E 0x02000000 +#define WIFINET_F_COUNTERM 0x04000000 +#define WIFINET_F_HIDESSID 0x08000000 ++#define WIFINET_F_HIDESSID_TO_BIT0_OFST 27 +#define WIFINET_F_WMEUPDATE 0x20000000 +#define WIFINET_F_DOTH 0x40000000 +#define WIFINET_F_CHANSWITCH 0x80000000 @@ -108591,6 +110448,9 @@ index 000000000000..58c774685641 +#define WIFINET_FEXT2_SWITCH_CHANNEL 0x80000000 +#define WIFINET_FEXT2_ALLOW_SWITCH_CHANNEL 0x01000000 + ++#define WIFINET_FEXT2_MGMT_RESTORE_CHANNEL 0x00000001 ++#define WIFINET_FEXT2_DPP_SEND 0x00000002 ++#define WIFINET_FEXT2_DPP_CONNECTION_STATUS_RETRY 0x00000004 + +#define WIFINET_FEXT2_PUREBGN (WIFINET_FEXT2_PUREB|WIFINET_FEXT2_PUREG|WIFINET_FEXT2_PUREN) +#define WIFINET_FEXT2_PUREBG (WIFINET_FEXT2_PUREG|WIFINET_FEXT2_PUREB) @@ -108796,10 +110656,10 @@ index 000000000000..58c774685641 +#endif /* _NET80211_IEEE80211_VAR_H_ */ diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_xmit.c b/drivers/net/wireless/w1/vmac/wifi_mac_xmit.c new file mode 100644 -index 000000000000..787bcf1e6bee +index 0000000000000000000000000000000000000000..ee538a7a28b911ae5103f00212e4dba17343b396 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_xmit.c -@@ -0,0 +1,3747 @@ +@@ -0,0 +1,3956 @@ +/* + **************************************************************************************** + * @@ -108819,7 +110679,7 @@ index 000000000000..787bcf1e6bee +#include +#include "wifi_cmd_func.h" + -+int wifi_mac_classify(struct wifi_station *sta, struct sk_buff *skb) ++static int wifi_mac_classify(struct wifi_station *sta, struct sk_buff *skb) +{ + struct wlan_net_vif *wnet_vif = sta->sta_wnet_vif; + struct ether_header *eh = (struct ether_header *) os_skb_data(skb); @@ -108878,7 +110738,7 @@ index 000000000000..787bcf1e6bee + if (v_wme_ac > d_wme_ac) + { + cb->u_tid = v_pri; -+ printk(" %s %d cb->u_tid = %d\n",__func__,__LINE__,cb->u_tid); ++ pr_debug(" %s %d cb->u_tid = %d\n",__func__,__LINE__,cb->u_tid); + os_skb_set_priority(skb,v_wme_ac); + } + @@ -108910,7 +110770,7 @@ index 000000000000..787bcf1e6bee + } + + txinfo->tid_index = os_skb_get_tid(skb); -+ //printk("%s tid_index:%d\n", __func__, txinfo->tid_index); ++ //pr_debug("%s tid_index:%d\n", __func__, txinfo->tid_index); + + return 0; +} @@ -108926,7 +110786,7 @@ index 000000000000..787bcf1e6bee +} + + -+void wifi_mac_get_rtsp_session(char* rtsp, struct wifi_mac_p2p* p2p) ++static void wifi_mac_get_rtsp_session(char* rtsp, struct wifi_mac_p2p* p2p) +{ + char *buf = rtsp; + char id_buf[8]; @@ -108945,7 +110805,7 @@ index 000000000000..787bcf1e6bee + strcat(p2p->wfd_session_id, id_buf); + buf++; + } -+ printk("wfd_session_id=%s\n", p2p->wfd_session_id); ++ pr_debug("wfd_session_id=%s\n", p2p->wfd_session_id); + } +} + @@ -109109,7 +110969,7 @@ index 000000000000..787bcf1e6bee + pending_cnt = wifimac->drv_priv->drv_ops.drv_tx_pending_pkt(wifimac->drv_priv); + + if (qlen_real + pending_cnt > 200) { -+ //printk("qlen_real:%d, pending_cnt:%d\n", qlen_real, pending_cnt); ++ //pr_debug("qlen_real:%d, pending_cnt:%d\n", qlen_real, pending_cnt); + wnet_vif->vm_devstats.tx_dropped++; + wnet_vif->vif_sts.sts_tx_tid_drop_bf_in_msdu[os_skb_get_tid(skb)]++; + return NETDEV_TX_BUSY; @@ -109119,7 +110979,7 @@ index 000000000000..787bcf1e6bee + return 0; +} + -+unsigned short wifi_mac_checksum_calc(unsigned short len_udp, unsigned char * src_addr, ++static unsigned short wifi_mac_checksum_calc(unsigned short len_udp, unsigned char * src_addr, + unsigned char *dest_addr, unsigned char type, unsigned char *buff) +{ + unsigned short padd = 0; @@ -109171,7 +111031,7 @@ index 000000000000..787bcf1e6bee + return 0; +} + -+int wifi_mac_tcp_csum(struct sk_buff *skb) ++static int wifi_mac_tcp_csum(struct sk_buff *skb) +{ + struct iphdr *iphdrp = (struct iphdr *)((unsigned char *)os_skb_data(skb)+sizeof(struct ether_header)); + struct tcphdr *th = (struct tcphdr *)((unsigned char *)iphdrp + (iphdrp->ihl << 2)); @@ -109191,22 +111051,23 @@ index 000000000000..787bcf1e6bee + struct ether_header *eh = NULL; + struct iphdr *iphdrp = NULL; + unsigned char hw_calculate_flag = 0; -+ struct wifi_mac_tx_info *txinfo = (struct wifi_mac_tx_info *)os_skb_cb(skb); ++ struct wifi_mac_tx_info *txinfo; + struct drv_txdesc *ptxdesc = NULL; + unsigned char error = 0; + -+ if (aml_wifi_is_enable_rf_test()) -+ goto bad; ++ if (aml_wifi_is_enable_rf_test()) ++ goto bad; + + if (skb != NULL) { + eh = (struct ether_header *)os_skb_data(skb); + os_skb_count_alloc(skb); -+ + } else { + error = 1; + goto bad; + } + ++ txinfo = (struct wifi_mac_tx_info *)os_skb_cb(skb); ++ + if (NET80211_IF_RUN_UP(wifimac) == 0) { + error = 2; + goto bad; @@ -109389,7 +111250,7 @@ index 000000000000..787bcf1e6bee +} + +static void -+wifi_mac_mgmt_output(struct wifi_station *sta, struct sk_buff *skb, int type) ++wifi_mac_mgmt_csa_action_broadcast_output(struct wifi_station *sta, struct sk_buff *skb, int type) +{ + struct wlan_net_vif *wnet_vif = sta->sta_wnet_vif; + struct wifi_mac *wifimac = sta->sta_wmac; @@ -109402,6 +111263,40 @@ index 000000000000..787bcf1e6bee + + wh = (struct wifi_frame *)os_skb_push(skb, sizeof(struct wifi_frame)); + wifi_mac_send_setup(wnet_vif, sta, wh, WIFINET_FC0_TYPE_MGT | type, ++ wnet_vif->vm_myaddr, BROADCAST_ADDRESS, sta->sta_bssid); ++ ++ if ((cb->flags & M_LINK0) != 0 && sta->sta_challenge != NULL) ++ { ++ cb->flags &= ~M_LINK0; ++ DPRINTF(AML_DEBUG_CONNECT, "recv addr is [%02x:%02x:%02x:%02x:%02x:%02x]\n", ++ wh->i_addr1[0], wh->i_addr1[1], wh->i_addr1[2], ++ wh->i_addr1[3], wh->i_addr1[4], wh->i_addr1[5]); ++ wh->i_fc[1] |= WIFINET_FC1_WEP; ++ } ++ ++ if (WIFINET_VMAC_IS_SLEEPING(sta->sta_wnet_vif)) ++ wh->i_fc[1] |= WIFINET_FC1_PWR_MGT; ++ ++ WIFINET_NODE_STAT(sta, tx_mgmt); ++ wifi_mac_tx_mgmt_frm(wifimac, skb); ++} ++ ++static void ++wifi_mac_mgmt_output(struct wifi_station *sta, struct sk_buff *skb, int type) ++{ ++ struct wlan_net_vif *wnet_vif; ++ struct wifi_mac *wifimac; ++ struct wifi_frame *wh; ++ struct wifi_skb_callback *cb = (struct wifi_skb_callback *)skb->cb; ++ ++ KASSERT(sta != NULL, ("null nsta")); ++ ++ wnet_vif = sta->sta_wnet_vif; ++ wifimac = sta->sta_wmac; ++ cb->sta = sta; ++ ++ wh = (struct wifi_frame *)os_skb_push(skb, sizeof(struct wifi_frame)); ++ wifi_mac_send_setup(wnet_vif, sta, wh, WIFINET_FC0_TYPE_MGT | type, + wnet_vif->vm_myaddr, sta->sta_macaddr, sta->sta_bssid); + + if ((cb->flags & M_LINK0) != 0 && sta->sta_challenge != NULL) @@ -109419,17 +111314,21 @@ index 000000000000..787bcf1e6bee +} + +static void -+wifi_mac_mgmt_probe_resp_output(struct wifi_station *sta, -+ struct sk_buff *skb, unsigned char *macaddr) ++wifi_mac_mgmt_probe_resp_output(struct wifi_station *sta, ++ struct sk_buff *skb, ++ unsigned char *macaddr) +{ -+ struct wlan_net_vif *wnet_vif = sta->sta_wnet_vif; -+ struct wifi_mac *wifimac = sta->sta_wmac; ++ struct wlan_net_vif *wnet_vif; ++ struct wifi_mac *wifimac; + struct wifi_frame *wh; + struct wifi_skb_callback *cb = (struct wifi_skb_callback *)skb->cb; + unsigned char * bssid = NULL; + unsigned char * sa = NULL; ++ + KASSERT(sta != NULL, ("null nsta")); + ++ wnet_vif = sta->sta_wnet_vif; ++ wifimac = sta->sta_wmac; + cb->sta = sta; + + wh = (struct wifi_frame *)os_skb_push(skb, sizeof(struct wifi_frame)); @@ -109473,13 +111372,17 @@ index 000000000000..787bcf1e6bee + unsigned char pkt_len = 0; + unsigned char subtype = 0; + int error = 0; -+ struct wlan_net_vif *wnet_vif = sta->sta_wnet_vif; -+ struct wifi_mac *wifimac = sta->sta_wmac; ++ struct wlan_net_vif *wnet_vif; ++ struct wifi_mac *wifimac; + struct wifi_mac_tx_info *txinfo = NULL; + struct wifi_frame *wh; + struct wifi_skb_callback *cb = NULL; + + KASSERT(sta != NULL, ("null nsta")); ++ ++ wnet_vif = sta->sta_wnet_vif; ++ wifimac = sta->sta_wmac; ++ + if (qos) { + pkt_len = sizeof(struct wifi_qos_frame) + FCS_LEN; + subtype = WIFINET_FC0_SUBTYPE_QOS_NULL; @@ -109718,7 +111621,7 @@ index 000000000000..787bcf1e6bee + return &wnet_vif->vm_nw_keys[wnet_vif->vm_def_txkey]; +} + -+unsigned short calculate_checksum(unsigned short *buffer, int len) ++static unsigned short calculate_checksum(unsigned short *buffer, int len) +{ + unsigned int cksum = 0; + unsigned short *p = buffer; @@ -109733,7 +111636,7 @@ index 000000000000..787bcf1e6bee + return (unsigned short) (~cksum); +} + -+void calculate_checksum_for_fragment_pkt(struct sk_buff *skb, struct ether_header eh, char hdrsize) { ++static void calculate_checksum_for_fragment_pkt(struct sk_buff *skb, struct ether_header eh, char hdrsize) { + unsigned short is_hw_calculate = M_FLAG_GET(skb, M_CHECKSUMHW); + unsigned char ip_pkt_offset; + unsigned short *ip_hdr; @@ -109749,7 +111652,7 @@ index 000000000000..787bcf1e6bee + struct tcphdr *th = (struct tcphdr *)((unsigned char *)iphdrp + (iphdrp->ihl << 2)); + struct udphdr *uh = (struct udphdr *)((unsigned char *)iphdrp + (iphdrp->ihl << 2)); + -+ //printk("chris ip_pkt_offset:%d, hdrsize:%d, iphdrp->ihl:%d\n", ip_pkt_offset, hdrsize, iphdrp->ihl); ++ //pr_debug("chris ip_pkt_offset:%d, hdrsize:%d, iphdrp->ihl:%d\n", ip_pkt_offset, hdrsize, iphdrp->ihl); + iphdrp->check = 0; + ip_hdr = (unsigned short *)((unsigned char *)os_skb_data(skb) + ip_pkt_offset); + iphdrp->check = calculate_checksum(ip_hdr, iphdrp->ihl * 4); @@ -110386,6 +112289,19 @@ index 000000000000..787bcf1e6bee +} + +unsigned char * ++wifi_mac_add_rsnxe(unsigned char *frm, struct wlan_net_vif *wnet_vif) ++{ ++ ++ KASSERT((wnet_vif->vm_flags & WIFINET_F_WPA) ++ && (wnet_vif->vm_flags & WIFINET_F_H2E), ("no WPA/RSNXE!")); ++ *frm++ = WIFINET_ELEMID_RSNX; ++ *frm++ = 0x1;//len ++ *frm++ = 0x20;//h2e ++ ++ return frm; ++} ++ ++unsigned char * +wifi_mac_add_wpa(unsigned char *frm, struct wlan_net_vif *wnet_vif) +{ + @@ -110649,42 +112565,42 @@ index 000000000000..787bcf1e6bee + return frm + htcaplen; +} + -+void print_ht_opt_information(unsigned char* ht_opt) ++static void print_ht_opt_information(unsigned char* ht_opt) +{ + if (ht_opt[0] != WIFINET_ELEMID_HTINFO) + { -+ printk("%s(%d), Not HT OP IE:%d.\n\n",__func__,__LINE__,ht_opt[0]); ++ pr_warn("%s(%d), Not HT OP IE:%d.\n\n",__func__,__LINE__,ht_opt[0]); + return; + } + + /*Print Primary Channel*/ -+ printk("%s(%d),primary channel:%d.\n",__func__,__LINE__,ht_opt[2]); ++ pr_debug("%s(%d),primary channel:%d.\n",__func__,__LINE__,ht_opt[2]); + + /*Second channel offset parsing*/ + switch( ht_opt[3] & 0x03 ) + { + case 1: -+ printk("%s(%d),Secondary Channel is ABOVE the primary channel.\n",__func__,__LINE__); ++ pr_debug("%s(%d),Secondary Channel is ABOVE the primary channel.\n",__func__,__LINE__); + break; + case 3: -+ printk("%s(%d),Secondary Channel is BELOW the primary channel.\n",__func__,__LINE__); ++ pr_debug("%s(%d),Secondary Channel is BELOW the primary channel.\n",__func__,__LINE__); + break; + case 0: -+ printk("%s(%d),No Secondary Channel is present.\n",__func__,__LINE__); ++ pr_debug("%s(%d),No Secondary Channel is present.\n",__func__,__LINE__); + break; + default: -+ printk("%s(%d),Reserved value.\n",__func__,__LINE__); ++ pr_warn("%s(%d),Reserved value.\n",__func__,__LINE__); + break; + } + + /*STA Channel Width parsing*/ + if ( ht_opt[3] & 0x03 ) + { -+ printk("%s(%d),HT_OP:Allow use of any channel width in the supported channle width set.\n",__func__,__LINE__); ++ pr_debug("%s(%d),HT_OP:Allow use of any channel width in the supported channel width set.\n",__func__,__LINE__); + } + else + { -+ printk("%s(%d),HT_OP:20M channel bandwidth.\n",__func__,__LINE__); ++ pr_debug("%s(%d),HT_OP:20M channel bandwidth.\n",__func__,__LINE__); + } + + return; @@ -110931,25 +112847,25 @@ index 000000000000..787bcf1e6bee + return frm + vht_cap_len; +} + -+void print_vht_opt_information(unsigned char* vht_opt) ++static void print_vht_opt_information(unsigned char* vht_opt) +{ + if (vht_opt[0] != WIFINET_ELEMID_VHTOP) + { -+ printk("%s(%d), Not VHT OP IE:%d.\n\n",__func__,__LINE__,vht_opt[0]); ++ pr_debug("%s(%d), Not VHT OP IE:%d.\n\n",__func__,__LINE__,vht_opt[0]); + return; + } + if (vht_opt[2] & 0x3 )/*Channel Width,1:80M;0:20M or 40M BSS bandwidth*/ + { -+ printk("%s(%d),Channel bandwidth: 80M.\n",__func__,__LINE__); ++ pr_debug("%s(%d),Channel bandwidth: 80M.\n",__func__,__LINE__); + } + else + { -+ printk("%s(%d),Channel bandwidth: 20M or 40M.\n",__func__,__LINE__); ++ pr_debug("%s(%d),Channel bandwidth: 20M or 40M.\n",__func__,__LINE__); + } + + /*Print vht_oper_centr_freq_seg0/1_idx*/ -+ printk("%s(%d),vht_oper_centr_freq_seg0_idx:%d.\n",__func__,__LINE__,vht_opt[3]); -+ printk("%s(%d),vht_oper_centr_freq_seg1_idx:%d.\n",__func__,__LINE__,vht_opt[4]); ++ pr_debug("%s(%d),vht_oper_centr_freq_seg0_idx:%d.\n",__func__,__LINE__,vht_opt[3]); ++ pr_debug("%s(%d),vht_oper_centr_freq_seg1_idx:%d.\n",__func__,__LINE__,vht_opt[4]); + + return; +} @@ -111204,7 +113120,8 @@ index 000000000000..787bcf1e6bee +#endif//#ifdef CONFIG_P2P + + sizeof(struct wifi_mac_ie_htcap) + sizeof(struct wifi_mac_ie_htinfo) + sizeof (struct wifi_mac_ie_obss_scan) + + sizeof (struct wifi_mac_ie_ext_cap) + WIFINET_APPIE_MAX + sizeof(struct wifi_mac_ie_vht_cap) + sizeof(struct wifi_mac_ie_vht_opt) -+ + sizeof(struct wifi_mac_ie_vht_txpwr_env) + sizeof(struct wifi_mac_ie_vht_ch_sw_wrp) + sizeof(struct wifi_mac_vendor_ie) * VENDOR_IE_MAX; ++ + sizeof(struct wifi_mac_ie_vht_txpwr_env) + sizeof(struct wifi_mac_ie_vht_ch_sw_wrp) + sizeof(struct wifi_mac_vendor_ie) * VENDOR_IE_MAX ++ + (((wnet_vif->vm_flags & WIFINET_F_WPA) && (wnet_vif->vm_flags & WIFINET_F_H2E))? WIFINET_RSNXE_SIZE:0); + + skb = wifi_mac_get_mgmt_frm(wifimac, pkt_len); + if (skb == NULL) @@ -111297,6 +113214,11 @@ index 000000000000..787bcf1e6bee + if ((wifimac->wm_flags & WIFINET_F_DOTH) || + (wifimac->wm_flags_ext & WIFINET_FEXT_COUNTRYIE)) + { ++ if (wifimac->wm_countryinfo.country_len == 0) ++ { ++ AML_OUTPUT("country ie should init\n"); ++ wifi_mac_build_country_ie(wnet_vif); ++ } + frm = wifi_mac_add_country(frm, wifimac); + } + @@ -111310,8 +113232,12 @@ index 000000000000..787bcf1e6bee + if (WIFINET_INCLUDE_11G(wnet_vif->vm_mac_mode)) + frm = wifi_mac_add_erp(frm, wifimac); + -+ if (wnet_vif->vm_flags & WIFINET_F_WPA) ++ if (wnet_vif->vm_flags & WIFINET_F_WPA) { + frm = wifi_mac_add_wpa(frm, wnet_vif); ++ if (wnet_vif->vm_flags & WIFINET_F_H2E) { ++ frm = wifi_mac_add_rsnxe(frm, wnet_vif); ++ } ++ } + + if (wnet_vif->vm_flags & WIFINET_F_WME) + { @@ -111372,7 +113298,10 @@ index 000000000000..787bcf1e6bee + if(wifi_mac_is_vht_enable(wnet_vif)) + { + frm = wifi_mac_add_vht_cap(frm, sta); -+ frm = wifi_mac_add_vht_opt(frm, sta, WIFINET_FC0_SUBTYPE_PROBE_RESP); ++ if (!wnet_vif->vm_p2p_support || (wnet_vif->vm_p2p_support && wnet_vif->vm_curchan != NULL)) ++ { ++ frm = wifi_mac_add_vht_opt(frm, sta, WIFINET_FC0_SUBTYPE_PROBE_RESP); ++ } + //frm = wifi_mac_add_vht_txpw(frm, sta); + //frm = wifi_mac_add_vht_ch_sw_wrp(frm, sta); + @@ -111480,7 +113409,7 @@ index 000000000000..787bcf1e6bee + return 0; +} + -+int aml_rsn_sync_pmkid(struct wifi_station *sta, int pmkid_index) ++static int aml_rsn_sync_pmkid(struct wifi_station *sta, int pmkid_index) +{ + struct wlan_net_vif *wnet_vif = sta->sta_wnet_vif; + struct wifi_mac_Rsnparms *rsn = &sta->sta_rsn; @@ -111563,18 +113492,19 @@ index 000000000000..787bcf1e6bee +void wifi_mac_check_opt_ie(struct wlan_net_vif *wnet_vif) +{ + unsigned char *frm = wnet_vif->vm_opt_ie; -+ unsigned int i = 0, j = 0; ++ unsigned short ie_len = 0; ++ unsigned int ie_oft = 0;//ie addr offset + -+ while(i < wnet_vif->vm_opt_ie_len) { -+ if (frm[i] == WIFINET_ELEMID_SUPP_REG_CLASS) { -+ j = i + frm[i+1] + 2; -+ if (j < wnet_vif->vm_opt_ie_len) { -+ memcpy(&frm[i], &frm[j], wnet_vif->vm_opt_ie_len - j); ++ while (ie_oft < wnet_vif->vm_opt_ie_len) { ++ ie_len = frm[ie_oft + 1] + 2; ++ if (frm[ie_oft] == WIFINET_ELEMID_SUPP_REG_CLASS) { ++ if (ie_oft + ie_len < wnet_vif->vm_opt_ie_len) { ++ memcpy(&frm[ie_oft], &frm[ie_oft + ie_len], wnet_vif->vm_opt_ie_len - ie_oft - ie_len); ++ wnet_vif->vm_opt_ie_len -= ie_len; + } -+ wnet_vif->vm_opt_ie_len -= (frm[i+1] + 2); + return; + } -+ i += frm[i+1] + 2; ++ ie_oft += ie_len; + } +} + @@ -111728,7 +113658,8 @@ index 000000000000..787bcf1e6bee + pkt_len = sizeof(capinfo) + sizeof(unsigned short) + sizeof(unsigned short) + 2 + WIFINET_RATE_SIZE + sizeof(struct wifi_mac_ie_timeout) + + 2 + (WIFINET_RATE_MAXSIZE - WIFINET_RATE_SIZE) + sizeof(struct wifi_mac_wme_param) + sizeof(struct wifi_mac_ie_htcap) + + sizeof(struct wifi_mac_ie_htinfo) + sizeof (struct wifi_mac_ie_obss_scan) + sizeof (struct wifi_mac_ie_ext_cap) + WIFINET_APPIE_MAX -+ + sizeof(struct wifi_mac_vendor_ie) * VENDOR_IE_MAX; ++ + sizeof(struct wifi_mac_vendor_ie) * VENDOR_IE_MAX ++ + ((sta->sta_use_h2e == WIFINET_H2E_VALID)? WIFINET_RSNXE_SIZE:0); + + skb = wifi_mac_get_mgmt_frm(wifimac, pkt_len); + if (skb == NULL) { @@ -111781,9 +113712,14 @@ index 000000000000..787bcf1e6bee + WIFINET_VMAC_UAPSD_ENABLED(wnet_vif)); + } + -+ printk("%s %d sta flags: 0x%x, assoc success :%d.\n",__func__,__LINE__,sta->sta_flags, *(int *)arg); ++ if (sta->sta_use_h2e == WIFINET_H2E_VALID) { ++ frm = wifi_mac_add_rsnxe(frm, wnet_vif); ++ AML_OUTPUT("add rsnxe ie\n"); ++ } ++ ++ pr_debug("%s %d sta flags: 0x%x, assoc success :%d.\n",__func__,__LINE__,sta->sta_flags, *(int *)arg); + if (sta->sta_flags & WIFINET_NODE_HT) { -+ printk("%s %d will add ht cat and op for assocresp\n",__func__,__LINE__); ++ pr_debug("%s %d will add ht cat and op for assocresp\n",__func__,__LINE__); + frm = wifi_mac_add_htcap(frm, sta); + frm = wifi_mac_add_htinfo(frm, sta); + @@ -111794,7 +113730,7 @@ index 000000000000..787bcf1e6bee + } + + if (wifi_mac_is_vht_enable(wnet_vif) && (sta->sta_flags & WIFINET_NODE_VHT)) { -+ printk("%s %d will add vht cat and op for assocresp\n",__func__,__LINE__); ++ pr_debug("%s %d will add vht cat and op for assocresp\n",__func__,__LINE__); + frm = wifi_mac_add_vht_cap( frm, sta) ; + frm = wifi_mac_add_vht_opt( frm, sta , WIFINET_FC0_SUBTYPE_ASSOC_RESP); + } @@ -111863,7 +113799,7 @@ index 000000000000..787bcf1e6bee + return 0; +} + -+void wifi_mac_get_bsscoexist_channel(unsigned char *chan_list, unsigned char *num_channels, unsigned char *num_intol) ++static void wifi_mac_get_bsscoexist_channel(unsigned char *chan_list, unsigned char *num_channels, unsigned char *num_intol) +{ + struct wifi_mac *wifi_mac = wifi_mac_get_mac_handle(); + struct wifi_mac_scan_state *ss = wifi_mac->wm_scan; @@ -111909,7 +113845,7 @@ index 000000000000..787bcf1e6bee + *num_intol = intol_count; +} + -+void wifi_mac_build_wmm_tspec_ie(struct wlan_net_vif *wnet_vif, struct wifi_mac_wmm_tspec_element *ie) ++static void wifi_mac_build_wmm_tspec_ie(struct wlan_net_vif *wnet_vif, struct wifi_mac_wmm_tspec_element *ie) +{ + struct wifi_mac_wmm_tspec_element *tspec = ie; + char uapsd = 0; @@ -111941,7 +113877,7 @@ index 000000000000..787bcf1e6bee + +} + -+int wifi_mac_up_to_ac(struct wlan_net_vif *wnet_vif) ++static int wifi_mac_up_to_ac(struct wlan_net_vif *wnet_vif) +{ + int ac = 0; + if (wnet_vif->vm_wmm_ac_params.up == 0 || wnet_vif->vm_wmm_ac_params.up == 1) { @@ -111956,13 +113892,13 @@ index 000000000000..787bcf1e6bee + return ac; +} + -+unsigned char wmm_ac_get_tid(const struct wifi_mac_wmm_tspec_element tspec) ++static unsigned char wmm_ac_get_tid(const struct wifi_mac_wmm_tspec_element tspec) +{ + return (tspec.ts_info[0] >> 1) & 0x0f; +} + + -+unsigned char wmm_ac_find_tid(struct wlan_net_vif *wnet_vif, unsigned char tid, unsigned char *dir) ++static unsigned char wmm_ac_find_tid(struct wlan_net_vif *wnet_vif, unsigned char tid, unsigned char *dir) +{ + unsigned char ac; + unsigned char idx; @@ -112064,7 +114000,7 @@ index 000000000000..787bcf1e6bee + + wifi_mac_addba_rsp_setup(sta, tid_index); + *(unsigned short *)&addbaresponse->rs_baparamset = htole16(*(unsigned short *)&baparamset); -+ //dump_memory_internel(&baparamset,sizeof(struct wifi_mac_ba_parameterset)); ++ //dump_memory_internal(&baparamset,sizeof(struct wifi_mac_ba_parameterset)); + addbaresponse->rs_batimeout = htole16(batimeout); + addbaresponse->rs_statuscode = htole16(statuscode); + @@ -112148,7 +114084,7 @@ index 000000000000..787bcf1e6bee + switch (action) { + case WIFINET_ACT_PUBLIC_BSSCOEXIST: + wifi_mac_get_bsscoexist_channel(chan_list, &num_channels, &num_intol); -+ printk("%s:%d, num_channels=%d, num_intol=%d.\n", __func__, __LINE__, num_channels, num_intol); ++ pr_debug("%s:%d, num_channels=%d, num_intol=%d.\n", __func__, __LINE__, num_channels, num_intol); + + frm = os_skb_put(skb, sizeof(struct wifi_mac_action_bss_coex_frame) + num_channels); + bsscoex = (struct wifi_mac_action_bss_coex_frame *)frm; @@ -112238,12 +114174,20 @@ index 000000000000..787bcf1e6bee + +int wifi_mac_send_mgmt(struct wifi_station *sta, int type, void *arg) +{ -+ struct wlan_net_vif *wnet_vif = sta->sta_wnet_vif; ++ struct wlan_net_vif *wnet_vif; + int ret; + unsigned char retry_count; + + KASSERT(sta != NULL, ("null nsta")); + ++ wnet_vif = sta->sta_wnet_vif; ++ ++ if (wnet_vif->vm_curchan == NULL && !wnet_vif->vm_p2p_support) { ++ ERROR_DEBUG_OUT("vm_curchan is NULL, just return\n"); ++ ret = EINVAL; ++ return ret; ++ } ++ + switch (type) { + case WIFINET_FC0_SUBTYPE_PROBE_RESP: + ret = wifi_mac_send_probe_rsp(wnet_vif,sta,arg); @@ -112329,7 +114273,7 @@ index 000000000000..787bcf1e6bee + memset(&ipv4, 0, sizeof(ipv4)); + ipv4 = ifa_v4->ifa_local; + -+ printk("wifi_mac_send_arp_req, ipv4:%08x\n", ipv4); ++ pr_debug("wifi_mac_send_arp_req, ipv4:%08x\n", ipv4); + for (i = 1; i < 15; ++i) { + skb = os_skb_alloc(pkt_len + 64 + HI_TXDESC_DATAOFFSET); + if (skb == NULL) { @@ -112361,7 +114305,7 @@ index 000000000000..787bcf1e6bee + return 1; +} + -+int wifi_mac_send_udp_pkt(struct wlan_net_vif *wnet_vif) { ++static int wifi_mac_send_udp_pkt(struct wlan_net_vif *wnet_vif) { + struct sk_buff *skb = NULL; + struct ether_header *eh = NULL; + wifi_ip_header *ip_hdr = NULL; @@ -112455,7 +114399,7 @@ index 000000000000..787bcf1e6bee + memset(&ipv4, 0, sizeof(ipv4)); + ipv4 = ifa_v4->ifa_local; + -+ printk("wifi_mac_set_arp_rsp rx, ipv4:%08x\n", ipv4); ++ pr_debug("wifi_mac_set_arp_rsp rx, ipv4:%08x\n", ipv4); + for (i = 1; i < 3; ++i) { + skb = os_skb_alloc(pkt_len); + if (skb == NULL) { @@ -112547,12 +114491,137 @@ index 000000000000..787bcf1e6bee + wifi_mac_free_skb(skbbuf); + } +} ++ ++unsigned char * ++wifi_mac_add_wide_bandwidth_subie(unsigned char *frm,struct wifi_station *sta) ++{ ++ struct wlan_net_vif *wnet_vif = sta->sta_wnet_vif; ++ struct wifi_channel *switch_chan = &(wnet_vif->csa_target.switch_chan); ++ ++ if (WIFINET_IS_CHAN_ERR(switch_chan)) { ++ ERROR_DEBUG_OUT("NULL chan\n"); ++ return frm; ++ } ++ ++ *frm++ = WIFINET_ELEMID_WIDE_BAND_CHAN_SWITCH; ++ *frm++ = 3; ++ if (switch_chan->chan_bw == WIFINET_BWC_WIDTH80) { ++ *frm++ = 1; ++ } else { ++ /* for 40m bw*/ ++ *frm++ = 0; ++ } ++ *frm++ = wifi_mac_mhz2chan(switch_chan->chan_cfreq1); ++ *frm++ = 0; ++ return frm; ++} ++ ++unsigned char * ++wifi_mac_add_chansw_wrapper(unsigned char *frm,struct wifi_station *sta) ++{ ++ ++ *frm++ = WIFINET_ELEMID_CHAN_SWITCH_WRAP; ++ *frm++ = WIFINET_WIDEBANDCHANSW_BYTES; ++ return wifi_mac_add_wide_bandwidth_subie(frm,sta); ++} ++ ++unsigned char * ++wifi_mac_add_extended_chanswitch(unsigned char *frm,struct wifi_station *sta) ++{ ++ struct wifi_mac *wifimac = sta->sta_wmac; ++ struct wlan_net_vif *wnet_vif = sta->sta_wnet_vif; ++ struct wifi_channel *switch_chan = &(wnet_vif->csa_target.switch_chan); ++ ++ *frm++ = WIFINET_ELEMID_EXTCHANSWITCHANN; ++ *frm++ = 4; ++ *frm++ = 1; ++ *frm++ = switch_chan->global_operating_class; ++ *frm++ = wifimac->wm_doth_channel; ++ *frm++ = wifimac->wm_doth_tbtt; ++ return frm; ++} ++ ++unsigned char * ++wifi_mac_add_chanswitch(unsigned char *frm,struct wifi_station *sta) ++{ ++ struct wifi_mac *wifimac = sta->sta_wmac; ++ ++ *frm++ = WIFINET_ELEMID_CHANSWITCHANN; ++ *frm++ = 3; ++ *frm++ = 1; ++ *frm++ = wifimac->wm_doth_channel; ++ *frm++ = wifimac->wm_doth_tbtt; ++ return frm; ++} ++ ++void wifi_mac_csa_send_action_task(SYS_TYPE param1,SYS_TYPE param2, SYS_TYPE param3,SYS_TYPE param4,SYS_TYPE param5) ++{ ++ struct wifi_mac *wifimac = (struct wifi_mac *)param1; ++ struct wlan_net_vif *wnet_vif = (struct wlan_net_vif *)param2; ++ struct cfg80211_chan_def *chan_def_ptr = (struct cfg80211_chan_def *)param3; ++ struct cfg80211_chan_def chan_def = {0}; ++ ++ ++ memcpy(&chan_def, chan_def_ptr, sizeof(struct cfg80211_chan_def)); ++ wifi_mac_csa_send_action(wifimac, wnet_vif, wnet_vif->vm_mainsta, chan_def); ++ AML_OUTPUT("target_chan:%d, cur_chan:%d, wnet_vif->csa_count:%d\n", chan_def.chan->hw_value, wifimac->wm_curchan->chan_pri_num, wnet_vif->csa_count); ++ ++ return; ++} ++ ++int wifi_mac_csa_send_action(struct wifi_mac *wifimac, struct wlan_net_vif *wnet_vif, struct wifi_station *sta, struct cfg80211_chan_def chan_def) ++{ ++ struct sk_buff *skb; ++ int ret = 0; ++ struct wifi_mac_csa_data* csa_data_p = NULL; ++ ++ skb = wifi_mac_get_mgmt_frm(wifimac, MAX_ACTION_LEN); ++ if (skb == NULL) { ++ wnet_vif->vif_sts.sts_tx_no_buf++; ++ return -ENOMEM; ++ } ++ ++ csa_data_p = (struct wifi_mac_csa_data*)os_skb_put(skb, sizeof(struct wifi_mac_csa_data)); ++ csa_data_p->extend_csa.ac_header.ia_category = AML_CATEGORY_PUBLIC; ++ csa_data_p->extend_csa.ac_header.ia_action = WIFINET_ACT_PUBLIC_CSA; //ACT_PUBLIC_EXT_CHL_SWITCH ++ csa_data_p->extend_csa.csa.chan_switch_mode = CSA_BLOCK_TX; ++ csa_data_p->extend_csa.csa.new_operation_class = wifi_mac_get_operation_class(chan_def); ++ csa_data_p->extend_csa.csa.new_chan_num = ieee80211_frequency_to_channel(chan_def.chan->center_freq); ++ csa_data_p->extend_csa.csa.chan_switch_count = wnet_vif->csa_count--; ++ csa_data_p->csa_wrapper.ie = WLAN_EID_WIDE_BW_CHANNEL_SWITCH; ++ csa_data_p->csa_wrapper.len = 3; ++ /* New channel width */ ++ switch (chan_def.width) { ++ case NL80211_CHAN_WIDTH_80: ++ csa_data_p->csa_wrapper.info[0] = IEEE80211_VHT_CHANWIDTH_80MHZ; ++ break; ++ case NL80211_CHAN_WIDTH_160: ++ csa_data_p->csa_wrapper.info[0] = IEEE80211_VHT_CHANWIDTH_160MHZ; ++ break; ++ case NL80211_CHAN_WIDTH_80P80: ++ csa_data_p->csa_wrapper.info[0] = IEEE80211_VHT_CHANWIDTH_80P80MHZ; ++ break; ++ default: ++ csa_data_p->csa_wrapper.info[0] = IEEE80211_VHT_CHANWIDTH_USE_HT; ++ } ++ /* new center frequency segment 0 */ ++ csa_data_p->csa_wrapper.info[1] = ieee80211_frequency_to_channel(chan_def.center_freq1); ++ /* new center frequency segment 1 */ ++ if (chan_def.center_freq2) ++ csa_data_p->csa_wrapper.info[2] = ieee80211_frequency_to_channel(chan_def.center_freq2); ++ else ++ csa_data_p->csa_wrapper.info[2] = 0; ++ ++ wifi_mac_mgmt_csa_action_broadcast_output(sta, skb, WIFINET_FC0_SUBTYPE_ACTION); ++ ++ return ret; ++} diff --git a/drivers/net/wireless/w1/vmac/wifi_mac_xmit.h b/drivers/net/wireless/w1/vmac/wifi_mac_xmit.h new file mode 100644 -index 000000000000..aff1a9ae9a5b +index 0000000000000000000000000000000000000000..36e4ade75d5cc94060d30633832cd8eb25a91051 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_mac_xmit.h -@@ -0,0 +1,80 @@ +@@ -0,0 +1,100 @@ +#ifndef __VM_WIFI_OUTPUT_H__ +#define __VM_WIFI_OUTPUT_H__ + @@ -112579,6 +114648,21 @@ index 000000000000..aff1a9ae9a5b +#define EN_AP_MODE_IN_QUIET_IE (1) +#define DIS_AP_MODE_IN_QUIET_IE (0) + ++#define CSA_COUNT 1 ++#define CSA_BLOCK_TX 1 ++ ++struct wifi_mac_csa_wrapper{ ++ unsigned char ie; ++ unsigned char len; ++ unsigned char info[3]; ++} __packed; ++ ++struct wifi_mac_csa_data { ++ //struct ieee80211_header mac_header; ++ struct wifi_mac_action_csa_frame extend_csa; ++ struct wifi_mac_csa_wrapper csa_wrapper; ++} __packed; ++ +void wifi_mac_complete_wbuf(struct sk_buff * skbbuf, int errcode); +void wifi_mac_send_setup(struct wlan_net_vif *wnet_vif, struct wifi_station *sta, struct wifi_frame *wh, + int type, const unsigned char sa[WIFINET_ADDR_LEN], const unsigned char da[WIFINET_ADDR_LEN], const unsigned char bssid[WIFINET_ADDR_LEN]); @@ -112598,6 +114682,7 @@ index 000000000000..aff1a9ae9a5b +unsigned char *wifi_mac_add_rates(unsigned char *, const struct wifi_mac_rateset *); +unsigned char *wifi_mac_add_xrates(unsigned char *, const struct wifi_mac_rateset *); +unsigned char *wifi_mac_add_wpa(unsigned char *, struct wlan_net_vif *); ++unsigned char *wifi_mac_add_rsnxe(unsigned char *, struct wlan_net_vif *); +unsigned char *wifi_mac_add_erp(unsigned char *, struct wifi_mac *); +unsigned char *wifi_mac_add_wme_param(unsigned char *, struct wifi_mac_wme_state *, int uapsd_enable); +unsigned char *wifi_mac_add_country(unsigned char *, struct wifi_mac *); @@ -112631,11 +114716,15 @@ index 000000000000..aff1a9ae9a5b +int wifi_mac_send_mgmt(struct wifi_station *, int, void *); +int wifi_mac_udp_send_timeout_ex(void *arg); +void wifi_mac_check_opt_ie(struct wlan_net_vif *wnet_vif); -+ ++unsigned char *wifi_mac_add_chansw_wrapper(unsigned char *frm,struct wifi_station *sta); ++unsigned char *wifi_mac_add_extended_chanswitch(unsigned char *frm,struct wifi_station *sta); ++unsigned char *wifi_mac_add_chanswitch(unsigned char *frm,struct wifi_station *sta); ++int wifi_mac_csa_send_action(struct wifi_mac *wifimac, struct wlan_net_vif *wnet_vif, struct wifi_station *sta, struct cfg80211_chan_def chan_def); ++void wifi_mac_csa_send_action_task(SYS_TYPE param1,SYS_TYPE param2, SYS_TYPE param3,SYS_TYPE param4,SYS_TYPE param5); +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_phy.c b/drivers/net/wireless/w1/vmac/wifi_phy.c new file mode 100644 -index 000000000000..9a252d436b49 +index 0000000000000000000000000000000000000000..ad50b5e90c393a3fd65262ae5a1989079eec4216 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_phy.c @@ -0,0 +1,346 @@ @@ -112774,11 +114863,11 @@ index 000000000000..9a252d436b49 + avg_num[2] = reg[6]&0xffff; + avg_num[3] = (reg[6]>>16)&0xffff; + -+ printk("phy statistic(dec): \n"); -+ printk("0) CP1 detect:%8d avg:%8d min:%8d max:%8d \n", trig_num[0],avg_num[0],min_num[0],max_num[0]); -+ printk("1) L-SIG SNR :%8d avg:%8d min:%8d max:%8d \n", trig_num[1],avg_num[1],min_num[1],max_num[1]); -+ printk("2) data CRC err:%8d avg:%8d min:%8d max:%8d \n", trig_num[2],avg_num[2],min_num[2],max_num[2]); -+ printk("3) data CRC OK:%8d avg:%8d min:%8d max:%8d \n", trig_num[3],avg_num[3],min_num[3],max_num[3]); ++ pr_debug("phy statistic(dec): \n"); ++ pr_debug("0) CP1 detect:%8d avg:%8d min:%8d max:%8d \n", trig_num[0],avg_num[0],min_num[0],max_num[0]); ++ pr_debug("1) L-SIG SNR :%8d avg:%8d min:%8d max:%8d \n", trig_num[1],avg_num[1],min_num[1],max_num[1]); ++ pr_debug("2) data CRC err:%8d avg:%8d min:%8d max:%8d \n", trig_num[2],avg_num[2],min_num[2],max_num[2]); ++ pr_debug("3) data CRC OK:%8d avg:%8d min:%8d max:%8d \n", trig_num[3],avg_num[3],min_num[3],max_num[3]); + +} + @@ -112808,7 +114897,7 @@ index 000000000000..9a252d436b49 + { + v2 = hif->hif_ops.hi_read_word(RG_AGC_OB_CCA_COND01); + v4 = hif->hif_ops.hi_read_word(RG_AGC_OB_CCA_COND23); -+ printk("cca: ts 0x%x, ts_num %d, cond0 %d cond1 %d cond2 %d cond3 %d \n", ++ pr_debug("cca: ts 0x%x, ts_num %d, cond0 %d cond1 %d cond2 %d cond3 %d \n", + data3->cca_cond_ts, data3->cca_cond_ts_num, + v2 & 0xffff, (v2 >> 16) & 0xffff, v4 & 0xffff, (v4 >> 16 ) & 0xffff); + } @@ -112923,15 +115012,15 @@ index 000000000000..9a252d436b49 + + if (data != wifi_fpga_regtable[i].regdata) + { -+ printk("%s(%d): --Error------write reg=0x%x failed dataori=0x%x, dataread=0x%x\n", ++ pr_err("%s(%d): --Error------write reg=0x%x failed dataori=0x%x, dataread=0x%x\n", + __func__, __LINE__, + wifi_fpga_regtable[i].regaddr, wifi_fpga_regtable[i].regdata, data); + }else{ -+ printk("wifi reg 0x%04x data 0x%08x, ori_data=0x%08x\n", ++ pr_debug("wifi reg 0x%04x data 0x%08x, ori_data=0x%08x\n", + wifi_fpga_regtable[i].regaddr, wifi_fpga_regtable[i].regdata, ori_data); + } + } -+ printk("%s(%d)-- \n",__func__,__LINE__); ++ pr_debug("%s(%d)-- \n",__func__,__LINE__); +#endif //PHY_TEST_FUNC + +#ifdef HAL_FPGA_VER @@ -112960,7 +115049,7 @@ index 000000000000..9a252d436b49 + bt_prd = 7500 * 10;//us + bt_act = 1500 * 10;//us + bt_offset = 3500;//us -+ printk("%s(%d)\n",__func__,__LINE__); ++ pr_debug("%s(%d)\n",__func__,__LINE__); + + /*bt wifi switch no channel conf*/ + hif->hif_ops.hi_write_word(RG_COEX_RF_STABLE_CTRL, 0x03002000 | (testbus_num << 26)); @@ -112975,7 +115064,7 @@ index 000000000000..9a252d436b49 + hif->hif_ops.hi_write_word(RG_COEX_BT_OWNER_CTRL, 0x1001003f); + set_reg_fragment(RG_COEX_HS5W_MANUAL4,0,0,1); + -+ printk("%s(%d) BT priority=%d (%dus %dus %dus)--\n", ++ pr_debug("%s(%d) BT priority=%d (%dus %dus %dus)--\n", + __func__,__LINE__,hif->hif_ops.hi_read_word(RG_COEX_PRIORITY_M6), + bt_prd,bt_act,bt_offset); +} @@ -112987,7 +115076,7 @@ index 000000000000..9a252d436b49 +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_phy.h b/drivers/net/wireless/w1/vmac/wifi_phy.h new file mode 100644 -index 000000000000..939a1c5826fa +index 0000000000000000000000000000000000000000..939a1c5826faaf114450b722323017ff67adb44f --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_phy.h @@ -0,0 +1,15 @@ @@ -113008,7 +115097,7 @@ index 000000000000..939a1c5826fa +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_pkt_desc.c b/drivers/net/wireless/w1/vmac/wifi_pkt_desc.c new file mode 100644 -index 000000000000..6cdf99577005 +index 0000000000000000000000000000000000000000..1f60f9e7423ee8e646259b13f8512c374c95dc75 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_pkt_desc.c @@ -0,0 +1,92 @@ @@ -113041,7 +115130,7 @@ index 000000000000..6cdf99577005 + } + + if (free_page_hold_count >= 50) { -+ //printk("free_page_hold_count lager than 50, maybe we can reboot here\n"); ++ //pr_debug("free_page_hold_count lager than 50, maybe we can reboot here\n"); + } + return NULL; + } @@ -113061,7 +115150,7 @@ index 000000000000..6cdf99577005 + + wifimac = wifi_mac_get_mac_handle(); + -+ //printk("%s ptxdesc:%p, txinfo:%p\n", __func__, txinfo->ptxdesc, txinfo); ++ //pr_debug("%s ptxdesc:%p, txinfo:%p\n", __func__, txinfo->ptxdesc, txinfo); + INIT_LIST_HEAD(&tx_queue); + + if (txinfo->ptxdesc != NULL) { @@ -113106,10 +115195,10 @@ index 000000000000..6cdf99577005 +} diff --git a/drivers/net/wireless/w1/vmac/wifi_pkt_desc.h b/drivers/net/wireless/w1/vmac/wifi_pkt_desc.h new file mode 100644 -index 000000000000..1a647af6fa30 +index 0000000000000000000000000000000000000000..9adf11fd2d9e441835f30c2e36d7b69524c225ae --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_pkt_desc.h -@@ -0,0 +1,148 @@ +@@ -0,0 +1,151 @@ +#ifndef _WIFI_PKT_DESC_H_ +#define _WIFI_PKT_DESC_H_ + @@ -113131,7 +115220,7 @@ index 000000000000..1a647af6fa30 +enum tx_frame_flag +{ + TX_OTHER_FRAME = 0, -+ TX_P2P_GO_NEGO_REQ_GO_NEGO_CONF = 1, ++ TX_P2P_GO_NEGO_CONF = 1, + TX_P2P_OTHER_GO_NEGO_FRAME = 2, + TX_P2P_PRESENCE_REQ = 3, +#ifdef CTS_VERIFIER_GAS @@ -113145,6 +115234,8 @@ index 000000000000..1a647af6fa30 + TX_MGMT_DHCP = 10, + TX_MGMT_DEAUTH = 11, + TX_MGMT_DISASSOC = 12, ++ TX_MGMT_CSA_ACTION = 14, ++ TX_MGMT_DPP_STATUS = 15, +}; + +struct wifi_mac_pkt_info @@ -113175,7 +115266,7 @@ index 000000000000..1a647af6fa30 +struct drv_txdesc +{ + struct list_head txdesc_queue; // drv_priv->txdesc_bufptr->txdesc_queue : to queue all descriptors -+ //-> drv_tx_descr_1->..->drv_tx_descr_n. ++ //-> drv_tx_descr_1->..->drv_tx_descr_n. + struct drv_txdesc *txdesc_queue_last; + struct drv_txdesc *txdesc_queue_lastframe; + struct drv_txdesc *txdesc_queue_next; /* next subframe in the aggregate */ @@ -113244,7 +115335,8 @@ index 000000000000..1a647af6fa30 + b_hwtkipmic:1,/* need hw tkip mic add*/ + b_amsdu:1, + b_tcp_saved_flag:1, -+ b_pmf:1; ++ b_pmf:1, ++ b_dpp:1; +} ; + +#define TX_DESC_BUF_LOCK_INIT(_sc) spin_lock_init(&(_sc)->tx_desc_buf_lock) @@ -113260,76 +115352,76 @@ index 000000000000..1a647af6fa30 +#endif//_WIFI_PKT_DESC_H_ diff --git a/drivers/net/wireless/w1/vmac/wifi_pt_conf.h b/drivers/net/wireless/w1/vmac/wifi_pt_conf.h new file mode 100644 -index 000000000000..5b55e26f0c0f +index 0000000000000000000000000000000000000000..62c34128983e355381fcf290b707dc8429723c4c --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_pt_conf.h @@ -0,0 +1,59 @@ -+/***************************************************************************************** -+ * -+ * Copyright (C) Amlogic 2010-2014 -+ * -+ * Project: 11N 80211 driver layer Software -+ * -+ * Description: -+ * Storage to save configuration when init test for hal layer throughput -+ * Author : Boatman Yang(xuexing.yang@amlogic.com) -+ * -+ * Date: 20160901 -+ **************************************************************************************** -+ */ -+ -+#ifndef _DRV_HAL_THR_CONF_H -+#define _DRV_HAL_THR_CONF_H -+ -+#define STA1_VMAC0_KEY_LEN 32 -+ -+#define STA1_VMAC0_IBSS 0 -+ -+#define DP_SEC_KEY_AUTH 1 -+#define DP_SEC_KEY_SUPP 0 -+ -+#define TYPE_COMMON 1 //send common packet, mpdu->ack->mpdu->ack...,every mpdu need catch the channel -+#define TYPE_AMPDU 2 // send ampdu packet -+#define TYPE_AMSDU 3 // send amsdu packet -+#define TYPE_AMSDU_AMPDU 4 // send ampdu packet with amsdu packet included -+#define TYPE_COMMON_NOACK 5 //mpdu->mpdu->mpdu... -+#define TYPE_BURST_ACK 6 //send common packet until one txop used up -+#define TYPE_BURST_BA 7 -+#define TYPE_STOP_TX 8 -+ -+#define TYPE_MANAGE 0 -+/*The following 1 item modified by xman for hal thr test*/ -+#define STA1_VMAC0_SEND_TYPE TYPE_BURST_BA //TYPE_AMPDU, Boatman modify for hal lay throughput test. -+ -+#define STA1_VMAC0_SEND_RATE 0x85//0x85 for mcs5, 0x84 for mcs4,original 0x87 -+#define STA1_VMAC0_SEND_40M 0 //0: 20M,1:40,2:80M channel bandwidth -+ -+#define STA1_VMAC0_AGG_NUM 2 -+ -+#define WIFI_IS_GREENFIELD BIT(5) -+ -+#define STA2_VMAC1_SEND_TID_CTRL 1//use STA2_VMAC1_SEND_TID value ,if 0 ,send frame form all tid 0~7 -+#define STA2_VMAC1_SEND_TID 3 //send frame for which tid, 5 for video and 6 for voice -+#define STA2_VMAC1_SEND_FRAME_NUM 1500//send frame num for test,original 100, xman modified. -+#define STA2_VMAC1_RX_FRAME_DUMP 1//dump rx frame data -+#define STA1_VMAC0_SEND_LEN 1200//need 10~1500 -+ -+//reserve param 1 -+ -+#define STA2_VMAC1_TKIPMIC_HW 0//if tkip txmic key rx frame data -+#define STA2_TCPIP_CHECKSUM 0 -+ -+ -+ -+ ++/***************************************************************************************** ++ * ++ * Copyright (C) Amlogic 2010-2014 ++ * ++ * Project: 11N 80211 driver layer Software ++ * ++ * Description: ++ * Storage to save configuration when init test for hal layer throughput ++ * Author : Boatman Yang(xuexing.yang@amlogic.com) ++ * ++ * Date: 20160901 ++ **************************************************************************************** ++ */ ++ ++#ifndef _DRV_HAL_THR_CONF_H ++#define _DRV_HAL_THR_CONF_H ++ ++#define STA1_VMAC0_KEY_LEN 32 ++ ++#define STA1_VMAC0_IBSS 0 ++ ++#define DP_SEC_KEY_AUTH 1 ++#define DP_SEC_KEY_SUPP 0 ++ ++#define TYPE_COMMON 1 //send common packet, mpdu->ack->mpdu->ack...,every mpdu need catch the channel ++#define TYPE_AMPDU 2 // send ampdu packet ++#define TYPE_AMSDU 3 // send amsdu packet ++#define TYPE_AMSDU_AMPDU 4 // send ampdu packet with amsdu packet included ++#define TYPE_COMMON_NOACK 5 //mpdu->mpdu->mpdu... ++#define TYPE_BURST_ACK 6 //send common packet until one txop used up ++#define TYPE_BURST_BA 7 ++#define TYPE_STOP_TX 8 ++ ++#define TYPE_MANAGE 0 ++/*The following 1 item modified by xman for hal thr test*/ ++#define STA1_VMAC0_SEND_TYPE TYPE_BURST_BA //TYPE_AMPDU, Boatman modify for hal lay throughput test. ++ ++#define STA1_VMAC0_SEND_RATE 0x85//0x85 for mcs5, 0x84 for mcs4,original 0x87 ++#define STA1_VMAC0_SEND_40M 0 //0: 20M,1:40,2:80M channel bandwidth ++ ++#define STA1_VMAC0_AGG_NUM 2 ++ ++#define WIFI_IS_GREENFIELD BIT(5) ++ ++#define STA2_VMAC1_SEND_TID_CTRL 1//use STA2_VMAC1_SEND_TID value ,if 0 ,send frame form all tid 0~7 ++#define STA2_VMAC1_SEND_TID 3 //send frame for which tid, 5 for video and 6 for voice ++#define STA2_VMAC1_SEND_FRAME_NUM 1500//send frame num for test,original 100, xman modified. ++#define STA2_VMAC1_RX_FRAME_DUMP 1//dump rx frame data ++#define STA1_VMAC0_SEND_LEN 1200//need 10~1500 ++ ++//reserve param 1 ++ ++#define STA2_VMAC1_TKIPMIC_HW 0//if tkip txmic key rx frame data ++#define STA2_TCPIP_CHECKSUM 0 ++ ++ ++ ++ +#endif \ No newline at end of file diff --git a/drivers/net/wireless/w1/vmac/wifi_pt_if.c b/drivers/net/wireless/w1/vmac/wifi_pt_if.c new file mode 100644 -index 000000000000..f0881ef6d47e +index 0000000000000000000000000000000000000000..fd61d0526aee176675c7f5acc85f46019fa824bf --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_pt_if.c -@@ -0,0 +1,361 @@ +@@ -0,0 +1,367 @@ +/***************************************************************************************** + * + * Copyright (C) Amlogic 2010-2014 @@ -113352,98 +115444,99 @@ index 000000000000..f0881ef6d47e +static void *our_txpriv_pool_buffer[HI_TXPRIVD_NUM_ALL_TID + 1]; +unsigned char our_txpriv_descriptors_buffer[DRIVER_TXPRIV_DESC_LEN]; + -+int send_frame_num =0; ++int send_frame_num = 0; +int recv_frame_num = 0; + -+void Do_make_amsdu_header(struct _WIFI_htframe *htframe,unsigned char *buffer, int len) ++static void Do_make_amsdu_header(struct _WIFI_htframe *htframe,unsigned char *buffer, int len) +{ + unsigned char tmp[1000]; + unsigned short msdulen = len; + -+ ///buffer is body, len is bodylen ++ /* buffer is body, len is bodylen */ + + htframe->QosCtrl[0] |= BIT(7); + memcpy(tmp,buffer,len); + memcpy(buffer,htframe->Address1,6); + memcpy(buffer+6,htframe->Address2,6); + WRITE_16B(buffer+12,msdulen); -+ //memcpy(buffer+12,&msdulen,2); ++ /* memcpy(buffer+12,&msdulen,2); */ + memcpy(buffer+14,tmp,len); +} + -+ -+void Driver_intr_tx_handle(void *drv_priv, -+ struct txdonestatus *tx_done_status, SYS_TYPE callback, unsigned char queue_id) ++void Driver_intr_tx_handle(void *drv_priv, struct txdonestatus *tx_done_status, ++ SYS_TYPE callback, unsigned char queue_id) +{ + unsigned char *buffer; + -+ buffer = (unsigned char*)(unsigned int*)OS_DMAA2DDRddress((void *)(unsigned long)callback); -+ //Here,do not need destroy it now, ++ buffer = (unsigned char*)(unsigned int *)OS_DMAA2DDRddress((void *)(unsigned long)callback); ++ /* Here,do not need destroy it now. */ + if (buffer != NULL) + //TxBuffer_Destroy(buffer); + + send_frame_num++; + -+ if((send_frame_num>STA2_VMAC1_SEND_FRAME_NUM) && (STA2_VMAC1_SEND_FRAME_NUM != 99999)){ -+ //printk("send complete> %d status %d \n",status, STA2_VMAC1_SEND_FRAME_NUM); -+ //Test_Done(1); ++ if ((send_frame_num > STA2_VMAC1_SEND_FRAME_NUM) && (STA2_VMAC1_SEND_FRAME_NUM != 99999)) { ++ /* pr_debug("send complete> %d status %d \n",status, STA2_VMAC1_SEND_FRAME_NUM); */ ++ /* Test_Done(1); */ + } -+ // -+ ///if one frame send fail ,end test -+ // ++ /* ++ * if one frame send fail ,end test ++ */ + if (tx_done_status->txstatus != TX_DESCRIPTOR_STATUS_SUCCESS) { -+ //printk("send complete status %d \n",status); -+ //Test_Done(0); ++ /* pr_debug("send complete status %d \n",status); */ ++ /* Test_Done(0); */ + } +} + -+void Driver_mic_error_event(void *drv_priv, -+ const void *wh,unsigned char *sa,unsigned char vmac_id) ++void Driver_mic_error_event(void *drv_priv, const void *wh, unsigned char *sa, ++ unsigned char vmac_id) +{ + DBG_HAL_THR_ENTER(); + DBG_HAL_THR_EXIT(); +} + -+void Driver_intr_rx_handle(void *drv_prv,struct sk_buff *skb, unsigned char Rssi, unsigned char RxRate, -+ unsigned char bw, unsigned char channel, unsigned char aggr, unsigned char wnet_vif_id,unsigned char keyid) ++void Driver_intr_rx_handle(void *drv_prv, struct sk_buff *skb, unsigned char Rssi, ++ unsigned char RxRate, unsigned char bw, unsigned char channel, ++ unsigned char aggr, unsigned char wnet_vif_id, unsigned char keyid) +{ + recv_frame_num++; + -+ Net_Receive( (unsigned char*)os_skb_data(skb), os_skb_get_pktlen(skb), Rssi); ++ Net_Receive((unsigned char*)os_skb_data(skb), os_skb_get_pktlen(skb), Rssi); + os_skb_free(skb); + return; +} + -+void Driver_intr_dtim_send(void *dev,unsigned char vid) ++void Driver_intr_dtim_send(void *dev, unsigned char vid) +{ + DBG_HAL_THR_ENTER(); + DBG_HAL_THR_EXIT(); +} + -+void Driver_intr_bcn_send(void *dev,unsigned char vid) ++void Driver_intr_bcn_send(void *dev, unsigned char vid) +{ + DBG_HAL_THR_ENTER(); + DBG_HAL_THR_EXIT(); +} -+void Driver_intr_ba_recv(void *dev,unsigned char vid) ++ ++void Driver_intr_ba_recv(void *dev, unsigned char vid) +{ + DBG_HAL_THR_ENTER(); + DBG_HAL_THR_EXIT(); +} + -+void drv_intr_bt_info_change(void * dpriv, unsigned char wnet_vif_id,unsigned char bt_lk_change) ++void drv_intr_bt_info_change(void* dpriv, unsigned char wnet_vif_id, unsigned char bt_lk_change) +{ + DBG_HAL_THR_ENTER(); + DBG_HAL_THR_EXIT(); +} + +int Do_HI_AGG_TxPriv_TYPE_AMSDU(struct _HI_TxPrivDescripter_chain* HI_TxPriv[], -+ unsigned char* skbptr[],int length[],int packetNum) ++ unsigned char* skbptr[], int length[], int packetNum) +{ + int i; -+ int headerlength,total = 0; ++ int headerlength, total; + struct _WIFI_htframe * htframe; -+ int msdulen =0; ++ int msdulen = 0; + unsigned char **buffer; + + htframe = (struct _WIFI_htframe *)os_skb_data((struct sk_buff *)skbptr[0]);//? not right. please change it @@ -113455,40 +115548,44 @@ index 000000000000..f0881ef6d47e +#if STA2_VMAC1_TKIPMIC_HW + if(i != packetNum-1) + { -+ length[i] -= 8;//tkip mic ++ length[i] -= 8;/* tkip mic */ + } -+#endif //STA2_VMAC1_TKIPMIC_HW -+ //printk("length[%d]= %d \n ",i,length[i]); ++#endif /* STA2_VMAC1_TKIPMIC_HW */ ++ /* pr_debug("length[%d]= %d \n ",i,length[i]); */ + + buffer = &os_skb_data((struct sk_buff *)skbptr[i]); + -+ Do_make_amsdu_header(htframe, *(unsigned char **)((unsigned long)buffer + i) + headerlength, length[i] - headerlength); -+ msdulen = ALIGN(length[i] - headerlength +14,4); ++ Do_make_amsdu_header(htframe, *(unsigned char **)((unsigned long)buffer + i) + headerlength, ++ length[i] - headerlength); ++ msdulen = ALIGN(length[i] - headerlength + 14, 4); + total += msdulen; -+ memcpy(os_skb_data((struct sk_buff *)skbptr[0]) + total, *(unsigned char **)((unsigned long)buffer + i) + headerlength, msdulen); ++ memcpy(os_skb_data((struct sk_buff *)skbptr[0]) + total, ++ *(unsigned char **)((unsigned long)buffer + i) + headerlength, ++ msdulen); + } ++ + length[0] = total; -+ Do_HI_AGG_TxPriv_TYPE_AMPDU(HI_TxPriv,skbptr,length,1); ++ Do_HI_AGG_TxPriv_TYPE_AMPDU(HI_TxPriv, skbptr, length, 1); ++ + return 1; +} + -+ -+void Do_HI_AGG_TxPriv_TYPE_AMPDU( -+ struct _HI_TxPrivDescripter_chain* HI_TxPriv[], -+ unsigned char* skbptr[],int length[],int packetNum) ++void Do_HI_AGG_TxPriv_TYPE_AMPDU(struct _HI_TxPrivDescripter_chain* HI_TxPriv[], ++ unsigned char* skbptr[], int length[], int packetNum) +{ -+ int i=0; -+ unsigned char FLAG=0; -+ unsigned short headerlength; -+ struct _WIFI_htframe * htframe; -+ unsigned int frame_control ; -+ unsigned int datalen =0; -+ unsigned char *buffer; ++ int i; + + for (i = 0; i < packetNum; i ++) + { ++ unsigned int datalen; ++ unsigned short headerlength; ++ unsigned char FLAG; ++ struct _WIFI_htframe *htframe; ++ unsigned char *buffer; ++ unsigned int frame_control; ++ + buffer = os_skb_data((struct sk_buff *)skbptr[i]); -+ frame_control = *(unsigned int*)buffer; ++ frame_control = *(unsigned int *)buffer; + headerlength = MacFrame_GetHeaderSize(frame_control); + htframe = (struct _WIFI_htframe *)buffer; + datalen = length[i]; @@ -113506,53 +115603,48 @@ index 000000000000..f0881ef6d47e + } + HI_TxPriv[i]->HI_TxPriv.DMAADDR = (SYS_TYPE)skbptr[i]; + HI_TxPriv[i]->HI_TxPriv.DDRADDR = (unsigned long)buffer; -+ //printk("HI_TxPriv.DDRADDR %p length=0x%x\n",buffer[i], length[i]); ++ /* pr_debug("HI_TxPriv.DDRADDR %p length=0x%x\n",buffer[i], length[i]); */ + HI_TxPriv[i]->HI_TxPriv.DMALEN = length[i]; -+ HI_TxPriv[i]->HI_TxPriv.MPDULEN = length[i]; ++ HI_TxPriv[i]->HI_TxPriv.MPDULEN = length[i]; + HI_TxPriv[i]->HI_TxPriv.Delimiter = 0; -+ ASSERT(HI_TxPriv[i]->HI_TxPriv.DMALEN >0); -+ HI_TxPriv[i]->HI_TxPriv.Flag= FLAG; -+ HI_TxPriv[i]->HI_TxPriv.Seqnum = (*(unsigned short *)htframe->SeqCtrl)>>4; -+ HI_TxPriv[i]->HI_TxPriv.HTC =*((unsigned short *)htframe->HtCtrl); ++ ASSERT(HI_TxPriv[i]->HI_TxPriv.DMALEN > 0); ++ HI_TxPriv[i]->HI_TxPriv.Flag = FLAG; ++ HI_TxPriv[i]->HI_TxPriv.Seqnum = (*(unsigned short *)htframe->SeqCtrl) >> 4; ++ HI_TxPriv[i]->HI_TxPriv.HTC = *((unsigned short *)htframe->HtCtrl); + HI_TxPriv[i]->HI_TxPriv.FrameControl = htframe->FrameCtrl; -+ //PRINT("htframe->FrameCtrl %x,fc %x \n",htframe->FrameCtrl,frame_control); ++ /* PRINT("htframe->FrameCtrl %x,fc %x \n",htframe->FrameCtrl,frame_control); */ + HI_TxPriv[i]->HI_TxPriv.TX_STATUS = TX_DESCRIPTOR_STATUS_NEW; -+ HI_TxPriv[i]->HI_TxPriv.ShortRetryNum =0; -+ HI_TxPriv[i]->HI_TxPriv.LongRetryNum =0; -+ HI_TxPriv[i]->HI_TxPriv.ACKRSSI =0; -+ HI_TxPriv[i]->HI_TxPriv.TimeStmp =0; ++ HI_TxPriv[i]->HI_TxPriv.ShortRetryNum = 0; ++ HI_TxPriv[i]->HI_TxPriv.LongRetryNum = 0; ++ HI_TxPriv[i]->HI_TxPriv.ACKRSSI = 0; ++ HI_TxPriv[i]->HI_TxPriv.TimeStmp = 0; + HI_TxPriv[i]->HI_TxPriv.hostreserve = (unsigned long)OS_DDR2DMAAddress((unsigned int*)buffer); + #ifdef UNO_B2B_SUPPORT + HI_TxPriv[i]->HI_TxPriv.PrivDmaAddr = (unsigned long)OS_DDR2DMAAddress(&HI_TxPriv[i]->HI_TxPriv); + #endif + HI_TxPriv[i]->buffer = buffer; -+ //OS_DCACHE_WRITE_TO_DEV((unsigned int*)buffer[i],length[i]); ++ /* OS_DCACHE_WRITE_TO_DEV((unsigned int*)buffer[i],length[i]); */ + } +} + + -+void Do_HI_AGG_TxPriv_TYPE_COMMO( -+ struct _HI_TxPrivDescripter_chain* HI_TxPriv, -+ unsigned char* skbptr, -+ int length,int packetNum) ++void Do_HI_AGG_TxPriv_TYPE_COMMO(struct _HI_TxPrivDescripter_chain* HI_TxPriv, ++ unsigned char* skbptr, int length,int packetNum) +{ -+ //int i=0; -+ unsigned char FLAG=0; ++ unsigned char FLAG; + unsigned short headerlength; -+ struct _WIFI_htframe * htframe; -+ unsigned int frame_control ; -+ unsigned int datalen =0; -+ //int privnum = 0; ++ struct _WIFI_htframe *htframe; ++ unsigned int frame_control; ++ unsigned int datalen = 0; + unsigned char *buffer = os_skb_data((struct sk_buff *)skbptr); + + DBG_HAL_THR_ENTER(); + + frame_control = *(unsigned int*)buffer; -+ headerlength = MacFrame_GetHeaderSize( frame_control ); ++ headerlength = MacFrame_GetHeaderSize(frame_control); + htframe = (struct _WIFI_htframe *)buffer; + datalen = length; -+ FLAG = 0; -+ FLAG |= THR_WIFI_MORE_AGG; ++ FLAG = THR_WIFI_MORE_AGG; + FLAG |= THR_WIFI_FIRST_BUFFER; + FLAG &= ~THR_WIFI_MORE_BUFFER; + FLAG &= ~THR_WIFI_MORE_AGG; @@ -113560,31 +115652,34 @@ index 000000000000..f0881ef6d47e + HI_TxPriv->HI_TxPriv.DMAADDR = (SYS_TYPE)skbptr; + HI_TxPriv->HI_TxPriv.DDRADDR = (unsigned long)buffer; + HI_TxPriv->HI_TxPriv.DMALEN = length; -+ HI_TxPriv->HI_TxPriv.MPDULEN = length; ++ HI_TxPriv->HI_TxPriv.MPDULEN = length; + HI_TxPriv->HI_TxPriv.Delimiter = 0; -+ HI_TxPriv->HI_TxPriv.Flag= FLAG; -+ HI_TxPriv->HI_TxPriv.Seqnum = (*(unsigned short *)htframe->SeqCtrl)>>4; -+ HI_TxPriv->HI_TxPriv.HTC =*((unsigned short *)htframe->HtCtrl); ++ HI_TxPriv->HI_TxPriv.Flag = FLAG; ++ HI_TxPriv->HI_TxPriv.Seqnum = (*(unsigned short *)htframe->SeqCtrl) >> 4; ++ HI_TxPriv->HI_TxPriv.HTC = *((unsigned short *)htframe->HtCtrl); + HI_TxPriv->HI_TxPriv.FrameControl = htframe->FrameCtrl; -+ //PRINT("htframe->FrameCtrl %x,fc %x \n",htframe->FrameCtrl,frame_control); -+ HI_TxPriv->HI_TxPriv.TX_STATUS = 0;//TX_DESCRIPTOR_STATUS_NEW -+ HI_TxPriv->HI_TxPriv.ShortRetryNum =0; -+ HI_TxPriv->HI_TxPriv.LongRetryNum =0; -+ HI_TxPriv->HI_TxPriv.ACKRSSI =0; -+ HI_TxPriv->HI_TxPriv.TimeStmp =0; ++ /* PRINT("htframe->FrameCtrl %x,fc %x \n",htframe->FrameCtrl,frame_control); */ ++ HI_TxPriv->HI_TxPriv.TX_STATUS = 0; /*TX_DESCRIPTOR_STATUS_NEW */ ++ HI_TxPriv->HI_TxPriv.ShortRetryNum = 0; ++ HI_TxPriv->HI_TxPriv.LongRetryNum = 0; ++ HI_TxPriv->HI_TxPriv.ACKRSSI = 0; ++ HI_TxPriv->HI_TxPriv.TimeStmp = 0; + HI_TxPriv->HI_TxPriv.hostreserve = (unsigned long)THR_OS_DDR2DMAAddress((unsigned int*)buffer); + HI_TxPriv->buffer = buffer; + + DBG_HAL_THR_EXIT(); +} + -+ +struct _HI_TxPrivDescripter_chain * Driver_GetTxPriv(void) +{ -+ struct _HI_TxPrivDescripter_chain *HI_TxPrivDp = ( struct _HI_TxPrivDescripter_chain* )Pool_GetBlock( &our_txpriv_pool ); ++ struct _HI_TxPrivDescripter_chain *HI_TxPrivDp; ++ ++ HI_TxPrivDp = (struct _HI_TxPrivDescripter_chain*)Pool_GetBlock(&our_txpriv_pool); + if (!HI_TxPrivDp) + return 0; -+ memset(HI_TxPrivDp,0,sizeof(struct _HI_TxPrivDescripter_chain ));// ++ ++ memset(HI_TxPrivDp, 0, sizeof(struct _HI_TxPrivDescripter_chain)); ++ + return HI_TxPrivDp; +} + @@ -113606,10 +115701,10 @@ index 000000000000..f0881ef6d47e + "driverTxPriv"); +} + -+void Driver_FreeAGG(struct _HI_AGG_TxDescripter_chain * HI_AGG_TxDp) ++void Driver_FreeAGG(struct _HI_AGG_TxDescripter_chain *HI_AGG_TxDp) +{ + DBG_HAL_THR_ENTER(); -+ //OS_DEL_HEAD(HI_AGG_TxDp->workList); ++ /* OS_DEL_HEAD(HI_AGG_TxDp->workList); */ + new_list_del(&HI_AGG_TxDp->workList,&HI_AGG_TxDp->workList); + FREE(HI_AGG_TxDp,"getagg"); + HI_AGG_TxDp = NULL; @@ -113617,14 +115712,13 @@ index 000000000000..f0881ef6d47e +} + +extern struct hal_layer_ops *FiOpt2Driver; -+unsigned char Driver_FillAgg(struct _HI_AGG_TxDescripter_chain * HI_AGG_TxDp) ++unsigned char Driver_FillAgg(struct _HI_AGG_TxDescripter_chain *HI_AGG_TxDp) +{ + int i = 0; + struct thr_list_head *head; + struct _HI_TxPrivDescripter_chain *HI_TxPrivDp; + struct sk_buff *Hi_Agg_Txd_Is_Over = NULL; -+ -+ struct hal_private *hal_priv = hal_get_priv(); ++ struct hal_private *hal_priv = hal_get_priv(); + + DBG_HAL_THR_ENTER(); + @@ -113635,20 +115729,22 @@ index 000000000000..f0881ef6d47e + + if (i == 0) { + Hi_Agg_Txd_Is_Over = FiOpt2Driver->hal_fill_agg_start(&HI_AGG_TxDp->HI_AGG_TxD,&HI_TxPrivDp->HI_TxPriv); -+ if(Hi_Agg_Txd_Is_Over == NULL){ ++ if (Hi_Agg_Txd_Is_Over == NULL) { + AML_TXLOCK_UNLOCK(); -+ goto AGGFREE; ++ goto AGGFREE; + } -+ Pool_PutBlock(&our_txpriv_pool, (void *)HI_TxPrivDp ); -+ } -+ else { ++ ++ Pool_PutBlock(&our_txpriv_pool, (void *)HI_TxPrivDp); ++ } else { + Hi_Agg_Txd_Is_Over = FiOpt2Driver->hal_fill_priv(&HI_TxPrivDp->HI_TxPriv,HI_AGG_TxDp->HI_AGG_TxD.TID); + if (Hi_Agg_Txd_Is_Over == NULL){ + AML_TXLOCK_UNLOCK(); -+ goto AGGFREE; ++ goto AGGFREE; + } -+ Pool_PutBlock(&our_txpriv_pool, (void *)HI_TxPrivDp ); ++ ++ Pool_PutBlock(&our_txpriv_pool, (void *)HI_TxPrivDp); + } ++ + i++; + } + AML_TXLOCK_UNLOCK(); @@ -113657,14 +115753,16 @@ index 000000000000..f0881ef6d47e +AGGFREE: + Driver_FreeAGG(HI_AGG_TxDp); + DBG_HAL_THR_EXIT(); ++ + return 0; +} + -+ -+struct _HI_AGG_TxDescripter_chain * Driver_GetAGG(void) ++struct _HI_AGG_TxDescripter_chain *Driver_GetAGG(void) +{ -+ struct _HI_AGG_TxDescripter_chain *HI_AGG_TxDp = NULL; -+ HI_AGG_TxDp = (struct _HI_AGG_TxDescripter_chain *)ZMALLOC(sizeof(struct _HI_AGG_TxDescripter_chain ),"getagg", GFP_ATOMIC); ++ struct _HI_AGG_TxDescripter_chain *HI_AGG_TxDp; ++ ++ HI_AGG_TxDp = (struct _HI_AGG_TxDescripter_chain *)ZMALLOC(sizeof(struct _HI_AGG_TxDescripter_chain), ++ "getagg", GFP_ATOMIC); + + if (!HI_AGG_TxDp) + return NULL; @@ -113672,28 +115770,28 @@ index 000000000000..f0881ef6d47e + return HI_AGG_TxDp; +} + -+void Driver_ListInit(struct _HI_AGG_TxDescripter_chain *HI_AGG_TxDp ) ++void Driver_ListInit(struct _HI_AGG_TxDescripter_chain *HI_AGG_TxDp) +{ -+ OS_LIST_INIT( &HI_AGG_TxDp->workList ); ++ OS_LIST_INIT(&HI_AGG_TxDp->workList); +} + +int Driver_IsTxPrivEnough(int num) +{ + if (our_txpriv_pool.min_count > num) + { -+ //printk("---xman debug: the min_count is :%d.\n",our_txpriv_pool.min_count); ++ /* pr_debug("---xman debug: the min_count is :%d.\n",our_txpriv_pool.min_count); */ + return 1; + } + else + { -+ printk("---xman debug: the min_count is :%d.\n",our_txpriv_pool.min_count); ++ pr_debug("---xman debug: the min_count is :%d.\n",our_txpriv_pool.min_count); + return 0; + } +} + diff --git a/drivers/net/wireless/w1/vmac/wifi_pt_if.h b/drivers/net/wireless/w1/vmac/wifi_pt_if.h new file mode 100644 -index 000000000000..d01048477177 +index 0000000000000000000000000000000000000000..a917f6913ab40b0e3b8a43e6375852ff2b8fcc9a --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_pt_if.h @@ -0,0 +1,470 @@ @@ -114161,7 +116259,7 @@ index 000000000000..d01048477177 +void Driver_intr_tx_handle(void * drv_priv,struct txdonestatus* tx_done_status,SYS_TYPE callback, unsigned char queue_id); +void Driver_ListInit(struct _HI_AGG_TxDescripter_chain *HI_AGG_TxDp ); +struct _HI_TxPrivDescripter_chain * Driver_GetTxPriv(void); -+int Do_HI_AGG_TxPriv_TYPE_AMSDU(struct _HI_TxPrivDescripter_chain* HI_TxPriv[],unsigned char* buffer[],int length[],int packetNum); ++int Do_HI_AGG_TxPriv_TYPE_AMSDU(struct _HI_TxPrivDescripter_chain* HI_TxPriv[],unsigned char* skbptr[],int length[],int packetNum); +void Do_HI_AGG_TxPriv_TYPE_AMPDU(struct _HI_TxPrivDescripter_chain* HI_TxPriv[],unsigned char* buffer[],int length[],int packetNum); +void Do_HI_AGG_TxPriv_TYPE_COMMO(struct _HI_TxPrivDescripter_chain* HI_TxPriv,unsigned char* buffer,int length,int packetNum); +void Driver_CreatTxPriv(void); @@ -114169,10 +116267,10 @@ index 000000000000..d01048477177 +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_pt_init.c b/drivers/net/wireless/w1/vmac/wifi_pt_init.c new file mode 100644 -index 000000000000..dd3d05a2eb4d +index 0000000000000000000000000000000000000000..ff04efc2b368a31c7c5db3d0015189d4556f2e1a --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_pt_init.c -@@ -0,0 +1,1041 @@ +@@ -0,0 +1,1040 @@ +/* + **************************************************************************************** + * @@ -114187,6 +116285,7 @@ index 000000000000..dd3d05a2eb4d + * Date: 20160901 + **************************************************************************************** + */ ++#include +#include "wifi_mac_com.h" +#include "wifi_pt_init.h" +#include "wifi_pt_network.h" @@ -114269,7 +116368,7 @@ index 000000000000..dd3d05a2eb4d + + + -+unsigned char Queue_HasObject( struct _Queue* my, void* object ) ++static unsigned char Queue_HasObject( struct _Queue* my, void* object ) +{ + void** start = my->start; + void** end = my->end; @@ -114286,7 +116385,7 @@ index 000000000000..dd3d05a2eb4d + + + -+unsigned char Queue_IsFull( struct _Queue* my ) ++static unsigned char Queue_IsFull( struct _Queue* my ) +{ + void** front = my->front; + void** back = my->back; @@ -114337,7 +116436,7 @@ index 000000000000..dd3d05a2eb4d + +#if 1 + -+void TxDescriptor_Destroy( struct _TxDescriptor* my ) ++static void TxDescriptor_Destroy( struct _TxDescriptor* my ) +{ + + DBG_HAL_THR_ENTER(); @@ -114395,7 +116494,7 @@ index 000000000000..dd3d05a2eb4d + WIFI_11N_MCS0 +}; + -+void thr_list_add(struct thr_list_head *new_head, ++static void thr_list_add(struct thr_list_head *new_head, + struct thr_list_head *prev, + struct thr_list_head *next) +{ @@ -114405,7 +116504,7 @@ index 000000000000..dd3d05a2eb4d + prev->next = new_head; +} + -+struct _HI_TxPrivDescripter_chain* ++static struct _HI_TxPrivDescripter_chain* +Do_HI_AGG_TxDP(struct _HI_AGG_TxDescripter_chain *HI_AGG_chain, + struct _HI_TxPrivDescripter_chain* HI_TxPriv[], + int length[],unsigned char TID, @@ -114464,7 +116563,7 @@ index 000000000000..dd3d05a2eb4d + ERROR_DEBUG_OUT("not support, bw in flag 0x%x\n", (HI_AGG_TxDP->FLAG >> 8) & 0x3); + } + -+ //printk("%s (%d) bw in flag 0x%x\n",__func__, __LINE__, (HI_AGG_TxDP->FLAG >> 8) & 0x3); ++ //pr_debug("%s (%d) bw in flag 0x%x\n",__func__, __LINE__, (HI_AGG_TxDP->FLAG >> 8) & 0x3); + + HI_AGG_TxDP->FLAG2 = TrcConfMib.dot11RDSupport ? TX_DESCRIPTER_RD_SUPPORT : 0; + HI_AGG_TxDP->FLAG2 |= TrcConfMib.dot11RDSupport ? TX_DESCRIPTER_HTC : 0; @@ -114515,7 +116614,7 @@ index 000000000000..dd3d05a2eb4d + for (i = 0; i< MpduNum-1; i++) { + HI_AGG_TxDP->AGGR_len += ALIGN(length[i]+exlen,4)+4+4+0; + HI_AGG_TxDP->aggr_page_num += howmanypage(length[i]+FW_TXDESC_DATAOFFSET, PAGE_LEN); -+ //printk("HI_AGG_TxDP->AGGR_len 0x%x ,length[%d] 0x%x\n",HI_AGG_TxDP->AGGR_len,i,length[i]); ++ //pr_debug("HI_AGG_TxDP->AGGR_len 0x%x ,length[%d] 0x%x\n",HI_AGG_TxDP->AGGR_len,i,length[i]); + } + + if (IS_VHT_RATE(HI_AGG_TxDP->CurrentRate)) { @@ -114527,7 +116626,7 @@ index 000000000000..dd3d05a2eb4d + } + + HI_AGG_TxDP->aggr_page_num += howmanypage(length[i]+FW_TXDESC_DATAOFFSET, PAGE_LEN); -+ //printk("current vht rate 0x%x\n",HI_AGG_TxDP->CurrentRate); ++ //pr_debug("current vht rate 0x%x\n",HI_AGG_TxDP->CurrentRate); + } + else { + HI_AGG_TxDP->AGGR_len += exlen; @@ -114541,10 +116640,10 @@ index 000000000000..dd3d05a2eb4d + HI_TxPriv[i]->HI_TxPriv.MPDULEN -= DP_SEC_TKIP_MIC_LEN; + } + } -+ // printk("HI_AGG_TxDP->AGGR_len %x ,MPDULEN %x\n",HI_AGG_TxDP->AGGR_len,HI_TxPriv[0]->HI_TxPriv.MPDULEN); -+ // printk("---xman debug---: Before OS_ADD_TAIL, HI_TxPrivNum: %d.\n",HI_TxPrivNum); ++ // pr_debug("HI_AGG_TxDP->AGGR_len %x ,MPDULEN %x\n",HI_AGG_TxDP->AGGR_len,HI_TxPriv[0]->HI_TxPriv.MPDULEN); ++ // pr_debug("---xman debug---: Before OS_ADD_TAIL, HI_TxPrivNum: %d.\n",HI_TxPrivNum); + for (i = 0; i < HI_TxPrivNum ; i ++) { -+ // printk(" Do_HI_AGG_TxDP +HI_TxPriv =%p DMAADDR =%x\n",HI_TxPriv[i],HI_TxPriv[i]->HI_TxPriv.DMAADDR); ++ // pr_debug(" Do_HI_AGG_TxDP +HI_TxPriv =%p DMAADDR =%x\n",HI_TxPriv[i],HI_TxPriv[i]->HI_TxPriv.DMAADDR); + //OS_ADD_TAIL(&HI_TxPriv[i]->workList,&HI_AGG_chain->workList); + thr_list_add(&HI_TxPriv[i]->workList,(&HI_AGG_chain->workList)->prev,&HI_AGG_chain->workList); + } @@ -114553,7 +116652,7 @@ index 000000000000..dd3d05a2eb4d + return HI_TxPriv[0]; +} + -+int HostSendTYPE_AMSDU(unsigned char* buffer[],int length[], ++static int HostSendTYPE_AMSDU(unsigned char* buffer[],int length[], + int packetNum,unsigned char TID,unsigned short FLAG) +{ + //int i; @@ -114579,7 +116678,7 @@ index 000000000000..dd3d05a2eb4d + +} + -+int HostSendTYPE_AMPDU(unsigned char* buffer[],int length[], ++static int HostSendTYPE_AMPDU(unsigned char* buffer[],int length[], + int packetNum,unsigned char TID,unsigned short FLAG) +{ + int i; @@ -114587,7 +116686,7 @@ index 000000000000..dd3d05a2eb4d + struct _HI_TxPrivDescripter_chain **HI_TxPriv = NULL; + int privnum = packetNum; + if (!Driver_IsTxPrivEnough(packetNum)) { -+ printk("warning: no tx desc\n"); ++ pr_warn("warning: no tx desc\n"); + return 0; + } + Hi_TxAgg = Driver_GetAGG(); @@ -114610,7 +116709,7 @@ index 000000000000..dd3d05a2eb4d + return 0; +} + -+int HostSendTYPE_COMMO(unsigned char* buffer,int length,unsigned char TID,unsigned short FLAG) ++static int HostSendTYPE_COMMO(unsigned char* buffer,int length,unsigned char TID,unsigned short FLAG) +{ + + int privnum =1; @@ -114639,7 +116738,7 @@ index 000000000000..dd3d05a2eb4d +} +#endif + -+void HostSendDataPacket(int type, int packetNum, unsigned short FLAG) ++static void HostSendDataPacket(int type, int packetNum, unsigned short FLAG) +{ + int i; + struct _TxDescriptor* descriptor = NULL; @@ -114669,7 +116768,7 @@ index 000000000000..dd3d05a2eb4d + } + packetNum = i; + if (packetNum ==0) { -+ printk(" HostSendDataPacket packetNum=0\n"); ++ pr_debug(" HostSendDataPacket packetNum=0\n"); + goto end; + } + } @@ -114684,7 +116783,7 @@ index 000000000000..dd3d05a2eb4d + goto end; + //if (TrcConfMib.dot11FragmentationThreshold < descriptor1->len ) + // FLAG = WIFI_IS_FRAGMENT; -+ //printk("---b2b debug ---Common type before HostSendTYPE_COMMO, FLAG is : %d\n", FLAG); ++ //pr_debug("---b2b debug ---Common type before HostSendTYPE_COMMO, FLAG is : %d\n", FLAG); + HostSendTYPE_COMMO((unsigned char *)descriptor1->skb,descriptor1->len, descriptor1->Tid,FLAG); + TxDescriptor_Destroy(descriptor1); + break; @@ -114696,17 +116795,17 @@ index 000000000000..dd3d05a2eb4d + goto end; + //if (TrcConfMib.dot11FragmentationThreshold < descriptor1->len ) + // FLAG = WIFI_IS_FRAGMENT; -+ //printk("---b2b debug ---Common type before HostSendTYPE_COMMO, FLAG is : %d\n", FLAG); ++ //pr_debug("---b2b debug ---Common type before HostSendTYPE_COMMO, FLAG is : %d\n", FLAG); + HostSendTYPE_COMMO((unsigned char *)descriptor1->skb,descriptor1->len, descriptor1->Tid,FLAG); + TxDescriptor_Destroy(descriptor1); + break; + case TYPE_AMPDU: -+ //printk("----length: %d, packetNum: %d, TID: %d, FLAG: %d.\n",*length,packetNum, TID, FLAG); ++ //pr_debug("----length: %d, packetNum: %d, TID: %d, FLAG: %d.\n",*length,packetNum, TID, FLAG); + FLAG |= WIFI_IS_AGGR; + HostSendTYPE_AMPDU( buffer,length,packetNum, TID, FLAG); + break; + case TYPE_AMSDU: -+ printk("\n---xman debug---,length:%d, packetNum:%d, TID: %d, FLAG:%x.\n",*length,packetNum, TID, FLAG); ++ pr_debug("\n---xman debug---,length:%d, packetNum:%d, TID: %d, FLAG:%x.\n",*length,packetNum, TID, FLAG); + HostSendTYPE_AMSDU(buffer,length,packetNum, TID, FLAG); + break; + case TYPE_AMSDU_AMPDU: @@ -114748,7 +116847,7 @@ index 000000000000..dd3d05a2eb4d + } + + hal_full = 0; -+ printk("pt max tx: %d\n", gB2BTestCasePacket.send_frame_num); ++ pr_debug("pt max tx: %d\n", gB2BTestCasePacket.send_frame_num); + + TrcConfMib.tid = STA2_VMAC1_SEND_TID; + loop = 0; @@ -114757,14 +116856,14 @@ index 000000000000..dd3d05a2eb4d + if(gB2BTestCasePacket.send_frame_num > loop) + { + if (FiOpt2Driver->hal_get_priv_cnt == NULL) { -+ printk("===>>> %s ==>> hal_get_priv_cnt is NULL\n", __func__); ++ pr_err("===>>> %s ==>> hal_get_priv_cnt is NULL\n", __func__); + break; + } + if ((FiOpt2Driver->hal_get_priv_cnt(TrcConfMib.tid) < TrcConfMib.testmpdunum ))//+1 + { + if(hal_full == 0) + { -+ printk("%s %d: hal buffer full.\n", __func__, __LINE__); ++ pr_warn("%s %d: hal buffer full.\n", __func__, __LINE__); + hal_full = 1; + } + msleep(10); @@ -114772,16 +116871,16 @@ index 000000000000..dd3d05a2eb4d + } + + HostSendDataPacket(TrcConfMib.testtype,TrcConfMib.testmpdunum,TrcConfMib.testflag); -+ //printk("test flag = 0x%x bw =0x%x\n", TrcConfMib.testflag, (TrcConfMib.testflag >>WIFI_CHANNEL_BW_OFFSET) & 0x3 ); ++ //pr_debug("test flag = 0x%x bw =0x%x\n", TrcConfMib.testflag, (TrcConfMib.testflag >>WIFI_CHANNEL_BW_OFFSET) & 0x3 ); + loop++; + }//tx max pkt + else + { -+ printk("**** pt send pkt %d done ***", loop); ++ pr_debug("**** pt send pkt %d done ***", loop); + break; // quite into to thread to sleep + } + }// start/stop loop -+ printk("**** stop : when pt send pkt %d done ***", loop); ++ pr_debug("**** stop : when pt send pkt %d done ***", loop); + }// thread loop + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0) @@ -114789,7 +116888,7 @@ index 000000000000..dd3d05a2eb4d +#else + kthread_complete_and_exit(&b2b_tx_struct.b2b_thread_cmplt, 0); +#endif -+ printk("**** exit b2b_tx_thread_function ***"); ++ pr_debug("**** exit b2b_tx_thread_function ***"); + return 0; +} + @@ -114867,13 +116966,13 @@ index 000000000000..dd3d05a2eb4d + // 8 + case TYPE_STOP_TX: + TrcConfMib.testtype=TYPE_STOP_TX; -+ printk("send stop!\n"); ++ pr_debug("send stop!\n"); + break; + default: + break; + } + -+ printk("%s(%d) test flag =0x%x, test type = 0x%x\n", ++ pr_debug("%s(%d) test flag =0x%x, test type = 0x%x\n", + __func__, __LINE__, TrcConfMib.testflag, usrtesttype); + + DBG_HAL_THR_EXIT(); @@ -114891,7 +116990,7 @@ index 000000000000..dd3d05a2eb4d + wait_for_completion(&b2b_tx_struct.b2b_thread_cmplt); + b2b_tx_struct.b2b_tx_thread =NULL; + /* -+ printk("======> Remove b2b tx thread\n"); ++ pr_debug("======> Remove b2b tx thread\n"); + b2b_tx_struct.b2b_tx_quit = 1; + kthread_stop(b2b_tx_struct.b2b_tx_thread); + b2b_tx_struct.b2b_tx_thread = NULL; @@ -114919,7 +117018,7 @@ index 000000000000..dd3d05a2eb4d + { + if ( TrcConfMib.the_bssid[i] != TrcConfMib.the_mac_address[i] ) + { -+ printk("\n\nb2b_compare_local_and_bssid: NOT the same\n"); ++ pr_err("\n\nb2b_compare_local_and_bssid: NOT the same\n"); + ret = 1; + break; + } @@ -114934,7 +117033,7 @@ index 000000000000..dd3d05a2eb4d + DBG_HAL_THR_ENTER(); + + -+ printk("********* b2b debug enter driver_open ***************\n"); ++ pr_debug("********* b2b debug enter driver_open ***************\n"); + + callback.mic_error_event = Driver_mic_error_event; + callback.intr_tx_handle = Driver_intr_tx_handle; @@ -114986,7 +117085,7 @@ index 000000000000..dd3d05a2eb4d + + if ( 0 != b2b_compare_local_and_bssid() )//Tx side + { -+ printk("\n---B2B debug---: Tx side\n"); ++ pr_debug("\n---B2B debug---: Tx side\n"); + TrcConfMib.dot11EncryptType = gB2BTestCasePacket.encryp_type; + TrcConfMib.dot11EncryptLen = STA1_VMAC0_KEY_LEN; + if(STA1_VMAC0_IBSS) @@ -115010,7 +117109,7 @@ index 000000000000..dd3d05a2eb4d + } + else + { -+ printk("\n---B2B debug---: Rx side\n"); ++ pr_debug("\n---B2B debug---: Rx side\n"); + TrcConfMib.dot11EncryptType = gB2BTestCasePacket.encryp_type; + TrcConfMib.dot11EncryptLen = STA1_VMAC0_KEY_LEN; + if(STA1_VMAC0_IBSS) @@ -115039,18 +117138,18 @@ index 000000000000..dd3d05a2eb4d + + if(BSS_BW_80M == 2) + { -+ printk("\n---B2B debug---: 80M bw\n"); ++ pr_debug("\n---B2B debug---: 80M bw\n"); + //amlhal_SetChannel_BW(SW_CBW80,SW_COFF_U30M); + } + else if(BSS_BW_40M == 1) + { + //amlhal_SetChannel_BW(SW_CBW40,SW_HI_CH_OFF_20U); -+ printk("\n---B2B debug---: 40M bw\n"); ++ pr_debug("\n---B2B debug---: 40M bw\n"); + //PhySetChanSupportType(WIFINET_BW_40PLUS); + } + else + { -+ printk("\n---B2B debug---: 20M bw\n"); ++ pr_debug("\n---B2B debug---: 20M bw\n"); + //amlhal_SetChannel_BW(SW_CBW20,SW_HI_CH_OFF_20); + //PhySetChanSupportType(WIFINET_BW_20); + } @@ -115066,11 +117165,11 @@ index 000000000000..dd3d05a2eb4d + + if (IS_ERR(b2b_tx_struct.b2b_tx_thread)) { + b2b_tx_struct.b2b_tx_thread = NULL; -+ printk(KERN_INFO "B2B: Create b2b tx task failed!\n"); ++ pr_info("B2B: Create b2b tx task failed!\n"); + goto b2b_tx_thread_create_fail; + } + else { -+ printk(KERN_INFO "B2B: Create b2b tx task success!\n"); ++ pr_info("B2B: Create b2b tx task success!\n"); + return; + } + @@ -115100,7 +117199,6 @@ index 000000000000..dd3d05a2eb4d + // + // Enforce (at least) word alignment of all the blocks + // -+ int i; + ASSERT( ( unsigned int )(unsigned long)buffer % 4 == 0 + && size % 4 == 0 && count != 0 ); + @@ -115111,8 +117209,7 @@ index 000000000000..dd3d05a2eb4d + my->size = size; + my->max_count = count; + my->min_count = count; -+ for ( i =0; i<16; i++) -+ my->name[i] = name[i]; ++ strscpy(my->name, name, sizeof(my->name)); + // + // Important: queue_buffer[] size must be at least count + 1 + // @@ -115138,7 +117235,7 @@ index 000000000000..dd3d05a2eb4d + return skb; +} + -+void TxDescriptor_Initialize(void) ++static void TxDescriptor_Initialize(void) +{ + Pool_Create(&our_tx_descriptor_pool, + TX_DESCRIPTOR_SIZE, @@ -115216,7 +117313,7 @@ index 000000000000..dd3d05a2eb4d + diff --git a/drivers/net/wireless/w1/vmac/wifi_pt_init.h b/drivers/net/wireless/w1/vmac/wifi_pt_init.h new file mode 100644 -index 000000000000..e0d6133dc052 +index 0000000000000000000000000000000000000000..96c1ea6056fd0a811a9b7de2d68aa2d6f45bd942 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_pt_init.h @@ -0,0 +1,249 @@ @@ -115253,7 +117350,7 @@ index 000000000000..e0d6133dc052 +#include +#include +#include -+#include /* printk() */ ++#include /* pr_debug() */ +#include +#include +#include @@ -115471,7 +117568,7 @@ index 000000000000..e0d6133dc052 +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_pt_network.c b/drivers/net/wireless/w1/vmac/wifi_pt_network.c new file mode 100644 -index 000000000000..82d76ab3e315 +index 0000000000000000000000000000000000000000..2954c66a96c889250277e32a38859dff9e12390a --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_pt_network.c @@ -0,0 +1,508 @@ @@ -115557,7 +117654,7 @@ index 000000000000..82d76ab3e315 + return MacFrame_IsType(frame_control,FRAME_TYPE_MANAGEMENT); +} + -+void B2B_Net_RequestTransmit(struct sk_buff *skb, ++static void B2B_Net_RequestTransmit(struct sk_buff *skb, + unsigned short len,unsigned short Tid) +{ + struct _TxDescriptor *descriptor = TxDescriptor_Create(); @@ -115679,12 +117776,12 @@ index 000000000000..82d76ab3e315 +} + + -+void RcvFrameTestSeq(unsigned char *packet,unsigned char tid) ++static void RcvFrameTestSeq(unsigned char *packet,unsigned char tid) +{ + return; +} + -+void RcvFrame(unsigned char *packet,int length,unsigned char tid) ++static void RcvFrame(unsigned char *packet,int length,unsigned char tid) +{ + int i; + static unsigned char sendPacketseq[MAX_TID]= {0};//256 is one test peri. @@ -115698,7 +117795,7 @@ index 000000000000..82d76ab3e315 + sendPacketseq[tid] ++; + return; +} -+void Net_Send( unsigned char type, unsigned char* input) ++static void Net_Send( unsigned char type, unsigned char* input) +{ + unsigned int header_length; + struct sk_buff *skb = TxBuffer_Alloc(); @@ -115774,8 +117871,8 @@ index 000000000000..82d76ab3e315 + B2b_Net_WriteSimcheck( cursor,gB2BTestCasePacket.pkt_length,TrcConfMib.tid ); + cursor = buffer + gB2BTestCasePacket.pkt_length; + -+ //printk( "---aml debug--: pkt len: %d.\n",pkt_len); -+ //dump_memory_internel(buffer,48); ++ //pr_debug( "---aml debug--: pkt len: %d.\n",pkt_len); ++ //dump_memory_internal(buffer,48); + B2B_Net_RequestTransmit(skb,cursor-buffer,TrcConfMib.tid); + //Net_RequestTransmit(buffer,pkt_len,TrcConfMib.tid); + @@ -115783,7 +117880,7 @@ index 000000000000..82d76ab3e315 + else { + my_network.tx_pool_error_count++; + ASSERT(0); -+ printk( "NULL TxBuffer_Create\n" ); ++ pr_debug( "NULL TxBuffer_Create\n" ); + } + DBG_HAL_THR_EXIT(); +} @@ -115799,7 +117896,7 @@ index 000000000000..82d76ab3e315 + //DBG_ENTER(); + // + // if(STA2_VMAC1_RX_FRAME_DUMP) -+ // dump_memory_internel(packet,len); ++ // dump_memory_internal(packet,len); + + frame_control = *(unsigned int*)packet; + headerlength = MacFrame_GetHeaderSize( frame_control ); @@ -115972,11 +118069,11 @@ index 000000000000..82d76ab3e315 + DBG_HAL_THR_ENTER(); + if ( usrtesttype > 11 || usrtesttype < 1 ) + { -+ printk("Warning: Not supported testing type.\n"); ++ pr_warn("Warning: Not supported testing type.\n"); + return; + } + -+ printk("b2b_init: test type 0x%08x\n", usrtesttype); ++ pr_debug("b2b_init: test type 0x%08x\n", usrtesttype); + + Task_Schedule(usrtesttype); + @@ -115985,7 +118082,7 @@ index 000000000000..82d76ab3e315 + diff --git a/drivers/net/wireless/w1/vmac/wifi_pt_network.h b/drivers/net/wireless/w1/vmac/wifi_pt_network.h new file mode 100644 -index 000000000000..4b68997223b7 +index 0000000000000000000000000000000000000000..4b68997223b74d7af85c20288fa9fba80196c70b --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_pt_network.h @@ -0,0 +1,90 @@ @@ -116081,7 +118178,7 @@ index 000000000000..4b68997223b7 +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_rate_ctrl.c b/drivers/net/wireless/w1/vmac/wifi_rate_ctrl.c new file mode 100644 -index 000000000000..e111d077cbed +index 0000000000000000000000000000000000000000..e111d077cbed3db9e3fef4fd6f140b35426515b6 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_rate_ctrl.c @@ -0,0 +1,78 @@ @@ -116165,7 +118262,7 @@ index 000000000000..e111d077cbed + diff --git a/drivers/net/wireless/w1/vmac/wifi_rate_ctrl.h b/drivers/net/wireless/w1/vmac/wifi_rate_ctrl.h new file mode 100644 -index 000000000000..e870072a8a74 +index 0000000000000000000000000000000000000000..e870072a8a74acc9d8d8e9d3658655ddf6d0026c --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_rate_ctrl.h @@ -0,0 +1,127 @@ @@ -116298,7 +118395,7 @@ index 000000000000..e870072a8a74 +#endif /* _DRV__RATE_SAMPLE_H */ diff --git a/drivers/net/wireless/w1/vmac/wifi_sdio.c b/drivers/net/wireless/w1/vmac/wifi_sdio.c new file mode 100644 -index 000000000000..f4ce6a176552 +index 0000000000000000000000000000000000000000..b7e48a1ddb4de1c5f22139975ba6bb52ee76aa51 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_sdio.c @@ -0,0 +1,2137 @@ @@ -116413,7 +118510,7 @@ index 000000000000..f4ce6a176552 +#if defined(DBG_PRINT_COST_TIME) + getnstimeofday(&now); + -+ printk("[sdio byte]: len=1 cost=%lds %luus\n", ++ pr_debug("[sdio byte]: len=1 cost=%lds %luus\n", + now.tv_sec-before.tv_sec, now.tv_nsec/1000 - before.tv_nsec/1000); +#endif /* End of DBG_PRINT_COST_TIME */ + @@ -116476,7 +118573,7 @@ index 000000000000..f4ce6a176552 +#if defined(DBG_PRINT_COST_TIME) + getnstimeofday(&now); + -+ printk("[sdio buffer]: len=%d cost=%lds %luus\n", ++ pr_debug("[sdio buffer]: len=%d cost=%lds %luus\n", + nbytes, now.tv_sec-before.tv_sec, now.tv_nsec/1000 - before.tv_nsec/1000); +#endif /* End of DBG_PRINT_COST_TIME */ + @@ -116866,7 +118963,7 @@ index 000000000000..f4ce6a176552 + sdio_release_host(func); + + if (mmc_cmd.error || mmc_dat.error) { -+ printk("ERROR CMD53 %s cmd_error = %d data_error=%d\n", ++ pr_err("ERROR CMD53 %s cmd_error = %d data_error=%d\n", + write ? "write" : "read", mmc_cmd.error, mmc_dat.error); + ret = mmc_cmd.error; + } @@ -116879,7 +118976,7 @@ index 000000000000..f4ce6a176552 + struct hw_interface * hif = hif_get_hw_interface(); + struct amlw_hwif_sdio *hif_sdio = aml_sdio_priv(); + -+ printk("[sdio sg cleanup]: enter\n"); ++ pr_debug("[sdio sg cleanup]: enter\n"); + + ASSERT(hif != NULL); + ASSERT(hif_sdio != NULL); @@ -116892,7 +118989,7 @@ index 000000000000..f4ce6a176552 + /* empty the free list */ + FREE(hif_sdio->scat_req, "sdio_alloc_prep_scat_req"); + -+ printk("[sdio sg cleanup]: exit\n"); ++ pr_debug("[sdio sg cleanup]: exit\n"); + + return; +} @@ -117055,7 +119152,7 @@ index 000000000000..f4ce6a176552 + return SDIOH_API_RC_FAIL; + } + memcpy(kmalloc_buf, buf, len); -+ //printk("%s, buf:%p\n", __func__, kmalloc_buf); ++ //pr_debug("%s, buf:%p\n", __func__, kmalloc_buf); + + result = _aml_sdio_request_buffer(func_num, incr_addr, SDIO_WRITE, addr, kmalloc_buf, len); + @@ -117138,7 +119235,7 @@ index 000000000000..f4ce6a176552 +#endif//HAL_FPGA_VER +#endif//SDIO_BUILD_IN + -+void aml_sdio_scat_complete (struct amlw_hif_scatter_req * scat_req) ++static void aml_sdio_scat_complete (struct amlw_hif_scatter_req * scat_req) +{ + int i; + struct hw_interface * hif = hif_get_hw_interface(); @@ -117233,7 +119330,7 @@ index 000000000000..f4ce6a176552 + sg_data_size = ALIGN(packet_len, blk_size); + if (sg_data_size > (max_req_size - ttl_len)) + { -+ printk(" setup scat-data: (%s): %d: sg_data_size %d, remain %d \n", ++ pr_debug(" setup scat-data: (%s): %d: sg_data_size %d, remain %d \n", + __func__, __LINE__, sg_data_size, max_req_size - ttl_len); + break; + } @@ -117267,14 +119364,14 @@ index 000000000000..f4ce6a176552 + } +#endif + /* -+ printk("setup scat-data: offset: %d: ttl: %d, datalen:%d\n", ++ pr_debug("setup scat-data: offset: %d: ttl: %d, datalen:%d\n", + pkt_offset, ttl_len, sg_data_size); + */ + } + + if ((ttl_len == 0) || (ttl_len % blk_size != 0)) + { -+ printk(" setup scat-data: (%s): %d: ttl_len %d \n", ++ pr_debug(" setup scat-data: (%s): %d: ttl_len %d \n", + __func__, __LINE__, ttl_len); + return result; + } @@ -117311,7 +119408,7 @@ index 000000000000..f4ce6a176552 + sdio_release_host(func); + + /* -+ printk("setup scat-data: (%s) ====addr: 0x%X, (blksz: %d, blocks: %d) , (ttl:%d,sg:%d,scat_count:%d,ttl_page:%d)====\n", ++ pr_debug("setup scat-data: (%s) ====addr: 0x%X, (blksz: %d, blocks: %d) , (ttl:%d,sg:%d,scat_count:%d,ttl_page:%d)====\n", + (scat_req->req & HIF_WRITE) ? "wr" : "rd", scat_req->addr, + mmc_dat.blksz, mmc_dat.blocks, ttl_len, + sg_count, scat_req->scat_count, ttl_page_num); @@ -117360,7 +119457,7 @@ index 000000000000..f4ce6a176552 + unsigned char reg = 1; + struct hw_interface* hif = hif_get_hw_interface(); + -+ printk("aml_sdio_reset \n"); ++ pr_debug("aml_sdio_reset \n"); + ASSERT(hif != NULL && hif->hif_ops.hi_bottom_write8 != NULL); + + hif->hif_ops.hi_bottom_write8(SDIO_FUNC0, SDIO_CCCR_IOABORT, reg); @@ -117372,17 +119469,17 @@ index 000000000000..f4ce6a176552 + unsigned int ck_reg = 0; + struct hw_interface* hif = hif_get_hw_interface(); + -+ printk("%s: b_gpio=%d \n",__FUNCTION__, b_gpio); ++ pr_debug("%s: b_gpio=%d \n",__FUNCTION__, b_gpio); + + if (b_gpio) + { + regdata= hif->hif_ops.hi_read8_func0(SDIO_CCCR_IEN); + -+ printk(" SDIO_CCCR_IEN=0x%x \n", regdata); ++ pr_debug(" SDIO_CCCR_IEN=0x%x \n", regdata); + regdata &= ~0x3; + + hif->hif_ops.hi_write8_func0(SDIO_CCCR_IEN,regdata); -+ printk(" SDIO CCCR IEN=0x%x \n", regdata); ++ pr_debug(" SDIO CCCR IEN=0x%x \n", regdata); + + regdata = hif->hif_ops.hi_read_word(RG_WIFI_IF_FW2HST_CLR); + @@ -117390,16 +119487,16 @@ index 000000000000..f4ce6a176552 + hif->hif_ops.hi_write_word(RG_WIFI_IF_FW2HST_CLR, regdata); + + ck_reg = hif->hif_ops.hi_read_word(RG_WIFI_IF_FW2HST_CLR); -+ printk("%s(%d) ck_reg 0x%x\n", __FUNCTION__, __LINE__, ck_reg); ++ pr_debug("%s(%d) ck_reg 0x%x\n", __FUNCTION__, __LINE__, ck_reg); + } + else + { + regdata= hif->hif_ops.hi_read8_func0(SDIO_CCCR_IEN); -+ printk(" SDIO_CCCR_IEN=0x%x \n", regdata); ++ pr_debug(" SDIO_CCCR_IEN=0x%x \n", regdata); + regdata |= 0x3; + + hif->hif_ops.hi_write8_func0(SDIO_CCCR_IEN,regdata); -+ printk(" SDIO_CCCR_IEN=0x%x \n", regdata); ++ pr_debug(" SDIO_CCCR_IEN=0x%x \n", regdata); + + regdata = hif->hif_ops.hi_read_word(RG_WIFI_IF_FW2HST_CLR); + regdata &= ~SDIO_FW2HOST_GPIO_EN; @@ -117433,7 +119530,7 @@ index 000000000000..f4ce6a176552 + + reg5c = hif->hif_ops.hi_read_word(RG_WIFI_IF_FW2HST_CLR); + -+ printk("%s(%d): -----------0x5C register=0x%x\n", __FUNCTION__, __LINE__, reg5c); ++ pr_debug("%s(%d): -----------0x5C register=0x%x\n", __FUNCTION__, __LINE__, reg5c); + reg5c |= BIT(31); + + hif->hif_ops.hi_write_word(RG_WIFI_IF_FW2HST_CLR, reg5c); @@ -117459,7 +119556,7 @@ index 000000000000..f4ce6a176552 + + //reg = hw_if->hif_ops.hi_read_word(RG_WIFI_IF_GPIO_IRQ_CNF); + -+ printk("SDIO GPIO IRQ CONFIG REG=0x%x\n",reg); ++ pr_debug("SDIO GPIO IRQ CONFIG REG=0x%x\n",reg); + + aml_sdio_irq_path(1); // 1: GPIO LINE PATH. 0: SDIO DATA LINE PATH + } @@ -117484,7 +119581,7 @@ index 000000000000..f4ce6a176552 +} + +#endif //USE_GPIO_IRQ -+void aml_sdio_interrupt(struct sdio_func * func) ++static void aml_sdio_interrupt(struct sdio_func * func) +{ + struct hal_private *hal_priv = hal_get_priv(); + @@ -117531,7 +119628,7 @@ index 000000000000..f4ce6a176552 + } +} + -+void aml_sdio_calibration(void) ++static void aml_sdio_calibration(void) +{ + struct hw_interface *hif = hif_get_hw_interface(); + int err; @@ -117558,10 +119655,10 @@ index 000000000000..f4ce6a176552 + if (err) { + //msleep(3000); + hif->hif_ops.hi_bottom_write8(SDIO_FUNC0, SDIO_CCCR_IOABORT, 0x1); -+ printk("%s error: i:%d, j:%d, k:%d, l:%d\n", __func__, i, j, k, l); ++ pr_err("%s error: i:%d, j:%d, k:%d, l:%d\n", __func__, i, j, k, l); + + } else { -+ printk("%s right, use this config: i:%d, j:%d, k:%d, l:%d\n", __func__, i, j, k, l); ++ pr_debug("%s right, use this config: i:%d, j:%d, k:%d, l:%d\n", __func__, i, j, k, l); + return; + } + } @@ -117615,12 +119712,12 @@ index 000000000000..f4ce6a176552 + switch (onoff) + { + case WLAN_POWER_OFF: -+ printk("%s: call customer specific GPIO to turn off WL_REG_ON\n", __FUNCTION__); ++ pr_debug("%s: call customer specific GPIO to turn off WL_REG_ON\n", __FUNCTION__); + break; + + case WLAN_POWER_ON: + platform_wifi_reset(); -+ printk("=========== WLAN placed in POWER ON ========\n"); ++ pr_debug("=========== WLAN placed in POWER ON ========\n"); + break; + } +} @@ -117652,7 +119749,7 @@ index 000000000000..f4ce6a176552 + struct hw_interface * hif = hif_get_hw_interface(); + + wifi_pmu_status = halpriv->hal_ops.hal_get_fw_ps_status(); -+ printk("%s wifi_pmu_status:0x%x\n", __func__, wifi_pmu_status); ++ pr_debug("%s wifi_pmu_status:0x%x\n", __func__, wifi_pmu_status); + + if (is_power_on) { + host_req_status = 0; @@ -117670,7 +119767,7 @@ index 000000000000..f4ce6a176552 + value_pmu_A22 = hif->hif_ops.hi_read_word(RG_PMU_A22); + value_pmu_A24 = hif->hif_ops.hi_read_word(RG_PMU_A24); + -+ printk("%s power on: before write A12=0x%x, A13=0x%x, A14=0x%x, A15=0x%x, A17=0x%x, A18=0x%x, A20=0x%x, A22=0x%x, A24=0x%x\n", ++ pr_debug("%s power on: before write A12=0x%x, A13=0x%x, A14=0x%x, A15=0x%x, A17=0x%x, A18=0x%x, A20=0x%x, A22=0x%x, A24=0x%x\n", + __func__, value_pmu_A12, value_pmu_A13, value_pmu_A14, value_pmu_A15,value_pmu_A17,value_pmu_A18,value_pmu_A20,value_pmu_A22,value_pmu_A24); + + // open bg ldo @@ -117715,10 +119812,10 @@ index 000000000000..f4ce6a176552 + msleep(20); + + wifi_pmu_status = halpriv->hal_ops.hal_get_fw_ps_status(); -+ printk("%s wifi_pmu_status:0x%x\n", __func__, wifi_pmu_status); ++ pr_debug("%s wifi_pmu_status:0x%x\n", __func__, wifi_pmu_status); + + while ((wifi_pmu_status & 0xF) != PMU_ACT_MODE) { -+ printk("%s wifi_pmu_status:0x%x\n", __func__, wifi_pmu_status); ++ pr_debug("%s wifi_pmu_status:0x%x\n", __func__, wifi_pmu_status); + wifi_pmu_status = halpriv->hal_ops.hal_get_fw_ps_status(); + } + @@ -117728,7 +119825,7 @@ index 000000000000..f4ce6a176552 + value_pmu_A20 = hif->hif_ops.hi_read_word(RG_PMU_A20); + value_pmu_A22 = hif->hif_ops.hi_read_word(RG_PMU_A22); + value_pmu_A24 = hif->hif_ops.hi_read_word(RG_PMU_A24); -+ printk("%s power on: after write A15=0x%x, A17=0x%x, A18=0x%x, A20=0x%x, A22=0x%x, A24=0x%x\n", ++ pr_debug("%s power on: after write A15=0x%x, A17=0x%x, A18=0x%x, A20=0x%x, A22=0x%x, A24=0x%x\n", + __func__, value_pmu_A15, value_pmu_A17,value_pmu_A18,value_pmu_A20,value_pmu_A22,value_pmu_A24); + + } else { @@ -117740,7 +119837,7 @@ index 000000000000..f4ce6a176552 + value_pmu_A22 = hif->hif_ops.hi_read_word(RG_PMU_A22); + value_pmu_A24 = hif->hif_ops.hi_read_word(RG_PMU_A24); + value_aon30 = hif->hif_ops.hi_read_word(RG_AON_A30); -+ printk("%s power off: before write A12=0x%x, A15=0x%x, A17=0x%x, A18=0x%x, A20=0x%x, A22=0x%x, A24=0x%x, AON30=0x%x\n", ++ pr_debug("%s power off: before write A12=0x%x, A15=0x%x, A17=0x%x, A18=0x%x, A20=0x%x, A22=0x%x, A24=0x%x, AON30=0x%x\n", + __func__, value_pmu_A12,value_pmu_A15,value_pmu_A17,value_pmu_A18,value_pmu_A20,value_pmu_A22,value_pmu_A24, value_aon30); + + // switch rf dig to dvdd09_ao @@ -117794,7 +119891,7 @@ index 000000000000..f4ce6a176552 + value_pmu_A24 = hif->hif_ops.hi_read_word(RG_PMU_A24); + value_aon30 = hif->hif_ops.hi_read_word(RG_AON_A30); + -+ printk("%s power off: after write A12=0x%x, A15=0x%x, A17=0x%x, A18=0x%x, A20=0x%x, A22=0x%x, A24=0x%x, AON30=0x%x\n", ++ pr_debug("%s power off: after write A12=0x%x, A15=0x%x, A17=0x%x, A18=0x%x, A20=0x%x, A22=0x%x, A24=0x%x, AON30=0x%x\n", + __func__, value_pmu_A12,value_pmu_A15,value_pmu_A17,value_pmu_A18,value_pmu_A20,value_pmu_A22, value_pmu_A24, value_aon30); + + hif->hif_ops.hi_write_word(RG_PMU_A22, 0x707); @@ -117819,11 +119916,11 @@ index 000000000000..f4ce6a176552 + struct hal_private * hal_priv = hal_get_priv(); + struct sdio_func *func; + -+ printk("SDIO_BUILD_IN %s\n", __func__); ++ pr_debug("SDIO_BUILD_IN %s\n", __func__); + aml_customer_gpio_wlan_ctrl(WLAN_POWER_ON); + + if (!w1_sdio_after_porbe) { -+ printk("sdio not probe, need set power \n"); ++ pr_debug("sdio not probe, need set power \n"); + set_usb_wifi_power(0); + msleep(100); + set_usb_wifi_power(1); @@ -117867,7 +119964,7 @@ index 000000000000..f4ce6a176552 + if ((hal_priv->hal_call_back != NULL) + &&(hal_priv->hal_call_back->dev_probe != NULL)) + { -+ printk("hal_priv->hal_call_back->dev_probe\n"); ++ pr_debug("hal_priv->hal_call_back->dev_probe\n"); + /*call driver probe to create vmac0 and vmac1 eventually*/ + ret = hal_priv->hal_call_back->dev_probe(); + if (ret < 0) @@ -117877,11 +119974,11 @@ index 000000000000..f4ce6a176552 + } + hal_priv->powersave_init_flag = 0; + -+ printk("%s(%d): sg ops init\n", __func__, __LINE__); ++ pr_debug("%s(%d): sg ops init\n", __func__, __LINE__); + hif->hif_ops.hi_enable_scat(); + + aml_sdio_enable_irq(SDIO_FUNC1); -+ printk("aml_sdio_probe-- ret %d\n", ret); ++ pr_debug("aml_sdio_probe-- ret %d\n", ret); + + if (aml_wifi_is_enable_rf_test()) { + mib_init(); @@ -117899,7 +119996,7 @@ index 000000000000..f4ce6a176552 +void aml_disable_wifi(void) +{ + wifi_sdio_access = 0; -+ printk("aml_disable_wifi start sdio access %d\n", wifi_sdio_access); ++ pr_debug("aml_disable_wifi start sdio access %d\n", wifi_sdio_access); + aml_sdio_disable_irq(SDIO_FUNC1); + config_pmu_reg(AML_W1_WIFI_POWER_OFF); + msleep(50); @@ -117911,14 +120008,14 @@ index 000000000000..f4ce6a176552 +{ + struct hal_private * hal_priv = hal_get_priv(); + -+ printk("aml_enable_wifi start\n"); ++ pr_debug("aml_enable_wifi start\n"); + aml_customer_gpio_wlan_ctrl(WLAN_POWER_ON); + + hal_recovery_init_priv(); + config_pmu_reg(AML_W1_WIFI_POWER_ON); + aml_sdio_enable_irq(SDIO_FUNC1); + wifi_sdio_access = 1; -+ printk("aml_enable_wifi start sdio access %d\n", wifi_sdio_access); ++ pr_debug("aml_enable_wifi start sdio access %d\n", wifi_sdio_access); + hal_fw_repair(); + + hal_priv->txcompletestatus->txdoneframecounter = 0; @@ -117926,7 +120023,7 @@ index 000000000000..f4ce6a176552 + hal_priv->txcompletestatus->txpagecounter = 0; + hal_priv->HalTxPageDoneCounter = 0; + -+ printk("aml_enable_wifi end\n"); ++ pr_debug("aml_enable_wifi end\n"); +} + + @@ -117973,7 +120070,7 @@ index 000000000000..f4ce6a176552 + } + + atomic_inc(&hal_priv->sdio_suspend_cnt); -+ //printk("%s:%d,wifi suspend %d, suspend cnt 0x%x, func num %d \n", __func__, __LINE__, ++ //pr_debug("%s:%d,wifi suspend %d, suspend cnt 0x%x, func num %d \n", __func__, __LINE__, + // hal_priv->hal_suspend_mode, atomic_read(&hal_priv->suspend_cnt) , func->num); + + /* we shall suspend all card for sdio. */ @@ -118022,7 +120119,7 @@ index 000000000000..f4ce6a176552 +// return -1; + + atomic_dec(&hal_priv->sdio_suspend_cnt); -+ //printk("%s:%d, func num %d, no resume 0x%x \n", __func__, __LINE__, ++ //pr_debug("%s:%d, func num %d, no resume 0x%x \n", __func__, __LINE__, + // func->num, atomic_read(&hal_priv->suspend_cnt)); + + return 0; @@ -118052,7 +120149,7 @@ index 000000000000..f4ce6a176552 + else + sdio_set_block_size(func, BLKSIZE); + -+ printk("%s(%d): func->num %d sdio block size=%d, \n", __func__, __LINE__, ++ pr_debug("%s(%d): func->num %d sdio block size=%d, \n", __func__, __LINE__, + func->num, func->cur_blksize); + + if (func->num == 1) @@ -118062,14 +120159,14 @@ index 000000000000..f4ce6a176552 + hwif_sdio->sdio_func_if[0] = &sdio_func_0; + } + hwif_sdio->sdio_func_if[func->num] = func; -+ printk("%s(%d): func->num %d sdio_func=%p, \n", __func__, __LINE__, ++ pr_debug("%s(%d): func->num %d sdio_func=%p, \n", __func__, __LINE__, + func->num, func); + + sdio_release_host(func); + sdio_set_drvdata(func, hwif_sdio); + if (func->num != FUNCNUM_SDIO_LAST) + { -+ printk("%s(%d):func_num=%d, lastfuncnum=%d\n", __func__, __LINE__, ++ pr_debug("%s(%d):func_num=%d, lastfuncnum=%d\n", __func__, __LINE__, + func->num, FUNCNUM_SDIO_LAST); + return 0; + } @@ -118093,7 +120190,7 @@ index 000000000000..f4ce6a176552 + if ((hal_priv->hal_call_back != NULL) + &&(hal_priv->hal_call_back->dev_probe != NULL)) + { -+ printk("hal_priv->hal_call_back->dev_probe\n"); ++ pr_debug("hal_priv->hal_call_back->dev_probe\n"); + /*call driver probe to create vmac0 and vmac1 eventually*/ + ret = hal_priv->hal_call_back->dev_probe(); + if (ret < 0) @@ -118103,11 +120200,11 @@ index 000000000000..f4ce6a176552 + } + hal_priv->powersave_init_flag = 0; + -+ printk("%s(%d): sg ops init\n", __func__, __LINE__); ++ pr_debug("%s(%d): sg ops init\n", __func__, __LINE__); + hif->hif_ops.hi_enable_scat(); + + aml_sdio_enable_irq(SDIO_FUNC1); -+ printk("aml_sdio_probe-- ret %d\n", ret); ++ pr_debug("aml_sdio_probe-- ret %d\n", ret); + + + if (aml_wifi_is_enable_rf_test()) { @@ -118137,9 +120234,9 @@ index 000000000000..f4ce6a176552 + return ; + } + -+ printk("\n==========================================\n"); -+ printk("aml_sdio_remove++ func->num =%d \n",func->num); -+ printk("==========================================\n"); ++ pr_debug("\n==========================================\n"); ++ pr_debug("aml_sdio_remove++ func->num =%d \n",func->num); ++ pr_debug("==========================================\n"); + aml_sdio_disable_irq(SDIO_FUNC1); + hal_priv->powersave_init_flag = 1; + hal_free(); @@ -118441,10 +120538,10 @@ index 000000000000..f4ce6a176552 +#endif /*end HAL_FPGA_VER */ diff --git a/drivers/net/wireless/w1/vmac/wifi_sdio.h b/drivers/net/wireless/w1/vmac/wifi_sdio.h new file mode 100644 -index 000000000000..a8883c97bdf4 +index 0000000000000000000000000000000000000000..3952753e7d76b78f7aaccd8ad5aae955c62a86e2 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_sdio.h -@@ -0,0 +1,194 @@ +@@ -0,0 +1,193 @@ +#ifndef AML_SDIO_H +#define AML_SDIO_H + @@ -118533,7 +120630,6 @@ index 000000000000..a8883c97bdf4 +#define SDIOH_API_RC_FAIL (0x01) +#define SDIOH_API_SUCCESS(status) (status == 0) + -+struct sdio_func *aml_priv_to_func(int func_n); + +int aml_sdio_bottom_write8(unsigned char func_num, int addr, unsigned char data); +unsigned char aml_sdio_bottom_read8(unsigned char func_num, int addr); @@ -118626,8 +120722,6 @@ index 000000000000..a8883c97bdf4 + extern unsigned char (*host_wake_w1_req)(void); + extern int (*host_suspend_req)(struct device* device); + extern int (*host_resume_req)(struct device* device); -+ extern void aml_wifi_sdio_power_lock(void); -+ extern void aml_wifi_sdio_power_unlock(void); + #define AML_W1_WIFI_POWER_ON 1 + #define AML_W1_WIFI_POWER_OFF 0 + @@ -118638,10 +120732,12 @@ index 000000000000..a8883c97bdf4 + int aml_sdio_pm_resume(struct device *device); +#endif + ++ struct sdio_func *aml_priv_to_func(int func_n); ++ +#endif //AML_SDIO_H diff --git a/drivers/net/wireless/w1/vmac/wifi_share_fifo.c b/drivers/net/wireless/w1/vmac/wifi_share_fifo.c new file mode 100644 -index 000000000000..d3d5eee1a007 +index 0000000000000000000000000000000000000000..b4f3bc8f7e5f8863a579412ac868edd6b8e892f5 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_share_fifo.c @@ -0,0 +1,517 @@ @@ -118690,7 +120786,7 @@ index 000000000000..d3d5eee1a007 +{ + struct _CO_SF_BLOCK_IDX *BlockOutIdxPtr; + BlockOutIdxPtr = &SharedFifoPtr->IdxTab[ BlockID ]; -+ printk("b%d I%d,O%d\n",BlockID,BlockOutIdxPtr->In,BlockOutIdxPtr->Out); ++ pr_debug("b%d I%d,O%d\n",BlockID,BlockOutIdxPtr->In,BlockOutIdxPtr->Out); +} + +void qfifo_mng_info_dump(struct _CO_SHARED_FIFO* const SharedFifoPtr) @@ -119164,7 +121260,7 @@ index 000000000000..d3d5eee1a007 +#endif diff --git a/drivers/net/wireless/w1/vmac/wifi_share_fifo.h b/drivers/net/wireless/w1/vmac/wifi_share_fifo.h new file mode 100644 -index 000000000000..8bb71efa847e +index 0000000000000000000000000000000000000000..8bb71efa847e7b6d180e838ac18b6abe63805b17 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_share_fifo.h @@ -0,0 +1,160 @@ @@ -119330,75 +121426,75 @@ index 000000000000..8bb71efa847e +#endif //CO_SHARED_FIFO_H diff --git a/drivers/net/wireless/w1/vmac/wifi_skbbuf.c b/drivers/net/wireless/w1/vmac/wifi_skbbuf.c new file mode 100644 -index 000000000000..cc91ac6543af +index 0000000000000000000000000000000000000000..5e9e3a9bcceba8e461c95b54031ed7ccc2d8f376 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_skbbuf.c @@ -0,0 +1,9 @@ -+#include "wifi_skbbuf.h" -+ -+#ifdef SKBBUF_DEBUG -+ -+int skb_alloc_time = 0; -+int skb_free_time = 0; -+ -+#endif -+ ++#include "wifi_skbbuf.h" ++ ++#ifdef SKBBUF_DEBUG ++ ++int skb_alloc_time = 0; ++int skb_free_time = 0; ++ ++#endif ++ diff --git a/drivers/net/wireless/w1/vmac/wifi_skbbuf.h b/drivers/net/wireless/w1/vmac/wifi_skbbuf.h new file mode 100644 -index 000000000000..5feb8e7975d2 +index 0000000000000000000000000000000000000000..cc41998d6292a707915e1b8855c5af9f2191f534 --- /dev/null +++ b/drivers/net/wireless/w1/vmac/wifi_skbbuf.h @@ -0,0 +1,50 @@ -+#ifndef _WIFI_SKBBUF_H_ -+#define _WIFI_SKBBUF_H_ -+ -+#include -+ -+//#define SKBBUF_DEBUG -+ -+#define OS_SKB_CB_MAXLEN (48)//kernel skb -> cb len = 48 -+#define os_skb_data(_skb) ((_skb)->data) -+#define os_skb_cb(_skb) ((_skb)->cb) -+#define os_skb_get_pktlen(_skb) ((_skb)->len) -+#define os_skb_get_tailroom(_skb) skb_tailroom(_skb) -+#define os_skb_get_priority(_skb) ((_skb)->priority) -+#define os_skb_set_priority(_skb, _p) ((_skb)->priority = (_p)) -+#define os_skb_hdrspace(_skb) skb_headroom(_skb) -+#define os_skb_next(_skb) ((_skb)->next) -+ -+#define os_skb_push(_skb, _len) skb_push(_skb, _len) -+#define os_skb_trim(_skb, _len) skb_trim(_skb,_len) -+#define os_skb_pull(_skb, _len) skb_pull(_skb, _len) -+#define os_skb_put(_skb, _len) skb_put(_skb, _len) -+ -+#ifdef SKBBUF_DEBUG -+extern int skb_alloc_time; -+extern int skb_free_time; -+ -+#define os_skb_count_alloc(skb) AML_OUTPUT("%s skb:%p, skb_alloc_time:%d\n", __func__, skb, skb_alloc_time++); -+#define os_skb_count_free(skb) AML_OUTPUT("%s skb:%p, skb_free_time:%d\n", __func__, skb, skb_free_time++); -+ -+#define os_skb_alloc(len) dev_alloc_skb(ALIGN(len, 4)); \ -+ AML_OUTPUT("%s skb:%p, skb_alloc_time:%d\n", __func__, skb, skb_alloc_time++); -+#define os_skb_copy(ori_skb, priority, skb) skb_copy(ori_skb, priority);\ -+ AML_OUTPUT("%s skb:%p, skb_alloc_time:%d\n", __func__, skb, skb_alloc_time++); -+#define os_skb_copy_expand(ori_skb, header_len, tail_len, priority, skb) skb_copy_expand(ori_skb, header_len, tail_len, priority);\ -+ AML_OUTPUT("%s skb:%p, skb_alloc_time:%d\n", __func__, skb, skb_alloc_time++); -+ -+#define os_skb_free(skb) consume_skb(skb);\ -+ AML_OUTPUT("%s skb:%p, skb_free_time:%d\n", __func__, skb, skb_free_time++); -+ -+#else -+ -+#define os_skb_count_alloc(skb) -+#define os_skb_count_free(skb) -+#define os_skb_alloc(_len) dev_alloc_skb(ALIGN(_len, 4)); -+#define os_skb_free(skbbuf) { consume_skb(skbbuf); skbbuf = NULL; } -+#define os_skb_copy(ori_skb, priority, skb) skb_copy(ori_skb, priority); -+#define os_skb_copy_expand(ori_skb, header_len, tail_len, priority, skb) skb_copy_expand(ori_skb, header_len, tail_len, priority); -+#endif -+ -+#endif//_WIFI_SKBBUF_H_ ++#ifndef _WIFI_SKBBUF_H_ ++#define _WIFI_SKBBUF_H_ ++ ++#include ++ ++//#define SKBBUF_DEBUG ++ ++#define OS_SKB_CB_MAXLEN (48)//kernel skb -> cb len = 48 ++#define os_skb_data(_skb) ((_skb)->data) ++#define os_skb_cb(_skb) ((_skb)->cb) ++#define os_skb_get_pktlen(_skb) ((_skb)->len) ++#define os_skb_get_tailroom(_skb) skb_tailroom(_skb) ++#define os_skb_get_priority(_skb) ((_skb)->priority) ++#define os_skb_set_priority(_skb, _p) ((_skb)->priority = (_p)) ++#define os_skb_hdrspace(_skb) skb_headroom(_skb) ++#define os_skb_next(_skb) ((_skb)->next) ++ ++#define os_skb_push(_skb, _len) skb_push(_skb, _len) ++#define os_skb_trim(_skb, _len) skb_trim(_skb,_len) ++#define os_skb_pull(_skb, _len) skb_pull(_skb, _len) ++#define os_skb_put(_skb, _len) skb_put(_skb, _len) ++ ++#ifdef SKBBUF_DEBUG ++extern int skb_alloc_time; ++extern int skb_free_time; ++ ++#define os_skb_count_alloc(skb) AML_OUTPUT("%s skb:%p, skb_alloc_time:%d\n", __func__, skb, skb_alloc_time++); ++#define os_skb_count_free(skb) AML_OUTPUT("%s skb:%p, skb_free_time:%d\n", __func__, skb, skb_free_time++); ++ ++#define os_skb_alloc(len) dev_alloc_skb(ALIGN(len, 4)); \ ++ AML_OUTPUT("%s skb:%p, skb_alloc_time:%d\n", __func__, skb, skb_alloc_time++); ++#define os_skb_copy(ori_skb, priority, skb) skb_copy(ori_skb, priority);\ ++ AML_OUTPUT("%s skb:%p, skb_alloc_time:%d\n", __func__, skb, skb_alloc_time++); ++#define os_skb_copy_expand(ori_skb, header_len, tail_len, priority, skb) skb_copy_expand(ori_skb, header_len, tail_len, priority);\ ++ AML_OUTPUT("%s skb:%p, skb_alloc_time:%d\n", __func__, skb, skb_alloc_time++); ++ ++#define os_skb_free(skb) consume_skb(skb);\ ++ AML_OUTPUT("%s skb:%p, skb_free_time:%d\n", __func__, skb, skb_free_time++); ++ ++#else ++ ++#define os_skb_count_alloc(skb) ++#define os_skb_count_free(skb) ++#define os_skb_alloc(_len) dev_alloc_skb(ALIGN(_len, 4)); ++#define os_skb_free(skbbuf) { consume_skb(skbbuf); skbbuf = NULL; } ++#define os_skb_copy(ori_skb, priority, skb) skb_copy(ori_skb, priority); ++#define os_skb_copy_expand(ori_skb, header_len, tail_len, priority, skb) skb_copy_expand(ori_skb, header_len, tail_len, priority); ++#endif ++ ++#endif//_WIFI_SKBBUF_H_ -- -2.39.5 +Armbian diff --git a/patch/kernel/archive/meson64-6.6/jethome-0010-wifi-fix-scan-rx-uaf-on-rsn-parse-failure.patch b/patch/kernel/archive/meson64-6.6/jethome-0010-wifi-fix-scan-rx-uaf-on-rsn-parse-failure.patch deleted file mode 100644 index f87e78d4b..000000000 --- a/patch/kernel/archive/meson64-6.6/jethome-0010-wifi-fix-scan-rx-uaf-on-rsn-parse-failure.patch +++ /dev/null @@ -1,99 +0,0 @@ -From: ThirdReality -Subject: [PATCH] fix(wifi): don't free a listed scan entry when RSN parsing fails - -wifi_mac_scan_rx()'s error path corrupts the scan table and takes the box down -with a NULL dereference inside the scan list walk: - - Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP - pc : wifi_mac_scan_rx+0x59c/0x83c [vlsicomm] - Call trace: - wifi_mac_scan_rx <- wifi_mac_recv_probersp <- wifi_mac_recv_mgmt - <- wifi_mac_input <- wifi_mac_input_all <- wifi_mac_rx_complete - <- drv_intr_rx_ok <- hal_soft_rx_cs <- hal_rx_thread - -The function takes one of two entries: an existing one from the scan table -(oldse, already linked into st->st_hash[] and st->st_entry), or a freshly -kzalloc()ed one that is not linked anywhere yet. The "goto fail" taken when -wifi_mac_parse_counterpart_rsn() rejects an AP's RSN IE then has to unlink the -entry only in the first case. It gets that test wrong: - - if (WIFINET_ADDR_EQ(se, oldse)) { - -WIFINET_ADDR_EQ() is memcmp(a1, a2, 6), meant for MAC addresses. Applied to -two struct scaninfo_entry pointers it compares the first six bytes of the -structs instead of the pointers, and dereferences oldse - which is NULL on -every newly allocated entry. So: - - - oldse == NULL: memcmp() reads through a NULL pointer. Both operands are - kmalloc'd from the same 128-byte-aligned bucket and the leading bytes are - list_head pointers into the same slab, so the comparison is junk even when - it does not fault outright. - - - oldse != NULL: if those six bytes happen to differ, the list_del_init() - pair is skipped and the entry is kfree()d while still linked, leaving - st_hash[hash] and st_entry pointing at freed memory. The next walker - - wifi_mac_recv_probersp()'s hash lookup, wifi_mac_scan_flush(), or - wifi_mac_scan_rx() itself - follows the dangling se_hash into the freed - slab. That is the Oops above: faulting address 0, x0 holding the stale - entry, and the faulting insn b9400300 loading from it. - -Reproducer is simply an AP in range whose RSN IE this parser refuses (it only -accepts RSN_VERSION with recognised cipher/AKM selectors, and rejects WPA3 -suites among others, all of which log "RSN akm cipher wrong" / "RSN bad -version" first) whose BSSID is already in the scan table. Hence the crash at -~12.9s, right as NetworkManager kicks off the first scan. - -Fix both halves: - - - compare the pointers (se == oldse), which is what the code meant; - - free only an entry that was never published, so the table can never point - at freed memory. A listed oldse is left in place with its previous, still - coherent contents: it was already there before this probe response arrived - and the ageing path will retire it normally. - -The unlink-then-free that the old code attempted was itself wrong for a listed -entry, because callers of wifi_mac_scan_rx() keep using the table right after -it returns. Not touching a listed entry is both simpler and safe. Dropping -the WIFI_SCAN_SE_LIST_LOCK() section with it is fine: the remaining work no -longer touches either list. - -This path runs from hal_rx_thread under GFP_ATOMIC, so it must not sleep; -nothing here does. - -Applies on top of jethome-0004. ---- ---- a/drivers/net/wireless/w1/vmac/wifi_mac_scan.c -+++ b/drivers/net/wireless/w1/vmac/wifi_mac_scan.c -@@ -821,17 +821,23 @@ - - return; - - fail: -- WIFI_SCAN_SE_LIST_LOCK(st); -- if (WIFINET_ADDR_EQ(se, oldse)) { -- list_del_init(&se->se_list); -- list_del_init(&se->se_hash); -- printk("[Micro]%s_%d,delete oldse\n", __func__, __LINE__); -- } -- WIFI_SCAN_SE_LIST_UNLOCK(st); -- FREE(se,"sta_add.se"); -- printk("[Micro]%s_%d\n", __func__, __LINE__); -+ /* -+ * Only a never-published entry may be freed. When se == oldse it is -+ * already linked into st_hash[]/st_entry and callers keep walking those -+ * lists after we return, so freeing it left the table pointing into freed -+ * slab memory. Leave it linked with its previous contents instead; -+ * ageing retires it normally. -+ */ -+ if (se != oldse) { -+ DPRINTF(AML_DEBUG_WARNING, "%s %d RSN parse failed, dropping new entry\n", -+ __func__, __LINE__); -+ FREE(se, "sta_add.se"); -+ } else { -+ DPRINTF(AML_DEBUG_WARNING, "%s %d RSN parse failed, keeping listed entry\n", -+ __func__, __LINE__); -+ } - return; - } - - static void quiet_intf (struct wlan_net_vif *wnet_vif, unsigned char enable) From 92b55b6c5f805948691c2707aee622816f8b2079 Mon Sep 17 00:00:00 2001 From: "guoping.liu" Date: Sat, 10 Oct 2026 12:55:52 +0800 Subject: [PATCH 2/9] feat(uboot): Use ThirdReality FIP for trhubv3 Sign trhubv3 u-boot with thirdreality/amlogic-boot-fip branch hubv3 (Amlogic SDK 2025r1 bl2/bl30/bl31, HubV3 DDR4 acs.bin). Other trhub boards still use jethub-j100. --- config/sources/families/trhub.conf | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/config/sources/families/trhub.conf b/config/sources/families/trhub.conf index 3512ca158..1bb82ed8d 100644 --- a/config/sources/families/trhub.conf +++ b/config/sources/families/trhub.conf @@ -39,10 +39,14 @@ elif [[ "$BOARD" == "trhubv3a" ]]; then OFFSET=126 fi +function fetch_sources_tools__thirdreality_amlogic_fip() { + fetch_from_repo "https://github.com/thirdreality/amlogic-boot-fip" "amlogic-boot-fip-thirdreality" "branch:hubv3" +} + uboot_custom_postprocess() { display_alert "uboot_custom_postprocess:" "${BOARD}" "info" if [[ "$BOARD" == "trhubv3" ]]; then - uboot_axg_postprocess_ng "$SRC/cache/sources/amlogic-boot-fip/jethub-j100" + uboot_axg_postprocess_ng "$SRC/cache/sources/amlogic-boot-fip-thirdreality/thirdreality-hubv3" elif [[ "$BOARD" == "linuxbox" ]]; then uboot_axg_postprocess_ng "$SRC/cache/sources/amlogic-boot-fip/jethub-j100" elif [[ "$BOARD" == "trhubv3b" ]]; then From f56745564c5fd94fccd5b19c7726d515b488d44d Mon Sep 17 00:00:00 2001 From: "guoping.liu" Date: Sat, 10 Oct 2026 15:24:07 +0800 Subject: [PATCH 3/9] feat(burn): Use own SDK 2025r1 USB loaders for hubv3 Replace bins/hubv3 DDR.USB/UBOOT.USB with u-boot.bin.usb.bl2/.usb.tpl built from Amlogic SDK 2025r1 board axg_hubv3_v1 (HubV3 DDR4 acs, bl30 v1.1.3545, bl31 v1.3.2), drop the JetHome .default copies, rename amlogic-dt-id to axg_hubv3_v1 and point convert.sh v3 at bins/hubv3. v3a/v3b still use bins/j100. --- amlogic-tools.repo/bins/hubv3/DDR.USB | Bin 49152 -> 49152 bytes amlogic-tools.repo/bins/hubv3/DDR.USB.default | Bin 49152 -> 0 bytes amlogic-tools.repo/bins/hubv3/UBOOT.USB | Bin 959488 -> 605184 bytes .../bins/hubv3/UBOOT.USB.default | Bin 590336 -> 0 bytes amlogic-tools.repo/convert.sh | 2 +- .../dts/meson-axg-thirdreality-trhub-v3.dts | 2 +- 6 files changed, 2 insertions(+), 2 deletions(-) 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ThirdReality HubV3L (trhubv3l) HubV3L (LinuxBox-Lite MB0.5) has the HubV3 pinout and software; only RAM differs (2x DDR3, 2 ranks, 1GB). - config/boards/trhubv3l.conf, BOOTCONFIG trhub_v3l_defconfig, BOOT_FDT_FILE meson-axg-thirdreality-trhub-v3l.dtb - u-boot board_trhubv3l: board_trhubv3 patches + v3l DTS/defconfig - kernel dt/meson-axg-thirdreality-trhub-v3l.dts: v3 with /memory = 1GB - FIP thirdreality-hubv3l (DDR3 2-rank acs.bin) - burn: bins/hubv3l from SDK 2025r1 axg_hubv3l_v1, dt-id axg_hubv3l_v1, convert.sh v3l - release info, factory-reset, supervisor prefix and BSP same as trhubv3 - make-armbian-build-release.sh -b hubv3l --- amlogic-tools.repo/bins/hubv3l/DDR.USB | Bin 0 -> 49152 bytes amlogic-tools.repo/bins/hubv3l/UBOOT.USB | Bin 0 -> 605184 bytes .../bins/hubv3l/image.armbian.cfg | 10 + amlogic-tools.repo/bins/hubv3l/image.haos.cfg | 17 + amlogic-tools.repo/bins/hubv3l/platform.conf | 9 + amlogic-tools.repo/convert.sh | 3 + .../dts/meson-axg-thirdreality-trhub-v3l.dts | 319 + config/boards/trhubv3l.conf | 19 + config/sources/families/trhub.conf | 4 +- lib/functions/rootfs/distro-agnostic.sh | 2 +- make-armbian-build-release.sh | 17 +- .../bsp/thirdreality/common/factory-reset.sh | 4 +- .../trhubv3a/supervisor/configuration.yaml | 1 + packages/bsp/thirdreality/trhubv3l | 1 + .../dt/meson-axg-thirdreality-trhub-v3l.dts | 17 + ...001-HACK-mmc-meson-gx-limit-to-24MHz.patch | 26 + ...change-clock-phase-value-on-axg-SoCs.patch | 54 + ...amlogic-2019-aml-partition-keyman-co.patch | 63704 ++++++++++++++++ ...amlogic-2019-aml-partition-keyman-co.patch | 505 + ...5-Add-usid-serial-mac-read-from-emmc.patch | 102 + ...efi-options-for-JetHub-D1-H1.patch.disable | 67 + ...rt-JetHub-D1-eth-mac-generation-with.patch | 54 + ...jethub-j100-fix-common-config-header.patch | 28 + ...-thirdreality-hubv3-linuxbox-support.patch | 1658 + .../0011-fixed-led-and-other-pin-ctrl.patch | 119 + ...0012-add-thirdreality-hubv3l-support.patch | 116 + 26 files changed, 66849 insertions(+), 7 deletions(-) create mode 100644 amlogic-tools.repo/bins/hubv3l/DDR.USB create mode 100644 amlogic-tools.repo/bins/hubv3l/UBOOT.USB create mode 100644 amlogic-tools.repo/bins/hubv3l/image.armbian.cfg create mode 100644 amlogic-tools.repo/bins/hubv3l/image.haos.cfg create mode 100644 amlogic-tools.repo/bins/hubv3l/platform.conf create mode 100644 amlogic-tools.repo/dts/meson-axg-thirdreality-trhub-v3l.dts create mode 100644 config/boards/trhubv3l.conf create mode 120000 packages/bsp/thirdreality/trhubv3l create mode 100644 patch/kernel/archive/meson64-6.6/dt/meson-axg-thirdreality-trhub-v3l.dts create mode 100644 patch/u-boot/v2023.10/board_trhubv3l/0001-HACK-mmc-meson-gx-limit-to-24MHz.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3l/0002-mmc-meson-gx-change-clock-phase-value-on-axg-SoCs.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3l/0003-Copy-and-update-amlogic-2019-aml-partition-keyman-co.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3l/0004-Copy-and-update-amlogic-2019-aml-partition-keyman-co.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3l/0005-Add-usid-serial-mac-read-from-emmc.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3l/0006-HACK-force-disable-efi-options-for-JetHub-D1-H1.patch.disable create mode 100644 patch/u-boot/v2023.10/board_trhubv3l/0007-ARM-amlogic-revert-JetHub-D1-eth-mac-generation-with.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3l/0008-board-amlogic-jethub-j100-fix-common-config-header.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3l/0010-add-thirdreality-hubv3-linuxbox-support.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3l/0011-fixed-led-and-other-pin-ctrl.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3l/0012-add-thirdreality-hubv3l-support.patch diff --git a/amlogic-tools.repo/bins/hubv3l/DDR.USB b/amlogic-tools.repo/bins/hubv3l/DDR.USB new file mode 100644 index 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+ model = "ThirdReality TRHub-V3L"; + amlogic-dt-id = "axg_hubv3l_v1"; + + aliases { + serial0 = &uart_AO; /* Console */ + serial1 = &uart_AO_B; /* External UART (Wireless Module) */ + serial2 = &uart_B; /* Bluetooth */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* 2048MB RAM */ + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + linux,cma { + compatible = "shared-dma-pool"; + reusable; size = <0x0 0x400000>; + alignment = <0x0 0x400000>; + linux,cma-default; + }; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vcc_5v: regulator-vcc_5v { + compatible = "regulator-fixed"; + regulator-name = "VCC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_5v>; + regulator-always-on; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + usb_pwr: regulator-usb_pwr { + compatible = "regulator-fixed"; + regulator-name = "USB_PWR"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + regulator-always-on; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */ + }; + + efusekey: efusekey { + keynum = <5>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key4 = <&key_4>; + + key_0: key_0 { + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1: key_1 { + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2: key_2 { + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3: key_3 { + keyname = "usid"; + offset = <18>; + size = <32>; + }; + key_4: key_4 { + keyname = "serial"; + offset = <50>; + size = <32>; + }; + }; //End efusekey + + unifykey { + compatible = "amlogic, unifykey"; + status = "ok"; + unifykey-num = <6>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + + keysn_0: key_0 { + key-name = "usid"; + key-device = "normal"; + key-permit = "read"; + }; + keysn_1: key_1 { + key-name = "mac"; + key-device = "normal"; + key-permit = "read"; + }; + keysn_2: key_2 { + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_3: key_3 { + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_4: key_4 { + key-name = "serial"; + key-device = "normal"; + key-permit = "read"; + }; + keysn_5:key_5 { + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + }; //End unifykey +}; + +/* Internal I2C bus (on CPU module) */ +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_z_pins>; + pinctrl-names = "default"; + + /* RTC */ + pcf8563: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + status = "okay"; + }; +}; + +/* Peripheral I2C bus (on motherboard) */ +&i2c_AO { + status = "okay"; + pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>; + pinctrl-names = "default"; +}; + +&pwm_ab { + status = "okay"; + pinctrl-0 = <&pwm_a_x20_pins>; + pinctrl-names = "default"; +}; + +/* wifi module */ +&sd_emmc_b { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr104; + max-frequency = <200000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* emmc storage */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* UART Bluetooth */ +&uart_B { + status = "okay"; + pinctrl-0 = <&uart_b_z_pins>, <&uart_b_z_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>; + }; +}; + +/* UART Console */ +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +/* UART Wireless module */ +&uart_AO_B { + status = "okay"; + pinctrl-0 = <&uart_ao_b_z_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; + phy-supply = <&usb_pwr>; +}; + +&spicc1 { + status = "okay"; +}; + +&audio { + status = "disabled"; +}; + +&efuse { + status = "okay"; + compatible = "amlogic,meson-gxbb-efuse", "amlogic, efuse"; + read_cmd = <0x82000030>; + write_cmd = <0x82000031>; + get_max_cmd = <0x82000033>; + key = <&efusekey>; + clock-names = "efuse_clk"; +}; + diff --git a/config/boards/trhubv3l.conf b/config/boards/trhubv3l.conf new file mode 100644 index 000000000..4de577d50 --- /dev/null +++ b/config/boards/trhubv3l.conf @@ -0,0 +1,19 @@ +# TRHub V3L (LinuxBox-Lite MB0.5) Amlogic A113X quad core 1GB DDR3 (2 ranks), eMMC 8GB; same pinout as V3 +BOARD_NAME="TRHub-V3L" +BOARDFAMILY="trhub" +HOST="linuxbox-hubv3l" +BOOTCONFIG="trhub_v3l_defconfig" +BOOT_FDT_FILE="amlogic/meson-axg-thirdreality-trhub-v3l.dtb" +KERNEL_TARGET="current,edge" +KERNEL_TEST_TARGET="current" +# WiFi modules (aml_sdio + vlsicomm) are loaded by amlogicw1.service +# (w1_start.sh) after boot, not via systemd-modules-load. Loading them early +# races the SDIO power-on/probe and can block ~90s on a cold-boot timing +# failure, so no MODULES_CURRENT override is set here. +#PACKAGE_LIST_BOARD="libubootenv-tool apparmor rfkill bluetooth bluez bluez-tools dbus-broker libprotobuf-lite32 python3-pip python3-dev python3.11-venv python3-aiohttp python3-gi python3-dbus python3-gi-cairo gir1.2-gtk-3.0watchdog ca-certificates cifs-utils libnfs13 curl dbus jq libglib2.0-bin lsb-release network-manager nfs-common systemd-journal-remote systemd-resolved udisks2 wget systemd-timesyncd ipset iputils-arping iputils-ping libturbojpeg0 libcjson1 tzdata libjemalloc2 libavahi-client3 libavahi-common3 libflac12 libogg0 libopus0 libsoxr0 libvorbis0a libvorbisenc2" +PACKAGE_LIST_BOARD="libubootenv-tool apparmor rfkill bluetooth bluez bluez-tools dbus-broker libprotobuf-lite32 python3-pip python3-dev python3.11-venv python3-aiohttp watchdog ca-certificates cifs-utils curl dbus jq libglib2.0-bin lsb-release network-manager nfs-common systemd-journal-remote systemd-resolved udisks2 wget systemd-timesyncd ipset iputils-arping iputils-ping libturbojpeg0 libcjson1 libjsoncpp25 tzdata libjemalloc2 avahi-daemon libavahi-client3 libavahi-common3 libmosquitto1 mosquitto mosquitto-clients" + +PACKAGE_LIST_BOARD_REMOVE="chrony resolvconf openvpn network-manager-openvpn unattended-upgrades" +PACKAGE_LIST_RM="armbian-zsh" +DEFAULT_CONSOLE="serial" +HAS_VIDEO_OUTPUT="no" \ No newline at end of file diff --git a/config/sources/families/trhub.conf b/config/sources/families/trhub.conf index 1bb82ed8d..e0bcc05a6 100644 --- a/config/sources/families/trhub.conf +++ b/config/sources/families/trhub.conf @@ -25,7 +25,7 @@ BOOTSIZE="128" # MiB - must match the 'boot' size in partition_arm.dtsi SUPERVISOR_VERSION="2.5.8" -if [[ "$BOARD" == "trhubv3" ]]; then +if [[ "$BOARD" == "trhubv3" || "$BOARD" == "trhubv3l" ]]; then CPUMAX=1416000 OFFSET=126 elif [[ "$BOARD" == "linuxbox" ]]; then @@ -47,6 +47,8 @@ uboot_custom_postprocess() { display_alert "uboot_custom_postprocess:" "${BOARD}" "info" if [[ "$BOARD" == "trhubv3" ]]; then uboot_axg_postprocess_ng "$SRC/cache/sources/amlogic-boot-fip-thirdreality/thirdreality-hubv3" + elif [[ "$BOARD" == "trhubv3l" ]]; then + uboot_axg_postprocess_ng "$SRC/cache/sources/amlogic-boot-fip-thirdreality/thirdreality-hubv3l" elif [[ "$BOARD" == "linuxbox" ]]; then uboot_axg_postprocess_ng "$SRC/cache/sources/amlogic-boot-fip/jethub-j100" elif [[ "$BOARD" == "trhubv3b" ]]; then diff --git a/lib/functions/rootfs/distro-agnostic.sh b/lib/functions/rootfs/distro-agnostic.sh index 9cb4c6fc6..14a607ee6 100644 --- a/lib/functions/rootfs/distro-agnostic.sh +++ b/lib/functions/rootfs/distro-agnostic.sh @@ -100,7 +100,7 @@ function install_distribution_agnostic() { echo "${VENDOR} ${IMAGE_VERSION:-"${REVISION}"} ${RELEASE^}" > "${SDCARD}"/etc/issue.net if [ "${RELEASE}" == "bookworm" ]; then - if [[ $BOARD == trhubv3 || $BOARD == linuxbox ]]; then + if [[ $BOARD == trhubv3 || $BOARD == trhubv3l || $BOARD == linuxbox ]]; then cat <<-EOF > "${SDCARD}/etc/t3r-release" PRETTY_NAME="LinuxBox Dev Edition" NAME="LinuxBox/HubV3" diff --git a/make-armbian-build-release.sh b/make-armbian-build-release.sh index 8b2de436c..c7434c5eb 100755 --- a/make-armbian-build-release.sh +++ b/make-armbian-build-release.sh @@ -27,7 +27,7 @@ check_command() { # Directories setup current_dir=$(pwd) print_info "Working directory is '$current_dir'" -echo "Usage: $0 [-b board:hubv3|hubv3a|hubv3b|linuxbox] -d [cn|us|kr] -r [revision]" +echo "Usage: $0 [-b board:hubv3|hubv3a|hubv3b|hubv3l|linuxbox] -d [cn|us|kr] -r [revision]" # Public release names are hubv3*, while Armbian retains trhubv3* internally. @@ -39,8 +39,8 @@ r3version="v2.14.01.51" usage() { local status="${1:-1}" - echo "Usage: $0 [-b board:hubv3|hubv3a|hubv3b|linuxbox] -d [cn|us|kr] -r [revision]" - echo " hubv3, hubv3a and hubv3b are the supported public board names." + echo "Usage: $0 [-b board:hubv3|hubv3a|hubv3b|hubv3l|linuxbox] -d [cn|us|kr] -r [revision]" + echo " hubv3, hubv3a, hubv3b and hubv3l are the supported public board names." exit "$status" } @@ -56,6 +56,10 @@ while getopts ":b:d:r:v:h" opt; do board="trhubv3a" board_label="hubv3a" ;; + hubv3l) + board="trhubv3l" + board_label="hubv3l" + ;; hubv3b) board="trhubv3b" board_label="hubv3b" @@ -258,6 +262,9 @@ case ${board} in trhubv3a) BOARD_NAME="hubv3a" ;; + trhubv3l) + BOARD_NAME="hubv3l" + ;; *) BOARD_NAME="${board}" ;; @@ -289,6 +296,10 @@ case ${BOARD} in ./convert.sh ../${IMG} v3a armbian compress output/usr/lib/linux*/u-boot.nosd.bin SUPPORTED="V3,V3A,V3B" ;; + trhubv3l) + ./convert.sh ../${IMG} v3l armbian compress output/usr/lib/linux*/u-boot.nosd.bin + SUPPORTED="V3L" + ;; jethubj100) ./convert.sh ../${IMG} d1 armbian compress output/usr/lib/linux*/u-boot.nosd.bin SUPPORTED="D1,D1P" diff --git a/packages/bsp/thirdreality/common/factory-reset.sh b/packages/bsp/thirdreality/common/factory-reset.sh index 8701edbf9..460ef8392 100755 --- a/packages/bsp/thirdreality/common/factory-reset.sh +++ b/packages/bsp/thirdreality/common/factory-reset.sh @@ -613,7 +613,7 @@ remove_otbr_agent remove_matter2mqtt # remove zigbee2mqtt -if [ "$trhub_model" == "trhubv3" ] || [ "$trhub_model" == "trhubv3a" ]; then +if [ "$trhub_model" == "trhubv3" ] || [ "$trhub_model" == "trhubv3a" ] || [ "$trhub_model" == "trhubv3l" ]; then remove_zigbee2mqtt remove_linuxbox_bridge else @@ -630,7 +630,7 @@ remove_openhab remove_music_assistant print_info "Purging remaining thirdreality packages (start)" -if [ "$trhub_model" == "trhubv3" ] || [ "$trhub_model" == "trhubv3a" ]; then +if [ "$trhub_model" == "trhubv3" ] || [ "$trhub_model" == "trhubv3a" ] || [ "$trhub_model" == "trhubv3l" ]; then debs=$(dpkg --list | awk '/^ii/ && $2 ~ /^thirdreality-/{print $2}') if [ -n "$debs" ]; then print_info "Found thirdreality packages: $debs" diff --git a/packages/bsp/thirdreality/trhubv3a/supervisor/configuration.yaml b/packages/bsp/thirdreality/trhubv3a/supervisor/configuration.yaml index 897536d5a..1611b8c0b 100644 --- a/packages/bsp/thirdreality/trhubv3a/supervisor/configuration.yaml +++ b/packages/bsp/thirdreality/trhubv3a/supervisor/configuration.yaml @@ -53,6 +53,7 @@ system_info: trhubv3: "3RHUB-" trhubv3a: "3RHUB-" trhubv3b: "3RCARE-" + trhubv3l: "3RHUB-" default: "3RHUB-" diff --git a/packages/bsp/thirdreality/trhubv3l b/packages/bsp/thirdreality/trhubv3l new file mode 120000 index 000000000..b3395ff29 --- /dev/null +++ b/packages/bsp/thirdreality/trhubv3l @@ -0,0 +1 @@ +trhubv3 \ No newline at end of file diff --git a/patch/kernel/archive/meson64-6.6/dt/meson-axg-thirdreality-trhub-v3l.dts b/patch/kernel/archive/meson64-6.6/dt/meson-axg-thirdreality-trhub-v3l.dts new file mode 100644 index 000000000..a6ee05e58 --- /dev/null +++ b/patch/kernel/archive/meson64-6.6/dt/meson-axg-thirdreality-trhub-v3l.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * ThirdReality HubV3L (LinuxBox-Lite MB0.5): same pinout as HubV3, + * 2x DDR3 16bit 2 ranks = 1GB. CMA is size-only and ramoops sits at + * 0x07000000, so both still fit below 1GB. + */ + +#include "meson-axg-thirdreality-trhub-v3.dts" + +/ { + compatible = "ThirdReality,trhub-v3l", "amlogic,a113d", "amlogic,meson-axg"; + model = "ThirdReality TRHub-V3L"; + + memory@0 { + reg = <0x0 0x0 0x0 0x40000000>; + }; +}; diff --git a/patch/u-boot/v2023.10/board_trhubv3l/0001-HACK-mmc-meson-gx-limit-to-24MHz.patch b/patch/u-boot/v2023.10/board_trhubv3l/0001-HACK-mmc-meson-gx-limit-to-24MHz.patch new file mode 100644 index 000000000..43cd435b1 --- /dev/null +++ b/patch/u-boot/v2023.10/board_trhubv3l/0001-HACK-mmc-meson-gx-limit-to-24MHz.patch @@ -0,0 +1,26 @@ +From 24ba56015b1ce831639f482d26aeec11ac523906 Mon Sep 17 00:00:00 2001 +From: Neil Armstrong +Date: Mon, 2 Sep 2019 15:42:04 +0200 +Subject: [PATCH 1/8] HACK: mmc: meson-gx: limit to 24MHz + +Signed-off-by: Neil Armstrong +--- + drivers/mmc/meson_gx_mmc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c +index fcf4f03d1e2..6ded4b619bf 100644 +--- a/drivers/mmc/meson_gx_mmc.c ++++ b/drivers/mmc/meson_gx_mmc.c +@@ -279,7 +279,7 @@ static int meson_mmc_probe(struct udevice *dev) + cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT | + MMC_MODE_HS_52MHz | MMC_MODE_HS; + cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV); +- cfg->f_max = 100000000; /* 100 MHz */ ++ cfg->f_max = SD_EMMC_CLKSRC_24M; + cfg->b_max = 511; /* max 512 - 1 blocks */ + cfg->name = dev->name; + +-- +2.43.2 + diff --git a/patch/u-boot/v2023.10/board_trhubv3l/0002-mmc-meson-gx-change-clock-phase-value-on-axg-SoCs.patch b/patch/u-boot/v2023.10/board_trhubv3l/0002-mmc-meson-gx-change-clock-phase-value-on-axg-SoCs.patch new file mode 100644 index 000000000..4e69e9237 --- /dev/null +++ b/patch/u-boot/v2023.10/board_trhubv3l/0002-mmc-meson-gx-change-clock-phase-value-on-axg-SoCs.patch @@ -0,0 +1,54 @@ +From d2c54d518b8b3f362a8395d2a81a2e7cef7a1ae0 Mon Sep 17 00:00:00 2001 +From: Vyacheslav Bocharov +Date: Thu, 2 Dec 2021 13:10:24 +0300 +Subject: [PATCH 2/8] mmc: meson-gx: change clock phase value on axg SoCs + +Amlogic AXG SoCs seems doesn't work over 50MHz. When phase sets to 270', +it's working fine over 50MHz on Amlogic AXG SoCs. +Based on 0dbb54eb3257c243c7968f967a6b183b1edb56c8 by Neil Armstrong + + +To distinguish which value is used adds an u-boot only axg compatible. +--- + drivers/mmc/meson_gx_mmc.c | 5 +++-- + drivers/mmc/meson_gx_mmc.h | 1 + + 2 files changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c +index 6ded4b619bf..5e32c386caa 100644 +--- a/drivers/mmc/meson_gx_mmc.c ++++ b/drivers/mmc/meson_gx_mmc.c +@@ -68,7 +68,8 @@ static void meson_mmc_config_clock(struct mmc *mmc) + * Other SoCs use CLK_CO_PHASE_180 by default. + * It needs to find what is a proper value about each SoCs. + */ +- if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1)) ++ if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1) || ++ meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_AXG)) + meson_mmc_clk |= CLK_CO_PHASE_270; + else + meson_mmc_clk |= CLK_CO_PHASE_180; +@@ -322,7 +323,7 @@ int meson_mmc_bind(struct udevice *dev) + + static const struct udevice_id meson_mmc_match[] = { + { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX }, +- { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX }, ++ { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_AXG }, + { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 }, + { /* sentinel */ } + }; +diff --git a/drivers/mmc/meson_gx_mmc.h b/drivers/mmc/meson_gx_mmc.h +index 8974b78f559..53201ceddae 100644 +--- a/drivers/mmc/meson_gx_mmc.h ++++ b/drivers/mmc/meson_gx_mmc.h +@@ -12,6 +12,7 @@ + enum meson_gx_mmc_compatible { + MMC_COMPATIBLE_GX, + MMC_COMPATIBLE_SM1, ++ MMC_COMPATIBLE_AXG, + }; + + #define SDIO_PORT_A 0 +-- +2.43.2 + diff --git a/patch/u-boot/v2023.10/board_trhubv3l/0003-Copy-and-update-amlogic-2019-aml-partition-keyman-co.patch b/patch/u-boot/v2023.10/board_trhubv3l/0003-Copy-and-update-amlogic-2019-aml-partition-keyman-co.patch new file mode 100644 index 000000000..1639ed179 --- /dev/null +++ b/patch/u-boot/v2023.10/board_trhubv3l/0003-Copy-and-update-amlogic-2019-aml-partition-keyman-co.patch @@ -0,0 +1,63704 @@ +From cc245241593c097c03d73caad7e7900392603b5b Mon Sep 17 00:00:00 2001 +From: Vyacheslav Bocharov +Date: Wed, 29 Jun 2022 09:26:35 +0300 +Subject: [PATCH 3/8] Copy and update amlogic-2019 aml partition/keyman code to + mainline + +--- + cmd/aml_mmc.c | 3542 ++ + cmd/storage.c | 1503 + + common/aml_dt.c | 600 + + common/partitions.c | 206 + + disk/part_aml.c | 110 + + drivers/amlogic/Kconfig | 14 + + drivers/amlogic/Makefile | 5 + + drivers/amlogic/keymanage/Kconfig | 21 + + drivers/amlogic/keymanage/Makefile | 32 + + drivers/amlogic/keymanage/key_manage.c | 689 + + drivers/amlogic/keymanage/key_manage.h | 61 + + drivers/amlogic/keymanage/key_manage_i.h | 65 + + drivers/amlogic/keymanage/key_unify.c | 610 + + drivers/amlogic/keymanage/km_dts.c | 392 + + drivers/amlogic/keymanage/km_efuse_key.c | 156 + + drivers/amlogic/keymanage/km_provision_key.c | 102 + + drivers/amlogic/keymanage/km_secure_key.c | 263 + + .../amlogic/keymanage/km_secure_key_2015.c | 118 + + drivers/amlogic/storagekey/Kconfig | 2 + + drivers/amlogic/storagekey/Makefile | 3 + + drivers/amlogic/storagekey/normal_key.c | 672 + + drivers/amlogic/storagekey/normal_key.h | 49 + + drivers/amlogic/storagekey/securestorage.c | 389 + + drivers/amlogic/storagekey/storagekey.c | 587 + + drivers/efuse/Kconfig | 4 + + drivers/efuse/Makefile | 9 + + drivers/efuse/aml_efuse.c | 123 + + drivers/efuse/bl31_apis.c | 474 + + drivers/efuse/efuse.c | 141 + + drivers/efuse/efuse_usr_space_api.c | 379 + + drivers/mmc/aml_emmc_partition.c | 1715 + + drivers/mmc/mmc_aml copy.c | 3299 ++ + drivers/mmc/mmc_aml.c | 416 + + drivers/mmc/storage_emmc.c | 946 + + include/amlogic/aml_cec.h | 86 + + include/amlogic/aml_efuse.h | 79 + + include/amlogic/aml_gpio.h | 54 + + include/amlogic/aml_hdmirx.h | 19 + + include/amlogic/aml_irblaster.h | 29 + + include/amlogic/aml_is31fl32xx.h | 9 + + include/amlogic/aml_led.h | 68 + + include/amlogic/aml_mmc.h | 105 + + include/amlogic/aml_mtd.h | 31 + + include/amlogic/aml_nand.h | 24 + + include/amlogic/aml_rsv.h | 106 + + include/amlogic/aml_tlv.h | 157 + + include/amlogic/aml_v2_burning.h | 31 + + include/amlogic/aml_v3_burning.h | 14 + + include/amlogic/amlkey_if.h | 85 + + include/amlogic/anti-rollback.h | 40 + + include/amlogic/asm/bl31_apis.h | 166 + + include/amlogic/asm/clock.h | 41 + + include/amlogic/asm/cpu_config.h | 101 + + include/amlogic/asm/cpu_sdio.h | 264 + + include/amlogic/asm/efuse.h | 62 + + include/amlogic/asm/io.h | 118 + + include/amlogic/asm/register.h | 98 + + include/amlogic/asm/regs.h | 32964 ++++++++++++++++ + include/amlogic/asm/romboot.h | 53 + + include/amlogic/asm/sd_emmc.h | 136 + + include/amlogic/asm/secure_apb.h | 4235 ++ + include/amlogic/auge_sound.h | 24 + + include/amlogic/blxx2bl33_param.h | 27 + + include/amlogic/canvas.h | 68 + + include/amlogic/color.h | 51 + + include/amlogic/cpu_id.h | 90 + + include/amlogic/enc_clk_config.h | 1 + + include/amlogic/fb.h | 399 + + include/amlogic/instaboot.h | 24 + + include/amlogic/jtag.h | 61 + + include/amlogic/keyunify.h | 56 + + include/amlogic/media/vout/aml_cvbs.h | 13 + + include/amlogic/media/vout/aml_vinfo.h | 148 + + include/amlogic/media/vout/aml_vmode.h | 98 + + include/amlogic/media/vout/aml_vout.h | 25 + + .../amlogic/media/vout/hdmitx/hdmi_common.h | 655 + + include/amlogic/media/vout/hdmitx/hdmitx.h | 11 + + .../amlogic/media/vout/hdmitx/hdmitx_ext.h | 6 + + .../amlogic/media/vout/hdmitx/hdmitx_module.h | 106 + + .../amlogic/media/vout/hdmitx/hdmitx_reg.h | 1041 + + include/amlogic/media/vout/hdmitx/mach_reg.h | 625 + + include/amlogic/media/vout/lcd/aml_lcd.h | 168 + + include/amlogic/media/vout/lcd/bl_extern.h | 88 + + include/amlogic/media/vout/lcd/bl_ldim.h | 118 + + include/amlogic/media/vout/lcd/lcd_extern.h | 116 + + include/amlogic/media/vout/lcd/lcd_vout.h | 520 + + include/amlogic/media/vpp/vpp.h | 24 + + include/amlogic/media/vpu/vpu.h | 11 + + include/amlogic/saradc.h | 103 + + include/amlogic/secure_storage.h | 46 + + include/amlogic/sound.h | 180 + + include/amlogic/spicc.h | 44 + + include/amlogic/spifc.h | 44 + + include/amlogic/storage.h | 501 + + include/amlogic/storagekey.h | 57 + + include/amlogic/store_wrapper.h | 56 + + include/amlstorage/emmc_partitions.h | 271 + + include/amlstorage/emmc_storage.h | 76 + + include/amlstorage/partition_table.h | 72 + + 99 files changed, 62896 insertions(+) + create mode 100644 cmd/aml_mmc.c + create mode 100644 cmd/storage.c + create mode 100644 common/aml_dt.c + create mode 100644 common/partitions.c + create mode 100644 disk/part_aml.c + create mode 100644 drivers/amlogic/Kconfig + create mode 100644 drivers/amlogic/Makefile + create mode 100644 drivers/amlogic/keymanage/Kconfig + create mode 100644 drivers/amlogic/keymanage/Makefile + create mode 100644 drivers/amlogic/keymanage/key_manage.c + create mode 100644 drivers/amlogic/keymanage/key_manage.h + create mode 100644 drivers/amlogic/keymanage/key_manage_i.h + create mode 100644 drivers/amlogic/keymanage/key_unify.c + create mode 100644 drivers/amlogic/keymanage/km_dts.c + create mode 100644 drivers/amlogic/keymanage/km_efuse_key.c + create mode 100644 drivers/amlogic/keymanage/km_provision_key.c + create mode 100644 drivers/amlogic/keymanage/km_secure_key.c + create mode 100644 drivers/amlogic/keymanage/km_secure_key_2015.c + create mode 100644 drivers/amlogic/storagekey/Kconfig + create mode 100644 drivers/amlogic/storagekey/Makefile + create mode 100644 drivers/amlogic/storagekey/normal_key.c + create mode 100644 drivers/amlogic/storagekey/normal_key.h + create mode 100644 drivers/amlogic/storagekey/securestorage.c + create mode 100644 drivers/amlogic/storagekey/storagekey.c + create mode 100644 drivers/efuse/Kconfig + create mode 100644 drivers/efuse/Makefile + create mode 100644 drivers/efuse/aml_efuse.c + create mode 100644 drivers/efuse/bl31_apis.c + create mode 100644 drivers/efuse/efuse.c + create mode 100644 drivers/efuse/efuse_usr_space_api.c + create mode 100644 drivers/mmc/aml_emmc_partition.c + create mode 100644 drivers/mmc/mmc_aml copy.c + create mode 100644 drivers/mmc/mmc_aml.c + create mode 100644 drivers/mmc/storage_emmc.c + create mode 100644 include/amlogic/aml_cec.h + create mode 100644 include/amlogic/aml_efuse.h + create mode 100644 include/amlogic/aml_gpio.h + create mode 100644 include/amlogic/aml_hdmirx.h + create mode 100644 include/amlogic/aml_irblaster.h + create mode 100644 include/amlogic/aml_is31fl32xx.h + create mode 100644 include/amlogic/aml_led.h + create mode 100644 include/amlogic/aml_mmc.h + create mode 100644 include/amlogic/aml_mtd.h + create mode 100644 include/amlogic/aml_nand.h + create mode 100644 include/amlogic/aml_rsv.h + create mode 100644 include/amlogic/aml_tlv.h + create mode 100644 include/amlogic/aml_v2_burning.h + create mode 100644 include/amlogic/aml_v3_burning.h + create mode 100644 include/amlogic/amlkey_if.h + create mode 100644 include/amlogic/anti-rollback.h + create mode 100644 include/amlogic/asm/bl31_apis.h + create mode 100644 include/amlogic/asm/clock.h + create mode 100644 include/amlogic/asm/cpu_config.h + create mode 100644 include/amlogic/asm/cpu_sdio.h + create mode 100644 include/amlogic/asm/efuse.h + create mode 100644 include/amlogic/asm/io.h + create mode 100644 include/amlogic/asm/register.h + create mode 100644 include/amlogic/asm/regs.h + create mode 100644 include/amlogic/asm/romboot.h + create mode 100644 include/amlogic/asm/sd_emmc.h + create mode 100644 include/amlogic/asm/secure_apb.h + create mode 100644 include/amlogic/auge_sound.h + create mode 100644 include/amlogic/blxx2bl33_param.h + create mode 100644 include/amlogic/canvas.h + create mode 100644 include/amlogic/color.h + create mode 100644 include/amlogic/cpu_id.h + create mode 100644 include/amlogic/enc_clk_config.h + create mode 100644 include/amlogic/fb.h + create mode 100644 include/amlogic/instaboot.h + create mode 100644 include/amlogic/jtag.h + create mode 100644 include/amlogic/keyunify.h + create mode 100644 include/amlogic/media/vout/aml_cvbs.h + create mode 100644 include/amlogic/media/vout/aml_vinfo.h + create mode 100644 include/amlogic/media/vout/aml_vmode.h + create mode 100644 include/amlogic/media/vout/aml_vout.h + create mode 100644 include/amlogic/media/vout/hdmitx/hdmi_common.h + create mode 100644 include/amlogic/media/vout/hdmitx/hdmitx.h + create mode 100644 include/amlogic/media/vout/hdmitx/hdmitx_ext.h + create mode 100644 include/amlogic/media/vout/hdmitx/hdmitx_module.h + create mode 100644 include/amlogic/media/vout/hdmitx/hdmitx_reg.h + create mode 100644 include/amlogic/media/vout/hdmitx/mach_reg.h + create mode 100644 include/amlogic/media/vout/lcd/aml_lcd.h + create mode 100644 include/amlogic/media/vout/lcd/bl_extern.h + create mode 100644 include/amlogic/media/vout/lcd/bl_ldim.h + create mode 100644 include/amlogic/media/vout/lcd/lcd_extern.h + create mode 100644 include/amlogic/media/vout/lcd/lcd_vout.h + create mode 100644 include/amlogic/media/vpp/vpp.h + create mode 100644 include/amlogic/media/vpu/vpu.h + create mode 100644 include/amlogic/saradc.h + create mode 100644 include/amlogic/secure_storage.h + create mode 100644 include/amlogic/sound.h + create mode 100644 include/amlogic/spicc.h + create mode 100644 include/amlogic/spifc.h + create mode 100644 include/amlogic/storage.h + create mode 100644 include/amlogic/storagekey.h + create mode 100644 include/amlogic/store_wrapper.h + create mode 100644 include/amlstorage/emmc_partitions.h + create mode 100644 include/amlstorage/emmc_storage.h + create mode 100644 include/amlstorage/partition_table.h + +diff --git a/cmd/aml_mmc.c b/cmd/aml_mmc.c +new file mode 100644 +index 00000000000..db9927e9120 +--- /dev/null ++++ b/cmd/aml_mmc.c +@@ -0,0 +1,3542 @@ ++/* ++ * (C) Copyright 2003 ++ * Kyle Harris, kharris@nexus-tech.net ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "../drivers/mmc/mmc_private.h" ++#include ++#include ++#include ++#include ++#include ++//#include ++#include ++#include ++ ++/* info system. */ ++#define dtb_err(fmt, ...) printf( "%s()-%d: " fmt , \ ++ __func__, __LINE__, ##__VA_ARGS__) ++ ++#define dtb_wrn(fmt, ...) printf( "%s()-%d: " fmt , \ ++ __func__, __LINE__, ##__VA_ARGS__) ++ ++/* for detail debug info */ ++#define dtb_info(fmt, ...) printf( "%s()-%d: " fmt , \ ++ __func__, __LINE__, ##__VA_ARGS__) ++ ++#define fb_err(fmt, ...) printf("%s()-%d: " fmt , \ ++ __func__, __LINE__, ##__VA_ARGS__) ++#define CONFIG_SYS_MMC_ENV_DEV 1 ++struct aml_dtb_rsv { ++ u8 data[DTB_BLK_SIZE*DTB_BLK_CNT - 4*sizeof(u32)]; ++ u32 magic; ++ u32 version; ++ u32 timestamp; ++ u32 checksum; ++}; ++ ++struct aml_dtb_info { ++ u32 stamp[2]; ++ u8 valid[2]; ++}; ++ ++#define stamp_after(a,b) ((int)(b) - (int)(a) < 0) ++/* glb dtb infos */ ++static struct aml_dtb_info dtb_infos = {{0, 0}, {0, 0}}; ++ ++#define CONFIG_SECURITYKEY ++ ++#if !defined(CONFIG_SYS_MMC_BOOT_DEV) ++ #define CONFIG_SYS_MMC_BOOT_DEV (CONFIG_SYS_MMC_ENV_DEV) ++#endif ++ ++#define GXB_START_BLK 0 ++#define GXL_START_BLK 1 ++ ++/* max 2MB for emmc in blks */ ++#define UBOOT_SIZE (0x1000) ++ ++ ++extern int mmc_key_write(unsigned char *buf, unsigned int size, uint32_t *actual_lenth); ++extern int mmc_key_read(unsigned char *buf, unsigned int size, uint32_t *actual_lenth); ++ ++/* move this out to storage */ ++//int info_disprotect = 0; ++ ++ ++int mmc_read_status(struct mmc *mmc, int timeout) ++{ ++ struct mmc_cmd cmd; ++ int err, retries = 5; ++ int status; ++ ++ cmd.cmdidx = MMC_CMD_SEND_STATUS; ++ cmd.resp_type = MMC_RSP_R1; ++ if (!mmc_host_is_spi(mmc)) ++ cmd.cmdarg = mmc->rca << 16; ++ do { ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ if (!err) { ++ if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && ++ (cmd.response[0] & MMC_STATUS_CURR_STATE) != ++ MMC_STATE_PRG) ++ break; ++ else if (cmd.response[0] & MMC_STATUS_MASK) { ++ printf("Status Error: 0x%08X\n", ++ cmd.response[0]); ++ return -18; ++ } ++ } else if (--retries < 0) ++ return err; ++ ++ udelay(1000); ++ ++ } while (timeout--); ++ ++ status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; ++ printf("CURR STATE:%d, status = 0x%x\n", status, cmd.response[0]); ++ ++ if (timeout <= 0) { ++ printf("read status Timeout waiting card ready\n"); ++ return -19; ++ } ++ if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR) { ++ printf("mmc status swwitch error status =0x%x\n", status); ++ return -21; ++ } ++ return 0; ++} ++ ++bool emmckey_is_protected (struct mmc *mmc) ++{ ++#ifdef CONFIG_STORE_COMPATIBLE ++#ifdef CONFIG_SECURITYKEY ++ if (info_disprotect & DISPROTECT_KEY) { ++ printf("%s(): disprotect\n", __func__); ++ return 0; ++ }else{ ++ printf("%s(): protect\n", __func__); ++ return 1; ++ } ++#else ++ return 0; ++#endif ++#else ++#ifdef CONFIG_SECURITYKEY ++ //return mmc->key_protect; ++ return 0; /* fixme, */ ++#else ++ return 0; ++#endif ++#endif ++} ++ ++unsigned emmc_cur_partition = 0; ++ ++ ++static int get_off_size(struct mmc * mmc, char * name, uint64_t offset, uint64_t size, u64 * blk, u64 * cnt, u64 * sz_byte) ++{ ++ struct partitions *part_info = NULL; ++ uint64_t off = 0; ++ int blk_shift = 0; ++ ++ blk_shift = ffs(mmc->read_bl_len) - 1; ++ // printf("blk_shift:%d , off:0x%llx , size:0x%llx.\n ",blk_shift,off,size ); ++ part_info = find_mmc_partition_by_name(name); ++ if (part_info == NULL) { ++ printf("get partition info failed !!\n"); ++ return -1; ++ } ++ off = part_info->offset + offset; ++ ++ // printf("part_info->offset:0x%llx , off:0x%llx , size:0x%llx.\n",part_info->offset ,off,size); ++ ++ *blk = off >> blk_shift ; ++ *cnt = size >> blk_shift ; ++ *sz_byte = size - ((*cnt) << blk_shift) ; ++ ++ // printf("get_partition_off_size : blk:0x%llx , cnt:0x%llx.\n",*blk,*cnt); ++ return 0; ++} ++ ++static int get_partition_size(unsigned char* name, uint64_t* addr) ++{ ++ struct partitions *part_info = NULL; ++ part_info = find_mmc_partition_by_name((char *)name); ++ if (part_info == NULL) { ++ printf("get partition info failed !!\n"); ++ return -1; ++ } ++ ++ *addr = part_info->size >> 9; // unit: 512 bytes ++ return 0; ++} ++ ++static inline int isstring(char *p) ++{ ++ char *endptr = p; ++ while (*endptr != '\0') { ++ if (!(((*endptr >= '0') && (*endptr <= '9')) ++ || ((*endptr >= 'a') && (*endptr <= 'f')) ++ || ((*endptr >= 'A') && (*endptr <= 'F')) ++ || (*endptr == 'x') || (*endptr == 'X'))) ++ return 1; ++ endptr++; ++ } ++ ++ return 0; ++} ++ ++/* ++ erase bootloader on user/boot0/boot1 which indicate by map. ++ bit 0: user ++ bit 1: boot0 ++ bit 2: boot1 ++*/ ++int amlmmc_erase_bootloader(int dev, int map) ++{ ++ int ret = 0, i, count = 3; ++ int blk_shift; ++ unsigned long n; ++ char *partname[3] = {"user", "boot0", "boot1"}; ++ // cpu_id_t cpu_id = get_cpu_id(); ++ struct mmc *mmc = find_mmc_device(dev); ++ ++ /* do nothing */ ++ if (0 == map) ++ goto _out; ++ ++ if (!mmc) { ++ printf("%s() %d: not valid emmc %d\n", __func__, __LINE__, dev); ++ ret = -1; ++ goto _out; ++ } ++ /* make sure mmc is initilized! */ ++ ret = mmc_init(mmc); ++ if (ret) { ++ printf("%s() %d: emmc %d init %d\n", __func__, __LINE__, dev, ret); ++ ret = -2; ++ goto _out; ++ } ++ ++ blk_shift = ffs(mmc->read_bl_len) -1; ++ /* erase bootloader in user/boot0/boot1 */ ++ for (i = 0; i < count; i++) { ++ if (map & (0x1 << i)) { ++ if (!blk_select_hwpart_devnum(UCLASS_MMC, 1, i)) { ++ lbaint_t start = 0, blkcnt; ++ ++ blkcnt = mmc->capacity >> blk_shift; ++ if (0 == i) { ++ struct partitions *part_info; ++ /* get info by partition */ ++ part_info = find_mmc_partition_by_name(MMC_BOOT_NAME); ++ if (part_info == NULL) { ++ printf("%s() %d: error!!\n", __func__, __LINE__); ++ /* fixme, do somthing! */ ++ continue; ++ } else { ++ start = part_info->offset>> blk_shift; ++ blkcnt = part_info->size>> blk_shift; ++ if (1) { //cpu_id.family_id >= MESON_CPU_MAJOR_ID_GXL) { ++ start = GXL_START_BLK; ++ blkcnt -= GXL_START_BLK; ++ } ++ } ++ } ++/* some customer may use boot1 higher 2M as private data. */ ++#ifdef CONFIG_EMMC_BOOT1_TOUCH_REGION ++ if (2 == i && CONFIG_EMMC_BOOT1_TOUCH_REGION <= mmc->capacity) { ++ blkcnt = CONFIG_EMMC_BOOT1_TOUCH_REGION >> blk_shift; ++ } ++#endif/* CONFIG_EMMC_BOOT1_TOUCH_REGION */ ++#ifdef CONFIG_AML_GPT ++ if (i == 0) ++ continue; ++#endif ++ printf("Erasing blocks " LBAFU " to " LBAFU " @ %s\n", ++ start, blkcnt, partname[i]); ++ n = blk_derase(mmc_get_blk_desc(mmc), start, blkcnt); ++ if (n != 0) { ++ printf("mmc erase %s failed\n", partname[i]); ++ ret = -3; ++ break; ++ } ++ } else ++ printf("%s() %d: switch dev %d to %s fail\n", ++ __func__, __LINE__, dev, partname[i]); ++ } ++ } ++ /* try to switch back to user. */ ++ blk_select_hwpart(mmc->dev, 0); ++ ++_out: ++ return ret; ++} ++ ++/* ++ write bootloader on user/boot0/boot1 which indicate by map. ++ bit 0: user ++ bit 1: boot0 ++ bit 2: boot1 ++*/ ++int amlmmc_write_bootloader(int dev, int map, unsigned int size, const void *src) ++{ ++ int ret = 0, i, count = 3; ++ unsigned long n; ++ char *partname[3] = {"user", "boot0", "boot1"}; ++ struct mmc *mmc = find_mmc_device(dev); ++ lbaint_t start = GXB_START_BLK, blkcnt; ++ //cpu_id_t cpu_id = get_cpu_id(); ++ ++ /* do nothing */ ++ if (0 == map) ++ goto _out; ++ ++ if (!mmc) { ++ printf("%s() %d: not valid emmc %d\n", __func__, __LINE__, dev); ++ ret = -1; ++ goto _out; ++ } ++ /* make sure mmc is initilized! */ ++ ret = mmc_init(mmc); ++ if (ret) { ++ printf("%s() %d: emmc %d init %d\n", __func__, __LINE__, dev, ret); ++ ret = -2; ++ goto _out; ++ } ++ ++ if(1) //(cpu_id.family_id >= MESON_CPU_MAJOR_ID_GXL) ++ start = GXL_START_BLK; ++ blkcnt = (size + mmc->read_bl_len - 1) / mmc->read_bl_len; ++ ++ /* erase bootloader in user/boot0/boot1 */ ++ for (i = 0; i < count; i++) { ++ if (map & (0x1 << i)) { ++ if (!blk_select_hwpart_devnum(UCLASS_MMC, 1, i)) { ++/* some customer may use boot1 higher 2M as private data. */ ++#ifdef CONFIG_EMMC_BOOT1_TOUCH_REGION ++ if (2 == i && CONFIG_EMMC_BOOT1_TOUCH_REGION <= size) { ++ printf("%s(), size %d exceeds TOUCH_REGION %d, skip\n", ++ __func__, size, CONFIG_EMMC_BOOT1_TOUCH_REGION); ++ break; ++ } ++#endif /* CONFIG_EMMC_BOOT1_TOUCH_REGION */ ++#ifdef CONFIG_AML_GPT ++ if (i == 0) ++ continue; ++#endif ++ printf("Wrting blocks " LBAFU " to " LBAFU " @ %s\n", ++ start, blkcnt, partname[i]); ++ n = blk_dwrite(mmc_get_blk_desc(mmc), start, blkcnt, src); ++ if (n != blkcnt) { ++ printf("mmc write %s failed\n", partname[i]); ++ ret = -3; ++ break; ++ } ++ } else ++ printf("%s() %d: switch dev %d to %s fail\n", ++ __func__, __LINE__, dev, partname[i]); ++ } ++ } ++ /* try to switch back to user. */ ++ blk_select_hwpart(mmc->dev, 0); ++ ++_out: ++ return ret; ++} ++ ++static int amlmmc_erase_in_dev(int argc, char *const argv[]) ++{ ++ int dev = 0; ++ u64 cnt = 0, blk = 0, n = 0; ++ struct mmc *mmc; ++ ++ dev = simple_strtoul(argv[2], NULL, 10); ++ blk = simple_strtoull(argv[3], NULL, 16); ++ cnt = simple_strtoull(argv[4], NULL, 16); ++ ++ if (dev < 0) { ++ printf("Cannot find dev.\n"); ++ return 1; ++ } ++ ++ mmc = find_mmc_device(dev); ++ ++ if (!mmc) ++ return 1; ++ ++ printf("MMC erase: dev # %d, start_erase_address(in block) # %#llx,\ ++ several blocks # %lld will be erased ...\n ", ++ dev, blk, cnt); ++ ++ mmc_init(mmc); ++ ++ if (cnt != 0) ++ n = blk_derase(mmc_get_blk_desc(mmc), blk, cnt); ++ ++ printf("dev # %d, %s, several blocks erased %s\n", ++ dev, " ", (n == 0) ? "OK" : "ERROR"); ++ ++ return (n == 0) ? 0 : 1; ++} ++ ++static int amlmmc_erase_in_card(int argc, char *const argv[]) ++{ ++ int dev = 0; ++ u64 cnt = 0, blk = 0, n = 0; ++ /*sz_byte =0;*/ ++ char *name = NULL; ++ u64 offset_addr = 0, size = 0; ++ struct mmc *mmc; ++ int tmp_shift; ++ ++ name = argv[2]; ++ dev = find_dev_num_by_partition_name (name); ++ offset_addr = simple_strtoull(argv[3], NULL, 16); ++ size = simple_strtoull(argv[4], NULL, 16); ++ mmc = find_mmc_device(dev); ++ ++ tmp_shift = ffs(mmc->read_bl_len) -1; ++ cnt = size >> tmp_shift; ++ blk = offset_addr >> tmp_shift; ++ /* sz_byte = size - (cnt<= part_info->size) { ++ printf("Start address out #%s# partition'address region,(addr_byte < 0x%llx)\n", ++ name, part_info->size); ++ return 1; ++ } ++ if ((offset_addr+size) > part_info->size) { ++ printf("End address exceeds #%s# partition,(offset = 0x%llx,size = 0x%llx)\n", ++ name, part_info->offset,part_info->size); ++ return 1; ++ } ++ get_off_size(mmc, name, offset_addr, size, &blk, &cnt, &sz_byte); ++ ++ if (dev < 0) { ++ printf("Cannot find dev.\n"); ++ return 1; ++ } ++ ++ ++ if (!mmc) ++ return 1; ++ ++ printf("MMC erase: dev # %d, start_erase_address(in block) # %#llx,\ ++ several blocks # %lld will be erased ...\n ", ++ dev, blk, cnt); ++ ++ mmc_init(mmc); ++ ++ if (cnt != 0) ++ n = blk_derase(mmc_get_blk_desc(mmc), blk, cnt); ++ ++ printf("dev # %d, %s, several blocks erased %s\n", ++ dev, argv[2], (n == 0) ? "OK" : "ERROR"); ++ return (n == 0) ? 0 : 1; ++} ++ ++static int amlmmc_erase_by_add(int argc, char *const argv[]) ++{ ++ int ret = 0; ++ ++ if (argc != 5) ++ return CMD_RET_USAGE; ++ ++ if (isdigit(argv[2][0])) ++ ret = amlmmc_erase_in_dev(argc, argv); ++ else if (strcmp(argv[2], "card") == 0) ++ ret = amlmmc_erase_in_card(argc, argv); ++ else if (isstring(argv[2])) ++ ret = amlmmc_erase_in_part(argc, argv); ++ ++ return ret; ++} ++ ++static int amlmmc_erase_non_loader(int argc, char *const argv[]) ++{ ++ int dev; ++ u32 n = 0; ++ int blk_shift; ++ u64 blk = 0, start_blk = 0; ++ struct partitions *part_info; ++ struct mmc *mmc; ++ ++ dev = 1; ++ if (dev < 0) { ++ printf("Cannot find dev.\n"); ++ return 1; ++ } ++ mmc = find_mmc_device(dev); ++ ++ if (!mmc) ++ return 1; ++ ++ mmc_init(mmc); ++ ++ blk_shift = ffs(mmc->read_bl_len) -1; ++ part_info = find_mmc_partition_by_name(MMC_BOOT_NAME); ++ ++ if (part_info == NULL) { ++ start_blk = 0; ++ printf("no uboot partition for eMMC boot, just erase from 0\n"); ++ } ++ else ++ start_blk = (part_info->offset + part_info->size) >> blk_shift; ++ ++ if (emmckey_is_protected(mmc)) { ++ part_info = find_mmc_partition_by_name(MMC_RESERVED_NAME); ++ if (part_info == NULL) { ++ return 1; ++ } ++ blk = part_info->offset; ++ // it means: there should be other partitions before reserve-partition. ++ if (blk > 0) ++ blk -= PARTITION_RESERVED; ++ blk >>= blk_shift; ++ blk -= start_blk; ++ // (1) erase all the area before reserve-partition ++ if (blk > 0) ++ n = blk_derase(mmc_get_blk_desc(mmc), start_blk, blk); ++ if (n == 0) { // not error ++ // (2) erase all the area after reserve-partition ++ start_blk = (part_info->offset + part_info->size + PARTITION_RESERVED) ++ >> blk_shift; ++ u64 erase_cnt = (mmc->capacity >> blk_shift) - start_blk; ++ n = blk_derase(mmc_get_blk_desc(mmc), start_blk, erase_cnt); ++ } ++ } else { ++ n = blk_derase(mmc_get_blk_desc(mmc), start_blk, 0); // erase the whole card ++ } ++ return (n == 0) ? 0 : 1; ++} ++ ++static int amlmmc_erase_single_part(int argc, char *const argv[]) ++{ ++ char *name = NULL; ++ int dev; ++ u32 n = 0; ++ int blk_shift; ++ u64 cnt = 0, blk = 0; ++ struct partitions *part_info; ++ struct mmc *mmc; ++ name = argv[2]; ++ dev = find_dev_num_by_partition_name(name); ++ if (dev < 0) { ++ printf("Cannot find dev.\n"); ++ return 1; ++ } ++ mmc = find_mmc_device(dev); ++ ++ if (!mmc) ++ return 1; ++ ++ mmc_init(mmc); ++ ++ blk_shift = ffs(mmc->read_bl_len) -1; ++ if (emmckey_is_protected(mmc) ++ && (strncmp(name, MMC_RESERVED_NAME, sizeof(MMC_RESERVED_NAME)) == 0x00)) { ++ printf("\"%s-partition\" is been protecting and should no be erased!\n", ++ MMC_RESERVED_NAME); ++ return 1; ++ } ++ ++ part_info = find_mmc_partition_by_name(name); ++ if (part_info == NULL) { ++ return 1; ++ } ++ ++ blk = part_info->offset >> blk_shift; ++ if (emmc_cur_partition && !strncmp(name, "bootloader", strlen("bootloader"))) ++ cnt = 0; ++ else ++ cnt = part_info->size >> blk_shift; ++ n = blk_derase(mmc_get_blk_desc(mmc), blk, cnt); ++ ++ return (n == 0) ? 0 : 1; ++} ++ ++static int amlmmc_erase_whole(int argc, char *const argv[]) ++{ ++ char *name = NULL; ++ int dev; ++ u32 n = 0; ++ int blk_shift; ++ //u64 cnt = 0, ++ u64 blk = 0, start_blk = 0; ++ struct partitions *part_info; ++ struct mmc *mmc; ++ int map; ++ ++ name = "logo"; ++ dev = find_dev_num_by_partition_name(name); ++ if (dev < 0) { ++ printf("Cannot find dev.\n"); ++ return 1; ++ } ++ mmc = find_mmc_device(dev); ++ if (!mmc) ++ return 1; ++ mmc_init(mmc); ++ blk_shift = ffs(mmc->read_bl_len) -1; ++ start_blk = 0; ++ ++ if (emmckey_is_protected(mmc)) { ++ part_info = find_mmc_partition_by_name(MMC_RESERVED_NAME); ++ if (part_info == NULL) { ++ return 1; ++ } ++ blk = part_info->offset; ++ // it means: there should be other partitions before reserve-partition. ++ if (blk > 0) ++ blk -= PARTITION_RESERVED; ++ blk >>= blk_shift; ++ blk -= start_blk; ++ // (1) erase all the area before reserve-partition ++ if (blk > 0) ++ n = blk_derase(mmc_get_blk_desc(mmc), start_blk, blk); ++ if (n == 0) { // not error ++ // (2) erase all the area after reserve-partition ++ start_blk = (part_info->offset + part_info->size + PARTITION_RESERVED) ++ >> blk_shift; ++ u64 erase_cnt = (mmc->capacity >> blk_shift) - start_blk; ++ n = blk_derase(mmc_get_blk_desc(mmc), start_blk, erase_cnt); ++ } ++ } else { ++ n = blk_derase(mmc_get_blk_desc(mmc), start_blk, 0); // erase the whole card ++ } ++ map = AML_BL_BOOT; ++ if (n == 0) ++ n = amlmmc_erase_bootloader(dev, map); ++ if (n) ++ printf("erase bootloader in boot partition failed\n"); ++ return (n == 0) ? 0 : 1; ++} ++ ++static int amlmmc_erase_non_cache(int arc, char *const argv[]) ++{ ++ char *name = NULL; ++ int dev; ++ u32 n = 0; ++ int blk_shift; ++ u64 blk = 0, start_blk = 0; ++ struct partitions *part_info; ++ struct mmc *mmc; ++ int map; ++ ++ name = "logo"; ++ dev = find_dev_num_by_partition_name(name); ++ if (dev < 0) { ++ printf("Cannot find dev.\n"); ++ return 1; ++ } ++ mmc = find_mmc_device(dev); ++ if (!mmc) ++ return 1; ++ mmc_init(mmc); ++ blk_shift = ffs(mmc->read_bl_len) -1; ++ if (emmckey_is_protected(mmc)) { ++ part_info = find_mmc_partition_by_name(MMC_RESERVED_NAME); ++ if (part_info == NULL) { ++ return 1; ++ } ++ ++ blk = part_info->offset; ++ // it means: there should be other partitions before reserve-partition. ++ if (blk > 0) { ++ blk -= PARTITION_RESERVED; ++ } ++ blk >>= blk_shift; ++ blk -= start_blk; ++ // (1) erase all the area before reserve-partition ++ if (blk > 0) { ++ n = blk_derase(mmc_get_blk_desc(mmc), start_blk, blk); ++ // printf("(1) erase blk: 0 --> %llx %s\n", blk, (n == 0) ? "OK" : "ERROR"); ++ } ++ if (n == 0) { // not error ++ // (2) erase all the area after reserve-partition ++ part_info = find_mmc_partition_by_name(MMC_CACHE_NAME); ++ if (part_info == NULL) { ++ return 1; ++ } ++ start_blk = (part_info->offset + part_info->size + PARTITION_RESERVED) ++ >> blk_shift; ++ u64 erase_cnt = (mmc->capacity >> blk_shift) - start_blk; ++ n = blk_derase(mmc_get_blk_desc(mmc), start_blk, erase_cnt); ++ } ++ } else { ++ n = blk_derase(mmc_get_blk_desc(mmc), start_blk, 0); // erase the whole card ++ } ++ map = AML_BL_BOOT; ++ if (n == 0) { ++ n = amlmmc_erase_bootloader(dev, map); ++ if (n) ++ printf("erase bootloader in boot partition failed\n"); ++ } ++ return (n == 0) ? 0 : 1; ++} ++ ++static int amlmmc_erase_dev(int argc, char *const argv[]) ++{ ++ return amlmmc_erase_whole(argc, argv); ++} ++ ++static int amlmmc_erase_allbootloader(int argc, char*const argv[]) ++{ ++ int map; ++ int rc; ++ char *name = NULL; ++ int dev; ++ map = AML_BL_ALL; ++ ++ name = "bootloader"; ++ dev = find_dev_num_by_partition_name(name); ++ ++ if (dev < 0) { ++ printf("Cannot find dev.\n"); ++ return 1; ++ } ++ ++ rc = amlmmc_erase_bootloader(dev, map); ++ return rc; ++} ++ ++static int amlmmc_erase_by_part(int argc, char *const argv[]) ++{ ++ int ret = CMD_RET_USAGE; ++ ++ if (argc != 3) ++ return ret; ++ ++ if (isdigit(argv[2][0])) ++ ret = amlmmc_erase_dev(argc, argv); ++ else if (strcmp(argv[2], "whole") == 0) ++ ret = amlmmc_erase_whole(argc, argv); ++ else if (strcmp(argv[2], "non_cache") == 0) ++ ret = amlmmc_erase_non_cache(argc, argv); ++ else if (strcmp(argv[2], "non_loader") == 0) ++ ret = amlmmc_erase_non_loader(argc, argv); ++ else if (strcmp(argv[2], "allbootloader") == 0) ++ ret = amlmmc_erase_allbootloader(argc, argv); ++ else ++ ret = amlmmc_erase_single_part(argc, argv); ++ return ret; ++} ++ ++static int do_amlmmc_erase(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ int ret = CMD_RET_USAGE; ++ ++ if (argc == 3) ++ ret = amlmmc_erase_by_part(argc, argv); ++ else if (argc == 5) ++ ret = amlmmc_erase_by_add(argc, argv); ++ ++ return ret; ++} ++ ++static int amlmmc_write_in_part(int argc, char *const argv[]) ++{ ++ int dev; ++ void *addr = NULL; ++ u64 cnt = 0, n = 0, blk = 0, sz_byte = 0; ++ char *name = NULL; ++ u64 offset = 0, size = 0; ++ //cpu_id_t cpu_id = get_cpu_id(); ++ struct mmc *mmc; ++ ++ name = argv[2]; ++ if (strcmp(name, "bootloader") == 0) ++ dev = CONFIG_SYS_MMC_BOOT_DEV; ++ else ++ dev = find_dev_num_by_partition_name (name); ++ addr = (void *)simple_strtoul(argv[3], NULL, 16); ++ offset = simple_strtoull(argv[4], NULL, 16); ++ size = simple_strtoull(argv[5], NULL, 16); ++ if (dev < 0) { ++ printf("Cannot find dev.\n"); ++ return 1; ++ } ++ mmc = find_mmc_device(dev); ++ if (!mmc) ++ return 1; ++ ++ if (strcmp(name, "bootloader") == 0) { ++ cnt = UBOOT_SIZE; ++ if (1) { //(cpu_id.family_id >= MESON_CPU_MAJOR_ID_GXL) { ++ blk = GXL_START_BLK; ++ cnt -= GXL_START_BLK; ++ } ++ else ++ blk = GXB_START_BLK; ++ } else ++ get_off_size(mmc, name, offset, size, &blk, &cnt, &sz_byte); ++ ++ mmc_init(mmc); ++ n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr); ++ //write sz_byte bytes ++ if ((n == cnt) && (sz_byte != 0)) { ++ // printf("sz_byte=%#llx bytes\n",sz_byte); ++ void *addr_tmp = malloc(mmc->write_bl_len); ++ void *addr_byte = (void*)(addr+cnt*(mmc->write_bl_len)); ++ ulong start_blk = blk+cnt; ++ ++ if (addr_tmp == NULL) { ++ printf("mmc write: malloc fail\n"); ++ return 1; ++ } ++ ++ if (blk_dread(mmc_get_blk_desc(mmc), start_blk, 1, addr_tmp) != 1) { // read 1 block ++ free(addr_tmp); ++ printf("mmc read 1 block fail\n"); ++ return 1; ++ } ++ ++ memcpy(addr_tmp, addr_byte, sz_byte); ++ if (blk_dwrite(mmc_get_blk_desc(mmc), start_blk, 1, addr_tmp) != 1) { // write 1 block ++ free(addr_tmp); ++ printf("mmc write 1 block fail\n"); ++ return 1; ++ } ++ free(addr_tmp); ++ } ++ //printf("%#llx blocks , %#llx bytes written: %s\n", n, sz_byte, (n==cnt) ? "OK" : "ERROR"); ++ return (n == cnt) ? 0 : 1; ++} ++ ++static int amlmmc_write_in_card(int argc, char *const argv[]) ++{ ++ int dev; ++ void *addr = NULL; ++ u64 cnt = 0, n = 0, blk = 0, sz_byte = 0; ++ char *name = NULL; ++ u64 offset = 0, size = 0; ++ struct mmc *mmc; ++ ++ name = argv[2]; ++ dev = find_dev_num_by_partition_name (name); ++ addr = (void *)simple_strtoul(argv[3], NULL, 16); ++ offset = simple_strtoull(argv[4], NULL, 16); ++ size = simple_strtoull(argv[5], NULL, 16); ++ if (dev < 0) { ++ printf("Cannot find dev.\n"); ++ return 1; ++ } ++ mmc = find_mmc_device(dev); ++ if (!mmc) ++ return 1; ++ ++ int blk_shift = ffs( mmc->read_bl_len) -1; ++ cnt = size >> blk_shift; ++ blk = offset >> blk_shift; ++ sz_byte = size - (cnt<write_bl_len); ++ void *addr_byte = (void*)(addr+cnt*(mmc->write_bl_len)); ++ ulong start_blk = blk+cnt; ++ ++ if (addr_tmp == NULL) { ++ printf("mmc write: malloc fail\n"); ++ return 1; ++ } ++ ++ if (blk_dread(mmc_get_blk_desc(mmc), start_blk, 1, addr_tmp) != 1) { // read 1 block ++ free(addr_tmp); ++ printf("mmc read 1 block fail\n"); ++ return 1; ++ } ++ ++ memcpy(addr_tmp, addr_byte, sz_byte); ++ if (blk_dwrite(mmc_get_blk_desc(mmc), start_blk, 1, addr_tmp) != 1) { // write 1 block ++ free(addr_tmp); ++ printf("mmc write 1 block fail\n"); ++ return 1; ++ } ++ free(addr_tmp); ++ } ++ //printf("%#llx blocks , %#llx bytes written: %s\n", n, sz_byte, (n==cnt) ? "OK" : "ERROR"); ++ return (n == cnt) ? 0 : 1; ++} ++ ++static int amlmmc_write_in_dev(int argc, char *const argv[]) ++{ ++ int dev; ++ void *addr = NULL; ++ u64 cnt = 0, n = 0, blk = 0; ++ struct mmc *mmc; ++ dev = simple_strtoul(argv[2], NULL, 10); ++ addr = (void *)simple_strtoul(argv[3], NULL, 16); ++ blk = simple_strtoull(argv[4], NULL, 16); ++ cnt = simple_strtoull(argv[5], NULL, 16); ++ if (dev < 0) { ++ printf("Cannot find dev.\n"); ++ return 1; ++ } ++ mmc = find_mmc_device(dev); ++ if (!mmc) ++ return 1; ++ ++ //printf("MMC write: dev # %d, block # %#llx, count # %#llx ... ", ++ //dev, blk, cnt); ++ ++ mmc_init(mmc); ++ ++ n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr); ++ return (n == cnt) ? 0 : 1; ++} ++ ++static int do_amlmmc_write(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ int ret = 0; ++ if (argc != 6) ++ return CMD_RET_USAGE; ++ ++ if (isdigit(argv[2][0])) ++ ret = amlmmc_write_in_dev(argc, argv); ++ else if (strcmp(argv[2], "card") == 0) ++ ret = amlmmc_write_in_card(argc, argv); ++ else if (isstring(argv[2])) ++ ret = amlmmc_write_in_part(argc, argv); ++ ++ return ret; ++} ++ ++static int amlmmc_read_in_dev(int argc, char *const argv[]) ++{ ++ int dev; ++ void *addr = NULL; ++ u64 cnt =0, n = 0, blk = 0; ++ struct mmc *mmc; ++ ++ dev = simple_strtoul(argv[2], NULL, 10); ++ addr = (void *)simple_strtoul(argv[3], NULL, 16); ++ blk = simple_strtoull(argv[4], NULL, 16); ++ cnt = simple_strtoull(argv[5], NULL, 16); ++ ++ if (dev < 0) { ++ printf("Cannot find dev.\n"); ++ return 1; ++ } ++ ++ mmc = find_mmc_device(dev); ++ if (!mmc) ++ return 1; ++ n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr); ++ return (n == cnt) ? 0 : 1; ++} ++ ++static int amlmmc_read_in_card(int argc, char *const argv[]) ++{ ++ int dev; ++ void *addr = NULL; ++ //u32 flag =0; ++ u64 cnt =0, n = 0, blk = 0, sz_byte = 0; ++ char *name = NULL; ++ u64 offset = 0, size = 0; ++ int blk_shift; ++ struct mmc *mmc; ++ void *addr_tmp; ++ void *addr_byte; ++ ulong start_blk; ++ ++ name = argv[2]; ++ dev = find_dev_num_by_partition_name (name); ++ addr = (void *)simple_strtoul(argv[3], NULL, 16); ++ size = simple_strtoull(argv[5], NULL, 16); ++ offset = simple_strtoull(argv[4], NULL, 16); ++ ++ if (dev < 0) { ++ printf("Cannot find dev.\n"); ++ return 1; ++ } ++ ++ mmc = find_mmc_device(dev); ++ if (!mmc) ++ return 1; ++ ++ blk_shift = ffs( mmc->read_bl_len) - 1; ++ cnt = size >> blk_shift; ++ blk = offset >> blk_shift; ++ sz_byte = size - (cnt<read_bl_len); ++ addr_byte = (void *)(addr+cnt*(mmc->read_bl_len)); ++ start_blk = blk+cnt; ++ if (addr_tmp == NULL) { ++ printf("mmc read: malloc fail\n"); ++ return 1; ++ } ++ if (blk_dread(mmc_get_blk_desc(mmc), start_blk, 1, addr_tmp) != 1) { // read 1 block ++ free(addr_tmp); ++ printf("mmc read 1 block fail\n"); ++ return 1; ++ } ++ memcpy(addr_byte, addr_tmp, sz_byte); ++ free(addr_tmp); ++ } ++ return (n == cnt) ? 0 : 1; ++} ++ ++static int amlmmc_read_in_part(int argc, char *const argv[]) ++{ ++ int dev; ++ void *addr = NULL; ++ u64 cnt = 0, n = 0, blk = 0, sz_byte = 0; ++ char *name = NULL; ++ u64 offset = 0, size = 0; ++ struct mmc *mmc; ++ void *addr_tmp; ++ void *addr_byte; ++ ulong start_blk; ++ ++ name = argv[2]; ++ dev = find_dev_num_by_partition_name (name); ++ addr = (void *)simple_strtoul(argv[3], NULL, 16); ++ offset = simple_strtoull(argv[4], NULL, 16); ++ size = simple_strtoull(argv[5], NULL, 16); ++ ++ if (dev < 0) { ++ printf("Cannot find dev.\n"); ++ return 1; ++ } ++ ++ mmc = find_mmc_device(dev); ++ if (!mmc) ++ return 1; ++ ++ get_off_size(mmc, name, offset, size, &blk, &cnt, &sz_byte); ++ mmc_init(mmc); ++ n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr); ++ ++ //read sz_byte bytes ++ if ((n == cnt) && (sz_byte != 0)) { ++ /*printf("sz_byte=%#llx bytes\n",sz_byte);*/ ++ addr_tmp = malloc(mmc->read_bl_len); ++ addr_byte = (void *)(addr+cnt*(mmc->read_bl_len)); ++ start_blk = blk+cnt; ++ ++ if (addr_tmp == NULL) { ++ printf("mmc read: malloc fail\n"); ++ return 1; ++ } ++ ++ if (blk_dread(mmc_get_blk_desc(mmc), start_blk, 1, addr_tmp) != 1) { // read 1 block ++ free(addr_tmp); ++ printf("mmc read 1 block fail\n"); ++ return 1; ++ } ++ ++ memcpy(addr_byte, addr_tmp, sz_byte); ++ free(addr_tmp); ++ } ++ return (n == cnt) ? 0 : 1; ++} ++ ++static int do_amlmmc_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ int ret = 0; ++ if (argc != 6) ++ return CMD_RET_USAGE; ++ ++ if (isdigit(argv[2][0])) ++ ret = amlmmc_read_in_dev(argc, argv); ++ else if (strcmp(argv[2], "card") == 0) ++ ret = amlmmc_read_in_card(argc, argv); ++ else if (isstring(argv[2])) ++ ret = amlmmc_read_in_part(argc, argv); ++ ++ return ret; ++} ++ ++static int do_amlmmc_env(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ printf("herh\n"); ++ env_relocate(); ++ return 0; ++} ++ ++static int do_amlmmc_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ print_mmc_devices('\n'); ++ return 0; ++} ++ ++static int do_amlmmc_size(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ char *name; ++ uint64_t* addr = NULL; ++ int dev; ++ struct mmc *mmc = NULL; ++ ++ if (argc != 4) ++ return CMD_RET_USAGE; ++ ++ name = argv[2]; ++ addr = (uint64_t *)simple_strtoul(argv[3], NULL, 16); ++ if (!strcmp(name, "wholeDev")) { ++ dev = CONFIG_SYS_MMC_BOOT_DEV; ++ mmc = find_mmc_device(dev); ++ if (!mmc) { ++ puts("no mmc devices available\n"); ++ return 1; ++ } ++ mmc_init(mmc); ++ ++ *addr = mmc->capacity >> 9; // unit: 512 bytes ++ return 0; ++ } ++ return get_partition_size((unsigned char *)name, addr); ++} ++ ++static int amlmmc_get_ext_csd(int argc, char *const argv[]) ++{ ++ int ret= 0; ++ u8 ext_csd[512] = {0}; ++ int dev, byte; ++ struct mmc *mmc; ++ ++ if (argc != 4) ++ return CMD_RET_USAGE; ++ ++ dev = simple_strtoul(argv[2], NULL, 10); ++ byte = simple_strtoul(argv[3], NULL, 10); ++ mmc = find_mmc_device(dev); ++ ++ if (!mmc) { ++ puts("no mmc devices available\n"); ++ return 1; ++ } ++ mmc_init(mmc); ++ ret = mmc_get_ext_csd(mmc, ext_csd); ++ printf("read EXT_CSD byte[%d] val[0x%x] %s\n", ++ byte, ext_csd[byte], (ret == 0) ? "ok" : "fail"); ++ ret = ret || ret; ++ return ret; ++} ++ ++static int amlmmc_set_ext_csd(int argc, char *const argv[]) ++{ ++ int ret = 0; ++ int dev, byte; ++ struct mmc *mmc; ++ int val; ++ ++ if (argc != 5) ++ return CMD_RET_USAGE; ++ ++ dev = simple_strtoul(argv[2], NULL, 10); ++ byte = simple_strtoul(argv[3], NULL, 10); ++ val = simple_strtoul(argv[4], NULL, 16); ++ if ((byte > 191) || (byte < 0)) { ++ printf("byte is not able to write!\n"); ++ return 1; ++ } ++ ++ mmc = find_mmc_device(dev); ++ ++ if (!mmc) { ++ puts("no mmc devices available\n"); ++ return 1; ++ } ++ ++ mmc_init(mmc); ++ ++ ret = mmc_set_ext_csd(mmc, byte, val); ++ printf("write EXT_CSD byte[%d] val[0x%x] %s\n", ++ byte, val, (ret == 0) ? "ok" : "fail"); ++ ret =ret || ret; ++ return ret; ++} ++ ++static int do_amlmmc_ext_csd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ int ret = CMD_RET_USAGE; ++ ++ if (argc == 4) ++ ret = amlmmc_get_ext_csd(argc,argv); ++ else if (argc == 5) ++ ret = amlmmc_set_ext_csd(argc,argv); ++ ++ return ret; ++} ++ ++static int do_amlmmc_switch(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ int rc = 0; ++ int dev; ++ struct mmc *mmc; ++ ++ if (argc != 4) ++ return CMD_RET_USAGE; ++ ++ dev = simple_strtoul(argv[2], NULL, 10); ++ mmc = find_mmc_device(dev); ++ ++ if (!mmc) { ++ puts("no mmc devices available\n"); ++ return 1; ++ } ++ ++ mmc_init(mmc); ++ printf("mmc switch to "); ++ ++ if (strcmp(argv[3], "boot0") == 0) { ++ rc = mmc_switch_part(mmc, 1); ++ if (rc == 0) { ++ emmc_cur_partition = 1; ++ printf("boot0 success\n"); ++ } else { ++ printf("boot0 failed\n"); ++ } ++ } ++ else if(strcmp(argv[3], "boot1") == 0) { ++ rc = mmc_switch_part(mmc, 2); ++ if (rc == 0) { ++ emmc_cur_partition = 2; ++ printf("boot1 success\n"); ++ } else { ++ printf("boot1 failed\n"); ++ } ++ } ++ else if(strcmp(argv[3], "user") == 0) { ++ rc = mmc_switch_part(mmc, 0); ++ if (rc == 0) { ++ emmc_cur_partition = 0; ++ printf("user success\n"); ++ } else { ++ printf("user failed\n"); ++ } ++ } ++#ifdef CONFIG_SUPPORT_EMMC_RPMB ++ else if(strcmp(argv[3], "rpmb") == 0) { ++ rc = mmc_switch_part(mmc, 3); ++ if (rc == 0) { ++ emmc_cur_partition = 3; ++ printf("rpmb success\n"); ++ } else { ++ printf("rpmb failed\n"); ++ } ++ } ++#endif ++ else ++ printf("%s failed\n", argv[3]); ++ return rc; ++} ++ ++static int do_amlmmc_controller(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ /*int dev; ++ struct mmc *mmc; ++ struct aml_card_sd_info *aml_priv; ++ struct sd_emmc_global_regs *sd_emmc_reg; ++ ++ if (argc != 3) ++ return CMD_RET_USAGE; ++ ++ dev = simple_strtoul(argv[2], NULL, 10); ++ ++ if (dev < 0) { ++ printf("Cannot find dev.\n"); ++ return 1; ++ } ++ ++ mmc = find_mmc_device(dev); ++ ++ if (!mmc) ++ return 1; ++ ++ aml_priv = mmc->priv; ++ sd_emmc_reg = aml_priv->sd_emmc_reg; ++ ++ printf("sd_emmc_reg->gclock = 0x%x\n", sd_emmc_reg->gclock); ++ printf("sd_emmc_reg->gdelay = 0x%x\n", sd_emmc_reg->gdelay); ++ printf("sd_emmc_reg->gadjust = 0x%x\n", sd_emmc_reg->gadjust); ++ printf("sd_emmc_reg->gcalout = 0x%x\n", sd_emmc_reg->gcalout); ++ if (!mmc->has_init) { ++ printf("mmc dev %d has not been initialed\n", dev); ++ return 1; ++ } ++ printf("sd_emmc_reg->gstart = 0x%x\n", sd_emmc_reg->gstart); ++ printf("sd_emmc_reg->gcfg = 0x%x\n", sd_emmc_reg->gcfg); ++ printf("sd_emmc_reg->gstatus = 0x%x\n", sd_emmc_reg->gstatus); ++ printf("sd_emmc_reg->girq_en = 0x%x\n", sd_emmc_reg->girq_en); ++ printf("sd_emmc_reg->gcmd_cfg = 0x%x\n", sd_emmc_reg->gcmd_cfg); ++ printf("sd_emmc_reg->gcmd_arg = 0x%x\n", sd_emmc_reg->gcmd_arg); ++ printf("sd_emmc_reg->gcmd_dat = 0x%x\n", sd_emmc_reg->gcmd_dat); ++ printf("sd_emmc_reg->gcmd_rsp0 = 0x%x\n", sd_emmc_reg->gcmd_rsp0); ++ printf("sd_emmc_reg->gcmd_rsp1 = 0x%x\n", sd_emmc_reg->gcmd_rsp1); ++ printf("sd_emmc_reg->gcmd_rsp2 = 0x%x\n", sd_emmc_reg->gcmd_rsp2); ++ printf("sd_emmc_reg->gcmd_rsp3 = 0x%x\n", sd_emmc_reg->gcmd_rsp3);*/ ++ return 0; ++} ++ ++static int do_amlmmc_response(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ /*int dev; ++ struct mmc *mmc; ++ struct aml_card_sd_info *aml_priv; ++ struct sd_emmc_global_regs *sd_emmc_reg; ++ ++ if (argc != 3) ++ return CMD_RET_USAGE; ++ ++ dev = simple_strtoul(argv[2], NULL, 10); ++ ++ if (dev < 0) { ++ printf("Cannot find dev.\n"); ++ return 1; ++ } ++ ++ mmc = find_mmc_device(dev); ++ ++ if (!mmc) ++ return 1; ++ if (!mmc->has_init) { ++ printf("mmc dev %d has not been initialed\n", dev); ++ return 1; ++ } ++ ++ aml_priv = mmc->priv; ++ sd_emmc_reg = aml_priv->sd_emmc_reg; ++ ++ printf("last cmd = %d, response0 = 0x%x\n", ++ (sd_emmc_reg->gcmd_cfg & 0x3f), sd_emmc_reg->gcmd_rsp0);*/ ++ return 0; ++} ++ ++static int do_amlmmc_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ int rc = 0; ++ int dev; ++ struct mmc *mmc; ++ ++ if (argc != 3) ++ return CMD_RET_USAGE; ++ ++ dev = simple_strtoul(argv[2], NULL, 10); ++ ++ if (dev < 0) { ++ printf("Cannot find dev.\n"); ++ return 1; ++ } ++ mmc = find_mmc_device(dev); ++ ++ if (!mmc) ++ return 1; ++ if (!mmc->has_init) { ++ printf("mmc dev %d has not been initialed\n", dev); ++ return 1; ++ } ++ rc = mmc_read_status(mmc, 1000); ++ if (rc) ++ return 1; ++ else ++ return 0; ++} ++ ++static int do_amlmmc_part(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ int dev; ++ struct blk_desc *mmc_dev; ++ struct mmc *mmc; ++ ++ if (argc != 3) ++ return CMD_RET_USAGE; ++ ++ dev = simple_strtoul(argv[2], NULL, 10); ++ mmc = find_mmc_device(dev); ++ ++ if (!mmc) { ++ puts("no mmc devices available\n"); ++ return 1; ++ } ++ mmc_init(mmc); ++ mmc_dev = mmc_get_blk_desc(mmc); ++ if (mmc_dev != NULL && ++ mmc_dev->type != DEV_TYPE_UNKNOWN) { ++ part_print(mmc_dev); ++ return 0; ++ } ++ puts("get mmc type error!\n"); ++ return 1; ++} ++ ++static int do_amlmmc_rescan(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ int dev; ++ struct mmc *mmc; ++ ++ if (argc != 3) ++ return CMD_RET_USAGE; ++ ++ dev = simple_strtoul(argv[2], NULL, 10); ++ ++ if (dev < 0) { ++ printf("Cannot find dev.\n"); ++ return 1; ++ } ++ ++ mmc = find_mmc_device(dev); ++ ++ if (!mmc) ++ return 1; ++ mmc->has_init =0; ++ return mmc_init(mmc); ++} ++ ++#ifdef CONFIG_SECURITYKEY ++static int do_amlmmc_key(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ struct mmc *mmc; ++ int dev; ++ ++ //char *name = "logo"; ++ dev = CONFIG_SYS_MMC_BOOT_DEV; ++ mmc = find_mmc_device(dev); ++ if (!mmc) { ++ printf("device %d is invalid\n",dev); ++ return 1; ++ } ++ //mmc->key_protect = 0; ++#ifdef CONFIG_STORE_COMPATIBLE ++ info_disprotect |= DISPROTECT_KEY; //disprotect ++ printf("emmc disprotect key\n"); ++#endif ++ return 0; ++} ++#endif ++ ++static int set_write_prot(struct mmc *mmc, u64 start) ++{ ++ struct mmc_cmd cmd; ++ int err; ++ ++ cmd.cmdidx = MMC_CMD_SET_WRITE_PROTECT; ++ cmd.cmdarg = start; ++ cmd.resp_type = MMC_RSP_R1b; ++ ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ if (err) ++ goto err_out; ++ ++ return 0; ++ ++err_out: ++ puts("Failed: mmc write protect failed\n"); ++ return err; ++} ++ ++static int set_us_wp_en(struct mmc *mmc, u8 *ext_csd, u8 wp_enable_type) ++{ ++ u8 index = EXT_CSD_USER_WP; ++ u8 user_wp = ext_csd[index]; ++ user_wp = user_wp & (~WP_ENABLE_MASK); ++ user_wp = user_wp | wp_enable_type; ++ int err = 0; ++ err = mmc_set_ext_csd(mmc, index, user_wp); ++ if (err) ++ printf("Failed: set write protect enable failed\n"); ++ return err; ++} ++ ++static int mmc_set_us_perm_wp_dis(struct mmc *mmc, u8 *ext_csd) ++{ ++ u8 usr_wp = ext_csd[EXT_CSD_USER_WP]; ++ u8 perm_disable_bit = US_PERM_WP_DIS_BIT; ++ ++ int err; ++ if (usr_wp & perm_disable_bit) ++ return 0; ++ ++ usr_wp = usr_wp | perm_disable_bit; ++ err = mmc_set_ext_csd(mmc, EXT_CSD_USER_WP, usr_wp); ++ if (err) { ++ printf("Failed: set permanent write protect disable failed\n"); ++ return 1; ++ } ++ return 0; ++} ++ ++static int mmc_is_us_pwr_wp_dis(u8 user_wp) ++{ ++ return user_wp & US_PWR_WP_DIS_BIT; ++} ++ ++static int mmc_is_us_perm_wp_dis(u8 user_wp) ++{ ++ return user_wp & US_PERM_WP_DIS_BIT; ++} ++ ++static int check_wp_type(u8 *addr, u8 wp_type, u64 set_protect_cnt) ++{ ++ u8 type_mask = WP_TYPE_MASK; ++ u64 cnt = set_protect_cnt; ++ u8 times = 0; ++ u8 index = 7; ++ u8 cur_group_wp_type = addr[index]; ++ ++ while (cnt != 0) { ++ if (wp_type != ((type_mask)&(cur_group_wp_type))) { ++ return 1; ++ } ++ if (times == 3) { ++ times = 0; ++ index--; ++ cur_group_wp_type = addr[index]; ++ } ++ else { ++ cur_group_wp_type = cur_group_wp_type >> 2; ++ times++; ++ } ++ cnt--; ++ } ++ return 0; ++} ++ ++static int set_register_to_temporary(struct mmc *mmc, u8 *ext_csd) ++{ ++ int err; ++ u8 wp_enable_type = WP_TEMPORARY_EN_BIT; ++ err = set_us_wp_en(mmc, ext_csd, wp_enable_type); ++ if (err) ++ printf("Failed: set temporary write protect failed\n"); ++ return err; ++} ++ ++static int set_register_to_pwr(struct mmc *mmc, u8 *ext_csd) ++{ ++ int err; ++ u8 user_wp = ext_csd[EXT_CSD_USER_WP]; ++ u8 wp_enable_type = WP_POWER_ON_EN_BIT; ++ if (mmc_is_us_pwr_wp_dis(user_wp)) { ++ printf("Failed: power on protection had been disabled\n"); ++ return 1; ++ } ++ ++ err = mmc_set_us_perm_wp_dis(mmc, ext_csd); ++ if (err) { ++ printf("Failed: set permanent protection diable failed\n"); ++ return 1; ++ } ++ ++ err = set_us_wp_en(mmc, ext_csd, wp_enable_type); ++ if (err) { ++ printf("Failed: set power on write protect enable failed\n"); ++ return 1; ++ } ++ return 0; ++} ++ ++static int set_register_to_perm(struct mmc *mmc, u8 *ext_csd) ++{ ++ int err; ++ u8 wp_enable_type = WP_PERM_EN_BIT; ++ u8 user_wp = ext_csd[EXT_CSD_USER_WP]; ++ ++ if (mmc_is_us_perm_wp_dis(user_wp)) { ++ printf("Failed: Permanent protection had been disabled\n"); ++ return 1; ++ } ++ ++ err = set_us_wp_en(mmc, ext_csd, wp_enable_type); ++ if (err) { ++ printf("Failed: set permanent write protect enable failed\n"); ++ return 1; ++ } ++ return 0; ++} ++ ++static int set_wp_register(struct mmc *mmc, u8 *ext_csd, u8 wp_type) ++{ ++ int ret = 1; ++ if (wp_type == WP_POWER_ON_TYPE) ++ ret = set_register_to_pwr(mmc, ext_csd); ++ else if (wp_type == WP_PERMANENT_TYPE) ++ ret = set_register_to_perm(mmc, ext_csd); ++ else if (wp_type == WP_TEMPORARY_TYPE) ++ ret = set_register_to_temporary(mmc, ext_csd); ++ return ret; ++} ++ ++static u64 write_protect_group_size(struct mmc *mmc, u8 *ext_csd) ++{ ++ int erase_group_def = ext_csd[EXT_CSD_ERASE_GROUP_DEF]; ++ u64 write_protect_group_size; ++ int wp_grp_size = mmc->csd[2] & WP_GRP_SIZE_MASK; ++ int hc_wp_grp_size = ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; ++ ++ if (erase_group_def == 0) ++ write_protect_group_size = (wp_grp_size + 1) * mmc->erase_grp_size; ++ else ++ write_protect_group_size = hc_wp_grp_size * mmc->erase_grp_size; ++ ++ return write_protect_group_size; ++} ++ ++int is_write_protect_valid(u8 *ext_csd) ++{ ++ u8 class_6_ctrl = ext_csd[EXT_CSD_CLASS_6_CTRL]; ++ if (class_6_ctrl == 0) ++ return 1; ++ return 0; ++} ++ ++static int compute_write_protect_range(struct mmc *mmc, char *name, ++ u8 *ext_csd, u64 *wp_grp_size_addr, u64 *start_addr, u64 *end) ++{ ++ int blk_shift; ++ struct partitions *part_info; ++ u64 cnt; ++ u64 start = *start_addr; ++ u64 align_start = *start_addr; ++ u64 wp_grp_size = *wp_grp_size_addr; ++ u64 group_num ; ++ u64 partition_end; ++ ++ wp_grp_size = write_protect_group_size(mmc, ext_csd); ++ ++ blk_shift = ffs(mmc->read_bl_len) -1; ++ ++ part_info = find_mmc_partition_by_name(name); ++ if (part_info == NULL) ++ return 1; ++ ++ start = part_info->offset >> blk_shift; ++ printf("start:%d wp_grp_size:%d",(int)start,(int)wp_grp_size); ++ if ((start % wp_grp_size)) { ++ align_start = (start + wp_grp_size - 1) / wp_grp_size * wp_grp_size; ++ printf("Caution! The partition start address isn't' aligned" ++ "to group size\n" ++ "the start address is change from 0x%llx to 0x%llx\n", ++ start, align_start); ++ } else { ++ align_start = start; ++ } ++ if (emmc_cur_partition && !strncmp(name, "bootloader", strlen("bootloader"))) ++ cnt =0; ++ else ++ cnt = part_info->size >> blk_shift; ++ if (cnt < wp_grp_size) { ++ printf("Caution: The partition size is 0x%llx sector smaller than " ++ "the group size 0x%llx sector, \n" ++ "so the partition can't be protect\n", cnt, wp_grp_size); ++ return 1; ++ } ++ ++ *start_addr = align_start; ++ *wp_grp_size_addr = wp_grp_size; ++ partition_end = start + cnt - 1; ++ group_num = (cnt - (align_start - start)) / wp_grp_size; ++ *end = align_start + group_num * wp_grp_size - 1; ++ ++ if (partition_end != *end) { ++ printf("Caution! The boundary of partition isn't aligned with write " ++ "protected group,\n" ++ "so the write protected boundry of the " ++ "partition is 0x%llx, rather than 0x%llx\n", ++ *end, partition_end); ++ } ++ ++ printf("write_protect group size is 0x%llx sector\n", wp_grp_size); ++ printf("The %s partition write protect group number is %lld\n", name, group_num); ++#ifdef WP_DEBUG ++ printf("the start address is 0x%llx, group size is 0x%llx, end is 0x%llx\n", ++ *start_addr, *wp_grp_size_addr, *end); ++#endif ++ return 0; ++} ++ ++static int send_wp_prot_type(struct mmc *mmc, void *dst, u64 blk) ++{ ++ struct mmc_cmd cmd; ++ int err; ++ struct mmc_data data; ++ ++ cmd.cmdidx = MMC_CMD_SEND_WRITE_PROT_TYPE; ++ cmd.cmdarg = blk; ++ cmd.resp_type = MMC_RSP_R1; ++ ++ data.dest = dst; ++ data.blocks = 1; ++ data.blocksize = 8; ++ data.flags = MMC_DATA_READ; ++ ++ err = mmc_send_cmd(mmc, &cmd, &data); ++ if (err) ++ goto err_out; ++ ++ return 0; ++ ++err_out: ++ puts("Failed: mmc send write protect type failed\n"); ++ return err; ++} ++ ++static int is_wp_set_failed(struct mmc *mmc, u8 wp_type, u64 start, u64 group_cnt) ++{ ++ u8 *addr = NULL; ++ u8 err = 0; ++ ++ addr = malloc(sizeof(u64)); ++ if (addr == NULL) { ++ printf("Failed: malloc failed\n"); ++ return 1; ++ } ++ ++ err = send_wp_prot_type(mmc, addr, start); ++ if (err) ++ goto err_out; ++ ++#ifdef WP_DEBUG ++ int i; ++ for (i = 0; i < 8; i++) ++ printf("write_protect status is %x\n", ((u8 *)addr)[i]); ++#endif ++ if (check_wp_type(addr, wp_type, group_cnt)) { ++ printf("Failed: Write Protection set failed\n"); ++ goto err_out; ++ } ++ return 0; ++ ++err_out: ++ free(addr); ++ return 1; ++} ++ ++static int send_part_wp_type(struct mmc *mmc, char *name) ++{ ++ int err = 0; ++ u8 ext_csd[512] = {0}; ++ u64 wp_grp_size, start, part_end; ++ u64 group_start; ++ void *addr = NULL; ++ int i; ++ int ret; ++ ++ ret = mmc_get_ext_csd(mmc, ext_csd); ++ if (ret) { ++ printf("Failed: get ext_csd failed\n"); ++ return 1; ++ } ++ ++ if (!is_write_protect_valid(ext_csd)) { ++ printf("Failed: CLASS_6_CTRL isn't '0' " ++ "write protect process is invalid\n"); ++ return 1; ++ } ++ ++ addr = malloc(sizeof(u64)); ++ if (addr == NULL) { ++ printf("Failed: malloc failed\n"); ++ return 1; ++ } ++ ++ err = compute_write_protect_range(mmc, name, ext_csd, ++ &wp_grp_size, &start, &part_end); ++ if (err) ++ return 1; ++ ++ group_start = start; ++ ++ while ((group_start + wp_grp_size - 1) <= part_end) { ++ err = send_wp_prot_type(mmc, addr, group_start); ++ if (err) ++ return 1; ++ printf("The write protect type for the 32 groups after 0x%llx is: \n0x", ++ group_start); ++ for (i = 0; i < 8; i++) ++ printf("%02x", ((u8*)addr)[i]); ++ printf("\n"); ++ group_start += 32 * wp_grp_size; ++ } ++ return 0; ++} ++ ++static int send_add_wp_type(struct mmc *mmc, u64 start, u64 cnt) ++{ ++ u8 ext_csd[512] = {0}; ++ u64 wp_grp_size = 0; ++ u64 part_end = 0; ++ u64 group_start; ++ u64 mmc_boundary; ++ int blk_shift; ++ void *addr = NULL; ++ int i; ++ int ret; ++ ++ ret = mmc_get_ext_csd(mmc, ext_csd); ++ if (ret) { ++ printf("Failed: get ext_csd failed\n"); ++ return 1; ++ } ++ ++ if (!is_write_protect_valid(ext_csd)) { ++ printf("Failed: CLASS_6_CTRL isn't '0' " ++ "write protect process is invalid\n"); ++ return 1; ++ } ++ ++ addr = malloc(sizeof(u64)); ++ if (addr == NULL) { ++ printf("Failed: malloc failed\n"); ++ return 1; ++ } ++ ++ wp_grp_size = write_protect_group_size(mmc, ext_csd); ++ ++ if ((start % wp_grp_size)) { ++ group_start = (start + wp_grp_size - 1) / wp_grp_size * wp_grp_size; ++ printf("Caution! The partition start address isn't' aligned" ++ "to group size\n" ++ "the start address is change from 0x%llx to 0x%llx\n", ++ start, group_start); ++ part_end = group_start + (cnt - 1) * wp_grp_size - 1; ++ printf("The write protect group number is 0x%llx, rather than 0x%lld\n", ++ cnt - 1, cnt); ++ } else { ++ group_start = start; ++ part_end = group_start + cnt * wp_grp_size - 1; ++ } ++ ++ blk_shift = ffs(mmc->read_bl_len) - 1; ++ mmc_boundary = mmc->capacity>>blk_shift; ++ ++ if ((part_end + 1) > mmc_boundary) { ++ printf("Error: the operation cross the boundary of mmc\n"); ++ return 1; ++ } ++ ++ while ((group_start + wp_grp_size - 1) <= part_end) { ++ ret = send_wp_prot_type(mmc, addr, group_start); ++ if (ret) ++ return 1; ++ printf("The write protect type for the 32 groups after 0x%llx is: \n0x", ++ group_start); ++ for (i = 0; i < 8; i++) ++ printf("%02x", ((u8*)addr)[i]); ++ printf("\n"); ++ group_start += 32 * wp_grp_size; ++ } ++ return 0; ++} ++ ++static int set_part_write_protect(struct mmc *mmc, u8 wp_type, char *name) ++{ ++ int err = 0; ++ u8 ext_csd[512] = {0}; ++ u8 group_num = 32; ++ u64 wp_grp_size, start, part_end; ++ u64 group_start; ++ u64 check_group_start; ++ u64 set_protect_cnt = 0; ++ ++ err = mmc_get_ext_csd(mmc, ext_csd); ++ if (err) { ++ printf("Failed: get ext_csd failed\n"); ++ return 1; ++ } ++ ++ if (!is_write_protect_valid(ext_csd)) { ++ printf("Failed: CLASS_6_CTRL isn't '0' " ++ "write protect process is invalid\n"); ++ return 1; ++ } ++ ++ err = compute_write_protect_range(mmc, name, ext_csd, ++ &wp_grp_size, &start, &part_end); ++ if (err) ++ return 1; ++ ++ group_start = start; ++ err = set_wp_register(mmc, ext_csd, wp_type); ++ if (err) ++ return 1; ++ while ((group_start + wp_grp_size - 1) <= part_end) { ++ err = set_write_prot(mmc, group_start); ++ if (err) ++ return 1; ++ group_start += wp_grp_size; ++ set_protect_cnt++; ++//check write protect type every 32 group ++ if (set_protect_cnt % 32 == 0) { ++ check_group_start = group_start - group_num * wp_grp_size; ++ err = is_wp_set_failed(mmc, wp_type, check_group_start, group_num); ++ if (err) ++ return 1; ++ } ++ } ++ ++ group_num = set_protect_cnt % 32; ++ check_group_start = group_start - group_num * wp_grp_size; ++ ++ if (group_num) { ++ err = is_wp_set_failed(mmc, wp_type, check_group_start, group_num); ++ if (err) ++ return 1; ++ } ++ ++ return 0; ++} ++ ++static int set_add_write_protect(struct mmc *mmc, u8 wp_type, u64 start, u64 cnt) ++{ ++ int err = 0; ++ u8 ext_csd[512] = {0}; ++ int group_num = 32; ++ u64 wp_grp_size, part_end; ++ u64 group_start; ++ u64 check_group_start; ++ u64 set_protect_cnt = 0; ++ u64 mmc_boundary = 0; ++ int blk_shift; ++ err = mmc_get_ext_csd(mmc, ext_csd); ++ ++ if (err) { ++ printf("Failed: get ext_csd failed\n"); ++ return 1; ++ } ++ ++ if (!is_write_protect_valid(ext_csd)) { ++ printf("Failed: CLASS_6_CTRL isn't '0' " ++ "write protect process is invalid\n"); ++ return 1; ++ } ++ ++ if (err) ++ return 1; ++ ++ wp_grp_size = write_protect_group_size(mmc, ext_csd); ++ ++ if ((start % wp_grp_size)) { ++ group_start = (start + wp_grp_size - 1) / wp_grp_size * wp_grp_size; ++ printf("Caution! The partition start address isn't' aligned" ++ "to group size\n" ++ "the start address is change from 0x%llx to 0x%llx\n", ++ start, group_start); ++ part_end = group_start + (cnt - 1) * wp_grp_size - 1; ++ printf("The write protect group number is 0x%llx, rather than 0x%lld\n", ++ cnt - 1, cnt); ++ } else { ++ group_start = start; ++ part_end = group_start + cnt * wp_grp_size - 1; ++ } ++ ++ blk_shift = ffs(mmc->read_bl_len) - 1; ++ mmc_boundary = mmc->capacity>>blk_shift; ++ ++ if ((part_end + 1) > mmc_boundary) { ++ printf("Error: the operation cross the boundary of mmc\n"); ++ return 1; ++ } ++ ++ err = set_wp_register(mmc, ext_csd, wp_type); ++ if (err) ++ return 1; ++ ++ while ((group_start + wp_grp_size - 1) <= part_end) { ++ err = set_write_prot(mmc, group_start); ++ if (err) ++ return 1; ++ group_start += wp_grp_size; ++ set_protect_cnt++; ++//check write protect type every 32 group ++ if (set_protect_cnt % 32 == 0) { ++ check_group_start = group_start - group_num * wp_grp_size; ++ err = is_wp_set_failed(mmc, wp_type, check_group_start, group_num); ++ if (err) ++ return 1; ++ } ++ } ++ ++ group_num = set_protect_cnt % 32; ++ check_group_start = group_start - group_num * wp_grp_size; ++ ++ if (group_num) { ++ err = is_wp_set_failed(mmc, wp_type, check_group_start, group_num); ++ if (err) ++ return 1; ++ } ++ ++ return 0; ++} ++ ++static int do_amlmmc_write_protect(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ int ret = CMD_RET_USAGE; ++ struct mmc *mmc; ++ int dev = 1; ++ char *name = NULL; ++ char *wp_type_str = NULL; ++ u8 write_protect_type; ++ u64 start, cnt; ++ ++ if (argc > 5 || argc < 4) ++ return ret; ++ if (argc == 4) { ++ name = argv[2]; ++ wp_type_str = argv[3]; ++ dev = find_dev_num_by_partition_name(name); ++ if (dev < 0) { ++ printf("Error: Cannot find dev.\n"); ++ return CMD_RET_USAGE; ++ } ++ } else { ++ start = simple_strtoull(argv[2], NULL, 16); ++ cnt = simple_strtoull(argv[3], NULL, 0); ++ wp_type_str = argv[4]; ++ } ++ ++ mmc = find_mmc_device(dev); ++ ++ if (IS_SD(mmc)) { ++ mmc = find_mmc_device(~dev); ++ if (IS_SD(mmc)) { ++ printf("SD card can not be write protect\n"); ++ return 1; ++ } ++ } ++ ++ if (!mmc) ++ return 1; ++ ++ mmc_init(mmc); ++ if (!mmc) ++ return 1; ++ ++ if (strcmp(wp_type_str, "temporary") == 0) ++ write_protect_type = WP_TEMPORARY_TYPE; ++ else if (strcmp(wp_type_str, "power_on") == 0 ) ++ write_protect_type = WP_POWER_ON_TYPE; ++ else if (strcmp(wp_type_str, "permanent") == 0) ++ write_protect_type = WP_PERMANENT_TYPE; ++ else ++ return ret; ++ ++ if (argc == 4) ++ ret = set_part_write_protect(mmc, write_protect_type, name); ++ else ++ ret = set_add_write_protect(mmc, write_protect_type, start, cnt); ++ ++ return ret; ++} ++ ++static int clear_write_prot_per_group(struct mmc *mmc, u64 blk) ++{ ++ struct mmc_cmd cmd; ++ int err; ++ ++ cmd.cmdidx = MMC_CMD_CLR_WRITE_PROT; ++ cmd.cmdarg = blk; ++ cmd.resp_type = MMC_RSP_R1b; ++ ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ ++ return err; ++} ++ ++static int set_part_clear_wp(struct mmc *mmc, char *name) ++{ ++ int err = 0; ++ u8 ext_csd[512] = {0}; ++ u8 group_num = 32; ++ u64 wp_grp_size, start, part_end; ++ u64 group_start; ++ u64 check_group_start; ++ u64 set_protect_cnt = 0; ++ u8 wp_type = WP_CLEAR_TYPE; ++ ++ err = mmc_get_ext_csd(mmc, ext_csd); ++ if (err) { ++ printf("get ext_csd failed\n"); ++ return 1; ++ } ++ ++ if (!is_write_protect_valid(ext_csd)) { ++ printf("CLASS_6_CTRL isn't '0' write protect process is invalid\n"); ++ return 1; ++ } ++ ++ err = compute_write_protect_range(mmc, name, ext_csd, ++ &wp_grp_size, &start, &part_end); ++ if (err) ++ return 1; ++ ++ group_start = start; ++/* ++ if (!is_wp_type_temporary(ext_csd)) { ++ printf("The write protect can't be clear\n"); ++ return 1; ++ } ++*/ ++ while ((group_start + wp_grp_size - 1) <= part_end) { ++ err = clear_write_prot_per_group(mmc, group_start); ++ if (err) { ++ printf("Error: The write protect can't be clear\n"); ++ return 1; ++ } ++ group_start += wp_grp_size; ++ set_protect_cnt++; ++//check write protect type every 32 group ++ if (set_protect_cnt % 32 == 0) { ++ check_group_start = group_start - group_num * wp_grp_size; ++ err = is_wp_set_failed(mmc, wp_type, check_group_start, group_num); ++ if (err) ++ return 1; ++ } ++ } ++ ++ group_num = set_protect_cnt % 32; ++ check_group_start = group_start - group_num * wp_grp_size; ++ ++ if (group_num) { ++ err = is_wp_set_failed(mmc, wp_type, check_group_start, group_num); ++ if (err) ++ return 1; ++ } ++ ++ return 0; ++} ++ ++static int set_add_clear_wp(struct mmc *mmc, u64 start, u64 cnt) ++{ ++ int err = 0; ++ u8 ext_csd[512] = {0}; ++ u8 group_num = 32; ++ u64 wp_grp_size, part_end; ++ u64 group_start; ++ u64 check_group_start; ++ u64 set_protect_cnt = 0; ++ u8 wp_type = WP_CLEAR_TYPE; ++ int blk_shift; ++ u64 mmc_boundary; ++ ++ err = mmc_get_ext_csd(mmc, ext_csd); ++ if (err) { ++ printf("get ext_csd failed\n"); ++ return 1; ++ } ++ ++ if (!is_write_protect_valid(ext_csd)) { ++ printf("CLASS_6_CTRL isn't '0' write protect process is invalid\n"); ++ return 1; ++ } ++ ++ wp_grp_size = write_protect_group_size(mmc, ext_csd); ++ ++ if ((start % wp_grp_size)) { ++ group_start = (start + wp_grp_size - 1) / wp_grp_size * wp_grp_size; ++ printf("Caution! The partition start address isn't' aligned" ++ "to group size\n" ++ "the start address is change from 0x%llx to 0x%llx\n", ++ start, group_start); ++ part_end = group_start + (cnt - 1) * wp_grp_size - 1; ++ printf("The write protect group number is 0x%llx, rather than 0x%lld\n", ++ cnt - 1, cnt); ++ } else { ++ group_start = start; ++ part_end = group_start + cnt * wp_grp_size - 1; ++ } ++ ++ blk_shift = ffs(mmc->read_bl_len) - 1; ++ mmc_boundary = mmc->capacity>>blk_shift; ++ ++ if ((part_end + 1) > mmc_boundary) { ++ printf("Error: the operation cross the boundary of mmc\n"); ++ return 1; ++ } ++ ++ while ((group_start + wp_grp_size - 1) <= part_end) { ++ err = clear_write_prot_per_group(mmc, group_start); ++ if (err) { ++ printf("Error: The write protect can't be clear\n"); ++ return 1; ++ } ++ group_start += wp_grp_size; ++ set_protect_cnt++; ++//check write protect type every 32 group ++ if (set_protect_cnt % 32 == 0) { ++ check_group_start = group_start - group_num * wp_grp_size; ++ err = is_wp_set_failed(mmc, wp_type, check_group_start, group_num); ++ if (err) ++ return 1; ++ } ++ } ++ ++ group_num = set_protect_cnt % 32; ++ check_group_start = group_start - group_num * wp_grp_size; ++ ++ if (group_num) { ++ err = is_wp_set_failed(mmc, wp_type, check_group_start, group_num); ++ if (err) ++ return 1; ++ } ++ ++ return 0; ++} ++ ++static int do_amlmmc_clear_wp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ int ret = CMD_RET_USAGE; ++ struct mmc *mmc; ++ int dev = 1; ++ char *name = NULL; ++ u64 start, cnt; ++ ++ if (argc < 3 || argc > 4) ++ return ret; ++ ++ if (argc == 3) { ++ name = argv[2]; ++ dev = find_dev_num_by_partition_name(name); ++ if (dev < 0) { ++ printf("Error: Cannot find dev.\n"); ++ return CMD_RET_USAGE; ++ } ++ } else { ++ start = simple_strtoull(argv[2], NULL, 16); ++ cnt = simple_strtoull(argv[3], NULL, 10); ++ } ++ ++ mmc = find_mmc_device(dev); ++ if (!mmc) ++ return 1; ++ ++ if (IS_SD(mmc)) { ++ mmc = find_mmc_device(~dev); ++ if (IS_SD(mmc)) { ++ printf("SD card can not be write protect\n"); ++ return 1; ++ } ++ } ++ ++ mmc_init(mmc); ++ if (!mmc) ++ return 1; ++ ++ if (argc == 3) ++ ret = set_part_clear_wp(mmc, name); ++ else ++ ret = set_add_clear_wp(mmc, start, cnt); ++ ++ return ret; ++} ++ ++static int send_write_prot_status_group(struct mmc *mmc, u64 blk) ++{ ++ struct mmc_cmd cmd; ++ struct mmc_data data; ++ int err; ++ void *addr = NULL; ++ int i = 0; ++ addr = malloc(4*sizeof(u8)); ++ ++ if (addr == NULL) { ++ printf("Failed: malloc failed\n"); ++ return 1; ++ } ++ ++ cmd.cmdidx = MMC_CMD_SEND_WRITE_PROT; ++ cmd.cmdarg = blk; ++ cmd.resp_type = MMC_RSP_R1; ++ ++ data.dest = addr; ++ data.blocks = 1; ++ data.blocksize = 4; ++ data.flags = MMC_DATA_READ; ++ ++ err = mmc_send_cmd(mmc, &cmd, &data); ++ if (err) ++ goto err_out; ++ ++ printf("The write protect type for the 32 groups after 0x%llx is:\n0x", ++ blk); ++ for (i = 0 ; i < 4; i++) ++ printf("%02x", ((u8 *)addr)[i]); ++ printf("\n"); ++ ++ free(addr); ++ return 0; ++err_out: ++ free(addr); ++ return 1; ++} ++ ++static int send_part_wp_status(struct mmc *mmc, char *name) ++{ ++ int err = 0; ++ u8 ext_csd[512] = {0}; ++ u64 wp_grp_size, start, part_end; ++ u64 group_start; ++ ++ err = mmc_get_ext_csd(mmc, ext_csd); ++ if (err) { ++ printf("Failed: get ext_csd failed\n"); ++ return 1; ++ } ++ ++ if (!is_write_protect_valid(ext_csd)) { ++ printf("Failed: CLASS_6_CTRL isn't '0' " ++ "write protect process is invalid\n"); ++ return 1; ++ } ++ ++ err = compute_write_protect_range(mmc, name, ext_csd, ++ &wp_grp_size, &start, &part_end); ++ if (err) ++ return 1; ++ ++ group_start = start; ++ ++ while ((group_start + wp_grp_size - 1) <= part_end) { ++ err = send_write_prot_status_group(mmc, group_start); ++ if (err) ++ return 1; ++ group_start += 32 * wp_grp_size; ++ } ++ ++ return 0; ++} ++ ++static int send_add_wp_status(struct mmc *mmc, u64 start, u64 cnt) ++{ ++ int err = 0; ++ u8 ext_csd[512] = {0}; ++ u64 wp_grp_size, part_end; ++ u64 group_start; ++ int blk_shift; ++ u64 mmc_boundary; ++ err = mmc_get_ext_csd(mmc, ext_csd); ++ if (err) { ++ printf("Failed: get ext_csd failed\n"); ++ return 1; ++ } ++ ++ if (!is_write_protect_valid(ext_csd)) { ++ printf("Failed: CLASS_6_CTRL isn't '0' " ++ "write protect process is invalid\n"); ++ return 1; ++ } ++ ++ wp_grp_size = write_protect_group_size(mmc, ext_csd); ++ ++ if ((start % wp_grp_size)) { ++ group_start = (start + wp_grp_size - 1) / wp_grp_size * wp_grp_size; ++ printf("Caution! The partition start address isn't' aligned" ++ "to group size\n" ++ "the start address is change from 0x%llx to 0x%llx\n", ++ start, group_start); ++ part_end = group_start + (cnt - 1) * wp_grp_size - 1; ++ printf("The write protect group number is 0x%llx, rather than 0x%lld\n", ++ cnt - 1, cnt); ++ } else { ++ group_start = start; ++ part_end = group_start + cnt * wp_grp_size - 1; ++ } ++ ++ blk_shift = ffs(mmc->read_bl_len) - 1; ++ mmc_boundary = mmc->capacity>>blk_shift; ++ ++ if ((part_end + 1) > mmc_boundary) { ++ printf("Error: the operation cross the boundary of mmc\n"); ++ return 1; ++ } ++ ++ while ((group_start + wp_grp_size - 1) <= part_end) { ++ err = send_write_prot_status_group(mmc, group_start); ++ if (err) ++ return 1; ++ group_start += 32 * wp_grp_size; ++ } ++ ++ return 0; ++} ++ ++static int do_amlmmc_send_wp_status(struct cmd_tbl *cmdtp, ++ int flag, int argc, char *const argv[]) ++{ ++ int ret = CMD_RET_USAGE; ++ struct mmc *mmc; ++ int dev = 1; ++ char *name = NULL; ++ u64 start, cnt; ++ ++ if (argc < 3 || argc > 4) ++ return ret; ++ ++ if (argc == 3) { ++ name = argv[2]; ++ dev = find_dev_num_by_partition_name(name); ++ if (dev < 0) { ++ printf("Error: Cannot find dev.\n"); ++ return 1; ++ } ++ } else { ++ start = simple_strtoull(argv[2], NULL, 16); ++ cnt = simple_strtoull(argv[3], NULL, 0); ++ } ++ ++ mmc = find_mmc_device(dev); ++ ++ if (IS_SD(mmc)) { ++ mmc = find_mmc_device(~dev); ++ if (IS_SD(mmc)) { ++ printf("SD card can not be write protect\n"); ++ return 1; ++ } ++ } ++ ++ if (!mmc) ++ return 1; ++ ++ mmc_init(mmc); ++ if (!mmc) ++ return 1; ++ ++ if (argc == 3) ++ ret = send_part_wp_status(mmc, name); ++ else ++ ret = send_add_wp_status(mmc, start, cnt); ++ ++ if (ret) { ++ printf("Failed: send partition write protect status failed\n"); ++ } ++ ++ return ret; ++} ++ ++static int do_amlmmc_send_wp_type(struct cmd_tbl *cmdtp, ++ int flag, int argc, char *const argv[]) ++{ ++ int ret = CMD_RET_USAGE; ++ struct mmc *mmc; ++ int dev = 1; ++ char *name = NULL; ++ u64 start, cnt; ++ ++ if (argc < 3 || argc > 4) ++ return ret; ++ ++ if (argc == 3) { ++ name = argv[2]; ++ dev = find_dev_num_by_partition_name(name); ++ if (dev < 0) { ++ printf("Error: Cannot find dev.\n"); ++ return 1; ++ } ++ } else { ++ start = simple_strtoull(argv[2], NULL, 16); ++ cnt = simple_strtoull(argv[3], NULL, 0); ++ } ++ ++ mmc = find_mmc_device(dev); ++ ++ if (!mmc) ++ return 1; ++ ++ if (IS_SD(mmc)) { ++ mmc = find_mmc_device(~dev); ++ if (IS_SD(mmc)) { ++ printf("SD card can not be write protect\n"); ++ return 1; ++ } ++ } ++ ++ mmc_init(mmc); ++ if (!mmc) ++ return 1; ++ if (argc == 3) ++ ret = send_part_wp_type(mmc, name); ++ else ++ ret = send_add_wp_type(mmc, start, cnt); ++ ++ if (ret) { ++ printf("Failed: send parittion write protect type failed\n"); ++ } ++ ++ return ret; ++} ++ ++static int set_driver_strength(struct mmc *mmc, int strength) ++{ ++ int ret = 0; ++ u8 ext_csd[512] = {0}; ++ u8 strength_type = 0; ++ u8 driver_strength; ++ u8 hs_timing = 0; ++ ret = mmc_get_ext_csd(mmc, ext_csd); ++ if (ret) { ++ printf("get ext_csd failed\n"); ++ return ret; ++ } ++ strength_type = 1 << strength; ++ driver_strength = ext_csd[EXT_CSD_DRIVER_STRENGTH]; ++ if (0 == (strength_type & driver_strength)) { ++ printf("Failed: This device didn't support strength type %d\n", strength); ++ return 1; ++ } ++ ++ hs_timing = ext_csd[EXT_CSD_HS_TIMING]; ++ if ((hs_timing >> 4) > 0) { ++ printf("Failed: The driver strength has been set already, \ ++ please reset the device\n"); ++ return 1; ++ } ++ ++ hs_timing = hs_timing | (strength << 4); ++ ++ ret = mmc_set_ext_csd(mmc, EXT_CSD_HS_TIMING, hs_timing); ++ if (ret) { ++ printf("set ext_csd hs_timing field failed\n"); ++ return ret; ++ } ++ ret = mmc_get_ext_csd(mmc, ext_csd); ++ if (ret) { ++ printf("get ext_csd failed\n"); ++ return ret; ++ } ++ printf("The ext_csd[HS_TIMING] has been set to 0x%x\n", ++ ext_csd[EXT_CSD_HS_TIMING]); ++ return ret; ++} ++ ++static int get_driver_strength(struct mmc *mmc) ++{ ++ int ret = 0; ++ u8 ext_csd[512] = {0}; ++ u8 support_ds_type = 0; ++ u8 cur_driver_strength; ++ u8 hs_timing = 0; ++ ret = mmc_get_ext_csd(mmc, ext_csd); ++ if (ret) { ++ printf("get ext_csd failed\n"); ++ return ret; ++ } ++ ++ support_ds_type = ext_csd[EXT_CSD_DRIVER_STRENGTH]; ++ ++ hs_timing = ext_csd[EXT_CSD_HS_TIMING]; ++ cur_driver_strength = hs_timing >> 4; ++ ++ printf("current strength type is: "); ++ int strength_type = 0; ++ while (support_ds_type) { ++ if (support_ds_type & 1) { ++ if (cur_driver_strength == strength_type) ++ printf("[%d] ", strength_type); ++ else ++ printf("%d ", strength_type); ++ } ++ strength_type++; ++ support_ds_type = support_ds_type >> 1; ++ } ++ printf("\n"); ++ return ret; ++} ++ ++static int amlmmc_set_driver_strength(int argc, char *const argv[]) ++{ ++ int ret = CMD_RET_USAGE; ++ int dev, strength; ++ struct mmc *mmc; ++ ++ if (argc != 4) ++ return CMD_RET_USAGE; ++ ++ dev = simple_strtoul(argv[2], NULL, 10); ++ strength = simple_strtoul(argv[3], NULL, 10); ++ mmc = find_mmc_device(dev); ++ if (!mmc) { ++ puts("no mmc devices available\n"); ++ return 1; ++ } ++ mmc_init(mmc); ++ if (!mmc) ++ return 1; ++ ++ ret = set_driver_strength(mmc, strength); ++ ++ return ret; ++} ++ ++static int amlmmc_get_driver_strength(int argc, char *const argv[]) ++{ ++ int ret = CMD_RET_USAGE; ++ int dev; ++ struct mmc *mmc; ++ ++ if (argc != 3) ++ return CMD_RET_USAGE; ++ ++ dev = simple_strtoul(argv[2], NULL, 10); ++ mmc = find_mmc_device(dev); ++ if (!mmc) { ++ puts("no mmc devices available\n"); ++ return 1; ++ } ++ mmc_init(mmc); ++ if (!mmc) ++ return 1; ++ ++ ret = get_driver_strength(mmc); ++ ++ return ret; ++} ++ ++static int do_amlmmc_driver_strength(struct cmd_tbl *cmdtp, ++ int flag, int argc, char *const argv[]) ++{ ++ int ret = CMD_RET_USAGE; ++ ++ if (argc == 3) ++ ret = amlmmc_get_driver_strength(argc,argv); ++ else if (argc == 4) ++ ret = amlmmc_set_driver_strength(argc,argv); ++ ++ return ret; ++} ++ ++static struct cmd_tbl cmd_amlmmc[] = { ++ U_BOOT_CMD_MKENT(read, 6, 0, do_amlmmc_read, "", ""), ++ U_BOOT_CMD_MKENT(write, 6, 0, do_amlmmc_write, "", ""), ++ U_BOOT_CMD_MKENT(erase, 5, 0, do_amlmmc_erase, "", ""), ++ U_BOOT_CMD_MKENT(rescan, 3, 0, do_amlmmc_rescan, "", ""), ++ U_BOOT_CMD_MKENT(part, 3, 0, do_amlmmc_part, "", ""), ++ U_BOOT_CMD_MKENT(list, 2, 0, do_amlmmc_list, "", ""), ++ U_BOOT_CMD_MKENT(switch, 4, 0, do_amlmmc_switch, "", ""), ++ U_BOOT_CMD_MKENT(status, 3, 0, do_amlmmc_status, "", ""), ++ U_BOOT_CMD_MKENT(ext_csd, 5, 0, do_amlmmc_ext_csd, "", ""), ++ U_BOOT_CMD_MKENT(response, 3, 0, do_amlmmc_response, "", ""), ++ U_BOOT_CMD_MKENT(controller, 3, 0, do_amlmmc_controller, "", ""), ++ U_BOOT_CMD_MKENT(size, 4, 0, do_amlmmc_size, "", ""), ++ U_BOOT_CMD_MKENT(env, 2, 0, do_amlmmc_env, "", ""), ++ U_BOOT_CMD_MKENT(write_protect, 5, 0, do_amlmmc_write_protect, "", ""), ++ U_BOOT_CMD_MKENT(send_wp_status, 4, 0, do_amlmmc_send_wp_status, "", ""), ++ U_BOOT_CMD_MKENT(send_wp_type, 4, 0, do_amlmmc_send_wp_type, "", ""), ++ U_BOOT_CMD_MKENT(clear_wp, 4, 0, do_amlmmc_clear_wp, "", ""), ++ U_BOOT_CMD_MKENT(ds, 4, 0, do_amlmmc_driver_strength, "", ""), ++#ifdef CONFIG_SECURITYKEY ++ U_BOOT_CMD_MKENT(key, 2, 0, do_amlmmc_key, "", ""), ++#endif ++}; ++ ++static int do_amlmmcops(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ struct cmd_tbl *cp; ++ ++ cp = find_cmd_tbl(argv[1], cmd_amlmmc, ARRAY_SIZE(cmd_amlmmc)); ++ ++ if (cp == NULL || argc > cp->maxargs) ++ return CMD_RET_USAGE; ++ ++ if (flag == CMD_FLAG_REPEAT && !cmd_is_repeatable(cp)) ++ return CMD_RET_SUCCESS; ++ ++ return cp->cmd(cmdtp, flag, argc, argv); ++} ++ ++U_BOOT_CMD( ++ amlmmc, 6, 1, do_amlmmcops, ++ "AMLMMC sub system", ++ "read ram_addr addr_byte# cnt_byte\n" ++ "amlmmc write ram_addr addr_byte# cnt_byte\n" ++ "amlmmc erase addr_byte# cnt_byte\n" ++ "amlmmc erase /\n" ++ "amlmmc rescan \n" ++ "amlmmc part - show partition infomation of mmc\n" ++ "amlmmc list - lists available devices\n" ++ "amlmmc env - display env partition offset\n" ++ "amlmmc switch - part name : boot0, boot1, user\n" ++ "amlmmc status - read sd/emmc device status\n" ++ "amlmmc ext_csd - read sd/emmc device EXT_CSD [byte]\n" ++ "amlmmc ext_csd - write sd/emmc device EXT_CSD [byte] value\n" ++ "amlmmc response - read sd/emmc last command response\n" ++ "amlmmc controller - read sd/emmc controller register\n" ++ "amlmmc write_protect \n" ++ " - set write protect on partition through power_on or temporary\n" ++ "amlmmc write_protect \n" ++ " - set write protect on specified address through power_on or temporary\n" ++ "amlmmc send_wp_status send protect status of partition\n" ++ "amlmmc send_wp_status send protect status on specified address\n" ++ "amlmmc send_wp_type send protect type of partition\n" ++ "amlmmc send_wp_type send protect type on specified address\n" ++ "amlmmc clear_wp clear write protect of partition\n" ++ "amlmmc clear_wp clear write protect on specified addresst\n" ++ "amlmmc ds set driver strength\n" ++#ifdef CONFIG_SECURITYKEY ++ "amlmmc key - disprotect key partition\n" ++#endif ++); ++ ++/* dtb read&write operation with backup updates */ ++static u32 _calc_dtb_checksum(struct aml_dtb_rsv * dtb) ++{ ++ int i = 0; ++ int size = sizeof(struct aml_dtb_rsv) - sizeof(u32); ++ u32 * buffer; ++ u32 checksum = 0; ++ ++ if ((u64)dtb % 4 != 0) { ++ BUG(); ++ } ++ ++ size = size >> 2; ++ buffer = (u32*) dtb; ++ while (i < size) ++ checksum += buffer[i++]; ++ ++ return checksum; ++} ++ ++static int _verify_dtb_checksum(struct aml_dtb_rsv * dtb) ++{ ++ u32 checksum; ++ ++ checksum = _calc_dtb_checksum(dtb); ++ dtb_info("calc %x, store %x\n", checksum, dtb->checksum); ++ ++ return !(checksum == dtb->checksum); ++} ++ ++static int _dtb_read(struct mmc *mmc, u64 blk, u64 cnt, void * addr) ++{ ++ int dev = EMMC_DTB_DEV; ++ u64 n; ++ n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr); ++ if (n != cnt) { ++ dtb_err("%s: dev # %d, block # %#llx, count # %#llx ERROR!\n", ++ __func__, dev, blk, cnt); ++ } ++ ++ return (n != cnt); ++} ++ ++static int _dtb_write(struct mmc *mmc, u64 blk, u64 cnt, void * addr) ++{ ++ int dev = EMMC_DTB_DEV; ++ u64 n; ++ n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr); ++ if (n != cnt) { ++ dtb_err("%s: dev # %d, block # %#llx, count # %#llx ERROR!\n", ++ __func__, dev, blk, cnt); ++ } ++ ++ return (n != cnt); ++} ++ ++static struct mmc *_dtb_init(void) ++{ ++ struct mmc *mmc = find_mmc_device(EMMC_DTB_DEV); ++ if (!mmc) { ++ dtb_err("not find mmc\n"); ++ return NULL; ++ } ++ ++ if (mmc_init(mmc)) { ++ dtb_err("mmc init failed\n"); ++ return NULL; ++ } ++ return mmc; ++} ++ ++static int dtb_read_shortcut(struct mmc * mmc, void *addr) ++{ ++ u64 blk, cnt, dtb_glb_offset; ++ int dev = EMMC_DTB_DEV; ++ struct aml_dtb_info *info = &dtb_infos; ++ struct partitions * part = NULL; ++ struct virtual_partition *vpart = NULL; ++ vpart = aml_get_virtual_partition_by_name(MMC_DTB_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ dtb_glb_offset = part->offset + vpart->offset; ++ /* short cut */ ++ if (info->valid[0]) { ++ dtb_info("short cut in...\n"); ++ blk = dtb_glb_offset / mmc->read_bl_len; ++ cnt = vpart->size / mmc->read_bl_len; ++ if (_dtb_read(mmc, blk, cnt, addr)) { ++ dtb_err("%s: dev # %d, block # %#llx,cnt # %#llx ERROR!\n", ++ __func__, dev, blk, cnt); ++ /*try dtb2 if it's valid */ ++ if (info->valid[1]) { ++ blk = (dtb_glb_offset + vpart->size) / mmc->read_bl_len; ++ cnt = vpart->size / mmc->read_bl_len; ++ if (_dtb_read(mmc, blk, cnt, addr)) { ++ dtb_err("%s: dev # %d, block # %#llx, cnt # %#llx ERROR!\n", ++ __func__, dev, blk, cnt); ++ return -1; ++ } ++ } ++ } ++ return 0; ++ } ++ return -2; ++} ++ ++static int update_dtb_info(struct mmc *mmc, void *addr) ++{ ++ int ret = 0, dev = EMMC_DTB_DEV; ++ u64 blk, cnt, dtb_glb_offset; ++ struct aml_dtb_rsv * dtb = (struct aml_dtb_rsv *) addr; ++ struct aml_dtb_info *info = &dtb_infos; ++ int cpy = 1, valid = 0; ++ struct partitions * part = NULL; ++ struct virtual_partition *vpart = NULL; ++ vpart = aml_get_virtual_partition_by_name(MMC_DTB_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ dtb_glb_offset = part->offset + vpart->offset; ++ ++ while (cpy >= 0) { ++ blk = (dtb_glb_offset + cpy * (vpart->size)) / mmc->read_bl_len; ++ cnt = vpart->size / mmc->read_bl_len; ++ ret = _dtb_read(mmc, blk, cnt, addr); ++ if (ret) { ++ dtb_err("%s: dev # %d, block # %#llx, cnt # %#llx ERROR!\n", ++ __func__, dev, blk, cnt); ++ } else { ++ ret = _verify_dtb_checksum(dtb); ++ /* check magic avoid whole 0 issue */ ++ if (!ret && (dtb->magic != 0)) { ++ info->stamp[cpy] = dtb->timestamp; ++ info->valid[cpy] = 1; ++ } ++ else ++ dtb_wrn("cpy %d is not valid\n", cpy); ++ } ++ valid += info->valid[cpy]; ++ cpy --; ++ } ++ return valid; ++} ++ ++static int update_invalid_dtb(struct mmc *mmc, void *addr) ++{ ++ int ret = 0, dev = EMMC_DTB_DEV; ++ u64 blk, cnt, dtb_glb_offset; ++ struct aml_dtb_rsv * dtb = (struct aml_dtb_rsv *) addr; ++ struct aml_dtb_info *info = &dtb_infos; ++ struct partitions * part = NULL; ++ struct virtual_partition *vpart = NULL; ++ vpart = aml_get_virtual_partition_by_name(MMC_DTB_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ dtb_glb_offset = part->offset + vpart->offset; ++ cnt = vpart->size / mmc->read_bl_len; ++ ++ if (info->valid[1]) { ++ blk = (dtb_glb_offset + vpart->size) / mmc->read_bl_len; ++ if (_dtb_read(mmc, blk, cnt, addr)) { ++ dtb_err("%s: dev # %d, block # %#llx,cnt # %#llx ERROR!\n", ++ __func__, dev, blk, cnt); ++ ret = -2; ++ } ++ /* fixme, update the invalid one - dtb1 */ ++ blk = (dtb_glb_offset) / mmc->read_bl_len; ++ if (_dtb_write(mmc, blk, cnt, addr)) { ++ dtb_err("%s: dev # %d, block # %#llx,cnt # %#llx ERROR!\n", ++ __func__, dev, blk, cnt); ++ ret = -4; ++ } ++ info->valid[0] = 1; ++ info->stamp[0] = dtb->timestamp; ++ ret = 0; ++ } else { ++ dtb_info("update dtb2"); ++ blk = (dtb_glb_offset + vpart->size) / mmc->read_bl_len; ++ if (_dtb_write(mmc, blk, cnt, addr)) { ++ dtb_err("%s: dev # %d, block # %#llx,cnt # %#llx ERROR!\n", ++ __func__, dev, blk, cnt); ++ ret = -2; ++ } ++ info->valid[1] = 1; ++ info->stamp[1] = dtb->timestamp; ++ } ++ return ret; ++} ++ ++int update_old_dtb(struct mmc *mmc, void *addr) ++{ ++ int ret = 0, dev = EMMC_DTB_DEV; ++ u64 blk, cnt, dtb_glb_offset; ++ struct aml_dtb_rsv * dtb = (struct aml_dtb_rsv *) addr; ++ struct aml_dtb_info *info = &dtb_infos; ++ struct partitions * part = NULL; ++ struct virtual_partition *vpart = NULL; ++ vpart = aml_get_virtual_partition_by_name(MMC_DTB_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ dtb_glb_offset = part->offset + vpart->offset; ++ cnt = vpart->size / mmc->read_bl_len; ++ if (stamp_after(info->stamp[1], info->stamp[0])) { ++ blk = (dtb_glb_offset + vpart->size) / mmc->read_bl_len; ++ if (_dtb_read(mmc, blk, cnt, addr)) { ++ dtb_err("%s: dev # %d, block # %#llx,cnt # %#llx ERROR!\n", ++ __func__, dev, blk, cnt); ++ ret = -3; ++ } ++ /*update dtb1*/ ++ blk = dtb_glb_offset / mmc->read_bl_len; ++ if (_dtb_write(mmc, blk, cnt, addr)) { ++ dtb_err("%s: dev # %d, block # %#llx,cnt # %#llx ERROR!\n", ++ __func__, dev, blk, cnt); ++ ret = -3; ++ } ++ info->stamp[0] = dtb->timestamp; ++ ret = 0; ++ } else if (stamp_after(info->stamp[0], info->stamp[1])) { ++ /*update dtb2*/ ++ blk = (dtb_glb_offset + vpart->size) / mmc->read_bl_len; ++ if (_dtb_write(mmc, blk, cnt, addr)) { ++ dtb_err("%s: dev # %d, block # %#llx,cnt # %#llx ERROR!\n", ++ __func__, dev, blk, cnt); ++ ret = -3; ++ } ++ info->stamp[1] = dtb->timestamp; ++ } else { ++ dtb_info("do nothing\n"); ++ } ++ return ret; ++} ++ ++int dtb_read(void *addr) ++{ ++ int ret = 0; ++ int valid = 0; ++ struct mmc *mmc; ++ ++ mmc = _dtb_init(); ++ if (mmc == NULL) ++ return -10; ++ ++ if (dtb_read_shortcut(mmc, addr) == 0) ++ return ret; ++ ++ valid = update_dtb_info(mmc, addr); ++ dtb_info("total valid %d\n", valid); ++ /* check valid */ ++ switch (valid) { ++ /* none is valid, using the 1st one for compatibility*/ ++ case 0: ++ ret = -1; ++ goto _out; ++ break; ++ /* only 1 is valid, using the valid one */ ++ case 1: ++ update_invalid_dtb(mmc, addr); ++ break; ++ /* both are valid, pickup new one. */ ++ case 2: ++ update_old_dtb(mmc, addr); ++ break; ++ default: ++ dtb_err("impossble valid values.\n"); ++ BUG(); ++ break; ++ } ++_out: ++ return ret; ++} ++ ++ ++int dtb_write(void *addr) ++{ ++ int ret = 0; ++ struct aml_dtb_rsv * dtb = (struct aml_dtb_rsv *) addr; ++ struct aml_dtb_info *info = &dtb_infos; ++ u64 blk, cnt, dtb_glb_offset; ++ int cpy, valid; ++ struct mmc * mmc; ++ struct partitions * part = NULL; ++ struct virtual_partition *vpart = NULL; ++ vpart = aml_get_virtual_partition_by_name(MMC_DTB_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ dtb_glb_offset = part->offset + vpart->offset; ++ ++ mmc = _dtb_init(); ++ if (NULL == mmc) ++ return -10; ++ ++ /* stamp */ ++ valid = info->valid[0] + info->valid[1]; ++ dtb_info("valid %d\n", valid); ++ if (0 == valid) ++ dtb->timestamp = 0; ++ else if (1 == valid) { ++ dtb->timestamp = 1 + info->stamp[info->valid[0]?0:1]; ++ } else { ++ /* both are valid */ ++ if (info->stamp[0] != info->stamp[1]) { ++ dtb_wrn("timestamp are not same %d:%d\n", ++ info->stamp[0], info->stamp[1]); ++ dtb->timestamp = 1 + stamp_after(info->stamp[1], info->stamp[0])? ++ info->stamp[1]:info->stamp[0]; ++ } else ++ dtb->timestamp = 1 + info->stamp[0]; ++ } ++ /*setting version and magic*/ ++ dtb->version = 1; /* base version */ ++ dtb->magic = 0x00447e41; /*A~D\0*/ ++ dtb->checksum = _calc_dtb_checksum(dtb); ++ dtb_info("new stamp %d, checksum 0x%x, version %d, magic %s\n", ++ dtb->timestamp, dtb->checksum, dtb->version, (char *)&dtb->magic); ++ ++ for (cpy = 0; cpy < DTB_COPIES; cpy++) { ++ blk = (dtb_glb_offset + cpy * (vpart->size)) / mmc->read_bl_len; ++ cnt = vpart->size / mmc->read_bl_len; ++ ret |= _dtb_write(mmc, blk, cnt, addr); ++ info->valid[cpy] = 1; ++ info->stamp[cpy] = dtb->timestamp; ++ } ++ ++ return ret; ++} ++ ++extern int check_valid_dts(unsigned char *buffer); ++int renew_partition_tbl(unsigned char *buffer) ++{ ++ int ret = 0; ++ ++ unsigned char *temp = NULL; ++ if (!buffer) ++ return 1; ++ temp = malloc (AML_DTB_IMG_MAX_SZ); ++ if (!temp) ++ return 1; ++ memcpy(temp, buffer, AML_DTB_IMG_MAX_SZ); ++ /* todo, check new dts imcoming.... */ ++ ret = check_valid_dts(temp); ++ free(temp); ++ /* todo, check new dts imcoming.... */ ++/* ret = check_valid_dts(buffer);*/ ++ /* only the dts new is valid */ ++ if (!ret) { ++ free_partitions(); ++ get_partition_from_dts(buffer); ++ if (0 == mmc_device_init(_dtb_init())) { ++ printf("partition table success\n"); ++ ret = 0; ++ goto _out; ++ } ++ printf("partition table error\n"); ++ ret = 1; ++ } ++ ++_out: ++ return ret; ++} ++ ++int do_amlmmc_dtb_key(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ int dev, ret = 0; ++ void *addr = NULL; ++ u64 cnt = 0, n = 0, blk = 0; ++ //u64 size; ++ struct partitions *part = NULL; ++ struct virtual_partition *vpart = NULL; ++ vpart = aml_get_virtual_partition_by_name(MMC_DTB_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ ++ switch (argc) { ++ case 3: ++ if (strcmp(argv[1], "erase") == 0) { ++ if (strcmp(argv[2], "dtb") == 0) { ++ printf("start erase dtb......\n"); ++ dev = EMMC_DTB_DEV; ++ struct mmc *mmc = find_mmc_device(dev); ++ if (!mmc) { ++ printf("not find mmc\n"); ++ return 1; ++ } ++ blk = (part->offset + vpart->offset) / mmc->read_bl_len; ++ cnt = (vpart->size * 2) / mmc->read_bl_len; ++ if (cnt != 0) ++ n = blk_derase(mmc_get_blk_desc(mmc), blk, cnt); ++ printf("dev # %d, %s, several blocks erased %s\n", ++ dev, (flag == 0) ? " ":(argv[2]),(n == 0) ? "OK" : "ERROR"); ++ return (n == 0) ? 0 : 1; ++ }else if (strcmp(argv[2], "key") == 0){ ++ printf("start erase key......\n"); ++ dev = 1; ++ struct mmc *mmc = find_mmc_device(dev); ++ if (!mmc) { ++ printf("not find mmc\n"); ++ return 1; ++ } ++ n = mmc_key_erase(); ++ printf("dev # %d, %s, several blocks erased %s\n", ++ dev, (flag == 0) ? " ":(argv[2]),(n == 0) ? "OK" : "ERROR"); ++ return (n == 0) ? 0 : 1; ++ } ++ } else if (strcmp(argv[1], "cali_pattern") == 0) { ++ ++ if (strcmp(argv[2], "write") == 0) { ++ dev = EMMC_DTB_DEV; ++ struct mmc *mmc = find_mmc_device(dev); ++ if (!mmc) { ++ printf("not find mmc\n"); ++ return 1; ++ } ++ vpart = aml_get_virtual_partition_by_name(MMC_PATTERN_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ addr = (void *)malloc(vpart->size); ++ if (addr == NULL) { ++ printf("cali_pattern malloc fail\n"); ++ return 1; ++ } ++ mmc_write_cali_mattern(addr); ++ blk = (part->offset + vpart->offset) / mmc->read_bl_len; ++ cnt = vpart->size / mmc->read_bl_len; ++ if (cnt != 0) ++ n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr); ++ printf("dev # %d, %s, several calibration pattern blocks write %s\n", ++ dev, (flag == 0) ? " ":(argv[2]),(n == cnt) ? "OK" : "ERROR"); ++ free(addr); ++ return (n == cnt) ? 0 : 1; ++ } ++ } ++ case 4: ++ addr = (void *)simple_strtoul(argv[2], NULL, 16); ++ if (strcmp(argv[1], "dtb_read") == 0) { ++ /* fixme, */ ++ ret = dtb_read(addr); ++ return 0; ++ ++ } else if (strcmp(argv[1], "dtb_write") == 0) { ++ /* fixme, should we check the return value? */ ++ ret = dtb_write(addr); ++ ret |= renew_partition_tbl(addr); ++ return ret; ++ } ++ return 0; ++ default: ++ break; ++ } ++ return 1; ++} ++ ++/* update partition table in reserved partition. */ ++__weak int emmc_update_ept(unsigned char *buffer) ++{ ++ int ret = 0; ++ ++#ifndef DTB_BIND_KERNEL ++ dtb_write(buffer); ++#endif ++ ret = renew_partition_tbl(buffer); ++ return ret; ++} ++ ++/* fixme, should use renew_partition_tbl here! */ ++__weak int emmc_update_mbr(unsigned char *buffer) ++{ ++ int ret = 0; ++ //cpu_id_t cpu_id = get_cpu_id(); ++ ++ if (0) { //(cpu_id.family_id < MESON_CPU_MAJOR_ID_GXL) { ++ ret = -1; ++ printf("MBR not support, try dtb\n"); ++ goto _out; ++ } ++#ifndef DTB_BIND_KERNEL ++ dtb_write(buffer); ++#endif ++ ret = get_partition_from_dts(buffer); ++ if (ret) { ++ printf("Fail to get partition talbe from dts\n"); ++ goto _out; ++ } ++ ret = mmc_device_init(_dtb_init()); ++ printf("%s: update mbr %s\n", __func__, ret?"Fail":"Success"); ++_out: ++ return ret; ++} ++ ++int emmc_erase_rsv(struct mmc *mmc, char *rsv_part) ++{ ++ u64 cnt = 0, n = 0, blk = 0; ++ struct partitions *part = NULL; ++ struct virtual_partition *vpart = NULL; ++ ++ if (rsv_part == NULL) ++ return -1; ++ ++ vpart = aml_get_virtual_partition_by_name(MMC_DTB_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ if (strcmp(rsv_part, "dtb") == 0) { ++ blk = (part->offset + vpart->offset) / mmc->read_bl_len; ++ cnt = (vpart->size * 2) / mmc->read_bl_len; ++ if (cnt != 0) ++ n = blk_derase(mmc_get_blk_desc(mmc), blk, cnt); ++ printf("%s is erased %s\n", ++ rsv_part, (n == 0) ? "OK" : "ERROR"); ++ return (n == 0) ? 0 : 1; ++ } else if (strcmp(rsv_part, "key") == 0) { ++ n = mmc_key_erase(); ++ printf("%s is erased %s\n", ++ rsv_part, (n == 0) ? "OK" : "ERROR"); ++ return (n == 0) ? 0 : 1; ++ } ++ return 1; ++} ++ ++int do_emmc_erase(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ int dev; ++ u64 cnt = 0, n = 0, blk = 0; ++ //u64 size; ++ struct partitions *part = NULL; ++ struct virtual_partition *vpart = NULL; ++ struct mmc *mmc; ++ if (argc != 3) ++ return CMD_RET_USAGE; ++ ++ vpart = aml_get_virtual_partition_by_name(MMC_DTB_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ if (strcmp(argv[2], "dtb") == 0) { ++ printf("start erase dtb......\n"); ++ dev = EMMC_DTB_DEV; ++ mmc = find_mmc_device(dev); ++ if (!mmc) { ++ printf("not find mmc\n"); ++ return 1; ++ } ++ blk = (part->offset + vpart->offset) / mmc->read_bl_len; ++ cnt = (vpart->size * 2) / mmc->read_bl_len; ++ if (cnt != 0) ++ n = blk_derase(mmc_get_blk_desc(mmc), blk, cnt); ++ printf("dev # %d, %s, several blocks erased %s\n", ++ dev, (flag == 0) ? " ":(argv[2]),(n == 0) ? "OK" : "ERROR"); ++ return (n == 0) ? 0 : 1; ++ } else if (strcmp(argv[2], "key") == 0) { ++ printf("start erase key......\n"); ++ dev = 1; ++ mmc = find_mmc_device(dev); ++ if (!mmc) { ++ printf("not find mmc\n"); ++ return 1; ++ } ++ n = mmc_key_erase(); ++ printf("dev # %d, %s, several blocks erased %s\n", ++ dev, (flag == 0) ? " ":(argv[2]),(n == 0) ? "OK" : "ERROR"); ++ return (n == 0) ? 0 : 1; ++ } ++ return 1; ++} ++ ++int do_emmc_dtb_read(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ int ret = 0; ++ void *addr = NULL; ++ ++ if (argc != 4) ++ return CMD_RET_USAGE; ++ ++ addr = (void *)simple_strtoul(argv[2], NULL, 16); ++ ret = dtb_read(addr); ++ return ret; ++} ++ ++int do_emmc_dtb_write(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ int ret = 0; ++ void *addr = NULL; ++ ++ if (argc != 4) ++ return CMD_RET_USAGE; ++ ++ addr = (void *)simple_strtoul(argv[2], NULL, 16); ++ ret = dtb_write(addr); ++ ret |= renew_partition_tbl(addr); ++ return ret; ++} ++ ++static int _fastboot_context_read(struct mmc *mmc, u64 blk, ++ u64 cnt, void *addr) ++{ ++ int dev = EMMC_FASTBOOT_CONTEXT_DEV; ++ u64 n; ++ ++ n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr); ++ if (n != cnt) { ++ fb_err("%s: dev # %d, block # %#llx, count # %#llx ERROR!\n", ++ __func__, dev, blk, cnt); ++ } ++ ++ return n != cnt; ++} ++ ++int fastboot_context_read(void *buf, size_t size) ++{ ++ uint32_t crc_result; ++ struct mmc *mmc; ++ struct FastbootContext *fb_cont; ++ int fb_size = sizeof(struct FastbootContext); ++ u64 blk, cnt, fb_glb_offset; ++ int dev = EMMC_FASTBOOT_CONTEXT_DEV; ++ struct partitions *part = NULL; ++ struct virtual_partition *vpart = NULL; ++ ++ mmc = find_mmc_device(dev); ++ if (!mmc) { ++ puts("no mmc devices available\n"); ++ return 1; ++ } ++ ++ if (mmc_init(mmc)) { ++ printf("%s() %d: emmc init failed\n", __func__, __LINE__); ++ return 1; ++ } ++ ++ vpart = aml_get_virtual_partition_by_name(MMC_FASTBOOT_CONTEXT_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ fb_glb_offset = part->offset + vpart->offset; ++ ++ blk = fb_glb_offset / mmc->read_bl_len; ++ cnt = size / mmc->read_bl_len; ++ ++ if (_fastboot_context_read(mmc, blk, cnt, buf)) ++ return 1; ++ ++ fb_cont = (struct FastbootContext *)buf; ++ crc_result = crc32(0, buf, fb_size - 4); ++ ++ if (crc_result != fb_cont->crc32) { ++ printf("%s %d: crc checksum ERROR!\n", __func__, __LINE__); ++ return 1; ++ } ++ return 0; ++} ++ ++ ++int do_emmc_fb_read(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ int ret = 0; ++ void *addr = NULL; ++ u64 size; ++ ++ if (argc != 4) ++ return CMD_RET_USAGE; ++ ++ addr = (void *)simple_strtoul(argv[2], NULL, 16); ++ size = simple_strtoull(argv[3], NULL, 16); ++ ret = fastboot_context_read(addr, size); ++ return ret; ++} ++ ++static int _fastboot_context_write(struct mmc *mmc, u64 blk, ++ u64 cnt, void *addr) ++{ ++ int dev = EMMC_FASTBOOT_CONTEXT_DEV; ++ int n; ++ ++ n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr); ++ ++ if (n != cnt) { ++ fb_err("%s: dev # %d, block # %#llx,cnt # %#llx ERROR!\n", ++ __func__, dev, blk, cnt); ++ } ++ ++ return n != cnt; ++} ++ ++int fastboot_context_write(void *buf, size_t size) ++{ ++ int ret = 0; ++ struct FastbootContext *fb_cont = (struct FastbootContext *)buf; ++ u64 blk, cnt, fb_glb_offset; ++ struct mmc *mmc; ++ struct partitions *part = NULL; ++ struct virtual_partition *vpart = NULL; ++ int dev = EMMC_FASTBOOT_CONTEXT_DEV; ++ int fb_size = sizeof(struct FastbootContext); ++ ++ mmc = find_mmc_device(dev); ++ if (!mmc) { ++ puts("no mmc devices available\n"); ++ return 1; ++ } ++ ++ ret = mmc_init(mmc); ++ if (ret) { ++ printf("%s() %d: emmc init failed\n", __func__, __LINE__); ++ return 1; ++ } ++ ++ vpart = aml_get_virtual_partition_by_name(MMC_FASTBOOT_CONTEXT_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ fb_glb_offset = part->offset + vpart->offset; ++ fb_cont->crc32 = crc32(0, buf, fb_size - 4); ++ blk = fb_glb_offset / mmc->read_bl_len; ++ cnt = size / mmc->read_bl_len; ++ ret = _fastboot_context_write(mmc, blk, cnt, buf); ++ ++ return ret; ++} ++ ++int do_emmc_fb_write(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ int ret = 0; ++ void *addr = NULL; ++ u64 size; ++ ++ if (argc != 4) ++ return CMD_RET_USAGE; ++ ++ addr = (void *)simple_strtoul(argv[2], NULL, 16); ++ size = simple_strtoull(argv[3], NULL, 16); ++ ret = fastboot_context_write(addr, size); ++ return ret; ++} ++ ++int do_emmc_key_read(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ int ret = 0; ++ void *addr = NULL; ++ u64 size; ++ uint32_t *actual_lenth=0; ++ ++ if (argc != 4) ++ return CMD_RET_USAGE; ++ ++ addr = (void *)simple_strtoul(argv[2], NULL, 16); ++ size = simple_strtoull(argv[3], NULL, 16); ++ printf("enter emmc key read !!\n"); ++ printf("addr:%p size:%llx\n",addr,size); ++ ret = mmc_key_read(addr, size,actual_lenth); ++ printf("ret:%d\n",ret); ++ return ret; ++} ++ ++int do_emmc_key_write(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) { ++ ++ int ret = 0; ++ void *addr = NULL; ++ u64 size; ++ uint32_t *actual_lenth=0; ++ ++ if (argc != 4) ++ return CMD_RET_USAGE; ++ ++ addr = (void *)simple_strtoul(argv[2], NULL, 16); ++ size = simple_strtoull(argv[3], NULL, 16); ++ ret = mmc_key_write(addr, size,actual_lenth); ++ return ret; ++ ++ ++} ++ ++ ++ ++ ++static struct cmd_tbl cmd_emmc[] = { ++ U_BOOT_CMD_MKENT(dtb_read, 4, 0, do_emmc_dtb_read, "", ""), ++ U_BOOT_CMD_MKENT(dtb_write, 4, 0, do_emmc_dtb_write, "", ""), ++ U_BOOT_CMD_MKENT(erase, 3, 0, do_emmc_erase, "", ""), ++ U_BOOT_CMD_MKENT(fastboot_read, 4, 0, do_emmc_fb_read, "", ""), ++ U_BOOT_CMD_MKENT(fastboot_write, 4, 0, do_emmc_fb_write, "", ""), ++ U_BOOT_CMD_MKENT(key_read, 4, 0, do_emmc_key_read, "", ""), ++ U_BOOT_CMD_MKENT(key_write, 4, 0, do_emmc_key_write, "", ""), ++}; ++ ++static int do_emmc_dtb_key(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ struct cmd_tbl *cp; ++ ++ cp = find_cmd_tbl(argv[1], cmd_emmc, ARRAY_SIZE(cmd_emmc)); ++ ++ if (cp == NULL || argc > cp->maxargs) ++ return CMD_RET_USAGE; ++ if (flag == CMD_FLAG_REPEAT && !cmd_is_repeatable(cp)) ++ return CMD_RET_SUCCESS; ++ return cp->cmd(cmdtp, flag, argc, argv); ++} ++ ++ ++U_BOOT_CMD( ++ emmc, 4, 1, do_emmc_dtb_key, ++ "EMMC sub system", ++ "dtb_read addr size\n" ++ "emmc dtb_write addr size\n" ++ "emmc erase dtb\n" ++ "emmc erase key\n" ++ "emmc fastboot_read addr size\n" ++ "emmc fastboot_write addr size\n" ++ "emmc key_read addr size\n" ++ "emmc key_write addr size\n" ++); ++ +diff --git a/cmd/storage.c b/cmd/storage.c +new file mode 100644 +index 00000000000..98147fbe22c +--- /dev/null ++++ b/cmd/storage.c +@@ -0,0 +1,1503 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Storage interface module ++ * ++ * Copyright (C) 2018 Amlogic Corporation ++ * ++ */ ++#include ++#include ++#include ++//#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++//#include ++#include ++#include ++ ++#undef pr_info ++#define pr_info printf ++ ++#ifdef CONFIG_SPI_FLASH ++extern int spi_nor_pre(void); ++extern int spi_nor_probe(u32 init_flag); ++#endif ++ ++#ifdef CONFIG_SPI_NAND ++extern int spi_nand_pre(void); ++extern int spi_nand_probe(u32 init_flag); ++#endif ++ ++#ifdef CONFIG_MTD_SPI_NAND ++extern int spi_nand_pre(void); ++extern int spi_nand_probe(u32 init_flag); ++#endif ++ ++#ifdef CONFIG_AML_NAND ++extern int amlnf_pre(void); ++extern int amlnf_probe(u32 init_flag); ++#endif ++ ++#ifdef CONFIG_MESON_NFC ++extern int nand_pre(void); ++extern int nand_probe(uint32_t init_flag); ++#endif ++ ++#ifdef CONFIG_MMC_MESON_GX ++extern int emmc_pre(void); ++extern int emmc_probe(u32 init_flag); ++#endif ++ ++#ifdef CONFIG_MMC_MESON_GX ++extern int sdcard_pre(void); ++extern int sdcard_probe(u32 init_flag); ++#endif ++/* for info protect, fixme later */ ++int info_disprotect = 0; ++ ++static struct storage_t *current; ++static struct device_node_t device_list[] = { ++#ifdef CONFIG_MESON_NFC ++ {BOOT_NAND_MTD, "mtd", nand_pre, nand_probe}, ++#endif ++#ifdef CONFIG_AML_NAND ++ {BOOT_NAND_NFTL, "nftl", amlnf_pre, amlnf_probe}, ++#endif ++#ifdef CONFIG_SPI_NAND ++ /* old drivers will be removed later */ ++ {BOOT_SNAND, "spi-nand", spi_nand_pre, spi_nand_probe}, ++#endif ++#ifdef CONFIG_MTD_SPI_NAND ++ {BOOT_SNAND, "spi-nand", spi_nand_pre, spi_nand_probe}, ++#endif ++#if CONFIG_SPI_FLASH ++ {BOOT_SNOR, "spi-nor", spi_nor_pre, spi_nor_probe}, ++#endif ++#if 0 ++ {BOOT_SD, "sd", sdcard_pre, sdcard_probe}, ++#endif ++ ++#ifdef CONFIG_MMC_MESON_GX ++ {BOOT_EMMC, "emmc", emmc_pre, emmc_probe}, ++#endif ++ ++}; ++ ++int store_register(struct storage_t *store_dev) ++{ ++ if (!store_dev) ++ return 1; ++ if (!current) { ++ INIT_LIST_HEAD(&store_dev->list); ++ current = store_dev; ++ return 0; ++ } ++ /** ++ * the head node will not be a valid node ++ * usually when we use the list, but in storage ++ * interface module, we init the device node as ++ * a head instead a global list_head pointer, ++ * it should be traversaled. ++ */ ++ if (store_dev == current) ++ return 0; ++ struct storage_t *dev; ++ ++ if (store_dev->type == current->type) ++ return 1; ++ list_for_each_entry(dev, ¤t->list, list) { ++ if (dev == store_dev) ++ return 0; ++ else if (dev->type == store_dev->type) ++ return 1; ++ } ++ list_add_tail(&store_dev->list, ¤t->list); ++ current = store_dev; ++ return 0; ++} ++ ++void store_unregister(struct storage_t *store_dev) ++{ ++ if (store_dev == current) { ++ if (list_empty_careful(&store_dev->list)) { ++ current = NULL; ++ } else { ++ current = list_entry((current->list).next, ++ struct storage_t, list); ++ list_del_init(&store_dev->list); ++ } ++ } else { ++ list_del_init(&store_dev->list); ++ } ++} ++ ++int sheader_need(void) ++{ ++ //const cpu_id_t cpuid = get_cpu_id(); ++ //const int familyId = cpuid.family_id; ++ ++ return 0; //(MESON_CPU_MAJOR_ID_SC2 == familyId); ++} ++ ++unsigned char *ubootdata = NULL; ++void sheader_load(void *addr) ++{ ++ ubootdata = addr; ++} ++ ++/* ++ * storage header which size is 512B ++ * is bind into the tail of bl2.bin. ++ * @addr: uboot address. ++ */ ++static p_payload_info_t parse_uboot_sheader(void *addr) ++{ ++ p_payload_info_t pInfo = (p_payload_info_t)(addr + BL2_SIZE); ++ ++ if (AML_MAGIC_HDR_L == pInfo->hdr.nMagicL && ++ AML_MAGIC_HDR_R == pInfo->hdr.nMagicR) { ++ printf("aml log : bootloader blxx mode!\n"); ++ return pInfo; ++ } ++ return NULL; ++} ++ ++boot_area_entry_t general_boot_part_entry[MAX_BOOT_AREA_ENTRIES] = { ++ {BOOT_BL2, BOOT_AREA_BB1ST, 0, BOOT_FIRST_BLOB_SIZE}, ++ {BOOT_BL2E, BOOT_AREA_BL2E, 0, 0x40000}, ++ {BOOT_BL2X, BOOT_AREA_BL2X, 0, 0x40000}, ++ {BOOT_DDRFIP, BOOT_AREA_DDRFIP, 0, 0x40000}, ++ {BOOT_DEVFIP, BOOT_AREA_DEVFIP, 0, 0x300000}, ++}; ++ ++struct boot_layout general_boot_layout = {.boot_entry = general_boot_part_entry}; ++struct storage_startup_parameter g_ssp; ++struct storage_bl *g_storage = NULL; ++ ++static void storage_boot_layout_debug_info( ++ struct boot_layout *boot_layout) ++{ ++ boot_area_entry_t *boot_entry = boot_layout->boot_entry; ++ int i; ++ ++ printf("boot area list: \n"); ++ for (i = 0; i < MAX_BOOT_AREA_ENTRIES && boot_entry[i].size; i++) { ++ printf("%10s ", boot_entry[i].name); ++ printf("%10llx ", boot_entry[i].offset); ++ printf("%10llx\n", boot_entry[i].size); ++ } ++} ++ ++/* use STORAGE_ROUND_UP, y must be power of 2 */ ++#define STORAGE_ROUND_UP_IF_UNALIGN(x, y) ((x) = (((x) + (y) - 1) & (~(y - 1)))) ++#define NAND_RSV_OFFSET 1024 ++#define ALIGN_SIZE (4096) ++static int storage_boot_layout_rebuild(struct boot_layout *boot_layout, ++ unsigned int bl2e_size, ++ unsigned int bl2x_size) ++{ ++ struct storage_startup_parameter *ssp = &g_ssp; ++ boot_area_entry_t *boot_entry = boot_layout->boot_entry; ++ uint64_t align_size, reserved_size = 0; ++ uint8_t i, cal_copy = ssp->boot_bakups; ++ ++ align_size = ALIGN_SIZE; ++ if ((ssp->boot_device == BOOT_NAND_NFTL) || ++ (ssp->boot_device == BOOT_NAND_MTD)) { ++ reserved_size = ssp->sip.nsp.layout_reserve_size; ++ align_size = ((NAND_RSV_OFFSET / cal_copy) * ssp->sip.nsp.page_size); ++ printf("reserved_size:0x%llx 0x%llx\n", reserved_size, align_size); ++ } else if (ssp->boot_device == BOOT_SNAND) { ++ reserved_size = ssp->sip.snasp.layout_reserve_size; ++ align_size = ((NAND_RSV_OFFSET / cal_copy) * ssp->sip.snasp.pagesize); ++ } else if (ssp->boot_device == BOOT_EMMC) { ++ ssp->boot_entry[0].offset = boot_entry[0].offset += ++ BL2_CORE_BASE_OFFSET_EMMC; ++ cal_copy = 1; ++ } ++ STORAGE_ROUND_UP_IF_UNALIGN(boot_entry[0].size, align_size); ++ ssp->boot_entry[0].size = boot_entry[0].size; ++ printf("ssp->boot_entry[0] offset:0x%x, size:0x%x\n", ++ ssp->boot_entry[0].offset, ssp->boot_entry[0].size); ++ printf("cal_copy:0x%x\n", cal_copy); ++ printf("align_size:0x%llx\n", align_size); ++ printf("reserved_size:0x%llx\n", reserved_size); ++ if ((ssp->boot_device == BOOT_NAND_NFTL) || ++ (ssp->boot_device == BOOT_NAND_MTD)) ++ align_size = ssp->sip.nsp.block_size; ++ else if (ssp->boot_device == BOOT_SNAND) ++ align_size = ssp->sip.snasp.pagesize * ++ ssp->sip.snasp.pages_per_eraseblock; ++ printf("align_size2:%llu\n", align_size); ++ ++ boot_entry[BOOT_AREA_BL2E].size = bl2e_size; ++ boot_entry[BOOT_AREA_BL2X].size = bl2x_size; ++ ++ for (i = 1; i < MAX_BOOT_AREA_ENTRIES && boot_entry[i - 1].size; i++) { ++ STORAGE_ROUND_UP_IF_UNALIGN(boot_entry[i].size, align_size); ++ boot_entry[i].offset = boot_entry[i-1].offset + ++ boot_entry[i-1].size * cal_copy + reserved_size; ++ reserved_size = 0; ++ ssp->boot_entry[i].size = boot_entry[i].size; ++ ssp->boot_entry[i].offset = boot_entry[i].offset; ++ } ++ ++ return 0; ++} ++ ++/* use STORAGE_ROUND_UP, y must be power of 2 */ ++#define STORAGE_ROUND_UP_IF_UNALIGN(x, y) ((x) = (((x) + (y) - 1) & (~(y - 1)))) ++#define NAND_RSV_OFFSET 1024 ++#define ALIGN_SIZE (4096) ++static int storage_boot_layout_general_setting(struct boot_layout *boot_layout, ++ int need_build) ++{ ++ //struct storage_startup_parameter *ssp = &g_ssp; ++ boot_area_entry_t *boot_entry = boot_layout->boot_entry; ++ struct storage_boot_entry *sbentry = g_ssp.boot_entry; ++ p_payload_info_t pInfo = parse_uboot_sheader(ubootdata);; ++ p_payload_info_hdr_t hdr = &pInfo->hdr; ++ p_payload_info_item_t pItem = pInfo->arrItems; ++ int offPayload = 0, szPayload = 0; ++ unsigned int bl2e_size, bl2x_size; ++ char name[8] = {0}; ++ int nIndex = 0; ++ ++ if (need_build == BOOT_ID_USB) { ++ for (nIndex = 1, pItem += 1; ++ nIndex < hdr->byItemNum; ++nIndex, ++pItem) { ++ memcpy(name, &pItem->nMagic, sizeof(unsigned int)); ++ offPayload = pItem->nOffset; ++ if (nIndex == BOOT_AREA_BL2E) ++ bl2e_size = pItem->nPayLoadSize; ++ if (nIndex == BOOT_AREA_BL2X) ++ bl2x_size = pItem->nPayLoadSize; ++ szPayload = pItem->nPayLoadSize; ++ pr_info("Item[%d]%4s offset 0x%08x sz 0x%x\n", ++ nIndex, name, offPayload, szPayload); ++ } ++ storage_boot_layout_rebuild(boot_layout, bl2e_size, bl2x_size); ++ } else { ++ /* may be sdcard boot and also have to rebuild layout */ ++ if (need_build == BOOT_ID_SDCARD) { ++ bl2e_size = sbentry[BOOT_AREA_BL2E].size; ++ bl2x_size = sbentry[BOOT_AREA_BL2X].size; ++ printf("bl2e_size=%x bl2x_size=%x current->type=%d\n", ++ bl2e_size, bl2x_size, current->type); ++ storage_boot_layout_rebuild(boot_layout, ++ bl2e_size, bl2x_size); ++ return 0; ++ } ++ /* normal boot */ ++ for (nIndex = 0; ++ nIndex < MAX_BOOT_AREA_ENTRIES && sbentry->size; ++ nIndex++, sbentry++) { ++ boot_entry[nIndex].size = sbentry->size; ++ boot_entry[nIndex].offset = sbentry->offset; ++ } ++ } ++ ++ return 0; ++} ++ ++uint8_t emmc_boot_seqs_tbl[8][2] = { ++ {0, 3}, {0, 2}, {0, 3}, {0, 1}, ++ {1, 2}, {1, 1}, {2, 1}, {0, 0} ++ }; ++ ++static int _get_emmc_boot_seqs(void) ++{ ++ uint8_t ebcfg = 0; ++ if (IS_FEAT_DIS_EMMC_USER()) ++ ebcfg |= (1<<2); ++ if (IS_FEAT_DIS_EMMC_BOOT_0()) ++ ebcfg |= (1<<1); ++ if (IS_FEAT_DIS_EMMC_BOOT_1()) ++ ebcfg |= (1<<0); ++ ++ return ebcfg; ++} ++ ++static int storage_get_emmc_boot_seqs(void) ++{ ++ return emmc_boot_seqs_tbl[_get_emmc_boot_seqs()][1];; ++} ++ ++static int storage_get_emmc_boot_start(void) ++{ ++ return emmc_boot_seqs_tbl[_get_emmc_boot_seqs()][0];; ++} ++ ++#define NAND_RSV_BLOCK_NUM 48 ++#define NSP_PAGE0_DISABLE 1 ++extern unsigned char *ubootdata; ++static int storage_get_and_parse_ssp(int *need_build) // boot_device: ++{ ++ struct storage_startup_parameter *ssp = &g_ssp; ++ union storage_independent_parameter *sip; ++ static struct param_e *storage_param_e; ++ int usb_boot = *need_build; ++ ++ memset(ssp, 0, sizeof(struct storage_startup_parameter)); ++ if (!usb_boot) { ++ storage_param_e = param_of(STORAGE_PARAM_TPYE); ++ if (!storage_param_e) ++ return -1; ++ memcpy(ssp, storage_param_e->data, ++ sizeof(struct storage_startup_parameter)); ++ /* may be sdcard boot and also have to rebuild layout */ ++ if (ssp->boot_device == BOOT_ID_SDCARD || ++ ssp->boot_device == BOOT_ID_USB) { ++ /* need change the storage base here */ ++ *need_build = ssp->boot_device; ++ } ++ } ++ ++ if (*need_build) { ++ sip = &ssp->sip; ++ ssp->boot_device = current->type; ++ switch (ssp->boot_device) { ++ case BOOT_EMMC: ++ ssp->boot_bakups = storage_get_emmc_boot_seqs(); ++ break; ++ case BOOT_SNOR: ++ if (IS_FEAT_EN_4BL2_SNOR()) ++ ssp->boot_bakups = 4; ++ if (IS_FEAT_DIS_NBL2_SNOR()) ++ ssp->boot_bakups = 1; ++ break; ++ case BOOT_SNAND: ++ if (IS_FEAT_EN_8BL2_SNAND()) ++ ssp->boot_bakups = 8; ++ if (IS_FEAT_DIS_NBL2_SNAND()) ++ ssp->boot_bakups = 1; ++ sip->snasp.pagesize = current->info.write_unit; ++ sip->snasp.pages_per_eraseblock = ++ current->info.erase_unit / current->info.write_unit; ++ sip->snasp.eraseblocks_per_lun = ++ (current->info.caps >> 20) / current->info.erase_unit; ++ sip->snasp.planes_per_lun = 1; ++ sip->snasp.luns_per_target = 1; ++ sip->snasp.ntargets = 1; ++ sip->snasp.layout_reserve_size = ++ NAND_RSV_BLOCK_NUM * current->info.erase_unit; ++ break; ++ case BOOT_NAND_NFTL: ++ case BOOT_NAND_MTD: ++ if (IS_FEAT_DIS_8BL2_NAND()) ++ ssp->boot_bakups = 4; ++ if (IS_FEAT_DIS_NBL2_NAND()) ++ ssp->boot_bakups = 1; ++ ssp->boot_bakups = 8; //FIXIT?? efuse do not work now. ++ sip->nsp.page_size = current->info.write_unit; ++ sip->nsp.block_size = current->info.erase_unit; ++ sip->nsp.pages_per_block = ++ current->info.erase_unit / current->info.write_unit; ++ sip->nsp.layout_reserve_size = ++ NAND_RSV_BLOCK_NUM * sip->nsp.block_size; ++ sip->nsp.page0_disable = NSP_PAGE0_DISABLE; ++ break; ++ default: ++ /* do nothing. */ ++ break; ++ } ++ ++ } ++ ++ /* sanity check */ ++ ++ printf("boot_device:%d\n", ssp->boot_device); ++ printf("boot_seq:%d\n", ssp->boot_seq); ++ printf("boot_bakups:%d\n", ssp->boot_bakups); ++ printf("rebuid_id :%d\n", *need_build); ++ ++ return 0; ++} ++ ++int storage_post_init(void) ++{ ++ int ret = -1; ++ int need_build = 0; ++ ++ ret = storage_get_and_parse_ssp(&need_build); ++ if (ret < 0) ++ return -1; ++ storage_boot_layout_general_setting(&general_boot_layout, need_build); ++ storage_boot_layout_debug_info(&general_boot_layout); ++ ++ return ret; ++} ++ ++int store_init(u32 init_flag) ++{ ++ // cpu_id_t cpu_id = get_cpu_id(); ++ int i, ret = 0; ++ u8 record = 0; ++ ++ /*1. pre scan*/ ++ for (i = 0; i < ARRAY_SIZE(device_list); i++) { ++ if (!device_list[i].pre()) { ++ record |= BIT(i); ++ } ++ } ++ ++ if (!record) { ++ pr_info("No Valid storage device\n"); ++ return record; ++ } ++ ++ if (0) //(cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) ++ storage_post_init(); ++ ++ /*2. Enter the probe of the valid device*/ ++ for (i = 0; i < ARRAY_SIZE(device_list); i++) { ++ if (record & BIT(i)) { ++ ret = device_list[i].probe(init_flag); ++ if (ret) ++ pr_info("the 0x%x storage device probe failed\n", ++ device_list[i].index); ++ } ++ } ++ ++ return record; ++} ++ ++static struct storage_t *store_get_current(void) ++{ ++ return current; ++} ++ ++int store_set_device(enum boot_type_e type) ++{ ++ struct list_head *entry; ++ struct storage_t *dev, *store_dev = store_get_current(); ++ ++ if (!store_dev) { ++ pr_info("%s %d no current device\n", __func__, __LINE__); ++ return 1; ++ } ++ if (store_dev->type == type) ++ return 0; ++ list_for_each(entry, &store_dev->list) { ++ dev = list_entry(entry, struct storage_t, list); ++ if (dev->type == type) { ++ current = dev; ++ return 0; ++ } ++ } ++ pr_info("%s %d please confirm the %d device is valid\n", ++ __func__, __LINE__, type); ++ return 1; ++} ++ ++enum boot_type_e store_get_type(void) ++{ ++ struct storage_t *store = store_get_current(); ++ ++ if (!store) { ++ pr_info("%s %d please init storage device first\n", ++ __func__, __LINE__); ++ return BOOT_NONE; ++ } ++ ++ return store->type; ++} ++ ++int store_get_device_info(struct storage_info_t *info) ++{ ++ struct storage_t *store = store_get_current(); ++ ++ if (!store) { ++ pr_info("%s %d please init storage device first\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ ++ memcpy((char *)info, (char *)&store->info, ++ sizeof(struct storage_info_t)); ++ return 0; ++} ++ ++int store_get_device_bootloader_mode(void) ++{ ++ struct storage_t *store = store_get_current(); ++ ++ if (!store) { ++ pr_info("%s %d please init storage device first\n", ++ __func__, __LINE__); ++ return -1; ++ } ++ return store->info.mode; ++} ++ ++int store_read(const char *name, loff_t off, size_t size, void *buf) ++{ ++ struct storage_t *store = store_get_current(); ++ ++ if (!store) { ++ pr_info("%s %d please init storage device first\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ return store->read(name, off, size, buf); ++} ++ ++int store_write(const char *name, loff_t off, size_t size, void *buf) ++{ ++ struct storage_t *store = store_get_current(); ++ ++ if (!store) { ++ pr_info("%s %d please init storage device first\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ return store->write(name, off, size, buf); ++} ++ ++int store_erase(const char *name, loff_t off, size_t size, int scrub) ++{ ++ struct storage_t *store = store_get_current(); ++ ++ if (!store) { ++ pr_info("%s %d please init storage device first\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ return store->erase(name, off, size, scrub); ++} ++ ++u64 store_part_size(const char *name) ++{ ++ struct storage_t *store = store_get_current(); ++ ++ if (!store) { ++ pr_info("%s %d please init storage device first\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ return store->get_part_size(name); ++} ++ ++u8 store_boot_copy_num(const char *name) ++{ ++ struct storage_t *store = store_get_current(); ++ ++ if (!store) { ++ pr_info("%s %d please init storage device first\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ return store->get_copies(name); ++} ++ ++ ++#ifndef SYSCTRL_SEC_STATUS_REG2 ++static u32 fake_reg = 0; ++#define SYSCTRL_SEC_STATUS_REG2 (&fake_reg) ++#endif ++u8 store_boot_copy_start(void) ++{ ++ struct storage_t *store = store_get_current(); ++ //cpu_id_t cpu_id = get_cpu_id(); ++ ++ if (!store) { ++ pr_info("%s %d please init storage device first\n", ++ __func__, __LINE__); ++ return 0; ++ } ++ if (store->type != BOOT_EMMC) ++ return 0; ++ if (0) // (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) ++ return storage_get_emmc_boot_start(); ++ return 0; ++} ++ ++u8 store_bootup_bootidx(const char *name) ++{ ++ // cpu_id_t cpu_id = get_cpu_id(); ++ u8 bl2_idx = 0, fip_idx = 0; ++ u32 val = 0; ++ ++ if (0) { // cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) { ++ bl2_idx = readl(SYSCTRL_SEC_STATUS_REG2) & 0xF; ++ //TODO: fixme after robust devfip is finished. ++ fip_idx = bl2_idx; ++ } else { ++ /* accroding to the: ++ commit 975b4acbcfa686601999d56843471d98e9c0a2cd ++ storage: robust boot: record bootlog in SEC_AO_SEC_GP_CFG2 [1/2] ++ PD#SWPL-4850 ++ ... ++ record the bootup bl2/fip into SEC_AO_SEC_GP_CFG2 ++ bit[27-25] bl2 ++ bit[24-22] fip ++ */ ++ val = readl(SEC_AO_SEC_GP_CFG2); ++ bl2_idx = (val >> 25) & 0x7; ++ fip_idx = (val >> 22) & 0x7; ++ } ++ if (!strncmp(name, "bl2", sizeof("bl2")) || ++ !strncmp(name, "spl", sizeof("spl"))) ++ return bl2_idx; ++ else ++ return fip_idx; ++} ++ ++void store_restore_bootidx(void) ++{ ++ // cpu_id_t cpu_id = get_cpu_id(); ++ if (0) { // (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) { ++ extern void aml_set_bootsequence(uint32_t val); ++ aml_set_bootsequence(0x55); ++ } ++ return; ++} ++ ++u64 store_boot_copy_size(const char *name) ++{ ++ struct storage_t *store = store_get_current(); ++ ++ if (!store) { ++ pr_info("%s %d please init storage device first\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ return store->get_copy_size(name); ++} ++ ++int store_boot_read(const char *name, u8 copy, size_t size, void *buf) ++{ ++ struct storage_t *store = store_get_current(); ++ ++ if (!store) { ++ pr_info("%s %d please init storage device first\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ return store->boot_read(name, copy, size, buf); ++} ++ ++int store_boot_write(const char *name, u8 copy, size_t size, void *buf) ++{ ++ struct storage_t *store = store_get_current(); ++ ++ if (!store) { ++ pr_info("%s %d please init storage device first\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ return store->boot_write(name, copy, size, buf); ++} ++ ++int store_boot_erase(const char *name, u8 copy) ++{ ++ struct storage_t *store = store_get_current(); ++ ++ if (!store) { ++ pr_info("%s %d please init storage device first\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ return store->boot_erase(name, copy); ++} ++ ++u32 store_rsv_size(const char *name) ++{ ++ struct storage_t *store = store_get_current(); ++ ++ if (!store) { ++ pr_info("%s %d please init storage device first\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ return store->get_rsv_size(name); ++} ++ ++int store_rsv_read(const char *name, size_t size, void *buf) ++{ ++ struct storage_t *store = store_get_current(); ++ ++ if (!store) { ++ pr_info("%s %d please init storage device first\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ return store->read_rsv(name, size, buf); ++} ++ ++int store_rsv_write(const char *name, size_t size, void *buf) ++{ ++ struct storage_t *store = store_get_current(); ++ ++ if (!store) { ++ pr_info("%s %d please init storage device first\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ return store->write_rsv(name, size, buf); ++} ++ ++int store_rsv_erase(const char *name) ++{ ++ struct storage_t *store = store_get_current(); ++ ++ if (!store) { ++ pr_info("%s %d please init storage device first\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ return store->erase_rsv(name); ++} ++ ++int store_rsv_protect(const char *name, bool ops) ++{ ++ struct storage_t *store = store_get_current(); ++ ++ if (!store) { ++ pr_info("%s %d please init storage device first\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ return store->protect_rsv(name, ops); ++} ++ ++static int do_store_init(struct cmd_tbl *cmdtp, ++ int flag, int argc, char * const argv[]) ++{ ++ u32 init_flag = 1; ++ u8 ret = 0; ++ ++ if (unlikely(argc != 2 && argc != 3)) ++ return CMD_RET_USAGE; ++ ++ if (argc == 3) ++ init_flag = simple_strtoul(argv[2], NULL, 10); ++ ++ /*Returns a nonzero value: device index*/ ++ if (store_init(init_flag)) ++ ret = 0; ++ else ret = 1; ++ return ret; ++} ++ ++void store_print_device(struct storage_t *store_dev) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(device_list); i++) ++ if (store_dev->type & device_list[i].index) ++ pr_info("device type: [%s]\n", device_list[i].type); ++ pr_info("name %s\n", store_dev->info.name); ++ pr_info("id :"); ++ for (i = 0; i < ARRAY_SIZE(store_dev->info.id); i++) ++ pr_info(" 0x%x", store_dev->info.id[i]); ++ pr_info("\n"); ++ pr_info("read unit %d\n", store_dev->info.read_unit); ++ pr_info("write unit %d\n", store_dev->info.write_unit); ++ pr_info("erase unit %d\n", store_dev->info.erase_unit); ++ pr_info("total size %lld\n", store_dev->info.caps); ++ if (store_dev->info.mode) ++ pr_info("bootloader in discrete mode : %d\n", ++ store_dev->info.mode); ++ else ++ pr_info("bootloader in compact mode : %d\n", ++ store_dev->info.mode); ++} ++ ++static int do_store_device(struct cmd_tbl *cmdtp, ++ int flag, int argc, char * const argv[]) ++{ ++ if (argc == 2) { ++ struct storage_t *store_dev, *dev; ++ struct list_head *entry; ++ ++ store_dev = store_get_current(); ++ pr_info("current device:\n"); ++ pr_info("----------------------------------\n"); ++ store_print_device(store_dev); ++ pr_info("----------------------------------\n"); ++ list_for_each(entry, &store_dev->list) { ++ dev = list_entry(entry, struct storage_t, list); ++ pr_info("valid device:\n"); ++ pr_info("----------------------------------\n"); ++ store_print_device(dev); ++ pr_info("----------------------------------\n"); ++ } ++ return 0; ++ } else if (argc == 3) { ++ char *name = NULL; ++ int i = 0, ret = 0; ++ name = argv[2]; ++ for (i = 0; i < ARRAY_SIZE(device_list); i++) ++ if (!strcmp(name, device_list[i].type)) { ++ ++ ret = store_set_device(device_list[i].index); ++ if (!ret) { ++ pr_info("now current device is: %s\n", ++ name); ++ return 0; ++ } ++ } ++ pr_info("%s %d no such device: %s\n", ++ __func__, __LINE__, name); ++ return ret; ++ } ++ return CMD_RET_USAGE; ++} ++ ++static int do_store_partition(struct cmd_tbl *cmdtp, ++ int flag, int argc, char * const argv[]) ++{ ++ struct storage_t *store_dev; ++ int i = 0, partitions = 0; ++ int ret = 0; ++ char name[16]; ++ ++ if (argc > 2) ++ return CMD_RET_USAGE; ++ else { ++ store_dev = store_get_current(); ++ if (store_dev->get_part_count) ++ partitions = store_dev->get_part_count(); ++ pr_info("%d partitions of device %s:\n", ++ partitions, store_dev->info.name); ++ ++ if (store_dev->list_part_name) ++ ret = store_dev->list_part_name(i, name); ++ ++ return ret; ++ } ++} ++ ++#ifdef CONFIG_AML_MTD ++extern int is_mtd_store_boot_area(const char *part_name); ++#endif ++static int do_store_erase(struct cmd_tbl *cmdtp, ++ int flag, int argc, char * const argv[]) ++{ ++ struct storage_t *store = store_get_current(); ++ unsigned long offset; ++ size_t size = 0; ++ char *name = NULL; ++ char *s; ++ int scrub_flag = 0, ret; ++ unsigned long time; ++ ++ const char *scrub = ++ "Warning: scrub_flag is 1!!!!" ++ "scrub operation!!!\n" ++ "will erase oob area\n" ++ "There is no reliable way to recover them.\n" ++ " " ++ "are sure of what you are doing!\n" ++ "\nReally erase this NAND flash? \n"; ++ ++ if (!store) { ++ pr_info("%s %d please init your storage device first!\n", ++ __func__, __LINE__); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (strncmp(argv[1], "scrub", 5) == 0) ++ scrub_flag = 1; ++ ++ if (scrub_flag == 1) { ++ puts(scrub); ++ if (!confirm_yesno()) { ++ printf("erase aborted\n"); ++ return 1; ++ } ++ } ++ ++ /*store erase.chip*/ ++ s = strchr(argv[1], '.'); ++ if (s != NULL && strcmp(s, ".chip") == 0) { ++ offset = 0; ++ } else { ++ /*store erase normal, partition name can't NULL*/ ++ if (unlikely(argc != 5)) ++ return CMD_RET_USAGE; ++ ++ size = (size_t)simple_strtoul(argv[argc - 1], NULL, 16); ++ offset = simple_strtoul(argv[argc - 2], NULL, 16); ++ name = argv[2]; ++#ifdef CONFIG_AML_MTD ++ if (is_mtd_store_boot_area(name)) { ++ pr_info("%s %d please enter normal partition name except tpl area!\n", ++ __func__, __LINE__); ++ return CMD_RET_FAILURE; ++ } ++#endif ++ } ++ ++ time = get_timer(0); ++ ret = store->erase(name, offset, size, scrub_flag); ++ time = get_timer(time); ++ ++ if (size != 0) ++ printf("%lu bytes ", size); ++ ++ printf("erased in %lu ms", time); ++ if ((time > 0) && (size != 0)) { ++ puts(" ("); ++ print_size(div_u64(size, time) * 1000, "/s"); ++ puts(")"); ++ } ++ puts("\n"); ++ ++ return ret; ++} ++ ++static int do_store_read(struct cmd_tbl *cmdtp, ++ int flag, int argc, char * const argv[]) ++{ ++ struct storage_t *store = store_get_current(); ++ unsigned long offset, addr, time; ++ size_t size; ++ char *name = NULL; ++ int ret; ++ ++ if (!store) { ++ pr_info("%s %d please init your storage device first!\n", ++ __func__, __LINE__); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (unlikely(argc != 5 && argc != 6)) ++ return CMD_RET_USAGE; ++ ++ addr = simple_strtoul(argv[2], NULL, 16); ++ size = (size_t)simple_strtoul(argv[argc - 1], NULL, 16); ++ offset = simple_strtoul(argv[argc - 2], NULL, 16); ++ if (argc == 6) ++ name = argv[3]; ++#ifdef CONFIG_AML_MTD ++ if (is_mtd_store_boot_area(name)) { ++ pr_info("%s %d please enter normal partition name except tpl area!\n", ++ __func__, __LINE__); ++ return CMD_RET_FAILURE; ++ } ++#endif ++ time = get_timer(0); ++ ret = store->read(name, offset, size, (u_char *)addr); ++ time = get_timer(time); ++ ++ if (size != 0) ++ printf("%lu bytes ", size); ++ ++ printf("read in %lu ms", time); ++ if ((time > 0) && (size != 0)) { ++ puts(" ("); ++ print_size(div_u64(size, time) * 1000, "/s"); ++ puts(")"); ++ } ++ puts("\n"); ++ ++ return ret; ++} ++ ++static int name2index(struct boot_layout *boot_layout, const char *img) ++{ ++ boot_area_entry_t *boot_entry = NULL; ++ int i; ++ ++ boot_entry = boot_layout->boot_entry; ++ for (i = 1; i < MAX_BOOT_AREA_ENTRIES && boot_entry[i].size; i++) { ++ if (!strncmp(img, boot_entry[i].name, strlen(boot_entry[i].name))) ++ return i; ++ } ++ ++ return -1; ++} ++ ++static int do_store_write_bl2img(struct cmd_tbl *cmdtp, ++ int flag, int argc, char * const argv[]) ++{ ++ struct storage_t *store = store_get_current(); ++ unsigned long offset, addr; ++ size_t size, size_src; ++ char *name = NULL; ++ int ret = -1, index; ++ struct boot_layout *boot_layout = &general_boot_layout; ++ ++ if (!store) { ++ pr_info("%s %d please init your storage device first!\n", ++ __func__, __LINE__); ++ return CMD_RET_FAILURE; ++ } ++ ++ addr = simple_strtoul(argv[2], NULL, 16); ++ name = argv[3]; ++ size = simple_strtoul(argv[4], NULL, 16); ++ ++ index = name2index(&general_boot_layout, name); ++ offset = boot_layout->boot_entry[index].offset; ++ size_src = boot_layout->boot_entry[index].size; ++ printf("[%s] offset:0x%lx, index:%d\n", name, offset, index); ++ ++ if (size_src != size) ++ printf("new img size:0x%lx != img src:0x%lx\n", size, size_src); ++ ++ ret = store->boot_write(name, offset, size, (u_char *)addr); ++ ++ return ret; ++} ++ ++int store_write_bl2img(void* addr, const char *name, size_t size) ++{ ++ struct storage_t *store = store_get_current(); ++ unsigned long offset; ++ size_t size_src; ++ int ret = -1, index; ++ struct boot_layout *boot_layout = &general_boot_layout; ++ ++ if (!store) { ++ pr_info("%s %d please init your storage device first!\n", ++ __func__, __LINE__); ++ return CMD_RET_FAILURE; ++ } ++ ++ index = name2index(&general_boot_layout, name); ++ offset = boot_layout->boot_entry[index].offset; ++ size_src = boot_layout->boot_entry[index].size; ++ printf("[%s] offset:0x%lx, index:%d\n", name, offset, index); ++ ++ if (size_src != size) ++ printf("new img size:0x%zx != img src:0x%zx\n", size, size_src); ++ ++ ret = store->boot_write(name, offset, size, (u_char *)addr); ++ if (size != 0) ++ printf("[%s][%d]%lx bytes\n", __func__, __LINE__, size); ++ ++ return ret; ++} ++ ++static int do_store_write(struct cmd_tbl *cmdtp, ++ int flag, int argc, char * const argv[]) ++{ ++ struct storage_t *store = store_get_current(); ++ unsigned long offset, addr, time; ++ size_t size; ++ char *name = NULL; ++ int ret; ++ ++ if (!store) { ++ pr_info("%s %d please init your storage device first!\n", ++ __func__, __LINE__); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (unlikely(argc != 5 && argc != 6)) ++ return CMD_RET_USAGE; ++ ++ addr = simple_strtoul(argv[2], NULL, 16); ++ offset = simple_strtoul(argv[argc - 2], NULL, 16); ++ size = (size_t)simple_strtoul(argv[argc - 1], NULL, 16); ++ if (argc == 6) ++ name = argv[3]; ++#ifdef CONFIG_AML_MTD ++ if (is_mtd_store_boot_area(name)) { ++ pr_info("%s %d please enter normal partition name except tpl area!\n", ++ __func__, __LINE__); ++ return CMD_RET_FAILURE; ++ } ++#endif ++ time = get_timer(0); ++ ret = store->write(name, offset, size, (u_char *)addr); ++ time = get_timer(time); ++ ++ if (size != 0) ++ printf("%lu bytes ", size); ++ ++ printf("write in %lu ms", time); ++ if ((time > 0) && (size != 0)) { ++ puts(" ("); ++ print_size(div_u64(size, time) * 1000, "/s"); ++ puts(")"); ++ } ++ puts("\n"); ++ ++ return ret; ++} ++ ++static int do_store_boot_read(struct cmd_tbl *cmdtp, ++ int flag, int argc, char * const argv[]) ++{ ++ struct storage_t *store = store_get_current(); ++ unsigned long addr; ++ size_t size; ++ u8 cpy; ++ char *name; ++ ++ if (!store) { ++ pr_info("%s %d please init your storage device first!\n", ++ __func__, __LINE__); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (unlikely(argc != 6)) ++ return CMD_RET_USAGE; ++ ++ name = argv[2]; ++ addr = (unsigned long)simple_strtoul(argv[3], NULL, 16); ++ cpy = (u8)simple_strtoul(argv[4], NULL, 16); ++ size = (size_t)simple_strtoul(argv[5], NULL, 16); ++ ++ return store->boot_read(name, cpy, size, (u_char *)addr); ++} ++ ++static int bl2x_mode_check_header(p_payload_info_t pInfo) ++{ ++ p_payload_info_hdr_t hdr = &pInfo->hdr; ++ const int nItemNum = hdr->byItemNum; ++ p_payload_info_item_t pItem = pInfo->arrItems; ++ u8 i = 0; ++ int sz_payload = 0; ++ uint64_t align_size = 1; ++ struct storage_startup_parameter *ssp = &g_ssp; ++ u8 cal_copy = ssp->boot_bakups; ++ ++ printf("\naml log : info parse...\n"); ++ printf("\tsztimes : %s\n",hdr->szTimeStamp); ++ printf("\tversion : %d\n",hdr->byVersion); ++ printf("\tItemNum : %d\n",nItemNum); ++ printf("\tSize : %d(0x%x)\n", hdr->nSize, hdr->nSize); ++ if (nItemNum > 8 || nItemNum < 3) { ++ pr_info("illegal nitem num %d\n", nItemNum); ++ return __LINE__; ++ } ++ if (ssp->boot_device == BOOT_NAND_MTD) ++ align_size = ((NAND_RSV_OFFSET / cal_copy) * ssp->sip.nsp.page_size); ++ else if (ssp->boot_device == BOOT_SNAND) ++ align_size = ((NAND_RSV_OFFSET / cal_copy) * ssp->sip.snasp.pagesize); ++ ++ sz_payload = pItem->nPayLoadSize; ++ STORAGE_ROUND_UP_IF_UNALIGN(sz_payload, align_size); ++ if (sz_payload > ssp->boot_entry[0].size) ++ return __LINE__; ++ if (ssp->boot_device == BOOT_NAND_MTD) ++ align_size = ssp->sip.nsp.block_size; ++ else if (ssp->boot_device == BOOT_SNAND) ++ align_size = ssp->sip.snasp.pagesize * ++ ssp->sip.snasp.pages_per_eraseblock; ++ ++pItem; ++ ++ for (i = 1; i < nItemNum; i++, ++pItem) { ++ sz_payload = pItem->nPayLoadSize; ++ STORAGE_ROUND_UP_IF_UNALIGN(sz_payload, align_size); ++ if (sz_payload > ssp->boot_entry[i].size) ++ return __LINE__; ++ } ++ ++ return 0; ++} ++ ++static int _store_boot_write(const char *part_name, u8 cpy, size_t size, void *addr) ++{ ++ // cpu_id_t cpu_id = get_cpu_id(); ++ enum boot_type_e medium_type = store_get_type(); ++ struct storage_startup_parameter *ssp = &g_ssp; ++ //struct storage_boot_entry *boot_entry = ssp->boot_entry; ++ //u8 i; ++ int ret = 0; ++ struct storage_t *store = store_get_current(); ++ int bl2_size = BL2_SIZE; ++ int bl2_cpynum = 0; ++ int tpl_per_size = CONFIG_TPL_SIZE_PER_COPY; ++ int tpl_cpynum = 0; ++ int bootloader_maxsize = 0; ++ ++ if (store_get_device_bootloader_mode() != DISCRETE_BOOTLOADER) ++ return store->boot_write(part_name, cpy, size, (u_char *)addr); ++ ++ if (BOOT_NAND_MTD == medium_type || BOOT_SNAND == medium_type) ++ tpl_cpynum = CONFIG_NAND_TPL_COPY_NUM; ++ else if (medium_type == BOOT_SNOR) ++ tpl_cpynum = CONFIG_NOR_TPL_COPY_NUM; ++ ++ if (0) { // cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) { ++ bl2_cpynum = ssp->boot_bakups; ++ } else { ++ bootloader_maxsize = bl2_size + tpl_per_size; ++ bl2_cpynum = CONFIG_BL2_COPY_NUM; ++ if (size > bootloader_maxsize) { ++ pr_info("bootloader sz 0x%lx too large,max sz 0x%x\n", ++ size, bootloader_maxsize); ++ return CMD_RET_FAILURE; ++ } ++ } ++ ++ if ((cpy >= tpl_cpynum || cpy >= bl2_cpynum) && (cpy != BOOT_OPS_ALL)) { ++ pr_info("update copy %d invalid, must < min(%d, %d)\n", ++ cpy, tpl_cpynum, bl2_cpynum); ++ return CMD_RET_FAILURE; ++ } ++ ++ p_payload_info_t pinfo = parse_uboot_sheader((u8 *)addr); ++ ++ if (!pinfo) { ++ ret = store->boot_write("tpl", cpy, size - bl2_size, (u_char *)(addr +bl2_size)); ++ if (ret) { ++ pr_info("failed update tpl\n"); ++ return CMD_RET_FAILURE; ++ } ++ } else { ++ if (bl2x_mode_check_header(pinfo)) { ++ pr_info("!!!warning bl2xx size is bigger than bl2x layout size\n"); ++ pr_info("plase check bl2x,or erase flash and turn off\n"); ++ pr_info("then turn on, and update uboot again\n"); ++ return CMD_RET_FAILURE; ++ } ++ ++ char name[8]; ++ int nindex = 0; ++ p_payload_info_hdr_t hdr = &pinfo->hdr; ++ p_payload_info_item_t pitem = pinfo->arrItems; ++ int off_payload = 0; ++ int sz_payload = 0; ++ ++ memset(name, 0, 8); ++ for (nindex = 1, pitem +=1; nindex < hdr->byItemNum; ++nindex, ++pitem) { ++ memcpy(name, &pitem->nMagic, sizeof(unsigned int)); ++ off_payload = pitem->nOffset; ++ sz_payload = pitem->nPayLoadSize; ++ pr_info("item[%d]%4s offset 0x%08x sz 0x%x\n", ++ nindex, name, off_payload, sz_payload); ++ if (!sz_payload) ++ continue; ++ ret = store->boot_write(general_boot_part_entry[nindex].name, cpy, sz_payload, (u_char *)(addr + off_payload)); ++ if (ret) { ++ pr_info("Fail in flash payload %s\n",name); ++ return CMD_RET_FAILURE; ++ } ++ } ++ } ++ ++ ret = store->boot_write("bl2", cpy, bl2_size, (u_char *)addr); ++ if (ret) { ++ pr_info("Fail in flash payload bl2\n"); ++ return CMD_RET_FAILURE; ++ } ++ return ret; ++ ++} ++ ++static int do_store_boot_write(struct cmd_tbl *cmdtp, ++ int flag, int argc, char * const argv[]) ++{ ++ struct storage_t *store = store_get_current(); ++ unsigned long addr; ++ size_t size; ++ u8 cpy = BOOT_OPS_ALL; ++ char *name; ++ ++ if (!store) { ++ pr_info("%s %d please init your storage device first!\n", ++ __func__, __LINE__); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (unlikely(argc != 5 && argc != 6)) ++ return CMD_RET_USAGE; ++ ++ name = argv[2]; ++ addr = (unsigned long)simple_strtoul(argv[3], NULL, 16); ++ size = (size_t)simple_strtoul(argv[argc - 1], NULL, 16); ++ if (argc == 6) ++ cpy = (u8)simple_strtoul(argv[4], NULL, 16); ++ ++ if (strcmp(name, "bootloader") == 0) { ++ return _store_boot_write(name, cpy, size, (u_char *)addr); ++ } ++ ++ return store->boot_write(name, cpy, size, (u_char *)addr); ++} ++ ++static int do_store_boot_erase(struct cmd_tbl *cmdtp, ++ int flag, int argc, char * const argv[]) ++{ ++ struct storage_t *store = store_get_current(); ++ u8 cpy = BOOT_OPS_ALL; ++ char *name; ++ ++ if (!store) { ++ pr_info("%s %d please init your storage device first!\n", ++ __func__, __LINE__); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (unlikely(argc != 3 && argc != 4)) ++ return CMD_RET_USAGE; ++ ++ name = argv[2]; ++ if (argc == 4) ++ cpy = (u8)simple_strtoul(argv[3], NULL, 16); ++ ++ return store->boot_erase(name, cpy); ++} ++ ++static int do_store_rsv_ops(struct cmd_tbl *cmdtp, ++ int flag, int argc, char * const argv[]) ++{ ++ struct storage_t *store = store_get_current(); ++ char *name = NULL; ++ ++ if (!store) { ++ pr_info("%s %d please init your storage device first!\n", ++ __func__, __LINE__); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (!strcmp(argv[2], "erase")) { ++ if (argc == 3) ++ ; ++ else if (argc == 4) ++ name = argv[3]; ++ else ++ return CMD_RET_USAGE; ++ return store->erase_rsv(name); ++ } else if (!strcmp(argv[2], "read") || ++ !strcmp(argv[2], "write")) { ++ u8 cmd = strcmp(argv[2], "read") ? 0 : 1; ++ unsigned long addr = simple_strtoul(argv[4], NULL, 16); ++ size_t size = (size_t)simple_strtoul(argv[5], NULL, 16); ++ ++ name = argv[3]; ++ if (unlikely(argc != 6)) ++ return CMD_RET_USAGE; ++ if (cmd) ++ return store->read_rsv(name, size, (u_char *)addr); ++ else ++ return store->write_rsv(name, size, (u_char *)addr); ++ } else if (!strcmp(argv[2], "protect")) { ++ bool flag = false; ++ char *ops; ++ ++ if (unlikely(argc != 4 && argc != 5)) ++ return CMD_RET_USAGE; ++ ++ name = (argc == 4) ? NULL : argv[3]; ++ ops = argv[argc - 1]; ++ if (!strcmp(ops, "on")) ++ flag = true; ++ else if (!strcmp(ops, "off")) ++ flag = false; ++ return store->protect_rsv(name, flag); ++ } ++ return CMD_RET_USAGE; ++} ++ ++static struct cmd_tbl cmd_store_sub[] = { ++ U_BOOT_CMD_MKENT(init, 4, 0, do_store_init, "", ""), ++ U_BOOT_CMD_MKENT(device, 4, 0, do_store_device, "", ""), ++ U_BOOT_CMD_MKENT(partition, 3, 0, do_store_partition, "", ""), ++ U_BOOT_CMD_MKENT(scrub, 5, 0, do_store_erase, "", ""), ++ U_BOOT_CMD_MKENT(erase, 5, 0, do_store_erase, "", ""), ++ U_BOOT_CMD_MKENT(read, 6, 0, do_store_read, "", ""), ++ U_BOOT_CMD_MKENT(write, 7, 0, do_store_write, "", ""), ++ U_BOOT_CMD_MKENT(write_bl2img, 5, 0, do_store_write_bl2img, "", ""), ++ U_BOOT_CMD_MKENT(boot_read, 6, 0, do_store_boot_read, "", ""), ++ U_BOOT_CMD_MKENT(boot_write, 6, 0, do_store_boot_write, "", ""), ++ U_BOOT_CMD_MKENT(boot_erase, 4, 0, do_store_boot_erase, "", ""), ++ U_BOOT_CMD_MKENT(rsv, 6, 0, do_store_rsv_ops, "", ""), ++}; ++ ++static int do_store(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ struct cmd_tbl *c; ++ ++ if (argc < 2) ++ return CMD_RET_USAGE; ++ ++ c = find_cmd_tbl(argv[1], cmd_store_sub, ARRAY_SIZE(cmd_store_sub)); ++ if (c) ++ return c->cmd(cmdtp, flag, argc, argv); ++ ++ return CMD_RET_USAGE; ++} ++ ++U_BOOT_CMD(store, CONFIG_SYS_MAXARGS, 1, do_store, ++ "STORE sub-system:", ++ "store init [flag]\n" ++ " init storage device\n" ++ "store device [name]\n" ++ " show or set storage device\n" ++ " 'store device' command will list\n" ++ " all valid storage device and print.\n" ++ " 'store device [name]' will set the\n" ++ " [name] device to the current device\n" ++ "store partition\n" ++ " show partitions of current device\n" ++ "store read addr [partition name] off size\n" ++ " read 'size' bytes from offset 'off'\n" ++ " of device/partition 'partition name' to.\n" ++ " address 'addr' of memory.\n" ++ " if partition name not value. read start with\n" ++ " offset in normal logic area,if tpl area exist\n" ++ " read offset at end of tpl area\n" ++ "store write addr [partition name] off size\n" ++ " write 'size' bytes to offset 'off' of\n" ++ " device/partition [partition name] from\n" ++ " address 'addr' of memory.\n" ++ " if partition name not value. write start with\n" ++ " offset in normal logic area,if tpl area exist\n" ++ " write offset at end of tpl area\n" ++ "store erase partition name off size.\n" ++ " erase 'size' bytes from offset 'off'\n" ++ " of device/partition [partition name]\n" ++ " partition name must't NULL\n" ++ "store scrub partition name off size.\n" ++ " erase 'size' bytes from offset 'off'\n" ++ " of device/partition [partition name]\n" ++ " includes oob area if the device has.\n" ++ " partition name must't NULL\n" ++ "store erase.chip\n" ++ " erase all nand chip,except bad block\n" ++ "store scrub.chip\n" ++ " erase all nand chip,include bad block\n" ++ "store boot_read name addr copy size\n" ++ " read 'size' bytes from 'copy'th backup\n" ++ " in name partition, 'copy' can't be null.\n" ++ " name:\n" ++ " in discrete mode: 'bl2'/'tpl'(fip)\n" ++ " in compact mode: 'bootloader'\n" ++ "store boot_write name addr [copy] size\n" ++ " write 'size' bytes to 'copy'th backup\n" ++ " in [name] partition from address\n" ++ " 'addr' of memory. when the optional 'copy'\n" ++ " is null, it will writes to all copies\n" ++ " name:\n" ++ " in discrete mode:\n" ++ " 'bl2/bl2e/bl2x/ddrfip/tpl(fip), only update part\n" ++ " 'bootloader', update whole uboot.bin, in this case\n" ++ " @copy:if used, must < min(tplCpyNum, Bl2CpyNum), update only the specified copy\n" ++ " if not used, update all the copies of bl2 bl2e bl2x ddrfip tpl!\n" ++ " in compact mode: 'bootloader'\n" ++ "store boot_erase name [copy]\n" ++ " erase the name info from 'copy'th backup\n" ++ " when the optional 'copy' not value, it\n" ++ " will erase all copies.\n" ++ " name:\n" ++ " in discrete mode: \n" ++ " 'bl2'/'tpl'(fip): erase bl2/tpl partition\n" ++ " 'bootloader':erase bl2 + tpl partition\n" ++ " in compact mode: 'bootloader'\n" ++ "store rsv read name addr size\n" ++ " read 'size' bytes 'name' rsv info\n" ++ " to address 'addr' of memory\n" ++ " 'name' could be key/dtb/env etc...\n" ++ "store rsv write name addr size\n" ++ " write 'size' bytes 'name' rsv info\n" ++ " from address 'addr' of memory\n" ++ "store rsv erase name\n" ++ " erase 'name' rsv info\n" ++ " name must't null\n" ++ "store rsv protect name on/off\n" ++ " turn on/off the rsv info protection\n" ++ " name must't null\n" ++); +diff --git a/common/aml_dt.c b/common/aml_dt.c +new file mode 100644 +index 00000000000..a6888999d44 +--- /dev/null ++++ b/common/aml_dt.c +@@ -0,0 +1,600 @@ ++/* ++* Copyright (C) 2017 Amlogic, Inc. All rights reserved. ++* * ++This program is free software; you can redistribute it and/or modify ++* it under the terms of the GNU General Public License as published by ++* the Free Software Foundation; either version 2 of the License, or ++* (at your option) any later version. ++* * ++This program is distributed in the hope that it will be useful, but WITHOUT ++* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++* more details. ++* * ++You should have received a copy of the GNU General Public License along ++* with this program; if not, write to the Free Software Foundation, Inc., ++* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++* * ++Description: ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#define AML_DT_DEBUG ++#ifdef AML_DT_DEBUG ++#define dbg_printf(...) printf(__VA_ARGS__) ++#else ++#define dbg_printf(...) ((void)0) ++#endif ++ ++#define AML_MULTI_DTB_API_NEW ++//#define AML_MULTI_DTB_CHECK_CMD //command for multi-dtb test ++ ++#ifdef AML_MULTI_DTB_API_NEW ++ ++/*for multi-dtb gzip buffer*/ ++#define GUNZIP_BUF_SIZE (1<<20) /*1MB is enough?*/ ++ ++/*magic for multi-dtb*/ ++#define MAGIC_GZIP_MASK (0x0000FFFF) ++#define MAGIC_GZIP_ID (0x00008B1F) ++#define IS_GZIP_PACKED(nMagic) (MAGIC_GZIP_ID == (MAGIC_GZIP_MASK & nMagic)) ++#define MAGIC_DTB_SGL_ID (0xedfe0dd0) ++#define MAGIC_DTB_MLT_ID (0x5f4c4d41) ++ ++/*amlogic multi-dtb version*/ ++#define AML_MUL_DTB_VER_1 (1) ++#define AML_MUL_DTB_VER_2 (2) ++ ++/*max char for dtb name, fixed to soc_package_board format*/ ++#define AML_MAX_DTB_NAME_SIZE (128) ++#define AML_DTB_TOKEN_MAX_COUNT (AML_MAX_DTB_NAME_SIZE>>1) ++ ++typedef struct{ ++ unsigned int nMagic; ++ unsigned int nVersion; ++ unsigned int nDTBCount; ++}st_dtb_hdr_t,*p_st_dtb_hdr_t; ++ ++/*v1,v2 multi-dtb only support max to 3 tokens for each DTB name*/ ++#define MULTI_DTB_TOKEN_MAX_COUNT (3) ++#define MULTI_DTB_TOKEN_UNIT_SIZE_V1 (4) //v1 support 4bytes for each token ++#define MULTI_DTB_TOKEN_UNIT_SIZE_V2 (16) //v2 support 16bytes for each token ++ ++/*v1 multi-dtb*/ ++typedef struct{ ++ unsigned char szToken[MULTI_DTB_TOKEN_MAX_COUNT][MULTI_DTB_TOKEN_UNIT_SIZE_V1]; ++ int nDTBOffset; ++ int nDTBIMGSize; ++}st_dtb_token_v1_t,*p_st_dtb_token_v1_t; ++ ++typedef struct{ ++ st_dtb_hdr_t hdr; ++ st_dtb_token_v1_t dtb[1]; ++}st_dtb_v1_t,*p_st_dtb_v1_t; ++ ++ ++/*v2 multi-dtb*/ ++typedef struct{ ++ unsigned char szToken[MULTI_DTB_TOKEN_MAX_COUNT][MULTI_DTB_TOKEN_UNIT_SIZE_V2]; ++ int nDTBOffset; ++ int nDTBIMGSize; ++}st_dtb_token_v2_t,*p_st_dtb_token_v2_t; ++ ++typedef struct{ ++ st_dtb_hdr_t hdr; ++ st_dtb_token_v2_t dtb[1]; ++}st_dtb_v2_t,*p_st_dtb_v2_t; ++ ++ ++/*to get the valid DTB index with matched DTB name*/ ++static int get_dtb_index(const char aml_dt_buf[128],unsigned long fdt_addr) ++{ ++ int nReturn = -1; ++ ++ if (!aml_dt_buf) ++ goto exit; ++ ++ p_st_dtb_hdr_t pDTBHdr = (p_st_dtb_hdr_t)fdt_addr; ++ char sz_aml_dt_msb[10][MULTI_DTB_TOKEN_UNIT_SIZE_V2]; ++ memset(sz_aml_dt_msb,0,sizeof(sz_aml_dt_msb)); ++ ++ /* split aml_dt with token '_', e.g "tm2-revb_t962x3_ab301" */ ++ //printf(" aml_dt : %s\n",aml_dt_buf); ++ ++ char *tokens[AML_DTB_TOKEN_MAX_COUNT]; ++ char sz_temp[AML_MAX_DTB_NAME_SIZE+4]; ++ memset(tokens,0,sizeof(tokens)); ++ memset(sz_temp,0,sizeof(sz_temp)); ++ strncpy(sz_temp,aml_dt_buf,128); ++ int i,j; ++ int nLen = strlen(sz_temp); ++ sz_temp[nLen]='_'; ++ sz_temp[nLen+1]='\0'; ++ nLen +=1; ++ tokens[0]=sz_temp; ++ for (i = 1; i < sizeof(tokens)/sizeof(tokens[0]); i++) ++ { ++ tokens[i] = strstr(tokens[i-1],"_"); ++ if (!tokens[i]) ++ break; ++ ++ *tokens[i]='\0'; ++ ++ tokens[i]=tokens[i]+1; ++ ++ if (!(*tokens[i])) ++ { ++ tokens[i] = 0; ++ break; ++ } ++ } ++ ++ //for (i=0;i<10 && tokens[i];++i) ++ // printf("token-%d:%s\n",i,tokens[i]); ++ ++ int nTokenLen = 0; ++ ++ switch (pDTBHdr->nVersion) ++ { ++ case AML_MUL_DTB_VER_1: ++ { ++ nTokenLen = MULTI_DTB_TOKEN_UNIT_SIZE_V1; ++ }break; ++ case AML_MUL_DTB_VER_2: ++ { ++ nTokenLen = MULTI_DTB_TOKEN_UNIT_SIZE_V2; ++ }break; ++ default: goto exit; break; ++ } ++ ++ ++ for (i = 0;i> ((3-m)<<3)) & 0xFF; ++ ++ /*replace 0 with 0x20*/ ++ for (m=0;mnVersion) ++ { ++ case AML_MUL_DTB_VER_1: ++ { ++ p_st_dtb_v1_t pDTB_V1 = (p_st_dtb_v1_t)fdt_addr; ++ for (i=0;i< pDTB_V1->hdr.nDTBCount;++i) ++ { ++ if (!memcmp(pDTB_V1->dtb[i].szToken,sz_aml_dt_msb, ++ MULTI_DTB_TOKEN_MAX_COUNT*nTokenLen)) ++ { ++ nReturn = i; ++ break; ++ } ++ } ++ ++ }break; ++ case AML_MUL_DTB_VER_2: ++ { ++ p_st_dtb_v2_t pDTB_V2 = (p_st_dtb_v2_t)fdt_addr; ++ for (i=0;i< pDTB_V2->hdr.nDTBCount;++i) ++ { ++ if (!memcmp(pDTB_V2->dtb[i].szToken,sz_aml_dt_msb, ++ MULTI_DTB_TOKEN_MAX_COUNT*nTokenLen)) ++ { ++ nReturn = i; ++ break; ++ } ++ } ++ ++ }break; ++ default: goto exit; break; ++ } ++ ++exit: ++ ++ return nReturn; ++ ++} ++ ++unsigned long __attribute__((unused)) get_multi_dt_entry(unsigned long fdt_addr) ++{ ++ unsigned long lReturn = 0; //return buffer for valid DTB; ++ void * gzip_buf = NULL; ++ unsigned long pInputFDT = fdt_addr; ++ p_st_dtb_hdr_t pDTBHdr = (p_st_dtb_hdr_t)pInputFDT; ++ unsigned long unzip_size = GUNZIP_BUF_SIZE; ++ ++ printf(" Amlogic Multi-DTB tool\n"); ++ ++ /* first check the blob header, support GZIP format */ ++ if ( IS_GZIP_PACKED(pDTBHdr->nMagic)) ++ { ++ printf(" GZIP format, decompress...\n"); ++ gzip_buf = malloc(GUNZIP_BUF_SIZE); ++ if (!gzip_buf) ++ { ++ printf(" ERROR! fail to allocate memory for GUNZIP...\n"); ++ goto exit; ++ } ++ memset(gzip_buf, 0, GUNZIP_BUF_SIZE); ++ if (gunzip(gzip_buf, GUNZIP_BUF_SIZE, (void *)pInputFDT, &unzip_size) < 0) ++ { ++ printf(" ERROR! GUNZIP process fail...\n"); ++ goto exit; ++ } ++ if (unzip_size > GUNZIP_BUF_SIZE) ++ { ++ printf(" ERROR! GUNZIP overflow...\n"); ++ goto exit; ++ } ++ //memcpy((void*)fdt_addr,gzip_buf,unzip_size); ++ pInputFDT = (unsigned long)gzip_buf; ++ pDTBHdr = (p_st_dtb_hdr_t)pInputFDT; ++ } ++ ++ ++ switch (pDTBHdr->nMagic) ++ { ++ case MAGIC_DTB_SGL_ID: ++ { ++ printf(" Single DTB detected\n"); ++ ++ if (fdt_addr != (unsigned long)pInputFDT) //in case of GZIP single DTB ++ memcpy((void*)fdt_addr,(void*)pInputFDT,unzip_size); ++ ++ lReturn = fdt_addr; ++ ++ }break; ++ case MAGIC_DTB_MLT_ID: ++ { ++ printf(" Multi DTB detected.\n"); ++ printf(" Multi DTB tool version: v%d.\n", pDTBHdr->nVersion); ++ printf(" Support %d DTBS.\n", pDTBHdr->nDTBCount); ++ ++ ++ /* check and set aml_dt */ ++ char aml_dt_buf[AML_MAX_DTB_NAME_SIZE+4]; ++ memset(aml_dt_buf, 0, sizeof(aml_dt_buf)); ++ ++ /* update 2016.07.27, checkhw and setenv everytime, ++ or else aml_dt will set only once if it is reserved */ ++ extern int checkhw(char * name); ++#if 1 ++ if (checkhw(aml_dt_buf) < 0 || strlen(aml_dt_buf) <= 0) ++ { ++ printf(" Get env aml_dt failed!\n"); ++ goto exit; ++ } ++#else ++ char *aml_dt = getenv(AML_DT_UBOOT_ENV); ++ /* if aml_dt not exist or env not ready, get correct dtb by name */ ++ if (NULL == aml_dt) ++ checkhw(aml_dt_buf); ++ else ++ memcpy(aml_dt_buf, aml_dt, ++ (strlen(aml_dt)>AML_MAX_DTB_NAME_SIZE?AML_MAX_DTB_NAME_SIZE:(strlen(aml_dt)+1))); ++#endif ++ ++ int dtb_match_num = get_dtb_index(aml_dt_buf,(unsigned long)pInputFDT); ++ ++ /*check valid dtb index*/ ++ if (dtb_match_num < 0 || dtb_match_num >= pDTBHdr->nDTBCount) ++ { ++ printf(" NOT found matched DTB for \"%s\"\n",aml_dt_buf); ++ goto exit; ++ } ++ ++ printf(" Found DTB for \"%s\"\n",aml_dt_buf); ++ ++ switch (pDTBHdr->nVersion) ++ { ++ case AML_MUL_DTB_VER_1: ++ { ++ p_st_dtb_v1_t pDTB_V1 = (p_st_dtb_v1_t)pInputFDT; ++ lReturn = pDTB_V1->dtb[dtb_match_num].nDTBOffset + pInputFDT; ++ ++ if (pInputFDT != fdt_addr) ++ { ++ memcpy((void*)fdt_addr, (void*)lReturn,pDTB_V1->dtb[dtb_match_num].nDTBIMGSize); ++ lReturn = fdt_addr; ++ } ++ ++ }break; ++ case AML_MUL_DTB_VER_2: ++ { ++ p_st_dtb_v2_t pDTB_V2 = (p_st_dtb_v2_t)pInputFDT; ++ lReturn = pDTB_V2->dtb[dtb_match_num].nDTBOffset + pInputFDT; ++ ++ if (pInputFDT != fdt_addr) ++ { ++ memcpy((void*)fdt_addr, (void*)lReturn,pDTB_V2->dtb[dtb_match_num].nDTBIMGSize); ++ lReturn = fdt_addr; ++ } ++ ++ }break; ++ default: ++ { ++ printf(" Invalid Multi-DTB Version [%d]!\n", ++ pDTBHdr->nVersion); ++ goto exit; ++ }break; ++ } ++ ++ }break; ++ default: goto exit; break; ++ } ++ ++exit: ++ ++ if (gzip_buf) ++ { ++ free(gzip_buf); ++ gzip_buf = 0; ++ } ++ ++ return lReturn; ++} ++ ++#else //#ifdef AML_MULTI_DTB_API_NEW ++ ++#define AML_DT_IND_LENGTH_V1 4 /*fixed*/ ++#define AML_DT_IND_LENGTH_V2 16 /*fixed*/ ++ ++#define AML_DT_IND_LENGTH 16 ++#define AML_DT_ID_VARI_TOTAL 3 //Total 3 strings ++#define AML_DT_EACH_ID_INT (AML_DT_IND_LENGTH / 4) ++ ++/*Latest version: v2*/ ++#define AML_DT_VERSION_OFFSET 4 ++#define AML_DT_TOTAL_DTB_OFFSET 8 ++#define AML_DT_FIRST_DTB_OFFSET 12 ++//#define AML_DT_DTB_HEADER_SIZE (8+(AML_DT_IND_LENGTH * AML_DT_ID_VARI_TOTAL)) ++#define AML_DT_DTB_DT_INFO_OFFSET 0 ++//#define AML_DT_DTB_OFFSET_OFFSET (AML_DT_IND_LENGTH * AML_DT_ID_VARI_TOTAL) ++//#define AML_DT_DTB_SIZE_OFFSET 16 ++ ++#define AML_DT_UBOOT_ENV "aml_dt" ++#define DT_HEADER_MAGIC 0xedfe0dd0 /*header of dtb file*/ ++#define AML_DT_HEADER_MAGIC 0x5f4c4d41 /*"AML_", multi dtbs supported*/ ++ ++#define IS_GZIP_FORMAT(data) ((data & (0x0000FFFF)) == (0x00008B1F)) ++#define GUNZIP_BUF_SIZE (0x500000) /* 5MB */ ++#define DTB_MAX_SIZE (AML_DTB_IMG_MAX_SZ) ++ ++//#define readl(addr) (*(volatile unsigned int*)(addr)) ++extern int checkhw(char * name); ++ ++unsigned long __attribute__((unused)) ++ get_multi_dt_entry(unsigned long fdt_addr){ ++ unsigned int dt_magic = readl(fdt_addr); ++ unsigned int dt_total = 0; ++ unsigned int dt_tool_version = 0; ++ unsigned int gzip_format = 0; ++ void * gzip_buf = NULL; ++ unsigned long dt_entry = fdt_addr; ++ ++ printf(" Amlogic multi-dtb tool\n"); ++ ++ /* first check the file header, support GZIP format */ ++ gzip_format = IS_GZIP_FORMAT(dt_magic); ++ if (gzip_format) { ++ printf(" GZIP format, decompress...\n"); ++ gzip_buf = malloc(GUNZIP_BUF_SIZE); ++ memset(gzip_buf, 0, GUNZIP_BUF_SIZE); ++ unsigned long unzip_size = GUNZIP_BUF_SIZE; ++ gunzip(gzip_buf, GUNZIP_BUF_SIZE, (void *)fdt_addr, &unzip_size); ++ dbg_printf(" DBG: unzip_size: 0x%x\n", (unsigned int)unzip_size); ++ if (unzip_size > GUNZIP_BUF_SIZE) { ++ printf(" Warning! GUNZIP overflow...\n"); ++ } ++ fdt_addr = (unsigned long)gzip_buf; ++ dt_magic = readl(fdt_addr); ++ } ++ ++ dbg_printf(" DBG: fdt_addr: 0x%x\n", (unsigned int)fdt_addr); ++ dbg_printf(" DBG: dt_magic: 0x%x\n", (unsigned int)dt_magic); ++ ++ /*printf(" Process device tree. dt magic: %x\n", dt_magic);*/ ++ if (dt_magic == DT_HEADER_MAGIC) {/*normal dtb*/ ++ printf(" Single dtb detected\n"); ++ if (gzip_format) { ++ memcpy((void *)dt_entry, (void *)fdt_addr, DTB_MAX_SIZE); ++ fdt_addr = dt_entry; ++ if (gzip_buf) ++ free(gzip_buf); ++ } ++ return fdt_addr; ++ } ++ else if (dt_magic == AML_DT_HEADER_MAGIC) {/*multi dtb*/ ++ printf(" Multi dtb detected\n"); ++ /* check and set aml_dt */ ++ int i = 0; ++ char *aml_dt_buf; ++ aml_dt_buf = (char *)malloc(sizeof(char)*64); ++ printf("Multi dtb malloc aml_dt_buf addr = %p\n", aml_dt_buf); ++ memset(aml_dt_buf, 0, sizeof(aml_dt_buf)); ++ ++ /* update 2016.07.27, checkhw and setenv everytime, ++ or else aml_dt will set only once if it is reserved */ ++#if 1 ++ checkhw(aml_dt_buf); ++#else ++ char *aml_dt = getenv(AML_DT_UBOOT_ENV); ++ /* if aml_dt not exist or env not ready, get correct dtb by name */ ++ if (NULL == aml_dt) ++ checkhw(aml_dt_buf); ++ else ++ memcpy(aml_dt_buf, aml_dt, (strlen(aml_dt)>64?64:(strlen(aml_dt)+1))); ++#endif ++ ++ unsigned int aml_dt_len = aml_dt_buf ? strlen(aml_dt_buf) : 0; ++ if (aml_dt_len <= 0) { ++ printf(" Get env aml_dt failed!\n"); ++ if (aml_dt_buf) ++ free(aml_dt_buf); ++ if (gzip_buf) ++ free(gzip_buf); ++ return fdt_addr; ++ } ++ ++ /*version control, compatible with v1*/ ++ dt_tool_version = readl(fdt_addr + AML_DT_VERSION_OFFSET); ++ unsigned int aml_each_id_length=0; ++ unsigned int aml_dtb_offset_offset; ++ unsigned int aml_dtb_header_size; ++ if (dt_tool_version == 1) ++ aml_each_id_length = 4; ++ else if(dt_tool_version == 2) ++ aml_each_id_length = 16; ++ ++ aml_dtb_offset_offset = aml_each_id_length * AML_DT_ID_VARI_TOTAL; ++ aml_dtb_header_size = 8+(aml_each_id_length * AML_DT_ID_VARI_TOTAL); ++ printf(" Multi dtb tool version: v%d .\n", dt_tool_version); ++ ++ /*fdt_addr + 0x8: num of dtbs*/ ++ dt_total = readl(fdt_addr + AML_DT_TOTAL_DTB_OFFSET); ++ printf(" Support %d dtbs.\n", dt_total); ++ ++ /* split aml_dt to 3 strings */ ++ char *tokens[3] = {NULL, NULL, NULL}; ++ for (i = 0; i < AML_DT_ID_VARI_TOTAL; i++) { ++ tokens[i] = strsep(&aml_dt_buf, "_"); ++ } ++ //if (aml_dt_buf) ++ //free(aml_dt_buf); ++ printf(" aml_dt soc: %s platform: %s variant: %s\n", tokens[0], tokens[1], tokens[2]); ++ ++ /*match and print result*/ ++ char **dt_info; ++ dt_info = (char **)malloc(sizeof(char *)*AML_DT_ID_VARI_TOTAL); ++ for (i = 0; i < AML_DT_ID_VARI_TOTAL; i++) ++ dt_info[i] = (char *)malloc(sizeof(char)*aml_each_id_length); ++ unsigned int dtb_match_num = 0xffff; ++ unsigned int x = 0, y = 0, z = 0; //loop counter ++ unsigned int read_data; ++ for (i = 0; i < dt_total; i++) { ++ for (x = 0; x < AML_DT_ID_VARI_TOTAL; x++) { ++ for (y = 0; y < aml_each_id_length; y+=4) { ++ read_data = readl(fdt_addr + AML_DT_FIRST_DTB_OFFSET + \ ++ i * aml_dtb_header_size + AML_DT_DTB_DT_INFO_OFFSET + \ ++ (x * aml_each_id_length) + y); ++ dt_info[x][y+0] = (read_data >> 24) & 0xff; ++ dt_info[x][y+1] = (read_data >> 16) & 0xff; ++ dt_info[x][y+2] = (read_data >> 8) & 0xff; ++ dt_info[x][y+3] = (read_data >> 0) & 0xff; ++ } ++ for (z=0; z 1) ++ loadaddr = simple_strtoul(argv[1],NULL,16); ++ ++ check_valid_dts((void*)loadaddr); ++ ++ return 0; ++} ++ ++U_BOOT_CMD( ++ dtb_chk, //command name ++ 2, //maxargs ++ 0, //repeatable ++ do_test, //command function ++ "multi-dtb check command", //description ++ " argv: dtb_chk \n" //usage ++ " do dtb check, which already loaded at .\n" ++); ++#endif //#ifdef AML_MULTI_DTB_CHECK_CMD +diff --git a/common/partitions.c b/common/partitions.c +new file mode 100644 +index 00000000000..25ad5e447d8 +--- /dev/null ++++ b/common/partitions.c +@@ -0,0 +1,206 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_MULTI_DTB ++ extern unsigned long get_multi_dt_entry(unsigned long fdt_addr); ++#endif ++ ++struct partitions_data{ ++ int nr; ++ struct partitions *parts; ++}; ++ ++struct partitions *part_table = NULL; ++static int parts_total_num; ++int has_boot_slot = 0; ++int has_system_slot = 0; ++bool dynamic_partition = false; ++bool vendor_boot_partition = false; ++ ++int get_partitions_table(struct partitions **table) ++{ ++ int ret = 0; ++ if (part_table && parts_total_num) { ++ *table = part_table; ++ ret = parts_total_num; ++ } ++ return ret; ++} ++int get_partition_count(void) ++{ ++ return parts_total_num; ++} ++struct partitions *get_partitions(void) ++{ ++ return part_table; ++} ++ ++void free_partitions(void) ++{ ++ if (part_table) ++ free(part_table); ++ part_table = NULL; ++} ++ ++#ifndef IS_FEAT_BOOT_VERIFY ++#define IS_FEAT_BOOT_VERIFY() 0 ++#endif// #ifndef IS_FEAT_BOOT_VERIFY ++ ++/* ++ return 0 if dts is valid ++ other value are falure. ++*/ ++int check_valid_dts(unsigned char *buffer) ++{ ++ int ret = -__LINE__; ++ char *dt_addr; ++ /* fixme, a work around way */ ++ unsigned char *sbuffer = (unsigned char *)env_get_hex("loadaddr", 0x1000000 + 0x100000); ++ /* g12a merge to trunk, use trunk code */ ++ //unsigned char *sbuffer = (unsigned char *)0x1000000; ++ ++ if (IS_FEAT_BOOT_VERIFY()) { ++ memcpy(sbuffer, buffer, AML_DTB_IMG_MAX_SZ); ++ flush_cache((unsigned long)sbuffer, AML_DTB_IMG_MAX_SZ); ++ ret = aml_sec_boot_check(AML_D_P_IMG_DECRYPT, (long unsigned)sbuffer, AML_DTB_IMG_MAX_SZ, 0); ++ if (ret) { ++ printf("\n %s() %d: Decrypt dtb: Sig Check %d\n", __func__, __LINE__, ret); ++ return -__LINE__; ++ } ++ memcpy(buffer, sbuffer, AML_DTB_IMG_MAX_SZ); ++ } ++#ifdef CONFIG_MULTI_DTB ++ dt_addr = (char *)get_multi_dt_entry((unsigned long)buffer); ++#else ++ dt_addr = (char *)buffer; ++#endif ++ pr_debug("start dts,buffer=%p,dt_addr=%p\n", buffer, dt_addr); ++ ret = fdt_check_header(dt_addr); ++ if ( ret < 0 ) ++ printf("%s: %s\n",__func__,fdt_strerror(ret)); ++ /* fixme, is it 0 when ok? */ ++ return ret; ++} ++ ++int get_partition_from_dts(unsigned char *buffer) ++{ ++ char *dt_addr; ++ int nodeoffset,poffset=0; ++ int *parts_num; ++ char propname[8]; ++ const uint32_t *phandle; ++ const char *uname; ++ const char *usize; ++ const char *umask; ++ int index; ++ int ret = -1; ++ ++ if ( buffer == NULL) ++ goto _err; ++ ++ ret = check_valid_dts(buffer); ++ printf("%s() %d: ret %d\n",__func__, __LINE__, ret); ++ if ( ret < 0 ) ++ { ++ printf("%s() %d: ret %d\n",__func__, __LINE__, ret); ++ goto _err; ++ } ++#ifdef CONFIG_MULTI_DTB ++ dt_addr = (char *)get_multi_dt_entry((unsigned long)buffer); ++#else ++ dt_addr = (char *)buffer; ++#endif ++ nodeoffset = fdt_path_offset(dt_addr, "/partitions"); ++ if (nodeoffset < 0) ++ { ++ printf("%s: not find /partitions node %s.\n",__func__,fdt_strerror(nodeoffset)); ++ ret = -1; ++ goto _err; ++ } ++ parts_num = (int *)fdt_getprop(dt_addr, nodeoffset, "parts", NULL); ++ printf("parts: %d\n",be32_to_cpup((u32*)parts_num)); ++ ++ if (parts_num > 0) ++ { ++ part_table = (struct partitions *)malloc(sizeof(struct partitions)*(be32_to_cpup((u32*)parts_num))); ++ if (!part_table) { ++ printk("%s part_table alloc _err\n",__func__); ++ //kfree(data); ++ return -1; ++ } ++ memset(part_table, 0, sizeof(struct partitions)*(be32_to_cpup((u32*)parts_num))); ++ parts_total_num = be32_to_cpup((u32*)parts_num); ++ } ++ dynamic_partition = false; ++ env_set("partiton_mode","normal"); ++ vendor_boot_partition = false; ++ env_set("vendor_boot_mode","false"); ++ for (index = 0; index < be32_to_cpup((u32*)parts_num); index++) ++ { ++ sprintf(propname,"part-%d", index); ++ ++ phandle = fdt_getprop(dt_addr, nodeoffset, propname, NULL); ++ if (!phandle) { ++ printf("don't find match part-%d\n",index); ++ goto _err; ++ } ++ if (phandle) { ++ poffset = fdt_node_offset_by_phandle(dt_addr, be32_to_cpup((u32*)phandle)); ++ if (!poffset) { ++ printf("%s:%d,can't find device node\n",__func__,__LINE__); ++ goto _err; ++ } ++ } ++ uname = fdt_getprop(dt_addr, poffset, "pname", NULL); ++ //printf("%s:%d uname: %s\n",__func__,__LINE__, uname); ++ /* a string but not */ ++ usize = fdt_getprop(dt_addr, poffset, "size", NULL); ++ //printf("%s:%d size: 0x%x 0x%x\n",__func__,__LINE__, be32_to_cpup((u32*)usize), be32_to_cpup((((u32*)usize)+1))); ++ umask = fdt_getprop(dt_addr, poffset, "mask", NULL); ++ //printf("%s:%d mask: 0x%x\n",__func__,__LINE__, be32_to_cpup((u32*)umask)); ++ /* fill parition table */ ++ if (uname != NULL) ++ memcpy(part_table[index].name, uname, strlen(uname)); ++ part_table[index].size = ((unsigned long)be32_to_cpup((u32*)usize) << 32) | (unsigned long)be32_to_cpup((((u32*)usize)+1)); ++ part_table[index].mask_flags = be32_to_cpup((u32*)umask); ++ printf("%02d:%10s\t%016llx %01x\n", index, uname, part_table[index].size, part_table[index].mask_flags); ++ ++ if (strcmp(uname, "boot_a") == 0) { ++ has_boot_slot = 1; ++ printf("set has_boot_slot = 1\n"); ++ } ++ else if (strcmp(uname, "boot") == 0) { ++ has_boot_slot = 0; ++ printf("set has_boot_slot = 0\n"); ++ } ++ if (strcmp(uname, "system_a") == 0) ++ has_system_slot = 1; ++ else if (strcmp(uname, "system") == 0) ++ has_system_slot = 0; ++ ++ if (strcmp(uname, "super") == 0) { ++ dynamic_partition = true; ++ env_set("partiton_mode","dynamic"); ++ printf("enable dynamic_partition\n"); ++ } ++ ++ if (strncmp(uname, "vendor_boot", 11) == 0) { ++ vendor_boot_partition = true; ++ env_set("vendor_boot_mode","true"); ++ printf("enable vendor_boot\n"); ++ } ++ } ++ return 0; ++ ++_err: ++ if (part_table != NULL) { ++ free(part_table); ++ part_table = NULL; ++ } ++ return ret; ++} +diff --git a/disk/part_aml.c b/disk/part_aml.c +new file mode 100644 +index 00000000000..828a1b2d5c3 +--- /dev/null ++++ b/disk/part_aml.c +@@ -0,0 +1,110 @@ ++/* ++ * (C) Copyright 2001 ++ * Yonghui.yu , Amlogic Inc, yonghui.yu@amlogic.com. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_HAVE_BLOCK_DEVICE ++extern int get_part_info_from_tbl(struct blk_desc * dev_desc, ++ int part_num, struct disk_partition * info); ++int get_part_info_by_name(struct blk_desc *dev_desc, ++ const char *name, struct disk_partition *info); ++#define AML_PART_DEBUG (0) ++ ++#if (AML_PART_DEBUG) ++#define PRINTF(fmt,args...) printf (fmt ,##args) ++#else ++#define PRINTF(fmt,args...) ++#endif ++ ++#define AML_SEC_SIZE (512) ++#define MAGIC_OFFSET (1) ++ ++/* read back boot partitons */ ++static int _get_partition_info_aml(struct blk_desc * dev_desc, ++ int part_num, struct disk_partition * info, int verb) ++{ ++ int ret = 0; ++ ++ if (UCLASS_MMC != dev_desc->if_type) ++ return -1; ++ ++ info->blksz=dev_desc->blksz; ++ sprintf ((char *)info->type, "U-Boot"); ++ /* using partition name in partition tables */ ++ ret = get_part_info_from_tbl(dev_desc, part_num, info); ++ if (ret) { ++ /*printf ("** Partition %d not found on device %d **\n", ++ part_num,dev_desc->devnum);*/ ++ return -1; ++ } ++ ++ PRINTF(" part %d found @ %lx size %lx\n",part_num,info->start,info->size); ++ return 0; ++} ++ ++int get_partition_info_aml(struct blk_desc * dev_desc, ++ int part_num, struct disk_partition * info) ++{ ++ return(_get_partition_info_aml(dev_desc, part_num, info, 1)); ++} ++ ++int get_partition_info_aml_by_name(struct blk_desc *dev_desc, ++ const char *name, struct disk_partition *info) ++{ ++ return (get_part_info_by_name(dev_desc, ++ name, info)); ++} ++ ++void print_part_aml(struct blk_desc * dev_desc) ++{ ++ struct disk_partition info; ++ int i; ++ if (_get_partition_info_aml(dev_desc,0,&info,0) == -1) { ++ printf("** No boot partition found on device %d **\n",dev_desc->devnum); ++ return; ++ } ++ printf("Part Start Sect x Size Type name\n"); ++ i=0; ++ do { ++ printf(" %02d " LBAFU " " LBAFU " %6ld %.32s %.32s\n", ++ i++, info.start, info.size, info.blksz, info.type, info.name); ++ } while (_get_partition_info_aml(dev_desc,i,&info,0)!=-1); ++} ++#define AML_MPT_OFFSET (73728) /* 36M */ ++/* fix 40Mbyte to check the MPT magic */ ++int test_part_aml (struct blk_desc *dev_desc) ++{ ++ ALLOC_CACHE_ALIGN_BUFFER(char, buffer, dev_desc->blksz); ++ if (blk_dread(dev_desc, AML_MPT_OFFSET, 1, (ulong *) buffer) != 1) ++ return -1; ++ if (!strncmp(buffer, "MPT", 3)) ++ return 1; // FIXME: return negative result for AML partition for normal u-boot bootsequence ++ return 1; ++} ++ ++ ++U_BOOT_PART_TYPE(aml) = { ++ .name = "AML", ++ .part_type = PART_TYPE_AML, ++ .max_entries = AML_ENTRY_NUMBERS, ++ .get_info = get_partition_info_aml, ++ .print = print_part_aml, ++ .test = test_part_aml, ++}; ++ ++#endif +diff --git a/drivers/amlogic/Kconfig b/drivers/amlogic/Kconfig +new file mode 100644 +index 00000000000..ff94c4b85e2 +--- /dev/null ++++ b/drivers/amlogic/Kconfig +@@ -0,0 +1,14 @@ ++menu "AMLOGIC Drivers" ++ ++config AML_DRIVER ++ bool "AML drivers Support" ++ select SHA1 ++ select SHA256 ++ help ++ Enable support for the Amlogic drivers. ++ ++source "drivers/amlogic/keymanage/Kconfig" ++ ++source "drivers/amlogic/storagekey/Kconfig" ++ ++endmenu +diff --git a/drivers/amlogic/Makefile b/drivers/amlogic/Makefile +new file mode 100644 +index 00000000000..544cc608b58 +--- /dev/null ++++ b/drivers/amlogic/Makefile +@@ -0,0 +1,5 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++ ++obj-$(CONFIG_UNIFY_KEY_MANAGE) += keymanage/ ++ ++obj-$(CONFIG_SECURE_STORAGE) += storagekey/ +diff --git a/drivers/amlogic/keymanage/Kconfig b/drivers/amlogic/keymanage/Kconfig +new file mode 100644 +index 00000000000..0c77689ae4b +--- /dev/null ++++ b/drivers/amlogic/keymanage/Kconfig +@@ -0,0 +1,21 @@ ++menuconfig UNIFY_KEY_MANAGE ++ bool "Amlogic unifykey" ++ depends on OF_LIBFDT ++ help ++ This enables support for keyman (Amlogic key manage), ++ A driver providing APIs for flash key and efuse key ++if UNIFY_KEY_MANAGE ++ config AML_SECURITY_KEY ++ depends on SECURE_STORAGE ++ bool "Amlogic flash key" ++ default y ++ select SHA256 ++ select SHA1 ++ help ++ "security key wrapper for APIs bl31" ++ config KEYMAN_PROVISION_KEY ++ bool "Amlogic burn provision key" ++ default n ++ help ++ "provision key wrapper for burn tool" ++endif #if UNIFY_KEY_MANAGE +diff --git a/drivers/amlogic/keymanage/Makefile b/drivers/amlogic/keymanage/Makefile +new file mode 100644 +index 00000000000..08dd44eaec6 +--- /dev/null ++++ b/drivers/amlogic/keymanage/Makefile +@@ -0,0 +1,32 @@ ++# ++# (C) Copyright 2000-2007 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++obj-$(CONFIG_UNIFY_KEY_MANAGE) += aml_key_manage.o ++ ++aml_key_manage-y = key_unify.o ++aml_key_manage-y += key_manage.o ++aml_key_manage-$(CONFIG_OF_LIBFDT) += km_dts.o ++aml_key_manage-$(CONFIG_EFUSE) += km_efuse_key.o ++aml_key_manage-$(CONFIG_AML_SECURITY_KEY) += km_secure_key.o ++aml_key_manage-$(CONFIG_KEYMAN_PROVISION_KEY) += km_provision_key.o ++ +diff --git a/drivers/amlogic/keymanage/key_manage.c b/drivers/amlogic/keymanage/key_manage.c +new file mode 100644 +index 00000000000..f8e0700b0a1 +--- /dev/null ++++ b/drivers/amlogic/keymanage/key_manage.c +@@ -0,0 +1,689 @@ ++/* ++ * \file key_encrypt_decrypt.c ++ * \brief encrypt a key before burn to target deive, ++ * decrypt a key after read from target device ++ * ++ * \version 1.0.0 ++ * \date 15/07/17 ++ * \author Sam.Wu ++ * ++ * Copyright (c) 2015 Amlogic. All Rights Reserved. ++ * ++ */ ++#include "key_manage_i.h" ++#include ++#include ++#include ++#include ++#include ++ ++ ++#if defined(CONFIG_AML_SECURITY_KEY) ++extern int _burn_key_in_type_hdcp2(const char* keyname, ++ void* databuf, const unsigned bufLen, char* decryptBuf); ++extern int _read_key_in_type_hdcp2(const char* keyname, ++ void* databuf, const unsigned bufLen, char* decryptBuf); ++extern int _km_hdcp2_size(void); ++#else ++static int _burn_key_in_type_hdcp2(const char* keyname, ++ void* databuf, const unsigned bufLen, char* decryptBuf) ++{ ++ KM_ERR("CONFIG_AML_SECURITY_KEY undefined\n"); ++ return -__LINE__; ++} ++static int _read_key_in_type_hdcp2(const char* keyname, ++ void* databuf, const unsigned bufLen, char* decryptBuf) ++{ ++ KM_ERR("CONFIG_AML_SECURITY_KEY undefined\n"); ++ return -__LINE__; ++} ++int _km_hdcp2_size(void) ++{ ++ KM_ERR("CONFIG_AML_SECURITY_KEY undefined\n"); ++ return 0; ++} ++#endif// #if defined(CONFIG_AML_SECURITY_KEY) ++ ++enum _KmUsrKeyType{ ++ KM_USER_KEY_TYPE_MAC = 0 ,//key format is all ascii, and splitted by : ++ KM_USER_KEY_TYPE_SHA1 ,//key format is end with 20 bytes sha1sum ++ KM_USER_KEY_TYPE_HDCP2 ,//special case, can only identified with name ++ KM_USER_KEY_TYPE_RAW ,//raw format which can burn to target directly ++}; ++ ++static const char* _cfgKeyTypes[] = { ++ [KM_USER_KEY_TYPE_MAC] = "mac" , ++ [KM_USER_KEY_TYPE_SHA1] = "sha1" , ++ [KM_USER_KEY_TYPE_HDCP2] = "hdcp2" , ++ [KM_USER_KEY_TYPE_RAW] = "raw" , ++}; ++#define _SUPPORTED_CFG_TYPES_NUM ( sizeof(_cfgKeyTypes) / sizeof(char*) ) ++ ++ ++static int km_get_user_key_format(const char* srcKeyName, int* key_type) ++{ ++ int ret = 0; ++ int srcKeyType = 0; ++ const char* cfgType = NULL; ++ ++ cfgType = keymanage_dts_get_key_type (srcKeyName) ; ++ if (NULL == cfgType) { ++ KM_ERR("Fail in get keytype cfg in dts for key[%s]\n", srcKeyName); ++ return __LINE__; ++ } ++ ++ for (srcKeyType = 0; srcKeyType < _SUPPORTED_CFG_TYPES_NUM; ++srcKeyType) ++ { ++ ret = strcmp(cfgType, _cfgKeyTypes[srcKeyType]); ++ if (!ret) break; ++ } ++ if (srcKeyType == _SUPPORTED_CFG_TYPES_NUM) { ++ KM_ERR("prop key-type[%s] unsupported in key[%s]\n", cfgType, srcKeyName); ++ return __LINE__; ++ } ++ ++ if (KM_USER_KEY_TYPE_RAW == srcKeyType) ++ { ++ do ++ { ++ ret = !strcmp(srcKeyName, "mac") || !strcmp(srcKeyName, "mac_bt") || !strcmp(srcKeyName, "mac_wifi"); ++ if (ret) { srcKeyType = KM_USER_KEY_TYPE_MAC; break; } ++ ++ /*ret = !strcmp(srcKeyName, "hdcp") ;*/ ++ /*if (ret) { srcKeyType = KM_USER_KEY_TYPE_SHA1; break; }*/ ++ ++ ret = !strcmp(srcKeyName, "hdcp2") ; ++ if (ret) { srcKeyType = KM_USER_KEY_TYPE_HDCP2; break; } ++ ++ }while(0); ++ } ++ ++ *key_type = srcKeyType; ++ return 0; ++} ++ ++#if 1//START MAC ++const int _UsrMacKeyLen = 17; ++ ++//key manager user interface: mac format check and change format if needed ++static int _burn_key_in_type_mac(const char* keyname, const char* srcKeyVal, const unsigned srcKeyLen, void* decryptBuf) ++{ ++ int ret = 0; ++ int index = 0; ++ ssize_t targetKeyLen = 0; ++ char* dstKeyVal = (char*)decryptBuf; ++ ++ if (_UsrMacKeyLen != srcKeyLen) { ++ KM_ERR("mac len %d is invalid, must be %d\n", srcKeyLen, _UsrMacKeyLen); ++ return -EINVAL; ++ } ++ ++ for (index = 0; index < _UsrMacKeyLen; index += 3) ++ { ++ int k = 0; ++ const char* p = srcKeyVal + index; ++ for (k = 0; k < 2; ++k) { ++ const char c = *p++; ++ if (!isxdigit(c)) { ++ KM_ERR("mac str(%s) fmt err at index[%d]\n", srcKeyVal, index + k); ++ return __LINE__; ++ } ++ } ++ if (':' != *p && index + k < _UsrMacKeyLen) { ++ KM_ERR("mac str(%s) fmt err at index[%d], must be :, but %c\n", srcKeyVal, index + 2, *p); ++ return __LINE__; ++ } ++ } ++ ++ enum key_manager_dev_e keyDev = keymanage_dts_get_key_device(keyname); ++ if (KEY_M_MAX_DEV == keyDev) { ++ KM_ERR("Fail get key dev for key[%s]\n", keyname); ++ return __LINE__; ++ } ++ if (KEY_M_EFUSE_NORMAL != keyDev) { targetKeyLen = _UsrMacKeyLen; } ++ else ++ {//efusekey, check configure size ++ ret = key_unify_query_size(keyname, &targetKeyLen); ++ if (ret) { ++ KM_ERR("Fail at get key size, ret=%d\n", ret); ++ return __LINE__; ++ } ++ ++ if (6 != targetKeyLen && targetKeyLen != _UsrMacKeyLen) { ++ KM_ERR("efuse key[%s] len %zd err\n", keyname, targetKeyLen); ++ return __LINE__; ++ } ++ } ++ ++ if (_UsrMacKeyLen == targetKeyLen) {//say its target not efuse ? ++ ret = key_unify_write(keyname, srcKeyVal, srcKeyLen); ++ return ret; ++ } ++ ++ KM_DBG("targetKeyLen=%zd\n", targetKeyLen); ++ for (index = 0; index < targetKeyLen; ++index) { ++ char theByteStr[4] ; ++ theByteStr[0] = srcKeyVal[index * 3 + 0]; ++ theByteStr[1] = srcKeyVal[index * 3 + 1]; ++ theByteStr[2] = '\0'; ++ unsigned byteSum = 0; ++ ++ byteSum = simple_strtoul(theByteStr, NULL, 16); ++ KM_DBG("byteSum[%d]=0x%x\n", index, byteSum); ++ if (byteSum > 0xff) { ++ KM_ERR("theByteStr=%s err\n", theByteStr); ++ return __LINE__; ++ } ++ dstKeyVal[index] = byteSum; ++ } ++ ++ ret = key_unify_write(keyname, dstKeyVal, targetKeyLen); ++ return ret; ++} ++ ++//Return value: key size that user wanted, ok if > 0 ++static int _read_key_in_type_mac(const char* keyname, char* databuf, const unsigned bufLen, char* decryptBuf) ++{ ++ int ret = 0; ++ int index = 0; ++ ssize_t keyDevSz = 0; ++ ++ if (_UsrMacKeyLen > bufLen) { ++ KM_ERR("mac len %d is invalid, must be %d\n", bufLen, _UsrMacKeyLen); ++ return -__LINE__; ++ } ++ ++ ret = key_unify_query_size (keyname, &keyDevSz) ; ++ if (ret) { ++ KM_ERR("Fail in get key sz, ret=%d\n", ret); ++ return -__LINE__; ++ } ++ ++ ret = key_unify_read (keyname, decryptBuf, (unsigned)keyDevSz) ; ++ if (ret) { ++ KM_ERR("fail in read key[%s]\n", keyname); ++ return -__LINE__; ++ } ++ ++ if (_UsrMacKeyLen == keyDevSz) { ++ memcpy(databuf, decryptBuf, keyDevSz); ++ return 0; ++ } ++ ++ databuf[0] = '\0'; ++ for (index = 0; index < keyDevSz; ++index) ++ { ++ const unsigned byteSum = decryptBuf[index]; ++ ++ sprintf(databuf, "%s%02x:", databuf, byteSum); ++ } ++ ++ return ret; ++} ++#endif//END MAC ++ ++#if 1//Start sha1sum ++//key value which end up 20 bytes sha1sum ++//check the sha1sum and remove it after checked ok ++static int _burn_key_in_type_sha1(const char* keyname, void* databuf, const unsigned bufLen, char* decryptBuf) ++{ ++ int ret = 0; ++ const unsigned srcKeyLen = bufLen; ++ const char* srcKeyVal = (char*)databuf; ++ const unsigned shaSumLen = 20; ++ const unsigned licLen = srcKeyLen - shaSumLen; ++ const u8* orgSum = (u8*)srcKeyVal + licLen; ++ u8 genSum[shaSumLen]; ++ ++ if (srcKeyLen <= 20) { ++ KM_ERR("Err key len %d for sha1 fmt\n", srcKeyLen); ++ return __LINE__; ++ } ++ ++ sha1_csum((u8*)srcKeyVal, licLen, genSum); ++ ++ ret = memcmp(orgSum, genSum, shaSumLen); ++ if (ret) { ++ const unsigned fmtStrLen = shaSumLen * 2 + 2; ++ char org_sha1Str[fmtStrLen + 2]; ++ char gen_sha1Str[fmtStrLen + 2]; ++ int byteIndex = 0; ++ ++ org_sha1Str[0] = gen_sha1Str[0] = '\0'; ++ for (byteIndex = 0; byteIndex < shaSumLen; ++byteIndex) ++ { ++ sprintf(org_sha1Str, "%s%02x", org_sha1Str, orgSum[byteIndex]); ++ sprintf(gen_sha1Str, "%s%02x", gen_sha1Str, genSum[byteIndex]); ++ } ++ KM_ERR("sha1sum, orgSum[%s] != genSum[%s]\n", org_sha1Str, gen_sha1Str); ++ ++ return __LINE__; ++ } ++ KM_MSG("Verify key with sha1sum OK\n"); ++ ++ ret = key_unify_write(keyname, srcKeyVal, licLen); ++ return ret; ++} ++#endif//END sha1sum ++/* * ++ * APIs of key manage ++*/ ++ ++int key_manage_init(const char* seednum, const char* dtbaddr) ++{ ++ int ret = key_unify_init(seednum, dtbaddr); ++ ++ return ret; ++} ++ ++int key_manage_exit(void) ++{ ++ return key_unify_uninit(); ++} ++ ++int key_manage_write(const char* keyname, const void* keydata, const unsigned dataLen) ++{ ++ int ret = 0; ++ int srcKeyType; ++ char* decryptBuf = NULL; ++ const int DecryptBufMaxLen = 64<<10; ++ ++ ret = key_unify_query_key_has_configure(keyname); ++ if (!ret) { ++ KM_ERR ("There isn't cfg for key[%s]\n", keyname) ; ++ return __LINE__; ++ } ++ ++ ret = km_get_user_key_format(keyname, &srcKeyType); ++ if (ret) { ++ KM_ERR ("Fail in get user key type\n") ; ++ return __LINE__; ++ } ++ ++ decryptBuf = (char*)malloc(DecryptBufMaxLen); ++ switch (srcKeyType) ++ { ++ case KM_USER_KEY_TYPE_MAC: ++ { ++ ret = _burn_key_in_type_mac(keyname, (char*)keydata, dataLen, decryptBuf); ++ } ++ break; ++ ++ case KM_USER_KEY_TYPE_SHA1: ++ { ++ ret = _burn_key_in_type_sha1(keyname, (char*)keydata, dataLen, decryptBuf); ++ } ++ break; ++ ++ case KM_USER_KEY_TYPE_HDCP2: ++ { ++ ret = _burn_key_in_type_hdcp2(keyname, (char*)keydata, dataLen, decryptBuf); ++ } ++ break; ++ ++ case KM_USER_KEY_TYPE_RAW: ++ { ++ ret = key_unify_write(keyname, (char*)keydata, dataLen); ++ } ++ break; ++ } ++ ++ free(decryptBuf); ++ return ret; ++} ++ ++int key_manage_read(const char* keyname, void* keydata, const unsigned bufLen) ++{ ++ int ret = 0; ++ ssize_t keysize = 0; ++ int srcKeyType = 0; ++ char* decryptBuf = NULL; ++ const int DecryptBufMaxLen = 64<<10; ++ ++ ret = key_manage_query_size(keyname, &keysize); ++ if (ret) { ++ KM_ERR ("Fail in query key size for key[%s]\n", keyname) ; ++ return __LINE__; ++ } ++ if (keysize > bufLen) { ++ KM_ERR ("keysize %zd > bufLen %d\n", keysize, bufLen) ; ++ return __LINE__; ++ } ++ ++ ret = km_get_user_key_format(keyname, &srcKeyType); ++ if (ret) { ++ KM_ERR ("Fail in get user key type\n") ; ++ return __LINE__; ++ } ++ ++ decryptBuf = (char*)malloc(DecryptBufMaxLen); ++ switch (srcKeyType) ++ { ++ case KM_USER_KEY_TYPE_MAC: ++ { ++ ret = _read_key_in_type_mac(keyname, (char*)keydata, (unsigned)keysize, decryptBuf); ++ } ++ break; ++ ++ case KM_USER_KEY_TYPE_HDCP2: ++ { ++ ret = _read_key_in_type_hdcp2(keyname, keydata, (unsigned)keysize, decryptBuf); ++ } ++ break; ++ ++ case KM_USER_KEY_TYPE_SHA1: ++ case KM_USER_KEY_TYPE_RAW: ++ default: ++ { ++ ret = key_unify_read(keyname, keydata, (unsigned)keysize); ++ } ++ break; ++ } ++ ++ free(decryptBuf); ++ return ret; ++} ++ ++int key_manage_query_size(const char* keyname, ssize_t* keysize) ++{ ++ int ret = 0; ++ int exist = 0; ++ int srcKeyType = 0; ++ ++ ret = key_manage_query_exist(keyname, &exist); ++ if (ret) { ++ KM_ERR ("Fail in query key exist\n") ; ++ return __LINE__; ++ } ++ if (!exist) { ++ KM_ERR ("key[%s] not programed yet\n", keyname) ; ++ return __LINE__; ++ } ++ ++ ret = km_get_user_key_format(keyname, &srcKeyType); ++ if (ret) { ++ KM_ERR ("Fail in get user key type\n") ; ++ return __LINE__; ++ } ++ ++ switch (srcKeyType) ++ { ++ case KM_USER_KEY_TYPE_MAC: ++ { ++ *keysize = _UsrMacKeyLen; ++ } ++ break; ++ ++ case KM_USER_KEY_TYPE_HDCP2: ++ { ++ *keysize = _km_hdcp2_size(); ++ } ++ break; ++ ++ case KM_USER_KEY_TYPE_RAW: ++ case KM_USER_KEY_TYPE_SHA1: ++ default: ++ ret = key_unify_query_size(keyname, keysize); ++ } ++ ++ return ret; ++} ++ ++int key_manage_query_exist(const char* keyname, int* exist) ++{ ++ int ret = 0; ++ ++ ret = key_unify_query_key_has_configure(keyname); ++ if (!ret) { ++ KM_ERR ("There isn't dts cfg for key[%s]\n", keyname) ; ++ return __LINE__; ++ } ++ ++ ret = key_unify_query_exist(keyname, exist); ++ ++ return ret; ++} ++ ++int key_manage_query_secure(const char* keyname, int* isSecure) ++{ ++ int ret = 0; ++ int exist = 0; ++ ++ ret = key_manage_query_exist(keyname, &exist); ++ if (ret) { ++ KM_ERR ("Fail in query key exist, ret=%d\n", ret) ; ++ return __LINE__; ++ } ++ if (!exist) { ++ KM_ERR ("Key[%s] not programed yet\n", keyname) ; ++ return __LINE__; ++ } ++ ++ ret = key_unify_query_secure(keyname, isSecure); ++ ++ return ret; ++} ++ ++int key_manage_query_canOverWrite(const char* keyname, int* canOverWrite) ++{ ++ return key_unify_query_canOverWrite(keyname, canOverWrite); ++} ++ ++static int do_keyman_init(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ int ret = 0; ++ const char* seedNum = argv[1]; ++ const char* dtbAddr = argc > 2 ? argv[2] : NULL; ++ ++ if (argc < 2) return CMD_RET_USAGE; ++ ++ ret = key_manage_init(seedNum, dtbAddr); ++ return ret; ++} ++ ++static int do_keyman_exit(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ return key_manage_exit(); ++} ++ ++//read keyname addr ++//fmt can be hex/str, if str, env keyname will be setted ++static int do_keyman_read(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ int ret = 0; ++ const char* keyname = argv[1]; ++ char* dataBuf = NULL; ++ const char* dataFmt = argc > 3 ? argv[3] : NULL; ++ ssize_t keyLen = 0; ++ if (argc < 3) return CMD_RET_USAGE; ++ ++ dataBuf = (char*)simple_strtoul(argv[2], NULL, 16); ++ if (!dataBuf) { ++ KM_ERR("Fail in parse argv[2] to dataBuf\n"); ++ return __LINE__; ++ } ++ ++ ret = key_manage_query_size(keyname, &keyLen); ++ if (ret) { ++ KM_DBG("Fail get sz for[%s]\n", keyname);//here occure in booting if key not burned yet! ++ return __LINE__; ++ } ++ ret = key_manage_read(keyname, dataBuf, keyLen); ++ if (ret) { ++ KM_ERR("Fail in read key[%s] at sz %zd\n", keyname, keyLen); ++ return __LINE__; ++ } ++ if (dataFmt) ++ { ++ if (!strcmp("hex", dataFmt)) ++ { ++ _keyman_buf_to_hex_ascii((uint8_t*)dataBuf, keyLen, NULL); ++ return 0; ++ } ++ else if(!strcmp("str", dataFmt)) ++ { ++ int i = 0; ++ ++ dataBuf[keyLen] = '\0'; ++ for (; i < keyLen; ++i) { ++ ret = isascii(dataBuf[i]); ++ if (!ret) { ++ KM_MSG("key value has non ascii, can't pr\n"); ++ return CMD_RET_FAILURE; ++ } ++ } ++ env_set(keyname, dataBuf);//setenv for bootargs ++ KM_DBG("env:%s=%s\n", keyname, dataBuf); ++ return 0; ++ } ++ else KM_MSG("Err key dataFmt(%s)\n", dataFmt); ++ } ++ ++ return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS; ++} ++ ++//argv: 1 2 3 ++//write keyname size addr ++//write keyname hex/str value ++static int do_keyman_write(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ int ret = 0; ++ const char* keyname = argv[1]; ++ const char* databuf = NULL; ++ char* tmpBuf = NULL; ++ const char* inputFmt = argv[2]; ++ unsigned dataLen = 0; ++ if (argc < 4) return CMD_RET_USAGE; ++ ++ if (!strcmp("hex", inputFmt)) ++ { ++ databuf = argv[3]; ++ dataLen = strlen(databuf) / 2; ++ ++ tmpBuf = (char*)malloc(dataLen); ++ ret = _keyman_hex_ascii_to_buf(databuf, tmpBuf, dataLen); ++ if (ret) { ++ KM_ERR("Fail in change hex argv[3] to bin, err=%d\n", ret); ++ free(tmpBuf); ++ return CMD_RET_FAILURE; ++ } ++ databuf = tmpBuf; ++ } ++ else if(!strcmp("str", inputFmt)) ++ { ++ databuf = argv[3]; ++ dataLen = strlen(databuf); ++ ++ const char* p = databuf; ++ for (; *p; ++p) { ++ if (!isascii(*p)) { ++ KM_ERR("inputFmt is %s, but argv[3] contain non ascii\n", inputFmt); ++ return CMD_RET_FAILURE; ++ } ++ } ++ KM_DBG("str:%s, len=%d\n", databuf, dataLen); ++ } ++ else ++ { ++ dataLen = simple_strtoul(argv[2], NULL, 0); ++ if (!dataLen) { ++ KM_ERR("dataLen err\n"); ++ return __LINE__; ++ } ++ if (dataLen > (64*1024)) { ++ KM_ERR("keylen 0x%x too large!\n", dataLen); ++ return __LINE__; ++ } ++ databuf = (char*)simple_strtoul(argv[3], NULL, 16); ++ } ++ ++ ret = key_manage_write(keyname, databuf, dataLen); ++ if (tmpBuf) free(tmpBuf) ; ++ return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS; ++} ++ ++//query: 1 2 ++// exist keyname ++// secure keyname ++// size keyname ++static int do_keyman_query(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ int ret = 0; ++ const char* cmd = argv[1]; ++ const char* keyname = argv[2]; ++ if (argc < 3) return CMD_RET_USAGE; ++ ++ if (!strcmp("exist", cmd)) ++ { ++ int exist = 0; ++ ret = key_manage_query_exist(keyname, &exist); ++ if (ret) { ++ KM_ERR("Fail in query key exist, err=%d", ret); ++ return CMD_RET_FAILURE; ++ } ++ KM_MSG("key[%s] is %s Exist\n", keyname, exist ? "" : "NOT"); ++ ret = exist ? CMD_RET_SUCCESS : CMD_RET_FAILURE; ++ } ++ else if(!strcmp("secure", cmd)) ++ { ++ int isSecure = 0; ++ ret = key_manage_query_secure(keyname, &isSecure); ++ if (ret) { ++ KM_ERR("Fail in query key secure, err=%d\n", ret); ++ return CMD_RET_FAILURE; ++ } ++ KM_MSG("key[%s] is %s Secure\n", keyname, isSecure ? "" : "NOT"); ++ ret = isSecure ? CMD_RET_SUCCESS : CMD_RET_FAILURE; ++ } ++ else if(!strcmp("size", cmd)) ++ { ++ ssize_t keysize = 0; ++ ret = key_manage_query_size(keyname, &keysize); ++ if (ret) { ++ KM_ERR("Fail in query key size, err=%d\n", ret); ++ return CMD_RET_FAILURE; ++ } ++ KM_MSG("key[%s] size is %zd\n", keyname, keysize); ++ ret = keysize ? CMD_RET_SUCCESS : CMD_RET_FAILURE; ++ } ++ else return CMD_RET_USAGE; ++ ++ return ret; ++} ++ ++static struct cmd_tbl cmd_keyman_sub[] = { ++ U_BOOT_CMD_MKENT(init, 3, 0, do_keyman_init, "", ""), ++ U_BOOT_CMD_MKENT(exit, 2, 0, do_keyman_exit, "", ""), ++ U_BOOT_CMD_MKENT(read, 4, 0, do_keyman_read, "", ""), ++ U_BOOT_CMD_MKENT(write, 4, 0, do_keyman_write, "", ""), ++ U_BOOT_CMD_MKENT(query, 3, 0, do_keyman_query, "", ""), ++}; ++ ++static int do_keymanage(struct cmd_tbl * cmdtp, int flag, int argc, char * const argv[]) ++{ ++ struct cmd_tbl *c; ++ ++ if (argc < 2) return CMD_RET_USAGE; ++ ++ c = find_cmd_tbl(argv[1], cmd_keyman_sub, ARRAY_SIZE(cmd_keyman_sub)); ++ ++ if (!c) { return CMD_RET_USAGE;} ++ ++ return c->cmd(cmdtp, flag, --argc, ++argv); ++} ++ ++U_BOOT_CMD( ++ keyman, //command name ++ 5, //maxargs ++ 0, //repeatable ++ do_keymanage, //command function ++ "Unify key ops interfaces based dts cfg", //description ++ " argv: \n" //usage ++ " init seedNum \n" ++ " read keyname addr \n" ++ " write keyname size addr \n" ++ " write keyname hex/str value\n" ++ " query exist/secure/size keyname\n" ++ " exit \n" ++); ++ +diff --git a/drivers/amlogic/keymanage/key_manage.h b/drivers/amlogic/keymanage/key_manage.h +new file mode 100644 +index 00000000000..ab482f45a05 +--- /dev/null ++++ b/drivers/amlogic/keymanage/key_manage.h +@@ -0,0 +1,61 @@ ++#ifndef __KEY_MANAGE_H__ ++#define __KEY_MANAGE_H__ ++ ++enum key_manager_dev_e{ ++ KEY_M_UNKNOW_DEV=0, ++ KEY_M_EFUSE_NORMAL, ++ KEY_M_SECURE_KEY, //secure nandkey/emmckey ++ KEY_M_NORAML_KEY, //non-secure nandkey/emmckey ++ KEY_M_PROVISION_KEY, //provision key ++ KEY_M_MAX_DEV, ++}; ++ ++/*key data format*/ ++enum key_manager_df_e{ ++ KEY_M_HEXDATA=0, ++ KEY_M_HEXASCII, ++ KEY_M_ALLASCII, ++ KEY_M_MAX_DF, ++}; ++ ++enum key_manager_permit_e{ ++ KEY_M_PERMIT_READ = (1<<0), ++ KEY_M_PERMIT_WRITE = (1<<1), ++ KEY_M_PERMIT_DEL = (1<<2), ++ KEY_M_PERMIT_MASK = 0Xf, ++}; ++ ++enum key_manager_type_e{ ++ KEY_M_TYPE_NORMAL = 0 , ++ KEY_M_TYPE_MAC , ++ KEY_M_TYPE_SHA1 , ++ KEY_M_TYPE_HDCP2 , ++ ++ KEY_M_TYPE_TOTAL_NUM ++}; ++ ++#define KEY_UNIFY_NAME_LEN 48 ++#define KEY_UNIFY_TYPE_LEN_MAX ( 16 - 1 ) ++ ++struct key_item_t{ ++ char name[KEY_UNIFY_NAME_LEN]; ++ char keyType[KEY_UNIFY_TYPE_LEN_MAX + 1];//mac/sha1/hdcp2/normal ++ char encType[KEY_UNIFY_TYPE_LEN_MAX + 1];//mac/sha1/hdcp2/normal ++ int id; ++ unsigned int dev; //key save in device //efuse, ++ unsigned int datFmt; //data format ++ unsigned int permit; ++ int flag; ++ int reserv;//reserve and align to 64 ++}; ++ ++struct key_info_t{ ++ int key_num; ++ int efuse_version; ++ int key_flag; ++ int encrypt_type; ++}; ++ ++ ++#endif // #ifndef __KEY_MANAGE_H__ ++ +diff --git a/drivers/amlogic/keymanage/key_manage_i.h b/drivers/amlogic/keymanage/key_manage_i.h +new file mode 100644 +index 00000000000..73404c1dbf1 +--- /dev/null ++++ b/drivers/amlogic/keymanage/key_manage_i.h +@@ -0,0 +1,65 @@ ++/* ++ * \file key_manage_i.h ++ * \brief common included files for key manager ++ * ++ * \version 1.0.0 ++ * \date 15/06/30 ++ * \author Sam.Wu ++ * ++ * Copyright (c) 2015 Amlogic. All Rights Reserved. ++ * ++ */ ++#ifndef __KEY_MANAGE_I_H__ ++#define __KEY_MANAGE_I_H__ ++ ++#include ++#include ++#include ++#include ++#include ++#include "key_manage.h" ++#include ++#include ++ ++#define KM_DBG(fmt ...) //printf("[KM]Dbg:"fmt) ++#define KM_MSG(fmt ...) printf("[KM]Msg:"fmt) ++#define KM_ERR(fmt ...) printf("[KM]Error:f[%s]L%d:", __func__, __LINE__),printf(fmt) ++ ++int _keyman_hex_ascii_to_buf(const char* input, char* buf, const unsigned bufSz); ++int _keyman_buf_to_hex_ascii(const uint8_t* pdata, const unsigned dataLen, char* fmtStr/*pr if NULL*/); ++ ++int keymanage_dts_parse(const void* dt_addr); ++enum key_manager_df_e keymanage_dts_get_key_fmt(const char *keyname); ++enum key_manager_dev_e keymanage_dts_get_key_device(const char *keyname); ++const char* keymanage_dts_get_key_type(const char* keyname); ++const char* keymanage_dts_get_enc_type(const char* keyname); ++char unifykey_get_efuse_version(void); ++int unifykey_get_encrypt_type(void); ++ ++int keymanage_efuse_init(const char *buf, int len); ++int keymange_efuse_exit(void); ++int keymanage_efuse_write(const char *keyname, const void* keydata, unsigned int datalen); ++int keymanage_efuse_exist(const char* keyname); ++ssize_t keymanage_efuse_size(const char* keyname); ++int keymanage_efuse_query_can_read(const char* keyname); ++int keymanage_efuse_read(const char *keyname, void* databuf, const unsigned bufsz); ++ ++int keymanage_securekey_init(const char* buf, int len); ++int keymanage_securekey_exit(void); ++int keymanage_secukey_write(const char *keyname, const void* keydata, unsigned int datalen); ++ssize_t keymanage_secukey_size(const char* keyname); ++int keymanage_secukey_exist(const char* keyname); ++int keymanage_secukey_can_read(const char* keyname); ++int keymanage_secukey_read(const char* keyname, void* databuf, unsigned buflen); ++ ++//provision key ops ++int keymanage_provision_init(const char *buf, int len); ++int keymanage_provision_exit(void); ++int keymanage_provision_write(const char *keyname, const void* keydata, unsigned int datalen); ++ssize_t keymanage_provision_size(const char* keyname); ++int keymanage_provision_exist(const char* keyname); ++int keymanage_provision_query_can_read(const char* keyname); ++int keymanage_provision_read(const char *keyname, void* databuf, const unsigned bufSz); ++ ++#endif//#ifndef __KEY_MANAGE_I_H__ ++ +diff --git a/drivers/amlogic/keymanage/key_unify.c b/drivers/amlogic/keymanage/key_unify.c +new file mode 100644 +index 00000000000..069fff08dd2 +--- /dev/null ++++ b/drivers/amlogic/keymanage/key_unify.c +@@ -0,0 +1,610 @@ ++/* ++ * Unify interfaces for read/write nandkey/emmckey/efuse key ++ */ ++#include "key_manage_i.h" ++#include ++#include ++#include ++#include ++ ++#define KEY_NO_EXIST 0 ++#define KEY_BURNED 1 ++ ++#define KEY_READ_PERMIT 10 ++#define KEY_READ_PROHIBIT 11 ++ ++#define KEY_WRITE_MASK (0x0f<<4) ++#define KEY_WRITE_PERMIT (10<<4) ++#define KEY_WRITE_PROHIBIT (11<<4) ++ ++typedef struct _devKeyOps{ ++ int (*pInitFunc) (const char* buf, int len); ++ int (*pUninitFunc)(void); ++ int (*pWriteFunc)(const char *keyname, const void* keydata, unsigned int datalen); ++ ssize_t (*pGetSize)(const char* keyname); ++ int (*pKeyExist)(const char* keyname); ++ int (*pKeyCanRead)(const char* keyname); ++ int (*pReadFunc)(const char* keyname, void* dataBuf, unsigned buflen); ++ ++ //Fields: ++ int can_overwrite;//is OTP ++ ++}KmDevKeyOps; ++ ++static KmDevKeyOps _SecukeyOps = { ++ .pInitFunc = keymanage_securekey_init , ++ .pUninitFunc = keymanage_securekey_exit , ++ .pWriteFunc = keymanage_secukey_write , ++ .pGetSize = keymanage_secukey_size , ++ .pKeyExist = keymanage_secukey_exist , ++ .pKeyCanRead = keymanage_secukey_can_read , ++ .pReadFunc = keymanage_secukey_read , ++ ++ .can_overwrite = 1 , ++}; ++ ++#if defined(CONFIG_EFUSE) ++static KmDevKeyOps _efuseKeyOps = { ++ .pInitFunc = keymanage_efuse_init , ++ .pUninitFunc = keymange_efuse_exit , ++ .pWriteFunc = keymanage_efuse_write , ++ .pGetSize = keymanage_efuse_size , ++ .pKeyExist = keymanage_efuse_exist , ++ .pKeyCanRead = keymanage_efuse_query_can_read , ++ .pReadFunc = keymanage_efuse_read , ++ ++ .can_overwrite = 0 , ++}; ++#endif//#if defined(CONFIG_EFUSE) ++ ++#if defined(CONFIG_KEYMAN_PROVISION_KEY) ++static KmDevKeyOps _provisionKeyOps = { ++ .pInitFunc = keymanage_provision_init , ++ .pUninitFunc = keymanage_provision_exit , ++ .pWriteFunc = keymanage_provision_write , ++ .pGetSize = keymanage_provision_size , ++ .pKeyExist = keymanage_provision_exist , ++ .pKeyCanRead = keymanage_provision_query_can_read , ++ .pReadFunc = keymanage_provision_read , ++ ++ .can_overwrite = 1 , ++}; ++#endif//#if defined(CONFIG_KEYMAN_PROVISION_KEY) ++ ++#define _KM_DEV_INDEX_SECUREKEY 0 ++#define _KM_DEV_INDEX_PROVISION 1 ++#if defined(CONFIG_KEYMAN_PROVISION_KEY) ++#define _KM_DEV_INDEX_EFUSE 2 ++#else ++#define _KM_DEV_INDEX_EFUSE 1 ++#endif//#if defined(CONFIG_KEYMAN_PROVISION_KEY) ++ ++static KmDevKeyOps* _km_devKeyOpsArr[] = { ++ [_KM_DEV_INDEX_SECUREKEY] = &_SecukeyOps, ++#if defined(CONFIG_KEYMAN_PROVISION_KEY) ++ [_KM_DEV_INDEX_PROVISION] = &_provisionKeyOps, ++#endif//#if defined(CONFIG_KEYMAN_PROVISION_KEY) ++#if defined(CONFIG_EFUSE) ++ [_KM_DEV_INDEX_EFUSE] = &_efuseKeyOps, ++#endif//#if defined(CONFIG_EFUSE) ++}; ++ ++static const int _KM_DEVCNT = sizeof(_km_devKeyOpsArr) / sizeof(_km_devKeyOpsArr[0]); ++ ++int _keyman_hex_ascii_to_buf(const char* input, char* buf, const unsigned bufSz) ++{ ++ int ret = 0; ++ const char* tmpStr = input; ++ const unsigned inputLen = strlen(input); ++ int i = 0; ++ ++ if (!inputLen) { ++ KM_ERR("err input len 0\n"); ++ return __LINE__; ++ } ++ if (inputLen & 1) { ++ KM_ERR("inputLen %d not even\n", inputLen); ++ return __LINE__; ++ } ++ if (bufSz * 2 > inputLen) { ++ KM_ERR("bufSz %d not enough\n", bufSz); ++ return __LINE__; ++ } ++ for (tmpStr = input; *tmpStr; ++tmpStr) ++ { ++ char c = *tmpStr; ++ ret = isxdigit(c); ++ if (!ret) { ++ KM_ERR("input(%s) contain non xdigit, c=%c\n", input, c); ++ return __LINE__; ++ } ++ } ++ ++ for (i = 0; i < inputLen; i += 2) ++ { ++ char tmpByte[8]; ++ tmpByte[2] = '\0'; ++ tmpByte[0] = input[i]; ++ tmpByte[1] = input[i + 1]; ++ ++ const unsigned val = simple_strtoul(tmpByte, NULL, 16); ++ if (val > 0xff) { ++ KM_ERR("Exception: val 0x%x > 0xff\n", val); ++ return __LINE__; ++ } ++ buf[i>>1] = val; ++ } ++ ++ return 0; ++} ++ ++int _keyman_buf_to_hex_ascii(const uint8_t* pdata, const unsigned dataLen, char* fmtStr/*pr if NULL*/) ++{ ++ if (NULL == fmtStr) //Only print ++ { ++ int i = 0; ++ KM_MSG("key len is %d, hex value in hexdump:", dataLen); ++ for (; i < dataLen; ++i, ++pdata) ++ { ++ if (!(i & 0xf)) printf("\n\t[0x%04x]:\t\t", i); ++ printf("%02x ", *pdata); ++ } ++ printf("\n"); ++ } ++ else ++ { ++ int i = 0; ++ ++ *fmtStr = '\0'; ++ for (; i < dataLen; ++i, ++pdata) ++ { ++ sprintf(fmtStr, "%s%02x", fmtStr, *pdata); ++ } ++ } ++ ++ return 0; ++} ++ ++/* ++ * function name: key_unify_init ++ * buf : input ++ * len : > 0 ++ * return : >=0: ok, other: fail ++ * */ ++int key_unify_init(const char* seedStr, const char* dtbLoadaddr) ++{ ++ int err=EINVAL; ++ int i; ++ uint64_t seedNum = 0; ++ ++ if (!dtbLoadaddr) ++ { ++ dtbLoadaddr = (char*) env_get_ulong("fdtcontroladdr", 16, CFG_SYS_SDRAM_BASE + (16U<<20)); ++ } ++ ++ if (keymanage_dts_parse(dtbLoadaddr)) { ++ KM_DBG("Fail parse /unifykey at addr[0x%p]\n", dtbLoadaddr); ++ return err; ++ } ++ ++ seedNum = simple_strtoull(seedStr, NULL, 0); ++ if (!seedNum) { ++ KM_ERR("Seed is 0 err\n"); ++ return __LINE__; ++ } ++ ++ if (amlkey_if_init(dtbLoadaddr)) { ++ KM_ERR("amlkey interface init fail\n"); ++ return __LINE__; ++ } ++ ++ for (i=0; i < _KM_DEVCNT; i++) ++ { ++ KmDevKeyOps* theDevOps = _km_devKeyOpsArr[i]; ++ err = theDevOps->pInitFunc((char*)&seedNum, sizeof(uint64_t)/sizeof(char)); ++ if (err) { ++ KM_ERR("Device[%d] init failed, err=%d\n", i, err); ++ return err; ++ } ++ } ++ ++ return 0; ++} ++ ++/* function name: key_unify_uninit ++ * functiion : uninit ++ * return : >=0 ok, <0 fail ++ * */ ++int key_unify_uninit(void) ++{ ++ int err=-EINVAL; ++ int i; ++ ++ for (i=0; i < _KM_DEVCNT; i++) ++ { ++ KmDevKeyOps* theDevOps = _km_devKeyOpsArr[i]; ++ err = theDevOps->pUninitFunc(); ++ if (err) { ++ KM_ERR("device[%d] unini fail\n", i); ++ /*return err;*/ ++ } ++ } ++ ++ return 0; ++} ++ ++static const KmDevKeyOps* _get_km_ops_by_name(const char* keyname) ++{ ++ KmDevKeyOps* theDevOps = NULL; ++ ++ //step 1: get device ops by configured key-device ++ enum key_manager_dev_e theDevice = keymanage_dts_get_key_device(keyname); ++ ++ switch (theDevice) ++ { ++ case KEY_M_EFUSE_NORMAL: ++ { ++ theDevOps = _km_devKeyOpsArr[_KM_DEV_INDEX_EFUSE]; ++ } ++ break; ++ ++ case KEY_M_NORAML_KEY: ++ case KEY_M_SECURE_KEY: ++ { ++ theDevOps = _km_devKeyOpsArr[_KM_DEV_INDEX_SECUREKEY]; ++ } ++ break; ++ ++ case KEY_M_PROVISION_KEY: ++ theDevOps = _km_devKeyOpsArr[_KM_DEV_INDEX_PROVISION]; ++ break; ++ ++ case KEY_M_UNKNOW_DEV: ++ default: ++ KM_ERR("key %s not know device %d\n", keyname, theDevice); ++ return NULL; ++ } ++ ++ return theDevOps; ++} ++ ++int key_unify_query_key_has_configure(const char* keyname) ++{ ++ return _get_km_ops_by_name(keyname) ? 1 : 0; ++} ++ ++/* funtion name: key_unify_write ++ * keyname : key name is ascii string ++ * keydata : key data buf ++ * datalen : key buf len ++ * return 0: ok, -0x1fe: no space, other fail ++ * ++ * Step 1: Get burn target from dtb ++ * Step 2: check whether can burned, OTP can't burned twice ++ * 2.1)check is programmed yet, burn directly if not programmed yet. ++ * 2.2)if programmed yet, check if OTP ++ * Step 3: burn the key to the target ++ * */ ++int key_unify_write(const char *keyname, const void* keydata, const unsigned datalen) ++{ ++ int err=0; ++ const KmDevKeyOps* theDevOps = NULL; ++ ++ theDevOps = _get_km_ops_by_name(keyname); ++ if (!theDevOps) { ++ KM_ERR("key[%s] no cfg in dts\n", keyname); ++ return __LINE__; ++ } ++ ++ if (!theDevOps->can_overwrite) { ++ KM_DBG("can't overwrite\n"); ++ int ret = theDevOps->pKeyExist(keyname); ++ if (ret) { ++ KM_ERR("OTP key[%s] already existed, can't program twice!\n", keyname); ++ return __LINE__; ++ } ++ } ++ ++ err = theDevOps->pWriteFunc(keyname, keydata, datalen); ++ ++ return err; ++} ++ ++/* ++ *function name: key_unify_read ++ * keyname : key name is ascii string ++ * keydata : key data buf ++ * datalen : key buf len ++ * reallen : key real len ++ * return : <0 fail, >=0 ok ++ * */ ++int key_unify_read(const char *keyname, void* keydata, const unsigned bufLen) ++{ ++ int err=0; ++ const KmDevKeyOps* theDevOps = NULL; ++ ++ theDevOps = _get_km_ops_by_name(keyname); ++ if (!theDevOps) { ++ KM_ERR("key[%s] no cfg in dts\n", keyname); ++ return __LINE__; ++ } ++ ++ int ret = theDevOps->pKeyExist(keyname); ++ if (!ret) { ++ KM_ERR("key[%s] not programed yet\n", keyname); ++ return __LINE__; ++ } ++ ++ ret = theDevOps->pKeyCanRead(keyname); ++ if (!ret) { ++ KM_ERR("key[%s] can't read as it's secure\n", keyname); ++ return __LINE__; ++ } ++ ++ const ssize_t keySz = theDevOps->pGetSize(keyname); ++ if (keySz > bufLen && bufLen) { ++ KM_ERR("keySz[%lu] > bufLen[%d]\n", keySz, bufLen); ++ return __LINE__; ++ } ++ ++ err = theDevOps->pReadFunc(keyname, keydata, keySz); ++ ++ return err; ++} ++ ++int key_unify_query_size(const char* keyname, ssize_t* keysize) ++{ ++ const KmDevKeyOps* theDevOps = NULL; ++ ++ theDevOps = _get_km_ops_by_name(keyname); ++ if (!theDevOps) { ++ KM_ERR("key[%s] not cfg in dts\n", keyname); ++ return __LINE__; ++ } ++ ++#if 0 ++ int ret = theDevOps->pKeyCanRead(keyname); ++ if (!ret) { ++ KM_ERR("key[%s] can't read as it's secure\n", keyname); ++ return __LINE__; ++ } ++#endif ++ ++ *keysize = theDevOps->pGetSize(keyname); ++ ++ return 0; ++} ++ ++int key_unify_query_exist(const char* keyname, int* exist) ++{ ++ const KmDevKeyOps* theDevOps = NULL; ++ ++ theDevOps = _get_km_ops_by_name (keyname) ; ++ if (!theDevOps) { ++ KM_ERR("key[%s] not cfg in dts\n", keyname); ++ return __LINE__; ++ } ++ ++ *exist = theDevOps->pKeyExist(keyname); ++ ++ return 0; ++} ++ ++int key_unify_query_secure(const char* keyname, int* isSecure) ++{ ++ const KmDevKeyOps* theDevOps = NULL; ++ ++ theDevOps = _get_km_ops_by_name (keyname) ; ++ if (!theDevOps) { ++ KM_ERR("key[%s] no cfg in dts\n", keyname); ++ return __LINE__; ++ } ++ ++ int ret = theDevOps->pKeyExist (keyname) ; ++ if (!ret) { ++ KM_ERR("key[%s] not programed yet\n", keyname); ++ return __LINE__; ++ } ++ ++ *isSecure = !theDevOps->pKeyCanRead (keyname) ; ++ if (!ret) { ++ KM_ERR ("key[%s] can't read as it's secure\n", keyname) ; ++ return __LINE__; ++ } ++ ++ return 0; ++} ++ ++int key_unify_query_canOverWrite(const char* keyname, int* canOverWrite) ++{ ++ const KmDevKeyOps* theDevOps = NULL; ++ ++ theDevOps = _get_km_ops_by_name(keyname); ++ if (!theDevOps) { ++ KM_ERR("key[%s] no cfg in dts\n", keyname); ++ return __LINE__; ++ } ++ ++ *canOverWrite = theDevOps->can_overwrite; ++ return 0; ++} ++ ++int do_keyunify (struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ int err; ++ char *cmd; ++ int ret = 0; ++ ++ if (argc < 2) return CMD_RET_USAGE; ++ ++ cmd = argv[1]; ++ //keyman init seedNum ++ if (!strcmp(cmd,"init")) ++ { ++ if (argc < 3) { ++ return CMD_RET_USAGE; ++ } ++ const char* seedNum = argv[2]; ++ const char* dtbLoadaddr = argc > 3 ? argv[3] : NULL; ++ err = key_unify_init(seedNum, dtbLoadaddr); ++ return err ? CMD_RET_FAILURE : CMD_RET_SUCCESS; ++ } ++ ++ //keyunify write keyname addr ++ //keyunify write keyname hexascii ++ if (!strcmp(cmd,"write")) ++ { ++ if (argc < 4) return CMD_RET_USAGE; ++ ++ const char* keyname = argv[2]; ++ const char* keyData = (char*)simple_strtoul(argv[3], NULL, 16); ++ unsigned len = argc > 4 ? simple_strtoul(argv[4], NULL, 0) : 0; ++ char* dataBuf = NULL; ++ ++ if (argc == 4) ++ { ++ const char* hexascii = argv[3]; ++ ++ len = strlen(hexascii) / 2; ++ dataBuf = (char*)malloc(len); ++ if (!dataBuf) { ++ KM_ERR("Fail in malloc len %d\n", len); ++ return CMD_RET_FAILURE; ++ } ++ ++ err = _keyman_hex_ascii_to_buf(hexascii, dataBuf, len); ++ if (err) { ++ KM_ERR("Fail in decrypt hexascii to buf, err=%d\n", err); ++ free(dataBuf); ++ return CMD_RET_FAILURE; ++ } ++ keyData = dataBuf; ++ } ++ ++ KM_DBG("write key[%s], addr=%p, len=%d\n", keyname, keyData, len); ++ err = key_unify_write(keyname, keyData, len); ++ if (err ) { ++ KM_ERR("%s key write fail, err=%d\n", keyname, err); ++ return CMD_RET_FAILURE; ++ } ++ if (dataBuf)free(dataBuf) ; ++ ++ return CMD_RET_SUCCESS; ++ } ++ ++ //keyman query size/secure/exist keyname ++ if (!strcmp(cmd,"query")) ++ { ++ if (argc < 4) return CMD_RET_USAGE; ++ ++ const char* subCmd = argv[2]; ++ const char* keyname = argv[3]; ++ ++ ret = CMD_RET_FAILURE; ++ if (!strcmp("size", subCmd)) ++ { ++ ssize_t keysize = 0; ++ err = key_unify_query_size(keyname, &keysize); ++ if (!err) { ++ ret = CMD_RET_SUCCESS; ++ KM_MSG("key[%s] is %u bytes\n", keyname, (unsigned)keysize); ++ } ++ } ++ else if(!strcmp("secure", subCmd)) ++ { ++ int isSecure = 0; ++ ++ err = key_unify_query_secure(keyname, &isSecure); ++ if (!err) { ++ ret = CMD_RET_SUCCESS; ++ KM_MSG("key[%s] is %s Secure\n", keyname, isSecure ? "DO" : "NON"); ++ } ++ } ++ else if(!strcmp("exist", subCmd)) ++ { ++ int exist = 0; ++ err = key_unify_query_exist(keyname, &exist); ++ if (!err) { ++ ret = CMD_RET_SUCCESS; ++ KM_MSG("key[%s] is %s existed\n", keyname, exist ? "DO" : "NON"); ++ } ++ } ++ else{ ++ return CMD_RET_USAGE; ++ } ++ ++ return ret; ++ } ++ ++ //keyman read keyname memAddr ++ if (!strcmp(cmd,"read")) ++ { ++ if (argc < 4) return CMD_RET_USAGE; ++ ++ const char* keyname = argv[2]; ++ void* keydata = (void*)simple_strtoul(argv[3], NULL, 16); ++ ++ ssize_t keysize = 0; ++ err = key_unify_query_size(keyname, &keysize); ++ if (err) { ++ KM_ERR("Fail in get keysz, err=%d\n", err); ++ return __LINE__; ++ } ++ ++ err = key_unify_read(keyname, keydata, (unsigned)keysize); ++ if (err) { ++ KM_ERR("%s key read fail\n", keyname); ++ return CMD_RET_FAILURE; ++ } ++ _keyman_buf_to_hex_ascii(keydata, (unsigned)keysize, NULL); ++ ++ return err; ++ } ++ ++ if (!strcmp(cmd,"uninit")) ++ { ++ return key_unify_uninit(); ++ } ++ ++ return CMD_RET_USAGE; ++} ++ ++U_BOOT_CMD( ++ keyunify, CONFIG_SYS_MAXARGS, 1, do_keyunify, ++ "key unify sub-system", ++ "init seedNum [dtbAddr] --init the drivers\n" ++ "keyunify uninit - init key in device\n" ++ "keyunify write keyname data ---- wirte key data. len non-exist if data is ascii str\n" ++ "keyunify read keyname data-addr \n" ++); ++ ++ ++#if !defined(CONFIG_AML_SECURITY_KEY) ++int keymanage_securekey_init(const char* buf, int len) { return -EINVAL; } ++int keymanage_securekey_exit(void){ return -EINVAL; } ++int keymanage_secukey_write(const char *keyname, const void* keydata, unsigned int datalen){ return -EINVAL; } ++ssize_t keymanage_secukey_size(const char* keyname){ return 0; } ++int keymanage_secukey_exist(const char* keyname){ return 0; } ++int keymanage_secukey_can_read(const char* keyname){ return 0; } ++int keymanage_secukey_read(const char* keyname, void* dataBuf, unsigned buflen){ return -EINVAL; } ++#endif// #if CONFIG_AML_SECURITY_KEY ++ ++#if !defined(CONFIG_EFUSE) ++int keymanage_efuse_init(const char *buf, int len) { return -EINVAL; } ++int keymange_efuse_exit(void) {return -EINVAL;} ++int keymanage_efuse_write(const char *keyname, const void* keydata, unsigned int datalen) { return -EINVAL; } ++int keymanage_efuse_exist(const char* keyname) { return -EINVAL; } ++ssize_t keymanage_efuse_size(const char* keyname) { return 0; } ++int keymanage_efuse_read(const char *keyname, void* dataBuf, const unsigned bufsz) { return -EINVAL; } ++int keymanage_efuse_query_is_burned(const char* keyname) { return -EINVAL; } ++int keymanage_efuse_query_can_read(const char* keyname) { return -EINVAL; } ++#endif// #ifdef CONFIG_EFUSE ++ ++#if !defined(CONFIG_OF_LIBFDT) ++int keymanage_dts_parse(const void* dt_addr){ return -EINVAL; } ++enum key_manager_df_e keymanage_dts_get_key_fmt(const char *keyname){ return -EINVAL; } ++enum key_manager_dev_e keymanage_dts_get_key_device(const char *keyname){ return -EINVAL; } ++char unifykey_get_efuse_version(void) { return -1; } ++#endif//#ifdef CONFIG_OF_LIBFDT ++ ++ +diff --git a/drivers/amlogic/keymanage/km_dts.c b/drivers/amlogic/keymanage/km_dts.c +new file mode 100644 +index 00000000000..d2a2186147a +--- /dev/null ++++ b/drivers/amlogic/keymanage/km_dts.c +@@ -0,0 +1,392 @@ ++#include "key_manage_i.h" ++//#include ++#include ++ ++#define UNIFYKEY_DATAFORMAT_HEXDATA "hexdata" ++#define UNIFYKEY_DATAFORMAT_HEXASCII "hexascii" ++#define UNIFYKEY_DATAFORMAT_ALLASCII "allascii" ++ ++#define UNIFYKEY_DEVICE_EFUSEKEY "efuse" ++#define UNIFYKEY_DEVICE_NORMAL "normal" ++#define UNIFYKEY_DEVICE_SECURESKEY "secure" ++#define UNIFYKEY_DEVICE_PROVISIONKEY "provision" ++ ++#define UNIFYKEY_PERMIT_READ "read" ++#define UNIFYKEY_PERMIT_WRITE "write" ++#define UNIFYKEY_PERMIT_DEL "del" ++ ++static struct key_info_t unify_key_info={.key_num =0, .key_flag = 0, .efuse_version = -1, .encrypt_type = 0}; ++static struct key_item_t *unifykey_item=NULL; ++static struct key_item_t* _defProvisonItem =NULL;//keyname start with "KEY_PROVISION_" and device is "provison" ++#define _PROVSION_DEFAULT_KEY_NAME "KEY_PROVISION_XXX" ++ ++static int unifykey_item_verify_check(struct key_item_t *key_item) ++{ ++ if (!key_item) { ++ KM_ERR("unify key item is invalid\n"); ++ return -1; ++ } ++ ++ if (!key_item->name || (key_item->dev == KEY_M_UNKNOW_DEV) ||(key_item->datFmt == KEY_M_MAX_DF)) { ++ KM_ERR("unify key item is invalid\n"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++static struct key_item_t *unifykey_find_item_by_name(const char *name) ++{ ++ struct key_item_t *pre_item; ++ int i = 0; ++ const unsigned cnt = unify_key_info.key_num; ++ ++ for (pre_item = unifykey_item; i < cnt; ++pre_item, ++i) ++ { ++ if (!strcmp(pre_item->name,name)) { ++ return pre_item; ++ } ++ } ++ ++ if (!strncmp(_PROVSION_DEFAULT_KEY_NAME, name, strlen(_PROVSION_DEFAULT_KEY_NAME) - 3)) { ++ return _defProvisonItem; ++ } ++ return NULL; ++} ++ ++enum key_manager_df_e keymanage_dts_get_key_fmt(const char *keyname) ++{ ++ struct key_item_t *key_manage; ++ enum key_manager_df_e keyValFmt = KEY_M_MAX_DF; ++ ++ if (!unify_key_info.key_flag) { ++ KM_ERR("/unify not parsed yet!\n"); ++ return KEY_M_MAX_DF; ++ } ++ ++ key_manage = unifykey_find_item_by_name(keyname); ++ if (key_manage == NULL) { ++ KM_ERR ("%s key name is not exist\n", keyname) ; ++ return keyValFmt; ++ } ++ if (unifykey_item_verify_check(key_manage)) { ++ KM_ERR ("%s key name is invalid\n", keyname) ; ++ return keyValFmt; ++ } ++ ++ keyValFmt = key_manage->datFmt; ++ return keyValFmt; ++} ++ ++//which device does the key stored in ++enum key_manager_dev_e keymanage_dts_get_key_device(const char *keyname) ++{ ++ struct key_item_t *key_manage; ++ ++ if (!unify_key_info.key_flag) { ++ KM_ERR("/unify not parsed yet!\n"); ++ return KEY_M_MAX_DEV; ++ } ++ key_manage = unifykey_find_item_by_name(keyname); ++ if (key_manage == NULL) { ++ KM_ERR("%s key name is not exist\n",keyname); ++ return KEY_M_MAX_DEV; ++ } ++ if (unifykey_item_verify_check(key_manage)) { ++ KM_ERR("%s key name is invalid\n",keyname); ++ return KEY_M_MAX_DEV; ++ } ++ ++ return key_manage->dev; ++} ++ ++const char* keymanage_dts_get_enc_type(const char* keyname) ++{ ++ struct key_item_t *key_manage; ++ ++ if (!unify_key_info.key_flag) { ++ KM_ERR("/unify not parsed yet!\n"); ++ return NULL; ++ } ++ key_manage = unifykey_find_item_by_name(keyname); ++ if (key_manage == NULL) { ++ KM_ERR("%s key name is not exist\n",keyname); ++ return NULL; ++ } ++ ++ return key_manage->encType; ++} ++ ++const char* keymanage_dts_get_key_type(const char* keyname) ++{ ++ struct key_item_t *key_manage; ++ ++ if (!unify_key_info.key_flag) { ++ KM_ERR("/unify not parsed yet!\n"); ++ return NULL; ++ } ++ key_manage = unifykey_find_item_by_name(keyname); ++ if (key_manage == NULL) { ++ KM_ERR("%s key name is not exist\n",keyname); ++ return NULL; ++ } ++ ++ return key_manage->keyType; ++} ++ ++char unifykey_get_efuse_version(void) ++{ ++ char ver=0; ++ ++ if (!unify_key_info.key_flag) { ++ KM_ERR("/unify not parsed yet!\n"); ++ return 0; ++ } ++ ++ if (unify_key_info.efuse_version != -1) { ++ ver = (char)unify_key_info.efuse_version; ++ } ++ return ver; ++} ++ ++int unifykey_get_encrypt_type(void) ++{ ++ return unify_key_info.encrypt_type; ++} ++ ++static int unifykey_item_dt_parse(const void* dt_addr,int nodeoffset,int id,char *item_path) ++{ ++ struct key_item_t *temp_item=NULL; ++ char *propdata; ++ struct fdt_property *prop; ++ int count; ++ ++ temp_item = unifykey_item + id; ++ ++ propdata = (char*)fdt_getprop(dt_addr, nodeoffset, "key-encrypt", NULL); ++ if (propdata) { ++ count = strlen(propdata); ++ if ( count > KEY_UNIFY_TYPE_LEN_MAX ) { ++ KM_ERR("key-encrypt [%s] too long\n", propdata); ++ return __LINE__; ++ } ++ memcpy(temp_item->encType, propdata, count); ++ } ++ ++ propdata = (char*)fdt_getprop(dt_addr, nodeoffset, "key-name",NULL); ++ if (!propdata) { ++ printf("%s get key-name fail,%s:%d\n",item_path,__func__,__LINE__); ++ return __LINE__; ++ } ++ ++ count = strlen(propdata); ++ if (count >= KEY_UNIFY_NAME_LEN) { ++ KM_ERR("key-name strlen (%d) > max(%d) at key_%d\n", count, KEY_UNIFY_NAME_LEN - 1, id); ++ return __LINE__; ++ } ++ memcpy(temp_item->name, propdata, count); ++ temp_item->name[count] = 0; ++ ++ propdata = (char*)fdt_getprop(dt_addr, nodeoffset, "key-device",NULL); ++ if (!propdata) { ++ KM_ERR("%s get key-device fail at key_%d\n",item_path, id); ++ return __LINE__; ++ } ++ ++ if (strcmp(propdata,UNIFYKEY_DEVICE_EFUSEKEY) == 0) { ++ temp_item->dev = KEY_M_EFUSE_NORMAL; ++ } ++ else if(strcmp(propdata,UNIFYKEY_DEVICE_SECURESKEY) == 0){ ++ temp_item->dev = KEY_M_SECURE_KEY; ++ } ++ else if(strcmp(propdata,UNIFYKEY_DEVICE_NORMAL) == 0){ ++ temp_item->dev = KEY_M_NORAML_KEY; ++ } ++ else{ ++ KM_ERR("key-device %s is unknown at key_%d\n", propdata, id); ++ return __LINE__; ++ } ++ ++ propdata = (char*)fdt_getprop((const void *)dt_addr, nodeoffset, "key-type",NULL); ++ if (!propdata) //prop 'key-type' not configured, default to raw except special names ++ { ++ strcpy(temp_item->keyType, "raw"); ++ } ++ else ++ { ++ const int keyTypeLen = strlen(propdata); ++ if (keyTypeLen > KEY_UNIFY_TYPE_LEN_MAX) { ++ KM_ERR("key[%s]cfg key-type[%s] sz %d > max %d\n", temp_item->name, propdata, keyTypeLen, KEY_UNIFY_TYPE_LEN_MAX); ++ return __LINE__; ++ } ++ strcpy(temp_item->keyType, propdata); ++ } ++ ++ prop = (struct fdt_property*)fdt_get_property((const void *)dt_addr,nodeoffset,"key-permit",NULL) ; ++ if (!prop) { ++ KM_ERR("%s get key-permit fail at key_%d\n",item_path, id); ++ return __LINE__; ++ } ++ ++ temp_item->permit = 0; ++ const int propLen = prop->len > 512 ? strnlen(prop->data, 512) : prop->len; ++ if (fdt_stringlist_contains(prop->data, propLen, UNIFYKEY_PERMIT_READ)) { ++ temp_item->permit |= KEY_M_PERMIT_READ; ++ } ++ if (fdt_stringlist_contains(prop->data, propLen, UNIFYKEY_PERMIT_WRITE)) { ++ temp_item->permit |= KEY_M_PERMIT_WRITE; ++ } ++ if (fdt_stringlist_contains(prop->data, propLen, UNIFYKEY_PERMIT_DEL)) { ++ temp_item->permit |= KEY_M_PERMIT_DEL; ++ } ++ ++ temp_item->id = id; ++ ++ KM_DBG("key[%02d] keyname %s, %d\n", id, temp_item->name, temp_item->dev); ++ ++ return 0; ++} ++ ++static int unifykey_item_create(const void* dt_addr,int num) ++{ ++ int ret = 0; ++ int i,nodeoffset; ++ char item_path[100]; ++ ++ for (i=0;i= 0) { ++ fdt_for_each_subnode(child, dt_addr, provisionOffset) { ++ provisionNum++; ++ } ++ } ++ unify_key_info.key_num = unifykeyNum + provisionNum; ++ KM_MSG("key_num: %d\n", unify_key_info.key_num); ++ ++ unify_key_info.encrypt_type = -1; ++ encrypt_type = (char*)fdt_getprop((const void *)dt_addr, nodeoffset, "unifykey-encrypt",NULL); ++ if (encrypt_type) { ++ unify_key_info.encrypt_type = be32_to_cpup((unsigned int*)encrypt_type); ++ } ++ ++ if (unify_key_info.key_num <= 0) { ++ KM_ERR("unifykey-num is not configured\n"); ++ return __LINE__; ++ } ++ if (unify_key_info.key_num > 256) { ++ KM_ERR("Cfg key_num is %d > 32,pls check!\n", unify_key_info.key_num); ++ return __LINE__; ++ } ++ ++ if (unifykey_item) { ++ free(unifykey_item); ++ } ++ const unsigned keyInfBufLen = unify_key_info.key_num * sizeof(struct key_item_t); ++ unifykey_item = (struct key_item_t*)malloc(keyInfBufLen); ++ memset(unifykey_item, 0 , keyInfBufLen); ++ ++ ret = unifykey_item_create(dt_addr,unifykeyNum); ++ unify_key_info.key_flag = ret ? 0 : 1; ++ ++ if (provisionOffset >= 0) ++ { ++ KM_DBG("dts: in find /provisionkey.\n"); ++ ++ int defPermits = 0; ++ const struct fdt_property *prop = fdt_get_property(dt_addr, provisionOffset,"key-permit-default",NULL) ; ++ if (prop) { ++ const int propLen = prop->len > 512 ? strnlen(prop->data, 512) : prop->len; ++ if (fdt_stringlist_contains(prop->data, propLen, UNIFYKEY_PERMIT_READ)) { ++ defPermits |= KEY_M_PERMIT_READ; ++ } ++ if (fdt_stringlist_contains(prop->data, propLen, UNIFYKEY_PERMIT_WRITE)) { ++ defPermits |= KEY_M_PERMIT_WRITE; ++ } ++ if (fdt_stringlist_contains(prop->data, propLen, UNIFYKEY_PERMIT_DEL)) { ++ defPermits |= KEY_M_PERMIT_DEL; ++ } ++ } ++ ++ int node = 0; ++ int id = unifykeyNum; ++ int szlen = 0; ++ fdt_for_each_subnode(node, dt_addr, provisionOffset) { ++ int len = 0; ++ const char* keyName = fdt_get_name(dt_addr, node, &len); ++ KM_DBG("provisionkey[%s] len %d\n", keyName, len); ++ ++ struct key_item_t *pItem= unifykey_item + id; ++ ++ szlen = strnlen(keyName, KEY_UNIFY_NAME_LEN - 1); ++ memcpy(pItem->name, keyName, szlen); ++ if (szlen < KEY_UNIFY_NAME_LEN) pItem->name[szlen] = '\0'; ++ ++ strcpy(pItem->keyType, "raw"); ++ pItem->dev = KEY_M_PROVISION_KEY; ++ pItem->permit = defPermits; ++ pItem->id = id++; ++ if (!strcmp(_PROVSION_DEFAULT_KEY_NAME, keyName)) _defProvisonItem = pItem; ++ } ++ ++ if ((node < 0) && (node != -FDT_ERR_NOTFOUND)) { ++ KM_ERR("in parse /provisionkey, err(%s)\n", fdt_strerror(node)); ++ return __LINE__; ++ } ++ } ++ ++ return ret; ++} ++ +diff --git a/drivers/amlogic/keymanage/km_efuse_key.c b/drivers/amlogic/keymanage/km_efuse_key.c +new file mode 100644 +index 00000000000..c5c1e53baf7 +--- /dev/null ++++ b/drivers/amlogic/keymanage/km_efuse_key.c +@@ -0,0 +1,156 @@ ++/* ++ * \file km_efuse_key.c ++ * \brief efuse key ops for key manage ++ * ++ * \version 1.0.0 ++ * \date 15/06/30 ++ * \author Sam.Wu ++ * ++ * Copyright (c) 2015 Amlogic. All Rights Reserved. ++ * ++ */ ++#include "key_manage_i.h" ++#include ++#include ++ ++#include ++#include ++ ++#define SECURE_BOOT_KEY_NAME "secure_boot_set" ++ ++extern int efuse_usr_api_init_dtb(const char* dt_addr); ++extern int efuse_usr_api_get_cfg_key_size(const char* keyname, unsigned* pSz); ++extern int efuse_usr_api_write_key(const char* keyname, const void* keydata, const unsigned dataSz); ++extern int efuse_usr_api_read_key(const char* keyname, void* databuf, const unsigned bufSz); ++ ++int keymanage_efuse_init(const char *buf, int len) ++{ ++ char ver; ++ int ret = 0; ++ ++ const char* dtbLoadAddr; ++ dtbLoadAddr = (char*) env_get_ulong("fdtcontroladdr", 16, CFG_SYS_SDRAM_BASE + (16U<<20)); ++ ++ ret = efuse_usr_api_init_dtb(dtbLoadAddr); ++ if (ret) { ++ KM_ERR("efuse init failed\n"); ++ return __LINE__; ++ } ++ ++ ver = unifykey_get_efuse_version(); ++ if (ver == 0) { ++ KM_DBG("efuse version not cfg\n"); ++ return 0; ++ } ++ ++ //TODO: program the efuse version ++ ++ return ret; ++} ++ ++int keymange_efuse_exit(void) ++{ ++ return 0; ++} ++ ++//must be hexdata if stored in efuse ++int keymanage_efuse_write(const char *keyname, const void* keydata, unsigned int datalen) ++{ ++ int ret = 0; ++ ++ if (!strcmp(SECURE_BOOT_KEY_NAME, keyname)) ++ { ++ char _cmdbuf[96]; ++ sprintf(_cmdbuf, "efuse %s %p", keyname, keydata); ++ ret = run_command(_cmdbuf, 0);; ++ } ++ else ++ { ++ ret = efuse_usr_api_write_key(keyname, keydata, datalen); ++ } ++ ++ return ret; ++} ++ ++ssize_t keymanage_efuse_size(const char* keyname) ++{ ++ int ret = 0; ++ unsigned cfgSz = 0; ++ ++ ret = efuse_usr_api_get_cfg_key_size(keyname, &cfgSz); ++ if (ret || !cfgSz) { ++ KM_ERR("Fail at get cfg size for efuse key[%s]\n", keyname); ++ return 0; ++ } ++ ++ return cfgSz; ++} ++ ++int keymanage_efuse_exist(const char* keyname) ++{ ++ ++ if (!strcmp(SECURE_BOOT_KEY_NAME, keyname)) ++ { ++ const unsigned long cfg10 = IS_FEAT_BOOT_VERIFY(); ++ KM_MSG("cfg10=0x%lX\n", cfg10); ++ return ( cfg10 ); ++ } ++ else ++ { ++ int ret = 0; ++ const ssize_t cfgSz = keymanage_efuse_size(keyname); ++ char* databuf = NULL; ++ int isEmpty = 1; ++ int i = 0; ++ ++ databuf = (char*)malloc(cfgSz); ++ if (!databuf) { ++ KM_ERR("Fail to alloc bufsz 0x%x for key %s\n", (unsigned)cfgSz, keyname); ++ return 0; ++ } ++ ret = keymanage_efuse_read(keyname, databuf, cfgSz); ++ if (ret) { ++ KM_ERR("Fail at read key[%s]\n", keyname); ++ goto _exit; ++ } ++ for (i = 0; i < cfgSz && isEmpty; ++i) { ++ isEmpty = !databuf[i]; ++ } ++ ++_exit: ++ free(databuf); ++ return !isEmpty; ++ } ++ ++ return __LINE__; ++} ++ ++int keymanage_efuse_query_can_read(const char* keyname) ++{ ++ if (!strcmp(SECURE_BOOT_KEY_NAME, keyname)) ++ { ++ return 0; ++ } ++ else ++ { ++ return 1;//user space always can be read ++ } ++} ++ ++//data format is hexdata ++int keymanage_efuse_read(const char *keyname, void* databuf, const unsigned bufSz) ++{ ++ int ret = 0; ++ unsigned cfgSz = 0; ++ ++ cfgSz = keymanage_efuse_size(keyname); ++ if (cfgSz > bufSz) { ++ KM_ERR("buf sz 0x%x < dts cfg sz 0x%x\n", bufSz, cfgSz); ++ return __LINE__; ++ } ++ ++ ret = efuse_usr_api_read_key(keyname, databuf, cfgSz); ++ ++ return ret; ++} ++ +diff --git a/drivers/amlogic/keymanage/km_provision_key.c b/drivers/amlogic/keymanage/km_provision_key.c +new file mode 100644 +index 00000000000..954a42b28a2 +--- /dev/null ++++ b/drivers/amlogic/keymanage/km_provision_key.c +@@ -0,0 +1,102 @@ ++/* ++* Copyright (C) 2017 Amlogic, Inc. All rights reserved. ++* * ++This program is free software; you can redistribute it and/or modify ++* it under the terms of the GNU General Public License as published by ++* the Free Software Foundation; either version 2 of the License, or ++* (at your option) any later version. ++* * ++This program is distributed in the hope that it will be useful, but WITHOUT ++* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++* more details. ++* * ++You should have received a copy of the GNU General Public License along ++* with this program; if not, write to the Free Software Foundation, Inc., ++* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++* * ++Description: ++*/ ++ ++#include "key_manage_i.h" ++#include ++ ++#define _CMD_BUF_LEN 512 ++static char _cmdBuf[_CMD_BUF_LEN]; ++ ++int keymanage_provision_init(const char *buf, int len) ++{ ++ KM_DBG("f(%s)L%d\n", __func__, __LINE__); ++ return 0; ++} ++ ++int keymanage_provision_exit(void) ++{ ++ KM_DBG("f(%s)L%d\n", __func__, __LINE__); ++ return 0; ++} ++ ++//must be hexdata if stored in efuse ++int keymanage_provision_write(const char *keyname, const void* keydata, unsigned int datalen) ++{ ++ KM_DBG("f(%s)L%d\n", __func__, __LINE__); ++ ++ snprintf(_cmdBuf, _CMD_BUF_LEN, "factory_provision write %s 0x%p 0x%x", keyname, keydata, datalen); ++ int iRet = run_command(_cmdBuf, 0); ++ KM_MSG("factory provision[%s], query sta=%d\n", keyname, iRet); ++ ++ return iRet; ++} ++ ++ssize_t keymanage_provision_size(const char* keyname) ++{ ++ KM_DBG("f(%s)L%d\n", __func__, __LINE__); ++ uint32_t retBuf[12]; ++ snprintf(_cmdBuf, _CMD_BUF_LEN, "factory_provision query %s 0x%p", keyname, retBuf); ++ int iRet = run_command(_cmdBuf, 0); ++ if (iRet) { ++ KM_MSG("factory provision[%s], query sta=%d\n", keyname, iRet); ++ return 0; ++ } ++ ++ return retBuf[0]; ++} ++ ++int keymanage_provision_exist(const char* keyname) ++{ ++ KM_DBG("f(%s)L%d\n", __func__, __LINE__); ++ snprintf(_cmdBuf, _CMD_BUF_LEN, "factory_provision query %s", keyname); ++ int iRet = run_command(_cmdBuf, 0); ++ if (iRet) KM_MSG("factory provision[%s], query sta=%d\n", keyname, iRet); ++ ++ return !iRet; ++} ++ ++int keymanage_provision_query_can_read(const char* keyname) ++{ ++ KM_DBG("f(%s)L%d\n", __func__, __LINE__); ++ ++ return 0;//always cannot be read ++} ++ ++//read hash instead of actual value ++int keymanage_provision_read(const char *keyname, void* databuf, const unsigned bufSz) ++{ ++ KM_DBG("f(%s)L%d\n", __func__, __LINE__); ++ uint32_t retBuf[12]; ++ snprintf(_cmdBuf, _CMD_BUF_LEN, "factory_provision query %s 0x%p", keyname, retBuf); ++ int iRet = run_command(_cmdBuf, 0); ++ if (iRet) { ++ KM_MSG("factory provision[%s], query sta=%d\n", keyname, iRet); ++ return __LINE__; ++ } ++ if (bufSz < 32) { ++ KM_ERR("bufsz %d not enough for sha256sum\n", bufSz); ++ return -__LINE__; ++ } ++ ++ KM_MSG("provision read return sha256sum, but not original data\n"); ++ memcpy(databuf, retBuf + 1, 32); ++ return 0;// ++} ++ +diff --git a/drivers/amlogic/keymanage/km_secure_key.c b/drivers/amlogic/keymanage/km_secure_key.c +new file mode 100644 +index 00000000000..f33652b1b67 +--- /dev/null ++++ b/drivers/amlogic/keymanage/km_secure_key.c +@@ -0,0 +1,263 @@ ++/* ++ * \file km_secure_key.c ++ * \brief secure storage key ops for key manage ++ * ++ * \version 1.0.0 ++ * \date 15/06/30 ++ * \author Sam.Wu ++ * ++ * Copyright (c) 2015 Amlogic. All Rights Reserved. ++ * ++ */ ++#include "key_manage_i.h" ++#include ++#include ++ ++int keymanage_securekey_init(const char* buf, int len) ++{ ++ int encrypt_type; ++ ++ encrypt_type = unifykey_get_encrypt_type(); ++ return amlkey_init((uint8_t*)buf, len, encrypt_type); //confirm ++} ++ ++int keymanage_securekey_exit(void) ++{ ++ return 0; ++} ++ ++int keymanage_secukey_write(const char *keyname, const void* keydata, unsigned int datalen) ++{ ++ int ret = 0; ++ uint8_t origSum[SHA256_SUM_LEN]; ++ const int isSecure = ( KEY_M_SECURE_KEY == keymanage_dts_get_key_device(keyname) ) ? 1 : 0; ++ const int isEncrypt= strlen(keymanage_dts_get_enc_type(keyname)) ? 1 : 0; ++ const unsigned int keyAttr = ( isSecure << 0 ) | ( isEncrypt << 8 ); ++ ssize_t writenLen = 0; ++ ++ if (isSecure) ++ { ++ sha256_context ctx; ++ sha256_starts(&ctx); ++ sha256_update(&ctx, keydata, datalen); ++ sha256_finish(&ctx, origSum); ++ } ++ ++ KM_MSG("isEncrypt=%s\n", keymanage_dts_get_enc_type(keyname)); ++ KM_DBG("%s, keyname=%s, keydata=%p, datalen=%d, isSecure=%d\n", __func__, keyname, keydata, datalen, isSecure); ++ KM_MSG("keyAttr is 0x%08X\n", keyAttr); ++ writenLen = amlkey_write((uint8_t*)keyname, (uint8_t*)keydata, datalen, keyAttr); ++ if (writenLen != datalen) { ++ KM_ERR("Want to write %u bytes, but only %zd Bytes\n", datalen, writenLen); ++ return __LINE__; ++ } ++ ++ if (isSecure) ++ { ++ uint8_t genSum[SHA256_SUM_LEN]; ++ ++ ret = amlkey_hash_4_secure((uint8_t*)keyname, genSum); ++ if (ret) { ++ KM_ERR("Failed when gen hash for secure key[%s], ret=%d\n", keyname, ret); ++ return __LINE__; ++ } ++ ++ ret = memcmp(origSum, genSum, SHA256_SUM_LEN); ++ if (ret) ++ { ++ int index = 0; ++ char origSum_str[SHA256_SUM_LEN * 2 + 2]; ++ char genSum_str[SHA256_SUM_LEN * 2 + 2]; ++ ++ origSum_str[0] = genSum_str[0] = '\0'; ++ for (index = 0; index < SHA256_SUM_LEN; ++index) { ++ ++ sprintf(origSum_str, "%s%02x", origSum_str, origSum[index]); ++ sprintf(genSum_str, "%s%02x", genSum_str, genSum[index]); ++ } ++ ++ KM_ERR("Failed in check hash, origSum[%s] != genSum[%s]\n", origSum_str, genSum_str); ++ return __LINE__; ++ } ++ KM_MSG("OK in check sha1256 in burn key[%s]\n", keyname); ++ } ++ ++ return ret; ++} ++ ++ssize_t keymanage_secukey_size(const char* keyname) ++{ ++ return amlkey_size((uint8_t*)keyname); //actully size ++} ++ ++int keymanage_secukey_exist(const char* keyname) ++{ ++ return amlkey_isexsit((uint8_t*)keyname); //exsit 1, non 0 ++} ++ ++int keymanage_secukey_can_read(const char* keyname) ++{ ++ return !amlkey_issecure((uint8_t*)keyname); //secure 1, non 0 ++} ++ ++int keymanage_secukey_read(const char* keyname, void* databuf, unsigned buflen) ++{ ++ int ret = 0; ++ ++ ret = keymanage_secukey_can_read(keyname); ++ if (!ret) { ++ KM_ERR("key[%s] can't read, is configured secured?\n", keyname); ++ return __LINE__; ++ } ++ ++ const ssize_t readLen = amlkey_read((uint8_t*)keyname, (uint8_t*)databuf, buflen); ++ if (readLen != buflen) { ++ KM_ERR("key[%s], want read %u Bytes, but %zd bytes\n", keyname, buflen, readLen); ++ return __LINE__; ++ } ++ ++ return 0; ++} ++ ++#if 1//hdcp2 rx start ++#define HDCP2_RX_LC128_LEN (36) ++#define HDCP2_RX_KEY_LEN (862) ++#pragma pack(push, 1) ++typedef struct _Hdcp2RxKeyFmt{ ++ unsigned version; ++ char lc128[HDCP2_RX_LC128_LEN]; ++ char keyVal[HDCP2_RX_KEY_LEN]; ++}Hdcp2RxKeyFmt_t; ++#pragma pack(pop) ++ ++#define HDCP2_RX_KEY_TOTAL_LEN sizeof(Hdcp2RxKeyFmt_t) ++#define HDCP2_RX_KEY_LC128_NAME "hdcp2lc128" ++#define HDCP2_RX_KEY_NAME "hdcp2key" ++#define HDCP2_RX_KEY_VERSION (0x02000000U) ++#define HDCP2_VERSION_LEN ( 4 ) ++ ++static char generalDataChange(const char input) ++{ ++ int i; ++ char result = 0; ++ ++ for (i=0; i<8; i++) { ++ if ((input & (1< bufLen) { ++ KM_ERR("hdcp2 rx len unsupported. want %d but get %d\n", keyLen, bufLen); ++ return __LINE__; ++ } ++ if (HDCP2_RX_KEY_VERSION != pHdcp2RxKey->version) { ++ KM_ERR("Version value 0x%x is error, should be 0x%x\n", pHdcp2RxKey->version, HDCP2_RX_KEY_VERSION); ++ return __LINE__; ++ } ++ ++ hdcp2DataEncryption(keyLen, databuf, decryptBuf); ++ KM_MSG("Ecnrypt hdcp2 END.\n"); ++ pHdcp2RxKey = (Hdcp2RxKeyFmt_t*)decryptBuf; ++ ++ const uint8_t* tmpName = (uint8_t*)HDCP2_RX_KEY_LC128_NAME; ++ unsigned tmpLen = HDCP2_RX_LC128_LEN; ++ unsigned isSecure = 0; ++ ssize_t retLen = 0; ++ retLen = amlkey_write(tmpName, (uint8_t*)&pHdcp2RxKey->lc128, tmpLen , isSecure); ++ if (retLen != tmpLen) { ++ KM_ERR ("Fail in write hdcp2 lc128, retLen %zd != want len %d\n", retLen, tmpLen) ; ++ return __LINE__; ++ } ++ ++ tmpName = (uint8_t*)HDCP2_RX_KEY_NAME; ++ tmpLen = HDCP2_RX_KEY_LEN; ++ retLen = amlkey_write(tmpName, (uint8_t*)&pHdcp2RxKey->keyVal, tmpLen , isSecure); ++ if (retLen != tmpLen) { ++ KM_ERR ("Fail in write hdcp2 key, retLen %zd != want len %d\n", retLen, tmpLen) ; ++ return __LINE__; ++ } ++ ++ tmpLen = HDCP2_VERSION_LEN; ++ retLen = amlkey_write((uint8_t*)keyname, (uint8_t*)&pHdcp2RxKey->version, tmpLen, isSecure); ++ if (retLen != tmpLen) { ++ KM_ERR ("Fail in write hdcp2 key, retLen %zd != want len %d\n", retLen, tmpLen) ; ++ return __LINE__; ++ } ++ ++ return 0; ++} ++ ++int _read_key_in_type_hdcp2(const char* keyname, void* databuf, const unsigned bufLen, char* decryptBuf) ++{ ++ const unsigned srcKeyLen = HDCP2_RX_KEY_TOTAL_LEN; ++ Hdcp2RxKeyFmt_t* pHdcp2RxKey = (Hdcp2RxKeyFmt_t*)decryptBuf; ++ const uint8_t* tmpName = NULL; ++ int tmpLen = 0; ++ ++ if (bufLen < srcKeyLen) { ++ KM_ERR("hdcp2 rx len unsupported. want %d but only %d\n", srcKeyLen, bufLen); ++ return __LINE__; ++ } ++ ++ ssize_t retLen = 0; ++ tmpName = (uint8_t*)keyname; ++ tmpLen = HDCP2_VERSION_LEN; ++ retLen = amlkey_read(tmpName, (uint8_t*)&pHdcp2RxKey->version, tmpLen); ++ if (retLen != tmpLen) { ++ KM_ERR ("Fail in read key[%s] at len %d\n", tmpName, tmpLen) ; ++ return __LINE__; ++ } ++ ++ tmpName = (uint8_t*)HDCP2_RX_KEY_NAME; ++ tmpLen = HDCP2_RX_KEY_LEN; ++ retLen = amlkey_read(tmpName, (uint8_t*)&pHdcp2RxKey->keyVal, tmpLen); ++ if (retLen != tmpLen) { ++ KM_ERR ("Fail in read key[%s] at len %d\n", tmpName, tmpLen) ; ++ return __LINE__; ++ } ++ ++ tmpName = (uint8_t*)HDCP2_RX_KEY_LC128_NAME; ++ tmpLen = HDCP2_RX_LC128_LEN; ++ retLen = amlkey_read(tmpName, (uint8_t*)&pHdcp2RxKey->lc128, tmpLen); ++ if (retLen != tmpLen) { ++ KM_ERR ("Fail in read key[%s] at len %d\n", tmpName, tmpLen) ; ++ return __LINE__; ++ } ++ ++ hdcp2DataDecryption(srcKeyLen, (char*)pHdcp2RxKey, databuf); ++ ++ return 0; ++} ++int _km_hdcp2_size(void) ++{ ++ return HDCP2_RX_KEY_TOTAL_LEN; ++} ++#endif//hdcp2 rx end ++ ++ +diff --git a/drivers/amlogic/keymanage/km_secure_key_2015.c b/drivers/amlogic/keymanage/km_secure_key_2015.c +new file mode 100644 +index 00000000000..5baabb88f05 +--- /dev/null ++++ b/drivers/amlogic/keymanage/km_secure_key_2015.c +@@ -0,0 +1,118 @@ ++/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ ++/* ++ * drivers/keymanage/km_secure_key.c ++ * ++ * Copyright (C) 2020 Amlogic, Inc. All rights reserved. ++ * ++ */ ++ ++#include "key_manage_i.h" ++#include ++#include ++ ++int keymanage_securekey_init(const char* buf, int len) ++{ ++ int encrypt_type; ++ ++ encrypt_type = unifykey_get_encrypt_type(); ++ return amlkey_init((uint8_t*)buf, len, encrypt_type); //confirm ++} ++ ++int keymanage_securekey_exit(void) ++{ ++ return 0; ++} ++ ++int keymanage_secukey_write(const char *keyname, const void* keydata, unsigned int datalen) ++{ ++ int ret = 0; ++ uint8_t origSum[SHA256_SUM_LEN]; ++ const int isSecure = ( KEY_M_SECURE_KEY == keymanage_dts_get_key_device(keyname) ) ? 1 : 0; ++ const int isEncrypt= strlen(keymanage_dts_get_enc_type(keyname)) ? 1 : 0; ++ const unsigned int keyAttr = ( isSecure << 0 ) | ( isEncrypt << 8 ); ++ ssize_t writenLen = 0; ++ ++ if (isSecure) ++ { ++ sha256_context ctx; ++ sha256_starts(&ctx); ++ sha256_update(&ctx, keydata, datalen); ++ sha256_finish(&ctx, origSum); ++ } ++ ++ KM_MSG("isEncrypt=%s\n", keymanage_dts_get_enc_type(keyname)); ++ KM_DBG("%s, keyname=%s, keydata=%p, datalen=%d, isSecure=%d\n", __func__, keyname, keydata, datalen, isSecure); ++ KM_MSG("keyAttr is 0x%08X\n", keyAttr); ++ writenLen = amlkey_write((uint8_t*)keyname, (uint8_t*)keydata, datalen, keyAttr); ++ if (writenLen != datalen) { ++ KM_ERR("Want to write %u bytes, but only %zd Bytes\n", datalen, writenLen); ++ return __LINE__; ++ } ++ ++ if (isSecure) ++ { ++ uint8_t genSum[SHA256_SUM_LEN]; ++ ++ ret = amlkey_hash_4_secure((uint8_t*)keyname, genSum); ++ if (ret) { ++ KM_ERR("Failed when gen hash for secure key[%s], ret=%d\n", keyname, ret); ++ return __LINE__; ++ } ++ ++ ret = memcmp(origSum, genSum, SHA256_SUM_LEN); ++ if (ret) ++ { ++ int index = 0; ++ char origSum_str[SHA256_SUM_LEN * 2 + 2]; ++ char genSum_str[SHA256_SUM_LEN * 2 + 2]; ++ ++ origSum_str[0] = genSum_str[0] = '\0'; ++ for (index = 0; index < SHA256_SUM_LEN; ++index) { ++ ++ sprintf(origSum_str, "%s%02x", origSum_str, origSum[index]); ++ sprintf(genSum_str, "%s%02x", genSum_str, genSum[index]); ++ } ++ ++ KM_ERR("Failed in check hash, origSum[%s] != genSum[%s]\n", origSum_str, genSum_str); ++ return __LINE__; ++ } ++ KM_MSG("OK in check sha1256 in burn key[%s]\n", keyname); ++ } ++ ++ return ret; ++} ++ ++ssize_t keymanage_secukey_size(const char* keyname) ++{ ++ return amlkey_size((uint8_t*)keyname); //actully size ++} ++ ++int keymanage_secukey_exist(const char* keyname) ++{ ++ return amlkey_isexsit((uint8_t*)keyname); //exsit 1, non 0 ++} ++ ++int keymanage_secukey_can_read(const char* keyname) ++{ ++ return !amlkey_issecure((uint8_t*)keyname); //secure 1, non 0 ++} ++ ++int keymanage_secukey_read(const char* keyname, void* databuf, unsigned buflen) ++{ ++ int ret = 0; ++ ++ ret = keymanage_secukey_can_read(keyname); ++ if (!ret) { ++ KM_ERR("key[%s] can't read, is configured secured?\n", keyname); ++ return __LINE__; ++ } ++ ++ const ssize_t readLen = amlkey_read((uint8_t*)keyname, (uint8_t*)databuf, buflen); ++ if (readLen != buflen) { ++ KM_ERR("key[%s], want read %u Bytes, but %zd bytes\n", keyname, buflen, readLen); ++ return __LINE__; ++ } ++ ++ return 0; ++} ++ +diff --git a/drivers/amlogic/storagekey/Kconfig b/drivers/amlogic/storagekey/Kconfig +new file mode 100644 +index 00000000000..311ab7e8ec3 +--- /dev/null ++++ b/drivers/amlogic/storagekey/Kconfig +@@ -0,0 +1,2 @@ ++config SECURE_STORAGE ++ bool "Amlogic bl31 storage key" +diff --git a/drivers/amlogic/storagekey/Makefile b/drivers/amlogic/storagekey/Makefile +new file mode 100644 +index 00000000000..6e7ccb4ba3e +--- /dev/null ++++ b/drivers/amlogic/storagekey/Makefile +@@ -0,0 +1,3 @@ ++obj-$(CONFIG_SECURE_STORAGE) += storagekey.o ++obj-$(CONFIG_SECURE_STORAGE) += securestorage.o ++obj-$(CONFIG_SECURE_STORAGE) += normal_key.o +diff --git a/drivers/amlogic/storagekey/normal_key.c b/drivers/amlogic/storagekey/normal_key.c +new file mode 100644 +index 00000000000..9e40c8fdfe9 +--- /dev/null ++++ b/drivers/amlogic/storagekey/normal_key.c +@@ -0,0 +1,672 @@ ++/* ++ * drivers/storagekey/normal_key.c ++ * ++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include "normal_key.h" ++ ++#undef pr_info ++#define pr_info(fmt ...) printf("[KM]Msg:"fmt) ++#undef pr_err ++#define pr_err(fmt ...) printf("[KM]Error:f[%s]L%d:", __func__, __LINE__),printf(fmt) ++ ++#define DBG 0 ++ ++/* Storage BLOCK RAW HEAD: fixed 512B*/ ++#define ENC_TYPE_DEFAULT 0 ++#define ENC_TYPE_EFUSE 1 ++#define ENC_TYPE_FIXED 2 ++ ++#define STORAGE_BLOCK_RAW_HEAD_SIZE 512 ++ ++#define BLOCK_VERSION_0 0 ++ ++#define ERR_HEADER 0x1 ++#define ERR_KEYMEMFAIL 0x2 ++#define ERR_KEYRDFAIL 0x4 ++#define ERR_KEYCHKFAIL 0x8 ++#define ERR_ENCHDFAIL 0x10 ++#define ERR_DATASZ 0x20 ++struct storage_block_raw_head { ++ u8 mark[16]; /* AMLNORMAL*/ ++ u32 version; ++ u32 enctype; /*from EFUSE, from default, from fixed*/ ++ u32 keycnt; ++ u32 initcnt; ++ u32 wrtcnt; ++ u32 errcnt; ++ u32 flags; ++ u8 headhash[32]; ++ u8 hash[32]; ++}; ++ ++/* Storage BLOCK ENC HEAD: fixed 512B*/ ++#define STORAGE_BLOCK_ENC_HEAD_SIZE 512 ++struct storage_block_enc_head { ++ u32 blocksize; ++ u32 flashsize; ++}; ++ ++/* Storage Format: TLV*/ ++enum emTLVTag { ++ EMTLVNONE, ++ ++ EMTLVHEAD, ++ EMTLVHEADSIZE, ++ ++ EMTLVOBJECT, ++ EMTLVOBJNAMESIZE, ++ EMTLVOBJNAME, ++ EMTLVOBJDATASIZE, ++ EMTLVOBJDATABUF, ++ EMTLVOBJTYPE, ++ EMTLVOBJATTR, ++ EMTLVOBJHASHBUF, ++ ++ EMTLVHEADFLASHSIZE, ++}; ++ ++struct storage_node { ++ struct list_head node; ++ struct storage_object object; ++}; ++ ++static LIST_HEAD(keys); ++static int blockinited; ++static struct storage_block_raw_head rawhead; ++static struct storage_block_enc_head enchead; ++static char *blockmark = "AMLNORMAL"; ++ ++#if DBG ++static void dump_raw_head(struct storage_block_raw_head *prawhead) ++{ ++ pr_info("rawhead:\n"); ++ pr_info("mark: %s\n", prawhead->mark); ++ pr_info("keycnt: %u\n", prawhead->keycnt); ++ pr_info("initcnt: %u\n", prawhead->initcnt); ++ pr_info("wrtcnt: %u\n", prawhead->wrtcnt); ++ pr_info("errcnt: %u\n", prawhead->errcnt); ++ pr_info("flags: 0x%x\n", prawhead->flags); ++} ++ ++static void dump_enc_head(struct storage_block_enc_head *penchead) ++{ ++ pr_info("enchead:\n"); ++ pr_info("blocksize: %u\n", penchead->blocksize); ++ pr_info("flashsize: %u\n", penchead->flashsize); ++} ++ ++static void dump_mem(const u8 *p, int len) ++{ ++ int idx = 0, j, tmp; ++ char buf[64]; ++ int total; ++ ++ while (idx < len) { ++ total = 0; ++ tmp = min(((int)len - idx), 16); ++ for (j = 0; j < tmp; j++) ++ total += snprintf(buf + total, 64 - total, ++ "%02x ", p[idx + j]); ++ buf[total] = 0; ++ pr_info("%s\n", buf); ++ idx += tmp; ++ } ++} ++ ++static void dump_object(struct storage_object *obj) ++{ ++ pr_info("key: [%u, %.*s, %x, %x, %u]\n", ++ obj->namesize, obj->namesize, obj->name, ++ obj->type, obj->attribute, obj->datasize); ++ if (obj->dataptr) { ++ pr_info("data:\n"); ++ dump_mem(obj->dataptr, obj->datasize); ++ } ++} ++#endif ++ ++static u32 Tlv_WriteUint32(u8 *output, s32 len, ++ u32 tag, u32 value) ++{ ++ u32 *out = (u32 *)output; ++ ++ if (len < 12) ++ return 0; ++ ++ out[0] = tag; ++ out[1] = 4; ++ out[2] = value; ++ return 12; ++} ++ ++static u32 Tlv_WriteBuf(u8 *output, s32 len, ++ u32 tag, ++ u32 length, u8 *input) ++{ ++ u8 *out = output; ++ u32 tmplen = (((length + 3) / 4) * 4); ++ ++ if (len < (s32)(8 + tmplen)) ++ return 0; ++ ++ *((u32 *)out) = tag; ++ *((u32 *)(out + 4)) = tmplen; ++ memset(out + 8, 0, tmplen); ++ memcpy(out + 8, input, length); ++ ++ return tmplen + 8; ++} ++ ++static u32 Tlv_ReadTl(u8 *input, int32_t len, ++ u32 *tag, u32 *length, ++ u32 *idx) ++{ ++ if (len < 8) ++ return 0; ++ ++ *tag = *((u32 *)input); ++ *length = *((u32 *)(input + 4)); ++ ++ if ((8 + *length) > len) ++ return 0; ++ *idx += 8; ++ ++ return 8; ++} ++ ++static u32 Tlv_ReadHead(u8 *input, int32_t len, ++ struct storage_block_enc_head *pblockhead) ++{ ++ u32 tag; ++ u32 sum; ++ u32 length; ++ u32 idx = 0; ++ u32 ret; ++ ++ ret = Tlv_ReadTl(input, len, ++ &tag, &sum, &idx); ++ if (!ret) ++ return 0; ++ ++ if (tag != EMTLVHEAD) ++ return 0; ++ ++ sum += ret; ++ while (idx < sum) { ++ ret = Tlv_ReadTl(input + idx, len - idx, ++ &tag, &length, &idx); ++ if (!ret) ++ return 0; ++ ++ switch (tag) { ++ case EMTLVHEADSIZE: ++ pblockhead->blocksize = *((u32 *)(input + idx)); ++ break; ++ case EMTLVHEADFLASHSIZE: ++ pblockhead->flashsize = *((u32 *)(input + idx)); ++ break; ++ default: ++ break; ++ } ++ idx += length; ++ } ++ return sum; ++} ++ ++static u32 Tlv_ReadObject(u8 *input, int32_t len, ++ struct storage_object *pcontent) ++{ ++ u32 tag; ++ u32 length; ++ u32 sum; ++ u32 idx = 0; ++ u32 ret; ++ ++ memset(pcontent, 0, sizeof(*pcontent)); ++ ret = Tlv_ReadTl(input, len, ++ &tag, &sum, &idx); ++ if (!ret) ++ return 0; ++ ++ if (tag != EMTLVOBJECT) ++ return 0; ++ ++ sum += ret; ++ while (idx < sum) { ++ ret = Tlv_ReadTl(input + idx, len - idx, ++ &tag, &length, &idx); ++ if (!ret) ++ goto tlv_readkeycontent_err; ++ ++ switch (tag) { ++ case EMTLVOBJNAMESIZE: ++ pcontent->namesize = *((u32 *)(input + idx)); ++ break; ++ case EMTLVOBJNAME: ++ memset(pcontent->name, 0, MAX_OBJ_NAME_LEN); ++ memcpy(pcontent->name, input + idx, pcontent->namesize); ++ break; ++ case EMTLVOBJTYPE: ++ pcontent->type = *((u32 *)(input + idx)); ++ break; ++ case EMTLVOBJATTR: ++ pcontent->attribute = *((u32 *)(input + idx)); ++ break; ++ case EMTLVOBJDATASIZE: ++ pcontent->datasize = *((u32 *)(input + idx)); ++ break; ++ case EMTLVOBJHASHBUF: ++ if (length != 32) ++ goto tlv_readkeycontent_err; ++ memcpy(pcontent->hashptr, input + idx, length); ++ break; ++ case EMTLVOBJDATABUF: ++ pcontent->dataptr = malloc(pcontent->datasize); ++ if (!pcontent->dataptr) ++ goto tlv_readkeycontent_err; ++ memcpy(pcontent->dataptr, ++ input + idx, pcontent->datasize); ++ break; ++ default: ++ break; ++ } ++ idx += length; ++ } ++ return sum; ++ ++tlv_readkeycontent_err: ++ free(pcontent->dataptr); ++ return 0; ++} ++ ++#define WRT_UINT32(tag, field) \ ++ ({ \ ++ u32 __tmp; \ ++ __tmp = Tlv_WriteUint32(output + idx, len - idx, \ ++ tag, field); \ ++ if (__tmp) \ ++ idx += __tmp; \ ++ __tmp; \ ++ }) ++ ++#define WRT_BUF(tag, buflen, buf) \ ++ ({ \ ++ u32 __tmp; \ ++ __tmp = Tlv_WriteBuf(output + idx, len - idx, \ ++ tag, buflen, buf); \ ++ if (__tmp) \ ++ idx += __tmp; \ ++ __tmp; \ ++ }) ++ ++u32 Tlv_WriteHead(struct storage_block_enc_head *enchead, ++ u8 *output, int32_t len) ++{ ++ u32 *sum; ++ u32 idx = 0; ++ ++ if (len < 8) ++ return 0; ++ ++ *(u32 *)output = EMTLVHEAD; ++ sum = (u32 *)(output + 4); ++ idx += 8; ++ ++ if (!WRT_UINT32(EMTLVHEADSIZE, enchead->blocksize)) ++ return 0; ++ if (!WRT_UINT32(EMTLVHEADFLASHSIZE, enchead->flashsize)) ++ return 0; ++ ++ *sum = idx - 8; ++ return idx; ++} ++ ++u32 Tlv_WriteObject(struct storage_object *object, ++ u8 *output, int32_t len) ++{ ++ u32 *sum; ++ u32 idx = 0; ++ ++ if (len < 8) ++ return 0; ++ ++ *(u32 *)output = EMTLVOBJECT; ++ sum = (u32 *)(output + 4); ++ idx += 8; ++ ++ if (object->namesize != 0) { ++ if (!WRT_UINT32(EMTLVOBJNAMESIZE, object->namesize)) ++ return 0; ++ if (!WRT_BUF(EMTLVOBJNAME, object->namesize, ++ (u8 *)object->name)) ++ return 0; ++ } ++ ++ if (object->dataptr && object->datasize != 0) { ++ if (!WRT_UINT32(EMTLVOBJDATASIZE, object->datasize)) ++ return 0; ++ if (!WRT_BUF(EMTLVOBJDATABUF, object->datasize, ++ object->dataptr)) ++ return 0; ++ } ++ ++ if (!WRT_BUF(EMTLVOBJHASHBUF, 32, object->hashptr)) ++ return 0; ++ if (!WRT_UINT32(EMTLVOBJTYPE, object->type)) ++ return 0; ++ if (!WRT_UINT32(EMTLVOBJATTR, object->attribute)) ++ return 0; ++ ++ *sum = idx - 8; ++ return idx; ++} ++ ++static int normalkey_hash(u8 *data, u32 len, u8 *hash) ++{ ++ sha256_context ctx; ++ sha256_starts(&ctx); ++ sha256_update(&ctx, data, len); ++ sha256_finish(&ctx, hash); ++ return 0; ++} ++ ++int normalkey_init(void) ++{ ++ if (blockinited) ++ return 0; ++ ++ blockinited = 1; ++ return 0; ++} ++ ++void normalkey_deinit(void) ++{ ++ struct storage_node *pos, *n; ++ ++ if (!blockinited) ++ return; ++ ++ blockinited = 0; ++ ++ list_for_each_entry_safe(pos, n, &keys, node) { ++ list_del(&pos->node); ++ free(pos->object.dataptr); ++ free(pos); ++ } ++} ++ ++struct storage_object *normalkey_get(const u8 *name) ++{ ++ struct storage_node *pos; ++ struct storage_object *obj; ++ u32 len; ++ ++ if (!name) ++ return NULL; ++ ++ len = strlen((const char*)name); ++ list_for_each_entry(pos, &keys, node) { ++ obj = &pos->object; ++ if (len == obj->namesize && ++ !memcmp(name, obj->name, len)) ++ return obj; ++ } ++ ++ return NULL; ++} ++ ++int normalkey_add(const u8 *name, u8 *buffer, u32 len, u32 attr) ++{ ++ struct storage_object *obj; ++ struct storage_node *node; ++ u32 namelen; ++ u8 *data; ++ ++ if (blockinited != 2) ++ return -1; ++ ++ if (!name || !buffer || !len || (attr & OBJ_ATTR_SECURE)) ++ return -1; ++ ++ namelen = strlen((const char*)name); ++ if (namelen > MAX_OBJ_NAME_LEN) ++ return -1; ++ ++ obj = normalkey_get(name); ++ if (obj) { ++ if (attr != obj->attribute) ++ return -1; ++ if (len > obj->datasize) { ++ data = malloc(len); ++ if (!data) ++ return -1; ++ free(obj->dataptr); ++ obj->dataptr = data; ++ } ++ } else { ++ node = malloc(sizeof(*node)); ++ if (!node) ++ return -1; ++ data = malloc(len); ++ if (!data) { ++ free(node); ++ return -1; ++ } ++ obj = &node->object; ++ memcpy(obj->name, name, namelen); ++ obj->namesize = namelen; ++ obj->attribute = attr; ++ obj->type = OBJ_TYPE_GENERIC; ++ obj->dataptr = data; ++ list_add(&node->node, &keys); ++ } ++ obj->datasize = len; ++ memcpy(obj->dataptr, buffer, len); ++ normalkey_hash(buffer, len, obj->hashptr); ++ return 0; ++} ++ ++int normalkey_del(const u8 *name) ++{ ++ struct storage_object *obj; ++ struct storage_node *node; ++ ++ if (blockinited != 2) ++ return -1; ++ ++ obj = normalkey_get(name); ++ if (!obj) ++ return -1; ++ ++ node = container_of(obj, struct storage_node, object); ++ list_del(&node->node); ++ free(obj->dataptr); ++ free(node); ++ ++ return 0; ++} ++ ++int normalkey_readfromblock(void *block, unsigned long size) ++{ ++ struct storage_block_raw_head *prawhead; ++ u8 *penchead, *pdata; ++ struct storage_node *node = NULL; ++ u8 hash[32]; ++ u32 idx; ++ u32 ret; ++ ++ if (blockinited != 1) ++ return -1; ++ ++ prawhead = (struct storage_block_raw_head *)block; ++ penchead = (u8 *)block + STORAGE_BLOCK_RAW_HEAD_SIZE; ++ pdata = penchead + STORAGE_BLOCK_ENC_HEAD_SIZE; ++ ++ if (!block || size <= ++ (STORAGE_BLOCK_ENC_HEAD_SIZE + STORAGE_BLOCK_RAW_HEAD_SIZE)) ++ return -1; ++ ++ blockinited = 2; ++ ++ memset(&rawhead, 0, sizeof(rawhead)); ++ strncpy((char*)rawhead.mark, blockmark, 15); ++ rawhead.version = BLOCK_VERSION_0; ++ ++ enchead.flashsize = size; ++ if (strcmp((const char *)prawhead->mark, blockmark) != 0) { ++ pr_info("mark is not found\n"); ++ return 0; ++ } ++ ++ normalkey_hash((u8 *)prawhead, sizeof(*prawhead) - 64, ++ rawhead.headhash); ++ if (memcmp(rawhead.headhash, prawhead->headhash, 32)) { ++ pr_info("rawhead hash check fail\n"); ++ rawhead.flags |= ERR_HEADER; ++ } else { ++ pr_info("rawhead hash check successful\n"); ++ rawhead.keycnt = prawhead->keycnt; ++ rawhead.initcnt = prawhead->initcnt; ++ rawhead.wrtcnt = prawhead->wrtcnt; ++ rawhead.errcnt = prawhead->errcnt; ++ rawhead.flags = prawhead->flags; ++ } ++ ++ rawhead.initcnt++; ++ ++#if DBG ++ dump_raw_head(&rawhead); ++#endif ++ ++ normalkey_hash(penchead, size - STORAGE_BLOCK_RAW_HEAD_SIZE, ++ rawhead.hash); ++ if (memcmp(rawhead.hash, prawhead->hash, 32)) { ++ pr_info("data hash check fail\n"); ++ rawhead.errcnt++; ++ return 0; ++ } ++ ++ ret = Tlv_ReadHead(penchead, STORAGE_BLOCK_ENC_HEAD_SIZE, ++ &enchead); ++ if (!ret) { ++ pr_info("read head fail\n"); ++ rawhead.flags |= ERR_ENCHDFAIL; ++ return 0; ++ } ++ ++#if DBG ++ dump_enc_head(&enchead); ++#endif ++ ++ if (size < (enchead.blocksize + STORAGE_BLOCK_ENC_HEAD_SIZE + ++ STORAGE_BLOCK_RAW_HEAD_SIZE)) { ++ rawhead.flags |= ERR_DATASZ; ++ return 0; ++ } ++ ++ idx = 0; ++ while (idx < enchead.blocksize) { ++ struct storage_object *obj = NULL; ++ ++ if (!node) { ++ node = malloc(sizeof(*node)); ++ if (!node) { ++ rawhead.flags |= ERR_KEYMEMFAIL; ++ break; ++ } ++ } ++ obj = &node->object; ++ ret = Tlv_ReadObject(pdata + idx, ++ enchead.blocksize - idx, obj); ++ if (!ret) { ++ rawhead.flags |= ERR_KEYRDFAIL; ++ break; ++ } ++ idx += ret; ++ ++ normalkey_hash(obj->dataptr, obj->datasize, hash); ++ if (memcmp(hash, obj->hashptr, 32)) { ++ free(obj->dataptr); ++ rawhead.flags |= ERR_KEYCHKFAIL; ++ continue; ++ } ++#if DBG ++ dump_object(obj); ++#endif ++ list_add(&node->node, &keys); ++ node = NULL; ++ } ++ ++ free(node); ++ return 0; ++} ++ ++int normalkey_writetoblock(void *block, unsigned long size) ++{ ++ u8 *prawhead; ++ u8 *penchead, *pdata; ++ struct storage_object *obj = NULL; ++ struct storage_node *node = NULL; ++ u32 idx; ++ u32 ret; ++ ++ if (blockinited != 2) ++ return -1; ++ ++ prawhead = (u8 *)block; ++ penchead = prawhead + STORAGE_BLOCK_RAW_HEAD_SIZE; ++ pdata = penchead + STORAGE_BLOCK_ENC_HEAD_SIZE; ++ ++ if (!block || size <= ++ (STORAGE_BLOCK_ENC_HEAD_SIZE + STORAGE_BLOCK_RAW_HEAD_SIZE)) ++ return -1; ++ ++ enchead.flashsize = size; ++ size -= (STORAGE_BLOCK_ENC_HEAD_SIZE + STORAGE_BLOCK_RAW_HEAD_SIZE); ++ idx = 0; ++ rawhead.keycnt = 0; ++ list_for_each_entry(node, &keys, node) { ++ obj = &node->object; ++ ret = Tlv_WriteObject(obj, pdata + idx, size - idx); ++ if (!ret) ++ return -1; ++ idx += ret; ++ rawhead.keycnt++; ++ } ++ enchead.blocksize = idx; ++ ++ ret = Tlv_WriteHead(&enchead, penchead, STORAGE_BLOCK_ENC_HEAD_SIZE); ++ if (!ret) ++ return -1; ++ ++ rawhead.wrtcnt++; ++ normalkey_hash((u8 *)&rawhead, sizeof(rawhead) - 64, ++ rawhead.headhash); ++ normalkey_hash(penchead, ++ enchead.flashsize - STORAGE_BLOCK_RAW_HEAD_SIZE, ++ rawhead.hash); ++ memcpy(prawhead, &rawhead, sizeof(rawhead)); ++ ++ return 0; ++} +diff --git a/drivers/amlogic/storagekey/normal_key.h b/drivers/amlogic/storagekey/normal_key.h +new file mode 100644 +index 00000000000..18772db67e0 +--- /dev/null ++++ b/drivers/amlogic/storagekey/normal_key.h +@@ -0,0 +1,49 @@ ++/* ++ * drivers/amlogic/storagekey/normal_key.h ++ * ++ * Copyright (C) 2017 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ */ ++ ++#ifndef _AML_NORMAL_KEY_H_ ++#define _AML_NORMAL_KEY_H_ ++ ++#define MAX_OBJ_NAME_LEN 80 ++ ++/*Attribute*/ ++#define OBJ_ATTR_SECURE BIT(0) ++#define OBJ_ATTR_OTP BIT(1) ++#define OBJ_ATTR_ENC BIT(8) ++ ++/* Type */ ++#define OBJ_TYPE_GENERIC 0xA00000BF ++ ++struct storage_object { ++ char name[MAX_OBJ_NAME_LEN]; ++ u32 namesize; ++ u32 attribute; /*secure, OTP*/ ++ u32 type; /*AES, RSA, GENERIC, ...*/ ++ u32 datasize; ++ u8 *dataptr; ++ u8 hashptr[32]; ++}; ++ ++int normalkey_init(void); ++void normalkey_deinit(void); ++struct storage_object *normalkey_get(const u8 *name); ++int normalkey_add(const u8 *name, u8 *buffer, u32 len, u32 attr); ++int normalkey_del(const u8 *name); ++int normalkey_readfromblock(void *block, unsigned long size); ++int normalkey_writetoblock(void *block, unsigned long size); ++ ++#endif +diff --git a/drivers/amlogic/storagekey/securestorage.c b/drivers/amlogic/storagekey/securestorage.c +new file mode 100644 +index 00000000000..c65fee5586f +--- /dev/null ++++ b/drivers/amlogic/storagekey/securestorage.c +@@ -0,0 +1,389 @@ ++#include ++#include ++#include ++ ++// TODO: refactor ++#include ++#include ++ ++static uint64_t storage_share_in_base; ++static uint64_t storage_share_out_base; ++static uint64_t storage_share_block_base; ++static uint64_t storage_share_block_size; ++static int32_t storage_init_status; ++ ++static uint64_t bl31_storage_ops(uint64_t function_id) ++{ ++ asm volatile( ++ __asmeq("%0", "x0") ++ "smc #0\n" ++ : "+r" (function_id)); ++ ++ return function_id; ++} ++uint64_t bl31_storage_ops2(uint64_t function_id, uint64_t arg1) ++{ ++ asm volatile( ++ __asmeq("%0", "x0") ++ __asmeq("%1", "x1") ++ "smc #0\n" ++ : "+r" (function_id) ++ : "r"(arg1)); ++ ++ return function_id; ++} ++uint64_t bl31_storage_ops3(uint64_t function_id, uint64_t arg1, uint32_t arg2) ++{ ++ asm volatile( ++ __asmeq("%0", "x0") ++ __asmeq("%1", "x1") ++ __asmeq("%2", "x2") ++ "smc #0\n" ++ : "+r" (function_id) ++ : "r"(arg1), "r"(arg2)); ++ ++ return function_id; ++} ++ ++static uint64_t bl31_storage_write(uint8_t *keyname, uint8_t *keybuf, ++ uint32_t keylen, uint32_t keyattr) ++{ ++ uint32_t *input = (uint32_t *)storage_share_in_base; ++ uint8_t *data; ++ uint32_t namelen; ++ ++ namelen = strlen((const char *)keyname); ++ *input++ = namelen; ++ *input++ = keylen; ++ *input++ = keyattr; ++ data = (uint8_t *)input; ++ memcpy(data, keyname, namelen); ++ data += namelen; ++ memcpy(data, keybuf, keylen); ++ return bl31_storage_ops(SECURITY_KEY_WRITE); ++} ++ ++static uint64_t bl31_storage_read(uint8_t *keyname, uint8_t *keybuf, ++ uint32_t keylen, uint32_t *readlen) ++{ ++ uint32_t *input = (uint32_t *)storage_share_in_base; ++ uint32_t *output = (uint32_t *)storage_share_out_base; ++ uint32_t namelen; ++ uint8_t *name, *buf; ++ uint64_t ret; ++ ++ namelen = strlen((const char *)keyname); ++ *input++ = namelen; ++ *input++ = keylen; ++ name = (uint8_t *)input; ++ memcpy(name, keyname, namelen); ++ ret = bl31_storage_ops(SECURITY_KEY_READ); ++ if (ret == RET_OK) { ++ *readlen = *output; ++ buf = (uint8_t *)(output+1); ++ memcpy(keybuf, buf, *readlen); ++ } ++ return ret; ++} ++ ++static uint64_t bl31_storage_query(uint8_t *keyname, uint32_t *retval) ++{ ++ uint32_t *input = (uint32_t *)storage_share_in_base; ++ uint32_t *output = (uint32_t *)storage_share_out_base; ++ uint32_t namelen; ++ uint8_t *name; ++ uint64_t ret; ++ ++ namelen = strlen((const char *)keyname); ++ *input++ = namelen; ++ name = (uint8_t *)input; ++ memcpy(name, keyname, namelen); ++ ret = bl31_storage_ops(SECURITY_KEY_QUERY); ++ if (ret == RET_OK) ++ *retval = *output; ++ return ret; ++} ++ ++static uint64_t bl31_storage_status(uint8_t *keyname, uint32_t *retval) ++{ ++ uint32_t *input = (uint32_t *)storage_share_in_base; ++ uint32_t *output = (uint32_t *)storage_share_out_base; ++ uint32_t namelen; ++ uint8_t *name; ++ uint64_t ret; ++ ++ namelen = strlen((const char *)keyname); ++ *input++ = namelen; ++ name = (uint8_t *)input; ++ memcpy(name, keyname, namelen); ++ ret = bl31_storage_ops(SECURITY_KEY_STATUS); ++ if (ret == RET_OK) ++ *retval = *output; ++ return ret; ++} ++static uint64_t bl31_storage_tell(uint8_t *keyname, uint32_t *retval) ++{ ++ uint32_t *input = (uint32_t *)storage_share_in_base; ++ uint32_t *output = (uint32_t *)storage_share_out_base; ++ uint32_t namelen; ++ uint8_t *name; ++ uint64_t ret; ++ ++ namelen = strlen((const char *)keyname); ++ *input++ = namelen; ++ name = (uint8_t *)input; ++ memcpy(name, keyname, namelen); ++ ret = bl31_storage_ops(SECURITY_KEY_TELL); ++ if (ret == RET_OK) ++ *retval = *output; ++ return ret; ++} ++ ++static uint64_t bl31_storage_verify(uint8_t *keyname, uint8_t *hashbuf) ++{ ++ uint32_t *input = (uint32_t *)storage_share_in_base; ++ uint32_t *output = (uint32_t *)storage_share_out_base; ++ uint32_t namelen; ++ uint8_t *name; ++ uint64_t ret; ++ ++ namelen = strlen((const char *)keyname); ++ *input++ = namelen; ++ name = (uint8_t *)input; ++ memcpy(name, keyname, namelen); ++ ret = bl31_storage_ops(SECURITY_KEY_VERIFY); ++ ++ if (ret == RET_OK) ++ memcpy(hashbuf, (uint8_t *)output, 32); ++ return ret; ++} ++ ++static uint64_t bl31_storage_list(uint8_t *listbuf, ++ uint32_t outlen, uint32_t *readlen) ++{ ++ uint32_t *output = (uint32_t *)storage_share_out_base; ++ uint64_t ret; ++ ++ ret = bl31_storage_ops(SECURITY_KEY_LIST); ++ if (ret == RET_OK) { ++ if (*output > outlen) ++ *readlen = outlen; ++ else ++ *readlen = *output; ++ memcpy(listbuf, (uint8_t *)(output+1), *readlen); ++ } ++ return ret; ++} ++ ++static uint64_t bl31_storage_remove(uint8_t *keyname) ++{ ++ uint32_t *input = (uint32_t *)storage_share_in_base; ++ uint32_t namelen; ++ uint8_t *name; ++ ++ namelen = strlen((const char *)keyname); ++ *input++ = namelen; ++ name = (uint8_t *)input; ++ memcpy(name, keyname, namelen); ++ return bl31_storage_ops(SECURITY_KEY_REMOVE); ++} ++ ++static inline int32_t smc_to_ns_errno(uint64_t errno) ++{ ++ int32_t ret = (int32_t)(errno&0xffffffff); ++ return ret; ++} ++ ++void secure_storage_init(void) ++{ ++ storage_share_in_base = ++ bl31_storage_ops(GET_SHARE_STORAGE_IN_BASE); ++ storage_share_out_base = ++ bl31_storage_ops(GET_SHARE_STORAGE_OUT_BASE); ++ storage_share_block_base = ++ bl31_storage_ops(GET_SHARE_STORAGE_BLOCK_BASE); ++ storage_share_block_size = ++ bl31_storage_ops(GET_SHARE_STORAGE_BLOCK_SIZE); ++ ++ if (storage_share_in_base == SMC_UNK ++ || storage_share_out_base == SMC_UNK ++ || storage_share_block_base == SMC_UNK ++ || storage_share_block_size == SMC_UNK) ++ storage_init_status = -1; ++ else ++ storage_init_status = 1; ++} ++ ++void *secure_storage_getbuffer(uint32_t *size) ++{ ++ if (storage_init_status == 0) ++ secure_storage_init(); ++ ++ if (storage_init_status == 1) { ++ storage_share_block_size = ++ bl31_storage_ops(GET_SHARE_STORAGE_BLOCK_SIZE); ++ *size = (uint32_t)storage_share_block_size; ++ return (void *)storage_share_block_base; ++ } ++ else { ++ *size = 0; ++ return NULL; ++ } ++} ++void secure_storage_notifier(void) ++{ ++ bl31_storage_ops(SECURITY_KEY_NOTIFY); ++} ++ ++void secure_storage_notifier_ex(uint32_t storagesize, uint32_t rsvarg) ++{ ++ bl31_storage_ops3(SECURITY_KEY_NOTIFY_EX, storagesize, rsvarg); ++} ++ ++int32_t secure_storage_write(uint8_t *keyname, uint8_t *keybuf, ++ uint32_t keylen, uint32_t keyattr) ++{ ++ uint32_t ret; ++ ++ if (storage_init_status == 0) ++ secure_storage_init(); ++ ++ if (storage_init_status == 1) ++ ret = bl31_storage_write(keyname, keybuf, keylen, keyattr); ++ else ++ ret = RET_EUND; ++ return smc_to_ns_errno(ret); ++} ++ ++int32_t secure_storage_read(uint8_t *keyname, uint8_t *keybuf, ++ uint32_t keylen, uint32_t *readlen) ++{ ++ uint64_t ret; ++ if (storage_init_status == 0) ++ secure_storage_init(); ++ ++ if (storage_init_status == 1) ++ ret = bl31_storage_read(keyname, keybuf, keylen, readlen); ++ else ++ ret = RET_EUND; ++ ++ return smc_to_ns_errno(ret); ++} ++ ++int32_t secure_storage_query(uint8_t *keyname, uint32_t *retval) ++{ ++ uint64_t ret; ++ if (storage_init_status == 0) ++ secure_storage_init(); ++ ++ if (storage_init_status == 1) ++ ret = bl31_storage_query(keyname, retval); ++ else ++ ret = RET_EUND; ++ ++ return smc_to_ns_errno(ret); ++} ++ ++int32_t secure_storage_status(uint8_t *keyname, uint32_t *retval) ++{ ++ uint64_t ret; ++ if (storage_init_status == 0) ++ secure_storage_init(); ++ ++ if (storage_init_status == 1) ++ ret = bl31_storage_status(keyname, retval); ++ else ++ ret = RET_EUND; ++ ++ return smc_to_ns_errno(ret); ++} ++ ++int32_t secure_storage_tell(uint8_t *keyname, uint32_t *retval) ++{ ++ uint64_t ret; ++ if (storage_init_status == 0) ++ secure_storage_init(); ++ ++ if (storage_init_status == 1) ++ ret = bl31_storage_tell(keyname, retval); ++ else ++ ret = RET_EUND; ++ ++ return smc_to_ns_errno(ret); ++} ++ ++int32_t secure_storage_verify(uint8_t *keyname, uint8_t *hashbuf) ++{ ++ uint64_t ret; ++ if (storage_init_status == 0) ++ secure_storage_init(); ++ ++ if (storage_init_status == 1) ++ ret = bl31_storage_verify(keyname, hashbuf); ++ else ++ ret = RET_EUND; ++ ++ return smc_to_ns_errno(ret); ++} ++ ++int32_t secure_storage_list(uint8_t *listbuf, ++ uint32_t buflen, uint32_t *readlen) ++{ ++ uint64_t ret; ++ if (storage_init_status == 0) ++ secure_storage_init(); ++ ++ if (storage_init_status == 1) ++ ret = bl31_storage_list(listbuf, buflen, readlen); ++ else ++ ret = RET_EUND; ++ ++ return smc_to_ns_errno(ret); ++} ++ ++int32_t secure_storage_remove(uint8_t *keyname) ++{ ++ uint64_t ret; ++ if (storage_init_status == 0) ++ secure_storage_init(); ++ ++ if (storage_init_status == 1) ++ ret = bl31_storage_remove(keyname); ++ else ++ ret = RET_EUND; ++ ++ return smc_to_ns_errno(ret); ++} ++ ++void secure_storage_set_info(uint32_t info) ++{ ++ register uint64_t x0 asm("x0")= SET_STORAGE_INFO; ++ register uint64_t x1 asm("x1") = info; ++ asm volatile( ++ __asmeq("%0", "x0") ++ __asmeq("%1", "x1") ++ "smc #0\n" ++ : :"r" (x0), "r"(x1)); ++ ++} ++ ++int32_t secure_storage_set_enctype(uint32_t type) ++{ ++ uint64_t ret; ++ ret = bl31_storage_ops2(SECURITY_KEY_SET_ENCTYPE, type); ++ return smc_to_ns_errno(ret); ++} ++ ++int32_t secure_storage_get_enctype(void) ++{ ++ uint64_t ret; ++ ret = bl31_storage_ops(SECURITY_KEY_GET_ENCTYPE); ++ return smc_to_ns_errno(ret); ++} ++ ++int32_t secure_storage_version(void) ++{ ++ uint64_t ret; ++ ret = bl31_storage_ops(SECURITY_KEY_VERSION); ++ return smc_to_ns_errno(ret); ++} +diff --git a/drivers/amlogic/storagekey/storagekey.c b/drivers/amlogic/storagekey/storagekey.c +new file mode 100644 +index 00000000000..646ad3f0ded +--- /dev/null ++++ b/drivers/amlogic/storagekey/storagekey.c +@@ -0,0 +1,587 @@ ++/* ++ * drivers/storagekey/storagekey.c ++ * ++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++*/ ++ ++/* extern from bl31 */ ++/* ++ * when RET_OK ++ * query: retval=1: key exsit,=0: key not exsitï¼› ++ * tell: retvak = key size ++ * status: retval=1: secure, retval=0: non-secure ++ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_STORE_COMPATIBLE ++#include ++#endif ++#include "normal_key.h" ++ ++/* key buffer status */ ++/* bit0, dirty flag*/ ++#define KEYBUFFER_CLEAN (0 << 0) ++#define KEYBUFFER_DIRTY (1 << 0) ++#define SECUESTORAGE_HEAD_SIZE (256) ++#define SECUESTORAGE_WHOLE_SIZE (0x40000) ++ ++struct storagekey_info_t { ++ uint8_t * buffer; ++ uint32_t size; ++ uint32_t status; ++}; ++ ++static struct storagekey_info_t storagekey_info = { ++ .buffer = NULL, ++ /* default size */ ++ .size = SECUESTORAGE_WHOLE_SIZE, ++ .status = KEYBUFFER_CLEAN, ++}; ++ ++/** ++ *1.init ++ * return ok 0, fail 1 ++ */ ++static int32_t _amlkey_init(uint8_t *seed, uint32_t len, int encrypt_type) ++{ ++ int32_t ret = 0; ++ uint32_t buffer_size, actual_size; ++ ++ /* do nothing for now*/ ++ printf("%s() enter!\n", __func__); ++ if (storagekey_info.buffer != NULL) { ++ printf("%s() %d: already init!\n", __func__, __LINE__); ++ goto _out; ++ } ++ ++ /* get buffer from bl31 */ ++ storagekey_info.buffer = secure_storage_getbuffer(&buffer_size); ++ if (storagekey_info.buffer == NULL) { ++ printf("%s() %d: can't get buffer from bl31!\n", ++ __func__, __LINE__); ++ ret = -1; ++ goto _out; ++ } ++ ++ if (encrypt_type == -1) ++ encrypt_type = 0; ++ secure_storage_set_enctype(encrypt_type); ++ actual_size = store_rsv_size("key"); ++ printf("%s %d actual_size: 0x%x\n", __func__, __LINE__, ++ actual_size); ++ ++ storagekey_info.size = min_t(uint32_t, actual_size, buffer_size); ++ ret = store_rsv_read("key", storagekey_info.size, storagekey_info.buffer); ++ /* When the key is invalid at the first burn, it should be initialized again. */ ++ if (ret == RSV_UNVAIL) ++ ret = 0; ++ if (ret) { ++ printf("amlkey init rsv read key faill\n"); ++ /* memset head info for bl31 */ ++ memset(storagekey_info.buffer, 0, SECUESTORAGE_HEAD_SIZE); ++ ret = 0; ++ goto _out; ++ } ++ ++ secure_storage_notifier_ex(storagekey_info.size, 0); ++ ++ storagekey_info.buffer = secure_storage_getbuffer(&buffer_size); ++ if (buffer_size != storagekey_info.size) { ++ ret = -1; ++ goto _out; ++ } ++ ++#ifdef CONFIG_STORE_COMPATIBLE ++ info_disprotect &= ~DISPROTECT_KEY; //protect ++#endif ++_out: ++ return ret; ++} ++ ++/** ++ *2. query if the key already programmed ++ * return: exsit 1, non 0 ++ */ ++static int32_t _amlkey_isexsit(const uint8_t * name) ++{ ++ int32_t ret = 0; ++ uint32_t retval; ++ ++ if ( NULL == name ) { ++ printf("%s() %d, invalid key ", __func__, __LINE__); ++ return 0; ++ } ++ ++ ret = secure_storage_query((uint8_t *)name, &retval); ++ if (ret) { ++ printf("%s() %d: ret %d\n", __func__, __LINE__, ret); ++ retval = 0; ++ } ++ ++ return (int32_t)retval; ++} ++ ++static uint32_t _amlkey_get_attr(const uint8_t * name) ++{ ++ int32_t ret = 0; ++ uint32_t retval; ++ ++ if ( NULL == name ) { ++ printf("%s() %d, invalid key ", __func__, __LINE__); ++ return 0; ++ } ++ ++ ret = secure_storage_status((uint8_t *)name, &retval); ++ if (ret) { ++ printf("%s() %d: ret %d\n", __func__, __LINE__, ret); ++ retval = 0; ++ } ++ ++ return retval; ++} ++ ++/** ++ * 3.1 query if the prgrammed key is secure. key must exsit! ++ * return secure 1, non 0; ++ */ ++int32_t amlkey_issecure(const uint8_t * name) ++{ ++ return (amlkey_get_attr(name)&UNIFYKEY_ATTR_SECURE_MASK); ++} ++ ++/** ++ * 3.2 query if the prgrammed key is encrypt ++ * return encrypt 1, non-encrypt 0; ++ */ ++int32_t amlkey_isencrypt(const uint8_t * name) ++{ ++ return (amlkey_get_attr(name)&UNIFYKEY_ATTR_ENCRYPT_MASK); ++} ++/** ++ * 4. actual bytes of key value ++ * return actual size. ++ */ ++static ssize_t _amlkey_size(const uint8_t *name) ++{ ++ ssize_t size = 0; ++ int32_t ret = 0; ++ uint32_t retval; ++ ++ if ( NULL == name ) { ++ printf("%s() %d, invalid key ", __func__, __LINE__); ++ return 0; ++ } ++ ++ ret = secure_storage_tell((uint8_t *)name, &retval); ++ if (ret) { ++ printf("%s() %d: ret %d\n", __func__, __LINE__, ret); ++ retval = 0; ++ } ++ size = (ssize_t)retval; ++ return size; ++} ++ ++/** ++ *5. read non-secure key in bytes, return bytes readback actully. ++ * return actual size read back. ++ */ ++static ssize_t _amlkey_read(const uint8_t *name, uint8_t *buffer, uint32_t len) ++{ ++ int32_t ret = 0; ++ ssize_t retval = 0; ++ uint32_t actul_len; ++ ++ if ( NULL == name ) { ++ printf("%s() %d, invalid key ", __func__, __LINE__); ++ return 0; ++ } ++ ret = secure_storage_read((uint8_t *)name, buffer, len, &actul_len); ++ if (ret) { ++ printf("%s() %d: return %d\n", __func__, __LINE__, ret); ++ retval = 0; ++ goto _out; ++ } ++ retval = actul_len; ++_out: ++ return retval; ++} ++ ++/** ++ * 6.write secure/non-secure key in bytes , return bytes readback actully ++ * attr: bit0, secure/non-secure; ++ * bit8, encrypt/non-encrypt; ++ * return actual size write down. ++ */ ++static ssize_t _amlkey_write(const uint8_t *name, uint8_t *buffer, uint32_t len, uint32_t attr) ++{ ++ int32_t ret = 0; ++ ssize_t retval = 0; ++ uint32_t actual_size; ++ ++ if ( NULL == name ) { ++ printf("%s() %d, invalid key ", __func__, __LINE__); ++ return retval; ++ } ++ ret = secure_storage_write((uint8_t *)name, buffer, len, attr); ++ if (ret) { ++ printf("%s() %d: return %d\n", __func__, __LINE__, ret); ++ retval = 0; ++ goto _out; ++ } else { ++ retval = (ssize_t)len; ++ /* write down! */ ++ if (storagekey_info.buffer != NULL) { ++ ret = store_rsv_write("key", storagekey_info.size, storagekey_info.buffer); ++ if (ret) { ++ printf("%s() %d, store_key_write fail\n", ++ __func__, __LINE__); ++ retval = 0; ++ } ++ actual_size = storagekey_info.size; ++ } ++ } ++_out: ++ return retval; ++} ++/** ++ * 7. get the hash value of programmed secure key | 32bytes length, sha256 ++ * return success 0, fail -1 ++ */ ++static int32_t _amlkey_hash_4_secure(const uint8_t * name, uint8_t * hash) ++{ ++ int32_t ret = 0; ++ ++ ret = secure_storage_verify((uint8_t *)name, hash); ++ ++ return ret; ++} ++ ++/** ++ * 7. del key by name ++ * return success 0, fail -1 ++ */ ++static int32_t _amlkey_del(const uint8_t * name) ++{ ++ int32_t ret = 0; ++ uint32_t actual_size; ++ ++ ret = secure_storage_remove((uint8_t *)name); ++ if ((ret == 0) && (storagekey_info.buffer != NULL)) { ++ /* flush back */ ++ ret = store_rsv_write("key", storagekey_info.size, storagekey_info.buffer); ++ if (ret) { ++ printf("%s() %d, store_key_write fail\n", ++ __func__, __LINE__); ++ } ++ } else { ++ printf("%s() %d, remove key fail\n", ++ __func__, __LINE__); ++ } ++ ++ return ret; ++} ++ ++ ++ ++#define DEFINE_MUTEX(...) ++#define mutex_lock(...) ++#define mutex_unlock(...) ++#define PAGE_ALIGNED(a) (((a)&0xFFF)==0) ++#undef pr_info ++#define pr_info(fmt ...) printf("[KM]Msg:"fmt) ++#undef pr_err ++#define pr_err(fmt ...) printf("[KM]Error:f[%s]L%d:", __func__, __LINE__),printf(fmt) ++ ++#define DEF_NORMAL_BLOCK_SIZE (256 * 1024) ++//static DEFINE_MUTEX(normalkey_lock); ++static uint32_t normal_blksz = DEF_NORMAL_BLOCK_SIZE; ++static uint32_t normal_flashsize = DEF_NORMAL_BLOCK_SIZE; ++static uint8_t *normal_block; ++ ++static int _store_key_read(uint8_t * buffer, uint32_t length, uint32_t *actual_lenth) ++{ ++ int ret; ++ uint32_t actual_size; ++ actual_size = store_rsv_size("key"); ++ if (actual_size <= 1024) ++ return -1; ++ ++ length = min_t(uint32_t, actual_size, length); ++ ret = store_rsv_read("key", length, buffer); ++ /* When the key is invalid at the first burn, it should be initialized again. */ ++ if (ret && ret != RSV_UNVAIL) { ++ printf("amlkey init rsv read key faill\n"); ++ return -1; ++ } ++ if (actual_lenth) ++ *actual_lenth = length; ++ return 0; ++} ++static int _store_key_write(uint8_t * buffer, uint32_t length, uint32_t *actual_lenth) ++{ ++ int32_t ret; ++ ret = store_rsv_write("key", length, buffer); ++ if (ret) ++ return -1; ++ if (actual_lenth) ++ *actual_lenth = length; ++ return 0; ++} ++ ++static int32_t _amlkey_init_normal(uint8_t *seed, uint32_t len, int encrypt_type) ++{ ++ static int inited = 0; ++ int ret; ++ ++ if (inited) ++ return 0; ++ inited = 1; ++ ++ if (!normal_block) ++ return -1; ++ ++ if (normalkey_init()) ++ return -1; ++ ++ mutex_lock(&normalkey_lock); ++ ret = _store_key_read(normal_block, ++ normal_blksz, ++ &normal_flashsize); ++ if (ret) { ++ pr_err("read storage fail\n"); ++ goto finish; ++ } ++ ++ ret = normalkey_readfromblock(normal_block, normal_flashsize); ++ if (ret) { ++ pr_err("init block key fail\n"); ++ goto finish; ++ } ++ ++#ifdef CONFIG_STORE_COMPATIBLE ++ info_disprotect &= ~DISPROTECT_KEY; //protect ++#endif ++ ret = 0; ++finish: ++ if (ret) ++ normalkey_deinit(); ++ mutex_unlock(&normalkey_lock); ++ ++ return ret; ++} ++ ++static int32_t _amlkey_exist_normal(const uint8_t *name) ++{ ++ struct storage_object *obj; ++ ++ mutex_lock(&normalkey_lock); ++ obj = normalkey_get(name); ++ mutex_unlock(&normalkey_lock); ++ ++ return !!obj; ++} ++ ++static uint32_t _amlkey_get_attr_normal(const uint8_t *name) ++{ ++ uint32_t attr = 0; ++ struct storage_object *obj; ++ ++ mutex_lock(&normalkey_lock); ++ obj = normalkey_get(name); ++ if (obj) ++ attr = obj->attribute; ++ mutex_unlock(&normalkey_lock); ++ ++ return attr; ++} ++ ++static ssize_t _amlkey_size_normal(const uint8_t *name) ++{ ++ unsigned int size = 0; ++ struct storage_object *obj; ++ ++ mutex_lock(&normalkey_lock); ++ obj = normalkey_get(name); ++ if (obj) ++ size = obj->datasize; ++ mutex_unlock(&normalkey_lock); ++ ++ return size; ++} ++ ++static ssize_t _amlkey_read_normal(const uint8_t *name, uint8_t *buffer, uint32_t len) ++{ ++ unsigned int size = 0; ++ struct storage_object *obj; ++ ++ mutex_lock(&normalkey_lock); ++ obj = normalkey_get(name); ++ if (obj && len >= obj->datasize) { ++ size = obj->datasize; ++ memcpy(buffer, obj->dataptr, size); ++ } ++ mutex_unlock(&normalkey_lock); ++ ++ return size; ++} ++ ++static ssize_t _amlkey_write_normal(const uint8_t *name, uint8_t *buffer, ++ uint32_t len, uint32_t attr) ++{ ++ int ret; ++ uint32_t wrtsz = 0; ++ ++ if (attr & OBJ_ATTR_SECURE) { ++ pr_err("can't write secure key\n"); ++ return 0; ++ } ++ ++ mutex_lock(&normalkey_lock); ++ ret = normalkey_add(name, buffer, len, attr); ++ if (ret) { ++ pr_err("write key fail\n"); ++ ret = 0; ++ goto unlock; ++ } ++ ++ ret = normalkey_writetoblock(normal_block, normal_flashsize); ++ if (ret) { ++ pr_err("write block fail\n"); ++ ret = 0; ++ goto unlock; ++ } ++ ++ ret = _store_key_write(normal_block, ++ normal_flashsize, ++ &wrtsz); ++ if (ret) { ++ pr_err("write storage fail\n"); ++ ret = 0; ++ goto unlock; ++ } ++ ret = len; ++unlock: ++ mutex_unlock(&normalkey_lock); ++ return ret; ++} ++ ++static int32_t _amlkey_hash_normal(const uint8_t *name, uint8_t *hash) ++{ ++ int ret = -1; ++ struct storage_object *obj; ++ ++ mutex_lock(&normalkey_lock); ++ obj = normalkey_get(name); ++ if (obj) { ++ ret = 0; ++ memcpy(hash, obj->hashptr, 32); ++ } ++ mutex_unlock(&normalkey_lock); ++ ++ return ret; ++} ++ ++int normal_key_init(const void* dt_addr) ++{ ++ uint32_t blksz = 0; ++ int nodeoffset; ++ char *pblksz; ++ ++ if (!dt_addr || fdt_check_header(dt_addr)!= 0) { ++ goto blkalloc; ++ } ++ ++ nodeoffset = fdt_path_offset(dt_addr, "/unifykey"); ++ if (nodeoffset < 0) { ++ goto blkalloc; ++ } ++ ++ pblksz = (char*)fdt_getprop((const void *)dt_addr, nodeoffset, "blocksize",NULL); ++ if (pblksz) { ++ blksz = be32_to_cpup((unsigned int*)pblksz); ++ } ++ ++ if (blksz && PAGE_ALIGNED(blksz)) { ++ normal_blksz = blksz; ++ pr_info("block size from config: %x\n", blksz); ++ } ++ ++blkalloc: ++ normal_block = malloc(normal_blksz); ++ if (!normal_block) { ++ pr_err("malloc block buffer fail: %x\n", normal_blksz); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++enum amlkey_if_type { ++ IFTYPE_SECURE_STORAGE, ++ IFTYPE_NORMAL_STORAGE, ++ IFTYPE_MAX ++}; ++ ++struct amlkey_if amlkey_ifs[] = { ++ [IFTYPE_SECURE_STORAGE] = { ++ .init = _amlkey_init, ++ .exsit = _amlkey_isexsit, ++ .get_attr = _amlkey_get_attr, ++ .size = _amlkey_size, ++ .read = _amlkey_read, ++ .write = _amlkey_write, ++ .hash = _amlkey_hash_4_secure, ++ }, ++ [IFTYPE_NORMAL_STORAGE] = { ++ .init = _amlkey_init_normal, ++ .exsit = _amlkey_exist_normal, ++ .get_attr = _amlkey_get_attr_normal, ++ .size = _amlkey_size_normal, ++ .read = _amlkey_read_normal, ++ .write = _amlkey_write_normal, ++ .hash = _amlkey_hash_normal, ++ } ++}; ++ ++struct amlkey_if *amlkey_if = &amlkey_ifs[IFTYPE_SECURE_STORAGE]; ++int amlkey_if_init(const void* dt_addr) ++{ ++ static int inited = 0; ++ uint32_t buffer_size; ++ int ret = 0; ++ ++ if (inited) ++ return 0; ++ inited = 1; ++ ++ if (secure_storage_getbuffer(&buffer_size)) { ++ amlkey_if = &amlkey_ifs[IFTYPE_SECURE_STORAGE]; ++ return ret; ++ } ++ ++ pr_info("normal key used!\n"); ++ ret = normal_key_init(dt_addr); ++ amlkey_if = &amlkey_ifs[IFTYPE_NORMAL_STORAGE]; ++ ++ return ret; ++} +diff --git a/drivers/efuse/Kconfig b/drivers/efuse/Kconfig +new file mode 100644 +index 00000000000..3ee40478a11 +--- /dev/null ++++ b/drivers/efuse/Kconfig +@@ -0,0 +1,4 @@ ++config EFUSE ++ bool "AML EFUSE Support" ++ help ++ Enable support for the Amlogic EFUSE controller. +diff --git a/drivers/efuse/Makefile b/drivers/efuse/Makefile +new file mode 100644 +index 00000000000..62ab0325baf +--- /dev/null ++++ b/drivers/efuse/Makefile +@@ -0,0 +1,9 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++ ++obj-$(CONFIG_EFUSE) += aml_efuse.o ++ ++obj-$(CONFIG_EFUSE) += efuse.o ++ ++obj-$(CONFIG_EFUSE) += efuse_usr_space_api.o ++ ++obj-$(CONFIG_EFUSE) += bl31_apis.o +diff --git a/drivers/efuse/aml_efuse.c b/drivers/efuse/aml_efuse.c +new file mode 100644 +index 00000000000..a553a201f71 +--- /dev/null ++++ b/drivers/efuse/aml_efuse.c +@@ -0,0 +1,123 @@ ++/* ++ * Copyright (C) 2014-2018 Amlogic, Inc. All rights reserved. ++ * ++ * All information contained herein is Amlogic confidential. ++ * ++ * This software is provided to you pursuant to Software License Agreement ++ * (SLA) with Amlogic Inc ("Amlogic"). This software may be used ++ * only in accordance with the terms of this agreement. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification is strictly prohibited without prior written permission from ++ * Amlogic. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++/* ++ * ++ * Copyright (C) 2018 Amlogic, Inc. All rights reserved. ++*/ ++ ++#include ++#include ++#include ++#include ++ ++//weak function for EFUSE license query ++//all following functions are defined with "weak" for customization of each SoC ++//EFUSE_LICX --> AO_SEC_SD_CFG10/9 --> EFUSE mirror ++int __attribute__((weak)) IS_FEAT_BOOT_VERIFY(void) ++{ ++ #ifndef ADDR_IS_FEAT_BOOT_VERIFY ++ #ifdef EFUSE_LIC0 ++ #define ADDR_IS_FEAT_BOOT_VERIFY (EFUSE_LIC0) ++ #define OSET_IS_FEAT_BOOT_VERIFY (0) ++ #elif defined(OTP_LIC0) ++ #define ADDR_IS_FEAT_BOOT_VERIFY (OTP_LIC0) ++ #define OSET_IS_FEAT_BOOT_VERIFY (0) ++ #else ++ #define ADDR_IS_FEAT_BOOT_VERIFY (AO_SEC_SD_CFG10) ++ #define OSET_IS_FEAT_BOOT_VERIFY (4) ++ #endif ++ #endif ++ ++ return ((readl(ADDR_IS_FEAT_BOOT_VERIFY) >> OSET_IS_FEAT_BOOT_VERIFY) & 1); ++ ++ #undef ADDR_IS_FEAT_BOOT_VERIFY ++ #undef OSET_IS_FEAT_BOOT_VERIFY ++} ++int __attribute__((weak)) IS_FEAT_BOOT_ENCRYPT(void) ++{ ++ #ifndef ADDR_IS_FEAT_BOOT_ENCRYPT ++ #ifdef EFUSE_LIC0 ++ #define ADDR_IS_FEAT_BOOT_ENCRYPT (EFUSE_LIC0) ++ #define OSET_IS_FEAT_BOOT_ENCRYPT (1) ++ #elif defined(OTP_LIC0) ++ #define ADDR_IS_FEAT_BOOT_ENCRYPT (OTP_LIC0) ++ #define OSET_IS_FEAT_BOOT_ENCRYPT (1) ++ #else ++ #define ADDR_IS_FEAT_BOOT_ENCRYPT (AO_SEC_SD_CFG10) ++ #define OSET_IS_FEAT_BOOT_ENCRYPT (28) ++ #endif ++ #endif ++ ++ return ((readl(ADDR_IS_FEAT_BOOT_ENCRYPT) >> OSET_IS_FEAT_BOOT_ENCRYPT) & 1); ++ ++ #undef ADDR_IS_FEAT_BOOT_ENCRYPT ++ #undef OSET_IS_FEAT_BOOT_ENCRYPT ++} ++ ++int __attribute__((weak)) IS_FEAT_DIS_EMMC_USER(void) ++{ ++ return 0; ++} ++ ++int __attribute__((weak)) IS_FEAT_DIS_EMMC_BOOT_0(void) ++{ ++ return 0; ++} ++ ++int __attribute__((weak)) IS_FEAT_DIS_EMMC_BOOT_1(void) ++{ ++ return 0; ++} ++ ++int __attribute__((weak)) IS_FEAT_EN_4BL2_SNOR(void) ++{ ++ return 0; ++} ++ ++int __attribute__((weak)) IS_FEAT_DIS_NBL2_SNOR(void) ++{ ++ return 0; ++} ++ ++int __attribute__((weak)) IS_FEAT_EN_8BL2_SNAND(void) ++{ ++ return 0; ++} ++ ++int __attribute__((weak)) IS_FEAT_DIS_NBL2_SNAND(void) ++{ ++ return 0; ++} ++ ++int __attribute__((weak)) IS_FEAT_DIS_8BL2_NAND(void) ++{ ++ return 0; ++} ++ ++int __attribute__((weak)) IS_FEAT_DIS_NBL2_NAND(void) ++{ ++ return 1; ++} +diff --git a/drivers/efuse/bl31_apis.c b/drivers/efuse/bl31_apis.c +new file mode 100644 +index 00000000000..18f6fc69683 +--- /dev/null ++++ b/drivers/efuse/bl31_apis.c +@@ -0,0 +1,474 @@ ++/* ++ * arch/arm/cpu/armv8/txlx/bl31_apis.c ++ * ++ * Copyright (C) 2014-2017 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++ */ ++ ++/* ++ * Trustzone API ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static long sharemem_input_base; ++static long sharemem_output_base; ++ ++long get_sharemem_info(unsigned long function_id) ++{ ++ asm volatile( ++ __asmeq("%0", "x0") ++ "smc #0\n" ++ : "+r" (function_id)); ++ ++ return function_id; ++} ++ ++int32_t set_boot_params(const keymaster_boot_params *boot_params) ++{ ++ const unsigned cmd = SET_BOOT_PARAMS; ++ ++ if (!boot_params) ++ return -1; ++ ++ if (!sharemem_input_base) ++ sharemem_input_base = ++ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE); ++ ++ memcpy((void *)sharemem_input_base, ++ (const void *)boot_params, sizeof(keymaster_boot_params)); ++ ++ asm __volatile__("" : : : "memory"); ++ register uint64_t x0 asm("x0") = cmd; ++ register uint64_t x1 asm("x1") = sizeof(keymaster_boot_params); ++ do { ++ asm volatile( ++ __asmeq("%0", "x0") ++ __asmeq("%1", "x0") ++ __asmeq("%2", "x1") ++ "smc #0\n" ++ : "=r"(x0) ++ : "r"(x0), "r"(x1)); ++ } while (0); ++ ++ return (!x0)? -1: 0; ++} ++ ++#ifdef CONFIG_EFUSE ++int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg) ++{ ++ int ret; ++ unsigned cmd, offset, size; ++ unsigned long *retcnt = (unsigned long *)(arg->retcnt_phy); ++ ++ if (!sharemem_input_base) ++ sharemem_input_base = ++ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE); ++ if (!sharemem_output_base) ++ sharemem_output_base = ++ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE); ++ ++ if (arg->cmd == EFUSE_HAL_API_READ) ++ cmd = EFUSE_READ; ++ else if (arg->cmd == EFUSE_HAL_API_WRITE) ++ cmd = EFUSE_WRITE; ++ else ++ cmd = EFUSE_WRITE_PATTERN; ++ offset = arg->offset; ++ size = arg->size; ++ ++ if (arg->cmd == EFUSE_HAL_API_WRITE) ++ memcpy((void *)sharemem_input_base, ++ (const void *)arg->buffer_phy, size); ++ asm __volatile__("" : : : "memory"); ++ ++ register uint64_t x0 asm("x0") = cmd; ++ register uint64_t x1 asm("x1") = offset; ++ register uint64_t x2 asm("x2") = size; ++ do { ++ asm volatile( ++ __asmeq("%0", "x0") ++ __asmeq("%1", "x0") ++ __asmeq("%2", "x1") ++ __asmeq("%3", "x2") ++ "smc #0\n" ++ : "=r"(x0) ++ : "r"(x0), "r"(x1), "r"(x2)); ++ } while (0); ++ ret = x0; ++ *retcnt = x0; ++ ++ if ((arg->cmd == EFUSE_HAL_API_READ) && (ret != 0)) ++ memcpy((void *)arg->buffer_phy, ++ (const void *)sharemem_output_base, ret); ++ ++ if (!ret) ++ return -1; ++ else ++ return 0; ++} ++ ++int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg) ++{ ++ int32_t ret; ++ unsigned cmd; ++ ++ if (arg->cmd == EFUSE_HAL_API_USER_MAX) ++ cmd = EFUSE_USER_MAX; ++ ++ asm __volatile__("" : : : "memory"); ++ ++ register uint64_t x0 asm("x0") = cmd; ++ ++ do { ++ asm volatile( ++ __asmeq("%0", "x0") ++ __asmeq("%1", "x0") ++ "smc #0\n" ++ : "=r"(x0) ++ : "r"(x0)); ++ } while (0); ++ ret = x0; ++ ++ if (!ret) ++ return -1; ++ else ++ return ret; ++} ++ ++ssize_t meson_trustzone_efuse_writepattern(const char *buf, size_t count) ++{ ++ struct efuse_hal_api_arg arg; ++ unsigned long retcnt; ++ ++ if (count != EFUSE_BYTES) ++ return 0; /* Past EOF */ ++ ++ arg.cmd = EFUSE_HAL_API_WRITE_PATTERN; ++ arg.offset = 0; ++ arg.size = count; ++ arg.buffer_phy = (unsigned long)buf; ++ arg.retcnt_phy = (unsigned long)&retcnt; ++ int ret; ++ ret = meson_trustzone_efuse(&arg); ++ return ret; ++} ++#endif ++ ++uint64_t meson_trustzone_efuse_check(unsigned char *addr) ++{ ++ uint64_t ret = 0; ++ struct sram_hal_api_arg arg = {}; ++ ++ arg.cmd = SRAM_HAL_API_CHECK_EFUSE; ++ arg.req_len = 0x1000000; ++ arg.res_len = 0; ++ arg.req_phy_addr = (unsigned long)addr; ++ arg.res_phy_addr = (unsigned long)NULL; ++ ++ asm __volatile__("" : : : "memory"); ++ ++ register uint64_t x0 asm("x0") = CALL_TRUSTZONE_HAL_API; ++ register uint64_t x1 asm("x1") = TRUSTZONE_HAL_API_SRAM; ++ register uint64_t x2 asm("x2") = (unsigned long)(&arg); ++ do { ++ asm volatile( ++ __asmeq("%0", "x0") ++ __asmeq("%1", "x0") ++ __asmeq("%2", "x1") ++ __asmeq("%3", "x2") ++ "smc #0\n" ++ : "=r"(x0) ++ : "r"(x0), "r"(x1), "r"(x2)); ++ } while (0); ++ ++ ret = x0; ++ ++ return ret; ++} ++ ++void debug_efuse_cmd(unsigned long cmd) ++{ ++ asm volatile( ++ __asmeq("%0", "x0") ++ "smc #0\n" ++ : : "r" (cmd)); ++} ++ ++void bl31_debug_efuse_write_pattern(const char *buf) ++{ ++ if (!sharemem_input_base) ++ sharemem_input_base = ++ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE); ++ memcpy((void *)sharemem_input_base, (const void *)buf, 512); ++ ++ debug_efuse_cmd(DEBUG_EFUSE_WRITE_PATTERN); ++} ++ ++void bl31_debug_efuse_read_pattern(char *buf) ++{ ++ if (!sharemem_output_base) ++ sharemem_output_base = ++ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE); ++ debug_efuse_cmd(DEBUG_EFUSE_READ_PATTERN); ++ ++ memcpy((void *)buf, (const void *)sharemem_output_base, 512); ++} ++ ++void aml_set_jtag_state(unsigned state, unsigned select) ++{ ++ uint64_t command; ++ if (state == JTAG_STATE_ON) ++ command = JTAG_ON; ++ else ++ command = JTAG_OFF; ++ asm __volatile__("" : : : "memory"); ++ ++ asm volatile( ++ __asmeq("%0", "x0") ++ __asmeq("%1", "x1") ++ "smc #0\n" ++ : : "r" (command), "r"(select)); ++} ++ ++unsigned aml_get_reboot_reason(void) ++{ ++ unsigned reason; ++ uint64_t ret; ++ ++ register uint64_t x0 asm("x0") = GET_REBOOT_REASON; ++ asm volatile( ++ __asmeq("%0", "x0") ++ "smc #0\n" ++ :"+r"(x0)); ++ ret = x0; ++ reason = (unsigned)(ret&0xffffffff); ++ return reason; ++} ++ ++void set_viu_probe_enable(void) ++{ ++ register uint64_t x0 asm("x0") = VIU_PREOBE_EN; ++ ++ asm volatile( ++ __asmeq("%0", "x0") ++ "smc #0\n" ++ :"+r"(x0)); ++} ++unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2) ++{ ++ register long x0 asm("x0") = function_id; ++ register long x1 asm("x1") = arg0; ++ register long x2 asm("x2") = arg1; ++ register long x3 asm("x3") = arg2; ++ asm volatile( ++ __asmeq("%0", "x0") ++ __asmeq("%1", "x1") ++ __asmeq("%2", "x2") ++ __asmeq("%3", "x3") ++ "smc #0\n" ++ : "+r" (x0) ++ : "r" (x1), "r" (x2), "r" (x3)); ++ ++ return function_id; ++} ++ ++void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2) ++{ ++ register long x0 asm("x0") = function_id; ++ register long x1 asm("x1") = arg0; ++ register long x2 asm("x2") = arg1; ++ register long x3 asm("x3") = arg2; ++ asm volatile( ++ __asmeq("%0", "x0") ++ __asmeq("%1", "x1") ++ __asmeq("%2", "x2") ++ __asmeq("%3", "x3") ++ "smc #0\n" ++ : "+r" (x0) ++ : "r" (x1), "r" (x2), "r" (x3)); ++ ++ return ; ++} ++ ++unsigned long aml_sec_boot_check(unsigned long nType, ++ unsigned long pBuffer, ++ unsigned long nLength, ++ unsigned long nOption) ++{ ++ uint64_t ret = 1; ++ ++//#define AML_SECURE_LOG_TE ++ ++#if defined(AML_SECURE_LOG_TE) ++ #define AML_GET_TE(a) do{a = *((volatile unsigned int*)0xc1109988);}while(0); ++ unsigned nT1,nT2,nT3; ++#else ++ #define AML_GET_TE(...) ++#endif ++ ++ AML_GET_TE(nT1); ++ ++ asm __volatile__("" : : : "memory"); ++ ++ register uint64_t x0 asm("x0") = AML_DATA_PROCESS; ++ register uint64_t x1 asm("x1") = nType; ++ register uint64_t x2 asm("x2") = pBuffer; ++ register uint64_t x3 asm("x3") = nLength; ++ register uint64_t x4 asm("x4") = nOption; ++ ++ do { ++ asm volatile( ++ __asmeq("%0", "x0") ++ __asmeq("%1", "x0") ++ __asmeq("%2", "x1") ++ __asmeq("%3", "x2") ++ __asmeq("%4", "x3") ++ __asmeq("%5", "x4") ++ "smc #0\n" ++ : "=r"(x0) ++ : "r"(x0), "r"(x1), "r"(x2),"r"(x3),"r"(x4)); ++ } while (0); ++ ++ ret = x0; ++ ++ AML_GET_TE(nT2);; ++ ++ flush_dcache_range((unsigned long )pBuffer, (unsigned long )pBuffer+nLength); ++ ++ AML_GET_TE(nT3); ++ ++#if defined(AML_SECURE_LOG_TE) ++ printf("aml log : dec use %d(us) , flush cache used %d(us)\n", ++ nT2 - nT1, nT3 - nT2); ++#endif ++ ++ return ret; ++} ++ ++void set_usb_boot_function(unsigned long command) ++{ ++ register long x0 asm("x0") = SET_USB_BOOT_FUNC; ++ register long x1 asm("x1") = command; ++ ++ asm volatile( ++ __asmeq("%0", "x0") ++ __asmeq("%1", "x1") ++ "smc #0\n" ++ : "+r" (x0) ++ : "r" (x1)); ++} ++ ++void aml_system_off(void) ++{ ++ /* TODO: Add poweroff capability */ ++ aml_reboot(0x82000042, 1, 0, 0); ++ aml_reboot(0x84000008, 0, 0, 0); ++} ++ ++int __get_chip_id(unsigned char *buff, unsigned int size) ++{ ++ if (buff == NULL || size < 16) ++ return -1; ++ ++ if (!sharemem_output_base) ++ sharemem_output_base = ++ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE); ++ ++ if (sharemem_output_base) { ++ register long x0 asm("x0") = GET_CHIP_ID; ++ register long x1 asm("x1") = 2; ++ ++ asm volatile( ++ __asmeq("%0", "x0") ++ __asmeq("%1", "x1") ++ "smc #0\n" ++ : "+r" (x0) ++ : "r" (x1)); ++ ++ if (x0 == 0) { ++ int version = *((unsigned int *)sharemem_output_base); ++ ++ if (version == 2) { ++ memcpy(buff, (void *)sharemem_output_base + 4, 16); ++ } ++ else { ++ /** ++ * Legacy 12-byte chip ID read out, transform data ++ * to expected order format. ++ */ ++ uint32_t chip_info = readl(P_AO_SEC_SD_CFG8); ++ uint8_t *ch; ++ int i; ++ ++ ((uint32_t *)buff)[0] = ++ ((chip_info & 0xff000000) | // Family ID ++ ((chip_info << 8) & 0xff0000) | // Chip Revision ++ ((chip_info >> 8) & 0xff00)); // Package ID ++ ++ ((uint32_t *)buff)[0] = htonl(((uint32_t *)buff)[0]); ++ ++ /* Transform into expected order for display */ ++ ch = (uint8_t *)(sharemem_output_base + 4); ++ for (i = 0; i < 12; i++) ++ buff[i + 4] = ch[11 - i]; ++ } ++ ++ return 0; ++ } ++ } ++ ++ return -1; ++} ++ ++int32_t get_avbkey_from_fip(uint8_t *buf, uint32_t buflen) ++{ ++ const unsigned cmd = GET_AVBKEY_FROM_FIP; ++ uint32_t retlen = 0; ++ uint32_t ret = 0; ++ ++ if (!buf) ++ return -1; ++ ++ if (!sharemem_output_base) ++ sharemem_output_base = ++ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE); ++ ++ asm __volatile__("" : : : "memory"); ++ register uint64_t x0 asm("x0") = cmd; ++ do { ++ asm volatile( ++ __asmeq("%0", "x0") ++ __asmeq("%1", "x0") ++ "smc #0\n" ++ : "=r"(x0) ++ : "r"(x0)); ++ } while (0); ++ ++ if (!x0) ++ ret = -1; ++ retlen = x0; ++ ++ if (ret != -1 && buflen >= retlen) ++ memcpy(buf, (const void *)sharemem_output_base, retlen); ++ ++ return ret; ++} +diff --git a/drivers/efuse/efuse.c b/drivers/efuse/efuse.c +new file mode 100644 +index 00000000000..5560bcd384c +--- /dev/null ++++ b/drivers/efuse/efuse.c +@@ -0,0 +1,141 @@ ++/* ++ * drivers/efuse/efuse.c ++ * ++ * Copyright (C) 2018 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++char efuse_buf[EFUSE_BYTES] = {0}; ++ ++ssize_t efuse_read(char *buf, size_t count, loff_t *ppos) ++{ ++ unsigned int pos = *ppos; ++ ++ struct efuse_hal_api_arg arg; ++ unsigned int retcnt; ++ int ret; ++ ++ arg.cmd = EFUSE_HAL_API_READ; ++ arg.offset = pos; ++ arg.size = count; ++ arg.buffer_phy = (unsigned long)buf; ++ arg.retcnt_phy = (unsigned long)&retcnt; ++ ret = meson_trustzone_efuse(&arg); ++ if (ret == 0) { ++ *ppos += retcnt; ++ return retcnt; ++ } else{ ++ return ret; ++ } ++} ++ ++ssize_t efuse_write(const char *buf, size_t count, loff_t *ppos) ++{ ++ unsigned int pos = *ppos; ++ ++ if ((pos & 0xffff) >= EFUSE_BYTES) ++ return 0; /* Past EOF */ ++ if (count > EFUSE_BYTES - pos) ++ count = EFUSE_BYTES - pos; ++ if (count > EFUSE_BYTES) ++ return -1; ++ ++ struct efuse_hal_api_arg arg; ++ unsigned int retcnt; ++ ++ arg.cmd = EFUSE_HAL_API_WRITE; ++ arg.offset = pos; ++ arg.size = count; ++ arg.buffer_phy = (unsigned long)buf; ++ arg.retcnt_phy = (unsigned long)&retcnt; ++ int ret; ++ ++ ret = meson_trustzone_efuse(&arg); ++ if (ret == 0) { ++ *ppos = retcnt; ++ return retcnt; ++ } else{ ++ return ret; ++ } ++} ++ ++int efuse_read_usr(char *buf, size_t count, loff_t *ppos) ++{ ++ char data[EFUSE_BYTES]; ++ char *pdata = NULL; ++ int ret; ++ loff_t pos; ++ ++ memset(data, 0, count); ++ ++ pdata = data; ++ pos = *ppos; ++ ret = efuse_read(pdata, count, (loff_t *)&pos); ++ ++ memcpy(buf, data, count); ++ ++ return ret; ++} ++ ++int efuse_write_usr(char *buf, size_t count, loff_t *ppos) ++{ ++ char data[EFUSE_BYTES]; ++ char *pdata = NULL; ++ char *penc = NULL; ++ int ret; ++ loff_t pos; ++ ++ if (count == 0) { ++ printf("data length: 0 is error!\n"); ++ return -1; ++ } ++ ++ memset(data, 0, EFUSE_BYTES); ++ memset(efuse_buf, 0, EFUSE_BYTES); ++ ++ memcpy(data, buf, count); ++ pdata = data; ++ penc = efuse_buf; ++ ++ memcpy(penc, pdata, count); ++ pos = *ppos; ++ ++ ret = efuse_write(efuse_buf, count, (loff_t *)&pos); ++ ++ return ret; ++} ++ ++uint32_t efuse_get_max(void) ++{ ++ struct efuse_hal_api_arg arg; ++ int ret; ++ ++ arg.cmd = EFUSE_HAL_API_USER_MAX; ++ ++ ret = meson_trustzone_efuse_get_max(&arg); ++ if (ret == 0) { ++ printf("ERROR: can not get efuse user max bytes!!!\n"); ++ return -1; ++ } else{ ++ return ret; ++ } ++} +diff --git a/drivers/efuse/efuse_usr_space_api.c b/drivers/efuse/efuse_usr_space_api.c +new file mode 100644 +index 00000000000..241b6d0be49 +--- /dev/null ++++ b/drivers/efuse/efuse_usr_space_api.c +@@ -0,0 +1,379 @@ ++/* ++ * \file efuse_usr_space_api.c ++ * \brief support read/write user space using keyname mode ++ * mapping keyname to offset by looking /efusekey in dtb ++ * ++ * \version 1.0.0 ++ * \date 15/07/14 ++ * \author Sam.Wu ++ * ++ * Copyright (c) 2015 Amlogic. All Rights Reserved. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define EFUSE_DBG(fmt...) //printf("[EFUSE_DBG]"fmt) ++#define EFUSE_MSG(fmt...) printf("[EFUSE_MSG]"fmt) ++#define EFUSE_ERR(fmt...) printf("[EFUSE_ERR]f(%s)L%d:", __func__, __LINE__),printf(fmt) ++ ++struct efusekey_info{ ++ char keyname[32]; ++ unsigned offset; ++ unsigned size; ++}; ++ ++static struct _efuseCfgInf{ ++ unsigned initMaigc;//magic to indicate whether inited ++ unsigned totalCfgKeyNums; ++ struct efusekey_info * pKeyInf; ++} ++_efuseKeyInfos = {.totalCfgKeyNums = 0, .pKeyInf = NULL}; ++ ++int efuse_usr_api_init_dtb(const char* dt_addr) ++{ ++ int nodeoffset, poffset = 0; ++ char propname[32]; ++ const void* phandle; ++ int ret; ++ int index; ++ uint32_t max_size; ++ unsigned efusekeynum = 0; ++ struct efusekey_info * efusekey_infos = NULL; ++ ++ ret = fdt_check_header(dt_addr); ++ if (ret < 0) { ++ EFUSE_ERR("fdt check failed [%s]\n", fdt_strerror(ret)); ++ return __LINE__; ++ } ++ _efuseKeyInfos.initMaigc = 0; ++ ++ nodeoffset = fdt_path_offset(dt_addr, "/efusekey"); ++ if (nodeoffset < 0) { ++ EFUSE_ERR("not find /efusekey node [%s].\n", fdt_strerror(nodeoffset)); ++ return __LINE__; ++ } ++ ++ phandle = fdt_getprop(dt_addr, nodeoffset, "keynum", NULL); ++ efusekeynum = be32_to_cpup((u32 *)phandle); ++ EFUSE_MSG("keynum is %x\n", efusekeynum); ++ ++ if (efusekey_infos) free(efusekey_infos) ; ++ efusekey_infos = (struct efusekey_info *)malloc(sizeof (struct efusekey_info) *efusekeynum); ++ if (!efusekey_infos) { ++ EFUSE_ERR("malloc err\n"); ++ return __LINE__; ++ } ++ ++ max_size = efuse_get_max(); ++ ++ for (index = 0; index < efusekeynum; index++) ++ { ++ struct efusekey_info* theKeyInf = efusekey_infos + index; ++ sprintf(propname, "key%d", index); ++ /* printf("%s: propname: %s\n",__func__,propname); */ ++ phandle = fdt_getprop(dt_addr, nodeoffset, propname, NULL); ++ if (!phandle) { ++ EFUSE_ERR("don't find match %s\n", propname); ++ goto err; ++ } ++ poffset = fdt_node_offset_by_phandle(dt_addr, ++ be32_to_cpup((u32 *)phandle)); ++ if (!poffset) { ++ EFUSE_ERR("can't find device node for key[%s]\n", propname); ++ goto err; ++ } ++ ++ ++ phandle = fdt_getprop(dt_addr, poffset, "keyname", NULL); ++ if (!phandle) { ++ EFUSE_ERR("Can't find keyname for key[%d]\n", index); ++ goto err; ++ } ++ strcpy(theKeyInf->keyname, phandle); ++ ++ phandle = fdt_getprop(dt_addr, poffset, "offset", NULL); ++ if (!phandle) { ++ EFUSE_ERR("Can't find offset for key[%s]\n", theKeyInf->keyname); ++ goto err; ++ } ++ theKeyInf->offset = be32_to_cpup((u32 *)phandle); ++ ++ phandle = fdt_getprop(dt_addr, poffset, "size", NULL); ++ if (!phandle) { ++ EFUSE_ERR("Can't find size for key[%s]\n", theKeyInf->keyname); ++ goto err; ++ } ++ theKeyInf->size = be32_to_cpup((u32 *)phandle); ++ ++ EFUSE_DBG("key[%02d] name=%12s, offset=0x%04x, size=0x%04x\n", ++ index, theKeyInf->keyname, theKeyInf->offset, theKeyInf->size); ++ if (theKeyInf->offset + theKeyInf->size > max_size) { ++ EFUSE_ERR("\n offset (0x%x) + size (0x%x) > max [0x%x]!\n", theKeyInf->offset, theKeyInf->size, max_size); ++ return __LINE__; ++ } ++ } ++ ++ _efuseKeyInfos.totalCfgKeyNums = efusekeynum; ++ _efuseKeyInfos.pKeyInf = efusekey_infos; ++ EFUSE_DBG("%s success!\n", __func__); ++ _efuseKeyInfos.initMaigc = 0xee; ++ return 0; ++ ++err: ++ free(efusekey_infos); ++ EFUSE_ERR("%s error!\n", __func__); ++ return -1; ++} ++ ++static int _get_cfg_key_inf_byname(const char* keyname, const struct efusekey_info ** pKeyInf) ++{ ++ int index = 0; ++ struct efusekey_info* theKeyInf = _efuseKeyInfos.pKeyInf; ++ int ret = 0; ++ ++ if (0xee != _efuseKeyInfos.initMaigc) { ++ EFUSE_ERR("Pls init first.\n"); ++ return __LINE__; ++ } ++ for (; index < _efuseKeyInfos.totalCfgKeyNums; ++index, ++theKeyInf) ++ { ++ const char* theKeyname = theKeyInf->keyname; ++ ret = strcmp(theKeyname, keyname); ++ if (ret) continue; ++ ++ *pKeyInf = theKeyInf; ++ return 0; ++ } ++ ++ EFUSE_ERR("efuse keyname(%s) not configured\n", keyname); ++ return __LINE__;//Not found the matched name ++} ++ ++int efuse_usr_api_get_cfg_key_size(const char* keyname, unsigned* pSz) ++{ ++ int ret = 0; ++ const struct efusekey_info* theCfgKeyInf = NULL; ++ ++ ret = _get_cfg_key_inf_byname(keyname, &theCfgKeyInf); ++ if (ret) { ++ EFUSE_ERR("not name cfg in dts.\n"); ++ return __LINE__; ++ } ++ ++ *pSz = theCfgKeyInf->size; ++ return 0; ++} ++ ++int efuse_usr_api_write_key(const char* keyname, const void* keydata, const unsigned dataSz) ++{ ++ int ret = 0; ++ const struct efusekey_info* theCfgKeyInf = NULL; ++ ++ ret = _get_cfg_key_inf_byname(keyname, &theCfgKeyInf); ++ if (ret) { ++ EFUSE_ERR("not name cfg in dts.\n"); ++ return __LINE__; ++ } ++ if (dataSz != theCfgKeyInf->size) { ++ EFUSE_ERR("dataSz 0x%x != cfg size 0x%x\n", dataSz, theCfgKeyInf->size); ++ return __LINE__; ++ } ++ ++ ret = efuse_write_usr((char*)keydata, theCfgKeyInf->size, (loff_t*)&theCfgKeyInf->offset); ++ if (ret < 0) { ++ EFUSE_ERR("error: efuse write fail.\n"); ++ return __LINE__; ++ } ++ ++ return 0; ++} ++ ++//usrefuse read mac $loadaddr (size) ++int efuse_usr_api_read_key(const char* keyname, void* databuf, const unsigned bufSz) ++{ ++ int ret = 0; ++ const struct efusekey_info* theCfgKeyInf = NULL; ++ loff_t offset = 0; ++ ++ ret = _get_cfg_key_inf_byname(keyname, &theCfgKeyInf); ++ if (ret) { ++ EFUSE_ERR("not name cfg in dts.\n"); ++ return __LINE__; ++ } ++ const unsigned cfgCnt = theCfgKeyInf->size; ++ if (cfgCnt > bufSz && bufSz) { ++ EFUSE_ERR("cfg size 0x%x > bufsz 0x%x\n", cfgCnt, bufSz); ++ return __LINE__; ++ } ++ EFUSE_DBG("keyname=%s, databuf=%p, bufSz=%d, cfgCnt=%u\n", keyname, databuf, bufSz, cfgCnt); ++ ++ offset = theCfgKeyInf->offset; ++ memset(databuf, cfgCnt, 0); ++ ret = efuse_read_usr((char*)databuf, cfgCnt, &offset); ++ if (ret == -1) { ++ EFUSE_ERR("ERROR: efuse read user data fail!, size=%u, offset=%llu\n", cfgCnt, offset); ++ return __LINE__; ++ } ++ ++ if (ret != cfgCnt) { ++ EFUSE_ERR("ERROR: read %d byte(s) not wanted %d byte(s) data\n", ret, cfgCnt); ++ return __LINE__; ++ } ++ ++ return 0; ++} ++ ++static int hex_ascii_to_buf(const char* input, uint8_t* buf, const unsigned bufSz) ++{ ++ int ret = 0; ++ const char* tmpStr = input; ++ const unsigned inputLen = strlen(input); ++ int i = 0; ++ ++ if (!inputLen) { ++ EFUSE_ERR("err input len 0\n"); ++ return __LINE__; ++ } ++ if ( ((inputLen>>1)<<1) != inputLen ) { ++ EFUSE_ERR("inputLen %d not even\n", inputLen); ++ return __LINE__; ++ } ++ if (bufSz * 2 > inputLen) { ++ EFUSE_ERR("bufSz %d not enough\n", bufSz); ++ return __LINE__; ++ } ++ for (tmpStr = input; *tmpStr; ++tmpStr) ++ { ++ char c = *tmpStr; ++ ret = isxdigit(c); ++ if (!ret) { ++ EFUSE_ERR("input(%s) contain non xdigit, c=%c\n", input, c); ++ return __LINE__; ++ } ++ } ++ ++ for (i = 0; i < inputLen; i += 2) ++ { ++ char tmpByte[8]; ++ tmpByte[2] = '\0'; ++ tmpByte[0] = input[i]; ++ tmpByte[1] = input[i + 1]; ++ ++ const unsigned val = simple_strtoul(tmpByte, NULL, 16); ++ if (val > 0xff) { ++ EFUSE_ERR("Exception: val 0x%x > 0xff\n", val); ++ return __LINE__; ++ } ++ buf[i>>1] = val; ++ } ++ ++ return 0; ++} ++ ++static int do_usr_efuse_api(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ int ret = 0; ++ const char* subcmd = argv[1]; ++ if (argc < 2) return CMD_RET_USAGE; ++ ++ if (!strcmp("init", subcmd)) ++ { ++ const char* dtbLoadAddr = NULL; ++ if (argc > 2) ++ { ++ dtbLoadAddr = (char*)simple_strtoul(argv[2], NULL, 0); ++ } ++ else ++ { ++ dtbLoadAddr = env_get("dtb_mem_addr"); ++ if (!dtbLoadAddr) { ++ env_set("dtb_mem_addr", simple_itoa(CFG_SYS_SDRAM_BASE + (16U<<20))); ++ } ++ dtbLoadAddr = (char*)simple_strtoul(dtbLoadAddr, NULL, 0); ++ } ++ ret = efuse_usr_api_init_dtb(dtbLoadAddr); ++ } ++ else if(!strcmp("size", subcmd)) ++ { ++ const char* keyname = argv[2]; ++ unsigned keysize = argc > 3 ? simple_strtoul(argv[3], NULL, 0) : 0; ++ ++ ret = efuse_usr_api_get_cfg_key_size(keyname, &keysize); ++ EFUSE_MSG("keysize=%d\n", keysize); ++ } ++ else if(!strcmp("read", subcmd)) ++ { ++ if (argc < 4) return CMD_RET_USAGE; ++ const char* keyname = argv[2]; ++ char* databuf = (char*)simple_strtoul(argv[3], NULL, 16); ++ unsigned bufSz = argc > 4 ? simple_strtoul(argv[4], NULL, 0) : 0; ++ ++ if (!bufSz) ++ { ++ ret = efuse_usr_api_get_cfg_key_size(keyname, &bufSz); ++ if (ret) { ++ EFUSE_ERR("Fail in get sz for key[%s]\n", keyname); ++ return __LINE__; ++ } ++ } ++ ++ ret = efuse_usr_api_read_key(keyname, databuf, bufSz); ++ if (!ret) ++ { ++ int i = 0; ++ printf("efuse read data"); ++ for (i = 0; i < bufSz; i++) { ++ if (i%8 == 0) printf("\n[0x%02x]:", i); ++ printf("%02x ", databuf[i]); ++ } ++ printf("\n"); ++ } ++ } ++ else if(!strcmp("write", subcmd)) ++ { ++ if (argc < 4) return CMD_RET_USAGE; ++ const char* keyname = argv[2]; ++ char* keydata = (char*)simple_strtoul(argv[3], NULL, 16); ++ unsigned bufSz = argc > 4 ? simple_strtoul(argv[4], NULL, 0) : 0; ++ uint8_t* tmpBuf = NULL; ++ ++ if (!bufSz) ++ { ++ const char* input = argv[3]; ++ bufSz = ( strlen(input) >> 1 ); ++ tmpBuf = malloc(bufSz); ++ ++ ret = hex_ascii_to_buf(input, tmpBuf, bufSz); ++ if (ret) { ++ EFUSE_ERR("Failed in change hex ascii to buf\n"); ++ return __LINE__; ++ } ++ keydata = (char*)tmpBuf; ++ } ++ ret = efuse_usr_api_write_key(keyname, keydata, bufSz); ++ if (tmpBuf) free(tmpBuf) ; ++ } ++ ++ return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS; ++} ++ ++U_BOOT_CMD( ++ efuse_user, ++ 5, //max argc ++ 1, //repeatable ++ do_usr_efuse_api, ++ "efuse user space read write ops", ++ "init --- init efuse user space\n" ++ "size keyname --- get key size configured in dts\n" ++ "read keyname addr --- read key value to mem addr \n" ++ "write --- write key value\n" ++ " efuse_user write keyname hexstring --- write key value in hex string\n" ++ " efuse_user write keyname addr size --- write key value, U need load you key value into mem addr first\n" ++); ++ +diff --git a/drivers/mmc/aml_emmc_partition.c b/drivers/mmc/aml_emmc_partition.c +new file mode 100644 +index 00000000000..550042adb35 +--- /dev/null ++++ b/drivers/mmc/aml_emmc_partition.c +@@ -0,0 +1,1715 @@ ++/* ++ * Copyright 2016, Amlogic Inc ++ * yonghui.yu ++ * ++ * Based vaguely on the Linux code ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mmc_private.h" ++#include ++#include ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++/* using mbr*/ ++#define CONFIG_PTBL_MBR (1) ++#if (CONFIG_PTBL_MBR) ++ /* cmpare partition name? */ ++ #define CONFIG_CMP_PARTNAME (0) ++ /* cmpare partition mask */ ++ #define CONFIG_CMP_PARTMASK (0) ++#else ++ #define CONFIG_CMP_PARTNAME (1) ++ #define CONFIG_CMP_PARTMASK (1) ++#endif ++/* debug info*/ ++#define CONFIG_MPT_DEBUG (0) ++#define GPT_PRIORITY (1) ++ ++#define apt_err(fmt, ...) printf( "%s()-%d: " fmt , \ ++ __func__, __LINE__, ##__VA_ARGS__) ++ ++#define apt_wrn(fmt, ...) printf( "%s()-%d: " fmt , \ ++ __func__, __LINE__, ##__VA_ARGS__) ++#if (CONFIG_MPT_DEBUG) ++/* for detail debug info */ ++#define apt_info(fmt, ...) printf( "%s()-%d: " fmt , \ ++ __func__, __LINE__, ##__VA_ARGS__) ++#else ++#define apt_info(fmt, ...) ++#endif ++ ++/* creat MBR for emmc */ ++#define MAX_PNAME_LEN (16) ++#define MAX_PART_COUNT (32) ++ ++/* ++ Global offset of reserved partition is 36MBytes ++ since MMC_BOOT_PARTITION_RESERVED is 32MBytes and ++ MMC_BOOT_DEVICE_SIZE is 4MBytes. ++ MMC_RESERVED_SIZE is 64MBytes for now. ++ layout detail inside reserved partition. ++ 0x000000 - 0x003fff: partition table ++ 0x004000 - 0x03ffff: storage key area (16k offset & 256k size) ++ 0x400000 - 0x47ffff: dtb area (4M offset & 512k size) ++ 0x480000 - 64MBytes: resv for other usage. ++ ... ++ */ ++/* ++#define RSV_DTB_OFFSET_GLB (SZ_1M*40) ++#define RSV_DTB_SIZE (512*1024UL) ++#define RSV_PTBL_OFFSET (SZ_1M*0) ++#define RSV_PTBL_SIZE (16*1024UL) ++#define RSV_SKEY_OFFSET (16*1024UL) ++#define RSV_SKEY_SIZE (256*1024UL) ++#define RSV_DTB_OFFSET (SZ_1M*4) ++*/ ++ ++/* virtual partitions which are in "reserved" */ ++#define MAX_MMC_VIRTUAL_PART_CNT (5) ++ ++ ++/* BinaryLayout of partition table stored in rsv area */ ++struct ptbl_rsv { ++ char magic[4]; /* MPT */ ++ unsigned char version[12]; /* binary version */ ++ int count; /* partition count in using */ ++ int checksum; ++ struct partitions partitions[MAX_MMC_PART_NUM]; ++}; ++ ++/* partition table for innor usage*/ ++struct _iptbl { ++ struct partitions *partitions; ++ int count; /* partition count in use */ ++}; ++ ++unsigned device_boot_flag = 0xff; ++bool is_partition_checked = false; ++ ++#ifndef CONFIG_AML_MMC_INHERENT_PART ++/* fixme, name should be changed as aml_inherent_ptbl */ ++struct partitions emmc_partition_table[] = { ++#ifndef CONFIG_AML_GPT ++ PARTITION_ELEMENT(MMC_BOOT_NAME, MMC_BOOT_DEVICE_SIZE, 0), ++#endif ++ PARTITION_ELEMENT(MMC_RESERVED_NAME, MMC_RESERVED_SIZE, 0), ++ /* prior partitions, same partition name with dts*/ ++ /* partition size will be overide by dts*/ ++ PARTITION_ELEMENT(MMC_CACHE_NAME, 0, 0), ++ PARTITION_ELEMENT(MMC_ENV_NAME, MMC_ENV_SIZE, 0), ++}; ++ ++struct virtual_partition virtual_partition_table[] = { ++ /* partition for name idx, off & size will not be used! */ ++#if (CONFIG_PTBL_MBR) ++ VIRTUAL_PARTITION_ELEMENT(MMC_MBR_NAME, MMC_MBR_OFFSET, MMC_MBR_SIZE), ++#endif ++ VIRTUAL_PARTITION_ELEMENT(MMC_BOOT_NAME0, 0, 0), ++ VIRTUAL_PARTITION_ELEMENT(MMC_BOOT_NAME1, 0, 0), ++ ++ /* virtual partition in reserved partition, take care off and size */ ++#ifdef CONFIG_AML_PARTITION ++ VIRTUAL_PARTITION_ELEMENT(MMC_TABLE_NAME, MMC_TABLE_OFFSET, MMC_TABLE_SIZE), ++#endif ++ VIRTUAL_PARTITION_ELEMENT(MMC_KEY_NAME, EMMCKEY_RESERVE_OFFSET, MMC_KEY_SIZE), ++ VIRTUAL_PARTITION_ELEMENT(MMC_PATTERN_NAME, CALI_PATTERN_OFFSET, CALI_PATTERN_SIZE), ++ VIRTUAL_PARTITION_ELEMENT(MMC_MAGIC_NAME, MAGIC_OFFSET, MAGIC_SIZE), ++ VIRTUAL_PARTITION_ELEMENT(MMC_RANDOM_NAME, RANDOM_OFFSET, RANDOM_SIZE), ++#ifndef DTB_BIND_KERNEL ++ VIRTUAL_PARTITION_ELEMENT(MMC_DTB_NAME, DTB_OFFSET, DTB_SIZE), ++#endif ++ VIRTUAL_PARTITION_ELEMENT(MMC_FASTBOOT_CONTEXT_NAME, ++ FASTBOOT_CONTEXT_OFFSET, FASTBOOT_CONTEXT_SIZE), ++ VIRTUAL_PARTITION_ELEMENT(MMC_DDR_PARAMETER_NAME,DDR_PARAMETER_OFFSET, DDR_PARAMETER_SIZE), ++}; ++ ++int get_emmc_partition_arraysize(void) ++{ ++ return ARRAY_SIZE(emmc_partition_table); ++} ++ ++int get_emmc_virtual_partition_arraysize(void) ++{ ++ return ARRAY_SIZE(virtual_partition_table); ++} ++ ++#endif ++ ++void __attribute__((unused)) _dump_part_tbl(struct partitions *p, int count) ++{ ++ int i = 0; ++ apt_info("count %d\n", count); ++ while (i < count) { ++ printf("%02d %10s %016llx %016llx\n", i, p[i].name, p[i].offset, p[i].size); ++ i++; ++ } ++ return; ++} ++ ++static int _get_part_index_by_name(struct partitions *tbl, ++ int cnt, const char *name) ++{ ++ int i=0; ++ struct partitions *part = NULL; ++ ++ while (i < cnt) { ++ part = &tbl[i]; ++ if (!strcmp(name, part->name)) { ++ apt_info("find %s @ tbl[%d]\n", name, i); ++ break; ++ } ++ i++; ++ }; ++ if (i == cnt) { ++ i = -1; ++ apt_wrn("do not find match in table %s\n", name); ++ } ++ return i; ++} ++ ++ ++ ++static struct partitions *_find_partition_by_name(struct partitions *tbl, ++ int cnt, const char *name) ++{ ++ int i = 0; ++ struct partitions *part = NULL; ++ ++ while (i < cnt) { ++ ++ part = &tbl[i]; ++ if (!strcmp(name, part->name)) { ++ apt_info("find %s @ tbl[%d]\n", name, i); ++ break; ++ } ++ i++; ++ }; ++ if (i == cnt) { ++ part = NULL; ++ apt_wrn("do not find match in table %s\n", name); ++ } ++ return part; ++} ++ ++/* fixme, must called after offset was calculated. */ ++static ulong _get_inherent_offset(const char *name) ++{ ++ struct partitions *part; ++ ++ part = _find_partition_by_name(emmc_partition_table, ++ get_emmc_partition_arraysize(), name); ++ if (NULL == part) ++ return -1; ++ else ++ return part->offset; ++} ++/* partition table (Emmc Partition Table) */ ++struct _iptbl *p_iptbl_ept = NULL; ++ ++/* trans byte into lba manner for rsv area read/write */ ++#ifdef CONFIG_AML_PARTITION ++static ulong _mmc_rsv_read(struct mmc *mmc, ulong offset, ulong size, void * buffer) ++{ ++ lbaint_t _blk, _cnt; ++ if (0 == size) ++ return 0; ++ ++ _blk = offset / mmc->read_bl_len; ++ _cnt = size / mmc->read_bl_len; ++ _cnt = blk_dread(mmc_get_blk_desc(mmc), _blk, _cnt, buffer); ++ ++ return (ulong)(_cnt * mmc->read_bl_len); ++} ++ ++static ulong _mmc_rsv_write(struct mmc *mmc, ulong offset, ulong size, void * buffer) ++{ ++ lbaint_t _blk, _cnt; ++ if (0 == size) ++ return 0; ++ ++ _blk = offset / mmc->read_bl_len; ++ _cnt = size / mmc->read_bl_len; ++ _cnt = blk_dwrite(mmc_get_blk_desc(mmc), _blk, _cnt, buffer); ++ ++ return (ulong)(_cnt * mmc->read_bl_len); ++} ++#endif ++ ++ ++static struct partitions * get_ptbl_from_dtb(struct mmc *mmc) ++{ ++ struct partitions * ptbl = NULL; ++#ifdef CONFIG_AML_PARTITION ++#ifndef DTB_BIND_KERNEL ++ unsigned char * buffer = NULL; ++ ulong ret, offset; ++ struct virtual_partition *vpart = aml_get_virtual_partition_by_name(MMC_DTB_NAME); ++ ++ /* try get dtb table from ddr, which may exsit while usb burning */ ++ if (NULL == get_partitions()) { ++ /* if failed, try rsv dtb area then. */ ++ buffer = malloc(vpart->size * DTB_COPIES); ++ if (NULL == buffer) { ++ apt_err("Can not alloc enough buffer\n"); ++ goto _err; ++ } ++ offset = _get_inherent_offset(MMC_RESERVED_NAME) + vpart->offset; ++ ret = _mmc_rsv_read(mmc, offset, (vpart->size * DTB_COPIES), buffer); ++ if (ret != (vpart->size * DTB_COPIES)) { ++ apt_err("Can not alloc enough buffer\n"); ++ goto _err1; ++ } ++ /* parse it */ ++ if (get_partition_from_dts(buffer)) { ++ apt_err("get partition table from dts failed. try from internal dts\n"); ++ if (buffer) ++ free(buffer); ++ buffer = (char*) env_get_ulong("fdtcontroladdr", 16, CFG_SYS_SDRAM_BASE + (16U<<20)); ++ if (get_partition_from_dts(buffer)) { ++ apt_err("get partition table from internal dts failed.\n"); ++ goto _err; ++ } ++ buffer = NULL; ++ } ++ /* double check part_table(glb) */ ++ if (NULL == get_partitions()) { ++ goto _err1; ++ } ++ apt_info("get partition table from dts successfully\n"); ++ ++ if (buffer) ++ free(buffer); ++ buffer = NULL; ++ } ++#endif ++#endif ++ /* asign partition info to *ptbl */ ++ ptbl = get_partitions(); ++ return ptbl; ++#ifdef CONFIG_AML_PARTITION ++#ifndef DTB_BIND_KERNEL ++_err1: ++ if (buffer) ++ free(buffer); ++_err: ++ free (ptbl); ++ return NULL; ++#endif ++#endif ++} ++ ++ ++ ++ ++static struct partitions *is_prio_partition(struct _iptbl *list, struct partitions *part) ++{ ++ int i; ++ struct partitions *plist = NULL; ++ ++ if (list->count == 0) ++ goto _out; ++ ++ apt_info("count %d\n", list->count); ++ for (i=0; icount; i++) { ++ plist = &list->partitions[i]; ++ apt_info("%d: %s, %s\n", i, part->name, plist->name); ++ if (!strcmp(plist->name, part->name)) { ++ apt_info("%s is prio in list[%d]\n", part->name, i); ++ break; ++ } ++ } ++ if (i == list->count) ++ plist = NULL; ++_out: ++ return plist; ++} ++ ++/* calculate offset of each partitions. ++ bottom is a flag for considering ++ */ ++static int _calculate_offset(struct mmc *mmc, struct _iptbl *itbl, u32 bottom) ++{ ++ int i; ++ struct partitions *part; ++ ulong gap = PARTITION_RESERVED; ++ int ret = 0; ++ ++ if (itbl->count <= 0) ++ return -1; ++ part = itbl->partitions; ++#if (CONFIG_MPT_DEBUG) ++ _dump_part_tbl(part, itbl->count); ++#endif ++ ++#if CONFIG_AML_GPT ++ part->offset = RESERVED_GPT_OFFSET; ++#endif ++ ++ if (!strcmp(part->name, "bootloader")) { ++ part->offset = 0; ++ gap = MMC_BOOT_PARTITION_RESERVED; ++ } ++ for (i=1; icount; i++) { ++ /**/ ++ part[i].offset = part[i-1].offset + part[i-1].size + gap; ++ /* check capicity overflow ?*/ ++ if (((part[i].offset + part[i].size) > mmc->capacity) || ++ (part[i].size == -1)) { ++ part[i].size = mmc->capacity - part[i].offset; ++ /* reserv space @ the bottom */ ++ if (bottom && (part[i].size > MMC_BOTTOM_RSV_SIZE)) { ++ apt_info("reserv %d bytes at bottom\n", MMC_BOTTOM_RSV_SIZE); ++ part[i].size -= MMC_BOTTOM_RSV_SIZE; ++ } ++ break; ++ } ++ gap = PARTITION_RESERVED; ++ } ++ if (i < (itbl->count - 1)) { ++ apt_err("too large partition table for current emmc, overflow!\n"); ++ ret = -1; ++ } ++#if (CONFIG_MPT_DEBUG) ++ _dump_part_tbl(part, itbl->count); ++#endif ++ return ret; ++} ++ ++static void compose_ept(struct _iptbl *dtb, struct _iptbl *inh, ++ struct _iptbl *ept) ++{ ++ int i; ++ struct partitions *partition = NULL; ++ struct partitions *dst, *src, *prio; ++ ++ /* overide inh info by dts */ ++ apt_info("dtb %p, inh %p, ept %p\n", dtb, inh, ept); ++ apt_info("ept->partitions %p\n", ept->partitions); ++ partition = ept->partitions; ++ apt_info("partition %p\n", partition); ++ for (i=0; icount %d\n", i, ept->count); ++ dst = &partition[ept->count]; ++ src = (i < inh->count) ? &inh->partitions[i]:&dtb->partitions[i-inh->count]; ++ ++ prio = is_prio_partition(ept, src); ++ if (prio) { ++ /* overide prio partition by new */ ++ apt_info("override %d: %s\n", ept->count, prio->name); ++ //*prio = *src; ++ dst = prio; ++ } else ++ ept->count ++; ++ *dst = *src; ++ if (-1 == src->size) { ++ apt_info("break! %s\n", src->name); ++ break; ++ } ++ } ++ ++ return; ++} ++#ifdef CONFIG_AML_PARTITION ++static int _get_version(unsigned char * s) ++{ ++ int version = 0; ++ if (!strncmp((char *)s, MMC_MPT_VERSION_2, sizeof(MMC_MPT_VERSION_2))) ++ version = 2; ++ else if (!strncmp((char *)s, MMC_MPT_VERSION_1, sizeof(MMC_MPT_VERSION_1))) ++ version = 1; ++ else ++ version = -1; ++ ++ return version; ++} ++ ++/* calc checksum. ++ there's a bug on v1 which did not calculate all the partitios. ++ */ ++static int _calc_iptbl_check_v2(struct partitions * part, int count) ++{ ++ int ret = 0, i; ++ int size = count * sizeof(struct partitions) >> 2; ++ int *buf = (int *)part; ++ ++ for (i = 0; i < size; i++) ++ ret +=buf[i]; ++ ++ return ret; ++} ++ ++static int _calc_iptbl_check_v1(struct partitions *part, int count) ++{ ++ int i, j; ++ u32 checksum = 0, *p; ++ ++ for (i = 0; i < count; i++) { ++ p = (u32*)part; ++ /*BUG here, do not fix it!!*/ ++ for (j = sizeof(struct partitions)/sizeof(checksum); j > 0; j--) { ++ checksum += *p; ++ p++; ++ } ++ } ++ ++ return checksum; ++} ++ ++static int _calc_iptbl_check(struct partitions * part, int count, int version) ++{ ++ if (1 == version) ++ return _calc_iptbl_check_v1(part, count); ++ else if (2 == version) ++ return _calc_iptbl_check_v2(part, count); ++ else ++ return -1; ++} ++ ++/* ept is malloced out side */ ++static int _cpy_iptbl(struct _iptbl * dst, struct _iptbl * src) ++{ ++ int ret = 0; ++ if (!dst || !src) { ++ apt_err("invalid arg %s\n", !dst ? "dst" : "src"); ++ ret = -1; ++ goto _out; ++ } ++ if (!dst->partitions || !src->partitions) { ++ apt_err("invalid arg %s->partitions\n", !dst ? "dst" : "src"); ++ ret = -2; ++ goto _out; ++ } ++ ++ dst->count = src->count; ++ memcpy(dst->partitions, src->partitions, sizeof(struct partitions) * src->count); ++ ++_out: ++ return ret; ++} ++ ++ ++/* get ptbl from rsv area from emmc */ ++static int get_ptbl_rsv(struct mmc *mmc, struct _iptbl *rsv) ++{ ++ struct ptbl_rsv * ptbl_rsv = NULL; ++ uchar * buffer = NULL; ++ ulong size, offset; ++ int checksum, version, ret = 0; ++ struct virtual_partition *vpart = aml_get_virtual_partition_by_name(MMC_TABLE_NAME); ++ ++ size = (sizeof(struct ptbl_rsv) + 511) / 512 * 512; ++ if (vpart->size < size) { ++ apt_err("too much partitons\n"); ++ ret = -1; ++ goto _out; ++ } ++ buffer = malloc(size); ++ if (NULL == buffer) { ++ apt_err("no enough memory for ptbl rsv\n"); ++ ret = -2; ++ goto _out; ++ } ++ /* read it from emmc. */ ++ offset = _get_inherent_offset(MMC_RESERVED_NAME) + vpart->offset; ++ if (size != _mmc_rsv_read(mmc, offset, size, buffer)) { ++ apt_err("read ptbl from rsv failed\n"); ++ ret = -3; ++ goto _out; ++ } ++ ++ ptbl_rsv = (struct ptbl_rsv *) buffer; ++ apt_info("magic %3.3s, version %8.8s, checksum %x\n", ptbl_rsv->magic, ++ ptbl_rsv->version, ptbl_rsv->checksum); ++ /* fixme, check magic ?*/ ++ if (strncmp(ptbl_rsv->magic, MMC_PARTITIONS_MAGIC, sizeof(MMC_PARTITIONS_MAGIC))) { ++ apt_err("magic faild %s, %3.3s\n", MMC_PARTITIONS_MAGIC, ptbl_rsv->magic); ++ ret = -4; ++ goto _out; ++ } ++ /* check version*/ ++ version = _get_version(ptbl_rsv->version); ++ if (version < 0) { ++ apt_err("version faild %s, %3.3s\n", MMC_PARTITIONS_MAGIC, ptbl_rsv->magic); ++ ret = -5; ++ goto _out; ++ } ++ if (ptbl_rsv->count > MAX_MMC_PART_NUM) { ++ apt_err("invalid partition count %d\n", ptbl_rsv->count); ++ ret = -1; ++ goto _out; ++ } ++ /* check sum */ ++ checksum = _calc_iptbl_check(ptbl_rsv->partitions, ptbl_rsv->count, version); ++ if (checksum != ptbl_rsv->checksum) { ++ apt_err("checksum faild 0x%x, 0x%x\n", ptbl_rsv->checksum, checksum); ++ ret = -6; ++ goto _out; ++ } ++ ++ rsv->count = ptbl_rsv->count; ++ memcpy(rsv->partitions, ptbl_rsv->partitions, rsv->count * sizeof(struct partitions)); ++ ++_out: ++ if (buffer) ++ free (buffer); ++ return ret; ++} ++ ++ ++/* update partition tables from src ++ if success, return 0; ++ else, return 1 ++ */ ++static int update_ptbl_rsv(struct mmc *mmc, struct _iptbl *src) ++{ ++ struct ptbl_rsv *ptbl_rsv = NULL; ++ uchar *buffer; ++ ulong size, offset; ++ int ret = 0, version; ++ struct virtual_partition *vpart = aml_get_virtual_partition_by_name(MMC_TABLE_NAME); ++ ++ size = (sizeof(struct ptbl_rsv) + 511) / 512 * 512; ++ buffer = malloc(size); ++ if (NULL == buffer) { ++ apt_err("no enough memory for ptbl rsv\n"); ++ return -1; ++ } ++ memset(buffer, 0 , size); ++ /* version, magic and checksum */ ++ ptbl_rsv = (struct ptbl_rsv *) buffer; ++ strcpy((char *)ptbl_rsv->version, MMC_MPT_VERSION); ++ strcpy(ptbl_rsv->magic, MMC_PARTITIONS_MAGIC); ++ if (src->count > MAX_MMC_PART_NUM) { ++ apt_err("too much partitions\n"); ++ ret = -1; ++ goto _err; ++ } ++ ptbl_rsv->count = src->count; ++ memcpy(ptbl_rsv->partitions, src->partitions, ++ sizeof(struct partitions)*src->count); ++ version = _get_version(ptbl_rsv->version); ++ ptbl_rsv->checksum = _calc_iptbl_check(src->partitions, src->count, version); ++ /* write it to emmc. */ ++ apt_info("magic %3.3s, version %8.8s, checksum %x\n", ptbl_rsv->magic, ptbl_rsv->version, ptbl_rsv->checksum); ++ offset = _get_inherent_offset(MMC_RESERVED_NAME) + vpart->offset; ++ if (_mmc_rsv_write(mmc, offset, size, buffer) != size) { ++ apt_err("write ptbl to rsv failed\n"); ++ ret = -1; ++ goto _err; ++ } ++_err: ++ free (buffer); ++ return ret; ++} ++ ++static void _free_iptbl(struct _iptbl *iptbl) ++{ ++ if (iptbl && iptbl->partitions) { ++ free(iptbl->partitions); ++ iptbl->partitions = NULL; ++ } ++ if (iptbl) { ++ free(iptbl); ++ iptbl = NULL; ++ } ++ ++ return; ++} ++ ++#endif ++static int _cmp_partition(struct partitions *dst, struct partitions *src, int overide) ++{ ++ int ret = 0; ++#if (CONFIG_CMP_PARTNAME) ++ if (strncmp(dst->name, src->name, sizeof(src->name))) ++ ret = -2; ++#endif ++ if (dst->size != src->size) ++ ret = -3; ++ if (dst->offset != src->offset) ++ ret = -4; ++#if (CONFIG_CMP_PARTMASK) ++ if (dst->mask_flags != src->mask_flags) ++ ret = -5; ++#endif ++ ++ if (ret && (!overide)) { ++ apt_err("name: %10.10s<->%10.10s\n", dst->name, src->name); ++ apt_err("size: %llx<->%llx\n", dst->size, src->size); ++ apt_err("offset: %llx<->%llx\n", dst->offset, src->offset); ++ apt_err("mask: %08x<->%08x\n", dst->mask_flags, src->mask_flags); ++ } ++ ++ if (overide) { ++ *dst = *src; ++ ret = 0; ++ } ++ ++ return ret; ++} ++ ++/* compare partition tables ++ if same, do nothing then return 0; ++ else, print the diff ones and return -x ++ -1:count ++ -2:name ++ -3:size ++ -4:offset ++ */ ++static int _cmp_iptbl(struct _iptbl * dst, struct _iptbl * src) ++{ ++ int ret = 0, i = 0; ++ struct partitions *dstp; ++ struct partitions *srcp; ++ ++ if (dst->count != src->count) { ++ apt_err("partition count is not same %d:%d\n", dst->count, src->count); ++ ret = -1; ++ goto _out; ++ } ++ ++ while (i < dst->count) { ++ dstp = &dst->partitions[i]; ++ srcp = &src->partitions[i]; ++ ret = _cmp_partition(dstp, srcp, 0); ++ if (ret) { ++ apt_err("partition %d has changed\n", i); ++ break; ++ } ++ i++; ++ } ++ ++_out: ++ return ret; ++} ++ ++ ++/* iptbl buffer opt. */ ++static int _zalloc_iptbl(struct _iptbl **_iptbl) ++{ ++ int ret = 0; ++ struct _iptbl *iptbl; ++ struct partitions *partition = NULL; ++ ++ partition = malloc(sizeof(struct partitions)*MAX_PART_COUNT); ++ if (NULL == partition) { ++ ret = -1; ++ apt_err("no enough memory for partitions\n"); ++ goto _out; ++ } ++ ++ iptbl = malloc(sizeof(struct _iptbl)); ++ if (NULL == iptbl) { ++ ret = -2; ++ apt_err("no enough memory for ept\n"); ++ free(partition); ++ goto _out; ++ } ++ memset(partition, 0, sizeof(struct partitions)*MAX_PART_COUNT); ++ memset(iptbl, 0, sizeof(struct _iptbl)); ++ ++ iptbl->partitions = partition; ++ apt_info("iptbl %p, partition %p, iptbl->partitions %p\n", ++ iptbl, partition, iptbl->partitions); ++ *_iptbl = iptbl; ++_out: ++ return ret; ++} ++ ++ ++/* ++ * fixme, need check space size later. ++ */ ++ ++static inline int le32_to_int(unsigned char *le32) ++{ ++ return ((le32[3] << 24) + ++ (le32[2] << 16) + ++ (le32[1] << 8) + ++ le32[0] ++ ); ++} ++ ++static int test_block_type(unsigned char *buffer) ++{ ++ int slot; ++ struct dos_partition *p; ++ ++ if ((buffer[DOS_PART_MAGIC_OFFSET + 0] != 0x55) || ++ (buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) ) { ++ return (-1); ++ } /* no DOS Signature at all */ ++ p = (struct dos_partition *)&buffer[DOS_PART_TBL_OFFSET]; ++ for (slot = 0; slot < 3; slot++) { ++ if (p->boot_ind != 0 && p->boot_ind != 0x80) { ++ if (!slot && ++ (strncmp((char *)&buffer[DOS_PBR_FSTYPE_OFFSET], ++ "FAT", 3) == 0 || ++ strncmp((char *)&buffer[DOS_PBR32_FSTYPE_OFFSET], ++ "FAT32", 5) == 0)) { ++ return DOS_PBR; /* is PBR */ ++ } else { ++ return -1; ++ } ++ } ++ } ++ return DOS_MBR; /* Is MBR */ ++} ++ ++//DOS_MBR OR DOS_PBR ++/* ++ * re-constructe iptbl from mbr&ebr infos. ++ * memory for iptbl_mbr must be alloced outside. ++ * ++ */ ++static void _construct_ptbl_by_mbr(struct mmc *mmc, struct _iptbl *iptbl_mbr) ++{ ++ int ret,i; ++ int flag = 0; ++ lbaint_t read_offset = 0; ++ int part_num = 0; ++ int primary_num = 0; ++ uint64_t logic_start = 0; ++ uint64_t externed_start = 0; ++ struct dos_partition *pt; ++ struct partitions *partitions = iptbl_mbr->partitions; ++ ++ apt_info("aml MBR&EBR debug...\n"); ++ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, 512); ++ for (;;) { ++ apt_info("**%02d: read_offset %016llx\n", part_num, (uint64_t)read_offset<<9); ++ ret = blk_dread(mmc_get_blk_desc(mmc), read_offset, 1, buffer); ++ if (read_offset == 0) ++ flag = 1; ++ else ++ flag = 0; ++ /* debug code */ ++ // print_buffer(0,buffer,1,512,16); ++ if (ret != 1) { ++ apt_err("ret %d fail to read current ebr&mbr from emmc! \n", ret); ++ break; ++ } ++ ret = test_block_type(buffer); ++ if (ret != 0 && ret != 1) { ++ apt_err("invalid magic value: 0x%02x%02x\n", ++ buffer[DOS_PART_MAGIC_OFFSET], buffer[DOS_PART_MAGIC_OFFSET + 1]); ++ break; ++ } ++ ++ pt = (dos_partition_t *)(&buffer[0] + DOS_PART_TBL_OFFSET); ++ for (i = 0; i < 4; i++, pt++) { ++ if ( (pt->boot_ind == 0x00 || pt->boot_ind == 0x80) && pt->sys_ind == 0x83 ) { ++ //emmc_partition[part_num]->name = NULL; ++ partitions[part_num].offset = ((uint64_t)(le32_to_int(pt->start4)+read_offset) << 9ULL); ++ partitions[part_num].size = (uint64_t)le32_to_int(pt->size4) << 9ULL; ++ partitions[part_num].mask_flags = pt->sys_ind; ++ ++ apt_info("--partition[%d]: %016llx, %016llx, 0x%08x \n", ++ part_num, partitions[part_num].offset, ++ partitions[part_num].size, ++ le32_to_int(pt->size4)); ++ part_num++; ++ if ( flag ) ++ primary_num++; ++ }else{/* get the next externed partition info */ ++ if ( pt->boot_ind == 0x00 && pt->sys_ind == 0x05) { ++ logic_start = (uint64_t)le32_to_int (pt->start4); ++ //logic_size = (uint64_t)le32_to_int (pt->size4); ++ } ++ } ++ } ++ /* mbr & ebr debug infos */ ++ apt_info("******%02d: read_offset=%016llx, logic_start=%016llx\n", ++ part_num,(uint64_t)read_offset*512ULL,logic_start*512ULL); ++ ++ if (part_num == primary_num) { ++ externed_start = logic_start; ++ read_offset = externed_start; ++ }else ++ read_offset = externed_start + logic_start; ++ if (logic_start == 0) ++ break; ++ logic_start = 0; ++ ++ } ++ iptbl_mbr->count = part_num; ++ apt_info("iptbl_mbr->count = %d\n", iptbl_mbr->count); ++ ++ return; ++} ++ ++static int __attribute__((unused)) _check_ptbl_mbr(struct mmc *mmc, struct _iptbl *ept) ++{ ++ int ret = 0; ++ /* re-constructed by mbr */ ++ struct _iptbl *iptbl_mbr = NULL, *ept2 = NULL; ++ struct partitions *partitions = NULL; ++ int i,j; ++ ++ iptbl_mbr = malloc(sizeof(struct _iptbl)); ++ if (NULL == iptbl_mbr) { ++ apt_err("no enough memory for iptbl_mbr\n"); ++ return -1; ++ } ++ memset(iptbl_mbr , 0, sizeof(struct _iptbl)); ++ partitions = (struct partitions *)malloc(sizeof(struct partitions) * DOS_PARTITION_COUNT); ++ if (NULL == partitions) { ++ apt_err("no enough memory for partitions\n"); ++ free(iptbl_mbr); ++ return -1; ++ } ++ memset(partitions, 0, sizeof(struct partitions) * DOS_PARTITION_COUNT); ++ iptbl_mbr->partitions = partitions; ++ ++ _construct_ptbl_by_mbr(mmc, iptbl_mbr); ++ if (iptbl_mbr->count > 0) ++ { ++ ret = 0; ++ goto _check_return; ++ } ++ ++ ept2 = (struct _iptbl*) malloc(sizeof(struct _iptbl)); ++ if (!ept2) ++ return -1; ++ ++ ept2 -> partitions = (struct partitions*) malloc (sizeof(struct partitions) * ept->count); ++ if (!ept2->partitions) ++ return -1; ++ memset (ept2->partitions, 0, sizeof(struct partitions) * ept->count); ++ ept2 -> count = 0; ++ ++ for (i=4,j=0;icount;i++) ++ { ++ apt_info("-!check partition name %s\n",ept->partitions[i].name); ++ memcpy(&ept2->partitions[j],&ept->partitions[i], sizeof(struct partitions)); ++ j++; ++ ++ } ++ ept2->count = j; ++ ++ ret = _cmp_iptbl(iptbl_mbr, ept2); ++ if (ept2->partitions) ++ free (ept2->partitions); ++ if (ept2) ++ free (ept2); ++ ++ if (partitions) ++ free(partitions); ++ if (iptbl_mbr) ++ free(iptbl_mbr); ++ _check_return: ++ apt_wrn("MBR is %s\n", ret?"Improper!":"OK!"); ++ return ret; ++} ++ ++/* construct a partition table entry of EBR */ ++static int _construct_ebr_1st_entry(struct _iptbl *p_iptbl,struct dos_partition *p_ebr, int part_num ) ++{ ++ uint64_t start_offset = 0; ++ uint64_t logic_size = 0; ++ ++ p_ebr->boot_ind = 0x00; ++ p_ebr->sys_ind = 0x83; ++ /* Starting = relative offset between this EBR sector and the first sector of the logical partition ++ * the gap between two partition is a fixed value of PARTITION_RESERVED ,otherwise the emmc partiton ++ * is different with reserved */ ++ start_offset = PARTITION_RESERVED >> 9; ++ /* Number of sectors = total count of sectors for this logical partition */ ++ // logic_size = (p_iptbl->partitions[part_num].size) >> 9ULL; ++ logic_size = lldiv(p_iptbl->partitions[part_num].size, 512); ++ apt_info("*** %02d: size 0x%016llx, logic_size 0x%016llx\n", part_num, p_iptbl->partitions[part_num].size, logic_size); ++ memcpy((unsigned char *)(p_ebr->start4), &start_offset, 4); ++ memcpy((unsigned char *)(p_ebr->size4), &logic_size, 4); ++ return 0; ++} ++ ++static int _construct_ebr_2nd_entry(struct _iptbl *p_iptbl, struct dos_partition *p_ebr, int part_num) ++{ ++ uint64_t start_offset = 0; ++ uint64_t logic_size = 0; ++ ++ if ((part_num+2) > p_iptbl->count) ++ return 0; ++ ++ p_ebr->boot_ind = 0x00; ++ p_ebr->sys_ind = 0x05; ++ /* Starting sector = LBA address of next EBR minus LBA address of extended partition's first EBR */ ++ start_offset = (p_iptbl->partitions[part_num+1].offset - PARTITION_RESERVED - ++ (p_iptbl->partitions[3].offset - PARTITION_RESERVED)) >> 9; ++ /* total count of sectors for next logical partition, but count starts from the next EBR sector */ ++ logic_size = (p_iptbl->partitions[part_num+1].size + PARTITION_RESERVED) >> 9; ++ ++ memcpy((unsigned char *)(p_ebr->start4), &start_offset, 4); ++ memcpy((unsigned char *)(p_ebr->size4), &logic_size, 4); ++ ++ return 0; ++} ++ ++/* construct a partition table entry of MBR OR EBR */ ++static int _construct_mbr_entry(struct _iptbl *p_iptbl, struct dos_partition *p_entry, int part_num) ++{ ++ uint64_t start_offset = 0; ++ uint64_t primary_size = 0; ++ uint64_t externed_size = 0; ++ int i; ++ /* the entry is active or not */ ++ if (part_num == 0 ) ++ p_entry->boot_ind = 0x00; ++ else ++ p_entry->boot_ind = 0x00; ++ ++ if (part_num == 3) {/* the logic partion entry */ ++ /* the entry type */ ++ p_entry->sys_ind = 0x05; ++ start_offset = (p_iptbl->partitions[3].offset - PARTITION_RESERVED) >> 9; ++ for ( i = 3;i< p_iptbl->count;i++) ++ externed_size = p_iptbl->partitions[i].size >> 9; ++ ++ memcpy((unsigned char *)p_entry->start4, &start_offset, 4); ++ memcpy((unsigned char *)p_entry->size4, &externed_size, 4); ++ }else{/* the primary partion entry */ ++ /* the entry type */ ++ p_entry->sys_ind = 0x83; ++ start_offset = (p_iptbl->partitions[part_num].offset) >> 9; ++ primary_size = (p_iptbl->partitions[part_num].size)>>9; ++ memcpy((unsigned char *)p_entry->start4, &start_offset, 4); ++ memcpy((unsigned char *)p_entry->size4, &primary_size, 4); ++ } ++ ++ return 0; ++} ++ ++static int _construct_mbr_or_ebr(struct _iptbl *p_iptbl, struct dos_mbr_or_ebr *p_br, ++ int part_num, int type) ++{ ++ int i; ++ ++ apt_info("!!!++++ %0d(%0d) my count:%i\n",part_num, p_iptbl->count,p_iptbl->count<4?p_iptbl->count:4); ++ if (DOS_MBR == type) { ++ /* constuct a integral MBR */ ++ for (i = 0; i< ((p_iptbl->count<4)?p_iptbl->count:4) ; i++) ++ _construct_mbr_entry(p_iptbl, &p_br->part_entry[i], i); ++ ++ }else{ ++ /* constuct a integral EBR */ ++ p_br->bootstart[DOS_PBR32_FSTYPE_OFFSET] = 'F'; ++ p_br->bootstart[DOS_PBR32_FSTYPE_OFFSET + 1] = 'A'; ++ p_br->bootstart[DOS_PBR32_FSTYPE_OFFSET + 2] = 'T'; ++ p_br->bootstart[DOS_PBR32_FSTYPE_OFFSET + 3] = '3'; ++ p_br->bootstart[DOS_PBR32_FSTYPE_OFFSET + 4] = '2'; ++ ++ _construct_ebr_1st_entry(p_iptbl, &p_br->part_entry[0], part_num); ++ _construct_ebr_2nd_entry(p_iptbl, &p_br->part_entry[1], part_num); ++ } ++ ++ p_br->magic[0] = 0x55 ; ++ p_br->magic[1] = 0xAA ; ++ return 0; ++} ++ ++static __attribute__((unused)) int _update_ptbl_mbr(struct mmc *mmc, struct _iptbl *p_iptbl) ++{ ++ int ret = 0, start_blk = 0, blk_cnt = 1; ++ unsigned char *src; ++ int i,j; ++ struct dos_mbr_or_ebr *mbr; ++ struct _iptbl *ptb ; ++ struct _iptbl *ptb2; ++ ++ ptb = p_iptbl; ++ ptb2 = (struct _iptbl*) malloc(sizeof(struct _iptbl)); ++ ++ ptb2 -> partitions = (struct partitions*) malloc (sizeof(struct partitions) * ptb->count); ++ memset (ptb2->partitions, 0, sizeof(struct partitions) * ptb->count); ++ ptb2 -> count = 0; ++ ++ for (i=4,j=0;icount;i++) ++ { ++ apt_info("-!check partition name %s\n",ptb->partitions[i].name); ++ memcpy(&ptb2->partitions[j],&ptb->partitions[i], sizeof(struct partitions)); ++ j++; ++ ++ } ++ ptb2->count = j; ++ ptb = ptb2; ++ ++ mbr = malloc(sizeof(struct dos_mbr_or_ebr)); ++ ++ for (i=0;icount;i++) { ++ apt_info("-update MBR-: partition[%02d]: %016llx - %016llx skipped:%s name:%s parts count:%02d\n",i, ++ ptb->partitions[i].offset, ptb->partitions[i].size, ptb->partitions[i].size==0? "yes" :"no", ptb->partitions[i].name, ptb->count); ++ } ++ ++ for (i = 0;i < ptb->count;) { ++ apt_info("!!!!--- update_ptbl_mbr %02d (%02d)\n", i, ptb->count); ++ memset(mbr ,0 ,sizeof(struct dos_mbr_or_ebr)); ++ if (i == 0) { ++ _construct_mbr_or_ebr(ptb, mbr, i, 0); ++ i = i+2; ++ } else ++ _construct_mbr_or_ebr(ptb, mbr, i, 2); ++ src = (unsigned char *)mbr; ++ apt_info("--%s(): %02d(%02d), off %x\n", __func__, i, ptb->count, start_blk); ++ ret = blk_dwrite(mmc_get_blk_desc(mmc), start_blk, blk_cnt, src); ++ i++; ++ if (ret != blk_cnt) { ++ apt_err("write current MBR failed! ret: %d != cnt: %d\n",ret,blk_cnt); ++ break; ++ } ++ start_blk = (ptb->partitions[i].offset - PARTITION_RESERVED) >> 9; ++ apt_info("!!!!end update_ptbl_mbr %02d (%02d)\n", i, ptb->count); ++ } ++ free(mbr); ++ free(ptb->partitions); ++ free(ptb); ++ ++ ret = !ret; ++ if (ret) ++ apt_err("write MBR failed!\n"); ++ else ++ apt_err("write MBR ok!!!!\n"); ++ ++ return ret; ++} ++ ++#ifdef CONFIG_AML_GPT ++int is_gpt_changed(struct mmc *mmc, struct _iptbl *p_iptbl_ept) ++{ ++ int i, k; ++ gpt_entry *gpt_pte = NULL; ++ size_t efiname_len; ++ struct _iptbl *ept = p_iptbl_ept; ++ struct partitions *partitions = ept->partitions; ++ int parts_num = ept->count; ++ uint64_t offset; ++ uint64_t size; ++ char name[PARTNAME_SZ]; ++ int gpt_changed = 0; ++ struct blk_desc *dev_desc = mmc_get_blk_desc(mmc); ++ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz); ++ ++ if (!dev_desc) { ++ printf("%s: Invalid Argument(s)\n", __func__); ++ return 1; ++ } ++ ++ if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, ++ gpt_head, &gpt_pte) != 1) { ++ printf("%s: ***ERROR:Invalid GPT ***\n", __func__); ++ if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), ++ gpt_head, &gpt_pte) != 1) { ++ printf("%s: ***ERROR: Invalid Backup GPT ***\n", ++ __func__); ++ return 1; ++ } else { ++ printf("%s: *** Using Backup GPT ***\n", ++ __func__); ++ } ++ //return 1; ++ } ++ for (i = 0; i < le32_to_cpu(gpt_head->num_partition_entries); i++) { ++ if (!is_pte_valid(&gpt_pte[i])) ++ break; ++ ++ offset = le64_to_cpu(gpt_pte[i].starting_lba<<9ULL); ++ if (partitions[i].offset != offset) { ++ printf("Caution! GPT offset had been changed\n"); ++ gpt_changed = 1; ++ break; ++ } ++ ++ size = ((le64_to_cpu(gpt_pte[i].ending_lba)+1) - ++ le64_to_cpu(gpt_pte[i].starting_lba)) << 9ULL; ++ if (i == parts_num - 1) { ++ if ((partitions[i].size - GPT_TOTAL_SIZE) != size) { ++ printf("Caution! GPT size had been changed\n"); ++ gpt_changed = 1; ++ break; ++ } ++ } else { ++ if (partitions[i].size != size) { ++ printf("Caution! GPT size had been changed\n"); ++ gpt_changed = 1; ++ break; ++ } ++ } ++ ++ /* partition name */ ++ efiname_len = sizeof(gpt_pte[i].partition_name) ++ / sizeof(efi_char16_t); ++ ++ memset(name, 0, PARTNAME_SZ); ++ for (k = 0; k < efiname_len; k++) ++ name[k] = (char)gpt_pte[i].partition_name[k]; ++ if (strcmp(name, partitions[i].name) != 0) { ++ printf("Caution! GPT name had been changed\n"); ++ gpt_changed = 1; ++ break; ++ } ++ ++ } ++ if ((i != parts_num) && (gpt_changed == 0)) { ++ gpt_changed = 1; ++ printf("Caution! GPT number had been changed\n"); ++ } ++ ++ free(gpt_pte); ++ return gpt_changed; ++} ++int is_gpt_broken(struct mmc *mmc) ++{ ++ gpt_entry *gpt_pte = NULL; ++ int broken_status = 0; ++ struct blk_desc *dev_desc = mmc_get_blk_desc(mmc); ++ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz); ++ ++ if (!dev_desc) { ++ printf("%s: Invalid Argument(s)\n", __func__); ++ return 1; ++ } ++ ++ if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, ++ gpt_head, &gpt_pte) != 1) { ++ broken_status += 1; ++ printf("%s: ***ERROR:Invalid GPT ***\n", __func__); ++ } ++ if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), ++ gpt_head, &gpt_pte) != 1) { ++ printf("%s: ***ERROR: Invalid Backup GPT ***\n", ++ __func__); ++ broken_status += 2; ++ } ++ ++ if (broken_status != 3) ++ free(gpt_pte); ++ return broken_status; ++ ++} ++ ++int fill_ept_by_gpt(struct mmc *mmc, struct _iptbl *p_iptbl_ept) ++{ ++ struct blk_desc *dev_desc = mmc_get_blk_desc(mmc); ++ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz); ++ gpt_entry *gpt_pte = NULL; ++ int i, k; ++ size_t efiname_len, dosname_len; ++ struct _iptbl *ept = p_iptbl_ept; ++ struct partitions *partitions = ept->partitions; ++ ++ if (!dev_desc) { ++ printf("%s: Invalid Argument(s)\n", __func__); ++ return 1; ++ } ++ ++ if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, ++ gpt_head, &gpt_pte) != 1) { ++ printf("%s: ***ERROR:Invalid GPT ***\n", __func__); ++ if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), ++ gpt_head, &gpt_pte) != 1) { ++ printf("%s: ***ERROR: Invalid Backup GPT ***\n", ++ __func__); ++ return 1; ++ } else { ++ printf("%s: *** Using Backup GPT ***\n", ++ __func__); ++ } ++ //return 1; ++ } ++ ++ for (i = 0; i < le32_to_cpu(gpt_head->num_partition_entries); i++) { ++ if (!is_pte_valid(&gpt_pte[i])) ++ break; ++ ++ partitions[i].offset = le64_to_cpu(gpt_pte[i].starting_lba<<9ULL); ++ partitions[i].size = ((le64_to_cpu(gpt_pte[i].ending_lba)+1) - ++ le64_to_cpu(gpt_pte[i].starting_lba)) << 9ULL; ++ /* mask flag */ ++ partitions[i].mask_flags = (uint32_t)le64_to_cpu(gpt_pte[i].attributes.fields.reserved); ++ /* partition name */ ++ efiname_len = sizeof(gpt_pte[i].partition_name) ++ / sizeof(efi_char16_t); ++ dosname_len = sizeof(partitions[i].name); ++ ++ memset(partitions[i].name, 0, sizeof(partitions[i].name)); ++ for (k = 0; k < min(dosname_len, efiname_len); k++) ++ partitions[i].name[k] = (char)gpt_pte[i].partition_name[k]; ++ ++ } ++ ept->count = i; ++ free(gpt_pte); ++ return 0; ++} ++ ++void trans_ept_to_diskpart(struct _iptbl *ept, struct disk_partition *disk_part) { ++ struct partitions *part = ept->partitions; ++ int count = ept->count; ++ int i; ++ for (i = 0; i < count; i++) { ++ disk_part[i].start = part[i].offset >> 9; ++ strcpy((char *)disk_part[i].name, part[i].name); ++ /* store maskflag into type, 8bits ONLY! */ ++ disk_part[i].type[0] = (uchar)part[i].mask_flags; ++ #ifdef CONFIG_PARTITION_TYPE_GUID ++ strcpy((char *)disk_part[i].type_guid, part[i].name); ++ #endif ++ #ifdef CONFIG_RANDOM_UUID ++ gen_rand_uuid_str(disk_part[i].uuid, UUID_STR_FORMAT_STD); ++ #endif ++ disk_part[i].bootable = 0; ++ if ( i == (count - 1)) ++ disk_part[i].size = 0; ++ else ++ disk_part[i].size = (part[i].size) >> 9; ++ } ++ return; ++} ++ ++ ++ ++ ++#endif ++ ++/*************************************************** ++ * init partition table for emmc device. ++ * returns 0 means ok. ++ * other means failure. ++ *************************************************** ++ * work flows: ++ * source of logic partition table(LPT) is from dts ++ * no matter MACRO is on/off ++ * 1. try to get LPT from dtb ++ * 1.1 if dtb exist, compose ept by LPT&inh ++ * 1.2 if not, go ahead ++ * 2. try to get ept from emmc rsv partition ++ * 2.1 if not: ++ * 2.1.1 when dtb exists ++ * 2.1.1.1 check ept with dtb ++ * 2.1.1.2 update rsv if needed ++ * 2.1.1 without dtb, exit ++ * 2.2 if got: ++ * 2.2.1 try to reconstruct ept by MBR ++ * 2.2.2 check it with ept ++ * 2.2.3 update MBR if needed ++ *************************************************** ++ * when normal boot: ++ * without dtb, with rsv, with MBR ++ * when blank emmc: ++ * without dtb, without rsv, without MBR ++ * when burning MBR on a blank emmc: ++ * with dtb, without rsv, without MBR ++ * when burning MBR on a emmc with rsv: ++ * with dtb, with rsv, without MBR ++ * when burning MBR on a emmc with rsv&MBR: ++ * with dtb, with rsv, with MBR ++ ***************************************************/ ++int mmc_device_init (struct mmc *mmc) ++{ ++ int ret = 1; ++#if (CONFIG_PTBL_MBR) || (!CONFIG_AML_PARTITION) ++ //cpu_id_t cpu_id = get_cpu_id(); ++#endif ++ /* partition table from dtb/code/emmc rsv */ ++ struct _iptbl iptbl_dtb, iptbl_inh; ++ ++ /* calculate inherent offset */ ++ iptbl_inh.count = get_emmc_partition_arraysize(); ++ if (iptbl_inh.count) { ++ iptbl_inh.partitions = emmc_partition_table; ++ _calculate_offset(mmc, &iptbl_inh, 0); ++ } ++ apt_info("inh count %d\n", iptbl_inh.count); ++#if (CONFIG_MPT_DEBUG) ++ apt_info("inherent partition table\n"); ++ _dump_part_tbl(iptbl_inh.partitions, iptbl_inh.count); ++#endif ++ /* For re-entry */ ++ if (NULL == p_iptbl_ept) { ++ ret = _zalloc_iptbl(&p_iptbl_ept); ++ if (ret) ++ goto _out; ++ } else { ++ p_iptbl_ept->count = 0; ++ memset(p_iptbl_ept->partitions, 0, ++ sizeof(struct partitions)*MAX_PART_COUNT); ++ } ++ ++ /* try to get partition table from dtb(ddr or emmc) */ ++ iptbl_dtb.partitions = get_ptbl_from_dtb(mmc); ++ /* construct ept by dtb if exist */ ++ if (iptbl_dtb.partitions) { ++ iptbl_dtb.count = get_partition_count(); ++ apt_info("dtb %p, count %d\n", iptbl_dtb.partitions, iptbl_dtb.count); ++ /* reserved partition must exist! */ ++ if (iptbl_inh.count) { ++ compose_ept(&iptbl_dtb, &iptbl_inh, p_iptbl_ept); ++ if (0 == p_iptbl_ept->count) { ++ apt_err("compose partition table failed!\n"); ++ goto _out; ++ } ++ /* calculate offset infos. considering GAPs */ ++ if (_calculate_offset(mmc, p_iptbl_ept, 1)) { ++ goto _out; ++ } ++ #if (CONFIG_MPT_DEBUG) ++ apt_info("ept partition table\n"); ++ _dump_part_tbl(p_iptbl_ept->partitions, p_iptbl_ept->count); ++ #endif ++ } else { ++ /* report fail, because there is no reserved partitions */ ++ apt_err("compose partition table failed!\n"); ++ ret = -1; ++ goto _out; ++ } ++ } else ++ apt_wrn("get partition table from dtb failed\n"); ++#ifndef CONFIG_AML_PARTITION ++ if (0) { //(cpu_id.family_id < MESON_CPU_MAJOR_ID_G12B) { ++ printf("CONFIG_AML_PARTITION should define before G12B\n"); ++ goto _out; ++ } ++#endif ++ ++#ifdef CONFIG_AML_PARTITION ++ int update = 1; ++ struct _iptbl *p_iptbl_rsv = NULL; ++ /* try to get partiton table from rsv */ ++ ret = _zalloc_iptbl(&p_iptbl_rsv); ++ if (ret) ++ goto _out; ++ ret = get_ptbl_rsv(mmc, p_iptbl_rsv); ++ apt_info("!!!! after call get_ptbl_rsv got %i parts\n",p_iptbl_rsv->count); ++ ++ if (p_iptbl_rsv->count) { ++ /* dtb exist, p_iptbl_ept already inited */ ++ if (iptbl_dtb.partitions) { ++ ret = _cmp_iptbl(p_iptbl_ept, p_iptbl_rsv); ++ if (!ret) { ++ update = 0; ++ } ++ } else { ++ /* without dtb, update ept with rsv */ ++ apt_info("!!!! call _cpy_iptbl from rsv to ept %i\n",p_iptbl_rsv->count); ++ _cpy_iptbl(p_iptbl_ept, p_iptbl_rsv); ++ update = 0; ++ } ++ } else { ++ /* without dtb& rsv */ ++ if (!iptbl_dtb.partitions) { ++ apt_err("dtb&rsv are not exist, no LPT source\n"); ++ ret = -9; ++ goto _out; ++ } ++ } ++ ++ if (update && iptbl_dtb.partitions) { ++ apt_wrn("update rsv with dtb!\n"); ++ ret = update_ptbl_rsv(mmc, p_iptbl_ept); ++ } ++#endif ++ //apt_wrn("ept source is %s\n", (ept_source == p_iptbl_ept)?"ept":"rsv"); ++#if (CONFIG_PTBL_MBR) ++ /* 1st sector was reserved by romboot after gxl */ ++ if (1) { //(cpu_id.family_id >= MESON_CPU_MAJOR_ID_GXL) { ++ if (_check_ptbl_mbr(mmc, p_iptbl_ept)) { ++ apt_info("!!!! after _check_ptbl_mbr, see %i ept parts, check result %i\n",p_iptbl_ept->count, _check_ptbl_mbr(mmc, p_iptbl_ept)); ++ /*fixme, comaptible for mbr&ebr */ ++ ret |= _update_ptbl_mbr(mmc, p_iptbl_ept); ++ apt_wrn("MBR Updated!\n"); ++ } ++ } ++#endif ++#ifdef CONFIG_AML_GPT ++ char *str_disk_guid; ++ int gpt_priority = GPT_PRIORITY; ++ struct disk_partition *disk_partition; ++ int dcount = p_iptbl_ept->count; ++ struct blk_desc *dev_desc = mmc_get_blk_desc(mmc); ++ disk_partition = calloc(1, PAD_TO_BLOCKSIZE(sizeof(struct disk_partition) * dcount, dev_desc)); ++ trans_ept_to_diskpart(p_iptbl_ept, disk_partition); ++ str_disk_guid = malloc(UUID_STR_LEN + 1); ++ if (str_disk_guid == NULL) { ++ free(disk_partition); ++ return -ENOMEM; ++ } ++#ifdef CONFIG_RANDOM_UUID ++ gen_rand_uuid_str(str_disk_guid, UUID_STR_FORMAT_STD); ++#endif ++ if (part_test_efi(mmc_get_blk_desc(mmc)) != 0) { ++ ret = gpt_restore(mmc_get_blk_desc(mmc), str_disk_guid, disk_partition, dcount); ++ printf("GPT IS RESTORED %s\n", ret ? "Failed!" : "OK!"); ++ } else if (is_gpt_changed(mmc, p_iptbl_ept)) { ++ if (gpt_priority) { ++ fill_ept_by_gpt(mmc, p_iptbl_ept); ++ printf("and gpt has higher priority, so ept had been update\n"); ++ } else { ++ gpt_restore(mmc_get_blk_desc(mmc), str_disk_guid, disk_partition, dcount); ++ printf("but EPT has higher priority, so gpt had been recover\n"); ++ } ++ } ++ ++ int broken_status = is_gpt_broken(mmc); ++ if (broken_status != 0 && broken_status != 3) { ++ fill_ept_by_gpt(mmc, p_iptbl_ept); ++ free(disk_partition); ++ dcount = p_iptbl_ept->count; ++ disk_partition = calloc(1, PAD_TO_BLOCKSIZE(sizeof(struct disk_partition) * dcount, dev_desc)); ++ trans_ept_to_diskpart(p_iptbl_ept, disk_partition); ++ ret = gpt_restore(mmc_get_blk_desc(mmc), str_disk_guid, disk_partition, p_iptbl_ept->count); ++ if (broken_status == 1) ++ printf("The first gpt has been restore\n"); ++ else if (broken_status == 2) ++ printf("The second gpt has been restore\n"); ++ else ++ printf("Both gpt has been restore\n"); ++ } ++ ++ free(str_disk_guid); ++ free(disk_partition); ++#endif ++ /* init part again */ ++ apt_info("!!!! init part again\n"); ++ part_init(mmc_get_blk_desc(mmc)); ++ ++_out: ++#ifdef CONFIG_AML_PARTITION ++ if (p_iptbl_rsv) ++ _free_iptbl(p_iptbl_rsv); ++#endif ++ return ret; ++} ++ ++ ++struct partitions *find_mmc_partition_by_name (char const *name) ++{ ++ struct partitions *partition = NULL; ++ ++ apt_info("p_iptbl_ept %p\n", p_iptbl_ept); ++ if (NULL == p_iptbl_ept) { ++ goto _out; ++ } ++ partition = p_iptbl_ept->partitions; ++ partition = _find_partition_by_name(partition, ++ p_iptbl_ept->count, name); ++ apt_info("partition %p\n", partition); ++ if (!partition) { ++ partition = _find_partition_by_name(emmc_partition_table, ++ get_emmc_partition_arraysize(), name); ++ } ++ apt_info("partition %p\n", partition); ++_out: ++ return partition; ++} ++ ++/* ++ find virtual partition in inherent table. ++*/ ++int find_virtual_partition_by_name (char const *name, struct partitions *partition) ++{ ++ int ret = 0; ++ ulong offset; ++ struct virtual_partition *vpart = aml_get_virtual_partition_by_name(MMC_DTB_NAME); ++ if (NULL == partition) ++ return -1; ++ ++ offset = _get_inherent_offset(MMC_RESERVED_NAME); ++ if (-1 == offset) { ++ apt_err("can't find %s in inherent\n", MMC_RESERVED_NAME); ++ return -1; ++ } ++ ++ if (!strcmp(name, "dtb")) { ++ strcpy(partition->name, name); ++ partition->offset = offset + vpart->offset; ++ partition->size = (vpart->size * DTB_COPIES); ++ } ++ ++ return ret; ++} ++ ++int find_dev_num_by_partition_name (char const *name) ++{ ++ int dev = -1; ++ ++ /* card */ ++ if (!strcmp(name, MMC_CARD_PARTITION_NAME)) { ++ dev = 0; ++ } else { /* eMMC OR TSD */ ++ /* partition name is valid */ ++ if (find_mmc_partition_by_name(name)) { ++ dev = 1; ++ } ++ } ++ return dev; ++} ++ ++static inline uint64_t get_part_size(struct partitions *part, int num) ++{ ++ return part[num].size; ++} ++ ++static inline uint64_t get_part_offset(struct partitions *part, int num) ++{ ++ return part[num].offset; ++} ++ ++static inline char * get_part_name(struct partitions *part, int num) ++{ ++ return (char *)part[num].name; ++} ++ ++int get_part_info_from_tbl(struct blk_desc *dev_desc, ++ int num, struct disk_partition *info) ++{ ++ int ret = 0; ++ struct partitions *part; ++ ++ if (NULL == p_iptbl_ept) ++ return -1; ++ if (num > (p_iptbl_ept->count-1)) ++ return -1; ++ part = p_iptbl_ept->partitions; ++ ++ /*get partition info by index! */ ++ info->start = (lbaint_t)(get_part_offset(part, num)/dev_desc->blksz); ++ info->size = (lbaint_t)(get_part_size(part, num)/dev_desc->blksz); ++ info->blksz = dev_desc->blksz; ++ strcpy((char *)info->name, get_part_name(part, num)); ++ ++ return ret; ++} ++#if (CONFIG_MPT_DEBUG) ++void show_partition_info(struct disk_partition *info) ++{ ++ printf("----------%s----------\n", __func__); ++ printf("name %10s\n", info->name); ++ printf("blksz " LBAFU "\n", info->blksz); ++ printf("sart %ld\n", info->start); ++ printf("size %ld\n", info->size); ++ printf("----------end----------\n"); ++} ++#endif ++ ++ ++struct partitions *aml_get_partition_by_name(const char *name) ++{ ++ struct partitions *partition = NULL; ++ partition = _find_partition_by_name(emmc_partition_table, ++ get_emmc_partition_arraysize(), name); ++ if (partition == NULL) ++ apt_wrn("do not find match in inherent table %s\n", name); ++ return partition; ++} ++ ++struct virtual_partition *aml_get_virtual_partition_by_name(const char *name) ++{ ++ int i = 0, cnt; ++ struct virtual_partition *part = NULL; ++ cnt = get_emmc_virtual_partition_arraysize(); ++ while (i < cnt) { ++ ++ part = &virtual_partition_table[i]; ++ if (!strcmp(name, part->name)) { ++ apt_info("find %10s @ tbl[%d]\n", name, i); ++ break; ++ } ++ i++; ++ }; ++ if (i == cnt) { ++ part = NULL; ++ apt_wrn("do not find match in table %10s\n", name); ++ } ++ return part; ++} ++ ++int get_part_info_by_name(struct blk_desc *dev_desc, ++ const char *name, struct disk_partition *info) ++{ ++ struct partitions *partition = NULL; ++ struct partitions virtual; ++ int ret = 0; ++ cpu_id_t cpu_id = get_cpu_id(); ++ ++ partition = find_mmc_partition_by_name((char *)name); ++ if (partition) { ++ info->start = (lbaint_t)(partition->offset/dev_desc->blksz); ++ info->size = (lbaint_t)(partition->size/dev_desc->blksz); ++ info->blksz = dev_desc->blksz; ++ strcpy((char *)info->name, partition->name); ++ } else if (!find_virtual_partition_by_name((char *)name, &virtual)) { ++ /* try virtual partitions */ ++ apt_wrn("Got %s in virtual table\n", name); ++ info->start = (lbaint_t)(virtual.offset/dev_desc->blksz); ++ info->size = (lbaint_t)(virtual.size/dev_desc->blksz); ++ info->blksz = dev_desc->blksz; ++ strcpy((char *)info->name, virtual.name); ++ } else { ++ /* all partitions were tried, fail */ ++ ret = -1; ++ goto _out; ++ } ++ /* for bootloader */ ++ if ((0 == info->start) && (cpu_id.family_id >= MESON_CPU_MAJOR_ID_GXL)) { ++ info->start = 1; ++ info->size -= 1; ++ } ++ ++#if (CONFIG_MPT_DEBUG) ++ show_partition_info(info); ++#endif ++_out: ++ return ret; ++} ++ ++ ++/* ++ * get the partition number by name ++ * return value ++ * < 0 means no partition found ++ * >= 0 means valid partition ++ */ ++__weak int get_partition_num_by_name(char const *name) ++{ ++ int ret = -1; ++ struct partitions *partition = NULL; ++ ++ if (NULL == p_iptbl_ept) ++ goto _out; ++ partition = p_iptbl_ept->partitions; ++ ret = _get_part_index_by_name(partition, ++ p_iptbl_ept->count, name); ++_out: ++ return ret; ++} ++ ++/* ++ * get the partition info by number ++ * return value ++ * < 0 means no partition found ++ * >= 0 means valid partition ++ */ ++__weak struct partitions *get_partition_info_by_num(const int num) ++{ ++ struct partitions *partition = NULL; ++ ++ if ((NULL == p_iptbl_ept) ++ || (num >= p_iptbl_ept->count)) ++ goto _out; ++ partition = &p_iptbl_ept->partitions[num]; ++ ++_out: ++ return partition; ++} +diff --git a/drivers/mmc/mmc_aml copy.c b/drivers/mmc/mmc_aml copy.c +new file mode 100644 +index 00000000000..66c0203dc6d +--- /dev/null ++++ b/drivers/mmc/mmc_aml copy.c +@@ -0,0 +1,3299 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2008, Freescale Semiconductor, Inc ++ * Andy Fleming ++ * ++ * Based vaguely on the Linux code ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mmc_private.h" ++#include ++#include ++#include ++#include ++#include ++ ++struct aml_pattern aml_pattern_table[] = { ++ AML_PATTERN_ELEMENT(MMC_PATTERN_NAME, CALI_PATTERN), ++ AML_PATTERN_ELEMENT(MMC_MAGIC_NAME, MAGIC_PATTERN), ++ AML_PATTERN_ELEMENT(MMC_RANDOM_NAME, RANDOM_PATTERN), ++}; ++static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage); ++static int mmc_power_cycle(struct mmc *mmc); ++#if !CONFIG_IS_ENABLED(MMC_TINY) ++static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps); ++#endif ++ ++extern int emmc_probe(uint32_t init_flag); ++ ++bool emmckey_is_access_range_legal (struct mmc *mmc, ulong start, lbaint_t blkcnt) { ++ ulong key_start_blk, key_end_blk; ++ u64 key_glb_offset; ++ struct partitions * part = NULL; ++ struct virtual_partition *vpart = NULL; ++ if (IS_MMC(mmc)) { ++ vpart = aml_get_virtual_partition_by_name(MMC_KEY_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ key_glb_offset = part->offset + vpart->offset; ++ key_start_blk = (key_glb_offset / MMC_BLOCK_SIZE); ++ key_end_blk = ((key_glb_offset + vpart->size) / MMC_BLOCK_SIZE - 1); ++ if (!(info_disprotect & DISPROTECT_KEY)) { ++ if ((key_start_blk <= (start + blkcnt -1)) ++ && (key_end_blk >= start) ++ && (blkcnt != start)) { ++ pr_info("%s, keys %ld, keye %ld, start %ld, blkcnt %ld\n", ++ mmc->cfg->name, key_start_blk, ++ key_end_blk, start, blkcnt); ++ pr_err("Emmckey: Access range is illegal!\n"); ++ return 0; ++ } ++ } ++ } ++ return 1; ++} ++ ++int emmc_boot_chk(struct mmc *mmc) ++{ ++ u32 val = 0; ++ ++ if (strcmp(mmc->dev->name, "emmc")) ++ return 0; ++ ++ val = readl(SEC_AO_SEC_GP_CFG0); ++ pr_info("SEC_AO_SEC_GP_CFG0 = %x\n", val); ++ if ((val & 0xf) == 0x1) ++ return 1; ++ ++ return 0; ++} ++ ++#if CONFIG_IS_ENABLED(MMC_TINY) ++static struct mmc mmc_static; ++struct mmc *find_mmc_device(int dev_num) ++{ ++ return &mmc_static; ++} ++ ++void mmc_do_preinit(void) ++{ ++ struct mmc *m = &mmc_static; ++#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT ++ mmc_set_preinit(m, 1); ++#endif ++ if (m->preinit) ++ mmc_start_init(m); ++} ++ ++struct blk_desc *mmc_get_blk_desc(struct mmc *mmc) ++{ ++ return &mmc->block_dev; ++} ++#endif ++ ++#if !CONFIG_IS_ENABLED(DM_MMC) ++ ++#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) ++static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout) ++{ ++ return -ENOSYS; ++} ++#endif ++ ++__weak int board_mmc_getwp(struct mmc *mmc) ++{ ++ return -1; ++} ++ ++int mmc_getwp(struct mmc *mmc) ++{ ++ int wp; ++ ++ wp = board_mmc_getwp(mmc); ++ ++ if (wp < 0) { ++ if (mmc->cfg->ops->getwp) ++ wp = mmc->cfg->ops->getwp(mmc); ++ else ++ wp = 0; ++ } ++ ++ return wp; ++} ++ ++__weak int board_mmc_getcd(struct mmc *mmc) ++{ ++ return -1; ++} ++#endif ++ ++#ifdef CONFIG_MMC_TRACE ++void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd) ++{ ++ pr_info("CMD_SEND:%d\n", cmd->cmdidx); ++ pr_info("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); ++} ++ ++void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret) ++{ ++ int i; ++ u8 *ptr; ++ ++ if (ret) { ++ pr_info("\t\tRET\t\t\t %d\n", ret); ++ } else { ++ switch (cmd->resp_type) { ++ case MMC_RSP_NONE: ++ pr_info("\t\tMMC_RSP_NONE\n"); ++ break; ++ case MMC_RSP_R1: ++ pr_info("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", ++ cmd->response[0]); ++ break; ++ case MMC_RSP_R1b: ++ pr_info("\t\tMMC_RSP_R1b\t\t 0x%08X \n", ++ cmd->response[0]); ++ break; ++ case MMC_RSP_R2: ++ pr_info("\t\tMMC_RSP_R2\t\t 0x%08X \n", ++ cmd->response[0]); ++ pr_info("\t\t \t\t 0x%08X \n", ++ cmd->response[1]); ++ pr_info("\t\t \t\t 0x%08X \n", ++ cmd->response[2]); ++ pr_info("\t\t \t\t 0x%08X \n", ++ cmd->response[3]); ++ pr_info("\n"); ++ pr_info("\t\t\t\t\tDUMPING DATA\n"); ++ for (i = 0; i < 4; i++) { ++ int j; ++ pr_info("\t\t\t\t\t%03d - ", i*4); ++ ptr = (u8 *)&cmd->response[i]; ++ ptr += 3; ++ for (j = 0; j < 4; j++) ++ pr_info("%02X ", *ptr--); ++ pr_info("\n"); ++ } ++ break; ++ case MMC_RSP_R3: ++ pr_info("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", ++ cmd->response[0]); ++ break; ++ default: ++ pr_info("\t\tERROR MMC rsp not supported\n"); ++ break; ++ } ++ } ++} ++ ++void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd) ++{ ++ int status; ++ ++ status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9; ++ pr_info("CURR STATE:%d\n", status); ++} ++#endif ++ ++#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG) ++const char *mmc_mode_name(enum bus_mode mode) ++{ ++ static const char *const names[] = { ++ [MMC_LEGACY] = "MMC legacy", ++ [SD_LEGACY] = "SD Legacy", ++ [MMC_HS] = "MMC High Speed (26MHz)", ++ [SD_HS] = "SD High Speed (50MHz)", ++ [UHS_SDR12] = "UHS SDR12 (25MHz)", ++ [UHS_SDR25] = "UHS SDR25 (50MHz)", ++ [UHS_SDR50] = "UHS SDR50 (100MHz)", ++ [UHS_SDR104] = "UHS SDR104 (208MHz)", ++ [UHS_DDR50] = "UHS DDR50 (50MHz)", ++ [MMC_HS_52] = "MMC High Speed (52MHz)", ++ [MMC_DDR_52] = "MMC DDR52 (52MHz)", ++ [MMC_HS_200] = "HS200 (200MHz)", ++ [MMC_HS_400] = "HS400 (200MHz)", ++ }; ++ ++ if (mode >= MMC_MODES_END) ++ return "Unknown mode"; ++ else ++ return names[mode]; ++} ++#endif ++ ++static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode) ++{ ++ static const int freqs[] = { ++ [MMC_LEGACY] = 25000000, ++ [SD_LEGACY] = 25000000, ++ [MMC_HS] = 26000000, ++ [SD_HS] = 50000000, ++ [MMC_HS_52] = 52000000, ++ [MMC_DDR_52] = 52000000, ++ [UHS_SDR12] = 25000000, ++ [UHS_SDR25] = 50000000, ++ [UHS_SDR50] = 100000000, ++ [UHS_DDR50] = 50000000, ++ [UHS_SDR104] = 208000000, ++ [MMC_HS_200] = 200000000, ++ [MMC_HS_400] = 200000000, ++ }; ++ ++ if (mode == MMC_LEGACY) ++ return mmc->legacy_speed; ++ else if (mode >= MMC_MODES_END) ++ return 0; ++ else ++ return freqs[mode]; ++} ++ ++static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode) ++{ ++ mmc->selected_mode = mode; ++ mmc->tran_speed = mmc_mode2freq(mmc, mode); ++ mmc->ddr_mode = mmc_is_mode_ddr(mode); ++ pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode), ++ mmc->tran_speed / 1000000); ++ return 0; ++} ++ ++#if !CONFIG_IS_ENABLED(DM_MMC) ++int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) ++{ ++ int ret; ++ ++ mmmc_trace_before_send(mmc, cmd); ++ ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); ++ mmmc_trace_after_send(mmc, cmd, ret); ++ ++ return ret; ++} ++#endif ++ ++int mmc_send_status(struct mmc *mmc, int timeout) ++{ ++ struct mmc_cmd cmd; ++ int err, retries = 5; ++ int status; ++ cmd.cmdidx = MMC_CMD_SEND_STATUS; ++ cmd.resp_type = MMC_RSP_R1; ++ if (!mmc_host_is_spi(mmc)) ++ cmd.cmdarg = mmc->rca << 16; ++ ++ while (1) { ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ if (!err) { ++ if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && ++ (cmd.response[0] & MMC_STATUS_CURR_STATE) != ++ MMC_STATE_PRG) ++ break; ++ ++ if (cmd.response[0] & MMC_STATUS_MASK) { ++#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) ++ pr_err("Status Error: 0x%08X\n", ++ cmd.response[0]); ++#endif ++ return -ECOMM; ++ } ++ } else if (--retries < 0) ++ return err; ++ ++ if (timeout-- <= 0) ++ break; ++ ++ udelay(1000); ++ } ++ ++ mmc_trace_state(mmc, &cmd); ++ if (timeout <= 0) { ++#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) ++ pr_debug("Timeout waiting card ready\n"); ++#endif ++ return -ETIMEDOUT; ++ } ++ status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; ++ if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR) { ++ pr_err("mmc status switch error status =0x%x\n", status); ++ return -21; ++ } ++ return 0; ++} ++ ++int mmc_set_blocklen(struct mmc *mmc, int len) ++{ ++ struct mmc_cmd cmd; ++ int err; ++ ++ if (mmc->ddr_mode) ++ return 0; ++ ++ cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; ++ cmd.resp_type = MMC_RSP_R1; ++ cmd.cmdarg = len; ++ ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ ++#ifdef CONFIG_MMC_QUIRKS ++ if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) { ++ int retries = 4; ++ /* ++ * It has been seen that SET_BLOCKLEN may fail on the first ++ * attempt, let's try a few more time ++ */ ++ do { ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ if (!err) ++ break; ++ } while (retries--); ++ } ++#endif ++ ++ return err; ++} ++ ++#ifdef MMC_SUPPORTS_TUNING ++static const u8 tuning_blk_pattern_4bit[] = { ++ 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc, ++ 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef, ++ 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb, ++ 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef, ++ 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c, ++ 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee, ++ 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff, ++ 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde, ++}; ++ ++static const u8 tuning_blk_pattern_8bit[] = { ++ 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00, ++ 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc, ++ 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff, ++ 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff, ++ 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd, ++ 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb, ++ 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff, ++ 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff, ++ 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, ++ 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, ++ 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, ++ 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, ++ 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, ++ 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, ++ 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, ++ 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, ++}; ++ ++int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error) ++{ ++ struct mmc_cmd cmd; ++ struct mmc_data data; ++ const u8 *tuning_block_pattern; ++ int size, err; ++ ++ if (mmc->bus_width == 8) { ++ tuning_block_pattern = tuning_blk_pattern_8bit; ++ size = sizeof(tuning_blk_pattern_8bit); ++ } else if (mmc->bus_width == 4) { ++ tuning_block_pattern = tuning_blk_pattern_4bit; ++ size = sizeof(tuning_blk_pattern_4bit); ++ } else { ++ return -EINVAL; ++ } ++ ++ ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size); ++ ++ cmd.cmdidx = opcode; ++ cmd.cmdarg = 0; ++ cmd.resp_type = MMC_RSP_R1; ++ ++ data.dest = (void *)data_buf; ++ data.blocks = 1; ++ data.blocksize = size; ++ data.flags = MMC_DATA_READ; ++ ++ err = mmc_send_cmd(mmc, &cmd, &data); ++ if (err) ++ return err; ++ ++ if (memcmp(data_buf, tuning_block_pattern, size)) ++ return -EIO; ++ ++ return 0; ++} ++#endif ++ ++static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, ++ lbaint_t blkcnt) ++{ ++ struct mmc_cmd cmd; ++ struct mmc_data data; ++ ++ if (blkcnt > 1) ++ cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; ++ else ++ cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; ++ ++ if (mmc->high_capacity) ++ cmd.cmdarg = start; ++ else ++ cmd.cmdarg = start * mmc->read_bl_len; ++ ++ cmd.resp_type = MMC_RSP_R1; ++ ++ data.dest = dst; ++ data.blocks = blkcnt; ++ data.blocksize = mmc->read_bl_len; ++ data.flags = MMC_DATA_READ; ++ ++ if (mmc_send_cmd(mmc, &cmd, &data)) ++ return 0; ++ ++ if (blkcnt > 1) { ++ cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; ++ cmd.cmdarg = 0; ++ cmd.resp_type = MMC_RSP_R1b; ++ if (mmc_send_cmd(mmc, &cmd, NULL)) { ++#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) ++ pr_err("mmc fail to send stop cmd\n"); ++#endif ++ return 0; ++ } ++ } ++ ++ return blkcnt; ++} ++ ++#if CONFIG_IS_ENABLED(BLK) ++ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst) ++#else ++ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, ++ void *dst) ++#endif ++{ ++#if CONFIG_IS_ENABLED(BLK) ++ struct blk_desc *block_dev = dev_get_uclass_platdata(dev); ++#endif ++ int dev_num = block_dev->devnum; ++ int err; ++ lbaint_t cur, blocks_todo = blkcnt; ++ ++ if (blkcnt == 0) ++ return 0; ++ ++ struct mmc *mmc = find_mmc_device(dev_num); ++ if (!mmc) ++ return 0; ++ ++ if (CONFIG_IS_ENABLED(MMC_TINY)) ++ err = mmc_switch_part(mmc, block_dev->hwpart); ++ else ++ err = blk_dselect_hwpart(block_dev, block_dev->hwpart); ++ ++ if (err < 0) ++ return 0; ++ ++ if ((start + blkcnt) > block_dev->lba) { ++#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) ++ pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", ++ start + blkcnt, block_dev->lba); ++#endif ++ return 0; ++ } ++ ++ if (mmc_set_blocklen(mmc, mmc->read_bl_len)) { ++ pr_debug("%s: Failed to set blocklen\n", __func__); ++ return 0; ++ } ++ if (!emmckey_is_access_range_legal(mmc, start, blkcnt)) ++ return 0; ++ ++ do { ++ cur = (blocks_todo > mmc->cfg->b_max) ? ++ mmc->cfg->b_max : blocks_todo; ++ if (mmc_read_blocks(mmc, dst, start, cur) != cur) { ++ pr_debug("%s: Failed to read blocks\n", __func__); ++ return 0; ++ } ++ blocks_todo -= cur; ++ start += cur; ++ dst += cur * mmc->read_bl_len; ++ } while (blocks_todo > 0); ++ ++ return blkcnt; ++} ++ ++static int mmc_go_idle(struct mmc *mmc) ++{ ++ struct mmc_cmd cmd; ++ int err; ++ ++ udelay(1000); ++ ++ cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; ++ cmd.cmdarg = 0; ++ cmd.resp_type = MMC_RSP_NONE; ++ ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ ++ if (err) ++ return err; ++ ++ udelay(2000); ++ ++ return 0; ++} ++ ++#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) ++static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage) ++{ ++ struct mmc_cmd cmd; ++ int err = 0; ++ ++ /* ++ * Send CMD11 only if the request is to switch the card to ++ * 1.8V signalling. ++ */ ++ if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) ++ return mmc_set_signal_voltage(mmc, signal_voltage); ++ ++ cmd.cmdidx = SD_CMD_SWITCH_UHS18V; ++ cmd.cmdarg = 0; ++ cmd.resp_type = MMC_RSP_R1; ++ ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ if (err) ++ return err; ++ ++ if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR)) ++ return -EIO; ++ ++ /* ++ * The card should drive cmd and dat[0:3] low immediately ++ * after the response of cmd11, but wait 100 us to be sure ++ */ ++ err = mmc_wait_dat0(mmc, 0, 100); ++ if (err == -ENOSYS) ++ udelay(100); ++ else if (err) ++ return -ETIMEDOUT; ++ ++ /* ++ * During a signal voltage level switch, the clock must be gated ++ * for 5 ms according to the SD spec ++ */ ++ mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE); ++ ++ err = mmc_set_signal_voltage(mmc, signal_voltage); ++ if (err) ++ return err; ++ ++ /* Keep clock gated for at least 10 ms, though spec only says 5 ms */ ++ mdelay(10); ++ mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE); ++ ++ /* ++ * Failure to switch is indicated by the card holding ++ * dat[0:3] low. Wait for at least 1 ms according to spec ++ */ ++ err = mmc_wait_dat0(mmc, 1, 1000); ++ if (err == -ENOSYS) ++ udelay(1000); ++ else if (err) ++ return -ETIMEDOUT; ++ ++ return 0; ++} ++#endif ++ ++static int sd_send_op_cond(struct mmc *mmc, bool uhs_en) ++{ ++ int timeout = 1000; ++ int err; ++ struct mmc_cmd cmd; ++ ++ while (1) { ++ cmd.cmdidx = MMC_CMD_APP_CMD; ++ cmd.resp_type = MMC_RSP_R1; ++ cmd.cmdarg = 0; ++ ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ ++ if (err) ++ return err; ++ ++ cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; ++ cmd.resp_type = MMC_RSP_R3; ++ ++ /* ++ * Most cards do not answer if some reserved bits ++ * in the ocr are set. However, Some controller ++ * can set bit 7 (reserved for low voltages), but ++ * how to manage low voltages SD card is not yet ++ * specified. ++ */ ++ cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : ++ (mmc->cfg->voltages & 0xff8000); ++ ++ if (mmc->version == SD_VERSION_2) ++ cmd.cmdarg |= OCR_HCS; ++ ++ if (uhs_en) ++ cmd.cmdarg |= OCR_S18R; ++ ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ ++ if (err) ++ return err; ++ ++ if (cmd.response[0] & OCR_BUSY) ++ break; ++ ++ if (timeout-- <= 0) ++ return -EOPNOTSUPP; ++ ++ udelay(1000); ++ } ++ ++ if (mmc->version != SD_VERSION_2) ++ mmc->version = SD_VERSION_1_0; ++ ++ if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ ++ cmd.cmdidx = MMC_CMD_SPI_READ_OCR; ++ cmd.resp_type = MMC_RSP_R3; ++ cmd.cmdarg = 0; ++ ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ ++ if (err) ++ return err; ++ } ++ ++ mmc->ocr = cmd.response[0]; ++ ++#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) ++ if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000) ++ == 0x41000000) { ++ err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180); ++ if (err) ++ return err; ++ } ++#endif ++ ++ mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); ++ mmc->rca = 0; ++ ++ return 0; ++} ++ ++static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg) ++{ ++ struct mmc_cmd cmd; ++ int err; ++ ++ cmd.cmdidx = MMC_CMD_SEND_OP_COND; ++ cmd.resp_type = MMC_RSP_R3; ++ cmd.cmdarg = 0; ++ if (use_arg && !mmc_host_is_spi(mmc)) ++ cmd.cmdarg = OCR_HCS | ++ (mmc->cfg->voltages & ++ (mmc->ocr & OCR_VOLTAGE_MASK)) | ++ (mmc->ocr & OCR_ACCESS_MODE); ++ ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ if (err) ++ return err; ++ mmc->ocr = cmd.response[0]; ++ return 0; ++} ++ ++static int mmc_send_op_cond(struct mmc *mmc) ++{ ++ int err, i; ++ ++ /* Some cards seem to need this */ ++ mmc_go_idle(mmc); ++ ++ /* Asking to the card its capabilities */ ++ for (i = 0; i < 2; i++) { ++ err = mmc_send_op_cond_iter(mmc, i != 0); ++ if (err) ++ return err; ++ ++ /* exit if not busy (flag seems to be inverted) */ ++ if (mmc->ocr & OCR_BUSY) ++ break; ++ } ++ mmc->op_cond_pending = 1; ++ return 0; ++} ++ ++static int mmc_complete_op_cond(struct mmc *mmc) ++{ ++ struct mmc_cmd cmd; ++ int timeout = 1000; ++ ulong start; ++ int err; ++ ++ mmc->op_cond_pending = 0; ++ if (!(mmc->ocr & OCR_BUSY)) { ++ /* Some cards seem to need this */ ++ mmc_go_idle(mmc); ++ ++ start = get_timer(0); ++ while (1) { ++ err = mmc_send_op_cond_iter(mmc, 1); ++ if (err) ++ return err; ++ if (mmc->ocr & OCR_BUSY) ++ break; ++ if (get_timer(start) > timeout) ++ return -EOPNOTSUPP; ++ udelay(100); ++ } ++ } ++ ++ if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ ++ cmd.cmdidx = MMC_CMD_SPI_READ_OCR; ++ cmd.resp_type = MMC_RSP_R3; ++ cmd.cmdarg = 0; ++ ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ ++ if (err) ++ return err; ++ ++ mmc->ocr = cmd.response[0]; ++ } ++ ++ mmc->version = MMC_VERSION_UNKNOWN; ++ ++ mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); ++ mmc->rca = 1; ++ ++ return 0; ++} ++ ++static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) ++{ ++ struct mmc_cmd cmd; ++ struct mmc_data data; ++ int err; ++ ++ /* Get the Card Status Register */ ++ cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; ++ cmd.resp_type = MMC_RSP_R1; ++ cmd.cmdarg = 0; ++ ++ data.dest = (char *)ext_csd; ++ data.blocks = 1; ++ data.blocksize = MMC_MAX_BLOCK_LEN; ++ data.flags = MMC_DATA_READ; ++ ++ err = mmc_send_cmd(mmc, &cmd, &data); ++ ++ return err; ++} ++ ++int mmc_get_ext_csd(struct mmc *mmc, u8 *ext_csd) ++{ ++ return mmc_send_ext_csd(mmc, ext_csd); ++} ++ ++int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) ++{ ++ struct mmc_cmd cmd; ++ int timeout = 1000; ++ int retries = 3; ++ int ret; ++ ++ cmd.cmdidx = MMC_CMD_SWITCH; ++ cmd.resp_type = MMC_RSP_R1b; ++ cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | ++ (index << 16) | ++ (value << 8); ++ ++ while (retries > 0) { ++ ret = mmc_send_cmd(mmc, &cmd, NULL); ++ ++ /* Waiting for the ready status */ ++ if (!ret) { ++ ret = mmc_send_status(mmc, timeout); ++ return ret; ++ } ++ ++ retries--; ++ } ++ ++ return ret; ++ ++} ++ ++#if !CONFIG_IS_ENABLED(MMC_TINY) ++u8 ext_csd_w[] = {191, 187, 185, 183, 179, 178, 177, 175, ++ 173, 171, 169, 167, 165, 164, 163, 162, ++ 161, 156, 155, 143, 140, 136, 134, 133, ++ 132, 131, 62, 59, 56, 52, 37, 34, ++ 33, 32, 31, 30, 29, 22, 17, 16, 15}; ++ ++int mmc_set_ext_csd(struct mmc *mmc, u8 index, u8 value) ++{ ++ int ret = -21, i; ++ ++ for (i = 0; i < sizeof(ext_csd_w); i++) { ++ if (ext_csd_w[i] == index) ++ break; ++ } ++ if (i != sizeof(ext_csd_w)) ++ ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, index, value); ++ ++ return ret; ++} ++ ++static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode) ++{ ++ int err; ++ int speed_bits; ++ ++ ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); ++ ++ switch (mode) { ++ case MMC_HS: ++ case MMC_HS_52: ++ case MMC_DDR_52: ++ speed_bits = EXT_CSD_TIMING_HS; ++ break; ++#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) ++ case MMC_HS_200: ++ speed_bits = EXT_CSD_TIMING_HS200; ++ break; ++#endif ++#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) ++ case MMC_HS_400: ++ speed_bits = EXT_CSD_TIMING_HS400; ++ break; ++#endif ++ case MMC_LEGACY: ++ speed_bits = EXT_CSD_TIMING_LEGACY; ++ break; ++ default: ++ return -EINVAL; ++ } ++ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, ++ speed_bits); ++ if (err) ++ return err; ++ ++ if ((mode == MMC_HS) || (mode == MMC_HS_52)) { ++ /* Now check to see that it worked */ ++ err = mmc_send_ext_csd(mmc, test_csd); ++ if (err) ++ return err; ++ ++ /* No high-speed support */ ++ if (!test_csd[EXT_CSD_HS_TIMING]) ++ return -ENOTSUPP; ++ } ++ ++ return 0; ++} ++ ++static int mmc_get_capabilities(struct mmc *mmc) ++{ ++ u8 *ext_csd = mmc->ext_csd; ++ char cardtype; ++ ++ mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY); ++ ++ if (mmc_host_is_spi(mmc)) ++ return 0; ++ ++ /* Only version 4 supports high-speed */ ++ if (mmc->version < MMC_VERSION_4) ++ return 0; ++ ++ if (!ext_csd) { ++ pr_err("No ext_csd found!\n"); /* this should enver happen */ ++ return -ENOTSUPP; ++ } ++ ++ mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; ++ ++ cardtype = ext_csd[EXT_CSD_CARD_TYPE]; ++ mmc->cardtype = cardtype; ++ ++#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) ++ if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V | ++ EXT_CSD_CARD_TYPE_HS200_1_8V)) { ++ mmc->card_caps |= MMC_MODE_HS200; ++ } ++#endif ++#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) ++ if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V | ++ EXT_CSD_CARD_TYPE_HS400_1_8V)) { ++ mmc->card_caps |= MMC_MODE_HS400; ++ } ++#endif ++ if (cardtype & EXT_CSD_CARD_TYPE_52) { ++ if (cardtype & EXT_CSD_CARD_TYPE_DDR_52) ++ mmc->card_caps |= MMC_MODE_DDR_52MHz; ++ mmc->card_caps |= MMC_MODE_HS_52MHz; ++ } ++ if (cardtype & EXT_CSD_CARD_TYPE_26) ++ mmc->card_caps |= MMC_MODE_HS; ++ ++ return 0; ++} ++#endif ++ ++static int mmc_set_capacity(struct mmc *mmc, int part_num) ++{ ++ switch (part_num) { ++ case 0: ++ mmc->capacity = mmc->capacity_user; ++ break; ++ case 1: ++ case 2: ++ mmc->capacity = mmc->capacity_boot; ++ break; ++ case 3: ++ mmc->capacity = mmc->capacity_rpmb; ++ break; ++ case 4: ++ case 5: ++ case 6: ++ case 7: ++ mmc->capacity = mmc->capacity_gp[part_num - 4]; ++ break; ++ default: ++ return -1; ++ } ++ ++ mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len); ++ ++ return 0; ++} ++ ++int mmc_switch_part(struct mmc *mmc, unsigned int part_num) ++{ ++ int ret; ++ ++ ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, ++ (mmc->part_config & ~PART_ACCESS_MASK) ++ | (part_num & PART_ACCESS_MASK)); ++ ++ /* ++ * Set the capacity if the switch succeeded or was intended ++ * to return to representing the raw device. ++ */ ++ if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) { ++ ret = mmc_set_capacity(mmc, part_num); ++ mmc_get_blk_desc(mmc)->hwpart = part_num; ++ } ++ ++ return ret; ++} ++ ++#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING) ++int mmc_hwpart_config(struct mmc *mmc, ++ const struct mmc_hwpart_conf *conf, ++ enum mmc_hwpart_conf_mode mode) ++{ ++ u8 part_attrs = 0; ++ u32 enh_size_mult; ++ u32 enh_start_addr; ++ u32 gp_size_mult[4]; ++ u32 max_enh_size_mult; ++ u32 tot_enh_size_mult = 0; ++ u8 wr_rel_set; ++ int i, pidx, err; ++ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); ++ ++ if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) ++ return -EINVAL; ++ ++ if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { ++ pr_err("eMMC >= 4.4 required for enhanced user data area\n"); ++ return -EMEDIUMTYPE; ++ } ++ ++ if (!(mmc->part_support & PART_SUPPORT)) { ++ pr_err("Card does not support partitioning\n"); ++ return -EMEDIUMTYPE; ++ } ++ ++ if (!mmc->hc_wp_grp_size) { ++ pr_err("Card does not define HC WP group size\n"); ++ return -EMEDIUMTYPE; ++ } ++ ++ /* check partition alignment and total enhanced size */ ++ if (conf->user.enh_size) { ++ if (conf->user.enh_size % mmc->hc_wp_grp_size || ++ conf->user.enh_start % mmc->hc_wp_grp_size) { ++ pr_err("User data enhanced area not HC WP group " ++ "size aligned\n"); ++ return -EINVAL; ++ } ++ part_attrs |= EXT_CSD_ENH_USR; ++ enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; ++ if (mmc->high_capacity) { ++ enh_start_addr = conf->user.enh_start; ++ } else { ++ enh_start_addr = (conf->user.enh_start << 9); ++ } ++ } else { ++ enh_size_mult = 0; ++ enh_start_addr = 0; ++ } ++ tot_enh_size_mult += enh_size_mult; ++ ++ for (pidx = 0; pidx < 4; pidx++) { ++ if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { ++ pr_err("GP%i partition not HC WP group size " ++ "aligned\n", pidx+1); ++ return -EINVAL; ++ } ++ gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; ++ if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { ++ part_attrs |= EXT_CSD_ENH_GP(pidx); ++ tot_enh_size_mult += gp_size_mult[pidx]; ++ } ++ } ++ ++ if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { ++ pr_err("Card does not support enhanced attribute\n"); ++ return -EMEDIUMTYPE; ++ } ++ ++ err = mmc_send_ext_csd(mmc, ext_csd); ++ if (err) ++ return err; ++ ++ max_enh_size_mult = ++ (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + ++ (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + ++ ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; ++ if (tot_enh_size_mult > max_enh_size_mult) { ++ pr_err("Total enhanced size exceeds maximum (%u > %u)\n", ++ tot_enh_size_mult, max_enh_size_mult); ++ return -EMEDIUMTYPE; ++ } ++ ++ /* The default value of EXT_CSD_WR_REL_SET is device ++ * dependent, the values can only be changed if the ++ * EXT_CSD_HS_CTRL_REL bit is set. The values can be ++ * changed only once and before partitioning is completed. */ ++ wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; ++ if (conf->user.wr_rel_change) { ++ if (conf->user.wr_rel_set) ++ wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; ++ else ++ wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; ++ } ++ for (pidx = 0; pidx < 4; pidx++) { ++ if (conf->gp_part[pidx].wr_rel_change) { ++ if (conf->gp_part[pidx].wr_rel_set) ++ wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); ++ else ++ wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); ++ } ++ } ++ ++ if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && ++ !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { ++ puts("Card does not support host controlled partition write " ++ "reliability settings\n"); ++ return -EMEDIUMTYPE; ++ } ++ ++ if (ext_csd[EXT_CSD_PARTITION_SETTING] & ++ EXT_CSD_PARTITION_SETTING_COMPLETED) { ++ pr_err("Card already partitioned\n"); ++ return -EPERM; ++ } ++ ++ if (mode == MMC_HWPART_CONF_CHECK) ++ return 0; ++ ++ /* Partitioning requires high-capacity size definitions */ ++ if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { ++ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, ++ EXT_CSD_ERASE_GROUP_DEF, 1); ++ ++ if (err) ++ return err; ++ ++ ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; ++ ++ /* update erase group size to be high-capacity */ ++ mmc->erase_grp_size = ++ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; ++ } ++ ++ /* all OK, write the configuration */ ++ for (i = 0; i < 4; i++) { ++ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, ++ EXT_CSD_ENH_START_ADDR+i, ++ (enh_start_addr >> (i*8)) & 0xFF); ++ if (err) ++ return err; ++ } ++ for (i = 0; i < 3; i++) { ++ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, ++ EXT_CSD_ENH_SIZE_MULT+i, ++ (enh_size_mult >> (i*8)) & 0xFF); ++ if (err) ++ return err; ++ } ++ for (pidx = 0; pidx < 4; pidx++) { ++ for (i = 0; i < 3; i++) { ++ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, ++ EXT_CSD_GP_SIZE_MULT+pidx*3+i, ++ (gp_size_mult[pidx] >> (i*8)) & 0xFF); ++ if (err) ++ return err; ++ } ++ } ++ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, ++ EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); ++ if (err) ++ return err; ++ ++ if (mode == MMC_HWPART_CONF_SET) ++ return 0; ++ ++ /* The WR_REL_SET is a write-once register but shall be ++ * written before setting PART_SETTING_COMPLETED. As it is ++ * write-once we can only write it when completing the ++ * partitioning. */ ++ if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { ++ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, ++ EXT_CSD_WR_REL_SET, wr_rel_set); ++ if (err) ++ return err; ++ } ++ ++ /* Setting PART_SETTING_COMPLETED confirms the partition ++ * configuration but it only becomes effective after power ++ * cycle, so we do not adjust the partition related settings ++ * in the mmc struct. */ ++ ++ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, ++ EXT_CSD_PARTITION_SETTING, ++ EXT_CSD_PARTITION_SETTING_COMPLETED); ++ if (err) ++ return err; ++ ++ return 0; ++} ++#endif ++ ++#if !CONFIG_IS_ENABLED(DM_MMC) ++int mmc_getcd(struct mmc *mmc) ++{ ++ int cd; ++ ++ cd = board_mmc_getcd(mmc); ++ ++ if (cd < 0) { ++ if (mmc->cfg->ops->getcd) ++ cd = mmc->cfg->ops->getcd(mmc); ++ else ++ cd = 1; ++ } ++ ++ return cd; ++} ++#endif ++ ++#if !CONFIG_IS_ENABLED(MMC_TINY) ++static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) ++{ ++ struct mmc_cmd cmd; ++ struct mmc_data data; ++ ++ /* Switch the frequency */ ++ cmd.cmdidx = SD_CMD_SWITCH_FUNC; ++ cmd.resp_type = MMC_RSP_R1; ++ cmd.cmdarg = (mode << 31) | 0xffffff; ++ cmd.cmdarg &= ~(0xf << (group * 4)); ++ cmd.cmdarg |= value << (group * 4); ++ ++ data.dest = (char *)resp; ++ data.blocksize = 64; ++ data.blocks = 1; ++ data.flags = MMC_DATA_READ; ++ ++ return mmc_send_cmd(mmc, &cmd, &data); ++} ++ ++static int sd_get_capabilities(struct mmc *mmc) ++{ ++ int err; ++ struct mmc_cmd cmd; ++ ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2); ++ ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16); ++ struct mmc_data data; ++ int timeout; ++#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) ++ u32 sd3_bus_mode; ++#endif ++ ++ mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY); ++ ++ if (mmc_host_is_spi(mmc)) ++ return 0; ++ ++ /* Read the SCR to find out if this card supports higher speeds */ ++ cmd.cmdidx = MMC_CMD_APP_CMD; ++ cmd.resp_type = MMC_RSP_R1; ++ cmd.cmdarg = mmc->rca << 16; ++ ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ ++ if (err) ++ return err; ++ ++ cmd.cmdidx = SD_CMD_APP_SEND_SCR; ++ cmd.resp_type = MMC_RSP_R1; ++ cmd.cmdarg = 0; ++ ++ timeout = 3; ++ ++retry_scr: ++ data.dest = (char *)scr; ++ data.blocksize = 8; ++ data.blocks = 1; ++ data.flags = MMC_DATA_READ; ++ ++ err = mmc_send_cmd(mmc, &cmd, &data); ++ ++ if (err) { ++ if (timeout--) ++ goto retry_scr; ++ ++ return err; ++ } ++ ++ mmc->scr[0] = __be32_to_cpu(scr[0]); ++ mmc->scr[1] = __be32_to_cpu(scr[1]); ++ ++ switch ((mmc->scr[0] >> 24) & 0xf) { ++ case 0: ++ mmc->version = SD_VERSION_1_0; ++ break; ++ case 1: ++ mmc->version = SD_VERSION_1_10; ++ break; ++ case 2: ++ mmc->version = SD_VERSION_2; ++ if ((mmc->scr[0] >> 15) & 0x1) ++ mmc->version = SD_VERSION_3; ++ break; ++ default: ++ mmc->version = SD_VERSION_1_0; ++ break; ++ } ++ ++ if (mmc->scr[0] & SD_DATA_4BIT) ++ mmc->card_caps |= MMC_MODE_4BIT; ++ ++ /* Version 1.0 doesn't support switching */ ++ if (mmc->version == SD_VERSION_1_0) ++ return 0; ++ ++ timeout = 4; ++ while (timeout--) { ++ err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, ++ (u8 *)switch_status); ++ ++ if (err) ++ return err; ++ ++ /* The high-speed function is busy. Try again */ ++ if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) ++ break; ++ } ++ ++ /* If high-speed isn't supported, we return */ ++ if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED) ++ mmc->card_caps |= MMC_CAP(SD_HS); ++ ++#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) ++ /* Version before 3.0 don't support UHS modes */ ++ if (mmc->version < SD_VERSION_3) ++ return 0; ++ ++ sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f; ++ if (sd3_bus_mode & SD_MODE_UHS_SDR104) ++ mmc->card_caps |= MMC_CAP(UHS_SDR104); ++ if (sd3_bus_mode & SD_MODE_UHS_SDR50) ++ mmc->card_caps |= MMC_CAP(UHS_SDR50); ++ if (sd3_bus_mode & SD_MODE_UHS_SDR25) ++ mmc->card_caps |= MMC_CAP(UHS_SDR25); ++ if (sd3_bus_mode & SD_MODE_UHS_SDR12) ++ mmc->card_caps |= MMC_CAP(UHS_SDR12); ++ if (sd3_bus_mode & SD_MODE_UHS_DDR50) ++ mmc->card_caps |= MMC_CAP(UHS_DDR50); ++#endif ++ ++ return 0; ++} ++ ++static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode) ++{ ++ int err; ++ ++ ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); ++ int speed; ++ ++ /* SD version 1.00 and 1.01 does not support CMD 6 */ ++ if (mmc->version == SD_VERSION_1_0) ++ return 0; ++ ++ switch (mode) { ++ case SD_LEGACY: ++ speed = UHS_SDR12_BUS_SPEED; ++ break; ++ case SD_HS: ++ speed = HIGH_SPEED_BUS_SPEED; ++ break; ++#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) ++ case UHS_SDR12: ++ speed = UHS_SDR12_BUS_SPEED; ++ break; ++ case UHS_SDR25: ++ speed = UHS_SDR25_BUS_SPEED; ++ break; ++ case UHS_SDR50: ++ speed = UHS_SDR50_BUS_SPEED; ++ break; ++ case UHS_DDR50: ++ speed = UHS_DDR50_BUS_SPEED; ++ break; ++ case UHS_SDR104: ++ speed = UHS_SDR104_BUS_SPEED; ++ break; ++#endif ++ default: ++ return -EINVAL; ++ } ++ ++ err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status); ++ if (err) ++ return err; ++ ++ if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed) ++ return -ENOTSUPP; ++ ++ return 0; ++} ++ ++static int sd_select_bus_width(struct mmc *mmc, int w) ++{ ++ int err; ++ struct mmc_cmd cmd; ++ ++ if ((w != 4) && (w != 1)) ++ return -EINVAL; ++ ++ cmd.cmdidx = MMC_CMD_APP_CMD; ++ cmd.resp_type = MMC_RSP_R1; ++ cmd.cmdarg = mmc->rca << 16; ++ ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ if (err) ++ return err; ++ ++ cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; ++ cmd.resp_type = MMC_RSP_R1; ++ if (w == 4) ++ cmd.cmdarg = 2; ++ else if (w == 1) ++ cmd.cmdarg = 0; ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ if (err) ++ return err; ++ ++ return 0; ++} ++#endif ++ ++#if CONFIG_IS_ENABLED(MMC_WRITE) ++static int sd_read_ssr(struct mmc *mmc) ++{ ++ static const unsigned int sd_au_size[] = { ++ 0, SZ_16K / 512, SZ_32K / 512, ++ SZ_64K / 512, SZ_128K / 512, SZ_256K / 512, ++ SZ_512K / 512, SZ_1M / 512, SZ_2M / 512, ++ SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512, ++ SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, ++ SZ_64M / 512, ++ }; ++ int err, i; ++ struct mmc_cmd cmd; ++ ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16); ++ struct mmc_data data; ++ int timeout = 3; ++ unsigned int au, eo, et, es; ++ ++ cmd.cmdidx = MMC_CMD_APP_CMD; ++ cmd.resp_type = MMC_RSP_R1; ++ cmd.cmdarg = mmc->rca << 16; ++ ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ if (err) ++ return err; ++ ++ cmd.cmdidx = SD_CMD_APP_SD_STATUS; ++ cmd.resp_type = MMC_RSP_R1; ++ cmd.cmdarg = 0; ++ ++retry_ssr: ++ data.dest = (char *)ssr; ++ data.blocksize = 64; ++ data.blocks = 1; ++ data.flags = MMC_DATA_READ; ++ ++ err = mmc_send_cmd(mmc, &cmd, &data); ++ if (err) { ++ if (timeout--) ++ goto retry_ssr; ++ ++ return err; ++ } ++ ++ for (i = 0; i < 16; i++) ++ ssr[i] = be32_to_cpu(ssr[i]); ++ ++ au = (ssr[2] >> 12) & 0xF; ++ if ((au <= 9) || (mmc->version == SD_VERSION_3)) { ++ mmc->ssr.au = sd_au_size[au]; ++ es = (ssr[3] >> 24) & 0xFF; ++ es |= (ssr[2] & 0xFF) << 8; ++ et = (ssr[3] >> 18) & 0x3F; ++ if (es && et) { ++ eo = (ssr[3] >> 16) & 0x3; ++ mmc->ssr.erase_timeout = (et * 1000) / es; ++ mmc->ssr.erase_offset = eo * 1000; ++ } ++ } else { ++ pr_debug("Invalid Allocation Unit Size.\n"); ++ } ++ ++ return 0; ++} ++#endif ++/* frequency bases */ ++/* divided by 10 to be nice to platforms without floating point */ ++static const int fbase[] = { ++ 10000, ++ 100000, ++ 1000000, ++ 10000000, ++}; ++ ++/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice ++ * to platforms without floating point. ++ */ ++static const u8 multipliers[] = { ++ 0, /* reserved */ ++ 10, ++ 12, ++ 13, ++ 15, ++ 20, ++ 25, ++ 30, ++ 35, ++ 40, ++ 45, ++ 50, ++ 55, ++ 60, ++ 70, ++ 80, ++}; ++ ++static inline int bus_width(uint cap) ++{ ++ if (cap == MMC_MODE_8BIT) ++ return 8; ++ if (cap == MMC_MODE_4BIT) ++ return 4; ++ if (cap == MMC_MODE_1BIT) ++ return 1; ++ pr_warn("invalid bus witdh capability 0x%x\n", cap); ++ return 0; ++} ++ ++#if !CONFIG_IS_ENABLED(DM_MMC) ++#ifdef MMC_SUPPORTS_TUNING ++static int mmc_execute_tuning(struct mmc *mmc, uint opcode) ++{ ++ return -ENOTSUPP; ++} ++#endif ++ ++static void mmc_send_init_stream(struct mmc *mmc) ++{ ++} ++ ++static int mmc_set_ios(struct mmc *mmc) ++{ ++ int ret = 0; ++ ++ if (mmc->cfg->ops->set_ios) ++ ret = mmc->cfg->ops->set_ios(mmc); ++ ++ return ret; ++} ++#endif ++ ++int mmc_set_clock(struct mmc *mmc, uint clock, bool disable) ++{ ++ if (!disable) { ++ if (clock > mmc->cfg->f_max) ++ clock = mmc->cfg->f_max; ++ ++ if (clock < mmc->cfg->f_min) ++ clock = mmc->cfg->f_min; ++ } ++ ++ mmc->clock = clock; ++ mmc->clk_disable = disable; ++ ++ pr_debug("clock is %s (%dHz)\n", ++ disable ? "disabled" : "enabled", clock); ++ ++ return mmc_set_ios(mmc); ++} ++ ++static int mmc_set_bus_width(struct mmc *mmc, uint width) ++{ ++ mmc->bus_width = width; ++ ++ return mmc_set_ios(mmc); ++} ++ ++#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG) ++/* ++ * helper function to display the capabilities in a human ++ * friendly manner. The capabilities include bus width and ++ * supported modes. ++ */ ++void mmc_dump_capabilities(const char *text, uint caps) ++{ ++ enum bus_mode mode; ++ ++ pr_debug("%s: widths [", text); ++ if (caps & MMC_MODE_8BIT) ++ pr_debug("8, "); ++ if (caps & MMC_MODE_4BIT) ++ pr_debug("4, "); ++ if (caps & MMC_MODE_1BIT) ++ pr_debug("1, "); ++ pr_debug("\b\b] modes ["); ++ for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++) ++ if (MMC_CAP(mode) & caps) ++ pr_debug("%s, ", mmc_mode_name(mode)); ++ pr_debug("\b\b]\n"); ++} ++#endif ++ ++struct mode_width_tuning { ++ enum bus_mode mode; ++ uint widths; ++#ifdef MMC_SUPPORTS_TUNING ++ uint tuning; ++#endif ++}; ++ ++#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE) ++int mmc_voltage_to_mv(enum mmc_voltage voltage) ++{ ++ switch (voltage) { ++ case MMC_SIGNAL_VOLTAGE_000: return 0; ++ case MMC_SIGNAL_VOLTAGE_330: return 3300; ++ case MMC_SIGNAL_VOLTAGE_180: return 1800; ++ case MMC_SIGNAL_VOLTAGE_120: return 1200; ++ } ++ return -EINVAL; ++} ++ ++static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage) ++{ ++ int err; ++ ++ if (mmc->signal_voltage == signal_voltage) ++ return 0; ++ ++ mmc->signal_voltage = signal_voltage; ++ err = mmc_set_ios(mmc); ++ if (err) ++ pr_debug("unable to set voltage (err %d)\n", err); ++ ++ return err; ++} ++#else ++static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage) ++{ ++ return 0; ++} ++#endif ++ ++#if !CONFIG_IS_ENABLED(MMC_TINY) ++static const struct mode_width_tuning sd_modes_by_pref[] = { ++#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) ++#ifdef MMC_SUPPORTS_TUNING ++ { ++ .mode = UHS_SDR104, ++ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, ++ .tuning = MMC_CMD_SEND_TUNING_BLOCK ++ }, ++#endif ++ { ++ .mode = UHS_SDR50, ++ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, ++ }, ++ { ++ .mode = UHS_DDR50, ++ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, ++ }, ++ { ++ .mode = UHS_SDR25, ++ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, ++ }, ++#endif ++ { ++ .mode = SD_HS, ++ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, ++#ifdef MMC_SUPPORTS_TUNING ++ .tuning = MMC_SD_HS_TUNING ++#endif ++ }, ++#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) ++ { ++ .mode = UHS_SDR12, ++ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, ++ }, ++#endif ++ { ++ .mode = SD_LEGACY, ++ .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, ++ } ++}; ++ ++#define for_each_sd_mode_by_pref(caps, mwt) \ ++ for (mwt = sd_modes_by_pref;\ ++ mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\ ++ mwt++) \ ++ if (caps & MMC_CAP(mwt->mode)) ++ ++static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps) ++{ ++ int err; ++ uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT}; ++ const struct mode_width_tuning *mwt; ++#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) ++ bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false; ++#else ++ bool uhs_en = false; ++#endif ++ uint caps; ++ ++#ifdef DEBUG ++ mmc_dump_capabilities("sd card", card_caps); ++ mmc_dump_capabilities("host", mmc->host_caps); ++#endif ++ ++ /* Restrict card's capabilities by what the host can do */ ++ caps = card_caps & mmc->host_caps; ++ ++ if (!uhs_en) ++ caps &= ~UHS_CAPS; ++ ++ for_each_sd_mode_by_pref(caps, mwt) { ++ uint *w; ++ ++ for (w = widths; w < widths + ARRAY_SIZE(widths); w++) { ++ if (*w & caps & mwt->widths) { ++ pr_debug("trying mode %s width %d (at %d MHz)\n", ++ mmc_mode_name(mwt->mode), ++ bus_width(*w), ++ mmc_mode2freq(mmc, mwt->mode) / 1000000); ++ ++ /* configure the bus width (card + host) */ ++ err = sd_select_bus_width(mmc, bus_width(*w)); ++ if (err) ++ goto error; ++ mmc_set_bus_width(mmc, bus_width(*w)); ++ ++ /* configure the bus mode (card) */ ++ err = sd_set_card_speed(mmc, mwt->mode); ++ if (err) ++ goto error; ++ ++ /* configure the bus mode (host) */ ++ mmc_select_mode(mmc, mwt->mode); ++ mmc_set_clock(mmc, mmc->tran_speed, ++ MMC_CLK_ENABLE); ++ ++#ifdef MMC_SUPPORTS_TUNING ++ /* execute tuning if needed */ ++ if (mwt->tuning && !mmc_host_is_spi(mmc)) { ++ err = mmc_execute_tuning(mmc, ++ mwt->tuning); ++ if (err) { ++ pr_debug("tuning failed\n"); ++ goto error; ++ } ++ } ++#endif ++ ++#if CONFIG_IS_ENABLED(MMC_WRITE) ++ err = sd_read_ssr(mmc); ++ if (err) ++ pr_warn("unable to read ssr\n"); ++#endif ++ if (!err) ++ return 0; ++ ++error: ++ /* revert to a safer bus speed */ ++ mmc_select_mode(mmc, SD_LEGACY); ++ mmc_set_clock(mmc, mmc->tran_speed, ++ MMC_CLK_ENABLE); ++ } ++ } ++ } ++ ++ pr_err("unable to select a mode\n"); ++ return -ENOTSUPP; ++} ++ ++/* ++ * read the compare the part of ext csd that is constant. ++ * This can be used to check that the transfer is working ++ * as expected. ++ */ ++static int mmc_read_and_compare_ext_csd(struct mmc *mmc) ++{ ++ int err; ++ const u8 *ext_csd = mmc->ext_csd; ++ ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); ++ ++ if (mmc->version < MMC_VERSION_4) ++ return 0; ++ ++ err = mmc_send_ext_csd(mmc, test_csd); ++ if (err) ++ return err; ++ ++ /* Only compare read only fields */ ++ if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] ++ == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && ++ ext_csd[EXT_CSD_HC_WP_GRP_SIZE] ++ == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && ++ ext_csd[EXT_CSD_REV] ++ == test_csd[EXT_CSD_REV] && ++ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] ++ == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && ++ memcmp(&ext_csd[EXT_CSD_SEC_CNT], ++ &test_csd[EXT_CSD_SEC_CNT], 4) == 0) ++ return 0; ++ ++ return -EBADMSG; ++} ++ ++#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE) ++static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode, ++ uint32_t allowed_mask) ++{ ++ u32 card_mask = 0; ++ ++ switch (mode) { ++ case MMC_HS_400: ++ case MMC_HS_200: ++ if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V | ++ EXT_CSD_CARD_TYPE_HS400_1_8V)) ++ card_mask |= MMC_SIGNAL_VOLTAGE_180; ++ if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V | ++ EXT_CSD_CARD_TYPE_HS400_1_2V)) ++ card_mask |= MMC_SIGNAL_VOLTAGE_120; ++ break; ++ case MMC_DDR_52: ++ if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) ++ card_mask |= MMC_SIGNAL_VOLTAGE_330 | ++ MMC_SIGNAL_VOLTAGE_180; ++ if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V) ++ card_mask |= MMC_SIGNAL_VOLTAGE_120; ++ break; ++ default: ++ card_mask |= MMC_SIGNAL_VOLTAGE_330; ++ break; ++ } ++ ++ while (card_mask & allowed_mask) { ++ enum mmc_voltage best_match; ++ ++ best_match = 1 << (ffs(card_mask & allowed_mask) - 1); ++ if (!mmc_set_signal_voltage(mmc, best_match)) ++ return 0; ++ ++ allowed_mask &= ~best_match; ++ } ++ ++ return -ENOTSUPP; ++} ++#else ++static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode, ++ uint32_t allowed_mask) ++{ ++ return 0; ++} ++#endif ++ ++static const struct mode_width_tuning mmc_modes_by_pref[] = { ++#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) ++ { ++ .mode = MMC_HS_400, ++ .widths = MMC_MODE_8BIT, ++ .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200 ++ }, ++#endif ++#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) ++ { ++ .mode = MMC_HS_200, ++ .widths = MMC_MODE_8BIT | MMC_MODE_4BIT, ++ .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200 ++ }, ++#endif ++ { ++ .mode = MMC_DDR_52, ++ .widths = MMC_MODE_8BIT | MMC_MODE_4BIT, ++ }, ++ { ++ .mode = MMC_HS_52, ++ .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT, ++#ifdef MMC_SUPPORTS_TUNING ++ .tuning = MMC_SD_HS_TUNING ++#endif ++ }, ++ { ++ .mode = MMC_HS, ++ .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT, ++ }, ++ { ++ .mode = MMC_LEGACY, ++ .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT, ++ } ++}; ++ ++#define for_each_mmc_mode_by_pref(caps, mwt) \ ++ for (mwt = mmc_modes_by_pref;\ ++ mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\ ++ mwt++) \ ++ if (caps & MMC_CAP(mwt->mode)) ++ ++static const struct ext_csd_bus_width { ++ uint cap; ++ bool is_ddr; ++ uint ext_csd_bits; ++} ext_csd_bus_width[] = { ++ {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8}, ++ {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4}, ++ {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8}, ++ {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4}, ++ {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1}, ++}; ++ ++#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) ++static int mmc_select_hs400(struct mmc *mmc) ++{ ++ int err; ++ ++ /* Set timing to HS200 for tuning */ ++ err = mmc_set_card_speed(mmc, MMC_HS_200); ++ if (err) ++ return err; ++ ++ /* configure the bus mode (host) */ ++ mmc_select_mode(mmc, MMC_HS_200); ++ mmc_set_clock(mmc, mmc->tran_speed, false); ++ ++ /* execute tuning if needed */ ++ err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200); ++ if (err) { ++ pr_debug("tuning failed\n"); ++ return err; ++ } ++ ++ /* Set back to HS */ ++ mmc_set_card_speed(mmc, MMC_HS); ++ mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false); ++ ++ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, ++ EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG); ++ if (err) ++ return err; ++ ++ err = mmc_set_card_speed(mmc, MMC_HS_400); ++ if (err) ++ return err; ++ ++ mmc_select_mode(mmc, MMC_HS_400); ++ err = mmc_set_clock(mmc, mmc->tran_speed, false); ++ if (err) ++ return err; ++ ++ return 0; ++} ++#else ++static int mmc_select_hs400(struct mmc *mmc) ++{ ++ return -ENOTSUPP; ++} ++#endif ++ ++#define for_each_supported_width(caps, ddr, ecbv) \ ++ for (ecbv = ext_csd_bus_width;\ ++ ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\ ++ ecbv++) \ ++ if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap)) ++ ++static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps) ++{ ++ int err; ++ const struct mode_width_tuning *mwt; ++ const struct ext_csd_bus_width *ecbw; ++ ++#ifdef DEBUG ++ mmc_dump_capabilities("mmc", card_caps); ++ mmc_dump_capabilities("host", mmc->host_caps); ++#endif ++ ++ /* Restrict card's capabilities by what the host can do */ ++ card_caps &= mmc->host_caps; ++ ++ /* Only version 4 of MMC supports wider bus widths */ ++ if (mmc->version < MMC_VERSION_4) ++ return 0; ++ ++ if (!mmc->ext_csd) { ++ pr_debug("No ext_csd found!\n"); /* this should enver happen */ ++ return -ENOTSUPP; ++ } ++ ++ for_each_mmc_mode_by_pref(card_caps, mwt) { ++ for_each_supported_width(card_caps & mwt->widths, ++ mmc_is_mode_ddr(mwt->mode), ecbw) { ++ enum mmc_voltage old_voltage; ++ pr_debug("trying mode %s width %d (at %d MHz)\n", ++ mmc_mode_name(mwt->mode), ++ bus_width(ecbw->cap), ++ mmc_mode2freq(mmc, mwt->mode) / 1000000); ++ old_voltage = mmc->signal_voltage; ++ err = mmc_set_lowest_voltage(mmc, mwt->mode, ++ MMC_ALL_SIGNAL_VOLTAGE); ++ if (err) ++ continue; ++ ++ /* configure the bus width (card + host) */ ++ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, ++ EXT_CSD_BUS_WIDTH, ++ ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG); ++ if (err) ++ goto error; ++ mmc_set_bus_width(mmc, bus_width(ecbw->cap)); ++ ++ if (mwt->mode == MMC_HS_400) { ++ err = mmc_select_hs400(mmc); ++ if (err) { ++ pr_err("Select HS400 failed %d\n", err); ++ goto error; ++ } ++ } else { ++ /* configure the bus speed (card) */ ++ err = mmc_set_card_speed(mmc, mwt->mode); ++ if (err) ++ goto error; ++ ++ /* ++ * configure the bus width AND the ddr mode ++ * (card). The host side will be taken care ++ * of in the next step ++ */ ++ if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) { ++ err = mmc_switch(mmc, ++ EXT_CSD_CMD_SET_NORMAL, ++ EXT_CSD_BUS_WIDTH, ++ ecbw->ext_csd_bits); ++ if (err) ++ goto error; ++ } ++ ++ /* configure the bus mode (host) */ ++ mmc_select_mode(mmc, mwt->mode); ++ mmc_set_clock(mmc, mmc->tran_speed, ++ MMC_CLK_ENABLE); ++#ifdef MMC_SUPPORTS_TUNING ++ ++ /* execute tuning if needed */ ++ if (mwt->tuning) { ++ err = mmc_execute_tuning(mmc, ++ mwt->tuning); ++ if (err) { ++ pr_debug("tuning failed\n"); ++ goto error; ++ } ++ } ++#endif ++ } ++ ++ /* do a transfer to check the configuration */ ++ err = mmc_read_and_compare_ext_csd(mmc); ++ if (!err) ++ return 0; ++error: ++ mmc_set_signal_voltage(mmc, old_voltage); ++ /* if an error occured, revert to a safer bus mode */ ++ mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, ++ EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1); ++ mmc_select_mode(mmc, MMC_LEGACY); ++ mmc_set_bus_width(mmc, 1); ++ } ++ } ++ ++ pr_err("unable to select a mode\n"); ++ ++ return -ENOTSUPP; ++} ++#endif ++ ++#if CONFIG_IS_ENABLED(MMC_TINY) ++DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN); ++#endif ++ ++static int mmc_startup_v4(struct mmc *mmc) ++{ ++ int err, i; ++ u64 capacity; ++ bool has_parts = false; ++ bool part_completed; ++ static const u32 mmc_versions[] = { ++ MMC_VERSION_4, ++ MMC_VERSION_4_1, ++ MMC_VERSION_4_2, ++ MMC_VERSION_4_3, ++ MMC_VERSION_4_4, ++ MMC_VERSION_4_41, ++ MMC_VERSION_4_5, ++ MMC_VERSION_5_0, ++ MMC_VERSION_5_1 ++ }; ++ ++#if CONFIG_IS_ENABLED(MMC_TINY) ++ u8 *ext_csd = ext_csd_bkup; ++ ++ if (IS_SD(mmc) || mmc->version < MMC_VERSION_4) ++ return 0; ++ ++ if (!mmc->ext_csd) ++ memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup)); ++ ++ err = mmc_send_ext_csd(mmc, ext_csd); ++ if (err) ++ goto error; ++ ++ /* store the ext csd for future reference */ ++ if (!mmc->ext_csd) ++ mmc->ext_csd = ext_csd; ++#else ++ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); ++ ++ if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4)) ++ return 0; ++ ++ /* check ext_csd version and capacity */ ++ err = mmc_send_ext_csd(mmc, ext_csd); ++ if (err) ++ goto error; ++ ++ /* store the ext csd for future reference */ ++ if (!mmc->ext_csd) ++ mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN); ++ if (!mmc->ext_csd) ++ return -ENOMEM; ++ memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN); ++#endif ++ if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions)) ++ return -EINVAL; ++ ++ mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]]; ++ ++ if (mmc->version >= MMC_VERSION_4_2) { ++ /* ++ * According to the JEDEC Standard, the value of ++ * ext_csd's capacity is valid if the value is more ++ * than 2GB ++ */ ++ capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 ++ | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 ++ | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 ++ | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; ++ capacity *= MMC_MAX_BLOCK_LEN; ++ if ((capacity >> 20) > 2 * 1024) ++ mmc->capacity_user = capacity; ++ } ++ ++ /* The partition data may be non-zero but it is only ++ * effective if PARTITION_SETTING_COMPLETED is set in ++ * EXT_CSD, so ignore any data if this bit is not set, ++ * except for enabling the high-capacity group size ++ * definition (see below). ++ */ ++ part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & ++ EXT_CSD_PARTITION_SETTING_COMPLETED); ++ ++ /* store the partition info of emmc */ ++ mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; ++ if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || ++ ext_csd[EXT_CSD_BOOT_MULT]) ++ mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; ++ if (part_completed && ++ (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) ++ mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; ++ ++ mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; ++ ++ mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; ++ ++ for (i = 0; i < 4; i++) { ++ int idx = EXT_CSD_GP_SIZE_MULT + i * 3; ++ uint mult = (ext_csd[idx + 2] << 16) + ++ (ext_csd[idx + 1] << 8) + ext_csd[idx]; ++ if (mult) ++ has_parts = true; ++ if (!part_completed) ++ continue; ++ mmc->capacity_gp[i] = mult; ++ mmc->capacity_gp[i] *= ++ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; ++ mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; ++ mmc->capacity_gp[i] <<= 19; ++ } ++ ++#ifndef CONFIG_SPL_BUILD ++ if (part_completed) { ++ mmc->enh_user_size = ++ (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) + ++ (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) + ++ ext_csd[EXT_CSD_ENH_SIZE_MULT]; ++ mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; ++ mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; ++ mmc->enh_user_size <<= 19; ++ mmc->enh_user_start = ++ (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) + ++ (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) + ++ (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) + ++ ext_csd[EXT_CSD_ENH_START_ADDR]; ++ if (mmc->high_capacity) ++ mmc->enh_user_start <<= 9; ++ } ++#endif ++ ++ /* dev life time estimate type A/B */ ++ mmc->dev_lifetime_est_typ_a ++ = ext_csd[EXT_CSD_DEV_LIFETIME_EST_TYP_A]; ++ mmc->dev_lifetime_est_typ_b ++ = ext_csd[EXT_CSD_DEV_LIFETIME_EST_TYP_B]; ++ ++ /* ++ * Host needs to enable ERASE_GRP_DEF bit if device is ++ * partitioned. This bit will be lost every time after a reset ++ * or power off. This will affect erase size. ++ */ ++ if (part_completed) ++ has_parts = true; ++ if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && ++ (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) ++ has_parts = true; ++ if (has_parts) { ++ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, ++ EXT_CSD_ERASE_GROUP_DEF, 1); ++ ++ if (err) ++ goto error; ++ ++ ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; ++ } ++ ++ if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { ++#if CONFIG_IS_ENABLED(MMC_WRITE) ++ /* Read out group size from ext_csd */ ++ mmc->erase_grp_size = ++ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; ++#endif ++ /* ++ * if high capacity and partition setting completed ++ * SEC_COUNT is valid even if it is smaller than 2 GiB ++ * JEDEC Standard JESD84-B45, 6.2.4 ++ */ ++ if (mmc->high_capacity && part_completed) { ++ capacity = (ext_csd[EXT_CSD_SEC_CNT]) | ++ (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | ++ (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | ++ (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); ++ capacity *= MMC_MAX_BLOCK_LEN; ++ mmc->capacity_user = capacity; ++ } ++ } ++#if CONFIG_IS_ENABLED(MMC_WRITE) ++ else { ++ /* Calculate the group size from the csd value. */ ++ int erase_gsz, erase_gmul; ++ erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; ++ erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; ++ mmc->erase_grp_size = (erase_gsz + 1) ++ * (erase_gmul + 1); ++ } ++#endif ++#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING) ++ mmc->hc_wp_grp_size = 1024 ++ * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] ++ * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; ++#endif ++ ++ mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; ++ ++ return 0; ++error: ++ if (mmc->ext_csd) { ++#if !CONFIG_IS_ENABLED(MMC_TINY) ++ free(mmc->ext_csd); ++#endif ++ mmc->ext_csd = NULL; ++ } ++ return err; ++} ++ ++static int mmc_startup(struct mmc *mmc) ++{ ++ int err, i; ++ uint mult, freq; ++ u64 cmult, csize; ++ struct mmc_cmd cmd; ++ struct blk_desc *bdesc; ++ ++#ifdef CONFIG_MMC_SPI_CRC_ON ++ if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ ++ cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; ++ cmd.resp_type = MMC_RSP_R1; ++ cmd.cmdarg = 1; ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ if (err) ++ return err; ++ } ++#endif ++ ++#ifdef CONFIG_MMC_FBOOT ++ if (emmc_boot_chk(mmc)) { ++ mmc_switch_part(mmc, 0); ++ ++ /* disSelect the card, and put it into detect Mode */ ++ if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ ++ cmd.cmdidx = MMC_CMD_SELECT_CARD; ++ cmd.resp_type = MMC_RSP_NONE; ++ cmd.cmdarg = 0; ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ ++ if (err) ++ return err; ++ } ++ ++ /* Put the Card in Identify Mode */ ++ cmd.cmdidx = MMC_CMD_SEND_CID; ++ cmd.resp_type = MMC_RSP_R2; ++ cmd.cmdarg = mmc->rca << 16; ++ ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ if (err) ++ return err; ++ ++ memcpy(mmc->cid, cmd.response, 16); ++ } else { ++#endif ++ /* Put the Card in Identify Mode */ ++ cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : ++ MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ ++ cmd.resp_type = MMC_RSP_R2; ++ cmd.cmdarg = 0; ++ ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ ++#ifdef CONFIG_MMC_QUIRKS ++ if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) { ++ int retries = 4; ++ /* ++ * It has been seen that SEND_CID may fail on the first ++ * attempt, let's try a few more time ++ */ ++ do { ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ if (!err) ++ break; ++ } while (retries--); ++ } ++#endif ++ ++ if (err) ++ return err; ++ ++ memcpy(mmc->cid, cmd.response, 16); ++ ++ /* ++ * For MMC cards, set the Relative Address. ++ * For SD cards, get the Relatvie Address. ++ * This also puts the cards into Standby State ++ */ ++ if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ ++ cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; ++ cmd.cmdarg = mmc->rca << 16; ++ cmd.resp_type = MMC_RSP_R6; ++ ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ ++ if (err) ++ return err; ++ ++ if (IS_SD(mmc)) ++ mmc->rca = (cmd.response[0] >> 16) & 0xffff; ++ } ++#ifdef CONFIG_MMC_FBOOT ++ } ++#endif ++ ++ /* Get the Card-Specific Data */ ++ cmd.cmdidx = MMC_CMD_SEND_CSD; ++ cmd.resp_type = MMC_RSP_R2; ++ cmd.cmdarg = mmc->rca << 16; ++ ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ ++ if (err) ++ return err; ++ ++ mmc->csd[0] = cmd.response[0]; ++ mmc->csd[1] = cmd.response[1]; ++ mmc->csd[2] = cmd.response[2]; ++ mmc->csd[3] = cmd.response[3]; ++ ++ if (mmc->version == MMC_VERSION_UNKNOWN) { ++ int version = (cmd.response[0] >> 26) & 0xf; ++ ++ switch (version) { ++ case 0: ++ mmc->version = MMC_VERSION_1_2; ++ break; ++ case 1: ++ mmc->version = MMC_VERSION_1_4; ++ break; ++ case 2: ++ mmc->version = MMC_VERSION_2_2; ++ break; ++ case 3: ++ mmc->version = MMC_VERSION_3; ++ break; ++ case 4: ++ mmc->version = MMC_VERSION_4; ++ break; ++ default: ++ mmc->version = MMC_VERSION_1_2; ++ break; ++ } ++ } ++ ++ /* divide frequency by 10, since the mults are 10x bigger */ ++ freq = fbase[(cmd.response[0] & 0x7)]; ++ mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; ++ ++ mmc->legacy_speed = freq * mult; ++ mmc_select_mode(mmc, MMC_LEGACY); ++ ++ mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); ++ mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); ++#if CONFIG_IS_ENABLED(MMC_WRITE) ++ ++ if (IS_SD(mmc)) ++ mmc->write_bl_len = mmc->read_bl_len; ++ else ++ mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); ++#endif ++ ++ if (mmc->high_capacity) { ++ csize = (mmc->csd[1] & 0x3f) << 16 ++ | (mmc->csd[2] & 0xffff0000) >> 16; ++ cmult = 8; ++ } else { ++ csize = (mmc->csd[1] & 0x3ff) << 2 ++ | (mmc->csd[2] & 0xc0000000) >> 30; ++ cmult = (mmc->csd[2] & 0x00038000) >> 15; ++ } ++ ++ mmc->capacity_user = (csize + 1) << (cmult + 2); ++ mmc->capacity_user *= mmc->read_bl_len; ++ mmc->capacity_boot = 0; ++ mmc->capacity_rpmb = 0; ++ for (i = 0; i < 4; i++) ++ mmc->capacity_gp[i] = 0; ++ ++ if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) ++ mmc->read_bl_len = MMC_MAX_BLOCK_LEN; ++ ++#if CONFIG_IS_ENABLED(MMC_WRITE) ++ if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) ++ mmc->write_bl_len = MMC_MAX_BLOCK_LEN; ++#endif ++ ++ if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { ++ cmd.cmdidx = MMC_CMD_SET_DSR; ++ cmd.cmdarg = (mmc->dsr & 0xffff) << 16; ++ cmd.resp_type = MMC_RSP_NONE; ++ if (mmc_send_cmd(mmc, &cmd, NULL)) ++ pr_warn("MMC: SET_DSR failed\n"); ++ } ++ ++ /* Select the card, and put it into Transfer Mode */ ++ if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ ++ cmd.cmdidx = MMC_CMD_SELECT_CARD; ++ cmd.resp_type = MMC_RSP_R1; ++ cmd.cmdarg = mmc->rca << 16; ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ ++ if (err) ++ return err; ++ } ++ ++ /* ++ * For SD, its erase group is always one sector ++ */ ++#if CONFIG_IS_ENABLED(MMC_WRITE) ++ mmc->erase_grp_size = 1; ++#endif ++ mmc->part_config = MMCPART_NOAVAILABLE; ++ ++ err = mmc_startup_v4(mmc); ++ if (err) ++ return err; ++ ++ err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart); ++ if (err) ++ return err; ++ ++#if CONFIG_IS_ENABLED(MMC_TINY) ++ mmc_set_clock(mmc, mmc->legacy_speed, false); ++ mmc_select_mode(mmc, IS_SD(mmc) ? SD_LEGACY : MMC_LEGACY); ++ mmc_set_bus_width(mmc, 1); ++#else ++ if (IS_SD(mmc)) { ++ err = sd_get_capabilities(mmc); ++ if (err) ++ return err; ++ err = sd_select_mode_and_width(mmc, mmc->card_caps); ++ } else { ++ err = mmc_get_capabilities(mmc); ++ if (err) ++ return err; ++ mmc_select_mode_and_width(mmc, mmc->card_caps); ++ } ++#endif ++ if (err) ++ return err; ++ ++ mmc->best_mode = mmc->selected_mode; ++ ++ /* Fix the block length for DDR mode */ ++ if (mmc->ddr_mode) { ++ mmc->read_bl_len = MMC_MAX_BLOCK_LEN; ++#if CONFIG_IS_ENABLED(MMC_WRITE) ++ mmc->write_bl_len = MMC_MAX_BLOCK_LEN; ++#endif ++ } ++ ++ /* fill in device description */ ++ bdesc = mmc_get_blk_desc(mmc); ++ bdesc->lun = 0; ++ bdesc->hwpart = 0; ++ bdesc->type = 0; ++ bdesc->blksz = mmc->read_bl_len; ++ bdesc->log2blksz = LOG2(bdesc->blksz); ++ bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len); ++#if !defined(CONFIG_SPL_BUILD) || \ ++ (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \ ++ !defined(CONFIG_USE_TINY_PRINTF)) ++ sprintf(bdesc->vendor, "Man %06x Snr %04x%04x", ++ mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), ++ (mmc->cid[3] >> 16) & 0xffff); ++ sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, ++ (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, ++ (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, ++ (mmc->cid[2] >> 24) & 0xff); ++ sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, ++ (mmc->cid[2] >> 16) & 0xf); ++#else ++ bdesc->vendor[0] = 0; ++ bdesc->product[0] = 0; ++ bdesc->revision[0] = 0; ++#endif ++ ++#if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)) ++ part_init(bdesc); ++#endif ++ ++ return 0; ++} ++ ++static int mmc_send_if_cond(struct mmc *mmc) ++{ ++ struct mmc_cmd cmd; ++ int err; ++ ++ cmd.cmdidx = SD_CMD_SEND_IF_COND; ++ /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ ++ cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; ++ cmd.resp_type = MMC_RSP_R7; ++ ++ err = mmc_send_cmd(mmc, &cmd, NULL); ++ if (err) ++ return err; ++ ++ if ((cmd.response[0] & 0xff) != 0xaa) ++ return -EOPNOTSUPP; ++ else ++ mmc->version = SD_VERSION_2; ++ ++ return 0; ++} ++ ++#if !CONFIG_IS_ENABLED(DM_MMC) ++/* board-specific MMC power initializations. */ ++__weak void board_mmc_power_init(void) ++{ ++} ++#endif ++ ++static int mmc_power_init(struct mmc *mmc) ++{ ++#if CONFIG_IS_ENABLED(DM_MMC) ++#if CONFIG_IS_ENABLED(DM_REGULATOR) ++ int ret; ++ ++ ret = device_get_supply_regulator(mmc->dev, "vmmc-supply", ++ &mmc->vmmc_supply); ++ if (ret) ++ pr_debug("%s: No vmmc supply\n", mmc->dev->name); ++ ++ ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply", ++ &mmc->vqmmc_supply); ++ if (ret) ++ pr_debug("%s: No vqmmc supply\n", mmc->dev->name); ++#endif ++#else /* !CONFIG_DM_MMC */ ++ /* ++ * Driver model should use a regulator, as above, rather than calling ++ * out to board code. ++ */ ++ board_mmc_power_init(); ++#endif ++ return 0; ++} ++ ++/* ++ * put the host in the initial state: ++ * - turn on Vdd (card power supply) ++ * - configure the bus width and clock to minimal values ++ */ ++static void mmc_set_initial_state(struct mmc *mmc) ++{ ++ int err; ++ ++ /* First try to set 3.3V. If it fails set to 1.8V */ ++ err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330); ++ if (err != 0) ++ err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180); ++ if (err != 0) ++ pr_warn("mmc: failed to set signal voltage\n"); ++ ++ mmc_select_mode(mmc, MMC_LEGACY); ++ mmc_set_bus_width(mmc, 1); ++ mmc_set_clock(mmc, 0, MMC_CLK_ENABLE); ++} ++ ++static int mmc_power_on(struct mmc *mmc) ++{ ++#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR) ++ if (mmc->vmmc_supply) { ++ int ret = regulator_set_enable(mmc->vmmc_supply, true); ++ ++ if (ret) { ++ puts("Error enabling VMMC supply\n"); ++ return ret; ++ } ++ } ++#endif ++ return 0; ++} ++ ++static int mmc_power_off(struct mmc *mmc) ++{ ++ mmc_set_clock(mmc, 0, MMC_CLK_DISABLE); ++#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR) ++ if (mmc->vmmc_supply) { ++ int ret = regulator_set_enable(mmc->vmmc_supply, false); ++ ++ if (ret) { ++ pr_debug("Error disabling VMMC supply\n"); ++ return ret; ++ } ++ } ++#endif ++ return 0; ++} ++ ++static int mmc_power_cycle(struct mmc *mmc) ++{ ++ int ret; ++ ++ ret = mmc_power_off(mmc); ++ if (ret) ++ return ret; ++ /* ++ * SD spec recommends at least 1ms of delay. Let's wait for 2ms ++ * to be on the safer side. ++ */ ++ udelay(2000); ++ return mmc_power_on(mmc); ++} ++ ++int mmc_get_op_cond(struct mmc *mmc) ++{ ++ bool uhs_en = supports_uhs(mmc->cfg->host_caps); ++ int err; ++ ++ if (mmc->has_init) ++ return 0; ++ ++#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT ++ mmc_adapter_card_type_ident(); ++#endif ++ err = mmc_power_init(mmc); ++ if (err) ++ return err; ++ ++#ifdef CONFIG_MMC_QUIRKS ++ mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN | ++ MMC_QUIRK_RETRY_SEND_CID; ++#endif ++ ++ err = mmc_power_cycle(mmc); ++ if (err) { ++ /* ++ * if power cycling is not supported, we should not try ++ * to use the UHS modes, because we wouldn't be able to ++ * recover from an error during the UHS initialization. ++ */ ++ pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n"); ++ uhs_en = false; ++ mmc->host_caps &= ~UHS_CAPS; ++ err = mmc_power_on(mmc); ++ } ++ if (err) ++ return err; ++ ++#if CONFIG_IS_ENABLED(DM_MMC) ++ /* The device has already been probed ready for use */ ++#else ++ /* made sure it's not NULL earlier */ ++ err = mmc->cfg->ops->init(mmc); ++ if (err) ++ return err; ++#endif ++ mmc->ddr_mode = 0; ++ ++retry: ++ mmc_set_initial_state(mmc); ++ mmc_send_init_stream(mmc); ++ ++ /* Reset the Card */ ++ err = mmc_go_idle(mmc); ++ if (err) ++ return err; ++ ++ /* The internal partition reset to user partition(0) at every CMD0*/ ++ mmc_get_blk_desc(mmc)->hwpart = 0; ++ ++ /* Test for SD version 2 */ ++ err = mmc_send_if_cond(mmc); ++ ++ /* Now try to get the SD card's operating condition */ ++ err = sd_send_op_cond(mmc, uhs_en); ++ if (err && uhs_en) { ++ uhs_en = false; ++ mmc_power_cycle(mmc); ++ goto retry; ++ } ++ ++ /* If the command timed out, we check for an MMC card */ ++ if (err == -ETIMEDOUT) { ++ err = mmc_send_op_cond(mmc); ++ ++ if (err) { ++#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) ++ pr_err("Card did not respond to voltage select!\n"); ++#endif ++ return -EOPNOTSUPP; ++ } ++ } ++ ++ return err; ++} ++ ++int mmc_start_init(struct mmc *mmc) ++{ ++ bool no_card; ++ int err = 0; ++ ++ /* ++ * all hosts are capable of 1 bit bus-width and able to use the legacy ++ * timings. ++ */ ++ mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) | ++ MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT; ++ ++#if !defined(CONFIG_MMC_BROKEN_CD) ++ /* we pretend there's no card when init is NULL */ ++ no_card = mmc_getcd(mmc) == 0; ++#else ++ no_card = 0; ++#endif ++#if !CONFIG_IS_ENABLED(DM_MMC) ++ no_card = no_card || (mmc->cfg->ops->init == NULL); ++#endif ++ if (no_card) { ++ mmc->has_init = 0; ++#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) ++ pr_err("MMC: no card present\n"); ++#endif ++ return -ENOMEDIUM; ++ } ++ ++#ifdef CONFIG_MMC_FBOOT ++ if (emmc_boot_chk(mmc)) { ++ mmc->high_capacity = 1; ++ mmc->rca = 1; ++ mmc->version = MMC_VERSION_UNKNOWN; ++ } else ++#endif ++ err = mmc_get_op_cond(mmc); ++ ++ if (!err) ++ mmc->init_in_progress = 1; ++ ++ return err; ++} ++ ++static int mmc_complete_init(struct mmc *mmc) ++{ ++ int err = 0; ++ ++ mmc->init_in_progress = 0; ++ if (mmc->op_cond_pending) ++ err = mmc_complete_op_cond(mmc); ++ ++ if (!err) ++ err = mmc_startup(mmc); ++ if (err) ++ mmc->has_init = 0; ++ else ++ mmc->has_init = 1; ++ return err; ++} ++ ++void mmc_write_cali_mattern(void *addr, struct aml_pattern *table) ++{ ++ int i = 0; ++ unsigned int s = 10; ++ u32 *mattern = (u32 *)addr; ++ struct virtual_partition *vpart = ++ aml_get_virtual_partition_by_name(table->name); ++ for (i = 0;i < (vpart->size)/4 - 1;i++) { ++ if (!strcmp(table->name, "random")) ++ mattern[i] = rand_r(&s); ++ else ++ mattern[i] = table->pattern; ++ } ++ mattern[i] = crc32(0, (u8 *)addr, (vpart->size - 4)); ++ return; ++} ++ ++int mmc_pattern_check(struct mmc *mmc, struct aml_pattern *table) ++{ ++ void *addr = NULL; ++ u64 cnt = 0, n = 0, blk = 0; ++ u32 *buf = NULL; ++ u32 crc32_s = 0; ++ struct partitions *part = NULL; ++ struct virtual_partition *vpart = NULL; ++ ++ vpart = aml_get_virtual_partition_by_name(table->name); ++ ++ addr = (void *)malloc(vpart->size); ++ if (!addr) { ++ printf("%s malloc failed\n", table->name); ++ return 1; ++ } ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ blk = (part->offset + vpart->offset) / mmc->read_bl_len; ++ cnt = vpart->size / mmc->read_bl_len; ++ n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr); ++ if (n != cnt) { ++ printf("read pattern failed\n"); ++ free(addr); ++ return 1; ++ } else { ++ buf = (u32 *)addr; ++ crc32_s = crc32(0, (u8 *)addr, (vpart->size - 4)); ++ if (crc32_s != buf[vpart->size/4 - 1]) { ++ printf("check %s failed,need to write\n", ++ table->name); ++ mmc_write_cali_mattern(addr, table); ++ n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr); ++ printf("several 0x%x pattern blocks write %s\n", ++ table->pattern, (n == cnt) ? "OK" : "ERROR"); ++ } ++ printf("crc32_s:0x%x == storage crc_pattern:0x%x!!!\n", ++ crc32_s, buf[vpart->size/4 - 1]); ++ } ++ free(addr); ++ return (n == cnt) ? 0 : 1; ++} ++ ++int mmc_init(struct mmc *mmc) ++{ ++ int err = 0, i; ++ __maybe_unused ulong start; ++#if CONFIG_IS_ENABLED(DM_MMC) ++ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev); ++ ++ upriv->mmc = mmc; ++#endif ++ if (mmc->has_init) ++ return 0; ++ ++ start = get_timer(0); ++ ++ if (!mmc->init_in_progress) ++ err = mmc_start_init(mmc); ++ ++ if (!err) ++ err = mmc_complete_init(mmc); ++ if (err) ++ pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start)); ++ info_disprotect |= DISPROTECT_KEY; ++ if (IS_MMC(mmc)) { ++ if (!is_partition_checked) { ++ if (mmc_device_init(mmc) == 0) { ++ is_partition_checked = true; ++ pr_info("eMMC/TSD partition table have been checked OK!\n"); ++ for (i = 0; i < ARRAY_SIZE(aml_pattern_table); i++) ++ mmc_pattern_check(mmc, &aml_pattern_table[i]); ++ } ++ } ++ } ++ info_disprotect &= ~DISPROTECT_KEY; ++ return err; ++ ++} ++ ++ulong mmc_ffu_write(int dev_num, lbaint_t start, lbaint_t blkcnt, const void *src) ++{ ++ struct mmc_cmd cmd; ++ struct mmc_data data; ++ int ret, timeout = 1000; ++ struct mmc *mmc = find_mmc_device(dev_num); ++ if (!mmc || !blkcnt) ++ return 0; ++ ++ printf("mmc ffu start = %lx, cnt = %lx, addr = %p\n", start, blkcnt, src); ++ ++ cmd.cmdidx = MMC_CMD_SET_BLOCK_COUNT; ++ cmd.cmdarg = blkcnt & 0xFFFF; ++ cmd.resp_type = MMC_RSP_R1; ++ ret = mmc_send_cmd(mmc, &cmd, NULL); ++ if (ret) { ++ printf("mmc set blkcnt failed\n"); ++ return 0; ++ } ++ ++ cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK; ++ cmd.cmdarg = start; ++ cmd.resp_type = MMC_RSP_R1b; ++ ++ data.src = src; ++ data.blocks = blkcnt; ++ data.blocksize = mmc->write_bl_len; ++ data.flags = MMC_DATA_WRITE; ++ ++ ret = mmc_send_cmd(mmc, &cmd, &data); ++ if (ret) { ++ printf("mmc write failed\n"); ++ return 0; ++ } ++ ++ /* Waiting for the ready status */ ++ if (mmc_send_status(mmc, timeout)) ++ return 0; ++ ++ return blkcnt; ++} ++ ++int mmc_ffu_op(int dev, u64 ffu_ver, void *addr, u64 cnt) ++{ ++ int err, i, supported_modes, fw_cfg, ffu_status; ++ u64 fw_ver = 0, n; ++ u8 ext_csd_ffu[512] = {0}; ++ lbaint_t ffu_addr=0; ++ struct mmc *mmc = find_mmc_device(dev); ++ if (!mmc) ++ return -ENODEV; ++ ++ printf("ffu update start\n"); ++ /* check Manufacturer MID */ ++ if ((mmc->cid[0] >> 24) == SAMSUNG_MID) { ++ ffu_addr = SAMSUNG_FFU_ADDR; ++ } else if ((mmc->cid[0] >> 24) == KINGSTON_MID) { ++ ffu_addr = KINGSTON_FFU_ADDR; ++ } else if ((mmc->cid[0] >> 24) == BIWIN_MID) { ++ ffu_addr = BIWIN_FFU_ADDR; ++ } else { ++ printf("FFU update for this manufacturer not support yet\n"); ++ return -1; ++ } ++ ++ /* ++ * check FFU Supportability ++ * check FFU Prohibited or not ++ * check current firmware version ++ */ ++ memset(ext_csd_ffu, 0, 512); ++ err = mmc_get_ext_csd(mmc, ext_csd_ffu); ++ if (err) ++ return err; ++ ++ supported_modes = ext_csd_ffu[EXT_CSD_SUPPORTED_MODES] & 0x1; ++ fw_cfg = ext_csd_ffu[EXT_CSD_FW_CFG] & 0x1; ++ for (i = 0; i < 8; i++) { ++ fw_ver |= ext_csd_ffu[EXT_CSD_FW_VERSION + 7 - i]; ++ if (i < 7) ++ fw_ver <<= 8; ++ } ++ if ((mmc->cid[0] >> 24) == BIWIN_MID) ++ fw_ver = ((fw_ver >> 16) & 0xffffffff); ++ printf("old fw_ver = %llx\n", fw_ver); ++ if (!supported_modes || fw_cfg || (fw_ver >= ffu_ver)) ++ return -1; ++ ++ /* Set FFU Mode */ ++ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_MODE_CFG, 1); ++ if (err) { ++ printf("Failed: set FFU mode\n"); ++ return err; ++ } ++ ++ /* Write patch file at one write command */ ++ n = mmc_ffu_write(dev, ffu_addr, cnt, addr); ++ if (n != cnt) { ++ printf("target is %llx block, but only %llx block has been write\n", cnt, n); ++ return -1; ++ } ++ ++ memset(ext_csd_ffu, 0, 512); ++ err = mmc_get_ext_csd(mmc, ext_csd_ffu); ++ if (err) ++ return err; ++ ++ for (i = 0; i < 8; i++) { ++ fw_ver |= ext_csd_ffu[EXT_CSD_FW_VERSION + 7 - i]; ++ if (i < 7) ++ fw_ver <<= 8; ++ } ++ if ((mmc->cid[0] >> 24) == BIWIN_MID) ++ fw_ver = ((fw_ver >> 16) & 0xffffffff); ++ printf("new fw_ver = %llx\n", fw_ver); ++ if ((mmc->cid[0] >> 24) == SAMSUNG_MID) { ++ /* Set Normal Mode */ ++ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_MODE_CFG, 0); ++ if (err) ++ return err; ++ } ++ ++ /* reset devices */ ++ err = mmc_go_idle(mmc); ++ if (err) ++ return err; ++ ++ /* Initialization */ ++ mmc->has_init = 0; ++ err = mmc_init(mmc); ++ if (err) ++ return err; ++ ++ /* Read ffu_status, check ffu_version */ ++ memset(ext_csd_ffu, 0, 512); ++ err = mmc_get_ext_csd(mmc, ext_csd_ffu); ++ if (err) ++ return err; ++ ffu_status = ext_csd_ffu[EXT_CSD_FFU_STATUS] & 0xff; ++ fw_ver = 0; ++ for (i = 0; i < 8; i++) { ++ fw_ver |= ext_csd_ffu[EXT_CSD_FW_VERSION + 7 - i]; ++ if (i < 7) ++ fw_ver <<= 8; ++ } ++ if ((mmc->cid[0] >> 24) == BIWIN_MID) ++ fw_ver = ((fw_ver >> 16) & 0xffffffff); ++ printf("new fw_ver = %llx\n", fw_ver); ++ if (ffu_status || (fw_ver != ffu_ver)) ++ return ffu_status; ++ ++ printf("FFU update ok!\n"); ++ return 0; ++} ++ ++int mmc_set_dsr(struct mmc *mmc, u16 val) ++{ ++ mmc->dsr = val; ++ return 0; ++} ++ ++/* CPU-specific MMC initializations */ ++__weak int cpu_mmc_init(bd_t *bis) ++{ ++ return -1; ++} ++ ++/* board-specific MMC initializations. */ ++__weak int board_mmc_init(bd_t *bis) ++{ ++ return -1; ++} ++ ++void mmc_set_preinit(struct mmc *mmc, int preinit) ++{ ++ mmc->preinit = preinit; ++} ++ ++#if CONFIG_IS_ENABLED(DM_MMC) ++static int mmc_probe(bd_t *bis) ++{ ++ int ret, i; ++ struct uclass *uc; ++ struct udevice *dev; ++ ++ ret = uclass_get(UCLASS_MMC, &uc); ++ if (ret) ++ return ret; ++ ++ /* ++ * Try to add them in sequence order. Really with driver model we ++ * should allow holes, but the current MMC list does not allow that. ++ * So if we request 0, 1, 3 we will get 0, 1, 2. ++ */ ++ for (i = 0; ; i++) { ++ ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev); ++ if (ret == -ENODEV) ++ break; ++ } ++ uclass_foreach_dev(dev, uc) { ++ ret = device_probe(dev); ++ if (ret) ++ pr_err("%s - probe failed: %d\n", dev->name, ret); ++ } ++ ++ return 0; ++} ++#else ++static int mmc_probe(bd_t *bis) ++{ ++ if (board_mmc_init(bis) < 0) ++ cpu_mmc_init(bis); ++ ++ return 0; ++} ++#endif ++ ++int mmc_initialize(bd_t *bis) ++{ ++ static int initialized = 0; ++ int ret; ++ if (initialized) /* Avoid initializing mmc multiple times */ ++ return 0; ++ initialized = 1; ++ ++#if !CONFIG_IS_ENABLED(BLK) ++#if !CONFIG_IS_ENABLED(MMC_TINY) ++ mmc_list_init(); ++#endif ++#endif ++ ret = mmc_probe(bis); ++ if (ret) ++ return ret; ++ ++#ifndef CONFIG_SPL_BUILD ++ //print_mmc_devices(','); ++#endif ++ ++ mmc_do_preinit(); ++ return 0; ++} ++ ++#ifdef CONFIG_CMD_BKOPS_ENABLE ++int mmc_set_bkops_enable(struct mmc *mmc) ++{ ++ int err; ++ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); ++ ++ err = mmc_send_ext_csd(mmc, ext_csd); ++ if (err) { ++ puts("Could not get ext_csd register values\n"); ++ return err; ++ } ++ ++ if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) { ++ puts("Background operations not supported on device\n"); ++ return -EMEDIUMTYPE; ++ } ++ ++ if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) { ++ puts("Background operations already enabled\n"); ++ return 0; ++ } ++ ++ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1); ++ if (err) { ++ puts("Failed to enable manual background operations\n"); ++ return err; ++ } ++ ++ puts("Enabled manual background operations\n"); ++ ++ return 0; ++} ++#endif ++ ++extern unsigned long blk_dwrite(struct blk_desc *block_dev, lbaint_t start, ++ lbaint_t blkcnt, const void *buffer); ++ ++int mmc_key_write(unsigned char *buf, unsigned int size, uint32_t *actual_lenth) ++{ ++ ulong start, start_blk, blkcnt, ret; ++ unsigned char * temp_buf = buf; ++ int i = 2, dev = EMMC_DTB_DEV; ++ struct partitions * part = NULL; ++ struct mmc *mmc; ++ struct virtual_partition *vpart = NULL; ++ vpart = aml_get_virtual_partition_by_name(MMC_KEY_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ ++ mmc = find_mmc_device(dev); ++ ++ start = part->offset + vpart->offset; ++ start_blk = (start / MMC_BLOCK_SIZE); ++ blkcnt = (size / MMC_BLOCK_SIZE); ++ info_disprotect |= DISPROTECT_KEY; ++ do { ++ ret = blk_dwrite(mmc_get_blk_desc(mmc), start_blk, blkcnt, temp_buf); ++ if (ret != blkcnt) { ++ pr_err("[%s] %d, mmc_bwrite error\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ start_blk += vpart->size / MMC_BLOCK_SIZE; ++ } while (--i); ++ info_disprotect &= ~DISPROTECT_KEY; ++ return 0; ++} ++ ++ ++ ++ ++extern unsigned long blk_derase(struct blk_desc *block_dev, lbaint_t start, ++ lbaint_t blkcnt); ++ ++int mmc_key_erase(void) ++{ ++ ulong start, start_blk, blkcnt, ret; ++ struct partitions * part = NULL; ++ struct virtual_partition *vpart = NULL; ++ struct mmc *mmc; ++ vpart = aml_get_virtual_partition_by_name(MMC_KEY_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ int dev = EMMC_DTB_DEV; ++ ++ mmc = find_mmc_device(dev); ++ start = part->offset + vpart->offset; ++ start_blk = (start / MMC_BLOCK_SIZE); ++ blkcnt = (vpart->size / MMC_BLOCK_SIZE) * 2;//key and backup key ++ info_disprotect |= DISPROTECT_KEY; ++ ret = blk_derase(mmc_get_blk_desc(mmc), start_blk, blkcnt); ++ info_disprotect &= ~DISPROTECT_KEY; ++ if (ret) { ++ pr_err("[%s] %d mmc_berase error\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ return 0; ++} ++ ++ ++int mmc_key_read(unsigned char *buf, unsigned int size, uint32_t *actual_lenth) ++{ ++ ulong start, start_blk, blkcnt, ret; ++ int dev = EMMC_DTB_DEV; ++ unsigned char *temp_buf = buf; ++ struct partitions * part = NULL; ++ struct mmc *mmc; ++ struct virtual_partition *vpart = NULL; ++ vpart = aml_get_virtual_partition_by_name(MMC_KEY_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ ++ mmc = find_mmc_device(dev); ++ *actual_lenth = 0x40000;/*key size is 256KB*/ ++ start = part->offset + vpart->offset; ++ start_blk = (start / MMC_BLOCK_SIZE); ++ blkcnt = (size / MMC_BLOCK_SIZE); ++ info_disprotect |= DISPROTECT_KEY; ++ ret = blk_dread(mmc_get_blk_desc(mmc), start_blk, blkcnt, temp_buf); ++ info_disprotect &= ~DISPROTECT_KEY; ++ if (ret != blkcnt) { ++ pr_err("[%s] %d, mmc_bread error\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ return 0; ++} ++ ++ ++ +diff --git a/drivers/mmc/mmc_aml.c b/drivers/mmc/mmc_aml.c +new file mode 100644 +index 00000000000..a9b0ff780f8 +--- /dev/null ++++ b/drivers/mmc/mmc_aml.c +@@ -0,0 +1,416 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2008, Freescale Semiconductor, Inc ++ * Andy Fleming ++ * ++ * Based vaguely on the Linux code ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mmc_private.h" ++#include ++#include ++#include ++#include ++#include ++ ++static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage); ++ ++extern int emmc_probe(uint32_t init_flag); ++ ++bool emmckey_is_access_range_legal (struct mmc *mmc, ulong start, lbaint_t blkcnt) { ++ ulong key_start_blk, key_end_blk; ++ u64 key_glb_offset; ++ struct partitions * part = NULL; ++ struct virtual_partition *vpart = NULL; ++ if (IS_MMC(mmc)) { ++ vpart = aml_get_virtual_partition_by_name(MMC_KEY_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ key_glb_offset = part->offset + vpart->offset; ++ key_start_blk = (key_glb_offset / MMC_BLOCK_SIZE); ++ key_end_blk = ((key_glb_offset + vpart->size) / MMC_BLOCK_SIZE - 1); ++ if (!(info_disprotect & DISPROTECT_KEY)) { ++ if ((key_start_blk <= (start + blkcnt -1)) ++ && (key_end_blk >= start) ++ && (blkcnt != start)) { ++ pr_info("%s, keys %ld, keye %ld, start %ld, blkcnt %ld\n", ++ mmc->cfg->name, key_start_blk, ++ key_end_blk, start, blkcnt); ++ pr_err("Emmckey: Access range is illegal!\n"); ++ return 0; ++ } ++ } ++ } ++ return 1; ++} ++ ++int emmc_boot_chk(struct mmc *mmc) ++{ ++ u32 val = 0; ++ ++ if (strcmp(mmc->dev->name, "emmc")) ++ return 0; ++ ++ val = readl(SEC_AO_SEC_GP_CFG0); ++ pr_info("SEC_AO_SEC_GP_CFG0 = %x\n", val); ++ if ((val & 0xf) == 0x1) ++ return 1; ++ ++ return 0; ++} ++ ++#if CONFIG_IS_ENABLED(MMC_TINY) ++static struct mmc mmc_static; ++struct mmc *find_mmc_device(int dev_num) ++{ ++ return &mmc_static; ++} ++ ++void mmc_do_preinit(void) ++{ ++ struct mmc *m = &mmc_static; ++#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT ++ mmc_set_preinit(m, 1); ++#endif ++ if (m->preinit) ++ mmc_start_init(m); ++} ++ ++struct blk_desc *mmc_get_blk_desc(struct mmc *mmc) ++{ ++ return &mmc->block_dev; ++} ++#endif ++ ++#if !CONFIG_IS_ENABLED(DM_MMC) ++ ++#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) ++static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout) ++{ ++ return -ENOSYS; ++} ++#endif ++ ++__weak int board_mmc_getwp(struct mmc *mmc) ++{ ++ return -1; ++} ++ ++int mmc_getwp(struct mmc *mmc) ++{ ++ int wp; ++ ++ wp = board_mmc_getwp(mmc); ++ ++ if (wp < 0) { ++ if (mmc->cfg->ops->getwp) ++ wp = mmc->cfg->ops->getwp(mmc); ++ else ++ wp = 0; ++ } ++ ++ return wp; ++} ++ ++__weak int board_mmc_getcd(struct mmc *mmc) ++{ ++ return -1; ++} ++#endif ++ ++#ifdef CONFIG_MMC_TRACE ++void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd) ++{ ++ pr_info("CMD_SEND:%d\n", cmd->cmdidx); ++ pr_info("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); ++} ++ ++void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret) ++{ ++ int i; ++ u8 *ptr; ++ ++ if (ret) { ++ pr_info("\t\tRET\t\t\t %d\n", ret); ++ } else { ++ switch (cmd->resp_type) { ++ case MMC_RSP_NONE: ++ pr_info("\t\tMMC_RSP_NONE\n"); ++ break; ++ case MMC_RSP_R1: ++ pr_info("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", ++ cmd->response[0]); ++ break; ++ case MMC_RSP_R1b: ++ pr_info("\t\tMMC_RSP_R1b\t\t 0x%08X \n", ++ cmd->response[0]); ++ break; ++ case MMC_RSP_R2: ++ pr_info("\t\tMMC_RSP_R2\t\t 0x%08X \n", ++ cmd->response[0]); ++ pr_info("\t\t \t\t 0x%08X \n", ++ cmd->response[1]); ++ pr_info("\t\t \t\t 0x%08X \n", ++ cmd->response[2]); ++ pr_info("\t\t \t\t 0x%08X \n", ++ cmd->response[3]); ++ pr_info("\n"); ++ pr_info("\t\t\t\t\tDUMPING DATA\n"); ++ for (i = 0; i < 4; i++) { ++ int j; ++ pr_info("\t\t\t\t\t%03d - ", i*4); ++ ptr = (u8 *)&cmd->response[i]; ++ ptr += 3; ++ for (j = 0; j < 4; j++) ++ pr_info("%02X ", *ptr--); ++ pr_info("\n"); ++ } ++ break; ++ case MMC_RSP_R3: ++ pr_info("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", ++ cmd->response[0]); ++ break; ++ default: ++ pr_info("\t\tERROR MMC rsp not supported\n"); ++ break; ++ } ++ } ++} ++ ++#endif ++ ++int mmc_get_ext_csd(struct mmc *mmc, u8 *ext_csd) ++{ ++ return mmc_send_ext_csd(mmc, ext_csd); ++} ++ ++#if !CONFIG_IS_ENABLED(MMC_TINY) ++u8 ext_csd_w[] = {191, 187, 185, 183, 179, 178, 177, 175, ++ 173, 171, 169, 167, 165, 164, 163, 162, ++ 161, 156, 155, 143, 140, 136, 134, 133, ++ 132, 131, 62, 59, 56, 52, 37, 34, ++ 33, 32, 31, 30, 29, 22, 17, 16, 15}; ++ ++int mmc_set_ext_csd(struct mmc *mmc, u8 index, u8 value) ++{ ++ int ret = -21, i; ++ ++ for (i = 0; i < sizeof(ext_csd_w); i++) { ++ if (ext_csd_w[i] == index) ++ break; ++ } ++ if (i != sizeof(ext_csd_w)) ++ ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, index, value); ++ ++ return ret; ++} ++ ++ ++#endif ++ ++#if !CONFIG_IS_ENABLED(DM_MMC) ++#ifdef MMC_SUPPORTS_TUNING ++static int mmc_execute_tuning(struct mmc *mmc, uint opcode) ++{ ++ return -ENOTSUPP; ++} ++#endif ++ ++static int mmc_set_ios(struct mmc *mmc) ++{ ++ int ret = 0; ++ ++ if (mmc->cfg->ops->set_ios) ++ ret = mmc->cfg->ops->set_ios(mmc); ++ ++ return ret; ++} ++#endif ++ ++struct mode_width_tuning { ++ enum bus_mode mode; ++ uint widths; ++#ifdef MMC_SUPPORTS_TUNING ++ uint tuning; ++#endif ++}; ++ ++#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE) ++int mmc_voltage_to_mv(enum mmc_voltage voltage) ++{ ++ switch (voltage) { ++ case MMC_SIGNAL_VOLTAGE_000: return 0; ++ case MMC_SIGNAL_VOLTAGE_330: return 3300; ++ case MMC_SIGNAL_VOLTAGE_180: return 1800; ++ case MMC_SIGNAL_VOLTAGE_120: return 1200; ++ } ++ return -EINVAL; ++} ++ ++static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage) ++{ ++ int err; ++ ++ if (mmc->signal_voltage == signal_voltage) ++ return 0; ++ ++ mmc->signal_voltage = signal_voltage; ++ err = mmc_set_ios(mmc); ++ if (err) ++ pr_debug("unable to set voltage (err %d)\n", err); ++ ++ return err; ++} ++#else ++static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage) ++{ ++ return 0; ++} ++#endif ++ ++#if !CONFIG_IS_ENABLED(DM_MMC) ++/* board-specific MMC power initializations. */ ++__weak void board_mmc_power_init(void) ++{ ++} ++#endif ++ ++#ifdef CONFIG_CMD_BKOPS_ENABLE ++int mmc_set_bkops_enable(struct mmc *mmc) ++{ ++ int err; ++ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); ++ ++ err = mmc_send_ext_csd(mmc, ext_csd); ++ if (err) { ++ puts("Could not get ext_csd register values\n"); ++ return err; ++ } ++ ++ if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) { ++ puts("Background operations not supported on device\n"); ++ return -EMEDIUMTYPE; ++ } ++ ++ if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) { ++ puts("Background operations already enabled\n"); ++ return 0; ++ } ++ ++ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1); ++ if (err) { ++ puts("Failed to enable manual background operations\n"); ++ return err; ++ } ++ ++ puts("Enabled manual background operations\n"); ++ ++ return 0; ++} ++#endif ++ ++extern unsigned long blk_dwrite(struct blk_desc *block_dev, lbaint_t start, ++ lbaint_t blkcnt, const void *buffer); ++ ++int mmc_key_write(unsigned char *buf, unsigned int size, uint32_t *actual_lenth) ++{ ++ ulong start, start_blk, blkcnt, ret; ++ unsigned char * temp_buf = buf; ++ int i = 2, dev = EMMC_DTB_DEV; ++ struct partitions * part = NULL; ++ struct mmc *mmc; ++ struct virtual_partition *vpart = NULL; ++ vpart = aml_get_virtual_partition_by_name(MMC_KEY_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ ++ mmc = find_mmc_device(dev); ++ ++ start = part->offset + vpart->offset; ++ start_blk = (start / MMC_BLOCK_SIZE); ++ blkcnt = (size / MMC_BLOCK_SIZE); ++ info_disprotect |= DISPROTECT_KEY; ++ do { ++ ret = blk_dwrite(mmc_get_blk_desc(mmc), start_blk, blkcnt, temp_buf); ++ if (ret != blkcnt) { ++ pr_err("[%s] %d, mmc_bwrite error\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ start_blk += vpart->size / MMC_BLOCK_SIZE; ++ } while (--i); ++ info_disprotect &= ~DISPROTECT_KEY; ++ return 0; ++} ++ ++extern unsigned long blk_derase(struct blk_desc *block_dev, lbaint_t start, ++ lbaint_t blkcnt); ++ ++int mmc_key_erase(void) ++{ ++ ulong start, start_blk, blkcnt, ret; ++ struct partitions * part = NULL; ++ struct virtual_partition *vpart = NULL; ++ struct mmc *mmc; ++ vpart = aml_get_virtual_partition_by_name(MMC_KEY_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ int dev = EMMC_DTB_DEV; ++ ++ mmc = find_mmc_device(dev); ++ start = part->offset + vpart->offset; ++ start_blk = (start / MMC_BLOCK_SIZE); ++ blkcnt = (vpart->size / MMC_BLOCK_SIZE) * 2;//key and backup key ++ info_disprotect |= DISPROTECT_KEY; ++ ret = blk_derase(mmc_get_blk_desc(mmc), start_blk, blkcnt); ++ info_disprotect &= ~DISPROTECT_KEY; ++ if (ret) { ++ pr_err("[%s] %d mmc_berase error\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ return 0; ++} ++ ++ ++int mmc_key_read(unsigned char *buf, unsigned int size, uint32_t *actual_lenth) ++{ ++ ulong start, start_blk, blkcnt, ret; ++ int dev = EMMC_DTB_DEV; ++ unsigned char *temp_buf = buf; ++ struct partitions * part = NULL; ++ struct mmc *mmc; ++ struct virtual_partition *vpart = NULL; ++ vpart = aml_get_virtual_partition_by_name(MMC_KEY_NAME); ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ ++ mmc = find_mmc_device(dev); ++ *actual_lenth = 0x40000;/*key size is 256KB*/ ++ start = part->offset + vpart->offset; ++ start_blk = (start / MMC_BLOCK_SIZE); ++ blkcnt = (size / MMC_BLOCK_SIZE); ++ info_disprotect |= DISPROTECT_KEY; ++ ret = blk_dread(mmc_get_blk_desc(mmc), start_blk, blkcnt, temp_buf); ++ info_disprotect &= ~DISPROTECT_KEY; ++ if (ret != blkcnt) { ++ pr_err("[%s] %d, mmc_bread error\n", ++ __func__, __LINE__); ++ return 1; ++ } ++ return 0; ++} ++ ++ ++ +diff --git a/drivers/mmc/storage_emmc.c b/drivers/mmc/storage_emmc.c +new file mode 100644 +index 00000000000..d938066e49b +--- /dev/null ++++ b/drivers/mmc/storage_emmc.c +@@ -0,0 +1,946 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++ ++#define USER_PARTITION 0 ++#define BOOT0_PARTITION 1 ++#define BOOT1_PARTITION 2 ++#define RPMB_PARTITION 3 ++ ++#define NOMAL_INIT 0 ++#define ERASE_ALL 3 ++#define ERASE_RESERVED 2 ++ ++#define GXB_START_BLK 0 ++#define GXL_START_BLK 1 ++#define STORAGE_EMMC 1 ++/* max 2MB for emmc in blks */ ++#define UBOOT_SIZE (0x1000) ++#define BLOCK_SIZE 512 ++ ++ ++ ++ ++ ++extern int find_dev_num_by_partition_name (char const *name); ++extern struct partitions *get_partition_info_by_num(const int num); ++extern bool emmckey_is_protected(struct mmc *mmc); ++extern int info_disprotect; ++extern int dtb_read(void *addr); ++extern int dtb_write(void *addr); ++extern int renew_partition_tbl(unsigned char *buffer); ++ ++static int storage_range_check(struct mmc *mmc,char const *part_name,loff_t offset, size_t *size,loff_t *off) { ++ ++ struct partitions *part_info = NULL; ++ ++ //cpu_id_t cpu_id = get_cpu_id(); ++ ++ ++ if (strcmp(part_name, "bootloader") == 0) { ++ *off = 0; ++ if (1) { //if (cpu_id.family_id >= MESON_CPU_MAJOR_ID_GXL) { ++ *off += 512; ++ } ++ if (*size == 0) { ++ *size =mmc->capacity_boot; ++ if (1) { //if (cpu_id.family_id >= MESON_CPU_MAJOR_ID_GXL) { ++ *size = *size - 512; ++ } ++ } ++ } else { ++ part_info = find_mmc_partition_by_name(part_name); ++ if (!part_info) { ++ printf("error partition name!\n"); ++ return 1; ++ } ++ if ((part_info->mask_flags & PART_PROTECT_FLAG) && ++ !(info_disprotect & DISPROTECT_KEY)) { ++ printf("%s is protected, pls open it in Dts\n", ++ part_info->name); ++ return 1; ++ } ++ ++ *off = part_info->offset+offset; ++ if (offset >= part_info->size) { ++ printf("Start address out #%s# partition'address region,(off < 0x%llx)\n", ++ part_name, part_info->size); ++ return 1; ++ } ++ if ((*off+*size) > (part_info->size+part_info->offset)) { ++ printf("End address exceeds #%s# partition,(offset = 0x%llx,size = 0x%llx)\n", ++ part_name, part_info->offset,part_info->size); ++ return 1; ++ } ++ ++ if (*size == 0) { ++ *size = part_info->size - offset; ++ } ++ } ++ return 0; ++} ++ ++ ++ ++static int storage_rsv_range_check(char const *part_name, size_t *size,loff_t *off) { ++ ++ struct partitions *part = NULL; ++ struct virtual_partition *vpart = NULL; ++ ++ ++ vpart = aml_get_virtual_partition_by_name(part_name); ++ ++ if (!vpart) { ++ printf("error partition name!\n"); ++ return 1; ++ } ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ if (!part) { ++ printf("error partition name!\n"); ++ return 1; ++ } ++ *off = part->offset + vpart->offset; ++ if ((*size) > vpart->size) { ++ printf("End address exceeds #%s# partition,(offset = 0x%llx,size = 0x%llx)\n", ++ part_name, vpart->offset,vpart->size); ++ return 1; ++ } ++ if (*size == 0) ++ *size = vpart->size; ++ return 0; ++} ++ ++ ++static int storage_byte_read(struct mmc *mmc,loff_t off, size_t size,void *addr) { ++ ++ int blk_shift = 0; ++ u64 cnt = 0, n = 0, blk = 0, sz_byte = 0; ++ ulong start_blk; ++ void *addr_tmp; ++ void *addr_byte; ++ ++ blk_shift = ffs(mmc->read_bl_len) - 1; ++ blk = off >> blk_shift ; ++ cnt = size >> blk_shift ; ++ sz_byte = size - ((cnt) << blk_shift) ; ++ mmc_init(mmc); ++ ++ pr_info("blk:%lld cnt:%lld \n",blk,cnt); ++ n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr); ++ if ((n == cnt) && (sz_byte != 0)) { ++ /*printf("sz_byte=%#llx bytes\n",sz_byte);*/ ++ addr_tmp = malloc(mmc->read_bl_len); ++ addr_byte = (void *)(addr+cnt*(mmc->read_bl_len)); ++ start_blk = blk+cnt; ++ ++ if (addr_tmp == NULL) { ++ printf("mmc read: malloc fail\n"); ++ return 1; ++ } ++ ++ if (blk_dread(mmc_get_blk_desc(mmc), start_blk, 1, addr_tmp) != 1) { // read 1 block ++ free(addr_tmp); ++ printf("mmc read 1 block fail\n"); ++ return 1; ++ } ++ ++ memcpy(addr_byte, addr_tmp, sz_byte); ++ free(addr_tmp); ++ } ++ return (n == cnt) ? 0 : 1; ++ ++ ++} ++ ++static int storage_byte_write(struct mmc *mmc,loff_t off, size_t size,void *addr) { ++ ++ int blk_shift = 0; ++ u64 cnt = 0, n = 0, blk = 0, sz_byte = 0; ++ ++ blk_shift = ffs(mmc->read_bl_len) - 1; ++ blk = off >> blk_shift ; ++ cnt = size >> blk_shift ; ++ sz_byte = size - ((cnt) << blk_shift); ++ mmc_init(mmc); ++ pr_info("blk:%lld cnt:%lld \n",blk,cnt); ++ ++ n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr); ++ if ((n == cnt) && (sz_byte != 0)) { ++ // printf("sz_byte=%#llx bytes\n",sz_byte); ++ void *addr_tmp = malloc(mmc->write_bl_len); ++ void *addr_byte = (void*)(addr+cnt*(mmc->write_bl_len)); ++ ulong start_blk = blk+cnt; ++ ++ if (addr_tmp == NULL) { ++ printf("mmc write: malloc fail\n"); ++ return 1; ++ } ++ ++ if (blk_dread(mmc_get_blk_desc(mmc), start_blk, 1, addr_tmp) != 1) { // read 1 block ++ free(addr_tmp); ++ printf("mmc read 1 block fail\n"); ++ return 1; ++ } ++ ++ memcpy(addr_tmp, addr_byte, sz_byte); ++ if (blk_dwrite(mmc_get_blk_desc(mmc), start_blk, 1, addr_tmp) != 1) { // write 1 block ++ free(addr_tmp); ++ printf("mmc write 1 block fail\n"); ++ return 1; ++ } ++ free(addr_tmp); ++ } ++ //printf("%#llx blocks , %#llx bytes written: %s\n", n, sz_byte, (n==cnt) ? "OK" : "ERROR"); ++ return (n == cnt) ? 0 : 1; ++} ++ ++ ++static int storage_byte_erase(struct mmc *mmc,loff_t off, size_t size) { ++ ++ int blk_shift = 0; ++ u64 cnt = 0, n = 0, blk = 0; ++ ++ blk_shift = ffs(mmc->read_bl_len) - 1; ++ blk = off >> blk_shift ; ++ cnt = size >> blk_shift ; ++ mmc_init(mmc); ++ pr_info("blk:%lld cnt:%lld \n",blk,cnt); ++ if (cnt) ++ n = blk_derase(mmc_get_blk_desc(mmc), blk, cnt); ++ printf("%lld blocks erased: %s\n", cnt, (n == 0) ? "OK" : "ERROR"); ++ return (n == 0) ? 0 : 1; ++} ++ ++static int storage_erase_in_part(char const *part_name, loff_t off, size_t size) ++{ ++ int ret = 1; ++ struct mmc *mmc; ++ loff_t offset; ++ ++ mmc = find_mmc_device(STORAGE_EMMC); ++ if (!mmc) ++ return 1; ++ ++ ret = storage_range_check(mmc,part_name, off, &size, &offset); ++ if (ret) ++ return ret; ++ ++ ret = storage_byte_erase(mmc, offset, size); ++ return (ret == 0) ? 0 : 1; ++} ++ ++ ++ ++static int storage_read_in_part(char const *part_name, loff_t off, size_t size, void *dest) ++{ ++ int ret =1; ++ struct mmc *mmc; ++ loff_t offset; ++ ++ mmc = find_mmc_device(STORAGE_EMMC); ++ if (!mmc) ++ return 1; ++ ++ ret = storage_range_check(mmc,part_name,off,&size,&offset); ++ ++ if (ret) return ret; ++ ++ ret = storage_byte_read(mmc, offset, size, dest); ++ ++ return ret; ++} ++ ++ ++static int storage_write_in_part(char const *part_name, loff_t off, size_t size, void *source) ++{ ++ int ret = 1; ++ loff_t offset; ++ struct mmc *mmc; ++ ++ mmc = find_mmc_device(STORAGE_EMMC); ++ if (!mmc) { ++ printf("Cannot find mmc. \n"); ++ return 1; ++ } ++ ret = storage_range_check(mmc,part_name, off, &size, &offset); ++ if (ret) return ret; ++ ++ ret = storage_byte_write(mmc, offset, size, source); ++ return ret; ++} ++ ++static int storage_mmc_erase_user(struct mmc *mmc) { ++ int ret = 0, i; ++ struct partitions *part_info = NULL; ++ ++ if (info_disprotect & DISPROTECT_KEY) {//key disprotect,erase all ++ ret = blk_derase(mmc_get_blk_desc(mmc), 0, 0); ++ } else {//key protect partition with the protect_flag ++ for (i = 0;;i++) { ++ part_info = get_partition_info_by_num(i); ++ if (part_info == NULL) ++ break; ++ if (!strcmp("reserved", part_info->name)) { ++ printf("Part:reserved is skiped\n"); ++ continue; ++ } ++ if (part_info->mask_flags & PART_PROTECT_FLAG) { ++ printf("Part:%s is protected\n", part_info->name); ++ continue; ++ } ++ ret = blk_derase(mmc_get_blk_desc(mmc), ++ part_info->offset / BLOCK_SIZE, ++ part_info->size / BLOCK_SIZE); ++ printf("Erased: %s %s\n", ++ part_info->name, ++ (ret == 0)? "OK" : "ERR"); ++ } ++ } ++ printf("User partition erased: %s\n", (ret == 0) ? "OK" : "ERROR"); ++ return ret; ++} ++ ++static int storage_mmc_erase(int flag, struct mmc *mmc) { ++ ++ int ret = 0; ++ loff_t off = 0; ++ size_t size = 0; ++ ++ if (flag >= ERASE_ALL) {//erase all except reserved ++ ret = storage_mmc_erase_user(mmc); ++ if (ret != 0) { ++ return -1; ++ } ++ ++ ret = blk_select_hwpart_devnum(UCLASS_MMC, STORAGE_EMMC, BOOT0_PARTITION); ++ if (ret) goto R_SWITCH_BACK; ++ ret = blk_derase(mmc_get_blk_desc(mmc), 0, 0); ++ printf("boot0 partition erased: %s\n", (ret == 0) ? "OK" : "ERROR"); ++ ++ ret = blk_select_hwpart_devnum(UCLASS_MMC, STORAGE_EMMC, BOOT1_PARTITION); ++ ++ if (ret) goto R_SWITCH_BACK; ++ ret = blk_derase(mmc_get_blk_desc(mmc), 0, 0); ++ printf("boot1 partition erased: %s\n", (ret == 0) ? "OK" : "ERROR"); ++R_SWITCH_BACK: ++ ret = blk_select_hwpart_devnum(UCLASS_MMC, STORAGE_EMMC, USER_PARTITION); ++ ++ } else if (flag == ERASE_RESERVED) {//erase reserved ++ ++ info_disprotect |= DISPROTECT_KEY; ++ ret = storage_rsv_range_check("reserved", &size, &off); ++ if (ret != 0) { ++ return -1; ++ } ++ ret = storage_erase_in_part("reserved", off, size); ++ info_disprotect &= ~DISPROTECT_KEY; ++ } ++ ++ return ret; ++ ++ ++} ++ ++ ++ ++int mmc_storage_init(unsigned char init_flag) { ++ ++ int ret =1; ++ struct mmc *mmc; ++ mmc = find_mmc_device(STORAGE_EMMC); ++ mmc->has_init=0; ++ pinctrl_select_state(mmc->dev, "default"); ++ if (!mmc) { ++ return -1; ++ } ++ ret = mmc_init(mmc); ++ if (ret != 0) { ++ return -1; ++ } ++ ret = storage_mmc_erase(init_flag, mmc); ++ return ret; ++} ++ ++ ++ ++ ++ ++uint64_t mmc_storage_get_part_size(const char *part_name) { ++ ++ struct partitions *part_info = NULL; ++ ++ part_info = find_mmc_partition_by_name(part_name); ++ ++ if (part_info == NULL) { ++ printf("get partition info failed !!\n"); ++ return -1; ++ } ++ return part_info->size; ++} ++ ++int mmc_storage_read(const char *part_name, loff_t off, size_t size, void *dest) { ++ ++ int ret=1; ++ struct mmc *mmc; ++ mmc = find_mmc_device(STORAGE_EMMC); ++ ++ if (!mmc) ++ return 1; ++ ++ if (!part_name) {//the operating object is the device,the unit of operation is block. ++ info_disprotect |= DISPROTECT_KEY; ++ ret = blk_dread(mmc_get_blk_desc(mmc), off, size, dest); ++ info_disprotect &= ~DISPROTECT_KEY; ++ printf("%d blocks read: %s\n", ret, (ret == size) ? "OK" : "ERROR"); ++ return (ret == size) ? 0 : 1; ++ ++ } else {//the opering object is partition,the unit of operation is byte. ++ ret = storage_read_in_part(part_name, off,size, dest); ++ } ++ ++ return ret; ++ ++} ++ ++ ++int mmc_storage_write(const char *part_name, loff_t off, size_t size, void *source) { ++ ++ int ret=1; ++ ++ struct mmc *mmc; ++ mmc = find_mmc_device(STORAGE_EMMC); ++ if (!mmc) ++ return 1; ++ ++ if (!part_name) {//the operating object is the device,the unit of operation is block. ++ info_disprotect |= DISPROTECT_KEY; ++ ret = blk_dwrite(mmc_get_blk_desc(mmc), off, size, source); ++ info_disprotect &= ~DISPROTECT_KEY; ++ printf("%d blocks written: %s\n", ret, (ret == size) ? "OK" : "ERROR"); ++ return (ret == size) ? 0 : 1; ++ } else {//the opering object is partition,the unit of operation is byte. ++ ret = storage_write_in_part(part_name, off, size, source); ++ } ++ return ret; ++} ++ ++int mmc_storage_erase(const char *part_name, loff_t off, size_t size, int scrub_flag) { ++ ++ int ret=1; ++ struct mmc *mmc; ++ mmc = find_mmc_device(STORAGE_EMMC); ++ if (!mmc) ++ return 1; ++ ++ if (!part_name) {//the operating object is the device,the unit of operation is block. ++ ret = storage_mmc_erase(ERASE_ALL, mmc); ++ return (ret == 0) ? 0 : 1; ++ } else {//the opering object is partition,the unit of operation is byte. ++ ret = storage_erase_in_part(part_name, off, size); ++ } ++ return ret; ++} ++ ++uint8_t mmc_storage_get_copies(const char *part_name) { ++ ++ char ret=3; ++ ++ return ret; ++ ++} ++ ++ ++uint64_t mmc_get_copy_size(const char *part_name) { ++ ++ struct partitions *part_info = NULL; ++ ++#ifdef CONFIG_AML_GPT ++ return UBOOT_SIZE*512; ++#else ++ part_info = find_mmc_partition_by_name("bootloader"); ++ if (part_info == NULL) { ++ printf("get partition info failed !!\n"); ++ return -1; ++ } ++ return part_info->size; ++#endif ++} ++ ++/* dtb read&write operation with backup updates */ ++static u32 _calc_boot_info_checksum(struct storage_emmc_boot_info *boot_info) ++{ ++ u32 *buffer = (u32*)boot_info; ++ u32 checksum = 0; ++ int i = 0; ++ ++ do { ++ checksum += buffer[i]; ++ } while (i++ < ((EMMC_BOOT_INFO_SIZE >> 2) - 2)); ++ ++ return checksum; ++} ++ ++static int fill_mask8_part(struct part_property *mask8) ++{ ++ struct partitions *part; ++ int i = 0, mask8_cnt = 0; ++ ++ part = get_partition_info_by_num(i); ++ while (part) { ++ if ((part->mask_flags == 8) ++ && (mask8_cnt++ < BOOTINFO_MAX_PARTITIONS)) { ++ strncpy(mask8->name, part->name, strlen(part->name)); ++ mask8->addr = part->offset / MMC_BLOCK_SIZE; ++ mask8->size = part->size / MMC_BLOCK_SIZE; ++ mask8++; ++ } ++ if (mask8_cnt == BOOTINFO_MAX_PARTITIONS) ++ break; ++ i++; ++ part = get_partition_info_by_num(i); ++ } ++ ++ return mask8_cnt; ++} ++ ++static int amlmmc_write_info_sector(struct mmc *mmc) ++{ ++ struct storage_emmc_boot_info *boot_info; ++ struct virtual_partition *ddr_part; ++ struct partitions *part; ++ /* partitons with mask = 8 need to fill to bootinfo */ ++ struct part_property *mask8; ++ int mask8_partition_count; ++ u8 *buffer; ++ int ret = 0, i; ++ ++ buffer = malloc(MMC_BLOCK_SIZE); ++ if (!buffer) ++ return -ENOMEM; ++ ++ memset(buffer, 0, sizeof(*boot_info)); ++ boot_info = (struct storage_emmc_boot_info *)buffer; ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ boot_info->rsv_base_addr = part->offset / MMC_BLOCK_SIZE; ++ ddr_part = aml_get_virtual_partition_by_name(MMC_DDR_PARAMETER_NAME); ++ boot_info->ddr.addr = ddr_part->offset / MMC_BLOCK_SIZE; ++ boot_info->ddr.size = ddr_part->size / MMC_BLOCK_SIZE; ++ ++ mask8 = boot_info->parts; ++ mask8_partition_count = fill_mask8_part(mask8); ++ ++ boot_info->version = 1; ++ boot_info->checksum = _calc_boot_info_checksum(boot_info); ++ ++ printf("boot_info.rsv_base_addr:\t%04x\n", boot_info->rsv_base_addr); ++ printf("boot_info.ddr.addr:%04x\n", boot_info->ddr.addr); ++ printf("boot_info.ddr.size:%04x\n", boot_info->ddr.size); ++ printf("boot info: parts %d\n", mask8_partition_count); ++ for (i = 0; i < mask8_partition_count; i++) { ++ printf("boot_info.part[%d]\n", i); ++ printf("\t.name:%s\n", boot_info->parts[i].name); ++ printf("\t.addr:%04x\n", boot_info->parts[i].addr); ++ printf("\t.size:%04x\n", boot_info->parts[i].size); ++ } ++ printf("boot_info.version:%04x\n", boot_info->version); ++ printf("boot_info.checksum:%04x\n", boot_info->checksum); ++ ++ if (blk_dwrite(mmc_get_blk_desc(mmc), 0, 1, buffer) != 1) ++ ret = -EIO; ++ ++ free(buffer); ++ return ret; ++} ++ ++int mmc_boot_read(const char *part_name, uint8_t cpy, size_t size, void *dest) { ++ ++ char ret=1; ++ int i; ++ ++ if (cpy == 0) ++ cpy = 1; ++ else if (cpy == 1) ++ cpy = 2; ++ else if (cpy == 2) ++ cpy = 4; ++ else if (cpy == 0xff) ++ cpy = 7; ++ for (i=0;i<3;i++) {//cpy: ++ ++ if (cpy & 1) { ++ ret = blk_select_hwpart_devnum(UCLASS_MMC, STORAGE_EMMC, i); ++ if (ret) goto R_SWITCH_BACK; ++#ifdef CONFIG_AML_GPT ++ if (i == 0) ++ continue; ++#endif ++ ret = storage_read_in_part(part_name, 0, size, dest); ++ ++ if (ret != 0) { ++ printf("storage read bootloader failed \n"); ++ goto R_SWITCH_BACK; ++ } ++ } ++ cpy = cpy >> 1; ++ } ++ ++ ++R_SWITCH_BACK: ++ ret = blk_select_hwpart_devnum(UCLASS_MMC, STORAGE_EMMC, USER_PARTITION); ++ if (ret != 0) { ++ printf("switch part failed \n"); ++ return -1; ++ } ++ ++ return ret; ++ ++} ++ ++int mmc_boot_write(const char *part_name, uint8_t cpy, size_t size, void *source) { ++ ++ char ret=1; ++ int i = 0; ++ struct mmc *mmc; ++ ++ mmc = find_mmc_device(STORAGE_EMMC); ++ ++ if (cpy == 0) ++ cpy = 1; ++ else if (cpy == 1) ++ cpy = 2; ++ else if (cpy == 2) ++ cpy = 4; ++ else if (cpy == 0xff) ++ cpy = 7; ++ ++ for (i=0;i<3;i++) {//cpy:bin 100 is oprate boot1,bin 010 is oprate boot0,bin 001 is oprate user bootloader.bin 111 is operate all boot. ++ ++ if (cpy & 1) { ++ ret = blk_select_hwpart_devnum(UCLASS_MMC, STORAGE_EMMC, i); ++ if (ret) goto W_SWITCH_BACK; ++#ifdef CONFIG_EMMC_BOOT1_TOUCH_REGION ++ if (i == 2) { ++ size = CONFIG_EMMC_BOOT1_TOUCH_REGION; ++ } ++#endif ++#ifdef CONFIG_AML_GPT ++ if (i == 0) ++ continue; ++#endif ++ ret = storage_write_in_part(part_name, 0, size, source); ++ ++ if (ret != 0) { ++ printf("storage write bootloader failed \n"); ++ goto W_SWITCH_BACK; ++ } ++ if (i != 0) ++ amlmmc_write_info_sector(mmc); ++ } ++ cpy = cpy >> 1; ++ } ++ ++ ++W_SWITCH_BACK: ++ ret = blk_select_hwpart_devnum(UCLASS_MMC, STORAGE_EMMC, USER_PARTITION); ++ if (ret != 0) { ++ printf("switch part failed \n"); ++ return -1; ++ } ++ ++ return ret; ++ ++} ++ ++int mmc_boot_erase(const char *part_name, uint8_t cpy) { ++ ++ char ret=1; ++ int i; ++ size_t size = 0; ++ ++ if (cpy == 0) ++ cpy = 1; ++ else if (cpy == 1) ++ cpy = 2; ++ else if (cpy == 2) ++ cpy = 4; ++ else if (cpy == 0xff) ++ cpy = 7; ++ for (i=0;i<3;i++) {//cpy: ++ ++ if (cpy & 1) { ++ ret = blk_select_hwpart_devnum(UCLASS_MMC, STORAGE_EMMC, i); ++ if (ret) goto E_SWITCH_BACK; ++#ifdef CONFIG_EMMC_BOOT1_TOUCH_REGION ++ if (i == 2) { ++ size = CONFIG_EMMC_BOOT1_TOUCH_REGION; ++ } ++#endif ++#ifdef CONFIG_AML_GPT ++ if (i == 0) ++ continue; ++#endif ++ ret = storage_erase_in_part(part_name, 0, size); ++ ++ if (ret != 0) { ++ printf("storage read bootloader failed \n"); ++ goto E_SWITCH_BACK; ++ } ++ } ++ cpy = cpy >> 1; ++ } ++ ++ ++E_SWITCH_BACK: ++ ret = blk_select_hwpart_devnum(UCLASS_MMC, STORAGE_EMMC, USER_PARTITION); ++ if (ret != 0) { ++ printf("switch part faild \n"); ++ return -1; ++ } ++ ++ ++ return ret; ++} ++ ++uint32_t mmc_get_rsv_size(const char *rsv_name) { ++ ++ struct virtual_partition *vpart = NULL; ++ vpart = aml_get_virtual_partition_by_name(rsv_name); ++ printf("the %s partition size is:%llx byte\n",rsv_name,vpart->size); ++ return vpart->size; ++ ++} ++ ++static inline int env_read(size_t size, void *buf) { ++ return storage_read_in_part("env", 0, size, buf); ++} ++ ++static inline int env_write(size_t size, void *buf) { ++ return storage_write_in_part("env", 0, size, buf); ++} ++ ++int mmc_read_rsv(const char *rsv_name, size_t size, void *buf) { ++ ++ char ret=1; ++ struct mmc *mmc; ++ loff_t off =0; ++ /*unsigned long dtImgAddr = simple_strtoul(buf, NULL, 16);*/ ++ ret = !strcmp("env", rsv_name) || !strcmp("key", rsv_name) ++ || !strcmp("dtb", rsv_name)||!strcmp("fastboot", rsv_name) ++ ||!strcmp("ddr-parameter", rsv_name); ++ if (!ret) return 1; ++ ++ mmc = find_mmc_device(STORAGE_EMMC); ++ if (!mmc) { ++ puts("no mmc devices available\n"); ++ return 1; ++ } ++ ++ if (!strcmp("env", rsv_name)) { ++ ret = env_read(size, buf); ++ return ret; ++ } ++ ++ ret = storage_rsv_range_check(rsv_name, &size, &off); ++ if (ret) return ret; ++ if (!strcmp("dtb", rsv_name)) { ++ ret = dtb_read(buf); ++ return ret; ++ } ++ ++ if (!strcmp("key", rsv_name)) ++ info_disprotect |= DISPROTECT_KEY; ++ ret = storage_byte_read(mmc, off, size, buf); ++ if (!strcmp("key", rsv_name)) ++ info_disprotect &= ~DISPROTECT_KEY; ++ if (ret != 0) { ++ printf("read resv failed\n"); ++ } ++ ++ return ret; ++} ++int mmc_write_rsv(const char *rsv_name, size_t size, void *buf) { ++ ++ char ret=1; ++ ++ struct mmc *mmc; ++ loff_t off = 0; ++ ++ ret = !strcmp("env", rsv_name) || !strcmp("key", rsv_name) ++ || !strcmp("dtb", rsv_name)||!strcmp("fastboot", rsv_name) ++ ||!strcmp("ddr-parameter", rsv_name); ++ if (!ret) ++ return 1; ++ mmc = find_mmc_device(STORAGE_EMMC); ++ if (!mmc) { ++ puts("no mmc devices available\n"); ++ return 1; ++ } ++ ++ if (!strcmp("env", rsv_name)) { ++ ret = env_write(size, buf); ++ return ret; ++ } ++ ++ ret = storage_rsv_range_check(rsv_name, &size, &off); ++ if (ret) return ret; ++ ++ if (!strcmp("dtb", rsv_name)) { ++ ret = dtb_write(buf); ++ ret |= renew_partition_tbl(buf); ++ } else { ++ if (!strcmp("key", rsv_name)) ++ info_disprotect |= DISPROTECT_KEY; ++ ret = storage_byte_write(mmc, off, size, buf); ++ if (!strcmp("key", rsv_name)) ++ info_disprotect &= ~DISPROTECT_KEY; ++ } ++ ++ if (ret != 0) ++ printf("write rsv failed\n"); ++ ++ return ret; ++} ++int mmc_erase_rsv(const char *rsv_name) { ++ ++ char ret=1; ++ struct mmc *mmc; ++ loff_t off = 0; ++ size_t size = 0; ++ ret = !strcmp("key", rsv_name) || !strcmp("dtb", rsv_name) ++ ||!strcmp("fastboot", rsv_name) ++ ||!strcmp("ddr-parameter", rsv_name); ++ if (!ret) return 1; ++ mmc = find_mmc_device(STORAGE_EMMC); ++ if (!mmc) { ++ puts("no mmc devices available\n"); ++ return 1; ++ } ++ ret = storage_rsv_range_check(rsv_name, &size, &off); ++ if (ret) return ret; ++ if (!strcmp("key", rsv_name)) ++ info_disprotect |= DISPROTECT_KEY; ++ ret = storage_byte_erase(mmc, off, size); ++ if (!strcmp("key", rsv_name)) ++ info_disprotect &= ~DISPROTECT_KEY; ++ if (ret != 0) { ++ printf("erase resv failed\n"); ++ } ++ return ret; ++} ++ ++int mmc_protect_rsv(const char *rsv_name, bool ops) { ++ ++ char ret=1; ++ ret = strcmp("key", rsv_name); ++ if (ret) return 1; ++ ++ if (ops) { ++ ++ info_disprotect &= ~DISPROTECT_KEY; ++ printf("Protect the key partition!\n"); ++ } else { ++ info_disprotect |= DISPROTECT_KEY; ++ printf("Disprotect the key partition!\n"); ++ } ++ return ret; ++ ++} ++ ++void config_storage_dev_func(struct storage_t *dev, struct mmc* mmc) ++{ ++ /******basic info*******/ ++ dev->type = BOOT_EMMC; ++ printf("store flag: %d, types: %d\n", dev->init_flag, dev->type); ++ /*dev->info.name = mmc->cid[0] & 0xff, ++ (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, ++ (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff; ++ dev->info.id = mmc->cid[0] >> 24;*/ ++ dev->info.read_unit = mmc->read_bl_len; ++ dev->info.write_unit = mmc->write_bl_len; ++ dev->info.erase_unit = mmc->erase_grp_size; ++ dev->info.caps = mmc->capacity_user; ++ dev->info.mode = COMPACT_BOOTLOADER; ++ ++ dev->get_part_size = mmc_storage_get_part_size; ++ dev->read = mmc_storage_read; ++ dev->write = mmc_storage_write; ++ dev->erase = mmc_storage_erase; ++ ++ dev->get_copies = mmc_storage_get_copies; ++ dev->get_copy_size = mmc_get_copy_size; ++ dev->boot_read = mmc_boot_read; ++ dev->boot_write = mmc_boot_write; ++ dev->boot_erase = mmc_boot_erase; ++ ++ dev->get_rsv_size = mmc_get_rsv_size; ++ dev->read_rsv = mmc_read_rsv; ++ dev->write_rsv = mmc_write_rsv; ++ dev->erase_rsv = mmc_erase_rsv; ++ dev->protect_rsv = mmc_protect_rsv; ++ ++ return; ++} ++ ++DECLARE_GLOBAL_DATA_PTR; ++int sdcard_pre(void) ++{ ++ return 0; ++} ++ ++ ++int sdcard_probe(uint32_t init_flag) ++{ ++ return 0; ++} ++ ++int emmc_pre(void) ++{ ++ char ret = 1; ++ struct mmc *mmc; ++ static struct storage_t *storage_dev = NULL; ++ ++ mmc_initialize(gd->bd); ++ mmc = find_mmc_device(STORAGE_EMMC); ++ mmc->has_init = 0; ++ ret = mmc_start_init(mmc); ++ if (ret == 0) { ++ /*struct store_operation *storage_opera = NULL;*/ ++ storage_dev = kzalloc(sizeof(struct storage_t), GFP_KERNEL); ++ if (storage_dev == NULL) { ++ printf("malloc failed for storage_dev\n"); ++ ret = -1; ++ return ret; ++ } ++ config_storage_dev_func(storage_dev, mmc); ++ store_register(storage_dev); ++ printf("emmc init success!\n"); ++ } else ++ printf("emmc init fail!\n"); ++ return ret; ++} ++ ++ ++int emmc_probe(uint32_t init_flag) ++{ ++ char ret = 0; ++ ++ ret = mmc_storage_init(init_flag); /*flag 0*/ ++ if (ret) { ++ printf("mmc init failed ret:%x\n", ret); ++ goto exit_error; ++ } ++ printf("emmc probe success\n"); ++ ++exit_error: ++ return ret; ++} ++ +diff --git a/include/amlogic/aml_cec.h b/include/amlogic/aml_cec.h +new file mode 100644 +index 00000000000..4f0b2bd3a1a +--- /dev/null ++++ b/include/amlogic/aml_cec.h +@@ -0,0 +1,86 @@ ++/* ++ * include/amlogic/aml_cec.h ++ * ++ * Copyright (C) 2012 AMLOGIC, INC. All Rights Reserved. ++ * Author: hongmin hua ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the smems of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ */ ++ ++ ++#ifndef _AML_CEC_H ++#define _AML_CEC_H ++ ++/* ++ * CEC OPCODES ++ */ ++#define CEC_OC_ABORT_MESSAGE 0xFF ++#define CEC_OC_ACTIVE_SOURCE 0x82 ++#define CEC_OC_CEC_VERSION 0x9E ++#define CEC_OC_CLEAR_ANALOGUE_TIMER 0x33 ++#define CEC_OC_CLEAR_DIGITAL_TIMER 0x99 ++#define CEC_OC_CLEAR_EXTERNAL_TIMER 0xA1 ++#define CEC_OC_DECK_CONTROL 0x42 ++#define CEC_OC_DECK_STATUS 0x1B ++#define CEC_OC_DEVICE_VENDOR_ID 0x87 ++#define CEC_OC_FEATURE_ABORT 0x00 ++#define CEC_OC_GET_CEC_VERSION 0x9F ++#define CEC_OC_GET_MENU_LANGUAGE 0x91 ++#define CEC_OC_GIVE_AUDIO_STATUS 0x71 ++#define CEC_OC_GIVE_DECK_STATUS 0x1A ++#define CEC_OC_GIVE_DEVICE_POWER_STATUS 0x8F ++#define CEC_OC_GIVE_DEVICE_VENDOR_ID 0x8C ++#define CEC_OC_GIVE_OSD_NAME 0x46 ++#define CEC_OC_GIVE_PHYSICAL_ADDRESS 0x83 ++#define CEC_OC_GIVE_SYSTEM_AUDIO_MODE_STATUS 0x7D ++#define CEC_OC_GIVE_TUNER_DEVICE_STATUS 0x08 ++#define CEC_OC_IMAGE_VIEW_ON 0x04 ++#define CEC_OC_INACTIVE_SOURCE 0x9D ++#define CEC_OC_MENU_REQUEST 0x8D ++#define CEC_OC_MENU_STATUS 0x8E ++#define CEC_OC_PLAY 0x41 ++#define CEC_OC_POLLING_MESSAGE 0xFC /* Fake Code - has no OP Code and requires only the header byte */ ++#define CEC_OC_RECORD_OFF 0x0B ++#define CEC_OC_RECORD_ON 0x09 ++#define CEC_OC_RECORD_STATUS 0x0A ++#define CEC_OC_RECORD_TV_SCREEN 0x0F ++#define CEC_OC_REPORT_AUDIO_STATUS 0x7A ++#define CEC_OC_REPORT_PHYSICAL_ADDRESS 0x84 ++#define CEC_OC_REPORT_POWER_STATUS 0x90 ++#define CEC_OC_REQUEST_ACTIVE_SOURCE 0x85 ++#define CEC_OC_ROUTING_CHANGE 0x80 ++#define CEC_OC_ROUTING_INFORMATION 0x81 ++#define CEC_OC_SELECT_ANALOGUE_SERVICE 0x92 ++#define CEC_OC_SELECT_DIGITAL_SERVICE 0x93 ++#define CEC_OC_SET_ANALOGUE_TIMER 0x34 ++#define CEC_OC_SET_AUDIO_RATE 0x9A ++#define CEC_OC_SET_DIGITAL_TIMER 0x97 ++#define CEC_OC_SET_EXTERNAL_TIMER 0xA2 ++#define CEC_OC_SET_MENU_LANGUAGE 0x32 ++#define CEC_OC_SET_OSD_NAME 0x47 ++#define CEC_OC_SET_OSD_STRING 0x64 ++#define CEC_OC_SET_STREAM_PATH 0x86 ++#define CEC_OC_SET_SYSTEM_AUDIO_MODE 0x72 ++#define CEC_OC_SET_TIMER_PROGRAM_TITLE 0x67 ++#define CEC_OC_STANDBY 0x36 ++#define CEC_OC_SYSTEM_AUDIO_MODE_REQUEST 0x70 ++#define CEC_OC_SYSTEM_AUDIO_MODE_STATUS 0x7E ++#define CEC_OC_TEXT_VIEW_ON 0x0D ++#define CEC_OC_TIMER_CLEARED_STATUS 0x43 ++#define CEC_OC_TIMER_STATUS 0x35 ++#define CEC_OC_TUNER_DEVICE_STATUS 0x07 ++#define CEC_OC_TUNER_STEP_DECREMENT 0x06 ++#define CEC_OC_TUNER_STEP_INCREMENT 0x05 ++#define CEC_OC_USER_CONTROL_PRESSED 0x44 ++#define CEC_OC_USER_CONTROL_RELEASED 0x45 ++#define CEC_OC_VENDOR_COMMAND 0x89 ++#define CEC_OC_VENDOR_COMMAND_WITH_ID 0xA0 ++#define CEC_OC_VENDOR_REMOTE_BUTTON_DOWN 0x8A ++#define CEC_OC_VENDOR_REMOTE_BUTTON_UP 0x8B ++ ++int cec_hw_init(int logic_addr, unsigned char fun_cfg); ++ ++#endif/*_AML_CEC_H*/ ++ +diff --git a/include/amlogic/aml_efuse.h b/include/amlogic/aml_efuse.h +new file mode 100644 +index 00000000000..4dece0725de +--- /dev/null ++++ b/include/amlogic/aml_efuse.h +@@ -0,0 +1,79 @@ ++ ++/* ++ * ++ * Copyright (C) 2018 Amlogic, Inc. All rights reserved. ++*/ ++ ++#ifndef __BL2_EFUSE_H__ ++#define __BL2_EFUSE_H__ ++ ++#if 0 ++//just keep following CFG10/9 for new API implement ++#define IS_FEAT_USB_PD_CHK_ENABLE() (readl(AO_SEC_SD_CFG10) & (1 << 1)) ++#define IS_FEAT_THERMAL_CALIBRATED() (readl(AO_SEC_SD_CFG10) & (1 << 2)) ++#define IS_FEAT_BOOT_VERIFY() (readl(AO_SEC_SD_CFG10) & (1 << 4)) ++#define IS_FEAT_ROOT_KEY_BURNED() (readl(AO_SEC_SD_CFG10) & (1 << 5)) ++#define IS_FEAT_PLL_SET_BURNED() (readl(AO_SEC_SD_CFG10) & (1 << 6)) ++#define IS_FEAT_M3_PLL_ENABLE() (readl(AO_SEC_SD_CFG10) & (1 << 7)) ++#define IS_FEAT_M4_PLL_ENABLE() (readl(AO_SEC_SD_CFG10) & (1 << 7)) ++#define IS_FEAT_A53_PLL_ENABLE() (readl(AO_SEC_SD_CFG10) & (1 << 8)) ++#define IS_FEAT_NAMD_EXT_CMD_BURNED() (readl(AO_SEC_SD_CFG10) & (1 << 9)) ++#define IS_FEAT_JTG_PD_CHK_ENABLE() (readl(AO_SEC_SD_CFG10) & (1 << 11)) ++#define IS_FEAT_JTG_ENABLE() (readl(AO_SEC_SD_CFG10) & (1 << 12)) ++#define IS_FEAT_CHIP_ID_BURNED (readl(AO_SEC_SD_CFG10) & (1 << 13)) ++#define IS_FEAT_DTS_ENABLE (readl(AO_SEC_SD_CFG10) & (1 << 14)) ++#define IS_FEAT_DISK_ENC_ENABLE (readl(AO_SEC_SD_CFG10) & (1 << 15)) ++#define IS_FEAT_DOLBY_AUDIO_ENABLE (readl(AO_SEC_SD_CFG10) & (1 << 16)) ++#define IS_FEAT_SCN_PD_CHK_ENABLE (readl(AO_SEC_SD_CFG10) & (1 << 17)) ++#define IS_FEAT_USB_BOOT_ENABLE (readl(AO_SEC_SD_CFG10) & (1 << 19)) ++#define IS_FEAT_SPI_BOOT_ENABLE (readl(AO_SEC_SD_CFG10) & (1 << 20)) ++#define IS_FEAT_RECOVERY_BOOT_ENABLE (readl(AO_SEC_SD_CFG10) & (1 << 21)) ++#define IS_FEAT_SD_BOOT_ENABLE (readl(AO_SEC_SD_CFG10) & (1 << 22)) ++#define IS_FEAT_NAND_EMMC_BOOT_ENABLE (readl(AO_SEC_SD_CFG10) & (1 << 23)) ++#define IS_FEAT_ANTIROLLBACK_ENABLE (readl(AO_SEC_SD_CFG10) & (1 << 25)) ++#define IS_FEAT_BOOT_ENCRYPT() (readl(AO_SEC_SD_CFG10) & (1 << 28)) ++#define IS_FEAT_A53_L1_ENABLE() (readl(AO_SEC_SD_CFG10) & (1 << 29)) ++#define IS_FEAT_KEY_LDR_INIT() (readl(AO_SEC_SD_CFG10) & (1 << 30)) ++#define IS_FEAT_AP_COLD_BOOT_LOCK() (readl(AO_SEC_SD_CFG10) & (1 << 31)) ++#define IS_FEAT_BOOT_M3_ENCRYPT() (readl(AO_SEC_SD_CFG9) & (1 << 5)) ++#define IS_FEAT_BOOT_M4_ENCRYPT() (readl(AO_SEC_SD_CFG9) & (1 << 6)) ++#define IS_FEAT_NAND_BL2_BKP_RETRY() (readl(AO_SEC_SD_CFG9) & (1 << 10)) ++#define IS_FEAT_EMMC_BL2_BKP_RETRY() (readl(AO_SEC_SD_CFG9) & (1 << 11)) ++#define IS_FEAT_SCAN_DISABLE() (readl(AO_SEC_SD_CFG9) & (1 << 12)) ++#define IS_FEAT_NAND_128P_DISABLE() (readl(AO_SEC_SD_CFG9) & (1 << 13)) ++#define IS_FEAT_EMMC_LAST_ENABLE() (readl(AO_SEC_SD_CFG9) & (1 << 14)) ++#define IS_FEAT_HIGH_USB_ENABLE() (readl(AO_SEC_SD_CFG9) & (1 << 15)) ++#define IS_FEAT_BOOT_M3_VERIFY() (readl(AO_SEC_SD_CFG9) & (1 << 16)) ++#define IS_FEAT_BOOT_M4_VERIFY() (readl(AO_SEC_SD_CFG9) & (1 << 17)) ++#define IS_FEAT_CORNOR_INFO_BURNED() (readl(AO_SEC_SD_CFG9) & (1 << 19)) ++#define IS_FEAT_SCK_BURNED() (readl(AO_SEC_SD_CFG9) & (1 << 20)) ++#define IS_FEAT_BLK0_WR_LOCKED() (readl(AO_SEC_SD_CFG9) & (1 << 21)) ++#define IS_FEAT_M4_DISABLE() (readl(AO_SEC_SD_CFG9) & (1 << 22)) ++#define IS_FEAT_M4_SP_MODE_ENABLE() (readl(AO_SEC_SD_CFG9) & (1 << 23)) ++#define IS_FEAT_A53_CLK_12G() (readl(AO_SEC_SD_CFG9) & (1 << 24)) ++#define IS_FEAT_A53_CLK_15G() (readl(AO_SEC_SD_CFG9) & (1 << 25)) ++#define IS_FEAT_A53_CLK_20G() (readl(AO_SEC_SD_CFG9) & (1 << 26)) ++#define IS_FEAT_USB_PLL_ENABLE() (readl(AO_SEC_SD_CFG9) & (1 << 27)) ++#define IS_FEAT_RMA_ENABLE() (readl(AO_SEC_SD_CFG9) & (1 << 28)) ++#define IS_FEAT_OPS_CLI_BURNED() (readl(AO_SEC_SD_CFG9) & (1 << 29)) ++#define IS_FEAT_M4_UNLOCK_ENABLE() (readl(AO_SEC_SD_CFG9) & (1 << 31)) ++#define IS_FEAT_DISABLE_PRINT() (readl(EFUSE_LIC0) & (1 << 22))) ++#endif ++ ++//weak function for each SoC implement ++//Unify EFUSE license query API ++//all following functions are defined with "weak" for customization of each SoC ++//EFUSE_LICX --> AO_SEC_SD_CFG10/9 --> EFUSE mirror ++int IS_FEAT_BOOT_VERIFY(void); ++int IS_FEAT_BOOT_ENCRYPT(void); ++int IS_FEAT_DIS_EMMC_USER(void); ++int IS_FEAT_DIS_EMMC_BOOT_0(void); ++int IS_FEAT_DIS_EMMC_BOOT_1(void); ++int IS_FEAT_EN_4BL2_SNOR(void); ++int IS_FEAT_DIS_NBL2_SNOR(void); ++int IS_FEAT_EN_8BL2_SNAND(void); ++int IS_FEAT_DIS_NBL2_SNAND(void); ++int IS_FEAT_DIS_8BL2_NAND(void); ++int IS_FEAT_DIS_NBL2_NAND(void); ++ ++#endif /* __BL2_EFUSE_H__ */ +diff --git a/include/amlogic/aml_gpio.h b/include/amlogic/aml_gpio.h +new file mode 100644 +index 00000000000..c1e1ed1ef5a +--- /dev/null ++++ b/include/amlogic/aml_gpio.h +@@ -0,0 +1,54 @@ ++#ifndef __AML_GPIO__ ++#define __AML_GPIO__ ++#include ++/** ++ * struct meson_reg_desc - a register descriptor ++ * ++ * @reg: register offset in the regmap ++ * @bit: bit index in register ++ * ++ * The structure describes the information needed to control pull, ++ * pull-enable, direction, etc. for a single pin ++ */ ++struct meson_reg_desc { ++ unsigned int reg; ++ unsigned int bit; ++}; ++ ++/** ++ * enum meson_reg_type - type of registers encoded in @meson_reg_desc ++ */ ++enum meson_reg_type { ++ REG_PULLEN, ++ REG_PULL, ++ REG_DIR, ++ REG_OUT, ++ REG_IN, ++ NUM_REG, ++}; ++ ++ ++ ++ ++struct meson_bank { ++ const char *name; ++ unsigned int first; ++ unsigned int last; ++ struct meson_reg_desc regs[NUM_REG]; ++}; ++#define GPIO_REG_BIT(reg, bit) ((reg<<5)|bit) ++#define GPIO_REG(value) ((value>>5)) ++#define GPIO_BIT(value) ((value&0x1F)) ++//#define BIT(bit) (1< ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the smems of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ */ ++ ++#ifndef _AML_HDMIRX_H ++#define _AML_HDMIRX_H ++ ++void hdmirx_hw_init(unsigned int port_map, ++ unsigned char *pedid_data, ++ int edid_size); ++ ++#endif /* _AML_HDMIRX_H */ +diff --git a/include/amlogic/aml_irblaster.h b/include/amlogic/aml_irblaster.h +new file mode 100644 +index 00000000000..b2c4ef703e7 +--- /dev/null ++++ b/include/amlogic/aml_irblaster.h +@@ -0,0 +1,29 @@ ++#ifndef __AML_IRBLATER_H ++#define __AML_IRBLATER_H ++ ++#define MAX_WINDOWS_LEN 512 ++struct aml_irblaster_drv_s { ++ unsigned int protocol; ++ unsigned int frequency; ++ unsigned int sendvalue; ++ unsigned int windows[MAX_WINDOWS_LEN]; ++ unsigned int windows_num; ++ unsigned int dutycycle; ++ unsigned int openflag; ++ int (*open)(void); ++ int (*close)(void); ++ int (*test)(unsigned int); ++ int (*send)(unsigned int); ++ int (*setprotocol)(char *); ++ const char *(*getprocotol)(void); ++ int (*setfrequency)(unsigned int); ++ unsigned int (*getfrequency)(void); ++ void (*print_windows)(void); ++ int (*read_reg)(volatile unsigned int *, unsigned int); ++ int (*write_reg)(volatile unsigned int *, unsigned int); ++}; ++ ++struct aml_irblaster_drv_s *aml_irblaster_get_driver(void); ++#endif ++ ++ +diff --git a/include/amlogic/aml_is31fl32xx.h b/include/amlogic/aml_is31fl32xx.h +new file mode 100644 +index 00000000000..6211ebc956c +--- /dev/null ++++ b/include/amlogic/aml_is31fl32xx.h +@@ -0,0 +1,9 @@ ++#ifndef __AML_IS31F132XX ++#define __AML_IS31F132XX ++ ++#define IS31F132XX_DEVICE_ADDR 0x3c ++ ++void board_is31fl32xx_init(void); ++void board_is31fl32xx_light_on(void); ++ ++#endif +diff --git a/include/amlogic/aml_led.h b/include/amlogic/aml_led.h +new file mode 100644 +index 00000000000..b2f3bda3f7a +--- /dev/null ++++ b/include/amlogic/aml_led.h +@@ -0,0 +1,68 @@ ++#ifndef __AML_LED_H__ ++#define __AML_LED_H__ ++ ++#define LED_TIMER_INTERVAL 10 //ms ++ ++#define LED_EVENT_NULL 0 ++#define LED_EVENT_OFF 1 ++#define LED_EVENT_ON 2 ++#define LED_EVENT_FLASH 3 ++#define LED_EVENT_BREATH 4 ++ ++#define SHUTDOWN_MODE 0 ++#define SUSPEND_RESUME_MODE 1 ++#define RECOVERY_MODE 2 ++ ++ ++enum led_workmode { ++ LWM_OFF, ++ LWM_ON, ++ LWM_FLASH, ++ LWM_BREATH, ++ LWM_NULL, ++}; ++ ++/* s,b,w type is enum led_workmode */ ++#define lwm_set_standby(mode, s) do {mode |= (s) << 0;} while(0) ++#define lwm_set_booting(mode, b) do {mode |= (b) << 4;} while(0) ++#define lwm_set_working(mode, w) do {mode |= (w) << 8;} while(0) ++#define lwm_set_suspend(mode, s) do {mode |= (s) << 12;} while(0) ++ ++#define lwm_get_standby(mode) (((mode) >> 0) & 0xF) ++#define lwm_get_booting(mode) (((mode) >> 4) & 0xF) ++#define lwm_get_working(mode) (((mode) >> 8) & 0xF) ++#define lwm_get_suspend(mode) (((mode) >> 12) & 0xF) ++ ++struct coord { ++ int x; ++ int y; ++}; ++ ++struct aml_led_config { ++ int off_brightness; ++ int on_brightness; ++ int flash_off_brightness; ++ int flash_off_time; ++ int flash_on_brightness; ++ int flash_on_time; ++ struct coord *breath_inflections; ++ int breath_inflections_num; ++ void (*set_brightness)(int brightness); ++}; ++ ++#define LED_EVENT_BUF_SIZE 3 ++struct aml_led { ++ int event[LED_EVENT_BUF_SIZE]; ++ int event_data[LED_EVENT_BUF_SIZE]; ++ int state; ++ int brightness; ++ int time; ++ int count; ++ struct aml_led_config *config; ++}; ++ ++void aml_led_init(struct aml_led *led, struct aml_led_config *config); ++void aml_led_timer_proc(struct aml_led *led); ++void aml_led_event(struct aml_led *led, int event, int event_data); ++ ++#endif +\ No newline at end of file +diff --git a/include/amlogic/aml_mmc.h b/include/amlogic/aml_mmc.h +new file mode 100644 +index 00000000000..4d7801c04e0 +--- /dev/null ++++ b/include/amlogic/aml_mmc.h +@@ -0,0 +1,105 @@ ++/* ++ * Copyright (C) 2017 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * yonghui.yu@amlogic.com ++ */ ++ ++ ++#ifndef __AML_MMC_H__ ++#define __AML_MMC_H__ ++ ++#include ++ ++ ++/* bootloader operation */ ++#define AML_BL_USER (0x1 << 0) ++#define AML_BL_BOOT0 (0x1 << 1) ++#define AML_BL_BOOT1 (0x1 << 2) ++#define AML_BL_BOOT (0x6) ++#define AML_BL_ALL (0x7) ++ ++/** For actul partitions with mask 8 store into bootinfo ++ * name: partition name. ++ * addr: sector addr of the partition ++ * size: sector cont of the partition ++*/ ++struct part_property ++{ ++ char name[8]; ++ uint32_t addr; ++ uint32_t size; ++}; ++#define PART_PROPERTY_SIZE sizeof(struct part_property) ++#define BOOTINFO_MAX_PARTITIONS (4) ++#define BOOTINFO_PARITIONS_SIZE (PART_PROPERTY_SIZE * BOOTINFO_MAX_PARTITIONS) ++ ++ ++#define VPART_PROPERTY_SIZE sizeof(struct vpart_property) ++struct vpart_property { ++ u32 addr; ++ u32 size; ++}; ++ ++/* ++ * sizeof(struct storage_emmc_boot_info) is strictly ++ * smaller than or equal to one sector. we will bind ++ * it in one sector with u-boot.bin together and ++ * write into boot loader area. ++ * @rsv_base_addr : the sector address of reserved area ++ * @dtb : the sector address and size of dtb property ++ * @ddr : the sector address and size of ddr property ++ */ ++#define EMMC_BOOT_INFO_SIZE 512 ++struct storage_emmc_boot_info { ++ u32 version; ++ u32 rsv_base_addr; ++ struct vpart_property dtb; ++ struct vpart_property ddr; ++ ++ struct part_property parts[BOOTINFO_MAX_PARTITIONS]; ++ uint8_t reserved[512 - 2 * VPART_PROPERTY_SIZE - BOOTINFO_PARITIONS_SIZE - 12]; ++ u32 checksum; ++}; ++ ++int amlmmc_write_bootloader(int dev, int map, ++ unsigned int size, const void *src); ++int amlmmc_erase_bootloader(int dev, int map); ++ ++ ++/* interface on reserved area. */ ++void mmc_write_cali_mattern(void *addr); ++ ++/* dtb operation */ ++int dtb_write(void *addr); ++ ++/* emmc key operation */ ++int mmc_key_read(unsigned char *buf, ++ unsigned int size, uint32_t *actual_lenth); ++int mmc_key_write(unsigned char *buf, ++ unsigned int size, uint32_t *actual_lenth); ++int mmc_key_erase(void); ++ ++/* partition operation */ ++int renew_partition_tbl(unsigned char *buffer); ++int find_dev_num_by_partition_name (char const *name); ++ ++#ifdef CONFIG_AML_PARTITION ++int emmc_update_mbr(unsigned char *buffer); ++#endif ++ ++/*mmc ext_csd register operation*/ ++int mmc_get_ext_csd(struct mmc *mmc, u8 *ext_csd); ++int mmc_set_ext_csd(struct mmc *mmc, u8 index, u8 value); ++ ++ ++ ++#endif /* __AML_MMC_H__ */ +diff --git a/include/amlogic/aml_mtd.h b/include/amlogic/aml_mtd.h +new file mode 100644 +index 00000000000..4eb17e4fa28 +--- /dev/null ++++ b/include/amlogic/aml_mtd.h +@@ -0,0 +1,31 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Header file of amlogic mtd driver ++ * ++ * Copyright (C) 2018 Amlogic Corporation ++ * ++ * Licensed under the GPL-2 or later. ++ * ++ */ ++ ++#ifndef __AMLMTD_H_ ++#define __AMLMTD_H_ ++#define BOOT_TOTAL_PAGES 1024 ++ ++#define CONFIG_BL2_COPY_NUM 8 ++#define CONFIG_TPL_SIZE_PER_COPY 0x200000 ++#define CONFIG_NOR_TPL_COPY_NUM 1 //for spi-nor ++#define CONFIG_NAND_TPL_COPY_NUM 4 // for slc & spi-nand ++ ++#define BOOT_LOADER "bootloader" ++#define BOOT_BL2 "bl2" ++#define BOOT_SPL "spl" ++#define BOOT_BL2E "bl2e" ++#define BOOT_BL2X "bl2x" ++#define BOOT_DDRFIP "ddrfip" ++#define BOOT_DEVFIP "devfip" ++#define BOOT_TPL "tpl" ++#define BOOT_FIP "fip" ++#define MAX_MTD_CNT 2 ++ ++#endif/* __AMLMTD_H_ */ +diff --git a/include/amlogic/aml_nand.h b/include/amlogic/aml_nand.h +new file mode 100644 +index 00000000000..8be39746818 +--- /dev/null ++++ b/include/amlogic/aml_nand.h +@@ -0,0 +1,24 @@ ++/* ++ * Copyright (C) 2017 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ */ ++#ifndef __AML_NAND_H__ ++#define __AML_NAND_H__ ++ ++int amlnf_dtb_save(u8 *buf, unsigned int len); ++int amlnf_dtb_erase(void); ++int get_boot_num(struct mtd_info *mtd, size_t rwsize); ++ ++/*#define RESERVED_BLOCK_NUM 48*/ ++ ++#endif/* __AML_NAND_H__ */ +diff --git a/include/amlogic/aml_rsv.h b/include/amlogic/aml_rsv.h +new file mode 100644 +index 00000000000..7e17c83435a +--- /dev/null ++++ b/include/amlogic/aml_rsv.h +@@ -0,0 +1,106 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Header file of amlogic reserve manager ++ * ++ * Copyright (C) 2018 Amlogic Corporation ++ * ++ * Licensed under the GPL-2 or later. ++ * ++ */ ++ ++#ifndef __MESON_RSV_H_ ++#define __MESON_RSV_H_ ++ ++#define NAND_RSV_BLOCK_NUM 48 ++ ++#define NAND_GAP_BLOCK_NUM 4 ++#define NAND_BBT_BLOCK_NUM 4 ++#define NAND_ENV_BLOCK_NUM 8 ++#define NAND_KEY_BLOCK_NUM 8 ++#define NAND_DTB_BLOCK_NUM 4 ++ ++#define BBT_NAND_MAGIC "nbbt" ++#define ENV_NAND_MAGIC "nenv" ++#define KEY_NAND_MAGIC "nkey" ++#define SEC_NAND_MAGIC "nsec" ++#define DTB_NAND_MAGIC "ndtb" ++ ++/*define abnormal state for reserved area*/ ++#define POWER_ABNORMAL_FLAG 0x01 ++#define ECC_ABNORMAL_FLAG 0x02 ++ ++ ++struct meson_rsv_info_t { ++ struct mtd_info *mtd; ++ struct valid_node_t *nvalid; ++ struct free_node_t *nfree; ++ unsigned int start; ++ unsigned int end; ++ unsigned int size; ++ char name[8]; ++ u_char valid; ++ u_char init; ++ void *handler; ++}; ++ ++struct valid_node_t { ++ s16 ec; ++ s16 blk_addr; ++ s16 page_addr; ++ int timestamp; ++ s16 status; ++}; ++ ++struct free_node_t { ++ unsigned int index; ++ s16 ec; ++ s16 blk_addr; ++ int dirty_flag; ++ struct free_node_t *next; ++}; ++ ++struct oobinfo_t { ++ char name[4]; ++ s16 ec; ++ unsigned timestamp:15; ++ unsigned status_page:1; ++}; ++ ++struct meson_rsv_handler_t { ++ struct mtd_info *mtd; ++ unsigned long long fn_bitmask; ++ struct free_node_t *free_node[NAND_RSV_BLOCK_NUM]; ++ struct meson_rsv_info_t *bbt; ++#ifndef CONFIG_ENV_IS_IN_NAND ++ struct meson_rsv_info_t *env; ++#endif ++ struct meson_rsv_info_t *key; ++ struct meson_rsv_info_t *dtb; ++ void *priv; ++}; ++ ++int meson_rsv_bbt_read(u_char *dest, size_t size); ++int meson_rsv_key_read(u_char *dest, size_t size); ++int meson_rsv_env_read(u_char *dest, size_t size); ++int meson_rsv_dtb_read(u_char *dest, size_t size); ++/* do not provide bbt write operates */ ++int meson_rsv_key_write(u_char *source, size_t size); ++int meson_rsv_env_write(u_char *source, size_t size); ++int meson_rsv_dtb_write(u_char *source, size_t size); ++uint32_t meson_rsv_bbt_size(void); ++uint32_t meson_rsv_key_size(void); ++uint32_t meson_rsv_env_size(void); ++uint32_t meson_rsv_dtb_size(void); ++/* do not provide bbt erase operates */ ++int meson_rsv_key_erase(void); ++int meson_rsv_env_erase(void); ++int meson_rsv_dtb_erase(void); ++int meson_rsv_check(struct meson_rsv_info_t *rsv_info); ++int meson_rsv_init(struct mtd_info *mtd, struct meson_rsv_handler_t *handler); ++int meson_rsv_scan(struct meson_rsv_info_t *rsv_info); ++int meson_rsv_read(struct meson_rsv_info_t *rsv_info, u_char *buf); ++int meson_rsv_save(struct meson_rsv_info_t *rsv_info, u_char *buf); ++int meson_rsv_write(struct meson_rsv_info_t *rsv_info, u_char *buf); ++int meson_rsv_erase_protect(struct meson_rsv_handler_t *handler, ++uint32_t block_addr); ++#endif/* __MESON_RSV_H_ */ +diff --git a/include/amlogic/aml_tlv.h b/include/amlogic/aml_tlv.h +new file mode 100644 +index 00000000000..93fa0a305f4 +--- /dev/null ++++ b/include/amlogic/aml_tlv.h +@@ -0,0 +1,157 @@ ++/* ++ * Copyright (C) 2018 Amlogic, Inc. All rights reserved. ++ * ++ * All information contained herein is Amlogic confidential. ++ * ++ * This software is provided to you pursuant to Software License Agreement ++ * (SLA) with Amlogic Inc ("Amlogic"). This software may be used ++ * only in accordance with the terms of this agreement. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification is strictly prohibited without prior written permission from ++ * Amlogic. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Created by haixiang.bao@amlogic.com ++ * ++ * Revision history: 1. 2018.05.31 v0.1 init for transfer data from BL2 to BL3X ++ * ++ */ ++ ++ ++#ifndef __AMLOGIC_TLV_H_ ++#define __AMLOGIC_TLV_H_ ++ ++typedef struct __s_bl2_tlv_item_t{ ++ unsigned int nType; //type: user defined, should sync between BL2 and BL3X ++ unsigned int nLength; //length: length of szContent, no alignment ++ unsigned int nStoreLength; //length: length of szContent, alignment to 16 ++ unsigned char szRserved1[4];//reserved for future ++ struct __s_bl2_tlv_item_t * pNextItem;//next item, list for fetch all quickly ++ unsigned char szContent[4]; //data transfered from BL2 ++}s_bl2_tlv_item_t; ++ ++typedef struct __s_bl2_to_bl3x_hdr_t{ ++ unsigned int nMagic; //magic for identify itself, AML_BL2_TMASTER_MAGIC (@BL2) ++ unsigned int nVersion; //version for control ++ unsigned int nHeadSize; //sizeof(this) ++ unsigned char szRserved1[4]; //reserved for furture ++ ++ unsigned char szBL2Info[96]; //BL2 build information ++ ++ s_bl2_tlv_item_t * pNextBlob; //next active valid blob item ++ unsigned int nTLVCount; //current valid TLV item number ++ unsigned int nTotalSize; //total size of all TLV items ++ unsigned char szSHA2TLV[32]; //SHA2 of all TLV items, size is nTotalSize ++ ++} s_bl2_to_bl3x_hdr_t; ++ ++typedef struct __s_bl2_to_bl3x_send_t{ ++ ++ s_bl2_to_bl3x_hdr_t hdr; ++ ++ unsigned char szSHA2Head[32]; ++ ++ s_bl2_tlv_item_t blob[1]; ++ ++} s_bl2_to_bl3x_send_t; ++ ++typedef enum{ ++ e_ok_ret = 0, ++ ++ e_err_not_support = 0x01, ++ ++ e_err_no_item = 0x10, ++ e_err_sha_hdr = 0x11, ++ e_err_sha_tlv = 0x12, ++ ++ e_err_in_data = 0x20, ++ e_err_in_size = 0x21, ++ e_err_over_size=0x22, ++ e_err_item_exit=0x23, ++ ++}e_ret_type; ++ ++typedef enum{ ++ e_t_ap_ver = 0x10, ++ e_t_scp_ver = 0x11, ++ e_t_sp_ver = 0x12, ++ e_t_bl2z_ver = 0x13, ++ e_t_bl30_ver = 0x14, ++ e_t_bl301_ver = 0x15, ++ e_t_bl31_ver = 0x16, ++ e_t_bl32_ver = 0x17, ++ e_t_bl33_ver = 0x18, ++ ++ e_t_root_aes = 0x20, ++ e_t_root_rsa_sha_all = 0x21, ++ e_t_root_rsa_sha = 0x22, ++ e_t_root_rsa_puk = 0x23, ++ ++ e_t_user_aes = 0x30, ++ e_t_user_rsa_sha_all = 0x31, ++ e_t_user_rsa_sha = 0x32, ++ e_t_user_rsa_puk = 0x33, ++ ++ e_t_bl30_rsa_puk = 0x50, ++ e_t_bl30_aes = 0x51, ++ ++ e_t_bl31_rsa_puk = 0x60, ++ e_t_bl31_aes = 0x61, ++ ++ e_t_bl32_rsa_puk = 0x70, ++ e_t_bl32_aes = 0x71, ++ ++ e_t_bl33_rsa_puk = 0x80, ++ e_t_bl33_aes = 0x81, ++ ++ ++ //.... ++ ++}e_item_type; ++ ++ ++//magic ID ++#define AML_BL2_TMASTER_MAGIC (0x324c4240) //@BL2 ++ ++//major & minor version ++#define AML_BL2_TMASTER_MAJ_VER (0x00) //major version ++#define AML_BL2_TMASTER_MIN_VER (0x01) //minor version ++#define AML_BL2_TMASTER_VERSION ((AML_BL2_TMASTER_MAJ_VER << 16) |\ ++ AML_BL2_TMASTER_MIN_VER) //major << 16 | minor version ++ ++//item data length alignment ++#define AML_BL2_TMASTER_ITEM_UNIT_LEN (16) ++#define AML_BL2_TMASTER_ITEM_ALIGN_LEN(len) ((len) + (AML_BL2_TMASTER_ITEM_UNIT_LEN-1)) & (~(AML_BL2_TMASTER_ITEM_UNIT_LEN-1)) ++ ++//CFG reg to store DDR address ++#define AML_BL2_TMASTER_CFG_REG (AO_SEC_GP_CFG6) ++ ++//DDR buffer size ++#ifndef AML_BL2_TMASTER_DDR_MLEN ++#define AML_BL2_TMASTER_DDR_MLEN ((1<<20) - sizeof(s_bl2_to_bl3x_send_t)) //1MB for transfer data from BL2 to BL3X ++#endif ++ ++//flag to pass BL2 build info to BL3X ++//#define CONFIG_AML_TLV_BL2_VER_INFO ++ ++//IMPORTANT: BECAUSE THOSE FUNCTIONS WILL USE DDR AS STORAGE(DEFAULT) THEN ++// ALL THE APIS MSUT BE USED AFTER DDR INIT DONE ++//global APIs to pad & fetch item ++//pad item with data, type and length ++e_ret_type aml_append_item(unsigned int nType, unsigned int nLength, unsigned char *pData); ++//fetch item with type ++e_ret_type aml_fetch_item(unsigned int nType, s_bl2_tlv_item_t **ppItem); ++ ++#endif /* __AMLOGIC_TLV_H_ */ +diff --git a/include/amlogic/aml_v2_burning.h b/include/amlogic/aml_v2_burning.h +new file mode 100644 +index 00000000000..1ecdad65b01 +--- /dev/null ++++ b/include/amlogic/aml_v2_burning.h +@@ -0,0 +1,31 @@ ++/* ++ * \file aml_v2_burning.h ++ * \brief common interfaces for version burning ++ * ++ * \version 1.0.0 ++ * \date 09/15/2013 ++ * \author Sam.Wu ++ * ++ * Copyright (c) 2013 Amlogic. All Rights Reserved. ++ * ++ */ ++ ++//is the uboot loaded from usb otg ++int is_tpl_loaded_from_usb(void); ++ ++//is the uboot loaded from sdcard mmc 0 ++//note only sdmmc supported by romcode when external device boot ++int is_tpl_loaded_from_ext_sdmmc(void); ++ ++//Check if uboot loaded from external sdmmc or usb otg ++int aml_burn_check_uboot_loaded_for_burn(int flag); ++ ++int aml_burn_factory_producing(int flag, bd_t* bis); ++ ++//usb producing mode, if tpl loaded from usb pc tool and auto enter producing mode ++int aml_try_factory_usb_burning(int flag, bd_t* bis); ++ ++//Auto enter sdcard burning if booted from sdcard and aml_sdc_burn.ini existed ++int aml_try_factory_sdcard_burning(int flag, bd_t* bis); ++ ++ +diff --git a/include/amlogic/aml_v3_burning.h b/include/amlogic/aml_v3_burning.h +new file mode 100644 +index 00000000000..545ef33b1cc +--- /dev/null ++++ b/include/amlogic/aml_v3_burning.h +@@ -0,0 +1,14 @@ ++/* ++ * \file aml_v3_burning.h ++ * \brief v3 burning entry ++ * ++ * \version 1.0.0 ++ * \date 2018/12/20 ++ * \author Sam.Wu ++ * ++ * Copyright (c) 2018 Amlogic. All Rights Reserved. ++ * ++ */ ++ ++int aml_v3_factory_usb_burning(int flag, bd_t* bis); ++ +diff --git a/include/amlogic/amlkey_if.h b/include/amlogic/amlkey_if.h +new file mode 100644 +index 00000000000..d15bbe7eee3 +--- /dev/null ++++ b/include/amlogic/amlkey_if.h +@@ -0,0 +1,85 @@ ++/* ++ * \file amlkey_if.h ++ * \brief APIs of secure key for users ++ * ++ * \version 1.0.0 ++ * \date 15/07/10 ++ * \author Sam.Wu ++ * ++ * Copyright (c) 2015 Amlogic. All Rights Reserved. ++ * ++ */ ++#ifndef __AMLKEY_IF_H__ ++#define __AMLKEY_IF_H__ ++ ++#define AMLKEY_NAME_LEN_MAX (80) ++ ++struct amlkey_if { ++ int32_t (*init)(uint8_t *seed, uint32_t len, int encrypt_type); ++ int32_t (*exsit)(const uint8_t *name); ++ ssize_t (*size)(const uint8_t *name); ++ uint32_t (*get_attr)(const uint8_t *name); ++ ssize_t (*read)(const uint8_t *name, uint8_t *buffer, uint32_t len); ++ ssize_t (*write)(const uint8_t *name, uint8_t *buffer, uint32_t len, uint32_t attr); ++ int32_t (*hash)(const uint8_t *name, uint8_t *hash); ++}; ++ ++extern struct amlkey_if *amlkey_if; ++ ++static inline uint32_t amlkey_get_attr(const uint8_t *name) ++{ ++ return amlkey_if->get_attr(name); ++} ++ ++int amlkey_if_init(const void* dt_addr); ++ ++//1.init ++static inline int32_t amlkey_init(uint8_t *seed, uint32_t len, int encrypt_type) ++{ ++ return amlkey_if->init(seed, len, encrypt_type); ++} ++ ++//2. query if the key already programmed, exsit 1, non 0 ++static inline int32_t amlkey_isexsit(const uint8_t * name) ++{ ++ return amlkey_if->exsit(name); ++} ++ ++//3. query attr, key must exsit before those functions were called. ++ //3.1 whether the prgrammed key is secure, secure 1, non 0 ++int32_t amlkey_issecure(const uint8_t * name); ++ ++ //3.2 whether the prgrammed key is encrypt, encrypt 1, non 0 ++int32_t amlkey_isencrypt(const uint8_t * name); ++ ++//4. actual bytes of key value ++static inline ssize_t amlkey_size(const uint8_t *name) ++{ ++ return amlkey_if->size(name); ++} ++ ++//5. read non-secure key in bytes, return byets readback actully. ++static inline ssize_t amlkey_read(const uint8_t *name, uint8_t *buffer, uint32_t len) ++{ ++ return amlkey_if->read(name, buffer, len); ++} ++ ++//6.write key with attribute in bytes , return byets readback actully ++ //attr: bit0: secure/non-secure; ++ // bit8: encrypt/non-encrypt ++#define UNIFYKEY_ATTR_SECURE_MASK (1<<0) ++#define UNIFYKEY_ATTR_ENCRYPT_MASK (1<<8) ++static inline ssize_t amlkey_write(const uint8_t *name, uint8_t *buffer, uint32_t len, ++ uint32_t attr) ++{ ++ return amlkey_if->write(name, buffer, len, attr); ++} ++ ++//7. get the hash value of programmed secure key | 32bytes length, sha256 ++static inline int32_t amlkey_hash_4_secure(const uint8_t *name, uint8_t *hash) ++{ ++ return amlkey_if->hash(name, hash); ++} ++ ++#endif// #ifndef __AMLKEY_IF_H__ ++ +diff --git a/include/amlogic/anti-rollback.h b/include/amlogic/anti-rollback.h +new file mode 100644 +index 00000000000..95d42651eab +--- /dev/null ++++ b/include/amlogic/anti-rollback.h +@@ -0,0 +1,40 @@ ++/* ++ * Copyright (C) 2014-2017 Amlogic, Inc. All rights reserved. ++ * ++ * All information contained herein is Amlogic confidential. ++ * ++ * This software is provided to you pursuant to Software License Agreement ++ * (SLA) with Amlogic Inc ("Amlogic"). This software may be used ++ * only in accordance with the terms of this agreement. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification is strictly prohibited without prior written permission from ++ * Amlogic. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef __ANTI_ROLLBACK_ ++#define __ANTI_ROLLBACK_ ++ ++#include ++ ++bool check_antirollback(uint32_t kernel_version); ++ ++bool set_avb_antirollback(uint32_t index, uint32_t version); ++bool get_avb_antirollback(uint32_t index, uint32_t* version); ++bool get_avb_lock_state(uint32_t* lock_state); ++bool avb_lock(void); ++bool avb_unlock(void); ++ ++#endif +diff --git a/include/amlogic/asm/bl31_apis.h b/include/amlogic/asm/bl31_apis.h +new file mode 100644 +index 00000000000..4227494b93e +--- /dev/null ++++ b/include/amlogic/asm/bl31_apis.h +@@ -0,0 +1,166 @@ ++ ++/* ++ * arch/arm/include/asm/arch-txl/bl31_apis.h ++ * ++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++*/ ++ ++/* ++ * Trustzone API ++ * ++ * Copyright (C) 2012 Amlogic, Inc. ++ * ++ * Author: Platform-SH@amlogic.com ++ * ++ */ ++ ++#ifndef __GXBB_BL31_APIS_H ++#define __GXBB_BL31_APIS_H ++ ++#include ++ ++/*#define SRAM_READ 0x82000010 ++#define CORE_RD_REV1 0x82000011 ++#define SRAM_ACS_READ 0x82000012 ++#define SRAM_ACS_INDIRECT_READ 0x82000013*/ ++ ++#define GET_SHARE_MEM_INPUT_BASE 0x82000020 ++#define GET_SHARE_MEM_OUTPUT_BASE 0x82000021 ++#define GET_REBOOT_REASON 0x82000022 ++#define GET_SHARE_STORAGE_IN_BASE 0x82000023 ++#define GET_SHARE_STORAGE_OUT_BASE 0x82000024 ++#define GET_SHARE_STORAGE_BLOCK_BASE 0x82000025 ++#define GET_SHARE_STORAGE_MESSAGE_BASE 0x82000026 ++#define GET_SHARE_STORAGE_BLOCK_SIZE 0x82000027 ++#define SET_STORAGE_INFO 0x82000028 ++#define SET_REBOOT_REASON 0x82000049 ++ ++/* Set Reboot Reason then Reboot*/ ++#define PSCI_SYS_REBOOT 0x84000009 ++ ++/* SECUREOS DEFINITION*/ ++/* SMC Identifiers for non-secure world functions */ ++#define CALL_TRUSTZONE_HAL_API 0x5 ++ ++/* EFUSE */ ++#define EFUSE_READ 0x82000030 ++#define EFUSE_WRITE 0x82000031 ++#define EFUSE_WRITE_PATTERN 0x82000032 ++#define EFUSE_USER_MAX 0x82000033 ++ ++#define DEBUG_EFUSE_WRITE_PATTERN 0x820000F0 ++#define DEBUG_EFUSE_READ_PATTERN 0x820000F1 ++ ++/* JTAG*/ ++#define JTAG_ON 0x82000040 ++#define JTAG_OFF 0x82000041 ++ ++#define SET_USB_BOOT_FUNC 0x82000043 ++ /* USB BOOT FUNC sub command list*/ ++ #define CLEAR_USB_BOOT 1 ++ #define FORCE_USB_BOOT 2 ++ #define RUN_COMD_USB_BOOT 3 ++ #define PANIC_DUMP_USB_BOOT 4 ++ ++#define GET_CHIP_ID 0x82000044 ++/* Security Key*/ ++#define SECURITY_KEY_QUERY 0x82000060 ++#define SECURITY_KEY_READ 0x82000061 ++#define SECURITY_KEY_WRITE 0x82000062 ++#define SECURITY_KEY_TELL 0x82000063 ++#define SECURITY_KEY_VERIFY 0x82000064 ++#define SECURITY_KEY_STATUS 0x82000065 ++#define SECURITY_KEY_NOTIFY 0x82000066 ++#define SECURITY_KEY_LIST 0x82000067 ++#define SECURITY_KEY_REMOVE 0x82000068 ++#define SECURITY_KEY_NOTIFY_EX 0x82000069 ++#define SECURITY_KEY_SET_ENCTYPE 0x8200006A ++#define SECURITY_KEY_GET_ENCTYPE 0x8200006B ++#define SECURITY_KEY_VERSION 0x8200006C ++ ++/*viu probe en*/ ++#define VIU_PREOBE_EN 0x82000080 ++ ++/* KEYMASTER */ ++#define SET_BOOT_PARAMS 0x82000072 ++#define SHA256_DIGEST_SIZE 32 ++typedef struct { ++ uint32_t device_locked; ++ uint32_t verified_boot_state; ++ uint8_t verified_boot_key[SHA256_DIGEST_SIZE]; ++ uint8_t verified_boot_hash[SHA256_DIGEST_SIZE]; ++} keymaster_boot_params; ++ ++/* Secure HAL APIs */ ++#define TRUSTZONE_HAL_API_SRAM 0x400 ++ ++ ++#define SRAM_HAL_API_CHECK_EFUSE 0x403 ++struct sram_hal_api_arg { ++ unsigned int cmd; ++ unsigned int req_len; ++ unsigned int res_len; ++ unsigned long req_phy_addr; ++ unsigned long res_phy_addr; ++ unsigned long ret_phy_addr; ++}; ++ ++#define JTAG_STATE_ON 0 ++#define JTAG_STATE_OFF 1 ++#define JTAG_M3_AO 0 ++#define JTAG_M3_EE 1 ++#define JTAG_A53_AO 2 ++#define JTAG_A53_EE 3 ++#define CLUSTER_BIT 2 ++ ++#define GET_AVBKEY_FROM_FIP 0x820000b0 ++ ++///////////////////////////////////////////////////////////////////////////////// ++#define AML_DATA_PROCESS (0x820000FF) ++ #define AML_D_P_W_EFUSE_SECURE_BOOT (0x10) ++ #define AML_D_P_W_EFUSE_PASSWORD (0x11) ++ #define AML_D_P_W_EFUSE_CUSTOMER_ID (0x12) ++ #define AML_D_P_W_EFUSE_AMLOGIC (0x20) ++ #define AML_D_P_IMG_DECRYPT (0x40) ++ #define AML_D_P_UPGRADE_CHECK (0x80) ++ #define AML_D_Q_IMG_SIG_HDR_SIZE (0x100) ++ ++#define GXB_EFUSE_PATTERN_SIZE (0x500) ++#define GXB_IMG_SIZE (24<<20) ++#define GXB_IMG_LOAD_ADDR (0x1080000) ++ #define GXB_IMG_DEC_KNL (1<<0) ++ #define GXB_IMG_DEC_RMD (1<<1) ++ #define GXB_IMG_DEC_DTB (1<<2) ++ #define GXB_IMG_DEC_ALL (GXB_IMG_DEC_KNL|GXB_IMG_DEC_RMD|GXB_IMG_DEC_DTB) ++ ++#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" ++ ++void aml_set_jtag_state(unsigned state, unsigned select); ++unsigned aml_get_reboot_reason(void); ++unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2); ++void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2); ++unsigned long aml_sec_boot_check(unsigned long ,unsigned long ,unsigned long,unsigned long ); ++long get_sharemem_info(unsigned long); ++void set_usb_boot_function(unsigned long command); ++void aml_system_off(void); ++ ++void bl31_get_chipid(unsigned int *, unsigned int *, ++ unsigned int *, unsigned int *); ++void set_viu_probe_enable(void); ++int32_t set_boot_params(const keymaster_boot_params*); ++int32_t get_avbkey_from_fip(uint8_t *buf, uint32_t buflen); ++#endif +diff --git a/include/amlogic/asm/clock.h b/include/amlogic/asm/clock.h +new file mode 100644 +index 00000000000..3a24778206e +--- /dev/null ++++ b/include/amlogic/asm/clock.h +@@ -0,0 +1,41 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2018 - AmLogic, Inc. ++ */ ++#ifndef _ARCH_MESON_G12A_CLOCK_H_ ++#define _ARCH_MESON_G12A_CLOCK_H_ ++ ++/* ++ * Clock controller register offsets ++ * ++ * Register offsets from the data sheet are listed in comment blocks below. ++ * Those offsets must be multiplied by 4 before adding them to the base address ++ * to get the right value ++ */ ++ ++#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet1 */ ++#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet1 */ ++#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet1 */ ++#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet1 */ ++#define HHI_FIX_PLL_CNTL0 0x2A0 /* 0xa8 offset in data sheet1 */ ++#define HHI_FIX_PLL_CNTL1 0x2A4 /* 0xa9 offset in data sheet1 */ ++#define HHI_SYS_PLL_CNTL0 0x2f4 /* 0xbd offset in data sheet1 */ ++#define HHI_SYS_PLL_CNTL1 0x2f8 /* 0xbe offset in data sheet1 */ ++#define HHI_SYS_PLL_CNTL2 0x2fc /* 0xbf offset in data sheet1 */ ++#define HHI_SYS_PLL_CNTL3 0x300 /* 0xc0 offset in data sheet1 */ ++#define HHI_SYS_PLL_CNTL4 0x304 /* 0xc1 offset in data sheet1 */ ++#define HHI_SYS_PLL_CNTL5 0x308 /* 0xc2 offset in data sheet1 */ ++#define HHI_SYS_PLL_CNTL6 0x30c /* 0xc3 offset in data sheet1 */ ++#define HHI_SPICC_CLK_CNTL 0x3dc /* 0xf7 offset in data sheet1 */ ++#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet1 */ ++#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet1 */ ++ ++#define CLKID_UNREALIZED 0xfff ++ ++/* AO registers */ ++#define AO_SAR_CLK 0x90 ++#define AO_CLK_GATE0 0x4c ++ ++ulong meson_measure_clk_rate(unsigned int clk); ++ ++#endif +diff --git a/include/amlogic/asm/cpu_config.h b/include/amlogic/asm/cpu_config.h +new file mode 100644 +index 00000000000..7e7c758f867 +--- /dev/null ++++ b/include/amlogic/asm/cpu_config.h +@@ -0,0 +1,101 @@ ++ ++/* ++ * arch/arm/include/asm/arch-txl/cpu_config.h ++ * ++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++*/ ++ ++#ifndef _BOOT_ROM_CONFIG_H_ ++#define _BOOT_ROM_CONFIG_H_ ++ ++/*********************************************************** ++ * The following constants are GXBB definition ++ **********************************************************/ ++#define ROMBOOT_START 0xD9040000 ++#define ROM_SIZE (64*1024) ++#define ROMBOOT_END (ROMBOOT_START+ROM_SIZE) ++ ++/*********************************************************** ++ * AHB-SRAM Total Size 80KB, layout shown as below ++ * ++ * ROMCODE use the top 32KB ++ * ++ * [ 128] 0xD901_3F80 - 0xD901_3FFF Reserved ++ * [ 128] 0xD901_3F00 - 0xD901_3F7F CPUs Boot Entry ++ * [ 256] 0xD901_3E00 - 0xD901_3EFF Debug Info ++ * [ 512] 0xD901_3C00 - 0xD901_3DFF eFuse mirror ++ * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3) ++ * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) * ++ * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) * ++ * [ 26K] 0xD900_C800 - 0xD901_2FFF BL1 Stack, BSS ++ * [ 1K] 0xD900_C400 - 0xD900_C7FF NAND, USB Buffer ++ * [ 1K] 0xD900_C000 - 0xD900_C3FF Reserved ++ * ++ **********************************************************/ ++#define RAM_START 0xD9000000 ++#define RAM_SIZE (80 * 1024) ++#define BL1_RAM_START (RAM_START + 0xC000) ++#define BL1_RAM_SIZE (32 * 1024) ++#define BL1_RAM_END (BL1_RAM_START + BL1_RAM_SIZE) ++#define BSS_START (BL1_RAM_START + (2 * 1024)) ++#define BSS_SIZE (18 * 1024) ++#define _STACK_END (BSS_START + BSS_SIZE + 8*1024) ++#define BL1_EFUSE_MIRROR (BL1_RAM_END - 1024) ++#define P_SHARED_EFUSE_MIRROR (volatile uint32_t *)(BL1_EFUSE_MIRROR) ++#define BL1_DEBUG_BUFFER (BL1_RAM_END - 512) ++#define CPU_BOOT_ENTRY (BL1_DEBUG_BUFFER + 256) ++#define P_SHARED_DEBUG_BUFF (volatile uint32_t *)(BL1_DEBUG_BUFFER) ++#define BL1_SEC_MBX (BL1_RAM_END - 2*1024) ++#define BL1_NAND_BUFF (BL1_RAM_START + 1024) ++#define BL1_USB_BUFF (BL1_NAND_BUFF) ++ ++#define MEMORY_LOC RAM_START ++ ++#define SRAM_DEBUG_BUFF_SIZE 256 ++ ++/* BL2 SPL size */ ++#define BL2_SIZE (64 * 1024) ++ ++//for signature test ++//#define CONFIG_AML_SIG_TEST_BUILD ++ ++/* Software SHA2 */ ++#define CONFIG_SHA2_SW ++ ++/* Hardware SHA2 */ ++#define CONFIG_SHA2_HW ++#define SHA2_HW_UPDATE_API ++ ++/* Keep timer config in conf.h */ ++#define CONFIG_TIMER ++ ++/* Bootrom debug info */ ++#define CONFIG_DEBUG_INFO ++ ++/* Mincrypt RSA library */ ++//#define CONFIG_MINCRYPT ++ ++/* PolarSSL RSA library */ ++#define CONFIG_POLARSSL_RSA ++ ++#ifdef CONFIG_POLARSSL_RSA ++#ifndef CONFIG_MALLOC ++#define CONFIG_MALLOC ++#endif /* ! CONFIG_MALLOC */ ++#endif /* CONFIG_POLARSSL_RSA */ ++ ++#endif /* _BOOT_ROM_CONFIG_H_ */ +diff --git a/include/amlogic/asm/cpu_sdio.h b/include/amlogic/asm/cpu_sdio.h +new file mode 100644 +index 00000000000..baf87065849 +--- /dev/null ++++ b/include/amlogic/asm/cpu_sdio.h +@@ -0,0 +1,264 @@ ++ ++/* ++ * arch/arm/include/asm/arch-txl/cpu_sdio.h ++ * ++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++*/ ++ ++#ifndef __CPU_SDIO_H__ ++#define __CPU_SDIO_H__ ++ ++#define SD_EMMC_BASE_A 0xFFE03000 ++#define SD_EMMC_BASE_B 0xFFE05000 ++#define SD_EMMC_BASE_C 0xFFE07000 ++ ++#define SDIO_PORT_A 0 ++#define SDIO_PORT_B 1 ++#define SDIO_PORT_C 2 ++ ++#if 0 ++#define SD_EMMC_RXD_ERROR 1 ++#define SD_EMMC_TXD_ERROR 1<<1 ++#define SD_EMMC_DESC_ERROR 1<<2 ++#define SD_EMMC_RESP_CRC_ERROR 1<<3 ++#define SD_EMMC_RESP_TIMEOUT_ERROR 1<<4 ++#define SD_EMMC_DESC_TIMEOUT_ERROR 1<<5 ++#endif ++ ++struct sd_emmc_global_regs { ++ volatile uint32_t gclock; // 0x00 ++ volatile uint32_t gdelay; // 0x04 ++ volatile uint32_t gdelay1; //0x08 ++ volatile uint32_t gadjust; // 0x0c ++ volatile uint32_t gcalout; // 0x10 ++ volatile uint32_t reserved_14[11]; // 0x14~0x3c ++ volatile uint32_t gstart; // 0x40 ++ volatile uint32_t gcfg; // 0x44 ++ volatile uint32_t gstatus; // 0x48 ++ volatile uint32_t girq_en; // 0x4c ++ volatile uint32_t gcmd_cfg; // 0x50 ++ volatile uint32_t gcmd_arg; // 0x54 ++ volatile uint32_t gcmd_dat; // 0x58 ++ volatile uint32_t gcmd_rsp0; // 0x5c ++ volatile uint32_t gcmd_rsp1; // 0x60 ++ volatile uint32_t gcmd_rsp2; // 0x64 ++ volatile uint32_t gcmd_rsp3; // 0x68 ++ volatile uint32_t reserved_6c; // 0x6c ++ volatile uint32_t gcurr_cfg; // 0x70 ++ volatile uint32_t gcurr_arg; // 0x74 ++ volatile uint32_t gcurr_dat; // 0x78 ++ volatile uint32_t gcurr_rsp; // 0x7c ++ volatile uint32_t gnext_cfg; // 0x80 ++ volatile uint32_t gnext_arg; // 0x84 ++ volatile uint32_t gnext_dat; // 0x88 ++ volatile uint32_t gnext_rsp; // 0x8c ++ volatile uint32_t grxd; // 0x90 ++ volatile uint32_t gtxd; // 0x94 ++ volatile uint32_t reserved_98[90]; // 0x98~0x1fc ++ volatile uint32_t gdesc[128]; // 0x200 ++ volatile uint32_t gping[128]; // 0x400 ++ volatile uint32_t gpong[128]; // 0x800 ++}; ++ ++union sd_emmc_setup { ++ uint32_t d32; ++ struct { ++ unsigned bw:3; ++ unsigned fast:1; ++ unsigned par:3; ++ unsigned hcs:1; ++ unsigned sd:1; ++ unsigned sdhc:1; ++ unsigned type:6; ++ unsigned rca:16; ++ } b; ++}; ++ ++struct sd_emmc_desc_info{ ++ uint32_t cmd_info; ++ uint32_t cmd_arg; ++ uint32_t data_addr; ++ uint32_t resp_addr; ++}; ++ ++struct cmd_cfg{ ++ uint32_t length:9; ++ uint32_t block_mode:1; ++ uint32_t r1b:1; ++ uint32_t end_of_chain:1; ++ uint32_t timeout:4; ++ uint32_t no_resp:1; ++ uint32_t no_cmd:1; ++ uint32_t data_io:1; ++ uint32_t data_wr:1; ++ uint32_t resp_nocrc:1; ++ uint32_t resp_128:1; ++ uint32_t resp_num:1; ++ uint32_t data_num:1; ++ uint32_t cmd_index:6; ++ uint32_t error:1; ++ uint32_t owner:1; ++}; ++ ++struct sd_emmc_status{ ++ uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire, for multiple block read, the CRC errors are ORed together.*/ ++ uint32_t txd_err:1; /*[8] TX data CRC error, for multiple block write, any one of blocks CRC error. */ ++ uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. The owner bit is ¡°0¡±, set cfg_ignore_owner to ignore this error.*/ ++ uint32_t resp_err:1; /*[10] Response CRC error.*/ ++ uint32_t resp_timeout:1; /*[11] No response received before time limit. The timeout limit is set by cfg_resp_timeout.*/ ++ uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. The timeout limit is set by descriptor itself.*/ ++ /* Consider the multiple block read/write, set the proper timeout limits.*/ ++ uint32_t end_of_chain:1; /*[13] End of Chain IRQ, Normal IRQ. */ ++ uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ, Normal IRQ, the descriptor chain execution keeps going on.*/ ++ uint32_t irq_sdio:1; /*[15] SDIO device uses DAT[1] to request IRQ. */ ++ uint32_t dat_i:8; /*[23:16] Input data signals. */ ++ uint32_t cmd_i:1; /*[24] nput response signal. */ ++ uint32_t ds:1; /*[25] Input data strobe. */ ++ uint32_t bus_fsm:4; /*[29:26] BUS fsm */ ++ uint32_t desc_wr_rdy:1; /*[30] Descriptor write back process is done and it is ready for CPU to read.*/ ++ uint32_t core_rdy:1; /*[31] desc_busy or sd_emmc_irq or bus_fsm is not idle.*/ ++};//__attribute__((__may_alias__)); ++ ++ ++struct sd_emmc_clock{ ++ uint32_t div:6; /*[5:0] Clock divider. Frequency = clock source/cfg_div, Maximum divider 63. */ ++ /*Clock off: cfg_div==0, the clock is disabled */ ++ /*Divider bypass: cfg_div==1, clock source is used as core clock without divider. */ ++ uint32_t src:2; /*[7:6] Clock source, 0: Crystal 24MHz, 1: Fix PLL, 850MHz*/ ++ /* 2: MPLL, <637MHz, used for 400MHz exactly. 3: different PLL */ ++ uint32_t core_phase:2; /*[9:8] Core clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/ ++ uint32_t tx_phase:2; /*[11:10] TX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/ ++ uint32_t rx_phase:2; /*[13:12] RX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/ ++ uint32_t reserved14:2; ++ uint32_t tx_delay:6; /*[21:16] TX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/ ++ uint32_t rx_delay:6; /*[27:22] RX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/ ++ uint32_t always_on:1; /*[28] 1: Keep clock always on. 0: Clock on/off controlled by activities. */ ++ /*Any APB3 access or descriptor execution will keep clock on.*/ ++ uint32_t irq_sdio_sleep:1; /*[29] 1: enable IRQ sdio when in sleep mode. */ ++ uint32_t irq_sdio_sleep_ds:1;/*[30] 1:enable ds as irq*/ ++ uint32_t reserved26:1; ++}; ++ ++struct sd_emmc_delay{ ++ uint32_t dat0:6; /*[3:0] Data 0 delay line. */ ++ uint32_t dat1:6; /*[7:4] Data 1 delay line. */ ++ uint32_t dat2:6; /*[11:8] Data 2 delay line. */ ++ uint32_t dat3:6; /*[15:12] Data 3 delay line. */ ++ uint32_t dat4:6; /*[19:16] Data 4 delay line. */ ++ uint32_t spare:2; ++}; ++ ++struct sd_emmc_delay1{ ++ uint32_t dat5:6; /*[23:20] Data 5 delay line. */ ++ uint32_t dat6:6; /*[27:24] Data 6 delay line. */ ++ uint32_t dat7:6; /*[31:28] Data 7 delay line. */ ++ uint32_t dat8:6; /*[31:28] Data 7 delay line. */ ++ uint32_t dat9:6; /*[31:28] Data 7 delay line. */ ++ uint32_t spare:2; ++}; ++ ++struct sd_emmc_adjust{ ++ uint32_t cmd_delay:4; /*[3:0] Command delay line. */ ++ uint32_t ds_delay:4; /*[7:4] DS delay line. */ ++ uint32_t cali_sel:4; /*[11:8] Select one signal to be tested.*/ ++ /*Signals are labeled from 0 to 9 the same as delay lines. */ ++ uint32_t cali_enable:1; /*[12] Enable calibration. */ ++ uint32_t adj_enable:1; /*[13] Adjust interface timing by resampling the input signals. */ ++ uint32_t cali_rise:1; /*[14] 1: test the rising edge. 0: test the falling edge. */ ++ uint32_t ds_enable:1; /*[15] Sampling the DAT based on DS in HS400 mode*/ ++ uint32_t adj_delay:6; /*[21:16] Resample the input signals when clock index==adj_delay. */ ++ uint32_t adj_auto:1; /*[22] Use cali_dut first falling edge to adjust the timing */ ++ /*set cali_enable to 1 to use this function*/ ++ uint32_t reserved23:9; ++}; ++ ++ ++struct sd_emmc_calout{ ++ uint32_t cali_idx:6; /*[5:0] Calibration reading. The event happens at this index. */ ++ uint32_t reserved6:1; ++ uint32_t cali_vld:1; /*[7] The reading is valid. */ ++ uint32_t cali_setup:8; /*[15:8] Copied from BASE+0x8 [15:8] include cali_sel, cali_enable, adj_enable, cali_rise. */ ++ uint32_t reserved16:16; ++}; ++ ++ ++struct sd_emmc_start{ ++ uint32_t init:1; /*[0] 1: Read descriptor from internal SRAM, limited to 32 descriptors. */ ++ /* 0: Read descriptor from external DDR */ ++ uint32_t busy:1; /*[1] 1: Start command chain execution process. 0: Stop */ ++ uint32_t addr:30; /*[31:2] Descriptor address, the last 2 bits are 0, 4 bytes aligned. */ ++ /* When internal SRAM is used, the valid address range is from 0x200~0x3ff */ ++ /* When external DDR is used, the valid address is anywhere in DDR, the length of chain is unlimited.*/ ++};//__attribute__((__may_alias__)); ++ ++ ++struct sd_emmc_config{ ++ uint32_t bus_width:2; /*[1:0] 0: 1 bit, 1: 4 bits, 2: 8 bits, 3: 2 bits (not supported)*/ ++ uint32_t ddr:1; /*[2] 1: DDR mode, 0: SDR mode */ ++ uint32_t dc_ugt:1; /*[3] 1: DDR access urgent, 0: DDR access normal. */ ++ uint32_t bl_len:4; /*[7:4] Block length 2^cfg_bl_len, because internal buffer size is limited to 512 bytes, the cfg_bl_len <=9. */ ++ uint32_t resp_timeout:4; /*[11:8] Wait response till 2^cfg_resp_timeout core clock cycles. Maximum 32768 core cycles. */ ++ uint32_t rc_cc:4; /*[15:12] Wait response-command, command-command gap before next command, 2^cfg_rc_cc core clock cycles. */ ++ uint32_t out_fall:1; /*[16] DDR mode only. The command and TXD start from rising edge. Set 1 to start from falling edge. */ ++ uint32_t blk_gap_ip:1; /*[17] 1: Enable SDIO data block gap interrupt period. 0: Disabled.*/ ++ uint32_t spare:1; /*[18] Spare, ??? need check*/ ++ uint32_t ignore_owner:1; /*[19] Use this descriptor even if its owner bit is ¡°0¡±.*/ ++ uint32_t chk_ds:1; /*[20] Check data strobe in HS400.*/ ++ uint32_t cmd_low:1; /*[21] Hold CMD as output Low, eMMC boot mode.*/ ++ uint32_t stop_clk:1; /*[22] 1: stop clock. 0: normal clock.*/ ++ /*In normal mode, the clock is automatically on/off during reading mode to back off reading in case of*/ ++ /*DDR slow response, stop clock is used in voltage switch.*/ ++ uint32_t auto_clk:1; /*[23] 1: when BUS is idle and no descriptor is available, turn off clock, to save power.*/ ++ /* 0: core clock is always on.*/ ++ uint32_t txd_add_err:1; /*[24] TXD add error test*/ ++ /*Test feature, should not be used in normal condition.*/ ++ /*It will inverted the first CRC bits of the 3rd block.*/ ++ /*Block index starts from 0, 1, 2, ¡­*/ ++ uint32_t txd_retry:1; /*[25] When TXD CRC error, host sends the block again.*/ ++ /*The total number of retries of one descriptor is limited to 15, */ ++ /*after 15 retries, the TXD_err is set to high.*/ ++ uint32_t revd:8; /*[31:26] reved*/ ++};//__attribute__((__may_alias__)); ++ ++ ++struct sd_emmc_irq_en{ ++ uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire.*/ ++ uint32_t txd_err:1; /*[8] TX data CRC error. */ ++ uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. */ ++ uint32_t resp_err:1; /*[10] Response CRC error.*/ ++ uint32_t resp_timeout:1; /*[11] No response received before time limit. */ ++ uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. */ ++ uint32_t end_of_chain:1; /*[13] End of Chain IRQ. */ ++ uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ. */ ++ uint32_t irq_sdio:1; /*[15] Enable sdio interrupt. */ ++ uint32_t revd:16; /*[31:16] reved*/ ++}; ++ ++struct sd_emmc_data_info{ ++ uint32_t cnt:10; /*[9:0] Rxd words received from BUS. Txd words received from DDR.*/ ++ uint32_t blk:9; /*[24:16] Rxd Blocks received from BUS. Txd blocks received from DDR.*/ ++ uint32_t revd:30; /*[31:17] Reved. */ ++}; ++ ++ ++struct sd_emmc_card_info{ ++ uint32_t txd_cnt:10; /*[9:0] Txd BUS cycle counter. */ ++ uint32_t txd_blk:9; /*[24:16] Txd BUS block counter.*/ ++ uint32_t revd:30; /*[31:17] Reved. */ ++}; ++ ++#endif +diff --git a/include/amlogic/asm/efuse.h b/include/amlogic/asm/efuse.h +new file mode 100644 +index 00000000000..b5ea02723f9 +--- /dev/null ++++ b/include/amlogic/asm/efuse.h +@@ -0,0 +1,62 @@ ++ ++/* ++ * arch/arm/include/asm/arch-txl/efuse.h ++ * ++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++*/ ++ ++#ifndef __EFUSE_H ++#define __EFUSE_H ++ ++#include ++#include ++ ++/* efuse HAL_API arg */ ++struct efuse_hal_api_arg { ++ unsigned int cmd; /* R/W */ ++ unsigned int offset; ++ unsigned int size; ++ unsigned long buffer_phy; ++ unsigned long retcnt_phy; ++}; ++ ++ ++#define EFUSE_BYTES 512 /* (EFUSE_BITS/8) */ ++ ++#define EFUSE_HAL_API_READ 0 ++#define EFUSE_HAL_API_WRITE 1 ++#define EFUSE_HAL_API_WRITE_PATTERN 2 ++#define EFUSE_HAL_API_USER_MAX 3 ++ ++#define EFUSE_USER_MASK (0x1 << 16) ++#define EFUSE_THERMAL_MASK (0x1 << 17) ++#define EFUSE_THERMAL_VERFLAG_MASK (0x1 << 18) ++#define EFUSE_ENCRYPT_MASK (0x1 << 19) ++ ++//#define ASSIST_HW_REV 0x1f53 ++ ++int efuse_read_usr(char *buf, size_t count, loff_t *ppos); ++int efuse_write_usr(char *buf, size_t count, loff_t *ppos); ++uint32_t efuse_get_max(void); ++ssize_t efuse_read(char *buf, size_t count, loff_t *ppos); ++ssize_t efuse_write(const char *buf, size_t count, loff_t *ppos); ++ ++int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg); ++int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg); ++ ++#endif ++ +diff --git a/include/amlogic/asm/io.h b/include/amlogic/asm/io.h +new file mode 100644 +index 00000000000..8640303b518 +--- /dev/null ++++ b/include/amlogic/asm/io.h +@@ -0,0 +1,118 @@ ++ ++/* ++ * arch/arm/include/asm/arch-txl/io.h ++ * ++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++*/ ++ ++#ifndef __MACH_MESSON_REGS_IO_H ++#define __MACH_MESSON_REGS_IO_H ++ ++#ifndef __ASSEMBLY__ ++ ++#include ++#define IO_CBUS_BASE (0xFFD00000L) ++#define IO_AXI_BUS_BASE (0xFFB00000L) /* gpv */ ++#define IO_AHB_BUS_BASE (0xFF500000L) /* usb0 */ ++#define IO_APB_BUS_BASE (0xFFFC0000L) /* AHB SRAM, sec/sys ahb? txlx_mem_map.xlsx */ ++#define IO_APB_HDMI_BUS_BASE (0xFFE00000L) /* */ ++#define IO_VPU_BUS_BASE (0xFF900000L) /* VPU */ ++ ++#define CBUS_REG_OFFSET(reg) ((reg) << 2) ++#define CBUS_REG_ADDR(reg) (IO_CBUS_BASE + CBUS_REG_OFFSET(reg)) ++ ++#define AXI_REG_OFFSET(reg) ((reg) << 2) ++#define AXI_REG_ADDR(reg) (IO_AXI_BUS_BASE + AXI_REG_OFFSET(reg)) ++ ++#define AHB_REG_OFFSET(reg) ((reg) << 2) ++#define AHB_REG_ADDR(reg) (IO_AHB_BUS_BASE + AHB_REG_OFFSET(reg)) ++ ++#define VPU_REG_OFFSET(reg) ((reg) << 2) ++#define VPU_REG_ADDR(reg) (IO_VPU_BUS_BASE + VPU_REG_OFFSET(reg)) ++ ++ ++#define APB_REG_OFFSET(reg) (reg) ++#define APB_REG_ADDR(reg) (IO_APB_BUS_BASE + APB_REG_OFFSET(reg)) ++#define APB_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0) ++ ++#define APB_HDMI_REG_OFFSET(reg) (reg) ++#define APB_HDMI_REG_ADDR(reg) (IO_APB_HDMI_BUS_BASE + APB_HDMI_REG_OFFSET(reg)) ++#define APB_HDMI_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0) ++ ++ ++#define WRITE_CBUS_REG(reg, val) __raw_writel(val, CBUS_REG_ADDR(reg)) ++#define READ_CBUS_REG(reg) (__raw_readl(CBUS_REG_ADDR(reg))) ++#define WRITE_CBUS_REG_BITS(reg, val, start, len) \ ++ WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) ++#define READ_CBUS_REG_BITS(reg, start, len) \ ++ ((READ_CBUS_REG(reg) >> (start)) & ((1L<<(len))-1)) ++#define CLEAR_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)&(~(mask)))) ++#define SET_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)|(mask))) ++ ++#define WRITE_AXI_REG(reg, val) __raw_writel(val, AXI_REG_ADDR(reg)) ++#define READ_AXI_REG(reg) (__raw_readl(AXI_REG_ADDR(reg))) ++#define WRITE_AXI_REG_BITS(reg, val, start, len) \ ++ WRITE_AXI_REG(reg, (READ_AXI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) ++#define READ_AXI_REG_BITS(reg, start, len) \ ++ ((READ_AXI_REG(reg) >> (start)) & ((1L<<(len))-1)) ++#define CLEAR_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)&(~(mask)))) ++#define SET_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)|(mask))) ++ ++#define WRITE_AHB_REG(reg, val) __raw_writel(val, AHB_REG_ADDR(reg)) ++#define READ_AHB_REG(reg) (__raw_readl(AHB_REG_ADDR(reg))) ++#define WRITE_AHB_REG_BITS(reg, val, start, len) \ ++ WRITE_AHB_REG(reg, (READ_AHB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) ++#define READ_AHB_REG_BITS(reg, start, len) \ ++ ((READ_AHB_REG(reg) >> (start)) & ((1L<<(len))-1)) ++#define CLEAR_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)&(~(mask)))) ++#define SET_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)|(mask))) ++ ++#define WRITE_APB_REG(reg, val) __raw_writel(val, APB_REG_ADDR(reg)) ++#define READ_APB_REG(reg) (__raw_readl(APB_REG_ADDR(reg))) ++#define WRITE_APB_REG_BITS(reg, val, start, len) \ ++ WRITE_APB_REG(reg, (READ_APB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) ++#define READ_APB_REG_BITS(reg, start, len) \ ++ ((READ_APB_REG(reg) >> (start)) & ((1L<<(len))-1)) ++#define CLEAR_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)&(~(mask)))) ++#define SET_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)|(mask))) ++ ++#define WRITE_APB_HDMI_REG(reg, val) __raw_writel(val, APB_HDMI_REG_ADDR(reg)) ++#define READ_APB_HDMI_REG(reg) (__raw_readl(APB_HDMI_REG_ADDR(reg))) ++#define WRITE_APB_HDMI_REG_BITS(reg, val, start, len) \ ++ WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) ++#define READ_APB_HDMI_REG_BITS(reg, start, len) \ ++ ((READ_APB_HDMI_REG(reg) >> (start)) & ((1L<<(len))-1)) ++#define CLEAR_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)&(~(mask)))) ++#define SET_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)|(mask))) ++ ++/* for back compatible alias */ ++#define WRITE_MPEG_REG(reg, val) \ ++ WRITE_CBUS_REG(reg, val) ++#define READ_MPEG_REG(reg) \ ++ READ_CBUS_REG(reg) ++#define WRITE_MPEG_REG_BITS(reg, val, start, len) \ ++ WRITE_CBUS_REG_BITS(reg, val, start, len) ++#define READ_MPEG_REG_BITS(reg, start, len) \ ++ READ_CBUS_REG_BITS(reg, start, len) ++#define CLEAR_MPEG_REG_MASK(reg, mask) \ ++ CLEAR_CBUS_REG_MASK(reg, mask) ++#define SET_MPEG_REG_MASK(reg, mask) \ ++ SET_CBUS_REG_MASK(reg, mask) ++#endif ++ ++ ++#endif +diff --git a/include/amlogic/asm/register.h b/include/amlogic/asm/register.h +new file mode 100644 +index 00000000000..aa342a50fd9 +--- /dev/null ++++ b/include/amlogic/asm/register.h +@@ -0,0 +1,98 @@ ++ ++/* ++ * arch/arm/include/asm/arch-txl/register.h ++ * ++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++*/ ++ ++#ifndef __REGISTER_H__ ++#define __REGISTER_H__ ++ ++#define IO_CBUS_BASE 0xFFD00000 ++#define IO_AXI_BUS_BASE 0xFFB00000 ++#define IO_AHB_BUS_BASE 0xFF500000 ++#define IO_APB_BUS_BASE 0xFFFC0000 ++#define IO_APB_HDMI_BUS_BASE 0xFFE00000 ++#define IO_VPU_BUS_BASE 0xFF900000 ++ ++#define CBUS_REG_OFFSET(reg) ((reg) << 2) ++#define CBUS_REG_ADDR(reg) (IO_CBUS_BASE + CBUS_REG_OFFSET(reg)) ++ ++#if 0 ++/* below UART0,UART1,AO_UART is m8 addr,it is placed is for compiling pass */ ++/* ------------------------------- ++// UART0 ++// ---------------------------- */ ++#define UART0_WFIFO 0x2130 ++#define UART0_RFIFO 0x2131 ++#define UART0_CONTROL 0x2132 ++#define UART0_STATUS 0x2133 ++#define UART0_MISC 0x2134 ++#define UART0_REG5 0x2135 ++/* ---------------------------- ++// UART1 ++----------------------------*/ ++#define UART1_WFIFO 0x2137 ++#define UART1_RFIFO 0x2138 ++#define UART1_CONTROL 0x2139 ++#define UART1_STATUS 0x213a ++#define UART1_MISC 0x213b ++#define UART1_REG5 0x213c ++ ++/* ------------------------------------------------------ ++ The following are handled by $periphs/rtl/periphs_reg.v ++ ---------------------------------------- */ ++#define PREG_CTLREG0_ADDR 0x2000 ++#define P_PREG_CTLREG0_ADDR CBUS_REG_ADDR(PREG_CTLREG0_ADDR) ++ ++/* ---------------------------- ++ clock measure (4) ++ ---------------------------- */ ++#define MSR_CLK_DUTY 0x21d6 ++#define MSR_CLK_REG0 0x21d7 ++#define MSR_CLK_REG1 0x21d8 ++#define MSR_CLK_REG2 0x21d9 ++#define P_MSR_CLK_DUTY CBUS_REG_ADDR(MSR_CLK_DUTY) ++#define P_MSR_CLK_REG0 CBUS_REG_ADDR(MSR_CLK_REG0) ++#define P_MSR_CLK_REG1 CBUS_REG_ADDR(MSR_CLK_REG1) ++#define P_MSR_CLK_REG2 CBUS_REG_ADDR(MSR_CLK_REG2) ++#endif ++ ++#if 0 ++/* -------------------------------- ++ * AO uart ++ * -------------------------------*/ ++#define IO_AOBUS_BASE 0xc8100000 ///1M ++ ++#define AOBUS_REG_OFFSET(reg) ((reg) ) ++#define AOBUS_REG_ADDR(reg) (IO_AOBUS_BASE + AOBUS_REG_OFFSET(reg)) ++ ++#define AO_UART_WFIFO ((0x01 << 10) | (0x30 << 2)) ///../ucode/c_always_on_pointer.h:89 ++#define P_AO_UART_WFIFO AOBUS_REG_ADDR(AO_UART_WFIFO) ++#define AO_UART_RFIFO ((0x01 << 10) | (0x31 << 2)) ///../ucode/c_always_on_pointer.h:90 ++#define P_AO_UART_RFIFO AOBUS_REG_ADDR(AO_UART_RFIFO) ++#define AO_UART_CONTROL ((0x01 << 10) | (0x32 << 2)) ///../ucode/c_always_on_pointer.h:91 ++#define P_AO_UART_CONTROL AOBUS_REG_ADDR(AO_UART_CONTROL) ++#define AO_UART_STATUS ((0x01 << 10) | (0x33 << 2)) ///../ucode/c_always_on_pointer.h:92 ++#define P_AO_UART_STATUS AOBUS_REG_ADDR(AO_UART_STATUS) ++#define AO_UART_MISC ((0x01 << 10) | (0x34 << 2)) ///../ucode/c_always_on_pointer.h:93 ++#define P_AO_UART_MISC AOBUS_REG_ADDR(AO_UART_MISC) ++#define AO_UART_REG5 ((0x01 << 10) | (0x35 << 2)) ///../ucode/c_always_on_pointer.h:94 ++#define P_AO_UART_REG5 AOBUS_REG_ADDR(AO_UART_REG5) ++#endif ++ ++#endif //__REGISTER_H__ +diff --git a/include/amlogic/asm/regs.h b/include/amlogic/asm/regs.h +new file mode 100644 +index 00000000000..26df3071ccb +--- /dev/null ++++ b/include/amlogic/asm/regs.h +@@ -0,0 +1,32964 @@ ++// ---------------------------------------------------------------------- ++// regs.h header ++// ++// bus base define, update manually ++// ++// ---------------------------------------------------------------------- ++// ++#ifndef _BASE_REGISTER ++#define _BASE_REGISTER ++#define REG_BASE_AOBUS (0xFF800000L) ++#define REG_BASE_PERIPHS (0xFF634000L) ++#define REG_BASE_CBUS (0xFFD00000L) ++#define REG_BASE_HIU (0xFF63C000L) ++#define REG_BASE_VCBUS (0xFF900000L) ++#define DMC_REG_BASE (0xFF638000L) ++#define REG_BASE_DSI_HOST (0xFFD00000L)/* 0xFFD07000L*/ ++ ++#endif /*_BASE_REGISTER*/ ++ ++#ifndef REG_OTHERS ++#define REG_OTHERS ++/* other regs */ ++#define SPI_START_ADDR 0xFB000000 ++#define P_SPI_START_ADDR (volatile unsigned int *)0xFB000000 ++ ++#endif /*REG_OTHERS*/ ++ ++// ---------------------------------------------------------------------- ++// This file is automatically generated from the script: ++// ++// ./create_headers_from_register_map_h.pl ++// ++// and was applied to the file ++// ++// ./register_map.h ++// ++// DO NOT EDIT!!!!! ++// ---------------------------------------------------------------------- ++// ++#ifdef REGISTER_H ++#else ++#define REGISTER_H ++#endif ++ ++// ---------------------------------------------------------------------- ++// This file is automatically generated from the script: ++// ++// ./create_headers_from_dos_params_h.pl ++// ++// and was applied to the file ++// ++// ./dos_param.h ++// ++// DO NOT EDIT!!!!! ++// ---------------------------------------------------------------------- ++// ++#ifdef DOS_REGISTER_H ++#else ++#define DOS_REGISTER_H ++ ++ ++// ++// Reading file: ./dos_param.h ++// ++//------------------------------------------------------------------------------ ++// Define all modules' base address under DOS ++// APB allocation from 32'hd0050000 ++//------------------------------------------------------------------------------ ++// Define base address for VDEC module under DOS: ++// DOS_VDEC_ASSIST_BASE_ADDR 14'h0000 ++// DOS_VDEC_MDEC_BASE_ADDR 14'h0900 ++// DOS_VDEC_VLD_BASE_ADDR 14'h0c00 ++// DOS_VDEC_IQIDCT_BASE_ADDR 14'h0e00 ++// DOS_VDEC_VCPU_BASE_ADDR 14'h0300 ++// DOS_VDEC_RESERVED_BASE_ADDR 14'h0f00 // Do not use this offset ++// Define base address for DOS top-level register module: ++// DOS_TOP_BASE_ADDR 14'h3f00 ++//------------------------------------------------------------------------------ ++// VDEC_ASSIST module level register offset ++//------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: DOS_VDEC_ASSIST_CBUS_BASE = 0x00 ++// ----------------------------------------------- ++#define VDEC_ASSIST_MMC_CTRL0 (0x0001) ++#define P_VDEC_ASSIST_MMC_CTRL0 (volatile unsigned int *)((0x0001 << 2) + 0xff620000) ++#define VDEC_ASSIST_MMC_CTRL1 (0x0002) ++#define P_VDEC_ASSIST_MMC_CTRL1 (volatile unsigned int *)((0x0002 << 2) + 0xff620000) ++#define VDEC_ASSIST_MMC_CTRL2 (0x0003) ++#define P_VDEC_ASSIST_MMC_CTRL2 (volatile unsigned int *)((0x0003 << 2) + 0xff620000) ++#define VDEC_ASSIST_MMC_CTRL3 (0x0004) ++#define P_VDEC_ASSIST_MMC_CTRL3 (volatile unsigned int *)((0x0004 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR1_INT0 (0x0025) ++#define P_VDEC_ASSIST_AMR1_INT0 (volatile unsigned int *)((0x0025 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR1_INT1 (0x0026) ++#define P_VDEC_ASSIST_AMR1_INT1 (volatile unsigned int *)((0x0026 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR1_INT2 (0x0027) ++#define P_VDEC_ASSIST_AMR1_INT2 (volatile unsigned int *)((0x0027 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR1_INT3 (0x0028) ++#define P_VDEC_ASSIST_AMR1_INT3 (volatile unsigned int *)((0x0028 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR1_INT4 (0x0029) ++#define P_VDEC_ASSIST_AMR1_INT4 (volatile unsigned int *)((0x0029 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR1_INT5 (0x002a) ++#define P_VDEC_ASSIST_AMR1_INT5 (volatile unsigned int *)((0x002a << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR1_INT6 (0x002b) ++#define P_VDEC_ASSIST_AMR1_INT6 (volatile unsigned int *)((0x002b << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR1_INT7 (0x002c) ++#define P_VDEC_ASSIST_AMR1_INT7 (volatile unsigned int *)((0x002c << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR1_INT8 (0x002d) ++#define P_VDEC_ASSIST_AMR1_INT8 (volatile unsigned int *)((0x002d << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR1_INT9 (0x002e) ++#define P_VDEC_ASSIST_AMR1_INT9 (volatile unsigned int *)((0x002e << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR1_INTA (0x002f) ++#define P_VDEC_ASSIST_AMR1_INTA (volatile unsigned int *)((0x002f << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR1_INTB (0x0030) ++#define P_VDEC_ASSIST_AMR1_INTB (volatile unsigned int *)((0x0030 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR1_INTC (0x0031) ++#define P_VDEC_ASSIST_AMR1_INTC (volatile unsigned int *)((0x0031 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR1_INTD (0x0032) ++#define P_VDEC_ASSIST_AMR1_INTD (volatile unsigned int *)((0x0032 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR1_INTE (0x0033) ++#define P_VDEC_ASSIST_AMR1_INTE (volatile unsigned int *)((0x0033 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR1_INTF (0x0034) ++#define P_VDEC_ASSIST_AMR1_INTF (volatile unsigned int *)((0x0034 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR2_INT0 (0x0035) ++#define P_VDEC_ASSIST_AMR2_INT0 (volatile unsigned int *)((0x0035 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR2_INT1 (0x0036) ++#define P_VDEC_ASSIST_AMR2_INT1 (volatile unsigned int *)((0x0036 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR2_INT2 (0x0037) ++#define P_VDEC_ASSIST_AMR2_INT2 (volatile unsigned int *)((0x0037 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR2_INT3 (0x0038) ++#define P_VDEC_ASSIST_AMR2_INT3 (volatile unsigned int *)((0x0038 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR2_INT4 (0x0039) ++#define P_VDEC_ASSIST_AMR2_INT4 (volatile unsigned int *)((0x0039 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR2_INT5 (0x003a) ++#define P_VDEC_ASSIST_AMR2_INT5 (volatile unsigned int *)((0x003a << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR2_INT6 (0x003b) ++#define P_VDEC_ASSIST_AMR2_INT6 (volatile unsigned int *)((0x003b << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR2_INT7 (0x003c) ++#define P_VDEC_ASSIST_AMR2_INT7 (volatile unsigned int *)((0x003c << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR2_INT8 (0x003d) ++#define P_VDEC_ASSIST_AMR2_INT8 (volatile unsigned int *)((0x003d << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR2_INT9 (0x003e) ++#define P_VDEC_ASSIST_AMR2_INT9 (volatile unsigned int *)((0x003e << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR2_INTA (0x003f) ++#define P_VDEC_ASSIST_AMR2_INTA (volatile unsigned int *)((0x003f << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR2_INTB (0x0040) ++#define P_VDEC_ASSIST_AMR2_INTB (volatile unsigned int *)((0x0040 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR2_INTC (0x0041) ++#define P_VDEC_ASSIST_AMR2_INTC (volatile unsigned int *)((0x0041 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR2_INTD (0x0042) ++#define P_VDEC_ASSIST_AMR2_INTD (volatile unsigned int *)((0x0042 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR2_INTE (0x0043) ++#define P_VDEC_ASSIST_AMR2_INTE (volatile unsigned int *)((0x0043 << 2) + 0xff620000) ++#define VDEC_ASSIST_AMR2_INTF (0x0044) ++#define P_VDEC_ASSIST_AMR2_INTF (volatile unsigned int *)((0x0044 << 2) + 0xff620000) ++#define VDEC_ASSIST_MBX_SSEL (0x0045) ++#define P_VDEC_ASSIST_MBX_SSEL (volatile unsigned int *)((0x0045 << 2) + 0xff620000) ++#define VDEC_ASSIST_TIMER0_LO (0x0060) ++#define P_VDEC_ASSIST_TIMER0_LO (volatile unsigned int *)((0x0060 << 2) + 0xff620000) ++#define VDEC_ASSIST_TIMER0_HI (0x0061) ++#define P_VDEC_ASSIST_TIMER0_HI (volatile unsigned int *)((0x0061 << 2) + 0xff620000) ++#define VDEC_ASSIST_TIMER1_LO (0x0062) ++#define P_VDEC_ASSIST_TIMER1_LO (volatile unsigned int *)((0x0062 << 2) + 0xff620000) ++#define VDEC_ASSIST_TIMER1_HI (0x0063) ++#define P_VDEC_ASSIST_TIMER1_HI (volatile unsigned int *)((0x0063 << 2) + 0xff620000) ++#define VDEC_ASSIST_DMA_INT (0x0064) ++#define P_VDEC_ASSIST_DMA_INT (volatile unsigned int *)((0x0064 << 2) + 0xff620000) ++#define VDEC_ASSIST_DMA_INT_MSK (0x0065) ++#define P_VDEC_ASSIST_DMA_INT_MSK (volatile unsigned int *)((0x0065 << 2) + 0xff620000) ++#define VDEC_ASSIST_DMA_INT2 (0x0066) ++#define P_VDEC_ASSIST_DMA_INT2 (volatile unsigned int *)((0x0066 << 2) + 0xff620000) ++#define VDEC_ASSIST_DMA_INT_MSK2 (0x0067) ++#define P_VDEC_ASSIST_DMA_INT_MSK2 (volatile unsigned int *)((0x0067 << 2) + 0xff620000) ++#define VDEC_ASSIST_MBOX0_IRQ_REG (0x0070) ++#define P_VDEC_ASSIST_MBOX0_IRQ_REG (volatile unsigned int *)((0x0070 << 2) + 0xff620000) ++#define VDEC_ASSIST_MBOX0_CLR_REG (0x0071) ++#define P_VDEC_ASSIST_MBOX0_CLR_REG (volatile unsigned int *)((0x0071 << 2) + 0xff620000) ++#define VDEC_ASSIST_MBOX0_MASK (0x0072) ++#define P_VDEC_ASSIST_MBOX0_MASK (volatile unsigned int *)((0x0072 << 2) + 0xff620000) ++#define VDEC_ASSIST_MBOX0_FIQ_SEL (0x0073) ++#define P_VDEC_ASSIST_MBOX0_FIQ_SEL (volatile unsigned int *)((0x0073 << 2) + 0xff620000) ++#define VDEC_ASSIST_MBOX1_IRQ_REG (0x0074) ++#define P_VDEC_ASSIST_MBOX1_IRQ_REG (volatile unsigned int *)((0x0074 << 2) + 0xff620000) ++#define VDEC_ASSIST_MBOX1_CLR_REG (0x0075) ++#define P_VDEC_ASSIST_MBOX1_CLR_REG (volatile unsigned int *)((0x0075 << 2) + 0xff620000) ++#define VDEC_ASSIST_MBOX1_MASK (0x0076) ++#define P_VDEC_ASSIST_MBOX1_MASK (volatile unsigned int *)((0x0076 << 2) + 0xff620000) ++#define VDEC_ASSIST_MBOX1_FIQ_SEL (0x0077) ++#define P_VDEC_ASSIST_MBOX1_FIQ_SEL (volatile unsigned int *)((0x0077 << 2) + 0xff620000) ++#define VDEC_ASSIST_MBOX2_IRQ_REG (0x0078) ++#define P_VDEC_ASSIST_MBOX2_IRQ_REG (volatile unsigned int *)((0x0078 << 2) + 0xff620000) ++#define VDEC_ASSIST_MBOX2_CLR_REG (0x0079) ++#define P_VDEC_ASSIST_MBOX2_CLR_REG (volatile unsigned int *)((0x0079 << 2) + 0xff620000) ++#define VDEC_ASSIST_MBOX2_MASK (0x007a) ++#define P_VDEC_ASSIST_MBOX2_MASK (volatile unsigned int *)((0x007a << 2) + 0xff620000) ++#define VDEC_ASSIST_MBOX2_FIQ_SEL (0x007b) ++#define P_VDEC_ASSIST_MBOX2_FIQ_SEL (volatile unsigned int *)((0x007b << 2) + 0xff620000) ++//------------------------------------------------------------------------------ ++// VDEC2_ASSIST module level register offset ++//------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: DOS_VDEC2_ASSIST_CBUS_BASE = 0x00 ++// ----------------------------------------------- ++#define VDEC2_ASSIST_MMC_CTRL0 (0x2001) ++#define P_VDEC2_ASSIST_MMC_CTRL0 (volatile unsigned int *)((0x2001 << 2) + 0xff620000) ++#define VDEC2_ASSIST_MMC_CTRL1 (0x2002) ++#define P_VDEC2_ASSIST_MMC_CTRL1 (volatile unsigned int *)((0x2002 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR1_INT0 (0x2025) ++#define P_VDEC2_ASSIST_AMR1_INT0 (volatile unsigned int *)((0x2025 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR1_INT1 (0x2026) ++#define P_VDEC2_ASSIST_AMR1_INT1 (volatile unsigned int *)((0x2026 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR1_INT2 (0x2027) ++#define P_VDEC2_ASSIST_AMR1_INT2 (volatile unsigned int *)((0x2027 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR1_INT3 (0x2028) ++#define P_VDEC2_ASSIST_AMR1_INT3 (volatile unsigned int *)((0x2028 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR1_INT4 (0x2029) ++#define P_VDEC2_ASSIST_AMR1_INT4 (volatile unsigned int *)((0x2029 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR1_INT5 (0x202a) ++#define P_VDEC2_ASSIST_AMR1_INT5 (volatile unsigned int *)((0x202a << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR1_INT6 (0x202b) ++#define P_VDEC2_ASSIST_AMR1_INT6 (volatile unsigned int *)((0x202b << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR1_INT7 (0x202c) ++#define P_VDEC2_ASSIST_AMR1_INT7 (volatile unsigned int *)((0x202c << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR1_INT8 (0x202d) ++#define P_VDEC2_ASSIST_AMR1_INT8 (volatile unsigned int *)((0x202d << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR1_INT9 (0x202e) ++#define P_VDEC2_ASSIST_AMR1_INT9 (volatile unsigned int *)((0x202e << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR1_INTA (0x202f) ++#define P_VDEC2_ASSIST_AMR1_INTA (volatile unsigned int *)((0x202f << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR1_INTB (0x2030) ++#define P_VDEC2_ASSIST_AMR1_INTB (volatile unsigned int *)((0x2030 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR1_INTC (0x2031) ++#define P_VDEC2_ASSIST_AMR1_INTC (volatile unsigned int *)((0x2031 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR1_INTD (0x2032) ++#define P_VDEC2_ASSIST_AMR1_INTD (volatile unsigned int *)((0x2032 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR1_INTE (0x2033) ++#define P_VDEC2_ASSIST_AMR1_INTE (volatile unsigned int *)((0x2033 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR1_INTF (0x2034) ++#define P_VDEC2_ASSIST_AMR1_INTF (volatile unsigned int *)((0x2034 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR2_INT0 (0x2035) ++#define P_VDEC2_ASSIST_AMR2_INT0 (volatile unsigned int *)((0x2035 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR2_INT1 (0x2036) ++#define P_VDEC2_ASSIST_AMR2_INT1 (volatile unsigned int *)((0x2036 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR2_INT2 (0x2037) ++#define P_VDEC2_ASSIST_AMR2_INT2 (volatile unsigned int *)((0x2037 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR2_INT3 (0x2038) ++#define P_VDEC2_ASSIST_AMR2_INT3 (volatile unsigned int *)((0x2038 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR2_INT4 (0x2039) ++#define P_VDEC2_ASSIST_AMR2_INT4 (volatile unsigned int *)((0x2039 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR2_INT5 (0x203a) ++#define P_VDEC2_ASSIST_AMR2_INT5 (volatile unsigned int *)((0x203a << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR2_INT6 (0x203b) ++#define P_VDEC2_ASSIST_AMR2_INT6 (volatile unsigned int *)((0x203b << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR2_INT7 (0x203c) ++#define P_VDEC2_ASSIST_AMR2_INT7 (volatile unsigned int *)((0x203c << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR2_INT8 (0x203d) ++#define P_VDEC2_ASSIST_AMR2_INT8 (volatile unsigned int *)((0x203d << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR2_INT9 (0x203e) ++#define P_VDEC2_ASSIST_AMR2_INT9 (volatile unsigned int *)((0x203e << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR2_INTA (0x203f) ++#define P_VDEC2_ASSIST_AMR2_INTA (volatile unsigned int *)((0x203f << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR2_INTB (0x2040) ++#define P_VDEC2_ASSIST_AMR2_INTB (volatile unsigned int *)((0x2040 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR2_INTC (0x2041) ++#define P_VDEC2_ASSIST_AMR2_INTC (volatile unsigned int *)((0x2041 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR2_INTD (0x2042) ++#define P_VDEC2_ASSIST_AMR2_INTD (volatile unsigned int *)((0x2042 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR2_INTE (0x2043) ++#define P_VDEC2_ASSIST_AMR2_INTE (volatile unsigned int *)((0x2043 << 2) + 0xff620000) ++#define VDEC2_ASSIST_AMR2_INTF (0x2044) ++#define P_VDEC2_ASSIST_AMR2_INTF (volatile unsigned int *)((0x2044 << 2) + 0xff620000) ++#define VDEC2_ASSIST_MBX_SSEL (0x2045) ++#define P_VDEC2_ASSIST_MBX_SSEL (volatile unsigned int *)((0x2045 << 2) + 0xff620000) ++#define VDEC2_ASSIST_TIMER0_LO (0x2060) ++#define P_VDEC2_ASSIST_TIMER0_LO (volatile unsigned int *)((0x2060 << 2) + 0xff620000) ++#define VDEC2_ASSIST_TIMER0_HI (0x2061) ++#define P_VDEC2_ASSIST_TIMER0_HI (volatile unsigned int *)((0x2061 << 2) + 0xff620000) ++#define VDEC2_ASSIST_TIMER1_LO (0x2062) ++#define P_VDEC2_ASSIST_TIMER1_LO (volatile unsigned int *)((0x2062 << 2) + 0xff620000) ++#define VDEC2_ASSIST_TIMER1_HI (0x2063) ++#define P_VDEC2_ASSIST_TIMER1_HI (volatile unsigned int *)((0x2063 << 2) + 0xff620000) ++#define VDEC2_ASSIST_DMA_INT (0x2064) ++#define P_VDEC2_ASSIST_DMA_INT (volatile unsigned int *)((0x2064 << 2) + 0xff620000) ++#define VDEC2_ASSIST_DMA_INT_MSK (0x2065) ++#define P_VDEC2_ASSIST_DMA_INT_MSK (volatile unsigned int *)((0x2065 << 2) + 0xff620000) ++#define VDEC2_ASSIST_DMA_INT2 (0x2066) ++#define P_VDEC2_ASSIST_DMA_INT2 (volatile unsigned int *)((0x2066 << 2) + 0xff620000) ++#define VDEC2_ASSIST_DMA_INT_MSK2 (0x2067) ++#define P_VDEC2_ASSIST_DMA_INT_MSK2 (volatile unsigned int *)((0x2067 << 2) + 0xff620000) ++#define VDEC2_ASSIST_MBOX0_IRQ_REG (0x2070) ++#define P_VDEC2_ASSIST_MBOX0_IRQ_REG (volatile unsigned int *)((0x2070 << 2) + 0xff620000) ++#define VDEC2_ASSIST_MBOX0_CLR_REG (0x2071) ++#define P_VDEC2_ASSIST_MBOX0_CLR_REG (volatile unsigned int *)((0x2071 << 2) + 0xff620000) ++#define VDEC2_ASSIST_MBOX0_MASK (0x2072) ++#define P_VDEC2_ASSIST_MBOX0_MASK (volatile unsigned int *)((0x2072 << 2) + 0xff620000) ++#define VDEC2_ASSIST_MBOX0_FIQ_SEL (0x2073) ++#define P_VDEC2_ASSIST_MBOX0_FIQ_SEL (volatile unsigned int *)((0x2073 << 2) + 0xff620000) ++#define VDEC2_ASSIST_MBOX1_IRQ_REG (0x2074) ++#define P_VDEC2_ASSIST_MBOX1_IRQ_REG (volatile unsigned int *)((0x2074 << 2) + 0xff620000) ++#define VDEC2_ASSIST_MBOX1_CLR_REG (0x2075) ++#define P_VDEC2_ASSIST_MBOX1_CLR_REG (volatile unsigned int *)((0x2075 << 2) + 0xff620000) ++#define VDEC2_ASSIST_MBOX1_MASK (0x2076) ++#define P_VDEC2_ASSIST_MBOX1_MASK (volatile unsigned int *)((0x2076 << 2) + 0xff620000) ++#define VDEC2_ASSIST_MBOX1_FIQ_SEL (0x2077) ++#define P_VDEC2_ASSIST_MBOX1_FIQ_SEL (volatile unsigned int *)((0x2077 << 2) + 0xff620000) ++#define VDEC2_ASSIST_MBOX2_IRQ_REG (0x2078) ++#define P_VDEC2_ASSIST_MBOX2_IRQ_REG (volatile unsigned int *)((0x2078 << 2) + 0xff620000) ++#define VDEC2_ASSIST_MBOX2_CLR_REG (0x2079) ++#define P_VDEC2_ASSIST_MBOX2_CLR_REG (volatile unsigned int *)((0x2079 << 2) + 0xff620000) ++#define VDEC2_ASSIST_MBOX2_MASK (0x207a) ++#define P_VDEC2_ASSIST_MBOX2_MASK (volatile unsigned int *)((0x207a << 2) + 0xff620000) ++#define VDEC2_ASSIST_MBOX2_FIQ_SEL (0x207b) ++#define P_VDEC2_ASSIST_MBOX2_FIQ_SEL (volatile unsigned int *)((0x207b << 2) + 0xff620000) ++//------------------------------------------------------------------------------ ++// HCODEC_ASSIST module level register offset ++//------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HCODEC_ASSIST_CBUS_BASE = 0x00 ++// ----------------------------------------------- ++#define HCODEC_ASSIST_MMC_CTRL0 (0x1001) ++#define P_HCODEC_ASSIST_MMC_CTRL0 (volatile unsigned int *)((0x1001 << 2) + 0xff620000) ++#define HCODEC_ASSIST_MMC_CTRL1 (0x1002) ++#define P_HCODEC_ASSIST_MMC_CTRL1 (volatile unsigned int *)((0x1002 << 2) + 0xff620000) ++#define HCODEC_ASSIST_MMC_CTRL2 (0x1003) ++#define P_HCODEC_ASSIST_MMC_CTRL2 (volatile unsigned int *)((0x1003 << 2) + 0xff620000) ++#define HCODEC_ASSIST_MMC_CTRL3 (0x1004) ++#define P_HCODEC_ASSIST_MMC_CTRL3 (volatile unsigned int *)((0x1004 << 2) + 0xff620000) ++//cfg_soft_rst = mfdin_reg0_crst[0]; // Soft Reset ++//cfg_cg_cfe = mfdin_reg0_crst[1]; // Clock Gating Forcing Enable ++//cfg_dbuf_rst = mfdin_reg0_crst[2]; // Reset DBUF information ++#define HCODEC_MFDIN_REG0_CRST (0x1008) ++#define P_HCODEC_MFDIN_REG0_CRST (volatile unsigned int *)((0x1008 << 2) + 0xff620000) ++//cfg_iformat = mfdin_reg1_ctrl[3:0]; // Data In Format: 0 :CANVAS 422 YCbCr<-one canvas, ++ // 1 :CANVAS 444 YCbCr(or RGB)<-one canvas, ++ // 2 :CANVAS 420 Y<-one CrCb<-one (NV21) ++ // 3 :CANVAS 420 Y<-one CbCr<-one (NV12) ++ // 4 :CANVAS 420 Y<-one Cb<-one Cr<-one ++ // 5 :CANVAS 444 Y<-one Cb<-one Cr<-one ++ // 6 : Reserved for other canvas mode ++ // 7 : should combine with cfg_ifmt_extra, for 10-12bits ++ // 8 :LINEAR RGB888 (24bit) ++ // 9 :LINEAR RGB565 (16bit) ++ // 10:LINEAR YUV422 ++ // 11:LINEAR YUV420 (Note:Legacy mode not supported) ++ // 12~15: Reserved for other linear mode ++//cfg_oformat = mfdin_reg1_ctrl[5:4]; // Data Out Format: 0:420 1:422 2:444 3:reserved ++//cfg_dsample_enable= mfdin_reg1_ctrl[6]; // Downsample Enable ++//cfg_dsample_trunc = mfdin_reg1_ctrl[7]; // Downsample Addition Option: 0:Round 1:Truncated ++//cfg_block_ysize = mfdin_reg1_ctrl[8]; // 0:block-y-size=16, 1:block-y-size=8(for JPEG's efficiency) ++//cfg_interp_enable = mfdin_reg1_ctrl[9]; // Chroma Interpolation Enable ++//cfg_interp_mode = mfdin_reg1_ctrl[11:10];// 0:average round 1:average truncated 2:repeat left 3:repeat right ++//cfg_r2y_enable = mfdin_reg1_ctrl[12]; // RGb->YUV Enable ++//cfg_r2y_mode = mfdin_reg1_ctrl[14:13];// RGb->YUV Mode ++//cfg_rgb565_mode = mfdin_reg1_ctrl[15]; // RGB565 mode: 0:fill zero in tail 1:fill zero in head ++//cfg_ifmt_extra = mfdin_reg1_ctrl[17:16];// when cfg_iformat==7, ++ // 0: CANVAS 12bit 422, YCbCr<-one canvas{...Y1[11:0],C1[11:0],Y0[11:0],C0[11:0]} ++ // 1: CANVAS 10bit 444, YCbCr<-one canvas{...2'b0,Y0[9:0],U0[9:0],V0[9:0]} ++ // 2: CANVAS 10bit 422, YCbCr<-one canvas{...Y1[9:0],C1[9:0],Y0[9:0],C0[9:0]} ++//cfg_reserved1 = mfdin_reg1_ctrl[18]; // Reserved ++//cfg_nr_enable = mfdin_reg1_ctrl[19]; // Noise Reduction Enable ++//cfg_outofpic = mfdin_reg1_ctrl[28:20];// Out Of Picture Control: [8]mode:0:extend 1:fixed, [7:0]fixed value ++//cfg_rd_blktype = mfdin_reg1_ctrl[30:29];// Block Type: 0:H264_I_PIC_ALL_4x4, 1:H264_P_PIC_Y_16x16_C_8x8, 2:JPEG_ALL_8x8, 3:Reserved ++//cfg_rd_nonycintl = mfdin_reg1_ctrl[31]; // 0:YC interleaved 1:YC non-interleaved(for JPEG) ++#define HCODEC_MFDIN_REG1_CTRL (0x1009) ++#define P_HCODEC_MFDIN_REG1_CTRL (volatile unsigned int *)((0x1009 << 2) + 0xff620000) ++//mfdin_reg2: DEBUG Only Status ++#define HCODEC_MFDIN_REG2_STAT (0x100a) ++#define P_HCODEC_MFDIN_REG2_STAT (volatile unsigned int *)((0x100a << 2) + 0xff620000) ++//cfg_canvas_index0 = mfdin_reg3_canv[7:0]; //canvas index 0 ++//cfg_canvas_index1 = mfdin_reg3_canv[15:8]; //canvas index 1 ++//cfg_canvas_index2 = mfdin_reg3_canv[23:16];//canvas index 2 ++//cfg_canv_idx0_bppx = mfdin_reg3_canv[25:24];//canvas bytes per pixel in x direction for index0, 0:half 1:1 2:2 3:3 ++//cfg_canv_idx1_bppx = mfdin_reg3_canv[27:26];//canvas bytes per pixel in x direction for index1, 0:half 1:1 2:2 3:3 ++//cfg_canv_idx0_bppy = mfdin_reg3_canv[29:28];//canvas bytes per pixel in y direction for index0, 0:half 1:1 2:2 3:3 ++//cfg_canv_idx1_bppy = mfdin_reg3_canv[31:30];//canvas bytes per pixel in y direction for index1, 0:half 1:1 2:2 3:3 ++#define HCODEC_MFDIN_REG3_CANV (0x100b) ++#define P_HCODEC_MFDIN_REG3_CANV (volatile unsigned int *)((0x100b << 2) + 0xff620000) ++//cfg_bytes_per_line = mfdin_reg4_lnr0[15:0]; //linear Bytes per line ++//cfg_linear_bytes4p = mfdin_reg4_lnr0[17:16]; //linear (Bytes per pixel) - 1 ++//cfg_linear_dbl2line = mfdin_reg4_lnr0[18]; //linear double size for odd line ++#define HCODEC_MFDIN_REG4_LNR0 (0x100c) ++#define P_HCODEC_MFDIN_REG4_LNR0 (volatile unsigned int *)((0x100c << 2) + 0xff620000) ++//cfg_base_address = mfdin_reg5_lnr1[31:0]; //linear base address ++#define HCODEC_MFDIN_REG5_LNR1 (0x100d) ++#define P_HCODEC_MFDIN_REG5_LNR1 (volatile unsigned int *)((0x100d << 2) + 0xff620000) ++//assign cfg_r2y_trunc = mfdin_reg6_dcfg[9]; //RGb->YUV Addition Option: 0:Round 1:Truncated ++//assign cfg_dma_ugt = mfdin_reg6_dcfg[8]; //DMA Urgent ++//assign cfg_dma_thread_id = mfdin_reg6_dcfg[7:6]; //DMA Thread ID ++//assign cfg_dma_burst_num = mfdin_reg6_dcfg[5:0]; //DMA Burst Number ++#define HCODEC_MFDIN_REG6_DCFG (0x100e) ++#define P_HCODEC_MFDIN_REG6_DCFG (volatile unsigned int *)((0x100e << 2) + 0xff620000) ++//cfg_soft_cmd = mfdin_reg7_scmd; // Soft Command [28]selfcleared start,[27:14]dmb_x,[13:0]dmb_y ++#define HCODEC_MFDIN_REG7_SCMD (0x100f) ++#define P_HCODEC_MFDIN_REG7_SCMD (volatile unsigned int *)((0x100f << 2) + 0xff620000) ++//cfg_pic_xsize = mfdin_reg8_dmbl[23:12]; //pixel (x,y) at the begining of last dmb in the picturem, picture x size ++//cfg_pic_ysize = mfdin_reg8_dmbl[11:0]; //picture y size ++#define HCODEC_MFDIN_REG8_DMBL (0x1010) ++#define P_HCODEC_MFDIN_REG8_DMBL (volatile unsigned int *)((0x1010 << 2) + 0xff620000) ++//cfg_endian = mfdin_reg9_endn; //Endian Control ++#define HCODEC_MFDIN_REG9_ENDN (0x1011) ++#define P_HCODEC_MFDIN_REG9_ENDN (volatile unsigned int *)((0x1011 << 2) + 0xff620000) ++//cfg_canv_biasx = mfdin_rega_cav1[23:12]; //canvas bias address x ++//cfg_canv_biasy = mfdin_rega_cav1[11:0]; //canvas bias address y ++#define HCODEC_MFDIN_REGA_CAV1 (0x1012) ++#define P_HCODEC_MFDIN_REGA_CAV1 (volatile unsigned int *)((0x1012 << 2) + 0xff620000) ++//cfg_amp_en = mfdin_regb_ampc[24]; //Amplitude Enable ++//cfg_amp_cy = mfdin_regb_ampc[23:16]; //Amplitude Coeff Y ++//cfg_amp_cu = mfdin_regb_ampc[15:8]; //Amplitude Coeff U ++//cfg_amp_cv = mfdin_regb_ampc[7:0]; //Amplitude Coeff V ++#define HCODEC_MFDIN_REGB_AMPC (0x1013) ++#define P_HCODEC_MFDIN_REGB_AMPC (volatile unsigned int *)((0x1013 << 2) + 0xff620000) ++//cfg_mb_end = mfdin_regc_mblp; // Soft Command [28]mb end enable,[27:14]dmb_x,[13:0]dmb_y ++#define HCODEC_MFDIN_REGC_MBLP (0x1014) ++#define P_HCODEC_MFDIN_REGC_MBLP (volatile unsigned int *)((0x1014 << 2) + 0xff620000) ++// cfg_y_snr_en = mfdin_reg0d[0]; ++// cfg_y_snr_err_norm = mfdin_reg0d[1]; ++// [3:0] cfg_y_snr_gau_bld_core = mfdin_reg0d[5:2]; ++// [7:0] cfg_y_snr_gau_bld_ofst = mfdin_reg0d[13:6]; ++// [5:0] cfg_y_snr_gau_bld_rate = mfdin_reg0d[19:14]; ++// [5:0] cfg_y_snr_gau_alp0_min = mfdin_reg0d[25:20]; ++// [5:0] cfg_y_snr_gau_alp0_max = mfdin_reg0d[31:26]; ++#define HCODEC_MFDIN_REG0D (0x1015) ++#define P_HCODEC_MFDIN_REG0D (volatile unsigned int *)((0x1015 << 2) + 0xff620000) ++// cfg_y_tnr_en = mfdin_reg0e[0]; ++// cfg_y_tnr_mc_en = mfdin_reg0e[1]; ++// cfg_y_tnr_txt_mode = mfdin_reg0e[2]; ++// [3:0] cfg_y_tnr_mot_sad_margin = mfdin_reg0e[6:3]; ++// [5:0] cfg_y_tnr_alpha_min = mfdin_reg0e[12:7]; ++// [5:0] cfg_y_tnr_alpha_max = mfdin_reg0e[18:13]; ++// [5:0] cfg_y_tnr_deghost_os = mfdin_reg0e[24:19]; ++#define HCODEC_MFDIN_REG0E (0x1016) ++#define P_HCODEC_MFDIN_REG0E (volatile unsigned int *)((0x1016 << 2) + 0xff620000) ++// [3:0] cfg_y_tnr_mot_cortxt_rate = mfdin_reg0f[3:0]; ++// [7:0] cfg_y_tnr_mot_distxt_ofst = mfdin_reg0f[15:8]; ++// [3:0] cfg_y_tnr_mot_distxt_rate = mfdin_reg0f[7:4]; ++// [7:0] cfg_y_tnr_mot_dismot_ofst = mfdin_reg0f[23:16]; ++// [7:0] cfg_y_tnr_mot_frcsad_lock = mfdin_reg0f[31:24]; ++#define HCODEC_MFDIN_REG0F (0x1017) ++#define P_HCODEC_MFDIN_REG0F (volatile unsigned int *)((0x1017 << 2) + 0xff620000) ++// [7:0] cfg_y_tnr_mot2alp_frc_gain = mfdin_reg10[7:0]; ++// [7:0] cfg_y_tnr_mot2alp_nrm_gain = mfdin_reg10[15:8]; ++// [7:0] cfg_y_tnr_mot2alp_dis_gain = mfdin_reg10[23:16]; ++// [5:0] cfg_y_tnr_mot2alp_dis_ofst = mfdin_reg10[29:24]; ++#define HCODEC_MFDIN_REG10 (0x1018) ++#define P_HCODEC_MFDIN_REG10 (volatile unsigned int *)((0x1018 << 2) + 0xff620000) ++// [7:0] cfg_y_bld_beta2alp_rate = mfdin_reg11[7:0]; ++// [5:0] cfg_y_bld_beta_min = mfdin_reg11[13:8]; ++// [5:0] cfg_y_bld_beta_max = mfdin_reg11[19:14]; ++#define HCODEC_MFDIN_REG11 (0x1019) ++#define P_HCODEC_MFDIN_REG11 (volatile unsigned int *)((0x1019 << 2) + 0xff620000) ++// REG12~16 for Chroma, same as Luma ++#define HCODEC_MFDIN_REG12 (0x101a) ++#define P_HCODEC_MFDIN_REG12 (volatile unsigned int *)((0x101a << 2) + 0xff620000) ++#define HCODEC_MFDIN_REG13 (0x101b) ++#define P_HCODEC_MFDIN_REG13 (volatile unsigned int *)((0x101b << 2) + 0xff620000) ++#define HCODEC_MFDIN_REG14 (0x101c) ++#define P_HCODEC_MFDIN_REG14 (volatile unsigned int *)((0x101c << 2) + 0xff620000) ++#define HCODEC_MFDIN_REG15 (0x101d) ++#define P_HCODEC_MFDIN_REG15 (volatile unsigned int *)((0x101d << 2) + 0xff620000) ++#define HCODEC_MFDIN_REG16 (0x101e) ++#define P_HCODEC_MFDIN_REG16 (volatile unsigned int *)((0x101e << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR1_INT0 (0x1025) ++#define P_HCODEC_ASSIST_AMR1_INT0 (volatile unsigned int *)((0x1025 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR1_INT1 (0x1026) ++#define P_HCODEC_ASSIST_AMR1_INT1 (volatile unsigned int *)((0x1026 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR1_INT2 (0x1027) ++#define P_HCODEC_ASSIST_AMR1_INT2 (volatile unsigned int *)((0x1027 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR1_INT3 (0x1028) ++#define P_HCODEC_ASSIST_AMR1_INT3 (volatile unsigned int *)((0x1028 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR1_INT4 (0x1029) ++#define P_HCODEC_ASSIST_AMR1_INT4 (volatile unsigned int *)((0x1029 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR1_INT5 (0x102a) ++#define P_HCODEC_ASSIST_AMR1_INT5 (volatile unsigned int *)((0x102a << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR1_INT6 (0x102b) ++#define P_HCODEC_ASSIST_AMR1_INT6 (volatile unsigned int *)((0x102b << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR1_INT7 (0x102c) ++#define P_HCODEC_ASSIST_AMR1_INT7 (volatile unsigned int *)((0x102c << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR1_INT8 (0x102d) ++#define P_HCODEC_ASSIST_AMR1_INT8 (volatile unsigned int *)((0x102d << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR1_INT9 (0x102e) ++#define P_HCODEC_ASSIST_AMR1_INT9 (volatile unsigned int *)((0x102e << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR1_INTA (0x102f) ++#define P_HCODEC_ASSIST_AMR1_INTA (volatile unsigned int *)((0x102f << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR1_INTB (0x1030) ++#define P_HCODEC_ASSIST_AMR1_INTB (volatile unsigned int *)((0x1030 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR1_INTC (0x1031) ++#define P_HCODEC_ASSIST_AMR1_INTC (volatile unsigned int *)((0x1031 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR1_INTD (0x1032) ++#define P_HCODEC_ASSIST_AMR1_INTD (volatile unsigned int *)((0x1032 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR1_INTE (0x1033) ++#define P_HCODEC_ASSIST_AMR1_INTE (volatile unsigned int *)((0x1033 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR1_INTF (0x1034) ++#define P_HCODEC_ASSIST_AMR1_INTF (volatile unsigned int *)((0x1034 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR2_INT0 (0x1035) ++#define P_HCODEC_ASSIST_AMR2_INT0 (volatile unsigned int *)((0x1035 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR2_INT1 (0x1036) ++#define P_HCODEC_ASSIST_AMR2_INT1 (volatile unsigned int *)((0x1036 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR2_INT2 (0x1037) ++#define P_HCODEC_ASSIST_AMR2_INT2 (volatile unsigned int *)((0x1037 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR2_INT3 (0x1038) ++#define P_HCODEC_ASSIST_AMR2_INT3 (volatile unsigned int *)((0x1038 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR2_INT4 (0x1039) ++#define P_HCODEC_ASSIST_AMR2_INT4 (volatile unsigned int *)((0x1039 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR2_INT5 (0x103a) ++#define P_HCODEC_ASSIST_AMR2_INT5 (volatile unsigned int *)((0x103a << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR2_INT6 (0x103b) ++#define P_HCODEC_ASSIST_AMR2_INT6 (volatile unsigned int *)((0x103b << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR2_INT7 (0x103c) ++#define P_HCODEC_ASSIST_AMR2_INT7 (volatile unsigned int *)((0x103c << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR2_INT8 (0x103d) ++#define P_HCODEC_ASSIST_AMR2_INT8 (volatile unsigned int *)((0x103d << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR2_INT9 (0x103e) ++#define P_HCODEC_ASSIST_AMR2_INT9 (volatile unsigned int *)((0x103e << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR2_INTA (0x103f) ++#define P_HCODEC_ASSIST_AMR2_INTA (volatile unsigned int *)((0x103f << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR2_INTB (0x1040) ++#define P_HCODEC_ASSIST_AMR2_INTB (volatile unsigned int *)((0x1040 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR2_INTC (0x1041) ++#define P_HCODEC_ASSIST_AMR2_INTC (volatile unsigned int *)((0x1041 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR2_INTD (0x1042) ++#define P_HCODEC_ASSIST_AMR2_INTD (volatile unsigned int *)((0x1042 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR2_INTE (0x1043) ++#define P_HCODEC_ASSIST_AMR2_INTE (volatile unsigned int *)((0x1043 << 2) + 0xff620000) ++#define HCODEC_ASSIST_AMR2_INTF (0x1044) ++#define P_HCODEC_ASSIST_AMR2_INTF (volatile unsigned int *)((0x1044 << 2) + 0xff620000) ++#define HCODEC_ASSIST_MBX_SSEL (0x1045) ++#define P_HCODEC_ASSIST_MBX_SSEL (volatile unsigned int *)((0x1045 << 2) + 0xff620000) ++#define HCODEC_ASSIST_TIMER0_LO (0x1060) ++#define P_HCODEC_ASSIST_TIMER0_LO (volatile unsigned int *)((0x1060 << 2) + 0xff620000) ++#define HCODEC_ASSIST_TIMER0_HI (0x1061) ++#define P_HCODEC_ASSIST_TIMER0_HI (volatile unsigned int *)((0x1061 << 2) + 0xff620000) ++#define HCODEC_ASSIST_TIMER1_LO (0x1062) ++#define P_HCODEC_ASSIST_TIMER1_LO (volatile unsigned int *)((0x1062 << 2) + 0xff620000) ++#define HCODEC_ASSIST_TIMER1_HI (0x1063) ++#define P_HCODEC_ASSIST_TIMER1_HI (volatile unsigned int *)((0x1063 << 2) + 0xff620000) ++#define HCODEC_ASSIST_DMA_INT (0x1064) ++#define P_HCODEC_ASSIST_DMA_INT (volatile unsigned int *)((0x1064 << 2) + 0xff620000) ++#define HCODEC_ASSIST_DMA_INT_MSK (0x1065) ++#define P_HCODEC_ASSIST_DMA_INT_MSK (volatile unsigned int *)((0x1065 << 2) + 0xff620000) ++#define HCODEC_ASSIST_DMA_INT2 (0x1066) ++#define P_HCODEC_ASSIST_DMA_INT2 (volatile unsigned int *)((0x1066 << 2) + 0xff620000) ++#define HCODEC_ASSIST_DMA_INT_MSK2 (0x1067) ++#define P_HCODEC_ASSIST_DMA_INT_MSK2 (volatile unsigned int *)((0x1067 << 2) + 0xff620000) ++#define HCODEC_ASSIST_MBOX0_IRQ_REG (0x1070) ++#define P_HCODEC_ASSIST_MBOX0_IRQ_REG (volatile unsigned int *)((0x1070 << 2) + 0xff620000) ++#define HCODEC_ASSIST_MBOX0_CLR_REG (0x1071) ++#define P_HCODEC_ASSIST_MBOX0_CLR_REG (volatile unsigned int *)((0x1071 << 2) + 0xff620000) ++#define HCODEC_ASSIST_MBOX0_MASK (0x1072) ++#define P_HCODEC_ASSIST_MBOX0_MASK (volatile unsigned int *)((0x1072 << 2) + 0xff620000) ++#define HCODEC_ASSIST_MBOX0_FIQ_SEL (0x1073) ++#define P_HCODEC_ASSIST_MBOX0_FIQ_SEL (volatile unsigned int *)((0x1073 << 2) + 0xff620000) ++#define HCODEC_ASSIST_MBOX1_IRQ_REG (0x1074) ++#define P_HCODEC_ASSIST_MBOX1_IRQ_REG (volatile unsigned int *)((0x1074 << 2) + 0xff620000) ++#define HCODEC_ASSIST_MBOX1_CLR_REG (0x1075) ++#define P_HCODEC_ASSIST_MBOX1_CLR_REG (volatile unsigned int *)((0x1075 << 2) + 0xff620000) ++#define HCODEC_ASSIST_MBOX1_MASK (0x1076) ++#define P_HCODEC_ASSIST_MBOX1_MASK (volatile unsigned int *)((0x1076 << 2) + 0xff620000) ++#define HCODEC_ASSIST_MBOX1_FIQ_SEL (0x1077) ++#define P_HCODEC_ASSIST_MBOX1_FIQ_SEL (volatile unsigned int *)((0x1077 << 2) + 0xff620000) ++#define HCODEC_ASSIST_MBOX2_IRQ_REG (0x1078) ++#define P_HCODEC_ASSIST_MBOX2_IRQ_REG (volatile unsigned int *)((0x1078 << 2) + 0xff620000) ++#define HCODEC_ASSIST_MBOX2_CLR_REG (0x1079) ++#define P_HCODEC_ASSIST_MBOX2_CLR_REG (volatile unsigned int *)((0x1079 << 2) + 0xff620000) ++#define HCODEC_ASSIST_MBOX2_MASK (0x107a) ++#define P_HCODEC_ASSIST_MBOX2_MASK (volatile unsigned int *)((0x107a << 2) + 0xff620000) ++#define HCODEC_ASSIST_MBOX2_FIQ_SEL (0x107b) ++#define P_HCODEC_ASSIST_MBOX2_FIQ_SEL (volatile unsigned int *)((0x107b << 2) + 0xff620000) ++//------------------------------------------------------------------------------ ++// MDEC module level register offset ++//------------------------------------------------------------------------------ ++// ++// Reading file: mdec_regs.h ++// ++//======================================================================== ++// MDEC module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_VDEC_MDEC_CBUS_BASE = 0x09 ++// ----------------------------------------------- ++#define MC_CTRL_REG (0x0900) ++#define P_MC_CTRL_REG (volatile unsigned int *)((0x0900 << 2) + 0xff620000) ++#define MC_MB_INFO (0x0901) ++#define P_MC_MB_INFO (volatile unsigned int *)((0x0901 << 2) + 0xff620000) ++#define MC_PIC_INFO (0x0902) ++#define P_MC_PIC_INFO (volatile unsigned int *)((0x0902 << 2) + 0xff620000) ++#define MC_HALF_PEL_ONE (0x0903) ++#define P_MC_HALF_PEL_ONE (volatile unsigned int *)((0x0903 << 2) + 0xff620000) ++#define MC_HALF_PEL_TWO (0x0904) ++#define P_MC_HALF_PEL_TWO (volatile unsigned int *)((0x0904 << 2) + 0xff620000) ++#define POWER_CTL_MC (0x0905) ++#define P_POWER_CTL_MC (volatile unsigned int *)((0x0905 << 2) + 0xff620000) ++#define MC_CMD (0x0906) ++#define P_MC_CMD (volatile unsigned int *)((0x0906 << 2) + 0xff620000) ++#define MC_CTRL0 (0x0907) ++#define P_MC_CTRL0 (volatile unsigned int *)((0x0907 << 2) + 0xff620000) ++#define MC_PIC_W_H (0x0908) ++#define P_MC_PIC_W_H (volatile unsigned int *)((0x0908 << 2) + 0xff620000) ++#define MC_STATUS0 (0x0909) ++#define P_MC_STATUS0 (volatile unsigned int *)((0x0909 << 2) + 0xff620000) ++#define MC_STATUS1 (0x090a) ++#define P_MC_STATUS1 (volatile unsigned int *)((0x090a << 2) + 0xff620000) ++#define MC_CTRL1 (0x090b) ++#define P_MC_CTRL1 (volatile unsigned int *)((0x090b << 2) + 0xff620000) ++#define MC_MIX_RATIO0 (0x090c) ++#define P_MC_MIX_RATIO0 (volatile unsigned int *)((0x090c << 2) + 0xff620000) ++#define MC_MIX_RATIO1 (0x090d) ++#define P_MC_MIX_RATIO1 (volatile unsigned int *)((0x090d << 2) + 0xff620000) ++#define MC_DP_MB_XY (0x090e) ++#define P_MC_DP_MB_XY (volatile unsigned int *)((0x090e << 2) + 0xff620000) ++#define MC_OM_MB_XY (0x090f) ++#define P_MC_OM_MB_XY (volatile unsigned int *)((0x090f << 2) + 0xff620000) ++#define PSCALE_RST (0x0910) ++#define P_PSCALE_RST (volatile unsigned int *)((0x0910 << 2) + 0xff620000) ++#define PSCALE_CTRL (0x0911) ++#define P_PSCALE_CTRL (volatile unsigned int *)((0x0911 << 2) + 0xff620000) ++#define PSCALE_PICI_W (0x0912) ++#define P_PSCALE_PICI_W (volatile unsigned int *)((0x0912 << 2) + 0xff620000) ++#define PSCALE_PICI_H (0x0913) ++#define P_PSCALE_PICI_H (volatile unsigned int *)((0x0913 << 2) + 0xff620000) ++#define PSCALE_PICO_W (0x0914) ++#define P_PSCALE_PICO_W (volatile unsigned int *)((0x0914 << 2) + 0xff620000) ++#define PSCALE_PICO_H (0x0915) ++#define P_PSCALE_PICO_H (volatile unsigned int *)((0x0915 << 2) + 0xff620000) ++#define PSCALE_PICO_START_X (0x0916) ++#define P_PSCALE_PICO_START_X (volatile unsigned int *)((0x0916 << 2) + 0xff620000) ++#define PSCALE_PICO_START_Y (0x0917) ++#define P_PSCALE_PICO_START_Y (volatile unsigned int *)((0x0917 << 2) + 0xff620000) ++#define PSCALE_DUMMY (0x0918) ++#define P_PSCALE_DUMMY (volatile unsigned int *)((0x0918 << 2) + 0xff620000) ++#define PSCALE_FILT0_COEF0 (0x0919) ++#define P_PSCALE_FILT0_COEF0 (volatile unsigned int *)((0x0919 << 2) + 0xff620000) ++#define PSCALE_FILT0_COEF1 (0x091a) ++#define P_PSCALE_FILT0_COEF1 (volatile unsigned int *)((0x091a << 2) + 0xff620000) ++#define PSCALE_CMD_CTRL (0x091b) ++#define P_PSCALE_CMD_CTRL (volatile unsigned int *)((0x091b << 2) + 0xff620000) ++#define PSCALE_CMD_BLK_X (0x091c) ++#define P_PSCALE_CMD_BLK_X (volatile unsigned int *)((0x091c << 2) + 0xff620000) ++#define PSCALE_CMD_BLK_Y (0x091d) ++#define P_PSCALE_CMD_BLK_Y (volatile unsigned int *)((0x091d << 2) + 0xff620000) ++#define PSCALE_STATUS (0x091e) ++#define P_PSCALE_STATUS (volatile unsigned int *)((0x091e << 2) + 0xff620000) ++#define PSCALE_BMEM_ADDR (0x091f) ++#define P_PSCALE_BMEM_ADDR (volatile unsigned int *)((0x091f << 2) + 0xff620000) ++#define PSCALE_BMEM_DAT (0x0920) ++#define P_PSCALE_BMEM_DAT (volatile unsigned int *)((0x0920 << 2) + 0xff620000) ++#define PSCALE_DRAM_BUF_CTRL (0x0921) ++#define P_PSCALE_DRAM_BUF_CTRL (volatile unsigned int *)((0x0921 << 2) + 0xff620000) ++#define PSCALE_MCMD_CTRL (0x0922) ++#define P_PSCALE_MCMD_CTRL (volatile unsigned int *)((0x0922 << 2) + 0xff620000) ++#define PSCALE_MCMD_XSIZE (0x0923) ++#define P_PSCALE_MCMD_XSIZE (volatile unsigned int *)((0x0923 << 2) + 0xff620000) ++#define PSCALE_MCMD_YSIZE (0x0924) ++#define P_PSCALE_MCMD_YSIZE (volatile unsigned int *)((0x0924 << 2) + 0xff620000) ++#define PSCALE_RBUF_START_BLKX (0x0925) ++#define P_PSCALE_RBUF_START_BLKX (volatile unsigned int *)((0x0925 << 2) + 0xff620000) ++#define PSCALE_RBUF_START_BLKY (0x0926) ++#define P_PSCALE_RBUF_START_BLKY (volatile unsigned int *)((0x0926 << 2) + 0xff620000) ++//`define PSCALE_RBUF_MB_WIDTH 8'h27 ++#define PSCALE_PICO_SHIFT_XY (0x0928) ++#define P_PSCALE_PICO_SHIFT_XY (volatile unsigned int *)((0x0928 << 2) + 0xff620000) ++#define PSCALE_CTRL1 (0x0929) ++#define P_PSCALE_CTRL1 (volatile unsigned int *)((0x0929 << 2) + 0xff620000) ++//Bit 15, wmask enable ++//Bit 14:13, filt0 srckey_less, ++//Bit 12:11, filt1 srckey_less, in the case of the interpolated data is equal distance to ++//key data and normal data, 00: select normal data, 01: select right data, 10: select key data ++//Bit 10:9, srckey mode, 00: equal, 01: less than or equal, 10: great than or equal ++//Bit 8, src key enable ++//Bit 7:0, y src key ++#define PSCALE_SRCKEY_CTRL0 (0x092a) ++#define P_PSCALE_SRCKEY_CTRL0 (volatile unsigned int *)((0x092a << 2) + 0xff620000) ++//Bit 15:8, cb src key ++//Bit 7:0, cr src key ++#define PSCALE_SRCKEY_CTRL1 (0x092b) ++#define P_PSCALE_SRCKEY_CTRL1 (volatile unsigned int *)((0x092b << 2) + 0xff620000) ++//Bit 22:16 canvas_rd_addr2 ++//Bit 14:8 canvas_rd_addr1 ++//Bit 6:0 canvas_rd_addr1 ++#define PSCALE_CANVAS_RD_ADDR (0x092c) ++#define P_PSCALE_CANVAS_RD_ADDR (volatile unsigned int *)((0x092c << 2) + 0xff620000) ++//Bit 22:16 canvas_wr_addr2 ++//Bit 14:8 canvas_wr_addr1 ++//Bit 6:0 canvas_wr_addr1 ++#define PSCALE_CANVAS_WR_ADDR (0x092d) ++#define P_PSCALE_CANVAS_WR_ADDR (volatile unsigned int *)((0x092d << 2) + 0xff620000) ++//bit 13:8 pscale thread ID and token ++//bit 7 disable write response count adding to busy bit ++//bit 5:0 pscale prearbitor burst num ++#define PSCALE_CTRL2 (0x092e) ++#define P_PSCALE_CTRL2 (volatile unsigned int *)((0x092e << 2) + 0xff620000) ++// 31 - use_omem_mb_xy_auto ++//23:16 - omem_max_mb_x ++//15:8 - omem_mb_y_auto ++// 7:0 - omem_mb_x_auto ++#define HDEC_MC_OMEM_AUTO (0x0930) ++#define P_HDEC_MC_OMEM_AUTO (volatile unsigned int *)((0x0930 << 2) + 0xff620000) ++#define HDEC_MC_MBRIGHT_IDX (0x0931) ++#define P_HDEC_MC_MBRIGHT_IDX (volatile unsigned int *)((0x0931 << 2) + 0xff620000) ++#define HDEC_MC_MBRIGHT_RD (0x0932) ++#define P_HDEC_MC_MBRIGHT_RD (volatile unsigned int *)((0x0932 << 2) + 0xff620000) ++#define MC_MPORT_CTRL (0x0940) ++#define P_MC_MPORT_CTRL (volatile unsigned int *)((0x0940 << 2) + 0xff620000) ++#define MC_MPORT_DAT (0x0941) ++#define P_MC_MPORT_DAT (volatile unsigned int *)((0x0941 << 2) + 0xff620000) ++#define MC_WT_PRED_CTRL (0x0942) ++#define P_MC_WT_PRED_CTRL (volatile unsigned int *)((0x0942 << 2) + 0xff620000) ++#define MC_MBBOT_ST_EVEN_ADDR (0x0944) ++#define P_MC_MBBOT_ST_EVEN_ADDR (volatile unsigned int *)((0x0944 << 2) + 0xff620000) ++#define MC_MBBOT_ST_ODD_ADDR (0x0945) ++#define P_MC_MBBOT_ST_ODD_ADDR (volatile unsigned int *)((0x0945 << 2) + 0xff620000) ++#define MC_DPDN_MB_XY (0x0946) ++#define P_MC_DPDN_MB_XY (volatile unsigned int *)((0x0946 << 2) + 0xff620000) ++#define MC_OMDN_MB_XY (0x0947) ++#define P_MC_OMDN_MB_XY (volatile unsigned int *)((0x0947 << 2) + 0xff620000) ++#define MC_HCMDBUF_H (0x0948) ++#define P_MC_HCMDBUF_H (volatile unsigned int *)((0x0948 << 2) + 0xff620000) ++#define MC_HCMDBUF_L (0x0949) ++#define P_MC_HCMDBUF_L (volatile unsigned int *)((0x0949 << 2) + 0xff620000) ++#define MC_HCMD_H (0x094a) ++#define P_MC_HCMD_H (volatile unsigned int *)((0x094a << 2) + 0xff620000) ++#define MC_HCMD_L (0x094b) ++#define P_MC_HCMD_L (volatile unsigned int *)((0x094b << 2) + 0xff620000) ++#define MC_IDCT_DAT (0x094c) ++#define P_MC_IDCT_DAT (volatile unsigned int *)((0x094c << 2) + 0xff620000) ++#define MC_CTRL_GCLK_CTRL (0x094d) ++#define P_MC_CTRL_GCLK_CTRL (volatile unsigned int *)((0x094d << 2) + 0xff620000) ++#define MC_OTHER_GCLK_CTRL (0x094e) ++#define P_MC_OTHER_GCLK_CTRL (volatile unsigned int *)((0x094e << 2) + 0xff620000) ++//Bit 29:24, mbbot thread ID and token ++//Bit 21:16, mc read/write thread ID and token ++//Bit 13:8, mbbot pre-arbitor burst number ++//Bit 5:0, mc pre-arbitor burst number ++#define MC_CTRL2 (0x094f) ++#define P_MC_CTRL2 (volatile unsigned int *)((0x094f << 2) + 0xff620000) ++// `define DBLK_QUANT 8'h76 // ONLY for $ucode/real/amrisc/rv.s, reg value from apollo ++//`define ANC1_CANVAS_ADDR 8'h80 ++//`define ANC2_CANVAS_ADDR 8'h81 ++//`define REC_CANVAS_ADDR 8'h89 ++//`define MDEC_PIC_W 8'h8c ++//`define MDEC_PIC_H 8'h8d ++// mdec_pic_dc_mux_ctrl[31] -- mcr_hevc_mode ++#define MDEC_PIC_DC_MUX_CTRL (0x098d) ++#define P_MDEC_PIC_DC_MUX_CTRL (volatile unsigned int *)((0x098d << 2) + 0xff620000) ++#define MDEC_PIC_DC_CTRL (0x098e) ++#define P_MDEC_PIC_DC_CTRL (volatile unsigned int *)((0x098e << 2) + 0xff620000) ++#define MDEC_PIC_DC_STATUS (0x098f) ++#define P_MDEC_PIC_DC_STATUS (volatile unsigned int *)((0x098f << 2) + 0xff620000) ++#define ANC0_CANVAS_ADDR (0x0990) ++#define P_ANC0_CANVAS_ADDR (volatile unsigned int *)((0x0990 << 2) + 0xff620000) ++#define ANC1_CANVAS_ADDR (0x0991) ++#define P_ANC1_CANVAS_ADDR (volatile unsigned int *)((0x0991 << 2) + 0xff620000) ++#define ANC2_CANVAS_ADDR (0x0992) ++#define P_ANC2_CANVAS_ADDR (volatile unsigned int *)((0x0992 << 2) + 0xff620000) ++#define ANC3_CANVAS_ADDR (0x0993) ++#define P_ANC3_CANVAS_ADDR (volatile unsigned int *)((0x0993 << 2) + 0xff620000) ++#define ANC4_CANVAS_ADDR (0x0994) ++#define P_ANC4_CANVAS_ADDR (volatile unsigned int *)((0x0994 << 2) + 0xff620000) ++#define ANC5_CANVAS_ADDR (0x0995) ++#define P_ANC5_CANVAS_ADDR (volatile unsigned int *)((0x0995 << 2) + 0xff620000) ++#define ANC6_CANVAS_ADDR (0x0996) ++#define P_ANC6_CANVAS_ADDR (volatile unsigned int *)((0x0996 << 2) + 0xff620000) ++#define ANC7_CANVAS_ADDR (0x0997) ++#define P_ANC7_CANVAS_ADDR (volatile unsigned int *)((0x0997 << 2) + 0xff620000) ++#define ANC8_CANVAS_ADDR (0x0998) ++#define P_ANC8_CANVAS_ADDR (volatile unsigned int *)((0x0998 << 2) + 0xff620000) ++#define ANC9_CANVAS_ADDR (0x0999) ++#define P_ANC9_CANVAS_ADDR (volatile unsigned int *)((0x0999 << 2) + 0xff620000) ++#define ANC10_CANVAS_ADDR (0x099a) ++#define P_ANC10_CANVAS_ADDR (volatile unsigned int *)((0x099a << 2) + 0xff620000) ++#define ANC11_CANVAS_ADDR (0x099b) ++#define P_ANC11_CANVAS_ADDR (volatile unsigned int *)((0x099b << 2) + 0xff620000) ++#define ANC12_CANVAS_ADDR (0x099c) ++#define P_ANC12_CANVAS_ADDR (volatile unsigned int *)((0x099c << 2) + 0xff620000) ++#define ANC13_CANVAS_ADDR (0x099d) ++#define P_ANC13_CANVAS_ADDR (volatile unsigned int *)((0x099d << 2) + 0xff620000) ++#define ANC14_CANVAS_ADDR (0x099e) ++#define P_ANC14_CANVAS_ADDR (volatile unsigned int *)((0x099e << 2) + 0xff620000) ++#define ANC15_CANVAS_ADDR (0x099f) ++#define P_ANC15_CANVAS_ADDR (volatile unsigned int *)((0x099f << 2) + 0xff620000) ++#define ANC16_CANVAS_ADDR (0x09a0) ++#define P_ANC16_CANVAS_ADDR (volatile unsigned int *)((0x09a0 << 2) + 0xff620000) ++#define ANC17_CANVAS_ADDR (0x09a1) ++#define P_ANC17_CANVAS_ADDR (volatile unsigned int *)((0x09a1 << 2) + 0xff620000) ++#define ANC18_CANVAS_ADDR (0x09a2) ++#define P_ANC18_CANVAS_ADDR (volatile unsigned int *)((0x09a2 << 2) + 0xff620000) ++#define ANC19_CANVAS_ADDR (0x09a3) ++#define P_ANC19_CANVAS_ADDR (volatile unsigned int *)((0x09a3 << 2) + 0xff620000) ++#define ANC20_CANVAS_ADDR (0x09a4) ++#define P_ANC20_CANVAS_ADDR (volatile unsigned int *)((0x09a4 << 2) + 0xff620000) ++#define ANC21_CANVAS_ADDR (0x09a5) ++#define P_ANC21_CANVAS_ADDR (volatile unsigned int *)((0x09a5 << 2) + 0xff620000) ++#define ANC22_CANVAS_ADDR (0x09a6) ++#define P_ANC22_CANVAS_ADDR (volatile unsigned int *)((0x09a6 << 2) + 0xff620000) ++#define ANC23_CANVAS_ADDR (0x09a7) ++#define P_ANC23_CANVAS_ADDR (volatile unsigned int *)((0x09a7 << 2) + 0xff620000) ++#define ANC24_CANVAS_ADDR (0x09a8) ++#define P_ANC24_CANVAS_ADDR (volatile unsigned int *)((0x09a8 << 2) + 0xff620000) ++#define ANC25_CANVAS_ADDR (0x09a9) ++#define P_ANC25_CANVAS_ADDR (volatile unsigned int *)((0x09a9 << 2) + 0xff620000) ++#define ANC26_CANVAS_ADDR (0x09aa) ++#define P_ANC26_CANVAS_ADDR (volatile unsigned int *)((0x09aa << 2) + 0xff620000) ++#define ANC27_CANVAS_ADDR (0x09ab) ++#define P_ANC27_CANVAS_ADDR (volatile unsigned int *)((0x09ab << 2) + 0xff620000) ++#define ANC28_CANVAS_ADDR (0x09ac) ++#define P_ANC28_CANVAS_ADDR (volatile unsigned int *)((0x09ac << 2) + 0xff620000) ++#define ANC29_CANVAS_ADDR (0x09ad) ++#define P_ANC29_CANVAS_ADDR (volatile unsigned int *)((0x09ad << 2) + 0xff620000) ++#define ANC30_CANVAS_ADDR (0x09ae) ++#define P_ANC30_CANVAS_ADDR (volatile unsigned int *)((0x09ae << 2) + 0xff620000) ++#define ANC31_CANVAS_ADDR (0x09af) ++#define P_ANC31_CANVAS_ADDR (volatile unsigned int *)((0x09af << 2) + 0xff620000) ++#define DBKR_CANVAS_ADDR (0x09b0) ++#define P_DBKR_CANVAS_ADDR (volatile unsigned int *)((0x09b0 << 2) + 0xff620000) ++#define DBKW_CANVAS_ADDR (0x09b1) ++#define P_DBKW_CANVAS_ADDR (volatile unsigned int *)((0x09b1 << 2) + 0xff620000) ++#define REC_CANVAS_ADDR (0x09b2) ++#define P_REC_CANVAS_ADDR (volatile unsigned int *)((0x09b2 << 2) + 0xff620000) ++//28:24, read/write, current canvas idx, used in h264 only now ++//23:0, read only, current canvas address, 23:16, Cr canvas addr, 15:8, Cb canvas addr, 7:0, Y canvas addr ++#define CURR_CANVAS_CTRL (0x09b3) ++#define P_CURR_CANVAS_CTRL (volatile unsigned int *)((0x09b3 << 2) + 0xff620000) ++#define MDEC_PIC_DC_THRESH (0x09b8) ++#define P_MDEC_PIC_DC_THRESH (volatile unsigned int *)((0x09b8 << 2) + 0xff620000) ++#define MDEC_PICR_BUF_STATUS (0x09b9) ++#define P_MDEC_PICR_BUF_STATUS (volatile unsigned int *)((0x09b9 << 2) + 0xff620000) ++#define MDEC_PICW_BUF_STATUS (0x09ba) ++#define P_MDEC_PICW_BUF_STATUS (volatile unsigned int *)((0x09ba << 2) + 0xff620000) ++#define MCW_DBLK_WRRSP_CNT (0x09bb) ++#define P_MCW_DBLK_WRRSP_CNT (volatile unsigned int *)((0x09bb << 2) + 0xff620000) ++#define MC_MBBOT_WRRSP_CNT (0x09bc) ++#define P_MC_MBBOT_WRRSP_CNT (volatile unsigned int *)((0x09bc << 2) + 0xff620000) ++#define MDEC_PICW_BUF2_STATUS (0x09bd) ++#define P_MDEC_PICW_BUF2_STATUS (volatile unsigned int *)((0x09bd << 2) + 0xff620000) ++#define WRRSP_FIFO_PICW_DBK (0x09be) ++#define P_WRRSP_FIFO_PICW_DBK (volatile unsigned int *)((0x09be << 2) + 0xff620000) ++#define WRRSP_FIFO_PICW_MC (0x09bf) ++#define P_WRRSP_FIFO_PICW_MC (volatile unsigned int *)((0x09bf << 2) + 0xff620000) ++#define AV_SCRATCH_0 (0x09c0) ++#define P_AV_SCRATCH_0 (volatile unsigned int *)((0x09c0 << 2) + 0xff620000) ++#define AV_SCRATCH_1 (0x09c1) ++#define P_AV_SCRATCH_1 (volatile unsigned int *)((0x09c1 << 2) + 0xff620000) ++#define AV_SCRATCH_2 (0x09c2) ++#define P_AV_SCRATCH_2 (volatile unsigned int *)((0x09c2 << 2) + 0xff620000) ++#define AV_SCRATCH_3 (0x09c3) ++#define P_AV_SCRATCH_3 (volatile unsigned int *)((0x09c3 << 2) + 0xff620000) ++#define AV_SCRATCH_4 (0x09c4) ++#define P_AV_SCRATCH_4 (volatile unsigned int *)((0x09c4 << 2) + 0xff620000) ++#define AV_SCRATCH_5 (0x09c5) ++#define P_AV_SCRATCH_5 (volatile unsigned int *)((0x09c5 << 2) + 0xff620000) ++#define AV_SCRATCH_6 (0x09c6) ++#define P_AV_SCRATCH_6 (volatile unsigned int *)((0x09c6 << 2) + 0xff620000) ++#define AV_SCRATCH_7 (0x09c7) ++#define P_AV_SCRATCH_7 (volatile unsigned int *)((0x09c7 << 2) + 0xff620000) ++#define AV_SCRATCH_8 (0x09c8) ++#define P_AV_SCRATCH_8 (volatile unsigned int *)((0x09c8 << 2) + 0xff620000) ++#define AV_SCRATCH_9 (0x09c9) ++#define P_AV_SCRATCH_9 (volatile unsigned int *)((0x09c9 << 2) + 0xff620000) ++#define AV_SCRATCH_A (0x09ca) ++#define P_AV_SCRATCH_A (volatile unsigned int *)((0x09ca << 2) + 0xff620000) ++#define AV_SCRATCH_B (0x09cb) ++#define P_AV_SCRATCH_B (volatile unsigned int *)((0x09cb << 2) + 0xff620000) ++#define AV_SCRATCH_C (0x09cc) ++#define P_AV_SCRATCH_C (volatile unsigned int *)((0x09cc << 2) + 0xff620000) ++#define AV_SCRATCH_D (0x09cd) ++#define P_AV_SCRATCH_D (volatile unsigned int *)((0x09cd << 2) + 0xff620000) ++#define AV_SCRATCH_E (0x09ce) ++#define P_AV_SCRATCH_E (volatile unsigned int *)((0x09ce << 2) + 0xff620000) ++#define AV_SCRATCH_F (0x09cf) ++#define P_AV_SCRATCH_F (volatile unsigned int *)((0x09cf << 2) + 0xff620000) ++#define AV_SCRATCH_G (0x09d0) ++#define P_AV_SCRATCH_G (volatile unsigned int *)((0x09d0 << 2) + 0xff620000) ++#define AV_SCRATCH_H (0x09d1) ++#define P_AV_SCRATCH_H (volatile unsigned int *)((0x09d1 << 2) + 0xff620000) ++#define AV_SCRATCH_I (0x09d2) ++#define P_AV_SCRATCH_I (volatile unsigned int *)((0x09d2 << 2) + 0xff620000) ++#define AV_SCRATCH_J (0x09d3) ++#define P_AV_SCRATCH_J (volatile unsigned int *)((0x09d3 << 2) + 0xff620000) ++#define AV_SCRATCH_K (0x09d4) ++#define P_AV_SCRATCH_K (volatile unsigned int *)((0x09d4 << 2) + 0xff620000) ++#define AV_SCRATCH_L (0x09d5) ++#define P_AV_SCRATCH_L (volatile unsigned int *)((0x09d5 << 2) + 0xff620000) ++#define AV_SCRATCH_M (0x09d6) ++#define P_AV_SCRATCH_M (volatile unsigned int *)((0x09d6 << 2) + 0xff620000) ++#define AV_SCRATCH_N (0x09d7) ++#define P_AV_SCRATCH_N (volatile unsigned int *)((0x09d7 << 2) + 0xff620000) ++// bit[29:24] A_brst_num_co_mb ++// bit[21:16] A_id_co_mb ++// bit[11:0] wrrsp_count_co_mb ++#define WRRSP_CO_MB (0x09d8) ++#define P_WRRSP_CO_MB (volatile unsigned int *)((0x09d8 << 2) + 0xff620000) ++// bit[29:24] A_brst_num_dcac ++// bit[21:16] A_id_dcac ++// bit[11:0] wrrsp_count_dcac ++#define WRRSP_DCAC (0x09d9) ++#define P_WRRSP_DCAC (volatile unsigned int *)((0x09d9 << 2) + 0xff620000) ++// bit[11:0] wrrsp_count_vld ++#define WRRSP_VLD (0x09da) ++#define P_WRRSP_VLD (volatile unsigned int *)((0x09da << 2) + 0xff620000) ++// doublew_cfg0[0]; // Second Channel Enable, 1:Enable 0:Disable ++// doublew_cfg0[3:1]; // [2:0] Endian Control for Luma ++// doublew_cfg0[5:4]; // [1:0] Pixel sel by horizontal, 0x:1/2 10:left 11:right ++// doublew_cfg0[7:6]; // [1:0] Pixel sel by vertical, 0x:1/2 10:up 11:down ++// doublew_cfg0[8]; // Size by horizontal, 0:original size 1: 1/2 shrunken size ++// doublew_cfg0[9]; // Size by vertical, 0:original size 1: 1/2 shrunken size ++// doublew_cfg0[10]; // 1:Round 0:Truncation ++// doublew_cfg0[11]; // DMA Urgent ++// doublew_cfg0[17:12]; // [5:0] DMA Burst Number ++// doublew_cfg0[23:18]; // [5:0] DMA ID ++// doublew_cfg0[26:24]; // [2:0] Endian Control for Chroma ++// doublew_cfg0[27]; // Source from, 1:MCW 0:DBLK ++// doublew_cfg0[29:28]; // [1:0] 0x:select both top and bottom 10:select top 11:select bottom ++// doublew_cfg0[30]; // 0:no merge 1:automatic merge ++// doublew_cfg0[31]; // 0:Y addr no change 1:Y addr divided to half ++#define MDEC_DOUBLEW_CFG0 (0x09db) ++#define P_MDEC_DOUBLEW_CFG0 (volatile unsigned int *)((0x09db << 2) + 0xff620000) ++// doublew_cfg1[7:0]; // [7:0] DMA Canvas Address for Luma ++// doublew_cfg1[15:8]; // [7:0] DMA Canvas Address for Chroma ++// doublew_cfg1[16]; // Disable 1st Write - ++// doublew_cfg1[17]; // Reverse to original version - ++// doublew_cfg1[18]; // DMA Address Mode - 0:Canvas Mode 1:Non-Canvas Mode ++#define MDEC_DOUBLEW_CFG1 (0x09dc) ++#define P_MDEC_DOUBLEW_CFG1 (volatile unsigned int *)((0x09dc << 2) + 0xff620000) ++// doublew_cfg2[11:0]; //[11:0] vertical flip initial value ++// doublew_cfg2[15]; // vertical flip enable ++// doublew_cfg2[24:16]; // [8:0] horizontal flip initial value ++// doublew_cfg2[31]; // horizontal flip enable ++#define MDEC_DOUBLEW_CFG2 (0x09dd) ++#define P_MDEC_DOUBLEW_CFG2 (volatile unsigned int *)((0x09dd << 2) + 0xff620000) ++// doublew_cfg3[31:0]; //[31:0] non-canvas start address for Luma - ++#define MDEC_DOUBLEW_CFG3 (0x09de) ++#define P_MDEC_DOUBLEW_CFG3 (volatile unsigned int *)((0x09de << 2) + 0xff620000) ++// doublew_cfg4[31:0]; //[31:0] non-canvas start address for Chroma - ++#define MDEC_DOUBLEW_CFG4 (0x09df) ++#define P_MDEC_DOUBLEW_CFG4 (volatile unsigned int *)((0x09df << 2) + 0xff620000) ++// doublew_cfg5[12:0]; //[12:0] non-canvas picture width for Luma - ++// doublew_cfg5[28:16]; //[12:0] non-canvas picture width for Chroma - ++#define MDEC_DOUBLEW_CFG5 (0x09e0) ++#define P_MDEC_DOUBLEW_CFG5 (volatile unsigned int *)((0x09e0 << 2) + 0xff620000) ++// doublew_cfg6: reserved ++#define MDEC_DOUBLEW_CFG6 (0x09e1) ++#define P_MDEC_DOUBLEW_CFG6 (volatile unsigned int *)((0x09e1 << 2) + 0xff620000) ++// doublew_cfg7: reserved ++#define MDEC_DOUBLEW_CFG7 (0x09e2) ++#define P_MDEC_DOUBLEW_CFG7 (volatile unsigned int *)((0x09e2 << 2) + 0xff620000) ++// doublew_status[11:0];//[11:0] wrrsp_count_doublew ++// doublew_status[12]; // doublew_status_busy ++// doublew_status[13]; // doublew_status_error ++#define MDEC_DOUBLEW_STATUS (0x09e3) ++#define P_MDEC_DOUBLEW_STATUS (volatile unsigned int *)((0x09e3 << 2) + 0xff620000) ++#define MDEC_EXTIF_CFG0 (0x09e4) ++#define P_MDEC_EXTIF_CFG0 (volatile unsigned int *)((0x09e4 << 2) + 0xff620000) ++#define MDEC_EXTIF_CFG1 (0x09e5) ++#define P_MDEC_EXTIF_CFG1 (volatile unsigned int *)((0x09e5 << 2) + 0xff620000) ++#define MDEC_EXTIF_STS0 (0x09e6) ++#define P_MDEC_EXTIF_STS0 (volatile unsigned int *)((0x09e6 << 2) + 0xff620000) ++//====================================== ++// MC Control Register Bits ++// ++//====================================== ++// For bits, just copy the defines...don't translate to addresses ++ #define MC_ENABLE 0x0001 ++ //`define MC_RESET 16'h0002 ++ #define SKIP_MB 0x0004 ++ ++//====================================== ++// MB Info Register Bits ++// ++//====================================== ++ #define INTRA_MB 0x0001 ++ ++ #define BWD_PRED 0x0004 ++ #define FWD_PRED 0x0008 ++ ++ #define FLD_MOT 0x0100 ++ #define FRM_16x8_MOT 0x0200 ++ #define DUAL_PRM_MOT 0x0300 ++ ++ #define FRM_DCT 0x0000 // Bit 10 ++ #define FLD_DCT 0x0400 ++ ++//====================================== ++// MB Info Register Bits ++// ++//====================================== ++ #define I_PIC 0x0001 ++ #define P_PIC 0x0002 ++ #define B_PIC 0x0003 ++ ++ #define FLD_PIC 0x0000 // Bit 8 ++ #define FRM_PIC 0x0100 ++//======================================================================== ++// DBLK Register: 12'h950 - 12'h97f ++//======================================================================== ++#define DBLK_RST (0x0950) ++#define P_DBLK_RST (volatile unsigned int *)((0x0950 << 2) + 0xff620000) ++#define DBLK_CTRL (0x0951) ++#define P_DBLK_CTRL (volatile unsigned int *)((0x0951 << 2) + 0xff620000) ++#define DBLK_MB_WID_HEIGHT (0x0952) ++#define P_DBLK_MB_WID_HEIGHT (volatile unsigned int *)((0x0952 << 2) + 0xff620000) ++#define DBLK_STATUS (0x0953) ++#define P_DBLK_STATUS (volatile unsigned int *)((0x0953 << 2) + 0xff620000) ++#define DBLK_CMD_CTRL (0x0954) ++#define P_DBLK_CMD_CTRL (volatile unsigned int *)((0x0954 << 2) + 0xff620000) ++#define DBLK_MB_XY (0x0955) ++#define P_DBLK_MB_XY (volatile unsigned int *)((0x0955 << 2) + 0xff620000) ++#define DBLK_QP (0x0956) ++#define P_DBLK_QP (volatile unsigned int *)((0x0956 << 2) + 0xff620000) ++#define DBLK_Y_BHFILT (0x0957) ++#define P_DBLK_Y_BHFILT (volatile unsigned int *)((0x0957 << 2) + 0xff620000) ++#define DBLK_Y_BHFILT_HIGH (0x0958) ++#define P_DBLK_Y_BHFILT_HIGH (volatile unsigned int *)((0x0958 << 2) + 0xff620000) ++#define DBLK_Y_BVFILT (0x0959) ++#define P_DBLK_Y_BVFILT (volatile unsigned int *)((0x0959 << 2) + 0xff620000) ++#define DBLK_CB_BFILT (0x095a) ++#define P_DBLK_CB_BFILT (volatile unsigned int *)((0x095a << 2) + 0xff620000) ++#define DBLK_CR_BFILT (0x095b) ++#define P_DBLK_CR_BFILT (volatile unsigned int *)((0x095b << 2) + 0xff620000) ++#define DBLK_Y_HFILT (0x095c) ++#define P_DBLK_Y_HFILT (volatile unsigned int *)((0x095c << 2) + 0xff620000) ++#define DBLK_Y_HFILT_HIGH (0x095d) ++#define P_DBLK_Y_HFILT_HIGH (volatile unsigned int *)((0x095d << 2) + 0xff620000) ++#define DBLK_Y_VFILT (0x095e) ++#define P_DBLK_Y_VFILT (volatile unsigned int *)((0x095e << 2) + 0xff620000) ++#define DBLK_CB_FILT (0x095f) ++#define P_DBLK_CB_FILT (volatile unsigned int *)((0x095f << 2) + 0xff620000) ++#define DBLK_CR_FILT (0x0960) ++#define P_DBLK_CR_FILT (volatile unsigned int *)((0x0960 << 2) + 0xff620000) ++#define DBLK_BETAX_QP_SEL (0x0961) ++#define P_DBLK_BETAX_QP_SEL (volatile unsigned int *)((0x0961 << 2) + 0xff620000) ++#define DBLK_CLIP_CTRL0 (0x0962) ++#define P_DBLK_CLIP_CTRL0 (volatile unsigned int *)((0x0962 << 2) + 0xff620000) ++#define DBLK_CLIP_CTRL1 (0x0963) ++#define P_DBLK_CLIP_CTRL1 (volatile unsigned int *)((0x0963 << 2) + 0xff620000) ++#define DBLK_CLIP_CTRL2 (0x0964) ++#define P_DBLK_CLIP_CTRL2 (volatile unsigned int *)((0x0964 << 2) + 0xff620000) ++#define DBLK_CLIP_CTRL3 (0x0965) ++#define P_DBLK_CLIP_CTRL3 (volatile unsigned int *)((0x0965 << 2) + 0xff620000) ++#define DBLK_CLIP_CTRL4 (0x0966) ++#define P_DBLK_CLIP_CTRL4 (volatile unsigned int *)((0x0966 << 2) + 0xff620000) ++#define DBLK_CLIP_CTRL5 (0x0967) ++#define P_DBLK_CLIP_CTRL5 (volatile unsigned int *)((0x0967 << 2) + 0xff620000) ++#define DBLK_CLIP_CTRL6 (0x0968) ++#define P_DBLK_CLIP_CTRL6 (volatile unsigned int *)((0x0968 << 2) + 0xff620000) ++#define DBLK_CLIP_CTRL7 (0x0969) ++#define P_DBLK_CLIP_CTRL7 (volatile unsigned int *)((0x0969 << 2) + 0xff620000) ++#define DBLK_CLIP_CTRL8 (0x096a) ++#define P_DBLK_CLIP_CTRL8 (volatile unsigned int *)((0x096a << 2) + 0xff620000) ++#define DBLK_STATUS1 (0x096b) ++#define P_DBLK_STATUS1 (volatile unsigned int *)((0x096b << 2) + 0xff620000) ++#define DBLK_GCLK_FREE (0x096c) ++#define P_DBLK_GCLK_FREE (volatile unsigned int *)((0x096c << 2) + 0xff620000) ++#define DBLK_GCLK_OFF (0x096d) ++#define P_DBLK_GCLK_OFF (volatile unsigned int *)((0x096d << 2) + 0xff620000) ++#define DBLK_AVSFLAGS (0x096e) ++#define P_DBLK_AVSFLAGS (volatile unsigned int *)((0x096e << 2) + 0xff620000) ++// bit 15:0 ++#define DBLK_CBPY (0x0970) ++#define P_DBLK_CBPY (volatile unsigned int *)((0x0970 << 2) + 0xff620000) ++// bit 11:8 -- deblk_cbpy_bottom ++// bit 7:4 -- deblk_cbpy_left ++// bit 3:0 -- deblk_cbpy_top ++#define DBLK_CBPY_ADJ (0x0971) ++#define P_DBLK_CBPY_ADJ (volatile unsigned int *)((0x0971 << 2) + 0xff620000) ++// bit 7:0 -- deblk_cbpc ++#define DBLK_CBPC (0x0972) ++#define P_DBLK_CBPC (volatile unsigned int *)((0x0972 << 2) + 0xff620000) ++// bit 15 -- bottom_mb ++// bit 14 -- left_mb ++// bit 13 -- top_mb ++// bit 12 -- reserved ++// bit 11:8 -- deblk_cbpc_bottom ++// bit 7:4 -- deblk_cbpc_left ++// bit 3:0 -- deblk_cbpc_top ++#define DBLK_CBPC_ADJ (0x0973) ++#define P_DBLK_CBPC_ADJ (volatile unsigned int *)((0x0973 << 2) + 0xff620000) ++// bit 15:8 -- deblk_hmvd -- {left_1, left_0, below_1, below_0, block3-0} ++// bit 7:0 -- deblk_vmvd -- {top_1, top_0, below_1, below_0, block3-0} ++#define DBLK_VHMVD (0x0974) ++#define P_DBLK_VHMVD (volatile unsigned int *)((0x0974 << 2) + 0xff620000) ++// bit 13:12 -- right_vmvd ++// bit 11 -- right_above_vmvd ++// bit 10 -- left_below_hmvd ++// bit 9 -- disable_dblk_luma ++// bit 8 -- disable_dblk_chroma ++// bit 7 -- bBelowRefDiff ++// bit 6 -- bLeftRefDiff ++// bit 5 -- bAboveRefDiff ++// bit 4 -- reserved ++// bit 3 -- s_below ++// bit 2 -- s_left ++// bit 1 -- s_above ++// bit 0 -- s ++#define DBLK_STRONG (0x0975) ++#define P_DBLK_STRONG (volatile unsigned int *)((0x0975 << 2) + 0xff620000) ++// bit 14:10 -- PQUANT ++// bit 9:5 -- left_PQUANT ++// bit 4:0 -- top_PQUANT ++#define DBLK_RV8_QUANT (0x0976) ++#define P_DBLK_RV8_QUANT (volatile unsigned int *)((0x0976 << 2) + 0xff620000) ++#define DBLK_CBUS_HCMD2 (0x0977) ++#define P_DBLK_CBUS_HCMD2 (volatile unsigned int *)((0x0977 << 2) + 0xff620000) ++#define DBLK_CBUS_HCMD1 (0x0978) ++#define P_DBLK_CBUS_HCMD1 (volatile unsigned int *)((0x0978 << 2) + 0xff620000) ++#define DBLK_CBUS_HCMD0 (0x0979) ++#define P_DBLK_CBUS_HCMD0 (volatile unsigned int *)((0x0979 << 2) + 0xff620000) ++#define DBLK_VLD_HCMD2 (0x097a) ++#define P_DBLK_VLD_HCMD2 (volatile unsigned int *)((0x097a << 2) + 0xff620000) ++#define DBLK_VLD_HCMD1 (0x097b) ++#define P_DBLK_VLD_HCMD1 (volatile unsigned int *)((0x097b << 2) + 0xff620000) ++#define DBLK_VLD_HCMD0 (0x097c) ++#define P_DBLK_VLD_HCMD0 (volatile unsigned int *)((0x097c << 2) + 0xff620000) ++#define DBLK_OST_YBASE (0x097d) ++#define P_DBLK_OST_YBASE (volatile unsigned int *)((0x097d << 2) + 0xff620000) ++#define DBLK_OST_CBCRDIFF (0x097e) ++#define P_DBLK_OST_CBCRDIFF (volatile unsigned int *)((0x097e << 2) + 0xff620000) ++//13:8 dblk thread ID and token ++//5:0 dblk prearbitor burst num ++#define DBLK_CTRL1 (0x097f) ++#define P_DBLK_CTRL1 (volatile unsigned int *)((0x097f << 2) + 0xff620000) ++// MCRCC_CTL1 ++// 31:3 ++// 2 ++// 1 ++// 0 ++#define MCRCC_CTL1 (0x0980) ++#define P_MCRCC_CTL1 (volatile unsigned int *)((0x0980 << 2) + 0xff620000) ++// MCRCC_CTL2 ++// 31:24 ++// 23:16 ++// 15:8 ++// 7:0 ++#define MCRCC_CTL2 (0x0981) ++#define P_MCRCC_CTL2 (volatile unsigned int *)((0x0981 << 2) + 0xff620000) ++// MCRCC_CTL3 ++// 31:24 ++// 23:16 ++// 15:8 ++// 7:0 ++#define MCRCC_CTL3 (0x0982) ++#define P_MCRCC_CTL3 (volatile unsigned int *)((0x0982 << 2) + 0xff620000) ++// bit[31:10] reserved ++// bit[9:0] sw_clock_gating control ++// [9] vdec clk_en for assist and cbus. ++// [8] vdec clk_en for ddr ++// [7] vdec clk_en for vcpu ++// [6] vdec clk_en for assist ++// [5] vdec clk_en for dblk ++// [4] vdec clk_en for iqidct ++// [3] vdec clk_en for mc ++// [2] vdec clk_en for pic_dc ++// [1] vdec clk_en for psc ++// [0] vdec clk_en for vld ++#define GCLK_EN (0x0983) ++#define P_GCLK_EN (volatile unsigned int *)((0x0983 << 2) + 0xff620000) ++// [0] Reserved ++// [1] Reserved ++// [2] Reset assist, mdec's CBUS ++// [3] Reset mdec's VLD ++// [4] Reset mdec's VLD ++// [5] Reset mdec's VLD ++// [6] Reset mdec's IQIDCT ++// [7] Reset mdec's MC ++// [8] Reset mdec's DBLK ++// [9] Reset mdec's PIC_DC ++// [10] Reset mdec's Pscale ++// [11] Reset vcpu's MCPU ++// [12] Reset vcpu's CCPU ++// [13] Reset mmc_pre_arb ++#define MDEC_SW_RESET (0x0984) ++#define P_MDEC_SW_RESET (volatile unsigned int *)((0x0984 << 2) + 0xff620000) ++//DBLK last address 12'h97f ++// ++// Closing file: mdec_regs.h ++// ++//------------------------------------------------------------------------------ ++// VLD module level register offset ++//------------------------------------------------------------------------------ ++// ++// Reading file: vld_regs.h ++// ++//======================================================================== ++// VLD module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_VDEC_VLD_CBUS_BASE = 0x0c ++// ----------------------------------------------- ++#define VLD_STATUS_CTRL (0x0c00) ++#define P_VLD_STATUS_CTRL (volatile unsigned int *)((0x0c00 << 2) + 0xff620000) ++// ++// bit 10 -- use_old_shift_en ++// bit 9 -- output_mv_not_pmv ++// bit 8:5 -- force_zigzag ++// bit 4 -- force_zigzag_en ++// bit 3 -- disable_viff_anempty_int ++// bit 2 -- disable_m2_ac_coeff_one_cycle ++// bit 1 -- forced_reset force reset pmv ++// bit 0 -- mpeg_type 0:mpeg1 1: mpeg2 ++#define MPEG1_2_REG (0x0c01) ++#define P_MPEG1_2_REG (volatile unsigned int *)((0x0c01 << 2) + 0xff620000) ++#define F_CODE_REG (0x0c02) ++#define P_F_CODE_REG (volatile unsigned int *)((0x0c02 << 2) + 0xff620000) ++#define PIC_HEAD_INFO (0x0c03) ++#define P_PIC_HEAD_INFO (volatile unsigned int *)((0x0c03 << 2) + 0xff620000) ++#define SLICE_VER_POS_PIC_TYPE (0x0c04) ++#define P_SLICE_VER_POS_PIC_TYPE (volatile unsigned int *)((0x0c04 << 2) + 0xff620000) ++#define QP_VALUE_REG (0x0c05) ++#define P_QP_VALUE_REG (volatile unsigned int *)((0x0c05 << 2) + 0xff620000) ++#define MBA_INC (0x0c06) ++#define P_MBA_INC (volatile unsigned int *)((0x0c06 << 2) + 0xff620000) ++#define MB_MOTION_MODE (0x0c07) ++#define P_MB_MOTION_MODE (volatile unsigned int *)((0x0c07 << 2) + 0xff620000) ++//`define PACKET_BYTE_COUNT 8'h08 ++// bit 15 -- force_search_startcode_en ++// bit 14 -- int_cpu_when_error (before do anything) ++// bit 13 -- vld_error_reset ++// bit 12 -- return_on_slice_header ++// bit 6 -- jpeg_ff00_en ++// bit 5:0 -- vld_power_ctl ++#define POWER_CTL_VLD (0x0c08) ++#define P_POWER_CTL_VLD (volatile unsigned int *)((0x0c08 << 2) + 0xff620000) ++#define MB_WIDTH (0x0c09) ++#define P_MB_WIDTH (volatile unsigned int *)((0x0c09 << 2) + 0xff620000) ++#define SLICE_QP (0x0c0a) ++#define P_SLICE_QP (volatile unsigned int *)((0x0c0a << 2) + 0xff620000) ++// `define MB_X_MB_Y 8'h0b /* current MBX and MBY */ ++#define PRE_START_CODE (0x0c0b) ++#define P_PRE_START_CODE (volatile unsigned int *)((0x0c0b << 2) + 0xff620000) ++#define SLICE_START_BYTE_01 (0x0c0c) ++#define P_SLICE_START_BYTE_01 (volatile unsigned int *)((0x0c0c << 2) + 0xff620000) ++#define SLICE_START_BYTE_23 (0x0c0d) ++#define P_SLICE_START_BYTE_23 (volatile unsigned int *)((0x0c0d << 2) + 0xff620000) ++#define RESYNC_MARKER_LENGTH (0x0c0e) ++#define P_RESYNC_MARKER_LENGTH (volatile unsigned int *)((0x0c0e << 2) + 0xff620000) ++// bit[6:5] - frame/field info, 01 - top, 10 - bottom, 11 - frame ++// bit[4:0] - buffer ID ++// L0_BUFF_ID_0, L0_BUFF_ID_1, L1_BUFF_ID_0, L1_BUFF_ID_1 ++#define DECODER_BUFFER_INFO (0x0c0f) ++#define P_DECODER_BUFFER_INFO (volatile unsigned int *)((0x0c0f << 2) + 0xff620000) ++#define FST_FOR_MV_X (0x0c10) ++#define P_FST_FOR_MV_X (volatile unsigned int *)((0x0c10 << 2) + 0xff620000) ++#define FST_FOR_MV_Y (0x0c11) ++#define P_FST_FOR_MV_Y (volatile unsigned int *)((0x0c11 << 2) + 0xff620000) ++#define SCD_FOR_MV_X (0x0c12) ++#define P_SCD_FOR_MV_X (volatile unsigned int *)((0x0c12 << 2) + 0xff620000) ++#define SCD_FOR_MV_Y (0x0c13) ++#define P_SCD_FOR_MV_Y (volatile unsigned int *)((0x0c13 << 2) + 0xff620000) ++#define FST_BAK_MV_X (0x0c14) ++#define P_FST_BAK_MV_X (volatile unsigned int *)((0x0c14 << 2) + 0xff620000) ++#define FST_BAK_MV_Y (0x0c15) ++#define P_FST_BAK_MV_Y (volatile unsigned int *)((0x0c15 << 2) + 0xff620000) ++#define SCD_BAK_MV_X (0x0c16) ++#define P_SCD_BAK_MV_X (volatile unsigned int *)((0x0c16 << 2) + 0xff620000) ++#define SCD_BAK_MV_Y (0x0c17) ++#define P_SCD_BAK_MV_Y (volatile unsigned int *)((0x0c17 << 2) + 0xff620000) ++// Bit 7:4 -- read_buffer_interlace 0-progressive, 1-interlace, used in VC1 ++// bit 3 -- disable_new_stcode_search_fix // From GXM ++// bit 2 -- weighting_prediction ++// bit 1 -- mb_weighting_flag ++// bit 0 -- slice_weighting_flag ++#define VLD_DECODE_CONTROL (0x0c18) ++#define P_VLD_DECODE_CONTROL (volatile unsigned int *)((0x0c18 << 2) + 0xff620000) ++#define VLD_REVERVED_19 (0x0c19) ++#define P_VLD_REVERVED_19 (volatile unsigned int *)((0x0c19 << 2) + 0xff620000) ++#define VIFF_BIT_CNT (0x0c1a) ++#define P_VIFF_BIT_CNT (volatile unsigned int *)((0x0c1a << 2) + 0xff620000) ++#define BYTE_ALIGN_PEAK_HI (0x0c1b) ++#define P_BYTE_ALIGN_PEAK_HI (volatile unsigned int *)((0x0c1b << 2) + 0xff620000) ++#define BYTE_ALIGN_PEAK_LO (0x0c1c) ++#define P_BYTE_ALIGN_PEAK_LO (volatile unsigned int *)((0x0c1c << 2) + 0xff620000) ++#define NEXT_ALIGN_PEAK (0x0c1d) ++#define P_NEXT_ALIGN_PEAK (volatile unsigned int *)((0x0c1d << 2) + 0xff620000) ++// bit 31 : byte_aligned_zero_23_from_org // From GXM ++// bit 30 : force_shift_out_drop_flag_zero // From GXM ++// bit 29 : en_st_protect_from_org // From GXM ++// bit 28 : enable_halt_decode_start_voff ++// bit 27 : disable_C_pred_check ++// bit 26 : disable_I4_pred_check ++// bit 25 : disable_I16_pred_check ++// bit 24 : check_avs_1st_drop ++// bit 23 : enable_cabac_protect // From GXM ++// bit 22 : enable_avs_drop_more ++// bit 21 : reset_avs_drop_ptr ++// bit 20 : reset_cabac_use_next_at_end_req ++// bit 19 : vc1_inv_intra_co_mb_ref_rd ++// bit 18 : vc1_inv_co_mb_ref_rd ++// bit 17 : vc1_inv_intra_co_mb_ref_wr ++// bit 16 : vc1_inv_co_mb_ref_wr ++// bit 15 : disable_mv_cal_begin_only ++// bit 14 : avs_drop_enable ++// bit 13:12 : avs_drop_ptr ++// bit 11:8 : avs_demu_ctl_reg ++// bit 7 : avs_enable ++// bit 6 : disable_dblk_hcmd ++// bit 5 : disable_mc_hcmd ++// bit 4 : first_mode3_set enable ++// bit 3 : first_mode3 ++// bit 2:1 : vc1_profile 0-SP, 1-MP, 2-reserved, 3-AP ++// bit 0 : vc1_enable ++#define VC1_CONTROL_REG (0x0c1e) ++#define P_VC1_CONTROL_REG (volatile unsigned int *)((0x0c1e << 2) + 0xff620000) ++#define PMV1_X (0x0c20) ++#define P_PMV1_X (volatile unsigned int *)((0x0c20 << 2) + 0xff620000) ++#define PMV1_Y (0x0c21) ++#define P_PMV1_Y (volatile unsigned int *)((0x0c21 << 2) + 0xff620000) ++#define PMV2_X (0x0c22) ++#define P_PMV2_X (volatile unsigned int *)((0x0c22 << 2) + 0xff620000) ++#define PMV2_Y (0x0c23) ++#define P_PMV2_Y (volatile unsigned int *)((0x0c23 << 2) + 0xff620000) ++#define PMV3_X (0x0c24) ++#define P_PMV3_X (volatile unsigned int *)((0x0c24 << 2) + 0xff620000) ++#define PMV3_Y (0x0c25) ++#define P_PMV3_Y (volatile unsigned int *)((0x0c25 << 2) + 0xff620000) ++#define PMV4_X (0x0c26) ++#define P_PMV4_X (volatile unsigned int *)((0x0c26 << 2) + 0xff620000) ++#define PMV4_Y (0x0c27) ++#define P_PMV4_Y (volatile unsigned int *)((0x0c27 << 2) + 0xff620000) ++// Can't use the same address for different defines ++// Therefore, create a single define that covers both ++// Only appears to be used in micro-code since the VLD hardware is ++// hard coded. ++// `define M4_TABLE_SELECT 8'h28 // Does this exist in HW ? Added from register_mp2.h ++// `define M4_TABLE_OUTPUT 8'h28 // Does this exist in HW ? Added from register_mp2.h ++#define M4_TABLE_SELECT (0x0c28) ++#define P_M4_TABLE_SELECT (volatile unsigned int *)((0x0c28 << 2) + 0xff620000) ++#define M4_CONTROL_REG (0x0c29) ++#define P_M4_CONTROL_REG (volatile unsigned int *)((0x0c29 << 2) + 0xff620000) ++#define BLOCK_NUM (0x0c2a) ++#define P_BLOCK_NUM (volatile unsigned int *)((0x0c2a << 2) + 0xff620000) ++#define PATTERN_CODE (0x0c2b) ++#define P_PATTERN_CODE (volatile unsigned int *)((0x0c2b << 2) + 0xff620000) ++#define MB_INFO (0x0c2c) ++#define P_MB_INFO (volatile unsigned int *)((0x0c2c << 2) + 0xff620000) ++#define VLD_DC_PRED (0x0c2d) ++#define P_VLD_DC_PRED (volatile unsigned int *)((0x0c2d << 2) + 0xff620000) ++#define VLD_ERROR_MASK (0x0c2e) ++#define P_VLD_ERROR_MASK (volatile unsigned int *)((0x0c2e << 2) + 0xff620000) ++#define VLD_DC_PRED_C (0x0c2f) ++#define P_VLD_DC_PRED_C (volatile unsigned int *)((0x0c2f << 2) + 0xff620000) ++#define LAST_SLICE_MV_ADDR (0x0c30) ++#define P_LAST_SLICE_MV_ADDR (volatile unsigned int *)((0x0c30 << 2) + 0xff620000) ++#define LAST_MVX (0x0c31) ++#define P_LAST_MVX (volatile unsigned int *)((0x0c31 << 2) + 0xff620000) ++#define LAST_MVY (0x0c32) ++#define P_LAST_MVY (volatile unsigned int *)((0x0c32 << 2) + 0xff620000) ++#define VLD_C38 (0x0c38) ++#define P_VLD_C38 (volatile unsigned int *)((0x0c38 << 2) + 0xff620000) ++#define VLD_C39 (0x0c39) ++#define P_VLD_C39 (volatile unsigned int *)((0x0c39 << 2) + 0xff620000) ++#define VLD_STATUS (0x0c3a) ++#define P_VLD_STATUS (volatile unsigned int *)((0x0c3a << 2) + 0xff620000) ++#define VLD_SHIFT_STATUS (0x0c3b) ++#define P_VLD_SHIFT_STATUS (volatile unsigned int *)((0x0c3b << 2) + 0xff620000) ++// `define VLD_SHIFT_INFO 8'h3b // Does this exist in HW ? used in $ucode/mpeg4 ++#define VOFF_STATUS (0x0c3c) ++#define P_VOFF_STATUS (volatile unsigned int *)((0x0c3c << 2) + 0xff620000) ++#define VLD_C3D (0x0c3d) ++#define P_VLD_C3D (volatile unsigned int *)((0x0c3d << 2) + 0xff620000) ++#define VLD_DBG_INDEX (0x0c3e) ++#define P_VLD_DBG_INDEX (volatile unsigned int *)((0x0c3e << 2) + 0xff620000) ++// vld_buff_info -- (index == 0) ++// Bit11] halt_decode_start_voff ++// Bit10] C_pred_error ++// Bit[9] I4_pred_error ++// Bit[8] I16_pred_error ++// Bit[7:6] mv_UR_ready_cnt; ++// Bit[5] vld_wr_idx ++// Bit[4] iq_rd_idx ++// Bit[3] vld_vi_block_rdy_1 ++// Bit[2] vld_vi_block_rdy_2 ++// Bit[1] voff_empty_1 ++// Bit[0] voff_empty_2 ++// cabac_buff_info_0 -- (index == 1) ++// Bit[31] shift_data_ready ++// Bit[30:29] Reserved ++// Bit[28:24] cabac_buffer_ptr ++// Bit[23:0] cabac_buffer ++// cabac_buff_info_1 -- (index == 2) ++// Bit[31:29] Reserved ++// Bit[28:20] Drange ++// Bit[19:16] bin_count_4 ++// Bit[15:13] Reserved ++// Bit[12:6] context_mem_do ++// Bit[5:3] coeff_state ++// Bit[2:0] mvd_state ++// h264_mv_present -- (index == 3) ++// Bit[31:16] mv_present_l0 ++// Bit[15:0] mv_present_l1 ++// h264_mv_cal_info_0 -- (index == 4) ++// [31:28] mv_cal_state ++// [27:24] direct_spatial_cnt ++// Bit[23:21] Reserved ++// Bit[20] mv_UR_ready_for_mv_cal ++// Bit[19] co_mb_mem_ready_for_mv_cal ++// Bit[18] mc_dblk_cmd_if_busy ++// Bit[17] h264_co_mb_wr_busy ++// Bit[16] H264_cbp_blk_ready ++// Bit[15] mc_hcmd_rrdy ++// Bit[14] mc_hcmd_srdy ++// Bit[13] mc_cmd_if_ready ++// Bit[12] mc_hcmd_mv_available ++// Bit[11:8] mc_cmd_if_state ++// Bit[7] dblk_hcmd_rrdy ++// Bit[6] dblk_hcmd_srdy ++// Bit[5] dblk_cmd_if_ready ++// Bit[4] dblk_hcmd_mv_available ++// Bit[3:0] dblk_cmd_if_state ++// h264_mv_cal_info_1 -- (index == 5) ++// Bit[31:29] Reserved ++// Bit[28:24] total_mvd_num_l0 ++// Bit[23:21] Reserved ++// Bit[20:16] mv_cal_ptr_l0 ++// Bit[15:13] Reserved ++// Bit[12:8] mc_hcmd_ptr_l0 ++// Bit[7:5] Reserved ++// Bit[4:0] dblk_hcmd_ptr_l0 ++// h264_mv_cal_info_2 -- (index == 6) ++// Bit[31:29] Reserved ++// Bit[28:24] total_mvd_num_l1 ++// Bit[23:21] Reserved ++// Bit[20:16] mv_cal_ptr_l1 ++// Bit[15:13] Reserved ++// Bit[12:8] mc_hcmd_ptr_l1 ++// Bit[7:5] Reserved ++// Bit[4:0] dblk_hcmd_ptr_l1 ++// h264_co_mb_info -- (index == 7) ++// Bit[31:26] Reserved ++// Bit[25] mv_scale_cal_busy ++// Bit[24:20] co_mv_count ++// Bit[19:16] co_mv_process_state ++// Bit[15] h264_co_mb_rd_busy ++// Bit[15] h264_co_mb_rd_ready ++// Bit[13:12] co_mv_transfer_block_cnt ++// Bit[11:8] co_mv_transfer_ptr ++// Bit[7] co_mv_POC_l1_busy ++// Bit[6] h264_weight_scale_cal_en ++// Bit[5] weight_cal_busy ++// Bit[4] weight_cal_not_finished ++// Bit[3:0] weight_process_state ++#define VLD_DBG_DATA (0x0c3f) ++#define P_VLD_DBG_DATA (volatile unsigned int *)((0x0c3f << 2) + 0xff620000) ++// -------------------------------------------- ++// VIFIFO DDR Interface ++// -------------------------------------------- ++// The VIFIFO start pointer into DDR memory is a 32-bit number ++// The Start pointer will automatically be truncated to land on ++// an 8-byte boundary. That is, bits [2:0] = 0; ++#define VLD_MEM_VIFIFO_START_PTR (0x0c40) ++#define P_VLD_MEM_VIFIFO_START_PTR (volatile unsigned int *)((0x0c40 << 2) + 0xff620000) ++// The current pointer points so some location between the START and END ++// pointers. The current pointer is a BYTE pointer. That is, you can ++// point to any BYTE address within the START/END range ++#define VLD_MEM_VIFIFO_CURR_PTR (0x0c41) ++#define P_VLD_MEM_VIFIFO_CURR_PTR (volatile unsigned int *)((0x0c41 << 2) + 0xff620000) ++#define VLD_MEM_VIFIFO_END_PTR (0x0c42) ++#define P_VLD_MEM_VIFIFO_END_PTR (volatile unsigned int *)((0x0c42 << 2) + 0xff620000) ++#define VLD_MEM_VIFIFO_BYTES_AVAIL (0x0c43) ++#define P_VLD_MEM_VIFIFO_BYTES_AVAIL (volatile unsigned int *)((0x0c43 << 2) + 0xff620000) ++// VIFIFO FIFO Control ++// bit [31:24] viff_empty_int_enable_cpu[7:0] ++// bit [23:16] viff_empty_int_enable_amrisc[7:0] ++// -bit 23 Video BUFFER < 0x400 Bytes ++// -bit 22 Video BUFFER < 0x200 Bytes ++// -bit 21 Video BUFFER < 0x100 Bytes ++// -bit 20 Video BUFFER < 0x80 Bytes ++// -bit 19 Video BUFFER < 0x40 Bytes ++// -bit 18 Video BUFFER < 0x20 Bytes ++// -bit 17 vififo < 16 double words ++// -bit 16 vififo < 8 double words ++// bit [15:13] unused ++// bit [12] A_urgent ++// bit [11] transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request ++// bit [10] use_level Set this bit to 1 to enable filling of the FIFO controlled by the buffer ++// level control. If this bit is 0, then use bit[1] to control the enabling of filling ++// bit [9] Data Ready. This bit is set when data can be popped ++// bit [8] fill busy This bit will be high when we're fetching data from the DDR memory ++// To reset this module, set cntl_enable = 0, and then wait for busy = 0. ++// After that you can pulse cntl_init to start over ++// bit [7] init_with_cntl_init ++// bit [6] reserved ++// bits [5:3] endian: see $lib/rtl/ddr_endian.v ++// bit [2] cntl_empty_en Set to 1 to enable reading the DDR memory FIFO ++// Set cntl_empty_en = cntl_fill_en = 0 when pulsing cntl_init ++// bit [1] cntl_fill_en Set to 1 to enable reading data from DDR memory ++// bit [0] cntl_init: After setting the read pointers, sizes, channel masks ++// and read masks, set this bit to 1 and then to 0 ++// NOTE: You don't need to pulse cntl_init if only the start address is ++// being changed ++#define VLD_MEM_VIFIFO_CONTROL (0x0c44) ++#define P_VLD_MEM_VIFIFO_CONTROL (volatile unsigned int *)((0x0c44 << 2) + 0xff620000) ++// -------------------------------------------- ++// VIFIFO Buffer Level Manager ++// -------------------------------------------- ++#define VLD_MEM_VIFIFO_WP (0x0c45) ++#define P_VLD_MEM_VIFIFO_WP (volatile unsigned int *)((0x0c45 << 2) + 0xff620000) ++#define VLD_MEM_VIFIFO_RP (0x0c46) ++#define P_VLD_MEM_VIFIFO_RP (volatile unsigned int *)((0x0c46 << 2) + 0xff620000) ++#define VLD_MEM_VIFIFO_LEVEL (0x0c47) ++#define P_VLD_MEM_VIFIFO_LEVEL (volatile unsigned int *)((0x0c47 << 2) + 0xff620000) ++// ++// bit [8] use_parser_video2_wp ++// bit [7] vbuf2_out_manual ++// bit [6] vbuf_out_manual ++// bit [5] empty (ReadOnly) ++// bit [4] full (ReadOnly) ++// bit [3:2] reserved ++// bit [1] manual mode Set to 1 for manual write pointer mode ++// bit [0] Init Set high then low after everything has been initialized ++#define VLD_MEM_VIFIFO_BUF_CNTL (0x0c48) ++#define P_VLD_MEM_VIFIFO_BUF_CNTL (volatile unsigned int *)((0x0c48 << 2) + 0xff620000) ++// bit 31:16 -- drop_bytes ++// bit 15:14 -- drop_status (Read-Only) ++// bit 13:12 -- sync_match_position (Read-Only) ++// bit 11:6 -- reserved ++// bit 5:4 -- TIME_STAMP_NUMBER, 0-32bits, 1-64bits, 2-96bits, 3-128bits ++// bit 3 -- stamp_soft_reset ++// bit 2 -- TIME_STAMP_length_enable ++// bit 1 -- TIME_STAMP_sync64_enable ++// bit 0 -- TIME_STAMP_enable ++#define VLD_TIME_STAMP_CNTL (0x0c49) ++#define P_VLD_TIME_STAMP_CNTL (volatile unsigned int *)((0x0c49 << 2) + 0xff620000) ++// bit 31:0 -- TIME_STAMP_SYNC_CODE_0 ++#define VLD_TIME_STAMP_SYNC_0 (0x0c4a) ++#define P_VLD_TIME_STAMP_SYNC_0 (volatile unsigned int *)((0x0c4a << 2) + 0xff620000) ++// bit 31:0 -- TIME_STAMP_SYNC_CODE_1 ++#define VLD_TIME_STAMP_SYNC_1 (0x0c4b) ++#define P_VLD_TIME_STAMP_SYNC_1 (volatile unsigned int *)((0x0c4b << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_0 ++#define VLD_TIME_STAMP_0 (0x0c4c) ++#define P_VLD_TIME_STAMP_0 (volatile unsigned int *)((0x0c4c << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_1 ++#define VLD_TIME_STAMP_1 (0x0c4d) ++#define P_VLD_TIME_STAMP_1 (volatile unsigned int *)((0x0c4d << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_2 ++#define VLD_TIME_STAMP_2 (0x0c4e) ++#define P_VLD_TIME_STAMP_2 (volatile unsigned int *)((0x0c4e << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_3 ++#define VLD_TIME_STAMP_3 (0x0c4f) ++#define P_VLD_TIME_STAMP_3 (volatile unsigned int *)((0x0c4f << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_LENGTH ++#define VLD_TIME_STAMP_LENGTH (0x0c50) ++#define P_VLD_TIME_STAMP_LENGTH (volatile unsigned int *)((0x0c50 << 2) + 0xff620000) ++// bit 15:0 vififo_rd_count ++#define VLD_MEM_VIFIFO_WRAP_COUNT (0x0c51) ++#define P_VLD_MEM_VIFIFO_WRAP_COUNT (volatile unsigned int *)((0x0c51 << 2) + 0xff620000) ++// bit 29:24 A_brst_num ++// bit 21:16 A_id ++// bit 15:0 level_hold ++#define VLD_MEM_VIFIFO_MEM_CTL (0x0c52) ++#define P_VLD_MEM_VIFIFO_MEM_CTL (volatile unsigned int *)((0x0c52 << 2) + 0xff620000) ++#define VLD_MEM_VBUF_RD_PTR (0x0c53) ++#define P_VLD_MEM_VBUF_RD_PTR (volatile unsigned int *)((0x0c53 << 2) + 0xff620000) ++#define VLD_MEM_VBUF2_RD_PTR (0x0c54) ++#define P_VLD_MEM_VBUF2_RD_PTR (volatile unsigned int *)((0x0c54 << 2) + 0xff620000) ++#define VLD_MEM_SWAP_ADDR (0x0c55) ++#define P_VLD_MEM_SWAP_ADDR (volatile unsigned int *)((0x0c55 << 2) + 0xff620000) ++// bit[23:16] - swap_d_count (Read Only) ++// bit[15:8] - swap_a_count (Read Only) ++// bit [7] - swap busy (Read Only) ++// bit [6:2] - reserved ++// bit [1] - 1 - STORE to Memory, 0 - LOAD from Memory ++// bit [0] - swap active ++#define VLD_MEM_SWAP_CTL (0x0c56) ++#define P_VLD_MEM_SWAP_CTL (volatile unsigned int *)((0x0c56 << 2) + 0xff620000) ++// ++// Closing file: vld_regs.h ++// ++//------------------------------------------------------------------------------ ++// IQ/IDCT module level register offset ++//------------------------------------------------------------------------------ ++// ++// Reading file: iqidct_regs.h ++// ++//======================================================================== ++// IQ/IDCT module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_VDEC_IQIDCT_CBUS_BASE = 0x0e ++// ----------------------------------------------- ++#define VCOP_CTRL_REG (0x0e00) ++#define P_VCOP_CTRL_REG (volatile unsigned int *)((0x0e00 << 2) + 0xff620000) ++#define QP_CTRL_REG (0x0e01) ++#define P_QP_CTRL_REG (volatile unsigned int *)((0x0e01 << 2) + 0xff620000) ++#define INTRA_QUANT_MATRIX (0x0e02) ++#define P_INTRA_QUANT_MATRIX (volatile unsigned int *)((0x0e02 << 2) + 0xff620000) ++#define NON_I_QUANT_MATRIX (0x0e03) ++#define P_NON_I_QUANT_MATRIX (volatile unsigned int *)((0x0e03 << 2) + 0xff620000) ++#define DC_SCALER (0x0e04) ++#define P_DC_SCALER (volatile unsigned int *)((0x0e04 << 2) + 0xff620000) ++#define DC_AC_CTRL (0x0e05) ++#define P_DC_AC_CTRL (volatile unsigned int *)((0x0e05 << 2) + 0xff620000) ++// `define RV_AI_CTRL 8'h05 // ONLY for $ucode/real/amrisc/rv.s reg value from apollo ++#define DC_AC_SCALE_MUL (0x0e06) ++#define P_DC_AC_SCALE_MUL (volatile unsigned int *)((0x0e06 << 2) + 0xff620000) ++#define DC_AC_SCALE_DIV (0x0e07) ++#define P_DC_AC_SCALE_DIV (volatile unsigned int *)((0x0e07 << 2) + 0xff620000) ++// `define DC_AC_SCALE_RESULT 8'h06 ++// `define RESERVED_E07 8'h07 ++#define POWER_CTL_IQIDCT (0x0e08) ++#define P_POWER_CTL_IQIDCT (volatile unsigned int *)((0x0e08 << 2) + 0xff620000) ++#define RV_AI_Y_X (0x0e09) ++#define P_RV_AI_Y_X (volatile unsigned int *)((0x0e09 << 2) + 0xff620000) ++#define RV_AI_U_X (0x0e0a) ++#define P_RV_AI_U_X (volatile unsigned int *)((0x0e0a << 2) + 0xff620000) ++#define RV_AI_V_X (0x0e0b) ++#define P_RV_AI_V_X (volatile unsigned int *)((0x0e0b << 2) + 0xff620000) ++// bit 15:0 will count up when rv_ai_mb finished when non zero ++// and rv_ai_mb_finished_int will be generate when this is not zero ++#define RV_AI_MB_COUNT (0x0e0c) ++#define P_RV_AI_MB_COUNT (volatile unsigned int *)((0x0e0c << 2) + 0xff620000) ++// For H264 I in PB picture Use -- dma type : h264_next_intra_dma ++#define NEXT_INTRA_DMA_ADDRESS (0x0e0d) ++#define P_NEXT_INTRA_DMA_ADDRESS (volatile unsigned int *)((0x0e0d << 2) + 0xff620000) ++// Bit 16 -- dcac_dma_read_cache_disable ++// Bit 15 -- dcac_dma_urgent ++// Bit 14 -- nv21_swap ++// Bit 13 -- nv21_top_dma ++// Bit 12 -- reset_rv_ai_wait_rd_data ++// Bit 11 -- set_rv_ai_wait_rd_data [12:11] = 3 means only dec 1 (For Skipped MB of MBAFF) ++// Bit 10 -- rv_ai_wait_rd_data (Read Only) ++// Bit 9 -- enable_rv_ai_wait_rd_data ++// Bit 8 -- disable_vc1_mv_update ++// Bit 7 -- pred_dc_signed ++// Bit 6 -- inc_vld_ready_count ++// Bit 5 -- dec_vld_ready_count ++// Bit 4 -- disable_ref_bidir_fix ++// Bit 3 -- disable_MV_UL_l1_bot_fix ++// Bit 2 -- disable_mb_aff_fix ++// Bit 1 -- canvas_addr_7 ++// Bit 0 -- constrained_intra_pred_flag for H264 ++#define IQIDCT_CONTROL (0x0e0e) ++#define P_IQIDCT_CONTROL (volatile unsigned int *)((0x0e0e << 2) + 0xff620000) ++// Bit[31:19] Reserved ++// Bit[18] iq_waiting ++// Bit[17] iq_om_wr_idx ++// Bit[16] iq_om_rd_idx ++// Bit[15] iq_om_busy ++// Bit[14] iq_om_2_busy ++// Bit[13] idx_fifo_0 ++// Bit[12] idx_fifo_1 ++// Bit[11] idx_fifo_2 ++// Bit[10] idx_fifo_3 ++// Bit[9] idx_fifo_4 ++// Bit[8] idx_fifo_5 ++// Bit[7] idx_fifo_6 ++// Bit[6] idx_fifo_7 ++// Bit[5:3] idx_fifo_wp ++// Bit[2:0] idx_fifo_rp ++#define IQIDCT_DEBUG_INFO_0 (0x0e0f) ++#define P_IQIDCT_DEBUG_INFO_0 (volatile unsigned int *)((0x0e0f << 2) + 0xff620000) ++// For RTL Simulation Only ++#define DEBLK_CMD (0x0e10) ++#define P_DEBLK_CMD (volatile unsigned int *)((0x0e10 << 2) + 0xff620000) ++// Bit[15+16] ds_mc_valid_2 ++// Bit[14+16] new_idct1_rd_idx_2 ++// Bit[13+16] new_idct1_wr_idx_2 ++// Bit[12+16] idct1_buff0_busy_2 ++// Bit[11+16] idct1_buff1_busy_2 ++// Bit[10+16] new_idct1_busy_2 ++// Bit[9+16] iq_om_8val_2 ++// Bit[8+16] idct1_pipe_busy_2 ++// Bit[7+16] wait_mb_left_finish_hold_2 ++// Bit[6+16] new_idct2_rd_idx_2 ++// Bit[5+16] new_idct2_wr_idx_2 ++// Bit[4+16] idct2_buff0_busy_2 ++// Bit[3+16] idct2_buff1_busy_2 ++// Bit[2+16] idct2_en_2 ++// Bit[1+16] new_idct2_busy_2 ++// Bit[0+16] new_idct1_ready_2 ++// Bit[15] ds_mc_valid_1 ++// Bit[14] new_idct1_rd_idx_1 ++// Bit[13] new_idct1_wr_idx_1 ++// Bit[12] idct1_buff0_busy_1 ++// Bit[11] idct1_buff1_busy_1 ++// Bit[10] new_idct1_busy_1 ++// Bit[9] iq_om_8val_1 ++// Bit[8] idct1_pipe_busy_1 ++// Bit[7] wait_mb_left_finish_hold_1 ++// Bit[6] new_idct2_rd_idx_1 ++// Bit[5] new_idct2_wr_idx_1 ++// Bit[4] idct2_buff0_busy_1 ++// Bit[3] idct2_buff1_busy_1 ++// Bit[2] idct2_en_1 ++// Bit[1] new_idct2_busy_1 ++// Bit[0] new_idct1_ready_1 ++#define IQIDCT_DEBUG_IDCT (0x0e11) ++#define P_IQIDCT_DEBUG_IDCT (volatile unsigned int *)((0x0e11 << 2) + 0xff620000) ++// bit 31 -- convas_enable ++// bit 30:24 -- convas_x_count ( 8 pixels / 64 bits ) ++// bit 23:16 -- convas_y_count ++// bit 15 -- dcac_dma_busy ++// bit 14 -- dcac_dma_read_cache_active ++// bit 13:8 -- dcac_dma_count ++// bit 7 -- dcac_dma_rw ++// bit 6 -- dcac_skip_read_mode ++// bit 5:0 -- dcac_dma_offset ++#define DCAC_DMA_CTRL (0x0e12) ++#define P_DCAC_DMA_CTRL (volatile unsigned int *)((0x0e12 << 2) + 0xff620000) ++// when (convas_enable == 0 ) ++// bit 31:0 dcac_dma_addr ++// when (convas_enable == 1 ) ++// bit 31:25 canvas_addr (7 bits) ++// bit 24:12 convas_y_start ( 13 btis ) ++// bit 11:0 convas_x_start ( 12 btis ) ++#define DCAC_DMA_ADDRESS (0x0e13) ++#define P_DCAC_DMA_ADDRESS (volatile unsigned int *)((0x0e13 << 2) + 0xff620000) ++// bit 7:0 -- dcac_cpu_addr ++#define DCAC_CPU_ADDRESS (0x0e14) ++#define P_DCAC_CPU_ADDRESS (volatile unsigned int *)((0x0e14 << 2) + 0xff620000) ++// bit 31:0 -- dcac_cpu_data ++#define DCAC_CPU_DATA (0x0e15) ++#define P_DCAC_CPU_DATA (volatile unsigned int *)((0x0e15 << 2) + 0xff620000) ++// bit 31:19 -- reserved ++// bit 18:16 -- block_num_reg -- Read-Only ++// bit 15:0 -- dcac_mb_count ++#define DCAC_MB_COUNT (0x0e16) ++#define P_DCAC_MB_COUNT (volatile unsigned int *)((0x0e16 << 2) + 0xff620000) ++// bit 31:18 -- reserved ++// For H264 : ++// bit 17:2 -- h264_quant ++// bit 11:6 -- h264_quant_c ++// bit 5:0 -- h264_quant_c ++// For VC1 : ++// bit 17 -- qindex_GT_8 ++// bit 16 -- HalfQPStep ++// bit 15:12 -- eQuantMode ++// bit 11:6 -- AltPQuant ++// bit 5:0 -- PQuant ++// ++#define IQ_QUANT (0x0e17) ++#define P_IQ_QUANT (volatile unsigned int *)((0x0e17 << 2) + 0xff620000) ++// bit 31:24 -- bitplane_width ++// bit 23:16 -- bitplane_height ++// bit 15:14 -- bitplane_start_x ++// bit 13:12 -- bitplane_start_y ++// bit 11:4 -- reserved ++// bit 3:1 -- bitplane_type ++// bit 0 -- bitplane_busy ++#define VC1_BITPLANE_CTL (0x0e18) ++#define P_VC1_BITPLANE_CTL (volatile unsigned int *)((0x0e18 << 2) + 0xff620000) ++// bit 24:16 -- wq_param1 ++// bit 8: 0 -- wq_param0 ++#define AVSP_IQ_WQ_PARAM_01 (0x0e19) ++#define P_AVSP_IQ_WQ_PARAM_01 (volatile unsigned int *)((0x0e19 << 2) + 0xff620000) ++// bit 24:16 -- wq_param3 ++// bit 8: 0 -- wq_param2 ++#define AVSP_IQ_WQ_PARAM_23 (0x0e1a) ++#define P_AVSP_IQ_WQ_PARAM_23 (volatile unsigned int *)((0x0e1a << 2) + 0xff620000) ++// bit 24:16 -- wq_param5 ++// bit 8: 0 -- wq_param4 ++#define AVSP_IQ_WQ_PARAM_45 (0x0e1b) ++#define P_AVSP_IQ_WQ_PARAM_45 (volatile unsigned int *)((0x0e1b << 2) + 0xff620000) ++// bit 31 -- weight_quant_en ++// bit 17:16 -- current_scene_model ++// bit 12: 8 -- chroma_qp_delta_cr ++// bit 4: 0 -- chroma_qp_delta_cb ++#define AVSP_IQ_CTL (0x0e1c) ++#define P_AVSP_IQ_CTL (volatile unsigned int *)((0x0e1c << 2) + 0xff620000) ++ #define RAM_TEST_CMD 0x002 ++ #define RAM_TEST_ADDR 0x003 ++ #define RAM_TEST_DATAH 0x004 ++ #define RAM_TEST_DATAL 0x005 ++ ++ #define RAM_TEST_RD_CMD 0x0000 ++ #define RAM_TEST_WR_CMD 0x8000 ++ #define IDCT_TM2_PT0 0x0001 ++ #define IDCT_TM2_PT1 0x0002 ++ #define IDCT_TM1_PT0 0x0004 ++ #define IDCT_TM1_PT1 0x0008 ++ #define IQ_OMEM_PT0 0x0010 ++ #define IQ_OMEM_PT1 0x0020 ++ #define MC_IMEM_PT0 0x0040 ++ #define ALL_RAM_PTS 0x007f ++//====================================== ++// VCOP Control Register Bits ++// ++//====================================== ++ //`define IQIDCT_RESET 16'h0001 // Bit 0 ++ #define QM_WEN 0x0002 // Bit 1 ++ #define IQIDCT_ENABLE 0x0004 // Bit 2 ++ #define INTRA_QM 0x0008 // Bit 3 0 = Use default; 1 = use loaded ++ #define NINTRA_QM 0x0010 // Bit 4 0 = Use default; 1 = use loaded ++//====================================== ++// QP Control Register Bits ++// ++//====================================== ++ #define INTRA_MODE 0x0080 // Bit 7 ++// Duplicate Address: When actually used ++// please move to a different address ++// `define FLD_DCT_TYPE 16'h0100 // Bit 8 0 = Frame DCT; 1 = field DCT ++// ++// Closing file: iqidct_regs.h ++// ++//------------------------------------------------------------------------------ ++// VCPU module level register offset ++//------------------------------------------------------------------------------ ++// ++// Reading file: vcpu_regs.h ++// ++//======================================================================== ++// VCPU module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_VDEC_VCPU_CBUS_BASE = 0x03 ++// ----------------------------------------------- ++#define MSP (0x0300) ++#define P_MSP (volatile unsigned int *)((0x0300 << 2) + 0xff620000) ++#define MPSR (0x0301) ++#define P_MPSR (volatile unsigned int *)((0x0301 << 2) + 0xff620000) ++#define MINT_VEC_BASE (0x0302) ++#define P_MINT_VEC_BASE (volatile unsigned int *)((0x0302 << 2) + 0xff620000) ++#define MCPU_INTR_GRP (0x0303) ++#define P_MCPU_INTR_GRP (volatile unsigned int *)((0x0303 << 2) + 0xff620000) ++#define MCPU_INTR_MSK (0x0304) ++#define P_MCPU_INTR_MSK (volatile unsigned int *)((0x0304 << 2) + 0xff620000) ++#define MCPU_INTR_REQ (0x0305) ++#define P_MCPU_INTR_REQ (volatile unsigned int *)((0x0305 << 2) + 0xff620000) ++#define MPC_P (0x0306) ++#define P_MPC_P (volatile unsigned int *)((0x0306 << 2) + 0xff620000) ++#define MPC_D (0x0307) ++#define P_MPC_D (volatile unsigned int *)((0x0307 << 2) + 0xff620000) ++#define MPC_E (0x0308) ++#define P_MPC_E (volatile unsigned int *)((0x0308 << 2) + 0xff620000) ++#define MPC_W (0x0309) ++#define P_MPC_W (volatile unsigned int *)((0x0309 << 2) + 0xff620000) ++#define MINDEX0_REG (0x030a) ++#define P_MINDEX0_REG (volatile unsigned int *)((0x030a << 2) + 0xff620000) ++#define MINDEX1_REG (0x030b) ++#define P_MINDEX1_REG (volatile unsigned int *)((0x030b << 2) + 0xff620000) ++#define MINDEX2_REG (0x030c) ++#define P_MINDEX2_REG (volatile unsigned int *)((0x030c << 2) + 0xff620000) ++#define MINDEX3_REG (0x030d) ++#define P_MINDEX3_REG (volatile unsigned int *)((0x030d << 2) + 0xff620000) ++#define MINDEX4_REG (0x030e) ++#define P_MINDEX4_REG (volatile unsigned int *)((0x030e << 2) + 0xff620000) ++#define MINDEX5_REG (0x030f) ++#define P_MINDEX5_REG (volatile unsigned int *)((0x030f << 2) + 0xff620000) ++#define MINDEX6_REG (0x0310) ++#define P_MINDEX6_REG (volatile unsigned int *)((0x0310 << 2) + 0xff620000) ++#define MINDEX7_REG (0x0311) ++#define P_MINDEX7_REG (volatile unsigned int *)((0x0311 << 2) + 0xff620000) ++#define MMIN_REG (0x0312) ++#define P_MMIN_REG (volatile unsigned int *)((0x0312 << 2) + 0xff620000) ++#define MMAX_REG (0x0313) ++#define P_MMAX_REG (volatile unsigned int *)((0x0313 << 2) + 0xff620000) ++#define MBREAK0_REG (0x0314) ++#define P_MBREAK0_REG (volatile unsigned int *)((0x0314 << 2) + 0xff620000) ++#define MBREAK1_REG (0x0315) ++#define P_MBREAK1_REG (volatile unsigned int *)((0x0315 << 2) + 0xff620000) ++#define MBREAK2_REG (0x0316) ++#define P_MBREAK2_REG (volatile unsigned int *)((0x0316 << 2) + 0xff620000) ++#define MBREAK3_REG (0x0317) ++#define P_MBREAK3_REG (volatile unsigned int *)((0x0317 << 2) + 0xff620000) ++#define MBREAK_TYPE (0x0318) ++#define P_MBREAK_TYPE (volatile unsigned int *)((0x0318 << 2) + 0xff620000) ++#define MBREAK_CTRL (0x0319) ++#define P_MBREAK_CTRL (volatile unsigned int *)((0x0319 << 2) + 0xff620000) ++#define MBREAK_STAUTS (0x031a) ++#define P_MBREAK_STAUTS (volatile unsigned int *)((0x031a << 2) + 0xff620000) ++#define MDB_ADDR_REG (0x031b) ++#define P_MDB_ADDR_REG (volatile unsigned int *)((0x031b << 2) + 0xff620000) ++#define MDB_DATA_REG (0x031c) ++#define P_MDB_DATA_REG (volatile unsigned int *)((0x031c << 2) + 0xff620000) ++#define MDB_CTRL (0x031d) ++#define P_MDB_CTRL (volatile unsigned int *)((0x031d << 2) + 0xff620000) ++#define MSFTINT0 (0x031e) ++#define P_MSFTINT0 (volatile unsigned int *)((0x031e << 2) + 0xff620000) ++#define MSFTINT1 (0x031f) ++#define P_MSFTINT1 (volatile unsigned int *)((0x031f << 2) + 0xff620000) ++#define CSP (0x0320) ++#define P_CSP (volatile unsigned int *)((0x0320 << 2) + 0xff620000) ++#define CPSR (0x0321) ++#define P_CPSR (volatile unsigned int *)((0x0321 << 2) + 0xff620000) ++#define CINT_VEC_BASE (0x0322) ++#define P_CINT_VEC_BASE (volatile unsigned int *)((0x0322 << 2) + 0xff620000) ++#define CCPU_INTR_GRP (0x0323) ++#define P_CCPU_INTR_GRP (volatile unsigned int *)((0x0323 << 2) + 0xff620000) ++#define CCPU_INTR_MSK (0x0324) ++#define P_CCPU_INTR_MSK (volatile unsigned int *)((0x0324 << 2) + 0xff620000) ++#define CCPU_INTR_REQ (0x0325) ++#define P_CCPU_INTR_REQ (volatile unsigned int *)((0x0325 << 2) + 0xff620000) ++#define CPC_P (0x0326) ++#define P_CPC_P (volatile unsigned int *)((0x0326 << 2) + 0xff620000) ++#define CPC_D (0x0327) ++#define P_CPC_D (volatile unsigned int *)((0x0327 << 2) + 0xff620000) ++#define CPC_E (0x0328) ++#define P_CPC_E (volatile unsigned int *)((0x0328 << 2) + 0xff620000) ++#define CPC_W (0x0329) ++#define P_CPC_W (volatile unsigned int *)((0x0329 << 2) + 0xff620000) ++#define CINDEX0_REG (0x032a) ++#define P_CINDEX0_REG (volatile unsigned int *)((0x032a << 2) + 0xff620000) ++#define CINDEX1_REG (0x032b) ++#define P_CINDEX1_REG (volatile unsigned int *)((0x032b << 2) + 0xff620000) ++#define CINDEX2_REG (0x032c) ++#define P_CINDEX2_REG (volatile unsigned int *)((0x032c << 2) + 0xff620000) ++#define CINDEX3_REG (0x032d) ++#define P_CINDEX3_REG (volatile unsigned int *)((0x032d << 2) + 0xff620000) ++#define CINDEX4_REG (0x032e) ++#define P_CINDEX4_REG (volatile unsigned int *)((0x032e << 2) + 0xff620000) ++#define CINDEX5_REG (0x032f) ++#define P_CINDEX5_REG (volatile unsigned int *)((0x032f << 2) + 0xff620000) ++#define CINDEX6_REG (0x0330) ++#define P_CINDEX6_REG (volatile unsigned int *)((0x0330 << 2) + 0xff620000) ++#define CINDEX7_REG (0x0331) ++#define P_CINDEX7_REG (volatile unsigned int *)((0x0331 << 2) + 0xff620000) ++#define CMIN_REG (0x0332) ++#define P_CMIN_REG (volatile unsigned int *)((0x0332 << 2) + 0xff620000) ++#define CMAX_REG (0x0333) ++#define P_CMAX_REG (volatile unsigned int *)((0x0333 << 2) + 0xff620000) ++#define CBREAK0_REG (0x0334) ++#define P_CBREAK0_REG (volatile unsigned int *)((0x0334 << 2) + 0xff620000) ++#define CBREAK1_REG (0x0335) ++#define P_CBREAK1_REG (volatile unsigned int *)((0x0335 << 2) + 0xff620000) ++#define CBREAK2_REG (0x0336) ++#define P_CBREAK2_REG (volatile unsigned int *)((0x0336 << 2) + 0xff620000) ++#define CBREAK3_REG (0x0337) ++#define P_CBREAK3_REG (volatile unsigned int *)((0x0337 << 2) + 0xff620000) ++#define CBREAK_TYPE (0x0338) ++#define P_CBREAK_TYPE (volatile unsigned int *)((0x0338 << 2) + 0xff620000) ++#define CBREAK_CTRL (0x0339) ++#define P_CBREAK_CTRL (volatile unsigned int *)((0x0339 << 2) + 0xff620000) ++#define CBREAK_STAUTS (0x033a) ++#define P_CBREAK_STAUTS (volatile unsigned int *)((0x033a << 2) + 0xff620000) ++#define CDB_ADDR_REG (0x033b) ++#define P_CDB_ADDR_REG (volatile unsigned int *)((0x033b << 2) + 0xff620000) ++#define CDB_DATA_REG (0x033c) ++#define P_CDB_DATA_REG (volatile unsigned int *)((0x033c << 2) + 0xff620000) ++#define CDB_CTRL (0x033d) ++#define P_CDB_CTRL (volatile unsigned int *)((0x033d << 2) + 0xff620000) ++#define CSFTINT0 (0x033e) ++#define P_CSFTINT0 (volatile unsigned int *)((0x033e << 2) + 0xff620000) ++#define CSFTINT1 (0x033f) ++#define P_CSFTINT1 (volatile unsigned int *)((0x033f << 2) + 0xff620000) ++#define IMEM_DMA_CTRL (0x0340) ++#define P_IMEM_DMA_CTRL (volatile unsigned int *)((0x0340 << 2) + 0xff620000) ++#define IMEM_DMA_ADR (0x0341) ++#define P_IMEM_DMA_ADR (volatile unsigned int *)((0x0341 << 2) + 0xff620000) ++#define IMEM_DMA_COUNT (0x0342) ++#define P_IMEM_DMA_COUNT (volatile unsigned int *)((0x0342 << 2) + 0xff620000) ++// bit[29:24] A_brst_num_imem ++// bit[21:16] A_id_imem ++// bit[11:0] wrrsp_count_imem (reserved) ++#define WRRSP_IMEM (0x0343) ++#define P_WRRSP_IMEM (volatile unsigned int *)((0x0343 << 2) + 0xff620000) ++#define LMEM_DMA_CTRL (0x0350) ++#define P_LMEM_DMA_CTRL (volatile unsigned int *)((0x0350 << 2) + 0xff620000) ++#define LMEM_DMA_ADR (0x0351) ++#define P_LMEM_DMA_ADR (volatile unsigned int *)((0x0351 << 2) + 0xff620000) ++#define LMEM_DMA_COUNT (0x0352) ++#define P_LMEM_DMA_COUNT (volatile unsigned int *)((0x0352 << 2) + 0xff620000) ++// bit[29:24] A_brst_num_lmem ++// bit[21:16] A_id_lmem ++// bit[11:0] wrrsp_count_lmem ++#define WRRSP_LMEM (0x0353) ++#define P_WRRSP_LMEM (volatile unsigned int *)((0x0353 << 2) + 0xff620000) ++#define MAC_CTRL1 (0x0360) ++#define P_MAC_CTRL1 (volatile unsigned int *)((0x0360 << 2) + 0xff620000) ++#define ACC0REG1 (0x0361) ++#define P_ACC0REG1 (volatile unsigned int *)((0x0361 << 2) + 0xff620000) ++#define ACC1REG1 (0x0362) ++#define P_ACC1REG1 (volatile unsigned int *)((0x0362 << 2) + 0xff620000) ++#define MAC_CTRL2 (0x0370) ++#define P_MAC_CTRL2 (volatile unsigned int *)((0x0370 << 2) + 0xff620000) ++#define ACC0REG2 (0x0371) ++#define P_ACC0REG2 (volatile unsigned int *)((0x0371 << 2) + 0xff620000) ++#define ACC1REG2 (0x0372) ++#define P_ACC1REG2 (volatile unsigned int *)((0x0372 << 2) + 0xff620000) ++#define CPU_TRACE (0x0380) ++#define P_CPU_TRACE (volatile unsigned int *)((0x0380 << 2) + 0xff620000) ++// ++// Closing file: vcpu_regs.h ++// ++//------------------------------------------------------------------------------ ++// HENC module level register offset ++//------------------------------------------------------------------------------ ++// ++// Reading file: henc_regs.h ++// ++//======================================================================== ++// MDEC module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HCODEC_HENC_CBUS_BASE = 0x0a ++// ----------------------------------------------- ++#define HENC_SCRATCH_0 (0x1ac0) ++#define P_HENC_SCRATCH_0 (volatile unsigned int *)((0x1ac0 << 2) + 0xff620000) ++#define HENC_SCRATCH_1 (0x1ac1) ++#define P_HENC_SCRATCH_1 (volatile unsigned int *)((0x1ac1 << 2) + 0xff620000) ++#define HENC_SCRATCH_2 (0x1ac2) ++#define P_HENC_SCRATCH_2 (volatile unsigned int *)((0x1ac2 << 2) + 0xff620000) ++#define HENC_SCRATCH_3 (0x1ac3) ++#define P_HENC_SCRATCH_3 (volatile unsigned int *)((0x1ac3 << 2) + 0xff620000) ++#define HENC_SCRATCH_4 (0x1ac4) ++#define P_HENC_SCRATCH_4 (volatile unsigned int *)((0x1ac4 << 2) + 0xff620000) ++#define HENC_SCRATCH_5 (0x1ac5) ++#define P_HENC_SCRATCH_5 (volatile unsigned int *)((0x1ac5 << 2) + 0xff620000) ++#define HENC_SCRATCH_6 (0x1ac6) ++#define P_HENC_SCRATCH_6 (volatile unsigned int *)((0x1ac6 << 2) + 0xff620000) ++#define HENC_SCRATCH_7 (0x1ac7) ++#define P_HENC_SCRATCH_7 (volatile unsigned int *)((0x1ac7 << 2) + 0xff620000) ++#define HENC_SCRATCH_8 (0x1ac8) ++#define P_HENC_SCRATCH_8 (volatile unsigned int *)((0x1ac8 << 2) + 0xff620000) ++#define HENC_SCRATCH_9 (0x1ac9) ++#define P_HENC_SCRATCH_9 (volatile unsigned int *)((0x1ac9 << 2) + 0xff620000) ++#define HENC_SCRATCH_A (0x1aca) ++#define P_HENC_SCRATCH_A (volatile unsigned int *)((0x1aca << 2) + 0xff620000) ++#define HENC_SCRATCH_B (0x1acb) ++#define P_HENC_SCRATCH_B (volatile unsigned int *)((0x1acb << 2) + 0xff620000) ++#define HENC_SCRATCH_C (0x1acc) ++#define P_HENC_SCRATCH_C (volatile unsigned int *)((0x1acc << 2) + 0xff620000) ++#define HENC_SCRATCH_D (0x1acd) ++#define P_HENC_SCRATCH_D (volatile unsigned int *)((0x1acd << 2) + 0xff620000) ++#define HENC_SCRATCH_E (0x1ace) ++#define P_HENC_SCRATCH_E (volatile unsigned int *)((0x1ace << 2) + 0xff620000) ++#define HENC_SCRATCH_F (0x1acf) ++#define P_HENC_SCRATCH_F (volatile unsigned int *)((0x1acf << 2) + 0xff620000) ++#define HENC_SCRATCH_G (0x1ad0) ++#define P_HENC_SCRATCH_G (volatile unsigned int *)((0x1ad0 << 2) + 0xff620000) ++#define HENC_SCRATCH_H (0x1ad1) ++#define P_HENC_SCRATCH_H (volatile unsigned int *)((0x1ad1 << 2) + 0xff620000) ++#define HENC_SCRATCH_I (0x1ad2) ++#define P_HENC_SCRATCH_I (volatile unsigned int *)((0x1ad2 << 2) + 0xff620000) ++#define HENC_SCRATCH_J (0x1ad3) ++#define P_HENC_SCRATCH_J (volatile unsigned int *)((0x1ad3 << 2) + 0xff620000) ++#define HENC_SCRATCH_K (0x1ad4) ++#define P_HENC_SCRATCH_K (volatile unsigned int *)((0x1ad4 << 2) + 0xff620000) ++#define HENC_SCRATCH_L (0x1ad5) ++#define P_HENC_SCRATCH_L (volatile unsigned int *)((0x1ad5 << 2) + 0xff620000) ++#define HENC_SCRATCH_M (0x1ad6) ++#define P_HENC_SCRATCH_M (volatile unsigned int *)((0x1ad6 << 2) + 0xff620000) ++#define HENC_SCRATCH_N (0x1ad7) ++#define P_HENC_SCRATCH_N (volatile unsigned int *)((0x1ad7 << 2) + 0xff620000) ++// bit [7:0] data_feed_buff_id ++#define IE_DATA_FEED_BUFF_INFO (0x1ad8) ++#define P_IE_DATA_FEED_BUFF_INFO (volatile unsigned int *)((0x1ad8 << 2) + 0xff620000) ++// ++// Closing file: henc_regs.h ++// ++//------------------------------------------------------------------------------ ++// VLC module level register offset ++//------------------------------------------------------------------------------ ++// ++// Reading file: vlc_regs.h ++// ++//======================================================================== ++// VLC module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HCODEC_VLC_CBUS_BASE = 0x0d ++// ----------------------------------------------- ++// Bit[31:28] - henc_status ++// Bit[27:8] - reserved ++// Bit[7] mc_hcmd_buff_enable ++// Bit[6] mc_hcmd_use_mc_hcmd_buff ++// Bit[5] mc_hcmd_use_mc_hcmd_hw_start ++// Bit[4] no_mc_out_null_non_skipped_mb ++// Bit[3] mc_out_even_skipped_mb ++// Bit[2] - hcmd_enable ++// Bit[1] - vlc_control_enable (0 will treat as soft_reset) ++// Bit[0] - vlc_input_enable (enable input interface) ++#define VLC_STATUS_CTRL (0x1d00) ++#define P_VLC_STATUS_CTRL (volatile unsigned int *)((0x1d00 << 2) + 0xff620000) ++// Bit [31] - small_luma_ignore_chroma ++// Bit[30:16] - Reserved ++// Bit [15] - enable_free_clk_mc_hcmd_buff ++// Bit [14] - enable_free_clk_reg ++// Bit [13] - enable_free_clk_stream ++// Bit [12] - enable_free_clk_pre_buff ++// Bit [11] - enable_free_clk_vb_buff ++// Bit [10] - enable_free_clk_dc_input ++// Bit [9] - enable_free_clk_input ++// Bit [8] - enable_free_clk_mv_cal ++// Bit [7] - enable_free_clk_status ++// Bit [6] - enable_free_clk_mc_dblk_cmd_if ++// Bit [5] - disable_mvd_enc_finished ++// Bit [4] - I16MB_share_ipred_mode_with_I4MB ++// Bit [3] - fixed_picture_qp ++// Bit [2] - use_set_b8_mode ( not used now) ++// Bit [1] - use_set_mb_skip_run ++// Bit [0] - pop_coeff_even_all_zero ++#define VLC_CONFIG (0x1d01) ++#define P_VLC_CONFIG (volatile unsigned int *)((0x1d01 << 2) + 0xff620000) ++// -------------------------------------------- ++// Bitstream DDR Interface ++// -------------------------------------------- ++#define VLC_VB_START_PTR (0x1d10) ++#define P_VLC_VB_START_PTR (volatile unsigned int *)((0x1d10 << 2) + 0xff620000) ++#define VLC_VB_END_PTR (0x1d11) ++#define P_VLC_VB_END_PTR (volatile unsigned int *)((0x1d11 << 2) + 0xff620000) ++#define VLC_VB_WR_PTR (0x1d12) ++#define P_VLC_VB_WR_PTR (volatile unsigned int *)((0x1d12 << 2) + 0xff620000) ++// Read Only, VLC_VB_SW_RD_PTR or VLC_VB_HW_RD_PTR ++#define VLC_VB_RD_PTR (0x1d13) ++#define P_VLC_VB_RD_PTR (volatile unsigned int *)((0x1d13 << 2) + 0xff620000) ++#define VLC_VB_SW_RD_PTR (0x1d14) ++#define P_VLC_VB_SW_RD_PTR (volatile unsigned int *)((0x1d14 << 2) + 0xff620000) ++// Read Only ++#define VLC_VB_LEFT (0x1d15) ++#define P_VLC_VB_LEFT (volatile unsigned int *)((0x1d15 << 2) + 0xff620000) ++// VB FIFO Control ++// bit [31:24] vb_full_int_enable_cpu[7:0] ++// bit [23:16] vb_full_int_enable_amrisc[7:0] ++// -bit 23 Video BUFFER LEFT < 0x400 Bytes ++// -bit 22 Video BUFFER LEFT < 0x200 Bytes ++// -bit 21 Video BUFFER LEFT < 0x100 Bytes ++// -bit 20 Video BUFFER LEFT < 0x80 Bytes ++// -bit 19 Video BUFFER LEFT < 0x40 Bytes ++// -bit 18 Video BUFFER LEFT < 0x20 Bytes ++// -bit 17 vbfifo left < 16 double words (8x64bits) ++// -bit 16 vbfifo left < 8 double words (4x64bits) ++// bit [15] wr_ptr_int_enable_cpu ++// bit [14] wr_ptr_int_enable_amrisc ++// bit [13] wr_ptr_int (Read Only, write 1 will clear) ++// bit [12] vb_full_int_enable_cpu(Read Only) ++// bit [11] vb_full_int_enable_amrisc(Read Only) ++// bit [10] reserved ++// bit [9] use_vb_hw_rd_ptr ++// bit [8] vb_always_ready Set to 1 to ignore vb_level blocking DDR write ++// bit [7] vb_ready_for_transfer (Read Only) ++// bit [6] data_ready_for_transfer (Read Only) ++// bits [5:3] vb_endian Set VB Endian inside DDR memory ++// bit [2] vb_write_busy Read Only - indicate DDR write busy ++// bit [1] vb_write_en Set to 1 to enable writing data to DDR memory ++// bit [0] vb_soft_reset Soft reset ++#define VLC_VB_CONTROL (0x1d16) ++#define P_VLC_VB_CONTROL (volatile unsigned int *)((0x1d16 << 2) + 0xff620000) ++// bit 31 transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request // default : 0 ++// bit 30 A_urgent // default : 0 ++// bit 29:24 A_brst_num // default : 0x3f ++// bit 23:22 reserved ++// bit 21:16 A_id // default : 0x20 ++// bit 15:0 vb_left_hold // default : 0 ++#define VLC_VB_MEM_CTL (0x1d17) ++#define P_VLC_VB_MEM_CTL (volatile unsigned int *)((0x1d17 << 2) + 0xff620000) ++// vb_wr_ptr address to generate interrupt ++#define VLC_VB_INT_PTR (0x1d18) ++#define P_VLC_VB_INT_PTR (volatile unsigned int *)((0x1d18 << 2) + 0xff620000) ++// bit[31:12] reserved ++// bit[11:0] vlc_wrrsp_count ++#define VLC_WRRSP (0x1d19) ++#define P_VLC_WRRSP (volatile unsigned int *)((0x1d19 << 2) + 0xff620000) ++#define VLC_TOTAL_BYTES (0x1d1a) ++#define P_VLC_TOTAL_BYTES (volatile unsigned int *)((0x1d1a << 2) + 0xff620000) ++// bit [31:26] reserved ++// bit [25] vb_flush ++// bit [24] vb_reg_ready ++// bit [23:16] vb_buff_left -- Read only ++// bit [15:8] vb_buff_wr_point -- RW ++// bit [7:0] vb_buff_rd_point -- RW ++#define VLC_VB_BUFF (0x1d1b) ++#define P_VLC_VB_BUFF (volatile unsigned int *)((0x1d1b << 2) + 0xff620000) ++// bit[31] flush_vlc_pre_buff ++// bit[30:27] reserved ++// bit[26:24] vb_pre_buff_level ++// bit[23:0] vb_pre_buff_data[55:32] ++#define VLC_VB_PRE_BUFF_HI (0x1d1c) ++#define P_VLC_VB_PRE_BUFF_HI (volatile unsigned int *)((0x1d1c << 2) + 0xff620000) ++// bit[31:0] vb_pre_buff_data[31:0] ++#define VLC_VB_PRE_BUFF_LOW (0x1d1d) ++#define P_VLC_VB_PRE_BUFF_LOW (volatile unsigned int *)((0x1d1d << 2) + 0xff620000) ++// bit[31] stream_encap_enable // 0x0000(00-03) will be changed to 0x000003(00-03) if enabled ++// bit[30:29] stream_encap_delay // delay bytes for encap used ++// bit[28:24] stream_buff_point ++// bit[23:0] stream_buff_data ++#define VLC_STREAM_BUFF (0x1d1e) ++#define P_VLC_STREAM_BUFF (volatile unsigned int *)((0x1d1e << 2) + 0xff620000) ++// bit[31] push_stream_block - Read Only (Will set if vb_buff full) ++// bit[30] push_stream_busy - Read Only (busy when output one byte from stream_buf (max 2 clocks for 8 bits push) ++// bit[29:28] stream_encap_status - Read Only ++// bit[27:21] reserved ++// Long Mode : (Amrisc need movilo and mvihi high to set stream_info) ++// bit[20:16] push_stream_long_length (0 or 31 : Mid or Short mode) ++// bit[15:0] push_stream_data ++// Mid Mode : (Amrisc need movi to set stream_info) ++// bit[15:12]] push_stream_mid_length (1-12 : mid mode active, 0-short mode, 15 - byte align) ++// bit[11:0] push_stream_data ++// Short Mode : (Amrisc can use mtspi to push stream directely) ++// bit[7:5] push_stream_short_length (0-5 : short length, else - invalid) ++// bit[4:0] push_stream_data ++#define VLC_PUSH_STREAM (0x1d1f) ++#define P_VLC_PUSH_STREAM (volatile unsigned int *)((0x1d1f << 2) + 0xff620000) ++// bit[15:8] ELEMENT_LENGTH ++// bit[7:1] reserved ++// bit[0] Write - push start, Read - Push Busy ++#define VLC_PUSH_ELEMENT (0x1d20) ++#define P_VLC_PUSH_ELEMENT (volatile unsigned int *)((0x1d20 << 2) + 0xff620000) ++#define VLC_ELEMENT_DATA (0x1d21) ++#define P_VLC_ELEMENT_DATA (volatile unsigned int *)((0x1d21 << 2) + 0xff620000) ++// bit[7] hcmd_intra_use_sw_info ++// bit[6] hcmd_use_sw_info ++// bit[5] always_use_info_0_cbp_blk ++// bit[4] always_update_info_0_cbp_blk ++// bit[3] reset_left_mb_wr ++// bit[2] reset_top_mb_wr ++// bit[1] set_left_mb_wr ++// bit[0] set_top_mb_wr ++#define VLC_SPECIAL_CTL (0x1d22) ++#define P_VLC_SPECIAL_CTL (volatile unsigned int *)((0x1d22 << 2) + 0xff620000) ++// bit[28] left_intra ++// bit[27:22] left_quant ++// bit[21:16] left_quant_c ++// bit[12] top_intra ++// bit[11:6] top_quant ++// bit[5:0] top_quant_c ++#define VLC_HCMD_T_L_INFO (0x1d23) ++#define P_VLC_HCMD_T_L_INFO (volatile unsigned int *)((0x1d23 << 2) + 0xff620000) ++// bit[12] cur_intra ++// bit[11:6] cur_quant ++// bit[5:0] cur_quant_c ++#define VLC_HCMD_CUR_INFO (0x1d24) ++#define P_VLC_HCMD_CUR_INFO (volatile unsigned int *)((0x1d24 << 2) + 0xff620000) ++// bit[13] top_left_info_in_data_mv_cal ++// bit[12] only_use_info_0_top_left_in_I ++// bit[11] top_left_info_in_data ++// bit[10] early_mix_mc_hcmd ++// bit[9] update_top_left_mix ++// bit[8] p_top_left_mix ++// bit[7] mv_cal_mixed_type ++// bit[6] mc_hcmd_mixed_type ++// bit[5] use_seperate_int_control ++// bit[4] hcmd_intra_use_q_info ++// bit[3] hcmd_left_use_prev_info ++// bit[2] hcmd_use_q_info ++// bit[1] use_q_delta_quant ++// bit[0] detect_I16_from_I4 ++#define VLC_ADV_CONFIG (0x1d25) ++#define P_VLC_ADV_CONFIG (volatile unsigned int *)((0x1d25 << 2) + 0xff620000) ++// 31 - use_hcmd_mb_xy_auto ++//23:16 - hcmd_max_mb_x ++//15:8 - hcmd_mb_y_auto ++// 7:0 - hcmd_mb_x_auto ++#define VLC_HCMD_MBXY_AUTO (0x1d26) ++#define P_VLC_HCMD_MBXY_AUTO (volatile unsigned int *)((0x1d26 << 2) + 0xff620000) ++// bit[31:0] vlc_int_control_inter -- will be used when use_seperate_int_control is set ++#define VLC_INT_CONTROL_INTER (0x1d2f) ++#define P_VLC_INT_CONTROL_INTER (volatile unsigned int *)((0x1d2f << 2) + 0xff620000) ++// -------------------------------------------- ++// Picture VLC ++// -------------------------------------------- ++// (&(int|(~AND_enable))|(|(int&OR_enable))) ++// bit[31] OR interrupt Enable Reserved ++// bit[30] OR interrupt Enable for mv_busy ++// bit[29] OR interrupt Enable for b8_mode_busy ++// bit[28] OR interrupt Enable for mb_skip_run_busy ++// bit[27] OR interrupt Enable for cbp_busy ++// bit[26] OR interrupt Enable for Reserved ++// bit[25] OR interrupt Enable for Reserved ++// bit[24] OR interrupt Enable for mb_info_busy ++// bit[23] AND interrupt Enable Reserved ++// bit[22] AND interrupt Enable for mv_busy ++// bit[21] AND interrupt Enable for b8_mode_busy ++// bit[20] AND interrupt Enable for mb_skip_run_busy ++// bit[19] AND interrupt Enable for cbp_busy ++// bit[18] AND interrupt Enable for Reserved ++// bit[17] AND interrupt Enable for Reserved ++// bit[16] AND interrupt Enable for mb_info_busy ++// bit[15] OR interrupt Enable Reserved ++// bit[14] OR interrupt Enable for mvd ++// bit[13] OR interrupt Enable for b8_mode ++// bit[12] OR interrupt Enable for mb_skip_run ++// bit[11] OR interrupt Enable for cbp_ready ++// bit[10] OR interrupt Enable for c_ipred_mode_ready ++// bit[9] OR interrupt Enable for ipred_mode_ready ++// bit[8] OR interrupt Enable for mb_info_ready ++// bit[7] AND interrupt Enable Reserved ++// bit[6] AND interrupt Enable for mvd ++// bit[5] AND interrupt Enable for b8_mode ++// bit[4] AND interrupt Enable for mb_skip_run ++// bit[3] AND interrupt Enable for cbp_ready ++// bit[2] AND interrupt Enable for c_ipred_mode_ready ++// bit[1] AND interrupt Enable for ipred_mode_ready ++// bit[0] AND interrupt Enable for mb_info_ready ++#define VLC_INT_CONTROL (0x1d30) ++#define P_VLC_INT_CONTROL (volatile unsigned int *)((0x1d30 << 2) + 0xff620000) ++// Bit[31:16] picture_height ++// Bit[15:0] picture_width ++#define VLC_PIC_SIZE (0x1d31) ++#define P_VLC_PIC_SIZE (volatile unsigned int *)((0x1d31 << 2) + 0xff620000) ++// [31:16] Reserved ++// [15:3] pic_width_in_mbs_minus1 ++// [2:0] picture_type ++#define VLC_PIC_INFO (0x1d32) ++#define P_VLC_PIC_INFO (volatile unsigned int *)((0x1d32 << 2) + 0xff620000) ++// Bit[31:16] MB_NR ++// Bit[15:8] MBY ++// Bit[7:0] MBX ++#define VLC_PIC_POSITION (0x1d33) ++#define P_VLC_PIC_POSITION (volatile unsigned int *)((0x1d33 << 2) + 0xff620000) ++// Bit[31] MV_busy ++// Bit[30:6] Reserved ++// Bit[15] Reserved ++// Bit[14] vlc_input_MV_busy ++// Bit[13] vlc_input_b8_mode_busy ++// Bit[12] vlc_input_mb_skip_run_busy ++// Bit[11] vlc_input_cbp_busy ++// Bit[10] Reserved ++// Bit[9] Reserved ++// Bit[8] vlc_input_mb_info_busy ++// Bit[7] Reserved ++// Bit[6] mvd ++// Bit[5] b8_mode ++// Bit[4] mb_skip_run ++// Bit[3] cbp ++// Bit[2] c_ipred_mode ++// Bit[1] ipred_mode ++// Bit[0] mb_info ( mb_type, mb_x, mb_y) ++#define VLC_INPUT_STATUS (0x1d34) ++#define P_VLC_INPUT_STATUS (volatile unsigned int *)((0x1d34 << 2) + 0xff620000) ++// Bit[31:28] detected_mb_type ++// Bit[27:16] mb_y ++// Bit[15:4] mb_x ++// Bit[3:0] mb_type ++#define VLC_MB_INFO (0x1d35) ++#define P_VLC_MB_INFO (volatile unsigned int *)((0x1d35 << 2) + 0xff620000) ++// commnad 0 -- no pending ++// normal command + 1 is pending command ++// ++// bit 31:28 -- pending command 7 ++// bit 27:24 -- pending command 6 ++// bit 23:20 -- pending command 5 ++// bit 19:16 -- pending command 4 ++// bit 15:12 -- pending command 3 ++// bit 11:8 -- pending command 2 ++// bit 7:4 -- pending command 1 ++// bit 3:0 -- pending command 0 ++#define VLC_ENC_PEND_CMD (0x1d36) ++#define P_VLC_ENC_PEND_CMD (volatile unsigned int *)((0x1d36 << 2) + 0xff620000) ++// For I Slice ++// Bit[31:16] Reserved ++// Bit[15:0] IntraType ++#define HENC_TOP_INFO_0 (0x1d37) ++#define P_HENC_TOP_INFO_0 (volatile unsigned int *)((0x1d37 << 2) + 0xff620000) ++#define HENC_LEFT_INFO_0 (0x1d38) ++#define P_HENC_LEFT_INFO_0 (volatile unsigned int *)((0x1d38 << 2) + 0xff620000) ++// For I Slice ++// Bit[31:24] V_nnz ++// Bit[23:16] U_nnz ++// Bit[15:0] Y_nnz ++#define HENC_TOP_INFO_1 (0x1d39) ++#define P_HENC_TOP_INFO_1 (volatile unsigned int *)((0x1d39 << 2) + 0xff620000) ++#define HENC_LEFT_INFO_1 (0x1d3a) ++#define P_HENC_LEFT_INFO_1 (volatile unsigned int *)((0x1d3a << 2) + 0xff620000) ++// bit[63:0] ipred_mode ++#define VLC_IPRED_MODE_HI (0x1d3b) ++#define P_VLC_IPRED_MODE_HI (volatile unsigned int *)((0x1d3b << 2) + 0xff620000) ++#define VLC_IPRED_MODE_LO (0x1d3c) ++#define P_VLC_IPRED_MODE_LO (volatile unsigned int *)((0x1d3c << 2) + 0xff620000) ++// bit[15:8] SE delta quant ++// bit[7:0] UE delta quant ++#define VLC_DELTA_QP (0x1d3d) ++#define P_VLC_DELTA_QP (volatile unsigned int *)((0x1d3d << 2) + 0xff620000) ++// bit[31:16] Reserved ++// bit[15:12] Reserved ++// bit[11:8] c_ipred_mode ++// bit[7:0] cbp ++#define VLC_MB_HEADER_INFO (0x1d3e) ++#define P_VLC_MB_HEADER_INFO (volatile unsigned int *)((0x1d3e << 2) + 0xff620000) ++// bit[31:16] mb_skip_run ++// bit[15:0] b8_mode ++#define VLC_P_MB_HEADER_INFO (0x1d3f) ++#define P_VLC_P_MB_HEADER_INFO (volatile unsigned int *)((0x1d3f << 2) + 0xff620000) ++// bit[31] write_ptr_update ++// bit[30] read_ptr_update ++// bit[29:20] coeff_buf_level ++// bit[19:10] coeff_buf_write_ptr ++// bit[9:0] coeff_buf_read_ptr ++#define VLC_COEFF_BUF_STATUS (0x1d40) ++#define P_VLC_COEFF_BUF_STATUS (volatile unsigned int *)((0x1d40 << 2) + 0xff620000) ++// bit[31:10] Reserved ++// bit[9:0] read_req_addr ++#define VLC_COEFF_RD_REQ (0x1d41) ++#define P_VLC_COEFF_RD_REQ (volatile unsigned int *)((0x1d41 << 2) + 0xff620000) ++// bit[20] - coeff_buf_read_finished ++// bit[19] - coeff_first ++// bit[18:4] - coeff_level ++// bit[3:0] - coeff_run ++#define VLC_COEFF (0x1d42) ++#define P_VLC_COEFF (volatile unsigned int *)((0x1d42 << 2) + 0xff620000) ++// bit[31] - coeff_info_ready ++// bit[30:25] - Reserved ++// bit[24:15] - block_begin_addr ++// bit[14:11] - trailing_one_sign ++// bit[10:6] - total_coeff ++// bit[5:4] - trailing_ones ++// bit[3:0] - total_zeros ++#define VLC_COEFF_INFO (0x1d43) ++#define P_VLC_COEFF_INFO (volatile unsigned int *)((0x1d43 << 2) + 0xff620000) ++// bit[31] write_ptr_update ++// bit[30] read_ptr_update ++// bit[29:25] Reserved ++// bit[24:20] dc_buf_level -- 0-16 ++// bit[19:15] Reserved ++// bit[14:10] dc_buf_write_ptr ++// bit[9:5] Reserved ++// bit[4:0] dc_buf_read_ptr ++#define VLC_DC_BUF_STATUS (0x1d44) ++#define P_VLC_DC_BUF_STATUS (volatile unsigned int *)((0x1d44 << 2) + 0xff620000) ++// bit[31:10] Reserved ++// bit[9:4] Reserved ++// bit[3:0] read_req_addr ++#define VLC_DC_RD_REQ (0x1d45) ++#define P_VLC_DC_RD_REQ (volatile unsigned int *)((0x1d45 << 2) + 0xff620000) ++// bit[31:17] - Reserved ++// bit[16] - dc_first ++// bit[15:1] - dc_level ++// bit[0] - dc_type 0 - CDC, 1 - LDC ++#define VLC_DC (0x1d46) ++#define P_VLC_DC (volatile unsigned int *)((0x1d46 << 2) + 0xff620000) ++// bit[31] - dc_info_ready ++// bit[30:25] - Reserved ++// bit[24:20] - Reserved ++// bit[19:15] - dc_idx_begin_addr ++// bit[14:11] - dc_trailing_one_sign ++// bit[10:6] - dc_total_coeff ++// bit[5:4] - dc_trailing_ones ++// bit[3:0] - dc_total_zeros ++#define VLC_DC_INFO (0x1d47) ++#define P_VLC_DC_INFO (volatile unsigned int *)((0x1d47 << 2) + 0xff620000) ++// bit[31:4] - Reserved ++// bit[3:0] - mv_rw_idx (auto increment when read/write VLC_MV) ++#define VLC_MV_INDEX (0x1d48) ++#define P_VLC_MV_INDEX (volatile unsigned int *)((0x1d48 << 2) + 0xff620000) ++// bit[31:16] - MVY ++// bit[15:0] - MVX ++#define VLC_MV (0x1d49) ++#define P_VLC_MV (volatile unsigned int *)((0x1d49 << 2) + 0xff620000) ++// bit[31:16] - MVY ++// bitp15:0] - MVX ++// Write to HENC_TOP_MV_0 will cause previous U->UL, UR->U, and UR write ++// Read will read U MV only ++#define HENC_TOP_MV_0 (0x1d4a) ++#define P_HENC_TOP_MV_0 (volatile unsigned int *)((0x1d4a << 2) + 0xff620000) ++#define HENC_TOP_MV_1 (0x1d4b) ++#define P_HENC_TOP_MV_1 (volatile unsigned int *)((0x1d4b << 2) + 0xff620000) ++#define HENC_TOP_MV_2 (0x1d4c) ++#define P_HENC_TOP_MV_2 (volatile unsigned int *)((0x1d4c << 2) + 0xff620000) ++#define HENC_TOP_MV_3 (0x1d4d) ++#define P_HENC_TOP_MV_3 (volatile unsigned int *)((0x1d4d << 2) + 0xff620000) ++#define HENC_LEFT_MV_0 (0x1d4e) ++#define P_HENC_LEFT_MV_0 (volatile unsigned int *)((0x1d4e << 2) + 0xff620000) ++#define HENC_LEFT_MV_1 (0x1d4f) ++#define P_HENC_LEFT_MV_1 (volatile unsigned int *)((0x1d4f << 2) + 0xff620000) ++#define HENC_LEFT_MV_2 (0x1d50) ++#define P_HENC_LEFT_MV_2 (volatile unsigned int *)((0x1d50 << 2) + 0xff620000) ++#define HENC_LEFT_MV_3 (0x1d51) ++#define P_HENC_LEFT_MV_3 (volatile unsigned int *)((0x1d51 << 2) + 0xff620000) ++// Bit[31:1] Reserved ++// Bit[0] top_left_mv_ready ++#define TOP_LEFT_READY (0x1d52) ++#define P_TOP_LEFT_READY (volatile unsigned int *)((0x1d52 << 2) + 0xff620000) ++// Bit[31:16] Reserved ++// Bit[15:0] mb_skip_run ++#define MB_SKIP_RUN (0x1d53) ++#define P_MB_SKIP_RUN (volatile unsigned int *)((0x1d53 << 2) + 0xff620000) ++// Bit[31:16] Reserved ++// Bit[15] Reserved ++// Bit[14:13] rd_struct // 00 - frame, 10 - top field, 11 - bottom field ++// Bit[12:11] wr_struct // 00 - frame, 10 - top field, 11 - bottom field ++// Bit[10:5] mv_buff_id ++// Bit[4:0] mv_ref ++#define VLC_HCMD_CONFIG (0x1d54) ++#define P_VLC_HCMD_CONFIG (volatile unsigned int *)((0x1d54 << 2) + 0xff620000) ++// Bit[9:0] h264_dblk_info ++#define VLC_HCMD_DBLK_INFO (0x1d55) ++#define P_VLC_HCMD_DBLK_INFO (volatile unsigned int *)((0x1d55 << 2) + 0xff620000) ++// Bit[3:0] vlc_dbg_idx ++#define VLC_DBG_IDX (0x1d56) ++#define P_VLC_DBG_IDX (volatile unsigned int *)((0x1d56 << 2) + 0xff620000) ++// Read Only ++#define VLC_DBG_READ (0x1d57) ++#define P_VLC_DBG_READ (volatile unsigned int *)((0x1d57 << 2) + 0xff620000) ++// [ 29] RW jpeg_comp2_ac_table_sel. Default 0. ++// [ 28] RW jpeg_comp2_dc_table_sel. Default 0. ++// [26:25] RW jpeg_comp2_cnt_max. Default 0. ++// [ 24] RW jpeg_comp2_en. Set 1 if the scan will include component 2 (Cr). Default 0. ++// [ 21] RW jpeg_comp1_ac_table_sel. Default 0. ++// [ 20] RW jpeg_comp1_dc_table_sel. Default 0. ++// [18:17] RW jpeg_comp1_cnt_max. Default 0. ++// [ 16] RW jpeg_comp1_en. Set 1 if the scan will include component 1 (Cb). Default 0. ++// [ 13] RW jpeg_comp0_ac_table_sel. Default 0. ++// [ 12] RW jpeg_comp0_dc_table_sel. Default 0. ++// [10: 9] RW jpeg_comp0_cnt_max. Default 0. ++// [ 8] RW jpeg_comp0_en. Set 1 if the scan will include component 0 (Y). Default 0. ++// [ 1] W jpeg_coeff_init. Write 1 to this bit to initialize JPEG run length encoder. ++// [ 0] RW jpeg_en. 0=Disable JPEG encoder; 1=Enable JPEG encoder. Default 0. ++#define VLC_JPEG_CTRL (0x1d58) ++#define P_VLC_JPEG_CTRL (volatile unsigned int *)((0x1d58 << 2) + 0xff620000) ++// [ 13] RW jpeg_coeff_buf_overfl. Write this bit to 1 to clear overfl. ++// [ 12] RW jpeg_coeff_buf_undrfl. Write this bit to 1 to clear undrfl. ++// [ 11] R jpeg_coeff_buf_full. ++// [ 10] R jpeg_coeff_buf_empty. ++// [ 8: 0] R jpeg_coeff_buf_level. ++#define VLC_JPEG_COEFF_BUF_STAT (0x1d59) ++#define P_VLC_JPEG_COEFF_BUF_STAT (volatile unsigned int *)((0x1d59 << 2) + 0xff620000) ++// [ 16] RW JPEG HUFFMAN table access mode. 0=Write; 1=Read. Default 1. ++// [ 8: 0] RW JPEG HUFFMAN table addr. Default 0. ++#define VLC_HUFFMAN_ADDR (0x1d5a) ++#define P_VLC_HUFFMAN_ADDR (volatile unsigned int *)((0x1d5a << 2) + 0xff620000) ++// [19: 0] RW JPEG HUFFMAN table data. ++#define VLC_HUFFMAN_DATA (0x1d5b) ++#define P_VLC_HUFFMAN_DATA (volatile unsigned int *)((0x1d5b << 2) + 0xff620000) ++// bit[31:0] enc_mv_bits - including b8_mode and mvd ++#define VLC_ENC_MV_BITS (0x1d5c) ++#define P_VLC_ENC_MV_BITS (volatile unsigned int *)((0x1d5c << 2) + 0xff620000) ++// bit[31:0] enc_coeff_bits - including cbp, token, trailing_sign, coeff_enc, h264_totzeros, h264_run ++#define VLC_ENC_COEFF_BITS (0x1d5d) ++#define P_VLC_ENC_COEFF_BITS (volatile unsigned int *)((0x1d5d << 2) + 0xff620000) ++// ++// Closing file: vlc_regs.h ++// ++//------------------------------------------------------------------------------ ++// QDCT module level register offset ++//------------------------------------------------------------------------------ ++// ++// Reading file: qdct_regs.h ++// ++//======================================================================== ++// QDCT module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HCODEC_QDCT_CBUS_BASE = 0x0f ++// ----------------------------------------------- ++// bit[31:28] - mb_info_state ++#define QDCT_STATUS_CTRL (0x1f00) ++#define P_QDCT_STATUS_CTRL (volatile unsigned int *)((0x1f00 << 2) + 0xff620000) ++// bit[18] - enable_free_clk_sad_top ++// bit[17] - enable_free_clk_ie_top ++// bit[16] - enable_free_clk_ie_sub ++// bit[15] - enable_free_clk_mc_out ++// bit[14] - enable_free_clk_i_pred_top ++// bit[13] - enable_free_clk_idct_top ++// bit[12] - enable_free_clk_iq_top ++// bit[11] - enable_free_clk_q_top ++// bit[10] - enable_free_clk_dc_buff_8 ++// bit[9] - enable_free_clk_dct_top ++// bit[8] - enable_free_clk_mb_info ++// bit[7] - enable_free_clk_mb_buff ++// bit[6] - enable_free_clk_reg ++// bit[5] - ignore_1_include_2nd_half_c ++// bit[4] - ignore_1_include_2nd_half ++// bit[3] - ignore_t_p8x8 ++// bit[2] - not_ignore_dc ++// bit[1] - ignore_small_lac_intra ++// bit[0] - disable_fast_zero_block ++#define QDCT_CONFIG (0x1f01) ++#define P_QDCT_CONFIG (volatile unsigned int *)((0x1f01 << 2) + 0xff620000) ++// bit[31] - ignore_lac_coeff_en ++// bit[30:26] - ignore_lac_coeff_else ++// bit[25:21] - ignore_lac_coeff_2 ++// bit[20:16] - ignore_lac_coeff_1 ++// bit[15] - ignore_cac_coeff_en ++// bit[14:10] - ignore_cac_coeff_else ++// bit[9:5] - ignore_cac_coeff_2 ++// bit[4:0] - ignore_cac_coeff_1 ++#define IGNORE_CONFIG (0x1f02) ++#define P_IGNORE_CONFIG (volatile unsigned int *)((0x1f02 << 2) + 0xff620000) ++// bit[31] - ignore_t_lac_coeff_en ++// bit[30:26] - ignore_t_lac_coeff_else ++// bit[25:21] - ignore_t_lac_coeff_2 ++// bit[20:16] - ignore_t_lac_coeff_1 ++// bit[15] - ignore_cdc_coeff_en ++// bit[14] - ignore_t_lac_coeff_else_le_3 ++// bit[13] - ignore_t_lac_coeff_else_le_4 ++// bit[12] - ignore_cdc_only_when_empty_cac_inter ++// bit[11] - ignore_cdc_only_when_one_empty_inter ++// bit[10:9] - ignore_cdc_range_max_inter // 0-0, 1-1, 2,-2, 3-3 ++// bit[8:7] - ignore_cdc_abs_max_inter // 0-1, 1-2, 2,-3, 3-4 ++// bit[6] - reserved ++// bit[5] - ignore_cdc_only_when_empty_cac_intra ++// bit[4] - ignore_cdc_only_when_one_empty_intra ++// bit[3:2] - ignore_cdc_range_max_intra // 0-0, 1-1, 2,-2, 3-3 ++// bit[1:0] - ignore_cdc_abs_max_intra // 0-1, 1-2, 2,-3, 3-4 ++#define IGNORE_CONFIG_2 (0x1f03) ++#define P_IGNORE_CONFIG_2 (volatile unsigned int *)((0x1f03 << 2) + 0xff620000) ++// -------------------------------------------- ++// MB DATA DDR Interface ++// -------------------------------------------- ++#define QDCT_MB_START_PTR (0x1f10) ++#define P_QDCT_MB_START_PTR (volatile unsigned int *)((0x1f10 << 2) + 0xff620000) ++#define QDCT_MB_END_PTR (0x1f11) ++#define P_QDCT_MB_END_PTR (volatile unsigned int *)((0x1f11 << 2) + 0xff620000) ++#define QDCT_MB_WR_PTR (0x1f12) ++#define P_QDCT_MB_WR_PTR (volatile unsigned int *)((0x1f12 << 2) + 0xff620000) ++#define QDCT_MB_RD_PTR (0x1f13) ++#define P_QDCT_MB_RD_PTR (volatile unsigned int *)((0x1f13 << 2) + 0xff620000) ++#define QDCT_MB_LEVEL (0x1f14) ++#define P_QDCT_MB_LEVEL (volatile unsigned int *)((0x1f14 << 2) + 0xff620000) ++// bit [31] disable_mbxy_ie_save ++// bit [30] no_wait_after_q_cdc ++// bit [29] ie_start_int_enable ++// bit [28] ignore_t_p8x8 ++// bit [27] zero_mc_out_null_non_skipped_mb ++// bit [26] no_mc_out_null_non_skipped_mb ++// bit [25] mc_out_even_skipped_mb ++// bit [24] mc_out_wait_cbp_ready ++// bit [23] mc_out_wait_mb_type_ready ++// bit [22] i_pred_int_enable ++// bit [21] intra_sat8_enable ++// bit [20] ie_sub_enable ++// bit [19] i_pred_enable ++// bit [18] iq_enable ++// bit [17] idct_enable ++// bit [16] no_zero_coeff_mb ++// bit [15] add_zero_coeff_block ++// bit [14] mb_pause_enable ++// bit [13] q_enable ++// bit [12] dct_enable ++// bit [11] ignore_magic_word ++// bit [10] mb_info_en ++// bit [9] mb_info_soft_reset ++// bit [8] mb_always_ready Set to 1 to ignore mb_level blocking DDR read ++// bit [7] mb_ready_for_transfer (Read Only) ++// bit [6] data_ready_for_transfer (Read Only) ++// bits [5:3] mb_endian Set MB Endian inside DDR memory ++// bit [2] mb_read_busy Read Only - indicate DDR read busy ++// bit [1] mb_read_en Set to 1 to enable reading data from DDR memory ++// bit [0] mb_soft_reset Soft reset ++#define QDCT_MB_CONTROL (0x1f15) ++#define P_QDCT_MB_CONTROL (volatile unsigned int *)((0x1f15 << 2) + 0xff620000) ++// bit 31 transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request // default : 0 ++// bit 30 A_urgent // default : 0 ++// bit 29:24 A_brst_num // default : 0x3f ++// bit 23 reserved ++// bit 22 read_till_zero ++// bit 21:16 A_id // default : 0x21 ++// bit 15:0 mb_level_hold // default : 0 ++#define QDCT_MB_MEM_CTL (0x1f16) ++#define P_QDCT_MB_MEM_CTL (volatile unsigned int *)((0x1f16 << 2) + 0xff620000) ++// bit [31:24] reserved ++// bit [23:16] vb_buff_level -- Read only ++// bit [15:8] vb_buff_wr_point -- RW ++// bit [7:0] vb_buff_rd_point -- RW ++#define QDCT_MB_BUFF (0x1f17) ++#define P_QDCT_MB_BUFF (volatile unsigned int *)((0x1f17 << 2) + 0xff620000) ++// bit [31:0] mb infor data begin magic word - default : 0xa55aaa55 ++#define QDCT_MB_MAGIC_WORD (0x1f18) ++#define P_QDCT_MB_MAGIC_WORD (volatile unsigned int *)((0x1f18 << 2) + 0xff620000) ++// Read Only Register ++// bit[19] dct_ready_1 ++// bit[18] dct_ready_0 ++// bit[17] dct_rd_idx ++// bit[16] dct_wr_idx ++// bit[15] dct_srdy ++// bit[14] dct_rrdy ++// bit[13] Reserved ++// bit[12:8] dct_block_number ++// bit[7:4] dct_rw_addr ++// bit[3:0] dct_status ++#define QDCT_DCT_STATUS (0x1f19) ++#define P_QDCT_DCT_STATUS (volatile unsigned int *)((0x1f19 << 2) + 0xff620000) ++// bit[24:23] vlc_quant_count ++// bit[22:16] vlc_delta_quant_data ++// bit[15:10] vlc_quant_data ++// bit[9:4] vlc_prev_quant_data ++// bit[3:0] q_status ++#define QDCT_Q_STATUS (0x1f1a) ++#define P_QDCT_Q_STATUS (volatile unsigned int *)((0x1f1a << 2) + 0xff620000) ++// bit[31:3] Reserved ++// bit[2:0] picture_type ++#define QDCT_PIC_INFO (0x1f1b) ++#define P_QDCT_PIC_INFO (volatile unsigned int *)((0x1f1b << 2) + 0xff620000) ++// bit[31:28] Reserved ++// bit[27:22] I_pic_quant_c ++// bit[21:16] I_pic_quant ++// bit[15] reserved ++// bit[14:12] quant_rem_c ++// bit[11:8] quant_per_c ++// bit[7] reserved ++// bit[6:4] quant_rem ++// bit[3:0] quant_per ++#define QDCT_Q_QUANT_I (0x1f1c) ++#define P_QDCT_Q_QUANT_I (volatile unsigned int *)((0x1f1c << 2) + 0xff620000) ++// bit[31:28] Reserved ++// bit[27:22] P_pic_quant_c ++// bit[21:16] P_pic_quant ++// bit[15] reserved ++// bit[14:12] quant_rem_c ++// bit[11:8] quant_per_c ++// bit[7] reserved ++// bit[6:4] quant_rem ++// bit[3:0] quant_per ++#define QDCT_Q_QUANT_P (0x1f1d) ++#define P_QDCT_Q_QUANT_P (volatile unsigned int *)((0x1f1d << 2) + 0xff620000) ++// bit[31] mb_info_pause ++// bit[30:16] pause_mby ++// bit[15:0] pause_mbx ++#define QDCT_MB_PAUSE_CTL (0x1f1e) ++#define P_QDCT_MB_PAUSE_CTL (volatile unsigned int *)((0x1f1e << 2) + 0xff620000) ++// bit[31] top_control_ready_i_pred ++// bit[30:28]top_dma_status ++// bit[27] top_control_ready_ie ++// bit[26:24]Reserved ++// bit[23] ul_mb ++// bit[22] right_mb ++// bit[21] top_mb ++// bit[20] left_mb ++// bit[19:8] mb_x ++// bit[7:6] i_pred_ref_idx_L ++// bit[5:4] i_pred_ref_idx_UL ++// bit[3:2] i_pred_ref_idx_U ++// bit[1:0] i_pred_ref_idx_UR ++#define QDCT_TOP_CONTROL (0x1f1f) ++#define P_QDCT_TOP_CONTROL (volatile unsigned int *)((0x1f1f << 2) + 0xff620000) ++// bit[31:0] top_base_addr - DDR Memory start address for save top Pixel ++#define QDCT_TOP_BASE_MEM (0x1f20) ++#define P_QDCT_TOP_BASE_MEM (volatile unsigned int *)((0x1f20 << 2) + 0xff620000) ++// bit 15:13 Reserved ++// bit 12 A_urgent // default : 0 ++// bit 11:6 A_brst_num // default : 0x3f ++// bit 5:0 A_id // default : 0x22 ++#define QDCT_TOP_MEM_CTL (0x1f21) ++#define P_QDCT_TOP_MEM_CTL (volatile unsigned int *)((0x1f21 << 2) + 0xff620000) ++// bit [11:0] top_wrrsp_count ++#define QDCT_TOP_WRRSP (0x1f22) ++#define P_QDCT_TOP_WRRSP (volatile unsigned int *)((0x1f22 << 2) + 0xff620000) ++// Bit[3:0] qdct_dbg_idx ++#define QDCT_DBG_IDX (0x1f23) ++#define P_QDCT_DBG_IDX (volatile unsigned int *)((0x1f23 << 2) + 0xff620000) ++// Read Only ++#define QDCT_DBG_READ (0x1f24) ++#define P_QDCT_DBG_READ (volatile unsigned int *)((0x1f24 << 2) + 0xff620000) ++// [19:18] RW jdct_inflow_ctrl. JPEG DCT input flow control. Default 0. ++// 0=No halt; ++// 1=DCT halts request at end of each 8x8 block; ++// 2=DCT halts request at end of each MCU. ++// [17:16] RW jpeg_coeff_last_sel. Default 0. ++// Select at which point to finish processing, give update to AmRISC so it can control the next step. ++// 0=Mark last coeff at the end of an 8x8 block; ++// 1=Mark at the end of an MCU; ++// 2=Mark at the end of a scan. ++// [ 15] RW jpeg_quant_sel_comp2. 0=Comp2 select Quantization table 0; 1=Select table 1. Default 0. ++// [ 14] RW jpeg_v_factor_comp2. Component 2's vertical sampling factor. Default 0. ++// [ 13] RW jpeg_h_factor_comp2. Component 2's horizontal sampling factor. Default 0. ++// [ 12] RW jpeg_comp2_en. Set 1 if the scan will include component 2 (Cr). Default 0. ++// [ 11] RW jpeg_quant_sel_comp1. 0=Comp1 select Quantization table 0; 1=Select table 1. Default 0. ++// [ 10] RW jpeg_v_factor_comp1. Component 1's vertical sampling factor. Default 0. ++// [ 9] RW jpeg_h_factor_comp1. Component 1's horizontal sampling factor. Default 0. ++// [ 8] RW jpeg_comp1_en. Set 1 if the scan will include component 1 (Cb). Default 0. ++// [ 7] RW jpeg_quant_sel_comp0. 0=Comp0 select Quantization table 0; 1=Select table 1. Default 0. ++// [ 6] RW jpeg_v_factor_comp0. Component 0's vertical sampling factor. Default 0. ++// [ 5] RW jpeg_h_factor_comp0. Component 0's horizontal sampling factor. Default 0. ++// [ 4] RW jpeg_comp0_en. Set 1 if the scan will include component 0 (Y). Default 0. ++// [ 3: 1] RW jdct_intr_sel. JPEG DCT interrupt select. Default 0. ++// 0=Disable intr; ++// 1=Intr at end of each 8x8 block of DCT input; ++// 2=Intr at end of each MCU of DCT input; ++// 3=Intr at end of a scan of DCT input; ++// 4=Intr at end of each 8x8 block of DCT output; ++// 5=Intr at end of each MCU of DCT output; ++// 6=Intr at end of a scan of DCT output. ++// [ 0] RW jpeg_en. 0=Disable JPEG QDCT; 1=Enable JPEG QDCT. Default 0. ++#define QDCT_JPEG_CTRL (0x1f25) ++#define P_QDCT_JPEG_CTRL (volatile unsigned int *)((0x1f25 << 2) + 0xff620000) ++// [29:16] RW jpeg_x_end. Picture X end. Default 0. ++// [13: 0] RW jpeg_x_start. Picture X start. Default 0. ++#define QDCT_JPEG_X_START_END (0x1f26) ++#define P_QDCT_JPEG_X_START_END (volatile unsigned int *)((0x1f26 << 2) + 0xff620000) ++// [29:16] RW jpeg_y_end. Picture Y end. Default 0. ++// [13: 0] RW jpeg_y_start. Picture Y start. Default 0. ++#define QDCT_JPEG_Y_START_END (0x1f27) ++#define P_QDCT_JPEG_Y_START_END (volatile unsigned int *)((0x1f27 << 2) + 0xff620000) ++// [ 8] RW JPEG QUANT table access mode. 0=Write; 1=Read. Default 1. ++// [ 5: 0] RW JPEG QUANT table addr. Default 0. ++#define QDCT_JPEG_QUANT_ADDR (0x1f28) ++#define P_QDCT_JPEG_QUANT_ADDR (volatile unsigned int *)((0x1f28 << 2) + 0xff620000) ++// [31: 0] RW JPEG QUANT table data. ++#define QDCT_JPEG_QUANT_DATA (0x1f29) ++#define P_QDCT_JPEG_QUANT_DATA (volatile unsigned int *)((0x1f29 << 2) + 0xff620000) ++// [ 1] W resume_jdct. ++// Write 1 to this bit will resume JPEG input engine when previously ++// it is halted by QDCT_JPEG_CTRL.jdct_inflow_ctrl. ++// [ 0] W jpeg_sof. ++// Write 1 to this bit will start JPEG input engine. ++#define QDCT_JPEG_SOF_RESUME (0x1f2a) ++#define P_QDCT_JPEG_SOF_RESUME (volatile unsigned int *)((0x1f2a << 2) + 0xff620000) ++// [31:30] R dct_st. jdct_ctrl state. 0=IDLE; 1=WAIT; 2=DCT_REQ. ++// [29:28] R mfdin_comp. Current component at pixel request to MFDIN. ++// [27:14] R mfdin_y. Current Y at pixel request to MFDIN. ++// [13: 0] R mfdin_x. Current X at pixel request to MFDIN. ++#define QDCT_JPEG_DCT_STATUS0 (0x1f2b) ++#define P_QDCT_JPEG_DCT_STATUS0 (volatile unsigned int *)((0x1f2b << 2) + 0xff620000) ++// [15:12] R JPEG Quant read MEM select. ++// [11: 8] R JPEG DCT2 write MEM select. ++// [ 7: 4] R JPEG DCT2 read MEM select. ++// [ 3: 0] R JPEG DCT1 write MEM select. ++#define QDCT_JPEG_DCT_STATUS1 (0x1f2c) ++#define P_QDCT_JPEG_DCT_STATUS1 (volatile unsigned int *)((0x1f2c << 2) + 0xff620000) ++// [28:16] RW jdct_coeff1. Default 13'h1D90; // 7568 = 4096 * sqrt(2) * (cos(Pi/8) + sin(Pi/8)) // 7569 ++// [12: 0] RW jdct_coeff0. Default 13'h16A1; // 5793 = 4096 * sqrt(2) ++#define QDCT_JPEG_DCT_COEFF01 (0x1f2d) ++#define P_QDCT_JPEG_DCT_COEFF01 (volatile unsigned int *)((0x1f2d << 2) + 0xff620000) ++// [28:16] RW jdct_coeff3. Default 13'h0C3F; // 3135 = 4096 * sqrt(2) * (cos(Pi/8) - sin(Pi/8)) ++// [12: 0] RW jdct_coeff2. Default 13'h08A9; // 2217 = 4096 * sqrt(2) * sin(Pi/8) // 2215 ++#define QDCT_JPEG_DCT_COEFF23 (0x1f2e) ++#define P_QDCT_JPEG_DCT_COEFF23 (volatile unsigned int *)((0x1f2e << 2) + 0xff620000) ++// [28:16] RW jdct_coeff5. Default 13'h046A; // 1130 = 4096 * (cos(3Pi/16) - sin(3Pi/16)) ++// [12: 0] RW jdct_coeff4. Default 13'h1631; // 5681 = 4096 * (cos(3Pi/16) + sin(3Pi/16)) // 5682 ++#define QDCT_JPEG_DCT_COEFF45 (0x1f2f) ++#define P_QDCT_JPEG_DCT_COEFF45 (volatile unsigned int *)((0x1f2f << 2) + 0xff620000) ++// [28:16] RW jdct_coeff7. Default 13'h0C92; // 3218 = 4096 * (cos(Pi/16) - sin(Pi/16)) ++// [12: 0] RW jdct_coeff6. Default 13'h12D0; // 4816 = 4096 * (cos(Pi/16) + sin(Pi/16)) ++#define QDCT_JPEG_DCT_COEFF67 (0x1f30) ++#define P_QDCT_JPEG_DCT_COEFF67 (volatile unsigned int *)((0x1f30 << 2) + 0xff620000) ++// [28:16] RW jdct_coeff9. Default 13'h0FB1; // 4017 = 4096 * cos(Pi/16) ++// [12: 0] RW jdct_coeff8. Default 13'h0D4E; // 3406 = 4096 * cos(3Pi/16) ++#define QDCT_JPEG_DCT_COEFF89 (0x1f31) ++#define P_QDCT_JPEG_DCT_COEFF89 (volatile unsigned int *)((0x1f31 << 2) + 0xff620000) ++#define QDCT_I_PRED_REF_WR_IDX (0x1f32) ++#define P_QDCT_I_PRED_REF_WR_IDX (volatile unsigned int *)((0x1f32 << 2) + 0xff620000) ++#define QDCT_I_PRED_REF_WR_DATA (0x1f33) ++#define P_QDCT_I_PRED_REF_WR_DATA (volatile unsigned int *)((0x1f33 << 2) + 0xff620000) ++// bit[29] mb_info_latch_no_I16_pred_mode ++// bit[28] ie_dma_mbxy_use_i_pred ++// bit[27] ie_dma_read_write_use_ip_idx ++// bit[26] ie_start_use_top_dma_count ++// bit[25] i_pred_top_dma_rd_mbbot ++// bit[24] i_pred_top_dma_wr_disable ++// bit[23] i_pred_mix ++// bit[22] me_ab_rd_when_intra_in_p ++// bit[21] force_mb_skip_run_when_intra ++// bit[20] mc_out_mixed_type ++// bit[19] ie_start_when_quant_not_full ++// bit[18] mb_info_state_mix ++// bit[17] mb_type_use_mix_result ++// bit[16] me_cb_ie_read_enable ++// bit[15] ie_cur_data_from_me ++// bit[14] rem_per_use_table ++// bit[13] q_latch_int_enable ++// bit[12] q_use_table ++// bit[11] q_start_wait ++// bit[10] LUMA_16_LEFT_use_cur ++// bit[9] DC_16_LEFT_SUM_use_cur ++// bit[8] c_ref_ie_sel_cur ++// bit[7] c_ipred_perfect_mode ++// bit[6] ref_ie_ul_sel 0-old, 1-use next_set ++// bit[5] mb_type_use_ie_result ++// bit[4] detect_I16_from_I4 ++// bit[3] ie_not_wait_ref_busy ++// bit[2] ie_I16_enable ++// bit[1:0] ie_done_sel (0, 1, 2, -1) ++#define QDCT_ADV_CONFIG (0x1f34) ++#define P_QDCT_ADV_CONFIG (volatile unsigned int *)((0x1f34 << 2) + 0xff620000) ++// bit [31:16] I16x16_weight ++// bit [15:0] I4x4_weight ++#define IE_WEIGHT (0x1f35) ++#define P_IE_WEIGHT (volatile unsigned int *)((0x1f35 << 2) + 0xff620000) ++// bit [31] reserved ++// bit [30] q_I16MB ++// bit [29] reserved ++// bit [28] reserved ++// bit [27:23] quant_table_addr I4MB:[0,7], I16MB:[8:15], INTER:[16:23], Reserved:[24:31] ++// bit [22] quant_table_addr_update(when notupdate_rem_per) (read is arb_result : q_intra) ++// bit [21:19] quant_rem_c ++// bit [18:16] quant_rem_y ++// bit [15:12] quant_per_c ++// bit [11:8] quant_per_y ++// bit [7:2] quant ++// bit [1] update_rem_per ++// bit [0] clear_wait_status ++#define Q_QUANT_CONTROL (0x1f36) ++#define P_Q_QUANT_CONTROL (volatile unsigned int *)((0x1f36 << 2) + 0xff620000) ++#define MBBOT_EVEN_ADDR (0x1f37) ++#define P_MBBOT_EVEN_ADDR (volatile unsigned int *)((0x1f37 << 2) + 0xff620000) ++#define MBBOT_ODD_ADDR (0x1f38) ++#define P_MBBOT_ODD_ADDR (volatile unsigned int *)((0x1f38 << 2) + 0xff620000) ++// bit [29:24] quant_table_data_3 ++// bit [21:16] quant_table_data_2 ++// bit [13:8] quant_table_data_1 ++// bit [5:0] quant_table_data_0 ++#define QUANT_TABLE_DATA (0x1f39) ++#define P_QUANT_TABLE_DATA (volatile unsigned int *)((0x1f39 << 2) + 0xff620000) ++// bit [31:16] ie_sad_offset_I16 ++// bit [15:0] ie_sad_offset_I4 ++#define SAD_CONTROL_0 (0x1f3a) ++#define P_SAD_CONTROL_0 (volatile unsigned int *)((0x1f3a << 2) + 0xff620000) ++// bit [31] sad_soft_reset ++// bit [30:27] reserved ++// bit [26:24] ie_sad_shift_I16 ++// bit [22:20] ie_sad_shift_I4 ++// bit [18:16] me_sad_shift_INTER ++// bit [15:0] me_sad_offset_INTER ++#define SAD_CONTROL_1 (0x1f3b) ++#define P_SAD_CONTROL_1 (volatile unsigned int *)((0x1f3b << 2) + 0xff620000) ++// bit [31] vlc_quant_rd_ptr ++// bit [30] vlc_quant_rd_ptr_update ++// bit [29] vlc_quant_wr_ptr ++// bit [28] vlc_quant_wr_ptr_update ++// bit [27:26] reserved ++// bit [25:19] vlc_delta_quant_1 ++// bit [18:13] vlc_quant_1 ++// bit [12:6] vlc_delta_quant_0 ++// bit [5:0] vlc_quant_0 ++#define QDCT_VLC_QUANT_CTL_0 (0x1f3c) ++#define P_QDCT_VLC_QUANT_CTL_0 (volatile unsigned int *)((0x1f3c << 2) + 0xff620000) ++// bit [31:30] me_sad_rd_idx ++// bit [29] me_sad_rd_idx_update ++// bit [28:27] me_sad_wr_idx ++// bit [26] me_sad_wr_idx_update ++// bit [25:24] ie_sad_rd_idx ++// bit [23] ie_sad_rd_idx_update ++// bit [22:21] ie_sad_wr_idx ++// bit [20] ie_sad_wr_idx_update ++// bit [19:12] Reserved ++// bit [11:6] vlc_max_delta_q_neg ++// bit [5:0] vlc_max_delta_q_pos ++#define QDCT_VLC_QUANT_CTL_1 (0x1f3d) ++#define P_QDCT_VLC_QUANT_CTL_1 (volatile unsigned int *)((0x1f3d << 2) + 0xff620000) ++// bit[4] jdct_int ++// bit[3] quant_latch ++// bit[2] me_done ++// bit[1] ie_start ++// bit[0] i_pred_start ++#define QDCT_INT_STATUS (0x1f3e) ++#define P_QDCT_INT_STATUS (volatile unsigned int *)((0x1f3e << 2) + 0xff620000) ++// bit[3] mix_i_pred_wait_left_en ++// bit[2:0] mc_pending_mb_count ++#define QDCT_MIX_I_PRED_STATUS (0x1f3f) ++#define P_QDCT_MIX_I_PRED_STATUS (volatile unsigned int *)((0x1f3f << 2) + 0xff620000) ++// IE/ME share same cbus_base as QDCT ++// ++// bit[31] active_ur_block ++// bit[30] active_ul_block ++// bit[21] disable_HENC_V_PRED_16 ++// bit[20] disable_HENC_H_PRED_16 ++// bit[19] disable_HENC_DC_PRED_16 ++// bit[18] disable_HENC_HENC_HOR_UP_PRED ++// bit[17] disable_HENC_VERT_LEFT_PRED ++// bit[16] disable_HENC_HENC_HOR_DOWN_PRED ++// bit[15] disable_HENC_VERT_RIGHT_PRED ++// bit[14] disable_HENC_DIAG_DOWN_RIGHT_PRED ++// bit[13] disable_HENC_DIAG_DOWN_LEFT_PRED ++// bit[12] disable_HENC_DC_PRED ++// bit[11] disable_HENC_HOR_PRED ++// bit[10] disable_HENC_VERT_PRED ++// bit[9] ie_c_wait_ie_pause ++// bit[8:4] max_ie_result_buff_count ++// bit[3] ie_wait_for_ie_result // use for (max_ie_result_buff_count == 0) to wait every block ++// bit[2] reserved ++// bit[1] ie_enable ++// bit[0] ie_soft_reset ++#define IE_CONTROL (0x1f40) ++#define P_IE_CONTROL (volatile unsigned int *)((0x1f40 << 2) + 0xff620000) ++// bit[31:12] Reserved ++// bit[11:0] mb_y ++#define IE_MB_POSITION (0x1f41) ++#define P_IE_MB_POSITION (volatile unsigned int *)((0x1f41 << 2) + 0xff620000) ++// bit[31:16] me_skip_run ++// bit[15:8] reserved ++// bit [7:4] me_b8_mode ++// bit [3:0] ie_me_mb_type ++#define IE_ME_MB_INFO (0x1f42) ++#define P_IE_ME_MB_INFO (volatile unsigned int *)((0x1f42 << 2) + 0xff620000) ++// bit[3] ie_result_buff_enable ++// bit[2] ie_result_buff_soft_reset ++// bit[1] sad_enable ++// bit[0] ie_sad_soft_reset ++#define SAD_CONTROL (0x1f43) ++#define P_SAD_CONTROL (volatile unsigned int *)((0x1f43 << 2) + 0xff620000) ++// bit[31:16] - ie_result_buff_count - read only ++// bit[14:12] -current_ie_result (pred_mode) - read only ++// bit[11] top_control_data_buff_wr_ptr - rd/wr ++// bit[10] top_control_data_buff_rd_ptr - rd/wr ++// bit[9:5] ie_result_buff_wr_ptr - rd/wr ++// bit[4:0] ie_result_buff_rd_ptr - rd/wr ++#define IE_RESULT_BUFFER (0x1f44) ++#define P_IE_RESULT_BUFFER (volatile unsigned int *)((0x1f44 << 2) + 0xff620000) ++// bit[63:0] ie_i4_pred_mode ++#define IE_I4_PRED_MODE_HI (0x1f45) ++#define P_IE_I4_PRED_MODE_HI (volatile unsigned int *)((0x1f45 << 2) + 0xff620000) ++#define IE_I4_PRED_MODE_LO (0x1f46) ++#define P_IE_I4_PRED_MODE_LO (volatile unsigned int *)((0x1f46 << 2) + 0xff620000) ++// bit [31:9] reserved ++// bit [8:4] i_pred_block_number ++// bit [3:0] ie_c_pred_mode ++#define IE_C_PRED_MODE (0x1f47) ++#define P_IE_C_PRED_MODE (volatile unsigned int *)((0x1f47 << 2) + 0xff620000) ++// 31:16 - Left, 0-select ie_pixel, 1-select mc_data_out ++// 15:0 - Top, 0-select ie_pixel, 1-select mc_data_out ++#define IE_CUR_REF_SEL (0x1f48) ++#define P_IE_CUR_REF_SEL (volatile unsigned int *)((0x1f48 << 2) + 0xff620000) ++// bit[31] enable_f_skip_1_step_3 ++// bit[30] enable_f_skip_1_step_2 ++// bit[29] enable_f_skip_1_step_1 ++// bit[28] step_3_enable ++// bit[27] step_2_sub_pixel ++// bit[26] always_f_skip_step_3 ++// bit[25] always_f_skip_step_2 ++// bit[24] always_f_skip_step_1 ++// bit[23] half_pixel_only ++// bit[22:13] reserved ++// bit[12] adv_mv_enable ++// bit[11] sad_short_valid ++// bit[10:9] mv_flexable_ctl 00:0x40, 01:0x80, 10:0xc0, 11 : 0x100 ++// bit[8] no_md_ab_rd ++// bit[7] use_dct_state ++// bit[6] enable_free_clk_me_ctl ++// bit[5] enable_free_clk_me_ab ++// bit[4] enable_free_clk_me_cb ++// bit[3] reserved ++// bit[2] me_done_int_enable ++// bit[1] me_enable ++// bit[0] me_soft_reset ++#define ME_CONTROL (0x1f49) ++#define P_ME_CONTROL (volatile unsigned int *)((0x1f49 << 2) + 0xff620000) ++// bit[31:28] Reserved ++// bit[27:16] me_start_mby ++// bit[15:12] Reserved ++// bit[11:0] me_start_mbx ++#define ME_START_POSITION (0x1f4a) ++#define P_ME_START_POSITION (volatile unsigned int *)((0x1f4a << 2) + 0xff620000) ++// bit [31:28] me_status - Read only ++// bit [27:24] me_cb_status // current buffer ++// bit [23:20] me_ab_status // anc buffer ++// bit [19] Reserved ++// bit [18:16] me_ab_wr_ptr // read only ++// bit [15:4] me_last_mbx ++// bit [3:1] me_ab_rd_ptr // read only ++// bit [0] me_action ++#define ME_STATUS (0x1f4b) ++#define P_ME_STATUS (volatile unsigned int *)((0x1f4b << 2) + 0xff620000) ++// all Read-only ++// bit [31:28] Reserved ++// bit [27:16] me_ab_mbx ++// bit [15:14] me_cb_wr_ptr ++// bit [13:12] me_cb_rd_ptr ++// bit [11:0] me_cb_mbx ++#define ME_DEBUG (0x1f4c) ++#define P_ME_DEBUG (volatile unsigned int *)((0x1f4c << 2) + 0xff620000) ++// bit[29:24] step_3_skip_line ++// bit[23:18] step_2_skip_line ++// bit[17:12] step_1_skip_line ++// bit[11:6] step_0_skip_line ++// bit[5:0] read_skip_line ++#define ME_SKIP_LINE (0x1f4d) ++#define P_ME_SKIP_LINE (volatile unsigned int *)((0x1f4d << 2) + 0xff620000) ++// bit 15:13 Reserved ++// bit 12 A_urgent // default : 0 ++// bit 11:6 A_brst_num // default : 0x3f ++// bit 5:0 A_id // default : 0x23 ++#define ME_AB_MEM_CTL (0x1f4e) ++#define P_ME_AB_MEM_CTL (volatile unsigned int *)((0x1f4e << 2) + 0xff620000) ++// bit[31:24] anc_pic_canvas ++// bit[23:12] max_me_mby_num ++// bit[11:0] max_me_mbx_num ++#define ME_PIC_INFO (0x1f4f) ++#define P_ME_PIC_INFO (volatile unsigned int *)((0x1f4f << 2) + 0xff620000) ++// bit [23:12] me_sad_enough_1 ++// bit [11:0] me_sad_enough_0 ++#define ME_SAD_ENOUGH_01 (0x1f50) ++#define P_ME_SAD_ENOUGH_01 (volatile unsigned int *)((0x1f50 << 2) + 0xff620000) ++// bit [25:12] adv_mv_8x8_enough ++// bit [11:0] me_sad_enough_2 ++#define ME_SAD_ENOUGH_23 (0x1f51) ++#define P_ME_SAD_ENOUGH_23 (volatile unsigned int *)((0x1f51 << 2) + 0xff620000) ++// bit [21:10] me_step0_big_sad ++// bit [9:5] me_step0_close_mv_y ++// bit [4:0] me_step0_close_mv_x ++#define ME_STEP0_CLOSE_MV (0x1f52) ++#define P_ME_STEP0_CLOSE_MV (volatile unsigned int *)((0x1f52 << 2) + 0xff620000) ++// bit[31:24] force_skip_sad_3 ++// bit[23:16] force_skip_sad_2 ++// bit[15:08] force_skip_sad_1 ++// bit[07:00] force_skip_sad_0 ++#define ME_F_SKIP_SAD (0x1f53) ++#define P_ME_F_SKIP_SAD (volatile unsigned int *)((0x1f53 << 2) + 0xff620000) ++// bit[31:24] force_skip_weight_3 ++// bit[23:16] force_skip_weight_2 ++// bit[15:08] force_skip_weight_1 ++// bit[07:00] force_skip_weight_0 ++#define ME_F_SKIP_WEIGHT (0x1f54) ++#define P_ME_F_SKIP_WEIGHT (volatile unsigned int *)((0x1f54 << 2) + 0xff620000) ++// Merge when ( ++// (flex & me_merge_flex_en) | ++// (big_sad & me_merge_sad_en)| ++// ((~me_merge_flex_en)&(~me_merge_sad_en)) ++// ) & ++// ( small_mv_diff |(~me_merge_small_mv_en)) ++// & (me_merge_flex_en | me_merge_sad_en | me_merge_small_mv_en) ++// bit[31] me_merge_mv_en_16 ++// bit[30] me_merge_small_mv_en_16 ++// bit[29] me_merge_flex_en_16 ++// bit[28] me_merge_sad_en_16 ++// bit[27] me_merge_mv_en_8 ++// bit[26] me_merge_small_mv_en_8 ++// bit[25] me_merge_flex_en_8 ++// bit[24] me_merge_sad_en_8 ++// bit[23:18] me_merge_mv_diff_16 ++// bit[17:12] me_merge_mv_diff_8 ++// bit[11:0] me_merge_min_sad ++#define ME_MV_MERGE_CTL (0x1f55) ++#define P_ME_MV_MERGE_CTL (volatile unsigned int *)((0x1f55 << 2) + 0xff620000) ++// bit[31:24] mv_step_weight_1 ++// bit[23:16] mv_pre_weight_1 ++// bit [15:0] mv_step_weight_0 ++// bit[7:0] mv_pre_weight_0 ++#define ME_MV_WEIGHT_01 (0x1f56) ++#define P_ME_MV_WEIGHT_01 (volatile unsigned int *)((0x1f56 << 2) + 0xff620000) ++// bit[31:24] mv_step_weight_3 (mv_step_weight_1_2nd) ++// bit[23:16] mv_pre_weight_3 (mv_pre_weight_1_2nd) ++// bit[15:8] mv_step_weight_2 ++// bit[7:0] mv_pre_weight_2 ++#define ME_MV_WEIGHT_23 (0x1f57) ++#define P_ME_MV_WEIGHT_23 (volatile unsigned int *)((0x1f57 << 2) + 0xff620000) ++// bit[31:24] me_sad_range_inc_3 ++// bit[23:16] me_sad_range_inc_2 ++// bit[15:8] me_sad_range_inc_1 ++// bit[7:0] me_sad_range_inc_0 ++#define ME_SAD_RANGE_INC (0x1f58) ++#define P_ME_SAD_RANGE_INC (volatile unsigned int *)((0x1f58 << 2) + 0xff620000) ++// bit[31:19] reserved ++// bit[18] sub_relative_any_1_en ++// bit[17] sub_relative_any_2_en ++// bit[16] sub_relative_any_3_en ++// bit[15] sub_relative_any_4_en ++// bit[14] sub_relative_any_h_en ++// bit[13] sub_make_non_flex_fix ++// bit[12] sub_make_big_non_flex_fix ++// bit[11:8] sub_normal_mv_diff_16 ++// bit[7:4] sub_normal_mv_diff_8 ++// bit[3:2] Reserved ++// bit[1] sub_merge_enable_16 ++// bit[0] sub_merge_enable_8 ++#define ME_SUB_MERGE_CTL (0x1f59) ++#define P_ME_SUB_MERGE_CTL (volatile unsigned int *)((0x1f59 << 2) + 0xff620000) ++// bit[31:28] sub_ref_mv_diff_near ++// bit[27:24] sub_ref_mv_diff_near_flex ++// bit[23:20] sub_ref_mv_diff ++// bit[19:16] sub_ref_mv_diff_flex ++// bit[15:8] sub_ref_mv_near_weight ++// bit[7:0] sub_ref_mv_weight ++#define ME_SUB_REF_MV_CTL (0x1f5a) ++#define P_ME_SUB_REF_MV_CTL (volatile unsigned int *)((0x1f5a << 2) + 0xff620000) ++// bit[31:24] sub_weight_max_sad ++// bit[23:16] sub_any_range_sad ++// bit[15:8] sub_any_min_sad ++// bit[7:0] sub_any_max_sad ++#define ME_SUB_ANY_WEIGHT_SAD (0x1f5b) ++#define P_ME_SUB_ANY_WEIGHT_SAD (volatile unsigned int *)((0x1f5b << 2) + 0xff620000) ++// bit[31:24] sub_fix_sad ++// bit[23:16] sub_fix_diff_sad ++// bit[15:8] sub_sad_flex_adj ++// bit[7:0] sub_big_non_flex_fix_sad ++#define ME_SUB_FIX_SAD (0x1f5c) ++#define P_ME_SUB_FIX_SAD (volatile unsigned int *)((0x1f5c << 2) + 0xff620000) ++// bit[31:24] sub_fix_min_sad ++// bit[23:16] sub_fix_min_diff_sad ++// bit[15:8] sub_fix_min_sad_2 ++// bit[7:0] sub_fix_min_diff_sad_2 ++#define ME_SUB_FIX_MIN_SAD (0x1f5d) ++#define P_ME_SUB_FIX_MIN_SAD (volatile unsigned int *)((0x1f5d << 2) + 0xff620000) ++// bit[31:24] sub_snap_to_ref_max_sad ++// bit[23] sub_snap_to_ref_non_flex ++// bit[22:16] sub_snap_to_ref_mv_diff ++// bit[15:4] sub_glitch_mv_sad ++// bit[3:0] sub_glitch_mv_diff ++#define ME_SUB_SNAP_GLITCH (0x1f5e) ++#define P_ME_SUB_SNAP_GLITCH (volatile unsigned int *)((0x1f5e << 2) + 0xff620000) ++// bit[31:20] sad_act_limit ++// bit[19:8] s_a_any_sad ++// bit[7] Reserved ++// bit[6:5] sub_merge_method ++// bit[4] use_sub_act_result ++// bit[3] s_a_rnd ++// bit[2] Reserved ++// bit[1] sub_act_en_16 ++// bit[0] sub_act_en ++#define ME_SUB_ACT_CTL (0x1f5f) ++#define P_ME_SUB_ACT_CTL (volatile unsigned int *)((0x1f5f << 2) + 0xff620000) ++// bit[31:16] reserved ++// bit[15:0] me_weight ++#define ME_WEIGHT (0x1f60) ++#define P_ME_WEIGHT (volatile unsigned int *)((0x1f60 << 2) + 0xff620000) ++// bit[31] ready_update ++// bit[30] data_update ++// bit[29:28] reserved ++// bit[27:22] me_quant_0 ++// bit[21] ie_sad_ready_0 ++// bit[20:18] Reserved ++// bit[17:16] me_sad_mv_type_0 ++// bit[15:0] me_sad_0 ++#define ME_SAD_0 (0x1f61) ++#define P_ME_SAD_0 (volatile unsigned int *)((0x1f61 << 2) + 0xff620000) ++// bit[31] ready_update ++// bit[30] data_update ++// bit[29:28] reserved ++// bit[27:22] me_quant_1 ++// bit[21] me_sad_ready_1 ++// bit[20:18] Reserved ++// bit[17:16] me_sad_mv_type_1 ++// bit[15:0] me_sad_1 ++#define ME_SAD_1 (0x1f62) ++#define P_ME_SAD_1 (volatile unsigned int *)((0x1f62 << 2) + 0xff620000) ++// bit[31] ready_update ++// bit[30] data_update ++// bit[29:28] reserved ++// bit[27:22] me_quant_2 ++// bit[21] me_sad_ready_2 ++// bit[20:18] Reserved ++// bit[17:16] me_sad_mv_type_2 ++// bit[15:0] me_sad_2 ++#define ME_SAD_2 (0x1f63) ++#define P_ME_SAD_2 (volatile unsigned int *)((0x1f63 << 2) + 0xff620000) ++// bit[31] ready_update ++// bit[30] data_update ++// bit[29:28] reserved ++// bit[27:22] me_quant_3 ++// bit[21] me_sad_ready_3 ++// bit[20:18] Reserved ++// bit[17:16] me_sad_mv_type_3 ++// bit[15:0] me_sad_3 ++#define ME_SAD_3 (0x1f64) ++#define P_ME_SAD_3 (volatile unsigned int *)((0x1f64 << 2) + 0xff620000) ++// bit[31] ready_update ++// bit[30] data_update ++// bit[29:28] reserved ++// bit[27:22] ie_quant_0 ++// bit[21] ie_sad_ready_0 ++// bit[20] I4/I16 (0-I4MB, 1-I16MB) ++// bit[19:0] ie_sad_0 ++#define IE_SAD_0 (0x1f65) ++#define P_IE_SAD_0 (volatile unsigned int *)((0x1f65 << 2) + 0xff620000) ++// bit[31] ready_update ++// bit[30] data_update ++// bit[29:28] reserved ++// bit[27:22] ie_quant_1 ++// bit[21] ie_sad_ready_1 ++// bit[20] I4/I16 (0-I4MB, 1-I16MB) ++// bit[19:0] ie_sad_1 ++#define IE_SAD_1 (0x1f66) ++#define P_IE_SAD_1 (volatile unsigned int *)((0x1f66 << 2) + 0xff620000) ++// bit[31] ready_update ++// bit[30] data_update ++// bit[29:28] reserved ++// bit[27:22] ie_quant_2 ++// bit[21] ie_sad_ready_2 ++// bit[20] I4/I16 (0-I4MB, 1-I16MB) ++// bit[19:0] ie_sad_2 ++#define IE_SAD_2 (0x1f67) ++#define P_IE_SAD_2 (volatile unsigned int *)((0x1f67 << 2) + 0xff620000) ++// bit[31] ready_update ++// bit[30] data_update ++// bit[29:28] reserved ++// bit[27:22] ie_quant_3 ++// bit[21] ie_sad_ready_3 ++// bit[20] I4/I16 (0-I4MB, 1-I16MB) ++// bit[19:0] ie_sad_3 ++#define IE_SAD_3 (0x1f68) ++#define P_IE_SAD_3 (volatile unsigned int *)((0x1f68 << 2) + 0xff620000) ++// bit[31] enable_large_diff_16x8 ++// bit[30] enable_large_diff_8x16 ++// bit[29:16] adv_mv_8x8_weight ++// bit[15:14] reserved ++// bit[13:0] adv_mv_4x4x4_weight ++#define ADV_MV_CTL0 (0x1f69) ++#define P_ADV_MV_CTL0 (volatile unsigned int *)((0x1f69 << 2) + 0xff620000) ++// bit[31:16] adv_mv_16x16_weight ++// bit[15] enable_large_diff_16x16 ++// bit[14:0] adv_mv_16_8_weight ++#define ADV_MV_CTL1 (0x1f6a) ++#define P_ADV_MV_CTL1 (volatile unsigned int *)((0x1f6a << 2) + 0xff620000) ++#define ADV_MV_CTL2 (0x1f6b) ++#define P_ADV_MV_CTL2 (volatile unsigned int *)((0x1f6b << 2) + 0xff620000) ++// bit[31] v3_skip_enable ++// bit[30] v3_step_1_weight_enable // for step1, will only use pre_weight for block0, only step_weight for block 1,2,3 ++// bit[29] v3_l2_skip_only_use_l2_sad // set to 1 may allow l1 maybe not skip ++// bit[28] v3_mv_sad_weight_enable ++// bit[27] v3_ipred_type_enable ++// bit[25:12] force_skip_sad_1 ++// bit[11:0] force_skip_sad_0 ++#define V3_SKIP_CONTROL (0x1f6c) ++#define P_V3_SKIP_CONTROL (volatile unsigned int *)((0x1f6c << 2) + 0xff620000) ++// bit[18:16] top_ipred_type_count ++// bit[15:14] Reserved ++// bit[13:12] top_ipred_type_rd_idx ++// bit[11:10] top_ipred_type_wr_idx ++// bit[9] left_ipred_type_ready ++// bit[8] top_ipred_type_ready ++// bit[7:6] left_mv_idx ++// bit[5:4] top_mv_idx ++// bit[3] - left_mv_ready ++// bit[2:0] top_mv_ready ++#define V3_TOP_LEFT_CTL (0x1f6d) ++#define P_V3_TOP_LEFT_CTL (volatile unsigned int *)((0x1f6d << 2) + 0xff620000) ++#define V3_TOP_MV (0x1f6e) ++#define P_V3_TOP_MV (volatile unsigned int *)((0x1f6e << 2) + 0xff620000) ++#define V3_LEFT_MV (0x1f6f) ++#define P_V3_LEFT_MV (volatile unsigned int *)((0x1f6f << 2) + 0xff620000) ++// bit[31:30] reserved ++// bit[29:16] v3_skip_weight_1 ++// bit[15:12] reserved ++// bit[11:0] v3_skip_weight_0 ++#define V3_SKIP_WEIGHT (0x1f70) ++#define P_V3_SKIP_WEIGHT (volatile unsigned int *)((0x1f70 << 2) + 0xff620000) ++// bit[31:28] reserved ++// bit[27:16] v3_l1_f_skip_max_sad ++// bit[15:12] reserved ++// bit[11:0] v3_l1_skip_max_sad ++#define V3_L1_SKIP_MAX_SAD (0x1f71) ++#define P_V3_L1_SKIP_MAX_SAD (volatile unsigned int *)((0x1f71 << 2) + 0xff620000) ++// bit[31:16] force_skip_sad_2 ++// bit[15:0] v3_skip_weight_2 ++#define V3_L2_SKIP_WEIGHT (0x1f72) ++#define P_V3_L2_SKIP_WEIGHT (volatile unsigned int *)((0x1f72 << 2) + 0xff620000) ++// bit[21:16] v3_mv_sad_table_addr 0-15 table_step_0 ++// bit[11:0] v3_mv_sad ++#define V3_MV_SAD_TABLE (0x1f73) ++#define P_V3_MV_SAD_TABLE (volatile unsigned int *)((0x1f73 << 2) + 0xff620000) ++// [31:16] v3_ie_f_zero_sad_i16 ++// [15:0] v3_ie_f_zero_sad_i4 ++#define V3_F_ZERO_CTL_0 (0x1f74) ++#define P_V3_F_ZERO_CTL_0 (volatile unsigned int *)((0x1f74 << 2) + 0xff620000) ++// [25] v3_no_ver_when_top_zero_en ++// [24] v3_no_hor_when_left_zero_en ++// [23:16] v3_max_I16_H_num // 0 means no break ++// [15:0] v3_me_f_zero_sad ++#define V3_F_ZERO_CTL_1 (0x1f75) ++#define P_V3_F_ZERO_CTL_1 (volatile unsigned int *)((0x1f75 << 2) + 0xff620000) ++#define V3_TOP_INTRA_INFO (0x1f76) ++#define P_V3_TOP_INTRA_INFO (volatile unsigned int *)((0x1f76 << 2) + 0xff620000) ++#define V3_LEFT_INTRA_INFO (0x1f77) ++#define P_V3_LEFT_INTRA_INFO (volatile unsigned int *)((0x1f77 << 2) + 0xff620000) ++// [31:24] C_ipred_weight_H ++// [23:16] C_ipred_weight_V ++// [15:8] I4_ipred_weight_else ++// [7:0] I4_ipred_weight_most ++#define V3_IPRED_TYPE_WEIGHT_0 (0x1f78) ++#define P_V3_IPRED_TYPE_WEIGHT_0 (volatile unsigned int *)((0x1f78 << 2) + 0xff620000) ++// [31:24] I16_ipred_weight_DC ++// [23:16] I16_ipred_weight_H ++// [15:8] I16_ipred_weight_V ++// [7:0] C_ipred_weight_DC ++#define V3_IPRED_TYPE_WEIGHT_1 (0x1f79) ++#define P_V3_IPRED_TYPE_WEIGHT_1 (volatile unsigned int *)((0x1f79 << 2) + 0xff620000) ++// [31:16] v3_left_small_max_me_sad ++// [15:0] v3_left_small_max_ie_sad ++#define V3_LEFT_SMALL_MAX_SAD (0x1f7a) ++#define P_V3_LEFT_SMALL_MAX_SAD (volatile unsigned int *)((0x1f7a << 2) + 0xff620000) ++// (qr==7) & (qp==15) means force zero block ++// [31:26] v4_force_q_r_intra ++// [25:20] v4_force_q_r_inter ++// [19] v4_force_q_y_enable ++// [18:16] v4_force_qr_y ++// [15:12] v4_force_qp_y ++// [11:0] v4_force_skip_sad ++#define V4_FORCE_SKIP_CFG (0x1f7b) ++#define P_V4_FORCE_SKIP_CFG (volatile unsigned int *)((0x1f7b << 2) + 0xff620000) ++// v5 Complexity // Y(256 pixel per MB) and C(128 pixel per MB) ++// For every 4x4 block, calculate average and Add abs(pixel-average) together ++// bit[31:16] v5_diff_sum_C ++// bit[15:0] v5_diff_sum_Y ++#define V5_MB_DIFF_SUM (0x1f7c) ++#define P_V5_MB_DIFF_SUM (volatile unsigned int *)((0x1f7c << 2) + 0xff620000) ++// bit[31:24] v5_small_diff_cnt_C ++// bit[23:16] v5_small_diff_C ++// bit[15:8] v5_small_diff_cnt_Y ++// bit[7:0] v5_small_diff_Y ++#define V5_SMALL_DIFF_CNT (0x1f7d) ++#define P_V5_SMALL_DIFF_CNT (volatile unsigned int *)((0x1f7d << 2) + 0xff620000) ++// bit[31:29] Reserved ++// bit[28:24] v5_simple_block_cnt // 0 -15 Y 16-23 C ++// bit[23:20] v5_simple_pixel_cnt ++// bit[19:18] v5_simple_dq_wr_ptr ++// bit[17:16] v5_simple_dq_rd_ptr ++// bit[15:12] v5_simple_dq (Read Only) ++// bit[11:8] v5_simple_me_weight(Read Only) ++// bit[7] v5_use_small_diff_cnt ++// bit[6] v5_simple_mb_inter_all_en ++// bit[5] v5_simple_mb_inter_8x8_en ++// bit[4] v5_simple_mb_inter_16_8_en ++// bit[3] v5_simple_mb_inter_16x16_en ++// bit[2] v5_simple_mb_intra_en ++// bit[1] v5_simple_mb_C_en ++// bit[0] v5_simple_mb_Y_en ++#define V5_SIMPLE_MB_CTL (0x1f7e) ++#define P_V5_SIMPLE_MB_CTL (volatile unsigned int *)((0x1f7e << 2) + 0xff620000) ++// bit[31:28] v5_simple_dq_shift ++// bit[27:24] v5_simple_dq_6(-7 to +7) ++// bit[23:20] v5_simple_dq_5(-7 to +7) ++// bit[19:16] v5_simple_dq_4(-7 to +7) ++// bit[15:12] v5_simple_dq_3(-7 to +7) ++// bit[11:08] v5_simple_dq_2(-7 to +7) ++// bit[07:04] v5_simple_dq_1(-7 to +7) ++// bit[03:00] v5_simple_dq_0(-7 to +7) ++#define V5_SIMPLE_MB_DQUANT (0x1f7f) ++#define P_V5_SIMPLE_MB_DQUANT (volatile unsigned int *)((0x1f7f << 2) + 0xff620000) ++// bit[31:28] v5_simple_me_weight_shift ++// bit[27:24] v5_simple_me_weight_6(-7 to +7) ++// bit[23:20] v5_simple_me_weight_5(-7 to +7) ++// bit[19:16] v5_simple_me_weight_4(-7 to +7) ++// bit[15:12] v5_simple_me_weight_3(-7 to +7) ++// bit[11:08] v5_simple_me_weight_2(-7 to +7) ++// bit[07:04] v5_simple_me_weight_1(-7 to +7) ++// bit[03:00] v5_simple_me_weight_0(-7 to +7) ++#define V5_SIMPLE_MB_ME_WEIGHT (0x1f80) ++#define P_V5_SIMPLE_MB_ME_WEIGHT (volatile unsigned int *)((0x1f80 << 2) + 0xff620000) ++// ++// Closing file: qdct_regs.h ++// ++//------------------------------------------------------------------------------ ++// HCODEC MDEC module level register offset ++//------------------------------------------------------------------------------ ++// ++// Reading file: hcodec_mdec_regs.h ++// ++//======================================================================== ++// MDEC module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HCODEC_HDEC_CBUS_BASE = 0x09 ++// ----------------------------------------------- ++//`define HCODEC_MC_CTRL_REG 8'h00 ++//`define HCODEC_MC_MB_INFO 8'h01 ++//`define HCODEC_MC_PIC_INFO 8'h02 ++//`define HCODEC_MC_HALF_PEL_ONE 8'h03 ++//`define HCODEC_MC_HALF_PEL_TWO 8'h04 ++//`define HCODEC_POWER_CTL_MC 8'h05 ++// ++//`define HCODEC_MC_CMD 8'h06 ++//`define HCODEC_MC_CTRL0 8'h07 ++//`define HCODEC_MC_PIC_W_H 8'h08 ++//`define HCODEC_MC_STATUS0 8'h09 ++//`define HCODEC_MC_STATUS1 8'h0a ++//`define HCODEC_MC_CTRL1 8'h0b ++//`define HCODEC_MC_MIX_RATIO0 8'h0c ++//`define HCODEC_MC_MIX_RATIO1 8'h0d ++//`define HCODEC_MC_DP_MB_XY 8'h0e //read only ++//`define HCODEC_MC_OM_MB_XY 8'h0f //read only ++// ++//`define HCODEC_MC_MPORT_CTRL 8'h40 ++//`define HCODEC_MC_MPORT_DAT 8'h41 ++//`define HCODEC_MC_WT_PRED_CTRL 8'h42 ++//`define HCODEC_MC_MBBOT_ST_EVEN_ADDR 8'h44 ++//`define HCODEC_MC_MBBOT_ST_ODD_ADDR 8'h45 ++//`define HCODEC_MC_DPDN_MB_XY 8'h46 //read only ++//`define HCODEC_MC_OMDN_MB_XY 8'h47 //read only ++//`define HCODEC_MC_HCMDBUF_H 8'h48 ++//`define HCODEC_MC_HCMDBUF_L 8'h49 ++//`define HCODEC_MC_HCMD_H 8'h4a //read only ++//`define HCODEC_MC_HCMD_L 8'h4b //read only ++//`define HCODEC_MC_IDCT_DAT 8'h4c ++// ++//`define HCODEC_MC_CTRL_GCLK_CTRL 8'h4d ++//`define HCODEC_MC_OTHER_GCLK_CTRL 8'h4e ++// ++////Bit 29:24, mbbot thread ID and token ++////Bit 21:16, mc read/write thread ID and token ++////Bit 13:8, mbbot pre-arbitor burst number ++////Bit 5:0, mc pre-arbitor burst number ++//`define HCODEC_MC_CTRL2 8'h4f ++// ++//// `define HCODEC_DBLK_QUANT 8'h76 // ONLY for $ucode/real/amrisc/rv.s, reg value from apollo ++// ++////`define HCODEC_ANC1_CANVAS_ADDR 8'h80 ++////`define HCODEC_ANC2_CANVAS_ADDR 8'h81 ++// ++////`define HCODEC_REC_CANVAS_ADDR 8'h89 ++// ++////`define HCODEC_MDEC_PIC_W 8'h8c ++////`define HCODEC_MDEC_PIC_H 8'h8d ++//`define HCODEC_MDEC_PIC_DC_CTRL 8'h8e ++//`define HCODEC_MDEC_PIC_DC_STATUS 8'h8f ++// ++//`define HCODEC_ANC0_CANVAS_ADDR 8'h90 ++//`define HCODEC_ANC1_CANVAS_ADDR 8'h91 ++//`define HCODEC_ANC2_CANVAS_ADDR 8'h92 ++//`define HCODEC_ANC3_CANVAS_ADDR 8'h93 ++//`define HCODEC_ANC4_CANVAS_ADDR 8'h94 ++//`define HCODEC_ANC5_CANVAS_ADDR 8'h95 ++//`define HCODEC_ANC6_CANVAS_ADDR 8'h96 ++//`define HCODEC_ANC7_CANVAS_ADDR 8'h97 ++//`define HCODEC_ANC8_CANVAS_ADDR 8'h98 ++//`define HCODEC_ANC9_CANVAS_ADDR 8'h99 ++//`define HCODEC_ANC10_CANVAS_ADDR 8'h9a ++//`define HCODEC_ANC11_CANVAS_ADDR 8'h9b ++//`define HCODEC_ANC12_CANVAS_ADDR 8'h9c ++//`define HCODEC_ANC13_CANVAS_ADDR 8'h9d ++//`define HCODEC_ANC14_CANVAS_ADDR 8'h9e ++//`define HCODEC_ANC15_CANVAS_ADDR 8'h9f ++//`define HCODEC_ANC16_CANVAS_ADDR 8'ha0 ++//`define HCODEC_ANC17_CANVAS_ADDR 8'ha1 ++//`define HCODEC_ANC18_CANVAS_ADDR 8'ha2 ++//`define HCODEC_ANC19_CANVAS_ADDR 8'ha3 ++//`define HCODEC_ANC20_CANVAS_ADDR 8'ha4 ++//`define HCODEC_ANC21_CANVAS_ADDR 8'ha5 ++//`define HCODEC_ANC22_CANVAS_ADDR 8'ha6 ++//`define HCODEC_ANC23_CANVAS_ADDR 8'ha7 ++//`define HCODEC_ANC24_CANVAS_ADDR 8'ha8 ++//`define HCODEC_ANC25_CANVAS_ADDR 8'ha9 ++//`define HCODEC_ANC26_CANVAS_ADDR 8'haa ++//`define HCODEC_ANC27_CANVAS_ADDR 8'hab ++//`define HCODEC_ANC28_CANVAS_ADDR 8'hac ++//`define HCODEC_ANC29_CANVAS_ADDR 8'had ++//`define HCODEC_ANC30_CANVAS_ADDR 8'hae ++//`define HCODEC_ANC31_CANVAS_ADDR 8'haf ++// ++//`define HCODEC_DBKR_CANVAS_ADDR 8'hb0 ++//`define HCODEC_DBKW_CANVAS_ADDR 8'hb1 ++//`define HCODEC_REC_CANVAS_ADDR 8'hb2 ++// ++////28:24, read/write, current canvas idx, used in h264 only now ++////23:0, read only, current canvas address, 23:16, Cr canvas addr, 15:8, Cb canvas addr, 7:0, Y canvas addr ++//`define HCODEC_CURR_CANVAS_CTRL 8'hb3 ++// ++//`define HCODEC_MDEC_PIC_DC_THRESH 8'hb8 ++//`define HCODEC_MDEC_PICR_BUF_STATUS 8'hb9 ++//`define HCODEC_MDEC_PICW_BUF_STATUS 8'hba ++//`define HCODEC_MCW_DBLK_WRRSP_CNT 8'hbb ++// ++//`define HCODEC_AV_SCRATCH_0 8'hc0 ++//`define HCODEC_AV_SCRATCH_1 8'hc1 ++//`define HCODEC_AV_SCRATCH_2 8'hc2 ++//`define HCODEC_AV_SCRATCH_3 8'hc3 ++//`define HCODEC_AV_SCRATCH_4 8'hc4 ++//`define HCODEC_AV_SCRATCH_5 8'hc5 ++//`define HCODEC_AV_SCRATCH_6 8'hc6 ++//`define HCODEC_AV_SCRATCH_7 8'hc7 ++//`define HCODEC_AV_SCRATCH_8 8'hc8 ++//`define HCODEC_AV_SCRATCH_9 8'hc9 ++//`define HCODEC_AV_SCRATCH_A 8'hca ++//`define HCODEC_AV_SCRATCH_B 8'hcb ++//`define HCODEC_AV_SCRATCH_C 8'hcc ++//`define HCODEC_AV_SCRATCH_D 8'hcd ++//`define HCODEC_AV_SCRATCH_E 8'hce ++//`define HCODEC_AV_SCRATCH_F 8'hcf ++//`define HCODEC_AV_SCRATCH_G 8'hd0 ++//`define HCODEC_AV_SCRATCH_H 8'hd1 ++//`define HCODEC_AV_SCRATCH_I 8'hd2 ++//`define HCODEC_AV_SCRATCH_J 8'hd3 ++//`define HCODEC_AV_SCRATCH_K 8'hd4 ++//`define HCODEC_AV_SCRATCH_L 8'hd5 ++//`define HCODEC_AV_SCRATCH_M 8'hd6 ++//`define HCODEC_AV_SCRATCH_N 8'hd7 ++// ++//// bit[29:24] A_brst_num_co_mb ++//// bit[21:16] A_id_co_mb ++//// bit[11:0] wrrsp_count_co_mb ++//`define HCODEC_WRRSP_CO_MB 8'hd8 ++//// bit[29:24] A_brst_num_dcac ++//// bit[21:16] A_id_dcac ++//// bit[11:0] wrrsp_count_dcac ++//`define HCODEC_WRRSP_DCAC 8'hd9 ++// ++////====================================== ++//// MC Control Register Bits ++//// ++////====================================== ++//// For bits, just copy the defines...don't translate to addresses ++// `define HCODEC_MC_ENABLE 16'h0001 ++// //`define MC_RESET 16'h0002 ++// `define HCODEC_SKIP_MB 16'h0004 ++// ++////====================================== ++//// MB Info Register Bits ++//// ++////====================================== ++// `define HCODEC_INTRA_MB 16'h0001 ++// ++// `define HCODEC_BWD_PRED 16'h0004 ++// `define HCODEC_FWD_PRED 16'h0008 ++// ++// `define HCODEC_FLD_MOT 16'h0100 ++// `define HCODEC_FRM_16x8_MOT 16'h0200 ++// `define HCODEC_DUAL_PRM_MOT 16'h0300 ++// ++// `define HCODEC_FRM_DCT 16'h0000 // Bit 10 ++// `define HCODEC_FLD_DCT 16'h0400 ++// ++////====================================== ++//// MB Info Register Bits ++//// ++////====================================== ++// `define HCODEC_I_PIC 16'h0001 ++// `define HCODEC_P_PIC 16'h0002 ++// `define HCODEC_B_PIC 16'h0003 ++// ++// `define HCODEC_FLD_PIC 16'h0000 // Bit 8 ++// `define HCODEC_FRM_PIC 16'h0100 ++// ++////======================================================================== ++//// DBLK Register: 12'h950 - 12'h97f ++////======================================================================== ++//`define HCODEC_DBLK_RST 8'h50 ++//`define HCODEC_DBLK_CTRL 8'h51 ++//`define HCODEC_DBLK_MB_WID_HEIGHT 8'h52 ++//`define HCODEC_DBLK_STATUS 8'h53 ++//`define HCODEC_DBLK_CMD_CTRL 8'h54 ++//`define HCODEC_DBLK_MB_XY 8'h55 ++//`define HCODEC_DBLK_QP 8'h56 ++//`define HCODEC_DBLK_Y_BHFILT 8'h57 ++//`define HCODEC_DBLK_Y_BHFILT_HIGH 8'h58 ++//`define HCODEC_DBLK_Y_BVFILT 8'h59 ++//`define HCODEC_DBLK_CB_BFILT 8'h5a ++//`define HCODEC_DBLK_CR_BFILT 8'h5b ++//`define HCODEC_DBLK_Y_HFILT 8'h5c ++//`define HCODEC_DBLK_Y_HFILT_HIGH 8'h5d ++//`define HCODEC_DBLK_Y_VFILT 8'h5e ++//`define HCODEC_DBLK_CB_FILT 8'h5f ++//`define HCODEC_DBLK_CR_FILT 8'h60 ++//`define HCODEC_DBLK_BETAX_QP_SEL 8'h61 ++//`define HCODEC_DBLK_CLIP_CTRL0 8'h62 ++//`define HCODEC_DBLK_CLIP_CTRL1 8'h63 ++//`define HCODEC_DBLK_CLIP_CTRL2 8'h64 ++//`define HCODEC_DBLK_CLIP_CTRL3 8'h65 ++//`define HCODEC_DBLK_CLIP_CTRL4 8'h66 ++//`define HCODEC_DBLK_CLIP_CTRL5 8'h67 ++//`define HCODEC_DBLK_CLIP_CTRL6 8'h68 ++//`define HCODEC_DBLK_CLIP_CTRL7 8'h69 ++//`define HCODEC_DBLK_CLIP_CTRL8 8'h6a ++// ++//`define HCODEC_DBLK_STATUS1 8'h6b ++//`define HCODEC_DBLK_GCLK_FREE 8'h6c ++//`define HCODEC_DBLK_GCLK_OFF 8'h6d ++// ++//`define HCODEC_DBLK_AVSFLAGS 8'h6e ++// ++//// bit 15:0 ++//`define HCODEC_DBLK_CBPY 8'h70 ++//// bit 11:8 -- deblk_cbpy_bottom ++//// bit 7:4 -- deblk_cbpy_left ++//// bit 3:0 -- deblk_cbpy_top ++//`define HCODEC_DBLK_CBPY_ADJ 8'h71 ++//// bit 7:0 -- deblk_cbpc ++//`define HCODEC_DBLK_CBPC 8'h72 ++//// bit 15 -- bottom_mb ++//// bit 14 -- left_mb ++//// bit 13 -- top_mb ++//// bit 12 -- reserved ++//// bit 11:8 -- deblk_cbpc_bottom ++//// bit 7:4 -- deblk_cbpc_left ++//// bit 3:0 -- deblk_cbpc_top ++//`define HCODEC_DBLK_CBPC_ADJ 8'h73 ++//// bit 15:8 -- deblk_hmvd -- {left_1, left_0, below_1, below_0, block3-0} ++//// bit 7:0 -- deblk_vmvd -- {top_1, top_0, below_1, below_0, block3-0} ++//`define HCODEC_DBLK_VHMVD 8'h74 ++//// bit 13:12 -- right_vmvd ++//// bit 11 -- right_above_vmvd ++//// bit 10 -- left_below_hmvd ++//// bit 9 -- disable_dblk_luma ++//// bit 8 -- disable_dblk_chroma ++//// bit 7 -- bBelowRefDiff ++//// bit 6 -- bLeftRefDiff ++//// bit 5 -- bAboveRefDiff ++//// bit 4 -- reserved ++//// bit 3 -- s_below ++//// bit 2 -- s_left ++//// bit 1 -- s_above ++//// bit 0 -- s ++//`define HCODEC_DBLK_STRONG 8'h75 ++//// bit 14:10 -- PQUANT ++//// bit 9:5 -- left_PQUANT ++//// bit 4:0 -- top_PQUANT ++//`define HCODEC_DBLK_RV8_QUANT 8'h76 ++// ++//`define HCODEC_DBLK_CBUS_HCMD2 8'h77 ++//`define HCODEC_DBLK_CBUS_HCMD1 8'h78 ++//`define HCODEC_DBLK_CBUS_HCMD0 8'h79 ++//`define HCODEC_DBLK_VLD_HCMD2 8'h7a ++//`define HCODEC_DBLK_VLD_HCMD1 8'h7b ++//`define HCODEC_DBLK_VLD_HCMD0 8'h7c ++// ++//`define HCODEC_DBLK_OST_YBASE 8'h7d ++//`define HCODEC_DBLK_OST_CBCRDIFF 8'h7e ++// ++////13:8 dblk thread ID and token ++////5:0 dblk prearbitor burst num ++//`define HCODEC_DBLK_CTRL1 8'h7f ++// ++////DBLK last address 12'h97f ++// ++// Closing file: hcodec_mdec_regs.h ++// ++//------------------------------------------------------------------------------ ++// HCODEC VLD module level register offset ++//------------------------------------------------------------------------------ ++// ++// Reading file: hcodec_vld_regs.h ++// ++//======================================================================== ++// VLD module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HCODEC_VLD_CBUS_BASE = 0x0c ++// ----------------------------------------------- ++// ++//`define HCODEC_VLD_STATUS_CTRL 8'h00 ++//// ++//// bit 10 -- use_old_shift_en ++//// bit 9 -- output_mv_not_pmv ++//// bit 8:5 -- force_zigzag ++//// bit 4 -- force_zigzag_en ++//// bit 3 -- disable_viff_anempty_int ++//// bit 2 -- disable_m2_ac_coeff_one_cycle ++//// bit 1 -- forced_reset force reset pmv ++//// bit 0 -- mpeg_type 0:mpeg1 1: mpeg2 ++//`define HCODEC_MPEG1_2_REG 8'h01 ++//`define HCODEC_F_CODE_REG 8'h02 ++//`define HCODEC_PIC_HEAD_INFO 8'h03 ++//`define HCODEC_SLICE_VER_POS_PIC_TYPE 8'h04 ++//`define HCODEC_QP_VALUE_REG 8'h05 ++//`define HCODEC_MBA_INC 8'h06 ++//`define HCODEC_MB_MOTION_MODE 8'h07 ++////`define HCODEC_PACKET_BYTE_COUNT 8'h08 ++//// bit 15 -- force_search_startcode_en ++//// bit 14 -- int_cpu_when_error (before do anything) ++//// bit 13 -- vld_error_reset ++//// bit 12 -- return_on_slice_header ++//// bit 6 -- jpeg_ff00_en ++//// bit 5:0 -- vld_power_ctl ++//`define HCODEC_POWER_CTL_VLD 8'h08 ++// ++//`define HCODEC_MB_WIDTH 8'h09 ++//`define HCODEC_SLICE_QP 8'h0a ++//// `define HCODEC_MB_X_MB_Y 8'h0b // current MBX and MBY ++//`define HCODEC_PRE_START_CODE 8'h0b // ONLY for $ucode/real/amrisc/rv.s, reg value from apollo ++//`define HCODEC_SLICE_START_BYTE_01 8'h0c // ONLY for $ucode/real/amrisc/rv.s, reg value from apollo ++//`define HCODEC_SLICE_START_BYTE_23 8'h0d // ONLY for $ucode/real/amrisc/rv.s, reg value from apollo ++//`define HCODEC_RESYNC_MARKER_LENGTH 8'h0e // Does this exist in HW ? used in $ucode/mpeg4 ++// ++//// bit[6:5] - frame/field info, 01 - top, 10 - bottom, 11 - frame ++//// bit[4:0] - buffer ID ++//// L0_BUFF_ID_0, L0_BUFF_ID_1, L1_BUFF_ID_0, L1_BUFF_ID_1 ++//`define HCODEC_DECODER_BUFFER_INFO 8'h0f // Current Only Used for VC1 Interlace Field ++// ++//`define HCODEC_FST_FOR_MV_X 8'h10 ++//`define HCODEC_FST_FOR_MV_Y 8'h11 ++//`define HCODEC_SCD_FOR_MV_X 8'h12 ++//`define HCODEC_SCD_FOR_MV_Y 8'h13 ++//`define HCODEC_FST_BAK_MV_X 8'h14 ++//`define HCODEC_FST_BAK_MV_Y 8'h15 ++//`define HCODEC_SCD_BAK_MV_X 8'h16 ++//`define HCODEC_SCD_BAK_MV_Y 8'h17 ++// ++//// Bit 7:4 -- read_buffer_interlace 0-progressive, 1-interlace, used in VC1 ++//// bit 3 -- reserved ++//// bit 2 -- weighting_prediction ++//// bit 1 -- mb_weighting_flag ++//// bit 0 -- slice_weighting_flag ++//`define HCODEC_VLD_DECODE_CONTROL 8'h18 ++//`define HCODEC_VLD_REVERVED_19 8'h19 ++// ++//`define HCODEC_VIFF_BIT_CNT 8'h1a ++//`define HCODEC_BYTE_ALIGN_PEAK_HI 8'h1b ++//`define HCODEC_BYTE_ALIGN_PEAK_LO 8'h1c ++//`define HCODEC_NEXT_ALIGN_PEAK 8'h1d // Does this exist in HW ? used in $ucode/mpeg4 ++// ++//// bit 19 : vc1_inv_intra_co_mb_ref_rd ++//// bit 18 : vc1_inv_co_mb_ref_rd ++//// bit 17 : vc1_inv_intra_co_mb_ref_wr ++//// bit 16 : vc1_inv_co_mb_ref_wr ++//// bit 15 : reserved ++//// bit 14 : avs_drop_enable ++//// bit 13:12 : avs_drop_ptr ++//// bit 11:8 : avs_demu_ctl_reg ++//// bit 7 : avs_enable ++//// bit 6 : disable_dblk_hcmd ++//// bit 5 : disable_mc_hcmd ++//// bit 4 : first_mode3_set enable ++//// bit 3 : first_mode3 ++//// bit 2:1 : vc1_profile 0-SP, 1-MP, 2-reserved, 3-AP ++//// bit 0 : vc1_enable ++//`define HCODEC_VC1_CONTROL_REG 8'h1e ++// ++//`define HCODEC_PMV1_X 8'h20 ++//`define HCODEC_PMV1_Y 8'h21 ++//`define HCODEC_PMV2_X 8'h22 ++//`define HCODEC_PMV2_Y 8'h23 ++//`define HCODEC_PMV3_X 8'h24 ++//`define HCODEC_PMV3_Y 8'h25 ++//`define HCODEC_PMV4_X 8'h26 ++//`define HCODEC_PMV4_Y 8'h27 ++//// Can't use the same address for different defines ++//// Therefore, create a single define HCODEC_that covers both ++//// Only appears to be used in micro-code since the VLD hardware is ++//// hard coded. ++//// `define HCODEC_M4_TABLE_SELECT 8'h28 // Does this exist in HW ? Added from register_mp2.h ++//// `define HCODEC_M4_TABLE_OUTPUT 8'h28 // Does this exist in HW ? Added from register_mp2.h ++//`define HCODEC_M4_TABLE_SELECT 8'h28 ++//`define HCODEC_M4_CONTROL_REG 8'h29 ++//`define HCODEC_BLOCK_NUM 8'h2a // Does this exist in HW ? Added from register_mp2.h ++//`define HCODEC_PATTERN_CODE 8'h2b // Does this exist in HW ? Added from register_mp2.h ++//`define HCODEC_MB_INFO 8'h2c // Does this exist in HW ? Added from register_mp2.h ++//`define HCODEC_VLD_DC_PRED 8'h2d // Does this exist in HW ? Added from register_mp4.h ++//`define HCODEC_VLD_ERROR_MASK 8'h2e ++//`define HCODEC_VLD_DC_PRED_C 8'h2f // Does this exist in HW ? Added from register_mp4.h ++// ++//`define HCODEC_LAST_SLICE_MV_ADDR 8'h30 ++//`define HCODEC_LAST_MVX 8'h31 ++//`define HCODEC_LAST_MVY 8'h32 ++// ++//`define HCODEC_VLD_C38 8'h38 ++//`define HCODEC_VLD_C39 8'h39 ++// ++//`define HCODEC_VLD_STATUS 8'h3a // Does this exist in HW ? used in $ucode/real/amrisc/rv.s ++//`define HCODEC_VLD_SHIFT_STATUS 8'h3b // Does this exist in HW ? used in $ucode/real/amrisc/rv.s ++//// `define HCODEC_VLD_SHIFT_INFO 8'h3b // Does this exist in HW ? used in $ucode/mpeg4 ++//`define HCODEC_VOFF_STATUS 8'h3c // Does this exist in HW ? used in $ucode/mpeg4 ++// ++//`define HCODEC_VLD_C3D 8'h3d ++// ++//`define HCODEC_VLD_DBG_INDEX 8'h3e ++// ++// ++//// vld_buff_info -- (index == 0) ++//// Bit[7:6] mv_UR_ready_cnt; ++//// Bit[5] vld_wr_idx ++//// Bit[4] iq_rd_idx ++//// Bit[3] vld_vi_block_rdy_1 ++//// Bit[2] vld_vi_block_rdy_2 ++//// Bit[1] voff_empty_1 ++//// Bit[0] voff_empty_2 ++// ++//// cabac_buff_info_0 -- (index == 1) ++//// Bit[31] shift_data_ready ++//// Bit[30:29] Reserved ++//// Bit[28:24] cabac_buffer_ptr ++//// Bit[23:0] cabac_buffer ++// ++//// cabac_buff_info_1 -- (index == 2) ++//// Bit[31:29] Reserved ++//// Bit[28:20] Drange ++//// Bit[19:16] bin_count_4 ++//// Bit[15:13] Reserved ++//// Bit[12:6] context_mem_do ++//// Bit[5:3] coeff_state ++//// Bit[2:0] mvd_state ++// ++//// h264_mv_present -- (index == 3) ++//// Bit[31:16] mv_present_l0 ++//// Bit[15:0] mv_present_l1 ++// ++//// h264_mv_cal_info_0 -- (index == 4) ++//// [31:28] mv_cal_state ++//// [27:24] direct_spatial_cnt ++//// Bit[23:21] Reserved ++//// Bit[20] mv_UR_ready_for_mv_cal ++//// Bit[19] co_mb_mem_ready_for_mv_cal ++//// Bit[18] mc_dblk_cmd_if_busy ++//// Bit[17] h264_co_mb_wr_busy ++//// Bit[16] H264_cbp_blk_ready ++//// Bit[15] mc_hcmd_rrdy ++//// Bit[14] mc_hcmd_srdy ++//// Bit[13] mc_cmd_if_ready ++//// Bit[12] mc_hcmd_mv_available ++//// Bit[11:8] mc_cmd_if_state ++//// Bit[7] dblk_hcmd_rrdy ++//// Bit[6] dblk_hcmd_srdy ++//// Bit[5] dblk_cmd_if_ready ++//// Bit[4] dblk_hcmd_mv_available ++//// Bit[3:0] dblk_cmd_if_state ++// ++//// h264_mv_cal_info_1 -- (index == 5) ++//// Bit[31:29] Reserved ++//// Bit[28:24] total_mvd_num_l0 ++//// Bit[23:21] Reserved ++//// Bit[20:16] mv_cal_ptr_l0 ++//// Bit[15:13] Reserved ++//// Bit[12:8] mc_hcmd_ptr_l0 ++//// Bit[7:5] Reserved ++//// Bit[4:0] dblk_hcmd_ptr_l0 ++// ++//// h264_mv_cal_info_2 -- (index == 6) ++//// Bit[31:29] Reserved ++//// Bit[28:24] total_mvd_num_l1 ++//// Bit[23:21] Reserved ++//// Bit[20:16] mv_cal_ptr_l1 ++//// Bit[15:13] Reserved ++//// Bit[12:8] mc_hcmd_ptr_l1 ++//// Bit[7:5] Reserved ++//// Bit[4:0] dblk_hcmd_ptr_l1 ++// ++//// h264_co_mb_info -- (index == 7) ++//// Bit[31:26] Reserved ++//// Bit[25] mv_scale_cal_busy ++//// Bit[24:20] co_mv_count ++//// Bit[19:16] co_mv_process_state ++//// Bit[15] h264_co_mb_rd_busy ++//// Bit[15] h264_co_mb_rd_ready ++//// Bit[13:12] co_mv_transfer_block_cnt ++//// Bit[11:8] co_mv_transfer_ptr ++//// Bit[7] co_mv_POC_l1_busy ++//// Bit[6] h264_weight_scale_cal_en ++//// Bit[5] weight_cal_busy ++//// Bit[4] weight_cal_not_finished ++//// Bit[3:0] weight_process_state ++// ++//`define HCODEC_VLD_DBG_DATA 8'h3f ++//// -------------------------------------------- ++//// VIFIFO DDR Interface ++//// -------------------------------------------- ++//// The VIFIFO start pointer into DDR memory is a 32-bit number ++//// The Start pointer will automatically be truncated to land on ++//// an 8-byte boundary. That is, bits [2:0] = 0; ++//`define HCODEC_VLD_MEM_VIFIFO_START_PTR 8'h40 ++//// The current pointer points so some location between the START and END ++//// pointers. The current pointer is a BYTE pointer. That is, you can ++//// point to any BYTE address within the START/END range ++//`define HCODEC_VLD_MEM_VIFIFO_CURR_PTR 8'h41 ++//`define HCODEC_VLD_MEM_VIFIFO_END_PTR 8'h42 ++//`define HCODEC_VLD_MEM_VIFIFO_BYTES_AVAIL 8'h43 ++//// VIFIFO FIFO Control ++//// bit [31:24] viff_empty_int_enable_cpu[7:0] ++//// bit [23:16] viff_empty_int_enable_amrisc[7:0] ++//// -bit 23 Video BUFFER < 0x400 Bytes ++//// -bit 22 Video BUFFER < 0x200 Bytes ++//// -bit 21 Video BUFFER < 0x100 Bytes ++//// -bit 20 Video BUFFER < 0x80 Bytes ++//// -bit 19 Video BUFFER < 0x40 Bytes ++//// -bit 18 Video BUFFER < 0x20 Bytes ++//// -bit 17 vififo < 16 double words ++//// -bit 16 vififo < 8 double words ++//// bit [15:13] unused ++//// bit [12] A_urgent ++//// bit [11] transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request ++//// bit [10] use_level Set this bit to 1 to enable filling of the FIFO controlled by the buffer ++//// level control. If this bit is 0, then use bit[1] to control the enabling of filling ++//// bit [9] Data Ready. This bit is set when data can be popped ++//// bit [8] fill busy This bit will be high when we're fetching data from the DDR memory ++//// To reset this module, set cntl_enable = 0, and then wait for busy = 0. ++//// After that you can pulse cntl_init to start over ++//// bit [7] init_with_cntl_init ++//// bit [6] reserved ++//// bits [5:3] endian: see $lib/rtl/ddr_endian.v ++//// bit [2] cntl_empty_en Set to 1 to enable reading the DDR memory FIFO ++//// Set cntl_empty_en = cntl_fill_en = 0 when pulsing cntl_init ++//// bit [1] cntl_fill_en Set to 1 to enable reading data from DDR memory ++//// bit [0] cntl_init: After setting the read pointers, sizes, channel masks ++//// and read masks, set this bit to 1 and then to 0 ++//// NOTE: You don't need to pulse cntl_init if only the start address is ++//// being changed ++//`define HCODEC_VLD_MEM_VIFIFO_CONTROL 8'h44 ++//// -------------------------------------------- ++//// VIFIFO Buffer Level Manager ++//// -------------------------------------------- ++//`define HCODEC_VLD_MEM_VIFIFO_WP 8'h45 // Manual or Parser write pointer ++//`define HCODEC_VLD_MEM_VIFIFO_RP 8'h46 ++//`define HCODEC_VLD_MEM_VIFIFO_LEVEL 8'h47 // must be low first to shadow low/high 16-bit words ++//// ++//// bit [8] use_parser_video2_wp ++//// bit [7] vbuf2_out_manual ++//// bit [6] vbuf_out_manual ++//// bit [5] empty (ReadOnly) ++//// bit [4] full (ReadOnly) ++//// bit [3:2] reserved ++//// bit [1] manual mode Set to 1 for manual write pointer mode ++//// bit [0] Init Set high then low after everything has been initialized ++//`define HCODEC_VLD_MEM_VIFIFO_BUF_CNTL 8'h48 ++// ++//// bit 31:16 -- drop_bytes ++//// bit 15:14 -- drop_status (Read-Only) ++//// bit 13:12 -- sync_match_position (Read-Only) ++//// bit 11:6 -- reserved ++//// bit 5:4 -- TIME_STAMP_NUMBER, 0-32bits, 1-64bits, 2-96bits, 3-128bits ++//// bit 3 -- stamp_soft_reset ++//// bit 2 -- TIME_STAMP_length_enable ++//// bit 1 -- TIME_STAMP_sync64_enable ++//// bit 0 -- TIME_STAMP_enable ++//`define HCODEC_VLD_TIME_STAMP_CNTL 8'h49 ++//// bit 31:0 -- TIME_STAMP_SYNC_CODE_0 ++//`define HCODEC_VLD_TIME_STAMP_SYNC_0 8'h4a ++//// bit 31:0 -- TIME_STAMP_SYNC_CODE_1 ++//`define HCODEC_VLD_TIME_STAMP_SYNC_1 8'h4b ++//// bit 31:0 TIME_STAMP_0 ++//`define HCODEC_VLD_TIME_STAMP_0 8'h4c ++//// bit 31:0 TIME_STAMP_1 ++//`define HCODEC_VLD_TIME_STAMP_1 8'h4d ++//// bit 31:0 TIME_STAMP_2 ++//`define HCODEC_VLD_TIME_STAMP_2 8'h4e ++//// bit 31:0 TIME_STAMP_3 ++//`define HCODEC_VLD_TIME_STAMP_3 8'h4f ++//// bit 31:0 TIME_STAMP_LENGTH ++//`define HCODEC_VLD_TIME_STAMP_LENGTH 8'h50 ++// ++//// bit 15:0 vififo_rd_count ++//`define HCODEC_VLD_MEM_VIFIFO_WRAP_COUNT 8'h51 ++// ++//// bit 29:24 A_brst_num ++//// bit 21:16 A_id ++//// bit 15:0 level_hold ++//`define HCODEC_VLD_MEM_VIFIFO_MEM_CTL 8'h52 ++// ++//`define HCODEC_VLD_MEM_VBUF_RD_PTR 8'h53 // manual read address for VBUF1 ++//`define HCODEC_VLD_MEM_VBUF2_RD_PTR 8'h54 // manual read address for VBUF2 ++// ++//`define HCODEC_VLD_MEM_SWAP_ADDR 8'h55 ++//// bit[23:16] - swap_d_count (Read Only) ++//// bit[15:8] - swap_a_count (Read Only) ++//// bit [7] - swap busy (Read Only) ++//// bit [6:2] - reserved ++//// bit [1] - 1 - STORE to Memory, 0 - LOAD from Memory ++//// bit [0] - swap active ++//`define HCODEC_VLD_MEM_SWAP_CTL 8'h56 ++// ++// Closing file: hcodec_vld_regs.h ++// ++//------------------------------------------------------------------------------ ++// HCODEC IQIDCT module level register offset ++//------------------------------------------------------------------------------ ++// ++// Reading file: hcodec_iqidct_regs.h ++// ++//======================================================================== ++// IQ/IDCT module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HCODEC_IQIDCT_CBUS_BASE = 0x0e ++// ----------------------------------------------- ++// ++//`define HCODEC_VCOP_CTRL_REG 8'h00 ++//`define HCODEC_QP_CTRL_REG 8'h01 ++//`define HCODEC_INTRA_QUANT_MATRIX 8'h02 ++//`define HCODEC_NON_I_QUANT_MATRIX 8'h03 ++//`define HCODEC_DC_SCALER 8'h04 ++//`define HCODEC_DC_AC_CTRL 8'h05 ++//// `define HCODEC_RV_AI_CTRL 8'h05 // ONLY for $ucode/real/amrisc/rv.s reg value from apollo ++//`define HCODEC_DC_AC_SCALE_MUL 8'h06 ++//`define HCODEC_DC_AC_SCALE_DIV 8'h07 ++//// `define HCODEC_DC_AC_SCALE_RESULT 8'h06 ++//// `define HCODEC_RESERVED_E07 8'h07 ++//`define HCODEC_POWER_CTL_IQIDCT 8'h08 ++//`define HCODEC_RV_AI_Y_X 8'h09 ++//`define HCODEC_RV_AI_U_X 8'h0a ++//`define HCODEC_RV_AI_V_X 8'h0b ++//// bit 15:0 will count up when rv_ai_mb finished when non zero ++//// and rv_ai_mb_finished_int will be generate when this is not zero ++//`define HCODEC_RV_AI_MB_COUNT 8'h0c ++//// For H264 I in PB picture Use -- dma type : h264_next_intra_dma ++//`define HCODEC_NEXT_INTRA_DMA_ADDRESS 8'h0d ++//// Bit 0 -- constrained_intra_pred_flag for H264 ++//`define HCODEC_IQIDCT_CONTROL 8'h0e ++// ++// ++//// Bit[31:19] Reserved ++//// Bit[18] iq_waiting ++//// Bit[17] iq_om_wr_idx ++//// Bit[16] iq_om_rd_idx ++//// Bit[15] iq_om_busy ++//// Bit[14] iq_om_2_busy ++//// Bit[13] idx_fifo_0 ++//// Bit[12] idx_fifo_1 ++//// Bit[11] idx_fifo_2 ++//// Bit[10] idx_fifo_3 ++//// Bit[9] idx_fifo_4 ++//// Bit[8] idx_fifo_5 ++//// Bit[7] idx_fifo_6 ++//// Bit[6] idx_fifo_7 ++//// Bit[5:3] idx_fifo_wp ++//// Bit[2:0] idx_fifo_rp ++// ++//`define HCODEC_IQIDCT_DEBUG_INFO_0 8'h0f ++// ++//// For RTL Simulation Only ++//`define HCODEC_DEBLK_CMD 8'h10 ++// ++//// Bit[15+16] ds_mc_valid_2 ++//// Bit[14+16] new_idct1_rd_idx_2 ++//// Bit[13+16] new_idct1_wr_idx_2 ++//// Bit[12+16] idct1_buff0_busy_2 ++//// Bit[11+16] idct1_buff1_busy_2 ++//// Bit[10+16] new_idct1_busy_2 ++//// Bit[9+16] iq_om_8val_2 ++//// Bit[8+16] idct1_pipe_busy_2 ++// ++//// Bit[7+16] wait_mb_left_finish_hold_2 ++//// Bit[6+16] new_idct2_rd_idx_2 ++//// Bit[5+16] new_idct2_wr_idx_2 ++//// Bit[4+16] idct2_buff0_busy_2 ++//// Bit[3+16] idct2_buff1_busy_2 ++//// Bit[2+16] idct2_en_2 ++//// Bit[1+16] new_idct2_busy_2 ++//// Bit[0+16] new_idct1_ready_2 ++// ++//// Bit[15] ds_mc_valid_1 ++//// Bit[14] new_idct1_rd_idx_1 ++//// Bit[13] new_idct1_wr_idx_1 ++//// Bit[12] idct1_buff0_busy_1 ++//// Bit[11] idct1_buff1_busy_1 ++//// Bit[10] new_idct1_busy_1 ++//// Bit[9] iq_om_8val_1 ++//// Bit[8] idct1_pipe_busy_1 ++// ++//// Bit[7] wait_mb_left_finish_hold_1 ++//// Bit[6] new_idct2_rd_idx_1 ++//// Bit[5] new_idct2_wr_idx_1 ++//// Bit[4] idct2_buff0_busy_1 ++//// Bit[3] idct2_buff1_busy_1 ++//// Bit[2] idct2_en_1 ++//// Bit[1] new_idct2_busy_1 ++//// Bit[0] new_idct1_ready_1 ++// ++//`define HCODEC_IQIDCT_DEBUG_IDCT 8'h11 ++// ++// ++// ++//// bit 31 -- convas_enable ++//// bit 30:24 -- convas_x_count ( 8 pixels / 64 bits ) ++//// bit 23:16 -- convas_y_count ++//// bit 15 -- dcac_dma_busy ++//// bit 14 -- dcac_dma_urgent ++//// bit 13:8 -- dcac_dma_count ++//// bit 7 -- dcac_dma_rw ++//// bit 6 -- dcac_skip_read_mode ++//// bit 5:0 -- dcac_dma_offset ++//`define HCODEC_DCAC_DMA_CTRL 8'h12 ++//// when (convas_enable == 0 ) ++//// bit 31:0 dcac_dma_addr ++//// when (convas_enable == 1 ) ++//// bit 31:25 canvas_addr (7 bits) ++//// bit 24:12 convas_y_start ( 13 btis ) ++//// bit 11:0 convas_x_start ( 12 btis ) ++//`define HCODEC_DCAC_DMA_ADDRESS 8'h13 ++//// bit 7:0 -- dcac_cpu_addr ++//`define HCODEC_DCAC_CPU_ADDRESS 8'h14 ++//// bit 31:0 -- dcac_cpu_data ++//`define HCODEC_DCAC_CPU_DATA 8'h15 ++// ++//// bit 31:19 -- reserved ++//// bit 18:16 -- block_num_reg -- Read-Only ++//// bit 15:0 -- dcac_mb_count ++//`define HCODEC_DCAC_MB_COUNT 8'h16 ++// ++//// bit 31:18 -- reserved ++//// For H264 : ++//// bit 17:2 -- h264_quant ++//// bit 11:6 -- h264_quant_c ++//// bit 5:0 -- h264_quant_c ++//// For VC1 : ++//// bit 17 -- qindex_GT_8 ++//// bit 16 -- HalfQPStep ++//// bit 15:12 -- eQuantMode ++//// bit 11:6 -- AltPQuant ++//// bit 5:0 -- PQuant ++//// ++//`define HCODEC_IQ_QUANT 8'h17 ++// ++//// bit 31:24 -- bitplane_width ++//// bit 23:16 -- bitplane_height ++//// bit 15:14 -- bitplane_start_x ++//// bit 13:12 -- bitplane_start_y ++//// bit 11:4 -- reserved ++//// bit 3:1 -- bitplane_type ++//// bit 0 -- bitplane_busy ++//`define HCODEC_VC1_BITPLANE_CTL 8'h18 ++// ++// ++// ++// `define HCODEC_RAM_TEST_CMD 12'h002 ++// `define HCODEC_RAM_TEST_ADDR 12'h003 ++// `define HCODEC_RAM_TEST_DATAH 12'h004 ++// `define HCODEC_RAM_TEST_DATAL 12'h005 ++// ++// `define HCODEC_RAM_TEST_RD_CMD 16'h0000 ++// `define HCODEC_RAM_TEST_WR_CMD 16'h8000 ++// `define HCODEC_IDCT_TM2_PT0 16'h0001 ++// `define HCODEC_IDCT_TM2_PT1 16'h0002 ++// `define HCODEC_IDCT_TM1_PT0 16'h0004 ++// `define HCODEC_IDCT_TM1_PT1 16'h0008 ++// `define HCODEC_IQ_OMEM_PT0 16'h0010 ++// `define HCODEC_IQ_OMEM_PT1 16'h0020 ++// `define HCODEC_MC_IMEM_PT0 16'h0040 ++// `define HCODEC_ALL_RAM_PTS 16'h007f ++// ++////====================================== ++//// VCOP Control Register Bits ++//// ++////====================================== ++// //`define HCODEC_IQIDCT_RESET 16'h0001 // Bit 0 ++// `define HCODEC_QM_WEN 16'h0002 // Bit 1 ++// `define HCODEC_IQIDCT_ENABLE 16'h0004 // Bit 2 ++// `define HCODEC_INTRA_QM 16'h0008 // Bit 3 0 = Use default; 1 = use loaded ++// `define HCODEC_NINTRA_QM 16'h0010 // Bit 4 0 = Use default; 1 = use loaded ++// ++////====================================== ++//// QP Control Register Bits ++//// ++////====================================== ++// `define HCODEC_INTRA_MODE 16'h0080 // Bit 7 ++//// Duplicate Address: When actually used ++//// please move to a different address ++//// `define HCODEC_FLD_DCT_TYPE 16'h0100 // Bit 8 0 = Frame DCT; 1 = field DCT ++// ++// ++// Closing file: hcodec_iqidct_regs.h ++// ++//------------------------------------------------------------------------------ ++// HCODEC IQIDCT module level register offset ++//------------------------------------------------------------------------------ ++// ++// Reading file: hcodec_vcpu_regs.h ++// ++//======================================================================== ++// VCPU module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HCODEC_VCPU_CBUS_BASE = 0x03 ++// ----------------------------------------------- ++//`define HCODEC_MSP 8'h00 ++//`define HCODEC_MPSR 8'h01 ++//`define HCODEC_MINT_VEC_BASE 8'h02 ++//`define HCODEC_MCPU_INTR_GRP 8'h03 ++//`define HCODEC_MCPU_INTR_MSK 8'h04 ++//`define HCODEC_MCPU_INTR_REQ 8'h05 ++//`define HCODEC_MPC_P 8'h06 ++//`define HCODEC_MPC_D 8'h07 ++//`define HCODEC_MPC_E 8'h08 ++//`define HCODEC_MPC_W 8'h09 ++//`define HCODEC_MINDEX0_REG 8'h0a ++//`define HCODEC_MINDEX1_REG 8'h0b ++//`define HCODEC_MINDEX2_REG 8'h0c ++//`define HCODEC_MINDEX3_REG 8'h0d ++//`define HCODEC_MINDEX4_REG 8'h0e ++//`define HCODEC_MINDEX5_REG 8'h0f ++//`define HCODEC_MINDEX6_REG 8'h10 ++//`define HCODEC_MINDEX7_REG 8'h11 ++//`define HCODEC_MMIN_REG 8'h12 ++//`define HCODEC_MMAX_REG 8'h13 ++//`define HCODEC_MBREAK0_REG 8'h14 ++//`define HCODEC_MBREAK1_REG 8'h15 ++//`define HCODEC_MBREAK2_REG 8'h16 ++//`define HCODEC_MBREAK3_REG 8'h17 ++//`define HCODEC_MBREAK_TYPE 8'h18 ++//`define HCODEC_MBREAK_CTRL 8'h19 ++//`define HCODEC_MBREAK_STAUTS 8'h1a ++//`define HCODEC_MDB_ADDR_REG 8'h1b ++//`define HCODEC_MDB_DATA_REG 8'h1c ++//`define HCODEC_MDB_CTRL 8'h1d ++//`define HCODEC_MSFTINT0 8'h1e ++//`define HCODEC_MSFTINT1 8'h1f ++// ++//`define HCODEC_CSP 8'h20 ++//`define HCODEC_CPSR 8'h21 ++//`define HCODEC_CINT_VEC_BASE 8'h22 ++//`define HCODEC_CCPU_INTR_GRP 8'h23 ++//`define HCODEC_CCPU_INTR_MSK 8'h24 ++//`define HCODEC_CCPU_INTR_REQ 8'h25 ++//`define HCODEC_CPC_P 8'h26 ++//`define HCODEC_CPC_D 8'h27 ++//`define HCODEC_CPC_E 8'h28 ++//`define HCODEC_CPC_W 8'h29 ++//`define HCODEC_CINDEX0_REG 8'h2a ++//`define HCODEC_CINDEX1_REG 8'h2b ++//`define HCODEC_CINDEX2_REG 8'h2c ++//`define HCODEC_CINDEX3_REG 8'h2d ++//`define HCODEC_CINDEX4_REG 8'h2e ++//`define HCODEC_CINDEX5_REG 8'h2f ++//`define HCODEC_CINDEX6_REG 8'h30 ++//`define HCODEC_CINDEX7_REG 8'h31 ++//`define HCODEC_CMIN_REG 8'h32 ++//`define HCODEC_CMAX_REG 8'h33 ++//`define HCODEC_CBREAK0_REG 8'h34 ++//`define HCODEC_CBREAK1_REG 8'h35 ++//`define HCODEC_CBREAK2_REG 8'h36 ++//`define HCODEC_CBREAK3_REG 8'h37 ++//`define HCODEC_CBREAK_TYPE 8'h38 ++//`define HCODEC_CBREAK_CTRL 8'h39 ++//`define HCODEC_CBREAK_STAUTS 8'h3a ++//`define HCODEC_CDB_ADDR_REG 8'h3b ++//`define HCODEC_CDB_DATA_REG 8'h3c ++//`define HCODEC_CDB_CTRL 8'h3d ++//`define HCODEC_CSFTINT0 8'h3e ++//`define HCODEC_CSFTINT1 8'h3f ++// ++//`define HCODEC_IMEM_DMA_CTRL 8'h40 ++//`define HCODEC_IMEM_DMA_ADR 8'h41 ++//`define HCODEC_IMEM_DMA_COUNT 8'h42 ++//// bit[29:24] A_brst_num_imem ++//// bit[21:16] A_id_imem ++//// bit[11:0] wrrsp_count_imem (reserved) ++//`define HCODEC_WRRSP_IMEM 8'h43 ++// ++//`define HCODEC_LMEM_DMA_CTRL 8'h50 ++//`define HCODEC_LMEM_DMA_ADR 8'h51 ++//`define HCODEC_LMEM_DMA_COUNT 8'h52 ++//// bit[29:24] A_brst_num_lmem ++//// bit[21:16] A_id_lmem ++//// bit[11:0] wrrsp_count_lmem ++//`define HCODEC_WRRSP_LMEM 8'h53 ++// ++//`define HCODEC_MAC_CTRL1 8'h60 ++//`define HCODEC_ACC0REG1 8'h61 ++//`define HCODEC_ACC1REG1 8'h62 ++// ++//`define HCODEC_MAC_CTRL2 8'h70 ++//`define HCODEC_ACC0REG2 8'h71 ++//`define HCODEC_ACC1REG2 8'h72 ++//`define HCODEC_CPU_TRACE 8'h80 ++// ++// ++// Closing file: hcodec_vcpu_regs.h ++// ++//------------------------------------------------------------------------------ ++// HEVC_ASSIST module level register offset ++//------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HEVC_ASSIST_CBUS_BASE = 0x00 ++// ----------------------------------------------- ++#define HEVC_ASSIST_AFIFO_CTRL (0x3001) ++#define P_HEVC_ASSIST_AFIFO_CTRL (volatile unsigned int *)((0x3001 << 2) + 0xff620000) ++#define HEVC_ASSIST_AFIFO_CTRL1 (0x3002) ++#define P_HEVC_ASSIST_AFIFO_CTRL1 (volatile unsigned int *)((0x3002 << 2) + 0xff620000) ++#define HEVC_ASSIST_GCLK_EN (0x3003) ++#define P_HEVC_ASSIST_GCLK_EN (volatile unsigned int *)((0x3003 << 2) + 0xff620000) ++#define HEVC_ASSIST_SW_RESET (0x3004) ++#define P_HEVC_ASSIST_SW_RESET (volatile unsigned int *)((0x3004 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR1_INT0 (0x3025) ++#define P_HEVC_ASSIST_AMR1_INT0 (volatile unsigned int *)((0x3025 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR1_INT1 (0x3026) ++#define P_HEVC_ASSIST_AMR1_INT1 (volatile unsigned int *)((0x3026 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR1_INT2 (0x3027) ++#define P_HEVC_ASSIST_AMR1_INT2 (volatile unsigned int *)((0x3027 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR1_INT3 (0x3028) ++#define P_HEVC_ASSIST_AMR1_INT3 (volatile unsigned int *)((0x3028 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR1_INT4 (0x3029) ++#define P_HEVC_ASSIST_AMR1_INT4 (volatile unsigned int *)((0x3029 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR1_INT5 (0x302a) ++#define P_HEVC_ASSIST_AMR1_INT5 (volatile unsigned int *)((0x302a << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR1_INT6 (0x302b) ++#define P_HEVC_ASSIST_AMR1_INT6 (volatile unsigned int *)((0x302b << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR1_INT7 (0x302c) ++#define P_HEVC_ASSIST_AMR1_INT7 (volatile unsigned int *)((0x302c << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR1_INT8 (0x302d) ++#define P_HEVC_ASSIST_AMR1_INT8 (volatile unsigned int *)((0x302d << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR1_INT9 (0x302e) ++#define P_HEVC_ASSIST_AMR1_INT9 (volatile unsigned int *)((0x302e << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR1_INTA (0x302f) ++#define P_HEVC_ASSIST_AMR1_INTA (volatile unsigned int *)((0x302f << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR1_INTB (0x3030) ++#define P_HEVC_ASSIST_AMR1_INTB (volatile unsigned int *)((0x3030 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR1_INTC (0x3031) ++#define P_HEVC_ASSIST_AMR1_INTC (volatile unsigned int *)((0x3031 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR1_INTD (0x3032) ++#define P_HEVC_ASSIST_AMR1_INTD (volatile unsigned int *)((0x3032 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR1_INTE (0x3033) ++#define P_HEVC_ASSIST_AMR1_INTE (volatile unsigned int *)((0x3033 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR1_INTF (0x3034) ++#define P_HEVC_ASSIST_AMR1_INTF (volatile unsigned int *)((0x3034 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR2_INT0 (0x3035) ++#define P_HEVC_ASSIST_AMR2_INT0 (volatile unsigned int *)((0x3035 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR2_INT1 (0x3036) ++#define P_HEVC_ASSIST_AMR2_INT1 (volatile unsigned int *)((0x3036 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR2_INT2 (0x3037) ++#define P_HEVC_ASSIST_AMR2_INT2 (volatile unsigned int *)((0x3037 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR2_INT3 (0x3038) ++#define P_HEVC_ASSIST_AMR2_INT3 (volatile unsigned int *)((0x3038 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR2_INT4 (0x3039) ++#define P_HEVC_ASSIST_AMR2_INT4 (volatile unsigned int *)((0x3039 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR2_INT5 (0x303a) ++#define P_HEVC_ASSIST_AMR2_INT5 (volatile unsigned int *)((0x303a << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR2_INT6 (0x303b) ++#define P_HEVC_ASSIST_AMR2_INT6 (volatile unsigned int *)((0x303b << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR2_INT7 (0x303c) ++#define P_HEVC_ASSIST_AMR2_INT7 (volatile unsigned int *)((0x303c << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR2_INT8 (0x303d) ++#define P_HEVC_ASSIST_AMR2_INT8 (volatile unsigned int *)((0x303d << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR2_INT9 (0x303e) ++#define P_HEVC_ASSIST_AMR2_INT9 (volatile unsigned int *)((0x303e << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR2_INTA (0x303f) ++#define P_HEVC_ASSIST_AMR2_INTA (volatile unsigned int *)((0x303f << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR2_INTB (0x3040) ++#define P_HEVC_ASSIST_AMR2_INTB (volatile unsigned int *)((0x3040 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR2_INTC (0x3041) ++#define P_HEVC_ASSIST_AMR2_INTC (volatile unsigned int *)((0x3041 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR2_INTD (0x3042) ++#define P_HEVC_ASSIST_AMR2_INTD (volatile unsigned int *)((0x3042 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR2_INTE (0x3043) ++#define P_HEVC_ASSIST_AMR2_INTE (volatile unsigned int *)((0x3043 << 2) + 0xff620000) ++#define HEVC_ASSIST_AMR2_INTF (0x3044) ++#define P_HEVC_ASSIST_AMR2_INTF (volatile unsigned int *)((0x3044 << 2) + 0xff620000) ++#define HEVC_ASSIST_MBX_SSEL (0x3045) ++#define P_HEVC_ASSIST_MBX_SSEL (volatile unsigned int *)((0x3045 << 2) + 0xff620000) ++#define HEVC_ASSIST_TIMER0_LO (0x3060) ++#define P_HEVC_ASSIST_TIMER0_LO (volatile unsigned int *)((0x3060 << 2) + 0xff620000) ++#define HEVC_ASSIST_TIMER0_HI (0x3061) ++#define P_HEVC_ASSIST_TIMER0_HI (volatile unsigned int *)((0x3061 << 2) + 0xff620000) ++#define HEVC_ASSIST_TIMER1_LO (0x3062) ++#define P_HEVC_ASSIST_TIMER1_LO (volatile unsigned int *)((0x3062 << 2) + 0xff620000) ++#define HEVC_ASSIST_TIMER1_HI (0x3063) ++#define P_HEVC_ASSIST_TIMER1_HI (volatile unsigned int *)((0x3063 << 2) + 0xff620000) ++#define HEVC_ASSIST_DMA_INT (0x3064) ++#define P_HEVC_ASSIST_DMA_INT (volatile unsigned int *)((0x3064 << 2) + 0xff620000) ++#define HEVC_ASSIST_DMA_INT_MSK (0x3065) ++#define P_HEVC_ASSIST_DMA_INT_MSK (volatile unsigned int *)((0x3065 << 2) + 0xff620000) ++#define HEVC_ASSIST_DMA_INT2 (0x3066) ++#define P_HEVC_ASSIST_DMA_INT2 (volatile unsigned int *)((0x3066 << 2) + 0xff620000) ++#define HEVC_ASSIST_DMA_INT_MSK2 (0x3067) ++#define P_HEVC_ASSIST_DMA_INT_MSK2 (volatile unsigned int *)((0x3067 << 2) + 0xff620000) ++#define HEVC_ASSIST_MBOX0_IRQ_REG (0x3070) ++#define P_HEVC_ASSIST_MBOX0_IRQ_REG (volatile unsigned int *)((0x3070 << 2) + 0xff620000) ++#define HEVC_ASSIST_MBOX0_CLR_REG (0x3071) ++#define P_HEVC_ASSIST_MBOX0_CLR_REG (volatile unsigned int *)((0x3071 << 2) + 0xff620000) ++#define HEVC_ASSIST_MBOX0_MASK (0x3072) ++#define P_HEVC_ASSIST_MBOX0_MASK (volatile unsigned int *)((0x3072 << 2) + 0xff620000) ++#define HEVC_ASSIST_MBOX0_FIQ_SEL (0x3073) ++#define P_HEVC_ASSIST_MBOX0_FIQ_SEL (volatile unsigned int *)((0x3073 << 2) + 0xff620000) ++#define HEVC_ASSIST_MBOX1_IRQ_REG (0x3074) ++#define P_HEVC_ASSIST_MBOX1_IRQ_REG (volatile unsigned int *)((0x3074 << 2) + 0xff620000) ++#define HEVC_ASSIST_MBOX1_CLR_REG (0x3075) ++#define P_HEVC_ASSIST_MBOX1_CLR_REG (volatile unsigned int *)((0x3075 << 2) + 0xff620000) ++#define HEVC_ASSIST_MBOX1_MASK (0x3076) ++#define P_HEVC_ASSIST_MBOX1_MASK (volatile unsigned int *)((0x3076 << 2) + 0xff620000) ++#define HEVC_ASSIST_MBOX1_FIQ_SEL (0x3077) ++#define P_HEVC_ASSIST_MBOX1_FIQ_SEL (volatile unsigned int *)((0x3077 << 2) + 0xff620000) ++#define HEVC_ASSIST_MBOX2_IRQ_REG (0x3078) ++#define P_HEVC_ASSIST_MBOX2_IRQ_REG (volatile unsigned int *)((0x3078 << 2) + 0xff620000) ++#define HEVC_ASSIST_MBOX2_CLR_REG (0x3079) ++#define P_HEVC_ASSIST_MBOX2_CLR_REG (volatile unsigned int *)((0x3079 << 2) + 0xff620000) ++#define HEVC_ASSIST_MBOX2_MASK (0x307a) ++#define P_HEVC_ASSIST_MBOX2_MASK (volatile unsigned int *)((0x307a << 2) + 0xff620000) ++#define HEVC_ASSIST_MBOX2_FIQ_SEL (0x307b) ++#define P_HEVC_ASSIST_MBOX2_FIQ_SEL (volatile unsigned int *)((0x307b << 2) + 0xff620000) ++// bit[31:24] - read request ++// bit[23:16] - write request ++// bit[7] - disable_aml_axi_clk_gating ++// bit[3:0] - arb_switch_cnt ++#define HEVC_ASSIST_AXI_CTRL (0x307c) ++#define P_HEVC_ASSIST_AXI_CTRL (volatile unsigned int *)((0x307c << 2) + 0xff620000) ++// bit[31:24] - read arb result ++// bit[23:16] - write arb result ++// bit[15:12] - read_ar_cnt ++// bit[11:8] - write_aw_cnt ++// bit[7] - arvalid_axi_s0 ++// bit[6] - arready_axi_s0 ++// bit[5] - awvalid_axi_s0 ++// bit[4] - awready_axi_s0 ++// bit[3:0] - write_fifo_cnt ++#define HEVC_ASSIST_AXI_STATUS (0x307d) ++#define P_HEVC_ASSIST_AXI_STATUS (volatile unsigned int *)((0x307d << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_0 (0x30c0) ++#define P_HEVC_ASSIST_SCRATCH_0 (volatile unsigned int *)((0x30c0 << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_1 (0x30c1) ++#define P_HEVC_ASSIST_SCRATCH_1 (volatile unsigned int *)((0x30c1 << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_2 (0x30c2) ++#define P_HEVC_ASSIST_SCRATCH_2 (volatile unsigned int *)((0x30c2 << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_3 (0x30c3) ++#define P_HEVC_ASSIST_SCRATCH_3 (volatile unsigned int *)((0x30c3 << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_4 (0x30c4) ++#define P_HEVC_ASSIST_SCRATCH_4 (volatile unsigned int *)((0x30c4 << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_5 (0x30c5) ++#define P_HEVC_ASSIST_SCRATCH_5 (volatile unsigned int *)((0x30c5 << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_6 (0x30c6) ++#define P_HEVC_ASSIST_SCRATCH_6 (volatile unsigned int *)((0x30c6 << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_7 (0x30c7) ++#define P_HEVC_ASSIST_SCRATCH_7 (volatile unsigned int *)((0x30c7 << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_8 (0x30c8) ++#define P_HEVC_ASSIST_SCRATCH_8 (volatile unsigned int *)((0x30c8 << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_9 (0x30c9) ++#define P_HEVC_ASSIST_SCRATCH_9 (volatile unsigned int *)((0x30c9 << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_A (0x30ca) ++#define P_HEVC_ASSIST_SCRATCH_A (volatile unsigned int *)((0x30ca << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_B (0x30cb) ++#define P_HEVC_ASSIST_SCRATCH_B (volatile unsigned int *)((0x30cb << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_C (0x30cc) ++#define P_HEVC_ASSIST_SCRATCH_C (volatile unsigned int *)((0x30cc << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_D (0x30cd) ++#define P_HEVC_ASSIST_SCRATCH_D (volatile unsigned int *)((0x30cd << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_E (0x30ce) ++#define P_HEVC_ASSIST_SCRATCH_E (volatile unsigned int *)((0x30ce << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_F (0x30cf) ++#define P_HEVC_ASSIST_SCRATCH_F (volatile unsigned int *)((0x30cf << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_G (0x30d0) ++#define P_HEVC_ASSIST_SCRATCH_G (volatile unsigned int *)((0x30d0 << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_H (0x30d1) ++#define P_HEVC_ASSIST_SCRATCH_H (volatile unsigned int *)((0x30d1 << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_I (0x30d2) ++#define P_HEVC_ASSIST_SCRATCH_I (volatile unsigned int *)((0x30d2 << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_J (0x30d3) ++#define P_HEVC_ASSIST_SCRATCH_J (volatile unsigned int *)((0x30d3 << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_K (0x30d4) ++#define P_HEVC_ASSIST_SCRATCH_K (volatile unsigned int *)((0x30d4 << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_L (0x30d5) ++#define P_HEVC_ASSIST_SCRATCH_L (volatile unsigned int *)((0x30d5 << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_M (0x30d6) ++#define P_HEVC_ASSIST_SCRATCH_M (volatile unsigned int *)((0x30d6 << 2) + 0xff620000) ++#define HEVC_ASSIST_SCRATCH_N (0x30d7) ++#define P_HEVC_ASSIST_SCRATCH_N (volatile unsigned int *)((0x30d7 << 2) + 0xff620000) ++//------------------------------------------------------------------------------ ++// HEVC_ASSIST module level register offset ++// Same as VDEC/HCODEC to avoid confusing software guy ++//------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HEVC_VCPU_CBUS_BASE = 0x03 ++// ----------------------------------------------- ++//------------------------------------------------------------------------------ ++// HEVC_PARSER module level register offset ++//------------------------------------------------------------------------------ ++// ++// Reading file: hevc_parser_regs.h ++// ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HEVC_PARSER_CBUS_BASE = 0x01 ++// ----------------------------------------------- ++// [31:0] After reset version, can be used for test scratch register ++#define HEVC_PARSER_VERSION (0x3100) ++#define P_HEVC_PARSER_VERSION (volatile unsigned int *)((0x3100 << 2) + 0xff620000) ++// [31:16] - axi_setting ++// [15] - disable_stream_clock_gating ++// [14] - wstrb_set ++// [13] - stream_read_pause ++// [6:4] - stream_fetch_endian ++// [3] - use_parser_vbuf_wp ++// [2] - use_parser_vbuf2_wp ++// [1] - stream_fetch_busy - Read Only ++// [0] - stream_fetch_enable ++#define HEVC_STREAM_CONTROL (0x3101) ++#define P_HEVC_STREAM_CONTROL (volatile unsigned int *)((0x3101 << 2) + 0xff620000) ++#define HEVC_STREAM_START_ADDR (0x3102) ++#define P_HEVC_STREAM_START_ADDR (volatile unsigned int *)((0x3102 << 2) + 0xff620000) ++#define HEVC_STREAM_END_ADDR (0x3103) ++#define P_HEVC_STREAM_END_ADDR (volatile unsigned int *)((0x3103 << 2) + 0xff620000) ++// SW stream_buffer_wr_ptr ++#define HEVC_STREAM_WR_PTR (0x3104) ++#define P_HEVC_STREAM_WR_PTR (volatile unsigned int *)((0x3104 << 2) + 0xff620000) ++#define HEVC_STREAM_RD_PTR (0x3105) ++#define P_HEVC_STREAM_RD_PTR (volatile unsigned int *)((0x3105 << 2) + 0xff620000) ++//[31:0] stream_buffer_level - read only ++#define HEVC_STREAM_LEVEL (0x3106) ++#define P_HEVC_STREAM_LEVEL (volatile unsigned int *)((0x3106 << 2) + 0xff620000) ++// [31:29] stream_buffer_hole 256*(4^0) bytes ++// [28:23] stream_fifo_hole ++// [22:16] stream_fifo_level ++// [15] stream_fifo_wr_ptr_update_en ++// [14:8] stream_fifo_wr_ptr ++// [7] stream_fifo_rd_ptr_update_en ++// [6:0] stream_fifo_rd_ptr ++#define HEVC_STREAM_FIFO_CTL (0x3107) ++#define P_HEVC_STREAM_FIFO_CTL (volatile unsigned int *)((0x3107 << 2) + 0xff620000) ++// [31:16] - Reserved ++// [15] - disable_shift_clock_gating ++// [14] - disable_start_code_protect ++// [10] - length_zero_startcode_en ++// [9] - length_valid_startcode_en ++// [8:6] - sft_valid_wr_position (default : 3 (at least 24 bits available)) ++// [5:4] - emulate_code_length_sub_1(Default : 2) ++// [3] - emulation_auto_on_startcode(Default : 0) ++// [2:1] - start_code_length_sub_1(Default : 2) ++// [0] - stream_shift_enable(Default : 0) ++#define HEVC_SHIFT_CONTROL (0x3108) ++#define P_HEVC_SHIFT_CONTROL (volatile unsigned int *)((0x3108 << 2) + 0xff620000) ++// [31:0] - max 4-bytes start code (Default : 0x00000100) ++#define HEVC_SHIFT_STARTCODE (0x3109) ++#define P_HEVC_SHIFT_STARTCODE (volatile unsigned int *)((0x3109 << 2) + 0xff620000) ++// [31:0] - max 4-bytes emulate code (Default : 0x00000300) ++#define HEVC_SHIFT_EMULATECODE (0x310a) ++#define P_HEVC_SHIFT_EMULATECODE (volatile unsigned int *)((0x310a << 2) + 0xff620000) ++// [2] - startcode_searching ++// [1] - emulation_check_on ++// [0] - startcode_check_on ++#define HEVC_SHIFT_STATUS (0x310b) ++#define P_HEVC_SHIFT_STATUS (volatile unsigned int *)((0x310b << 2) + 0xff620000) ++// [31:0] hevc_shifted_data - read only ++#define HEVC_SHIFTED_DATA (0x310c) ++#define P_HEVC_SHIFTED_DATA (volatile unsigned int *)((0x310c << 2) + 0xff620000) ++// [31:0] shift_byte_count[31:0] ++#define HEVC_SHIFT_BYTE_COUNT (0x310d) ++#define P_HEVC_SHIFT_BYTE_COUNT (volatile unsigned int *)((0x310d << 2) + 0xff620000) ++// [31:28] - shift_byte_count[35:32] ++// [27:20] - element_read_data[31:24] ++// [10] - bytealign ++// [9] - signed_element ++// [8] - start_element_read ++// [7] - shift_busy ++// [6:0] - shift_bits ++#define HEVC_SHIFT_COMMAND (0x310e) ++#define P_HEVC_SHIFT_COMMAND (volatile unsigned int *)((0x310e << 2) + 0xff620000) ++// 31:8 - element_read_data[23:0] ++// 7:2 - element_read_length ++// 1:0 - element_read_state ++#define HEVC_ELEMENT_RESULT (0x310f) ++#define P_HEVC_ELEMENT_RESULT (volatile unsigned int *)((0x310f << 2) + 0xff620000) ++// [31:16] - cabac_buffer ++// [15] - cabac_buffer_init ++// [14] - cabac_context_init ++// [13] - disable_cabac_clock_gating ++// [12] - cabac_init_flag ++// [11] - Reserved ++// [10] - VP9_init_mv ++// [9] - VP9_init_ref_mode ++// [8] - VP9_init_if_y_mode ++// [7] - VP9_init_intra_inter ++// [6] - VP9_init_inter_mode ++// [5] - VP9_init_coef ++// [4] - VP9_init_tx_mode ++// [3] - VP9_init_skip ++// [2] - VP9_init_partition ++// [1] - VP9_key_frame ++// [0] - cabac_enable(Default : 0) ++#define HEVC_CABAC_CONTROL (0x3110) ++#define P_HEVC_CABAC_CONTROL (volatile unsigned int *)((0x3110 << 2) + 0xff620000) ++// [31:25] - chromaQPOffset_U ++// [24:18] - chromaQPOffset_V ++// [17:16] - MaxTrSize 0-4x4, 1-8x8, 2-16x16, 3-32x32 ++// [15:14] - MinTrSize 0-4x4, 1-8x8, 2-16x16, 3-32x32 ++// HEVC ++// [13:12] - MaxCUSize 0-8x8, 1-16x16, 2-32x32, 3-64x64 ++// [11:10] - MinCUSize 0-8x8, 1-16x16, 2-32x32, 3-64x64 ++// [9] - slice_sao_luma_flag ++// [8] - slice_sao_chroma_flag ++// VP9 -- When vp9_enable ++// [13:11] - MaxCUSize 0-8x8, 1-16x16, 2-32x32, 3-64x64, 7-4x4 ++// [10:8] - MinCUSize 0-8x8, 1-16x16, 2-32x32, 3-64x64, 7-4x4 ++// [7:2] - slice_quant ++// [1:0] - slice_type ++// AVS2 ++// [13:12] - MaxCUSize 0-8x8, 1-16x16, 2-32x32, 3-64x64 ++// [11:10] - MinCUSize 0-8x8, 1-16x16, 2-32x32, 3-64x64 ++// [9] - reserved ++// [8] - slice_quant[6] ++// [7:2] - slice_quant ++// [1:0] - slice_type ++#define HEVC_PARSER_SLICE_INFO (0x3111) ++#define P_HEVC_PARSER_SLICE_INFO (volatile unsigned int *)((0x3111 << 2) + 0xff620000) ++// bit[16] - 0:command, 1:address(will auto increase when write command) ++// bit[15:0]- command or addr ++#define HEVC_PARSER_CMD_WRITE (0x3112) ++#define P_HEVC_PARSER_CMD_WRITE (volatile unsigned int *)((0x3112 << 2) + 0xff620000) ++// [31:16] - reserved ++// [15] - disable_parser_core_clock_gating ++// [14:1] - Reserved ++// [0] - parser_core_enable(Default : 0) ++#define HEVC_PARSER_CORE_CONTROL (0x3113) ++#define P_HEVC_PARSER_CORE_CONTROL (volatile unsigned int *)((0x3113 << 2) + 0xff620000) ++// [31:16] - pre_parser_cmd ++// [15] - start_cmd_fetch/fetch_busy ++// [14] - parser_cmd_ready ++// [13] - pre_parser_cmd_ready ++// [12] - do_not_wait_if_busy ++// [11:8] - cmd_fetch_status // Read-only ++// [7:0] - cmd_fetch_addr ++#define HEVC_PARSER_CMD_FETCH (0x3114) ++#define P_HEVC_PARSER_CMD_FETCH (volatile unsigned int *)((0x3114 << 2) + 0xff620000) ++// [31:16] - parser_cmd ++// [9:5] - parser_function ++// [4:0] - cmd_status ++#define HEVC_PARSER_CMD_STATUS (0x3115) ++#define P_HEVC_PARSER_CMD_STATUS (volatile unsigned int *)((0x3115 << 2) + 0xff620000) ++// [31] - end_of_picture ++// [30] - uiLeft ++// [39] - uiTop ++// [28] - uiTopRight ++// [27:24] - Reserved ++// [23:12] - uiLin ++// [11:0] - uiCol ++#define HEVC_PARSER_LCU_INFO (0x3116) ++#define P_HEVC_PARSER_LCU_INFO (volatile unsigned int *)((0x3116 << 2) + 0xff620000) ++// 29:28 - min_cu_size_qp_delta ++// 27 - cu_qp_delta_enabled_flag ++// 26 - amp_enabled_flag ++// 25:23 - max_num_merge_cand ++// 22 - mvd_l1_zero_flag ++// 21:16 - num_ref_idx_l1_active ++// 15:10 - num_ref_idx_l0_active ++// 9:7 - max_transform_hierarchy_depth_inter ++// 6:4 - max_transform_hierarchy_depth_intra ++// 3 - transquant_bypass_enable_flag ++// 2 - constrained_intra_pred_flag ++// 1 - transform_skip_enabled_flag ++// 0 - sign_data_hiding_flag ++#define HEVC_PARSER_HEADER_INFO (0x3117) ++#define P_HEVC_PARSER_HEADER_INFO (volatile unsigned int *)((0x3117 << 2) + 0xff620000) ++#define HEVC_PARSER_RESULT_0 (0x3118) ++#define P_HEVC_PARSER_RESULT_0 (volatile unsigned int *)((0x3118 << 2) + 0xff620000) ++#define HEVC_PARSER_RESULT_1 (0x3119) ++#define P_HEVC_PARSER_RESULT_1 (volatile unsigned int *)((0x3119 << 2) + 0xff620000) ++#define HEVC_PARSER_RESULT_2 (0x311a) ++#define P_HEVC_PARSER_RESULT_2 (volatile unsigned int *)((0x311a << 2) + 0xff620000) ++#define HEVC_PARSER_RESULT_3 (0x311b) ++#define P_HEVC_PARSER_RESULT_3 (volatile unsigned int *)((0x311b << 2) + 0xff620000) ++// For HEVC ++// bit[31:24] - quant[47:40] ++// bit[23:16] - quant[39:32] ++// For VP9 ++// bit[31:24] - intra_flag ++// bit[23:16] - SplitFlag_4 ++// bit[15:8] - SkipFlag ++// bit[7] - SliceEnd|end_of_picture ++// bit[6:3] - SplitFlag_8 ++// bit[2:1] - SplitFlag_16 ++// bit[0] - SplitFlag_32 ++#define HEVC_CABAC_TOP_INFO (0x311c) ++#define P_HEVC_CABAC_TOP_INFO (volatile unsigned int *)((0x311c << 2) + 0xff620000) ++// For HEVC ++// bit[31:0] - quant[31:0] ++// For VP9 ++// bit [31:24] - vp9_top_eob_v ++// bit [23:16] - vp9_top_eob_u ++// bit [15:0] - vp9_top_eob_y ++#define HEVC_CABAC_TOP_INFO_2 (0x311d) ++#define P_HEVC_CABAC_TOP_INFO_2 (volatile unsigned int *)((0x311d << 2) + 0xff620000) ++// For HEVC ++// bit[31:24] - quant[47:40] ++// bit[23:16] - quant[39:32] ++// For VP9 ++// bit[31:24] - Reserved ++// bit[23:16] - SplitFlag_4 ++// bit[15:8] - SkipFlag ++// bit[7] - Reserved ++// bit[6:3] - SplitFlag_8 ++// bit[2:1] - SplitFlag_16 ++// bit[0] - SplitFlag_32 ++#define HEVC_CABAC_LEFT_INFO (0x311e) ++#define P_HEVC_CABAC_LEFT_INFO (volatile unsigned int *)((0x311e << 2) + 0xff620000) ++// For HEVC ++// bit[31:0] - quant[31:0] ++// For VP9 ++// bit [31:24] - vp9_left_eob_v ++// bit [23:16] - vp9_left_eob_u ++// bit [15:0] - vp9_left_eob_y ++#define HEVC_CABAC_LEFT_INFO_2 (0x311f) ++#define P_HEVC_CABAC_LEFT_INFO_2 (volatile unsigned int *)((0x311f << 2) + 0xff620000) ++// [31:29] - stream_buffer_empty_int_ctl (32bytes - 4k bytes) (default : 4 : 512 bytes interrupt) ++// [28:26] - stream_fifo_empty_int_ctl (0 - 128)(default : 0 - 0 byte interrupt) ++// [25] - stream_buffer_empty_int_cpu_enable ++// [24] - stream_buffer_empty_int_amrisc_enable ++// [23] - stream_fifo_empty_int_cpu_enable ++// [22] - stream_fifo_empty_int_amrisc_enable ++// [15] - disable_parser_clock_gating ++// [8] - dec_done_int_cpu_enable ++// [7] - dec_done_int_amrisc_enable ++// [6] - cmd_done_int_cpu_enable ++// [5] - cmd_done_int_amrisc_enable ++// [4] - startcode_found_int_cpu_enable ++// [3] - startcode_found_int_amrisc_enable ++// [2] - parser_int_cpu_level (default : 0(pulse)) ++// [1] - parser_int_amrisc_level (default : 0(pulse)) ++// [0] - parser_int_enable(Default : 0) ++#define HEVC_PARSER_INT_CONTROL (0x3120) ++#define P_HEVC_PARSER_INT_CONTROL (volatile unsigned int *)((0x3120 << 2) + 0xff620000) ++// [7] - stream_empty_int_cpu ++// [6] - stream_empty_int_amrisc ++// [2] - dec_done_int ++// [1] - cmd_done_int ++// [0] - startcode_found_int ++#define HEVC_PARSER_INT_STATUS (0x3121) ++#define P_HEVC_PARSER_INT_STATUS (volatile unsigned int *)((0x3121 << 2) + 0xff620000) ++// [31] - parser_mpred_if_busy -- Read Only ++// [8] - sao_sw_pred_enable ++// [7] - sao_top_save_even_no_sao ++// [6] - disable_parser_sao_if_clock_gating ++// [5] - parser_sao_if_en ++// [4] - scaler_if_leave_one_more_space ++// [3] - disable_parser_mpred_if_clock_gating ++// [2] - parser_mpred_if_en ++// [1] - disable_parser_scaler_if_clock_gating ++// [0] - parser_scaler_if_en ++#define HEVC_PARSER_IF_CONTROL (0x3122) ++#define P_HEVC_PARSER_IF_CONTROL (volatile unsigned int *)((0x3122 << 2) + 0xff620000) ++// [31:16] PicHeightInLumaSamples ++// [15:0] PicWidthInLumaSamples ++#define HEVC_PARSER_PICTURE_SIZE (0x3123) ++#define P_HEVC_PARSER_PICTURE_SIZE (volatile unsigned int *)((0x3123 << 2) + 0xff620000) ++// [31] - start_lcu_mpred_cmd ++// [30] - lcu_decoding_start ++// [29] - do_not_wait_if_busy ++// [23:0] - lcu_idx ++#define HEVC_PARSER_LCU_START (0x3124) ++#define P_HEVC_PARSER_LCU_START (volatile unsigned int *)((0x3124 << 2) + 0xff620000) ++// [31:30] - bit_depth_chroma_minus8 ++// [29:24] - MAX_QP ++// [23:20] - qpBdOffsetC ++// [19:16] - qpBdOffsetY ++// [15:12] - pcm_sample_bit_depth_chroma ++// [11:8] - pcm_sample_bit_depth_luma ++// [7:6] - max_pcm_luma_coding_block_size ++// [5:4] - min_pcm_luma_coding_block_size ++// [3:2] - bit_depth_luma_minus8 ++// [1] - enable_negtive_quant ++// [0] - pcm_enabled_flag ++#define HEVC_PARSER_HEADER_INFO2 (0x3125) ++#define P_HEVC_PARSER_HEADER_INFO2 (volatile unsigned int *)((0x3125 << 2) + 0xff620000) ++// Read Only ++// bit[23] - 1'b1 ++// bit[22] - Reserved ++// bit[21:16] - quant_V ++// bit[15] - 1'b1 ++// bit[14] - Reserved ++// bit[13:8] - quant_U ++// bit[7] - 1'b1 ++// bit[6] - Reserved ++// bit[5:0] - quant_Y ++#define HEVC_PARSER_QUANT_READ (0x3126) ++#define P_HEVC_PARSER_QUANT_READ (volatile unsigned int *)((0x3126 << 2) + 0xff620000) ++#define HEVC_PARSER_RESERVED_27 (0x3127) ++#define P_HEVC_PARSER_RESERVED_27 (volatile unsigned int *)((0x3127 << 2) + 0xff620000) ++// bit[15:8] - skip_addr_SaoOffData ++// bit[7:0] - skip_addr_SaoMerge ++#define HEVC_PARSER_CMD_SKIP_0 (0x3128) ++#define P_HEVC_PARSER_CMD_SKIP_0 (volatile unsigned int *)((0x3128 << 2) + 0xff620000) ++// bit[31:24] - skip_point_coding_unit_slice_type_RET ++// bit[23:16] - skip_point_coding_unit_slice_type_B ++// bit[15:8] - skip_point_coding_unit_slice_type_P ++// bit[7:0] - skip_point_coding_unit_slice_type_I ++#define HEVC_PARSER_CMD_SKIP_1 (0x3129) ++#define P_HEVC_PARSER_CMD_SKIP_1 (volatile unsigned int *)((0x3129 << 2) + 0xff620000) ++// bit[31:24] - reserved ++// bit[23:16] - skip_point_coding_unit_pred_mode_RET ++// bit[15:8] - skip_point_coding_unit_pred_mode_INTER ++// bit[7:0] - skip_point_coding_unit_pred_mode_INTRA ++#define HEVC_PARSER_CMD_SKIP_2 (0x312a) ++#define P_HEVC_PARSER_CMD_SKIP_2 (volatile unsigned int *)((0x312a << 2) + 0xff620000) ++// Write : ++// [24:16] context_addr for dec_Bin ++// [15:0] parser_cmd ++// Read result: ++// cabac_context_decodeBin, // 31 ++// cabac_context_decodeBinEP, // 30 ++// cabac_context_decodeBinTrm, // 29 ++// cabac_context_decodeBinBit, // 28 ++// parser_command, // 27:22 ++// cabac_context_ready, // 21 ++// cmd_status, // 20:16 ++// cabac_manual_data // 15:0 ++// ++#define HEVC_PARSER_MANUAL_CMD (0x312b) ++#define P_HEVC_PARSER_MANUAL_CMD (volatile unsigned int *)((0x312b << 2) + 0xff620000) ++// bit [9:0] - Read adress : ++// address 0-255 stream_fifo (128x64) ++// address 256-319 context_mem (256x7) ++// address 320-448 parser_cmd_mem (256x16) ++#define HEVC_PARSER_MEM_RD_ADDR (0x312c) ++#define P_HEVC_PARSER_MEM_RD_ADDR (volatile unsigned int *)((0x312c << 2) + 0xff620000) ++// bit [9:0] - Write adress : ++// address 0-255 stream_fifo (128x64) ++// address 256-319 context_mem (256x7) ++// address 512-640 parser_cmd_mem (256x16) ++#define HEVC_PARSER_MEM_WR_ADDR (0x312d) ++#define P_HEVC_PARSER_MEM_WR_ADDR (volatile unsigned int *)((0x312d << 2) + 0xff620000) ++// bit[31:0] read/write data ++#define HEVC_PARSER_MEM_RW_DATA (0x312e) ++#define P_HEVC_PARSER_MEM_RW_DATA (volatile unsigned int *)((0x312e << 2) + 0xff620000) ++// [31:20] sao_lcu_x ++// [19:8] sao_lcu_y ++// [7] sao_lcu_xy_update ++// [6:2] reserved ++// [1] sao_wait_up_read ++// [0] sao_wait_write ++#define HEVC_SAO_IF_STATUS (0x3130) ++#define P_HEVC_SAO_IF_STATUS (volatile unsigned int *)((0x3130 << 2) + 0xff620000) ++// Y_offset_3, // 31:26 ++// Y_offset_2, // 25:20 ++// Y_offset_1, // 19:14 ++// Y_offset_0, // 13:8 ++// Y_typeAuxInfo[3:0], // 7:4 ++// Y_typeIdc, // 3:1 [0, 1, 2, 3]-EO, [4,5]-BO+Y_typeAuxInfo[4] ++// Y_modelIdc // 0 ++#define HEVC_SAO_IF_DATA_Y (0x3131) ++#define P_HEVC_SAO_IF_DATA_Y (volatile unsigned int *)((0x3131 << 2) + 0xff620000) ++#define HEVC_SAO_IF_DATA_U (0x3132) ++#define P_HEVC_SAO_IF_DATA_U (volatile unsigned int *)((0x3132 << 2) + 0xff620000) ++#define HEVC_SAO_IF_DATA_V (0x3133) ++#define P_HEVC_SAO_IF_DATA_V (volatile unsigned int *)((0x3133 << 2) + 0xff620000) ++#define HEVC_STREAM_SWAP_ADDR (0x3134) ++#define P_HEVC_STREAM_SWAP_ADDR (volatile unsigned int *)((0x3134 << 2) + 0xff620000) ++// bit[31:24] - swap_wrrsp_count ++// bit[23:16] - swap_d_count (Read Only) ++// bit[15:8] - swap_a_count (Read Only) (7:0 or 9:2) ++// bit [7] - swap busy (Read Only) ++// bit [6:4] - swap_d_count[10:8] (Read Only) ++// bit [3] - swap_a_count[10] (Read Only) ++// bit [2] - swap_wrrsp_count_update ++// bit [1] - 1 - STORE to Memory, 0 - LOAD from Memory ++// bit [0] - swap active ++#define HEVC_STREAM_SWAP_CTRL (0x3135) ++#define P_HEVC_STREAM_SWAP_CTRL (volatile unsigned int *)((0x3135 << 2) + 0xff620000) ++#define HEVC_IQIT_IF_WAIT_CNT (0x3136) ++#define P_HEVC_IQIT_IF_WAIT_CNT (volatile unsigned int *)((0x3136 << 2) + 0xff620000) ++#define HEVC_MPRED_IF_WAIT_CNT (0x3137) ++#define P_HEVC_MPRED_IF_WAIT_CNT (volatile unsigned int *)((0x3137 << 2) + 0xff620000) ++#define HEVC_SAO_IF_WAIT_CNT (0x3138) ++#define P_HEVC_SAO_IF_WAIT_CNT (volatile unsigned int *)((0x3138 << 2) + 0xff620000) ++// [31:0] packet_length_count ++#define HEVC_STREAM_PACKET_LENGTH (0x3139) ++#define P_HEVC_STREAM_PACKET_LENGTH (volatile unsigned int *)((0x3139 << 2) + 0xff620000) ++// [31] data_length_protect_enable ++// [30] data_protect_fill_00_enable ++// [29] data_protect_fill_ff_enable ++// [28:19] Reserved ++// [18:0] data_length_protect_count ++#define HEVC_SHIFT_LENGTH_PROTECT (0x313a) ++#define P_HEVC_SHIFT_LENGTH_PROTECT (volatile unsigned int *)((0x313a << 2) + 0xff620000) ++// bit[3:0] parser_debug_idx ++#define HEVC_PARSER_DEBUG_IDX (0x313e) ++#define P_HEVC_PARSER_DEBUG_IDX (volatile unsigned int *)((0x313e << 2) + 0xff620000) ++// bit[31:0] parser_debug_dat -- read only ++#define HEVC_PARSER_DEBUG_DAT (0x313f) ++#define P_HEVC_PARSER_DEBUG_DAT (volatile unsigned int *)((0x313f << 2) + 0xff620000) ++// bit[22] - vp9_second_pu_use_if_busy_2 ++// bit[21] - parser_mpred_if_busy_when_pu_mpred_busy ++// bit[20:9] - Reserved ++// bit[8] - force_skip_1 (SEG_LVL_SKIP) ++// bit[7:3] - vp9_status ++// bit[2] - change_vp9_status ++// bit[1] - vp9_decode_start(W)/vp9_decode_busy ++// bit[0] - vp9_enable ++#define VP9_CONTROL (0x3140) ++#define P_VP9_CONTROL (volatile unsigned int *)((0x3140 << 2) + 0xff620000) ++// bit[15:8]- vp9_emd_cmd_parameter ++// bit[3] - vp9_emd_cmd_busy ++// bit[2:0] - vp9_emd_command (bit[7]-start/busy) ++// 0 - vp9_read ++// ( ++// input : bit[15:8] - prob, ++// bit[7:4] - vp9_read_literal_bits(1-16 bits) ++// output : bit[31:16] - result) ++// ) ++// 1 - vp9_diff_update_prob ++// ( ++// input : bit[7:4] - function: ++// `define vp9_read_tx_mode_prob 0 ++// `define vp9_read_coef_prob 1 ++// `define vp9_read_skip_prob 2 ++// `define vp9_read_inter_mode_prob 3 ++// `define vp9_read_interp_prob 4 ++// `define vp9_read_intra_inter_prob 5 ++// `define vp9_read_comp_inter_prob 6 ++// `define vp9_read_comp_ref_prob 7 ++// `define vp9_read_single_ref_prob 8 ++// `define vp9_read_if_y_mode_prob 9 ++// `define vp9_read_partition_prob 10 ++// `define vp9_read_mv_prob 11 ++// bit[29:16] - total loop times ++// bit[31:30] - probs_common ++// output : bit[15:8] - prob) ++// ) ++#define VP9_EMD_CMD (0x3141) ++#define P_VP9_EMD_CMD (volatile unsigned int *)((0x3141 << 2) + 0xff620000) ++// vp9_top_y_mode[31:0] ++#define VP9_TOP_Y_MODE_0 (0x3142) ++#define P_VP9_TOP_Y_MODE_0 (volatile unsigned int *)((0x3142 << 2) + 0xff620000) ++// vp9_top_y_mode[63:32] ++#define VP9_TOP_Y_MODE_1 (0x3143) ++#define P_VP9_TOP_Y_MODE_1 (volatile unsigned int *)((0x3143 << 2) + 0xff620000) ++// vp9_left_y_mode[31:0] ++#define VP9_LEFT_Y_MODE_0 (0x3144) ++#define P_VP9_LEFT_Y_MODE_0 (volatile unsigned int *)((0x3144 << 2) + 0xff620000) ++// vp9_left_y_mode[63:32] ++#define VP9_LEFT_Y_MODE_1 (0x3145) ++#define P_VP9_LEFT_Y_MODE_1 (volatile unsigned int *)((0x3145 << 2) + 0xff620000) ++// bit[31] - 0:write_vp9_quant, 1:write_vp9_seg_feature ++// For write_vp9_seg_feature: ++// bit[24:22] - seg_id ++// bit[21] - seg_q_enable ++// bit[20] - seg_q_sign ++// bit[19:12] - seg_q_abs ++// bit[11] - seg_lf_enable ++// bit[10] - seg_lf_sign ++// bit[9:4] - seg_lf_abs ++// bit[3] - seg_ref_enable ++// bit[2:1] - seg_ref_abs ++// bit[0] - seg_skip_enable ++// For write_vp9_quant: ++// bit[19:16] - Write index : Seg_0_Y-0, Seg_0_UV-1, ... Seq_7_Y-14, Seq_7_UV-15 ++// bit[15:8] - AC quant ++// bit[7:0] - DC quant ++#define VP9_QUANT_WR (0x3146) ++#define P_VP9_QUANT_WR (volatile unsigned int *)((0x3146 << 2) + 0xff620000) ++// bit [31:16] - vp9_inter_mode_top/{8'h0, vp9_seg_pred_top} ++// bit [15:0] - vp9_top_tx_mode (odd/even mi has same tx_mode) ++#define HEVC_CABAC_TOP_INFO_3 (0x3147) ++#define P_HEVC_CABAC_TOP_INFO_3 (volatile unsigned int *)((0x3147 << 2) + 0xff620000) ++// bit [31:16] - vp9_inter_mode_left/{8'h0, vp9_seg_pred_left} ++// bit [15:0] - vp9_left_tx_mode (odd/even mi has same tx_mode) ++#define HEVC_CABAC_LEFT_INFO_3 (0x3148) ++#define P_HEVC_CABAC_LEFT_INFO_3 (volatile unsigned int *)((0x3148 << 2) + 0xff620000) ++// bit [31:16] - ref_frame[1] ++// bit [15:0] - ref_frame[0] ++#define HEVC_CABAC_TOP_INFO_4 (0x3149) ++#define P_HEVC_CABAC_TOP_INFO_4 (volatile unsigned int *)((0x3149 << 2) + 0xff620000) ++// bit [31:16] - ref_frame[1] ++// bit [15:0] - ref_frame[0] ++#define HEVC_CABAC_LEFT_INFO_4 (0x314a) ++#define P_HEVC_CABAC_LEFT_INFO_4 (volatile unsigned int *)((0x314a << 2) + 0xff620000) ++// bit [31:16] - interp_filter ++// bit [15:8] - Reserved ++// bit [7:0] - vp9_seg_pred_top ++#define HEVC_CABAC_TOP_INFO_5 (0x314b) ++#define P_HEVC_CABAC_TOP_INFO_5 (volatile unsigned int *)((0x314b << 2) + 0xff620000) ++// bit [31:16] - interp_filter ++// bit [15:8] - Reserved ++// bit [7:0] - vp9_seg_pred_left ++#define HEVC_CABAC_LEFT_INFO_5 (0x314c) ++#define P_HEVC_CABAC_LEFT_INFO_5 (volatile unsigned int *)((0x314c << 2) + 0xff620000) ++// bit[31] - operation start (read : busy) ++// bit[30:28] - operation_endian ++// bit[27:24] - Reserved ++// bit[23:22] - operation_mem 00:prob_mem, 01:count_mem ++// bit[21:20] - operation_cmd 0:clear, 1-store, 2-load ++// bit[19:10] - operation_end_addr ++// bit[9:0] - operation_start_addr ++#define VP9_MEM_OPERATION (0x314d) ++#define P_VP9_MEM_OPERATION (volatile unsigned int *)((0x314d << 2) + 0xff620000) ++// bit[27] - vp9_seg_pred_info_3 ++// bit[26] - vp9_seg_abs_delta ++// bit[25] - vp9_seg_temporal ++// bit[24] - vp9_seg_update_map ++// bit[23] - vp9_seg_enable ++// bit[22] - vp9_lossless_use_set ++// bit[21] - vp9_lossless_set_data ++// bit[20] - vp9_swap_Y_MODE_with_INFO45 ++// bit[19] - vp9_allow_hp ++// bit[18:16] - vp9_interp_filter ++// bit[15] - vp9_intra_frame ++// bit[14:12] - vp9_tx_mode ++// bit[11:10] - vp9_ref_mode // SINGLE_REFERENCE(0), COMPOUND_REFERENCE(1), REFERENCE_MODE_SELECT(2) ++// bit[9] - VPX_BITS_10 ++// bit[8] - ref_frame_bias[2] ++// bit[7] - ref_frame_bias[1] ++// bit[6] - ref_frame_bias[0] ++// [5:4] - comp_var_ref[1] ++// [3:2] - comp_var_ref[0] ++// [1:0] - comp_fixed_ref ++#define VP9_DECODING_INFO (0x314f) ++#define P_VP9_DECODING_INFO (volatile unsigned int *)((0x314f << 2) + 0xff620000) ++// [7] -- segment_id_map_from_shadow ++// [6] -- segment_id_map_to_shadow ++// [5] -- shadow_rw_addr_update ++// [4:0] -- shadiw_rw_addr ++#define VP9_SHADOW_CTRL (0x3150) ++#define P_VP9_SHADOW_CTRL (volatile unsigned int *)((0x3150 << 2) + 0xff620000) ++// [31:0] -- shadow_rw_data ++#define VP9_SHADOW_DATA (0x3151) ++#define P_VP9_SHADOW_DATA (volatile unsigned int *)((0x3151 << 2) + 0xff620000) ++// bit[22] - avs2_second_pu_use_if_busy_2 ++// bit[21] - parser_mpred_if_busy_when_pu_mpred_busy ++// bit[20:9] - Reserved ++// bit[8] - force_skip_1 (SEG_LVL_SKIP) ++// bit[7:3] - avs2_status ++// bit[2] - change_avs2_status ++// bit[1] - avs2_decode_start(W)/avs2_decode_busy ++// bit[0] - avs2_enable ++#define AVS2_CONTROL (0x3152) ++#define P_AVS2_CONTROL (volatile unsigned int *)((0x3152 << 2) + 0xff620000) ++// bit[7] - useNSIP (nonsquare_intra_prediction_enable) ++// bit[6] - secT_enabled (secondary_transform_enable_flag) ++// bit[5] - slice_alf_enable_Y ++// bit[4] - slice_alf_enable_U ++// bit[3] - slice_alf_enable_V ++// bit[2] - slice_sao_enable_Y ++// bit[1] - slice_sao_enable_U ++// bit[0] - slice_sao_enable_V ++#define AVS2_DEC_INFO (0x3153) ++#define P_AVS2_DEC_INFO (volatile unsigned int *)((0x3153 << 2) + 0xff620000) ++// ++// Closing file: hevc_parser_regs.h ++// ++//------------------------------------------------------------------------------ ++// HEVC_MPRED module level register offset ++//------------------------------------------------------------------------------ ++// ++// Reading file: hevc_mpred_regs.h ++// ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HEVC_MPRED_CBUS_BASE = 0x02 ++// ----------------------------------------------- ++#define HEVC_MPRED_VERSION (0x3200) ++#define P_HEVC_MPRED_VERSION (volatile unsigned int *)((0x3200 << 2) + 0xff620000) ++// [31:0] reversion default:32'h00010001 ++#define HEVC_MPRED_CTRL0 (0x3201) ++#define P_HEVC_MPRED_CTRL0 (volatile unsigned int *)((0x3201 << 2) + 0xff620000) ++// [1:0] slice_type[1:0] ++// [2] new_pic ++// [3] new_tile ++// [4] SliceSegment ++// [5] TMVPFlag_en ++// [6] LDCFlag ++// [7] ColFromL0Flag ++// [8] reserved ++// [9] above_en ++// [10] mv_wr_en :collocated MV write enable: 0=no-write,1=write;default:1'b1 ++// [11] mv_rd_en ++// [12] col_isIntra ++// [13] reserved ++// [14] LongTerm_Curr ++// [15] LongTerm_Col ++// [19:16] lcu_size_log2[3:0] ++// [23:20] cu_size_log2[3:0] ++// [26:24] plevel[2:0] ++// [31:27] reserved ++#define HEVC_MPRED_CTRL1 (0x3202) ++#define P_HEVC_MPRED_CTRL1 (volatile unsigned int *)((0x3202 << 2) + 0xff620000) ++// [3:0] MERGE_MAX_NUM_CANDS[3:0] ++// [7:4] AMVP_MAX_NUM_CANDS[3:0] ++// [23:8] reserved ++// [24] clk_forceon ++// [31:25] reserved ++#define HEVC_MPRED_INT_EN (0x3203) ++#define P_HEVC_MPRED_INT_EN (volatile unsigned int *)((0x3203 << 2) + 0xff620000) ++// [0] mpred_int_enable ++// [1] mpred_int_amrisc_level ++// [2] mpred_int_cpu_level ++// [3] slice_done_int_amrisc_enable ++// [4] slice_done_int_cpu_enable ++// [15] disable_mpred_int_clock_gating ++#define HEVC_MPRED_INT_STATUS (0x3204) ++#define P_HEVC_MPRED_INT_STATUS (volatile unsigned int *)((0x3204 << 2) + 0xff620000) ++// [0] slice_done IRQ ++// [31] write "1"=slice start(self clear,read always return "0") ++#define HEVC_MPRED_PIC_SIZE (0x3205) ++#define P_HEVC_MPRED_PIC_SIZE (volatile unsigned int *)((0x3205 << 2) + 0xff620000) ++// [15:0] pic_width[15:0] ++// [31:16] pic_height[15:0] ++#define HEVC_MPRED_PIC_SIZE_LCU (0x3206) ++#define P_HEVC_MPRED_PIC_SIZE_LCU (volatile unsigned int *)((0x3206 << 2) + 0xff620000) ++// [15:0] lcu_x_num_1[15:0] (=lcu_x_total-1) ++// [31:16] lcu_y_num_1[15:0] (=lcu_y_total-1) ++#define HEVC_MPRED_TILE_START (0x3207) ++#define P_HEVC_MPRED_TILE_START (volatile unsigned int *)((0x3207 << 2) + 0xff620000) ++// [15:0] tile_start_lcu_x[15:0] ++// [31:16] tile_start_lcu_y[15:0] ++#define HEVC_MPRED_TILE_SIZE_LCU (0x3208) ++#define P_HEVC_MPRED_TILE_SIZE_LCU (volatile unsigned int *)((0x3208 << 2) + 0xff620000) ++// [15:0] tile_width_lcu[15:0] ++// [31:16] tile_height_lcu[15:0] ++#define HEVC_MPRED_REF_NUM (0x3209) ++#define P_HEVC_MPRED_REF_NUM (volatile unsigned int *)((0x3209 << 2) + 0xff620000) ++// [3:0] refNum_L0[3:0] ++// [11:8] refNum_L1[3:0] ++// [19:16] col_refNum_L0[3:0] ++// [27:24] col_refNum_L1[3:0] ++#define HEVC_MPRED_LT_REF (0x320a) ++#define P_HEVC_MPRED_LT_REF (volatile unsigned int *)((0x320a << 2) + 0xff620000) ++// [00] LongTerm_L0_Ref00 ++// [01] LongTerm_L0_Ref01 ++// ...... ++// [15] LongTerm_L0_Ref15 ++// [16] LongTerm_L1_Ref00 ++// [17] LongTerm_L1_Ref01 ++// ...... ++// [31] LongTerm_L1_Ref15 ++#define HEVC_MPRED_LT_COLREF (0x320b) ++#define P_HEVC_MPRED_LT_COLREF (volatile unsigned int *)((0x320b << 2) + 0xff620000) ++// [00] LongTerm_Col_L0_Ref00 ++// [01] LongTerm_Col_L0_Ref01 ++// ...... ++// [15] LongTerm_Col_L0_Ref15 ++// [16] LongTerm_Col_L1_Ref00 ++// [17] LongTerm_Col_L1_Ref01 ++// ...... ++// [31] LongTerm_Col_L1_Ref15 ++#define HEVC_MPRED_REF_EN_L0 (0x320c) ++#define P_HEVC_MPRED_REF_EN_L0 (volatile unsigned int *)((0x320c << 2) + 0xff620000) ++// [00] L0_ref00_en ++// [01] L0_ref01_en ++// ...... ++// [15] L0_ref15_en ++#define HEVC_MPRED_REF_EN_L1 (0x320d) ++#define P_HEVC_MPRED_REF_EN_L1 (volatile unsigned int *)((0x320d << 2) + 0xff620000) ++// [00] L1_ref00_en ++// [01] L1_ref01_en ++// ...... ++// [15] L1_ref15_en ++#define HEVC_MPRED_COLREF_EN_L0 (0x320e) ++#define P_HEVC_MPRED_COLREF_EN_L0 (volatile unsigned int *)((0x320e << 2) + 0xff620000) ++// [00] COL_L0_ref00_en ++// [01] COL_L0_ref01_en ++// ...... ++// [15] COL_L0_ref15_en ++#define HEVC_MPRED_COLREF_EN_L1 (0x320f) ++#define P_HEVC_MPRED_COLREF_EN_L1 (volatile unsigned int *)((0x320f << 2) + 0xff620000) ++// [00] COL_L1_ref00_en ++// [01] COL_L1_ref01_en ++// ...... ++// [15] COL_L1_ref15_en ++#define HEVC_MPRED_AXI_WCTRL (0x3210) ++#define P_HEVC_MPRED_AXI_WCTRL (volatile unsigned int *)((0x3210 << 2) + 0xff620000) ++// [11:8] aw_id_set[3:0] ++#define HEVC_MPRED_AXI_RCTRL (0x3211) ++#define P_HEVC_MPRED_AXI_RCTRL (volatile unsigned int *)((0x3211 << 2) + 0xff620000) ++// [11:8] ar_id_set[3:0] ++#define HEVC_MPRED_ABV_START_ADDR (0x3212) ++#define P_HEVC_MPRED_ABV_START_ADDR (volatile unsigned int *)((0x3212 << 2) + 0xff620000) ++#define HEVC_MPRED_MV_WR_START_ADDR (0x3213) ++#define P_HEVC_MPRED_MV_WR_START_ADDR (volatile unsigned int *)((0x3213 << 2) + 0xff620000) ++#define HEVC_MPRED_MV_RD_START_ADDR (0x3214) ++#define P_HEVC_MPRED_MV_RD_START_ADDR (volatile unsigned int *)((0x3214 << 2) + 0xff620000) ++#define HEVC_MPRED_MV_WPTR (0x3215) ++#define P_HEVC_MPRED_MV_WPTR (volatile unsigned int *)((0x3215 << 2) + 0xff620000) ++#define HEVC_MPRED_MV_RPTR (0x3216) ++#define P_HEVC_MPRED_MV_RPTR (volatile unsigned int *)((0x3216 << 2) + 0xff620000) ++#define HEVC_MPRED_MV_WR_ROW_JUMP (0x3217) ++#define P_HEVC_MPRED_MV_WR_ROW_JUMP (volatile unsigned int *)((0x3217 << 2) + 0xff620000) ++#define HEVC_MPRED_MV_RD_ROW_JUMP (0x3218) ++#define P_HEVC_MPRED_MV_RD_ROW_JUMP (volatile unsigned int *)((0x3218 << 2) + 0xff620000) ++#define HEVC_MPRED_CURR_LCU (0x3219) ++#define P_HEVC_MPRED_CURR_LCU (volatile unsigned int *)((0x3219 << 2) + 0xff620000) ++#define HEVC_MPRED_ABV_WPTR (0x321a) ++#define P_HEVC_MPRED_ABV_WPTR (volatile unsigned int *)((0x321a << 2) + 0xff620000) ++#define HEVC_MPRED_ABV_RPTR (0x321b) ++#define P_HEVC_MPRED_ABV_RPTR (volatile unsigned int *)((0x321b << 2) + 0xff620000) ++#define HEVC_MPRED_CTRL2 (0x321c) ++#define P_HEVC_MPRED_CTRL2 (volatile unsigned int *)((0x321c << 2) + 0xff620000) ++#define HEVC_MPRED_CTRL3 (0x321d) ++#define P_HEVC_MPRED_CTRL3 (volatile unsigned int *)((0x321d << 2) + 0xff620000) ++#define HEVC_MPRED_MV_WLCUY (0x321e) ++#define P_HEVC_MPRED_MV_WLCUY (volatile unsigned int *)((0x321e << 2) + 0xff620000) ++#define HEVC_MPRED_MV_RLCUY (0x321f) ++#define P_HEVC_MPRED_MV_RLCUY (volatile unsigned int *)((0x321f << 2) + 0xff620000) ++#define HEVC_MPRED_L0_REF00_POC (0x3220) ++#define P_HEVC_MPRED_L0_REF00_POC (volatile unsigned int *)((0x3220 << 2) + 0xff620000) ++#define HEVC_MPRED_L0_REF01_POC (0x3221) ++#define P_HEVC_MPRED_L0_REF01_POC (volatile unsigned int *)((0x3221 << 2) + 0xff620000) ++#define HEVC_MPRED_L0_REF02_POC (0x3222) ++#define P_HEVC_MPRED_L0_REF02_POC (volatile unsigned int *)((0x3222 << 2) + 0xff620000) ++#define HEVC_MPRED_L0_REF03_POC (0x3223) ++#define P_HEVC_MPRED_L0_REF03_POC (volatile unsigned int *)((0x3223 << 2) + 0xff620000) ++#define HEVC_MPRED_L0_REF04_POC (0x3224) ++#define P_HEVC_MPRED_L0_REF04_POC (volatile unsigned int *)((0x3224 << 2) + 0xff620000) ++#define HEVC_MPRED_L0_REF05_POC (0x3225) ++#define P_HEVC_MPRED_L0_REF05_POC (volatile unsigned int *)((0x3225 << 2) + 0xff620000) ++#define HEVC_MPRED_L0_REF06_POC (0x3226) ++#define P_HEVC_MPRED_L0_REF06_POC (volatile unsigned int *)((0x3226 << 2) + 0xff620000) ++#define HEVC_MPRED_L0_REF07_POC (0x3227) ++#define P_HEVC_MPRED_L0_REF07_POC (volatile unsigned int *)((0x3227 << 2) + 0xff620000) ++#define HEVC_MPRED_L0_REF08_POC (0x3228) ++#define P_HEVC_MPRED_L0_REF08_POC (volatile unsigned int *)((0x3228 << 2) + 0xff620000) ++#define HEVC_MPRED_L0_REF09_POC (0x3229) ++#define P_HEVC_MPRED_L0_REF09_POC (volatile unsigned int *)((0x3229 << 2) + 0xff620000) ++#define HEVC_MPRED_L0_REF10_POC (0x322a) ++#define P_HEVC_MPRED_L0_REF10_POC (volatile unsigned int *)((0x322a << 2) + 0xff620000) ++#define HEVC_MPRED_L0_REF11_POC (0x322b) ++#define P_HEVC_MPRED_L0_REF11_POC (volatile unsigned int *)((0x322b << 2) + 0xff620000) ++#define HEVC_MPRED_L0_REF12_POC (0x322c) ++#define P_HEVC_MPRED_L0_REF12_POC (volatile unsigned int *)((0x322c << 2) + 0xff620000) ++#define HEVC_MPRED_L0_REF13_POC (0x322d) ++#define P_HEVC_MPRED_L0_REF13_POC (volatile unsigned int *)((0x322d << 2) + 0xff620000) ++#define HEVC_MPRED_L0_REF14_POC (0x322e) ++#define P_HEVC_MPRED_L0_REF14_POC (volatile unsigned int *)((0x322e << 2) + 0xff620000) ++#define HEVC_MPRED_L0_REF15_POC (0x322f) ++#define P_HEVC_MPRED_L0_REF15_POC (volatile unsigned int *)((0x322f << 2) + 0xff620000) ++#define HEVC_MPRED_L1_REF00_POC (0x3230) ++#define P_HEVC_MPRED_L1_REF00_POC (volatile unsigned int *)((0x3230 << 2) + 0xff620000) ++#define HEVC_MPRED_L1_REF01_POC (0x3231) ++#define P_HEVC_MPRED_L1_REF01_POC (volatile unsigned int *)((0x3231 << 2) + 0xff620000) ++#define HEVC_MPRED_L1_REF02_POC (0x3232) ++#define P_HEVC_MPRED_L1_REF02_POC (volatile unsigned int *)((0x3232 << 2) + 0xff620000) ++#define HEVC_MPRED_L1_REF03_POC (0x3233) ++#define P_HEVC_MPRED_L1_REF03_POC (volatile unsigned int *)((0x3233 << 2) + 0xff620000) ++#define HEVC_MPRED_L1_REF04_POC (0x3234) ++#define P_HEVC_MPRED_L1_REF04_POC (volatile unsigned int *)((0x3234 << 2) + 0xff620000) ++#define HEVC_MPRED_L1_REF05_POC (0x3235) ++#define P_HEVC_MPRED_L1_REF05_POC (volatile unsigned int *)((0x3235 << 2) + 0xff620000) ++#define HEVC_MPRED_L1_REF06_POC (0x3236) ++#define P_HEVC_MPRED_L1_REF06_POC (volatile unsigned int *)((0x3236 << 2) + 0xff620000) ++#define HEVC_MPRED_L1_REF07_POC (0x3237) ++#define P_HEVC_MPRED_L1_REF07_POC (volatile unsigned int *)((0x3237 << 2) + 0xff620000) ++#define HEVC_MPRED_L1_REF08_POC (0x3238) ++#define P_HEVC_MPRED_L1_REF08_POC (volatile unsigned int *)((0x3238 << 2) + 0xff620000) ++#define HEVC_MPRED_L1_REF09_POC (0x3239) ++#define P_HEVC_MPRED_L1_REF09_POC (volatile unsigned int *)((0x3239 << 2) + 0xff620000) ++#define HEVC_MPRED_L1_REF10_POC (0x323a) ++#define P_HEVC_MPRED_L1_REF10_POC (volatile unsigned int *)((0x323a << 2) + 0xff620000) ++#define HEVC_MPRED_L1_REF11_POC (0x323b) ++#define P_HEVC_MPRED_L1_REF11_POC (volatile unsigned int *)((0x323b << 2) + 0xff620000) ++#define HEVC_MPRED_L1_REF12_POC (0x323c) ++#define P_HEVC_MPRED_L1_REF12_POC (volatile unsigned int *)((0x323c << 2) + 0xff620000) ++#define HEVC_MPRED_L1_REF13_POC (0x323d) ++#define P_HEVC_MPRED_L1_REF13_POC (volatile unsigned int *)((0x323d << 2) + 0xff620000) ++#define HEVC_MPRED_L1_REF14_POC (0x323e) ++#define P_HEVC_MPRED_L1_REF14_POC (volatile unsigned int *)((0x323e << 2) + 0xff620000) ++#define HEVC_MPRED_L1_REF15_POC (0x323f) ++#define P_HEVC_MPRED_L1_REF15_POC (volatile unsigned int *)((0x323f << 2) + 0xff620000) ++#define HEVC_MPRED_PIC_SIZE_EXT (0x3240) ++#define P_HEVC_MPRED_PIC_SIZE_EXT (volatile unsigned int *)((0x3240 << 2) + 0xff620000) ++#define HEVC_MPRED_DBG_MODE0 (0x3241) ++#define P_HEVC_MPRED_DBG_MODE0 (volatile unsigned int *)((0x3241 << 2) + 0xff620000) ++#define HEVC_MPRED_DBG_MODE1 (0x3242) ++#define P_HEVC_MPRED_DBG_MODE1 (volatile unsigned int *)((0x3242 << 2) + 0xff620000) ++#define HEVC_MPRED_DBG2_MODE (0x3243) ++#define P_HEVC_MPRED_DBG2_MODE (volatile unsigned int *)((0x3243 << 2) + 0xff620000) ++#define HEVC_MPRED_IMP_CMD0 (0x3244) ++#define P_HEVC_MPRED_IMP_CMD0 (volatile unsigned int *)((0x3244 << 2) + 0xff620000) ++#define HEVC_MPRED_IMP_CMD1 (0x3245) ++#define P_HEVC_MPRED_IMP_CMD1 (volatile unsigned int *)((0x3245 << 2) + 0xff620000) ++#define HEVC_MPRED_IMP_CMD2 (0x3246) ++#define P_HEVC_MPRED_IMP_CMD2 (volatile unsigned int *)((0x3246 << 2) + 0xff620000) ++#define HEVC_MPRED_IMP_CMD3 (0x3247) ++#define P_HEVC_MPRED_IMP_CMD3 (volatile unsigned int *)((0x3247 << 2) + 0xff620000) ++#define HEVC_MPRED_DBG2_DATA_0 (0x3248) ++#define P_HEVC_MPRED_DBG2_DATA_0 (volatile unsigned int *)((0x3248 << 2) + 0xff620000) ++#define HEVC_MPRED_DBG2_DATA_1 (0x3249) ++#define P_HEVC_MPRED_DBG2_DATA_1 (volatile unsigned int *)((0x3249 << 2) + 0xff620000) ++#define HEVC_MPRED_DBG2_DATA_2 (0x324a) ++#define P_HEVC_MPRED_DBG2_DATA_2 (volatile unsigned int *)((0x324a << 2) + 0xff620000) ++#define HEVC_MPRED_DBG2_DATA_3 (0x324b) ++#define P_HEVC_MPRED_DBG2_DATA_3 (volatile unsigned int *)((0x324b << 2) + 0xff620000) ++#define HEVC_MPRED_CTRL4 (0x324c) ++#define P_HEVC_MPRED_CTRL4 (volatile unsigned int *)((0x324c << 2) + 0xff620000) ++// [0] above intermedia data compress: 0=no-compress,1=compress;default:1'b0 ++// [1] collocated MV intermedia data compress: 0=no-compress,1=compress;default:1'b0 ++// [2] vp9_mode,0=hevc_mode,1=vp9_mode,default=0 ++// [6] vp9_use_prev_frame_mvs 0=not allow vp9_use_prev_frame_mvs,1=allow vp9_use_prev_frame_mvs,default=0 ++// [8] vp9_not_allow_hp 0=vp9_allow_hp,1=vp9_not_allow_hp,default=0 ++// [9] vp9_is_compound 0=vp9_is_not_compound,1=vp9_is_compound,default=0 ++// [12] vp9_ref_sign_bias[1] ref1(last) ref_sign_bias, default=0 ++// [13] vp9_ref_sign_bias[2] ref2(golden) ref_sign_bias,default=0 ++// [14] vp9_ref_sign_bias[3] ref3(altref) ref_sign_bias,default=0 ++#define HEVC_MPRED_CTRL5 (0x324d) ++#define P_HEVC_MPRED_CTRL5 (volatile unsigned int *)((0x324d << 2) + 0xff620000) ++#define HEVC_MPRED_POC24_CTRL0 (0x324e) ++#define P_HEVC_MPRED_POC24_CTRL0 (volatile unsigned int *)((0x324e << 2) + 0xff620000) ++#define HEVC_MPRED_POC24_CTRL1 (0x324f) ++#define P_HEVC_MPRED_POC24_CTRL1 (volatile unsigned int *)((0x324f << 2) + 0xff620000) ++#define HEVC_MPRED_DBG_DATA_0 (0x3250) ++#define P_HEVC_MPRED_DBG_DATA_0 (volatile unsigned int *)((0x3250 << 2) + 0xff620000) ++#define HEVC_MPRED_DBG_DATA_1 (0x3251) ++#define P_HEVC_MPRED_DBG_DATA_1 (volatile unsigned int *)((0x3251 << 2) + 0xff620000) ++#define HEVC_MPRED_DBG_DATA_2 (0x3252) ++#define P_HEVC_MPRED_DBG_DATA_2 (volatile unsigned int *)((0x3252 << 2) + 0xff620000) ++#define HEVC_MPRED_DBG_DATA_3 (0x3253) ++#define P_HEVC_MPRED_DBG_DATA_3 (volatile unsigned int *)((0x3253 << 2) + 0xff620000) ++#define HEVC_MPRED_DBG_DATA_4 (0x3254) ++#define P_HEVC_MPRED_DBG_DATA_4 (volatile unsigned int *)((0x3254 << 2) + 0xff620000) ++#define HEVC_MPRED_DBG_DATA_5 (0x3255) ++#define P_HEVC_MPRED_DBG_DATA_5 (volatile unsigned int *)((0x3255 << 2) + 0xff620000) ++#define HEVC_MPRED_DBG_DATA_6 (0x3256) ++#define P_HEVC_MPRED_DBG_DATA_6 (volatile unsigned int *)((0x3256 << 2) + 0xff620000) ++#define HEVC_MPRED_DBG_DATA_7 (0x3257) ++#define P_HEVC_MPRED_DBG_DATA_7 (volatile unsigned int *)((0x3257 << 2) + 0xff620000) ++#define HEVC_MPRED_CTRL6 (0x3258) ++#define P_HEVC_MPRED_CTRL6 (volatile unsigned int *)((0x3258 << 2) + 0xff620000) ++#define HEVC_MPRED_CTRL7 (0x3259) ++#define P_HEVC_MPRED_CTRL7 (volatile unsigned int *)((0x3259 << 2) + 0xff620000) ++#define HEVC_MPRED_CTRL8 (0x325a) ++#define P_HEVC_MPRED_CTRL8 (volatile unsigned int *)((0x325a << 2) + 0xff620000) ++#define HEVC_MPRED_CTRL9 (0x325b) ++#define P_HEVC_MPRED_CTRL9 (volatile unsigned int *)((0x325b << 2) + 0xff620000) ++#define HEVC_MPRED_CUR_POC (0x3260) ++#define P_HEVC_MPRED_CUR_POC (volatile unsigned int *)((0x3260 << 2) + 0xff620000) ++#define HEVC_MPRED_COL_POC (0x3261) ++#define P_HEVC_MPRED_COL_POC (volatile unsigned int *)((0x3261 << 2) + 0xff620000) ++#define HEVC_MPRED_MV_RD_END_ADDR (0x3262) ++#define P_HEVC_MPRED_MV_RD_END_ADDR (volatile unsigned int *)((0x3262 << 2) + 0xff620000) ++// ++// Closing file: hevc_mpred_regs.h ++// ++//------------------------------------------------------------------------------ ++// HEVC_IPP module level register offset ++//------------------------------------------------------------------------------ ++// ++// Reading file: hevc_ipp_regs.h ++// ++// John A. Thodiyil ++// Register map for intra/inter/pcm pixel-prediction + MCRCC + DECOMP ++// August 14th, 2013 ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HEVC_IPP_CBUS_BASE = 0x04 ++// ----------------------------------------------- ++#define HEVCD_IPP_TOP_CNTL (0x3400) ++#define P_HEVCD_IPP_TOP_CNTL (volatile unsigned int *)((0x3400 << 2) + 0xff620000) ++// [0] -- software reset ipp and mpp ++// [1] -- enable ipp ++// [3:2] -- reserved ++// [5:4] -- codec[1:0] 00:hevc 01:vp9 10:avs2 11:reserved ++// [31:6] -- reserved ++#define HEVCD_IPP_TOP_STATUS (0x3401) ++#define P_HEVCD_IPP_TOP_STATUS (volatile unsigned int *)((0x3401 << 2) + 0xff620000) ++// [0] -- ready for next tile/frame ++// [1] -- ready for next ctb ++// [2] -- ready for next slice ++// [3] -- reserved ++// [4] -- ipp_axi_rd_idle ++// [5] -- ipp_axi_wr_idle ++// [6] -- mpp_axi_rd_idle ++// [31:7] -- reserved ++#define HEVCD_IPP_TOP_FRMCONFIG (0x3402) ++#define P_HEVCD_IPP_TOP_FRMCONFIG (volatile unsigned int *)((0x3402 << 2) + 0xff620000) ++// [14:0] -- frame width in luma pixels ++// [30:16] -- frame height in luma pixels ++#define HEVCD_IPP_TOP_TILECONFIG1 (0x3403) ++#define P_HEVCD_IPP_TOP_TILECONFIG1 (volatile unsigned int *)((0x3403 << 2) + 0xff620000) ++// [11:0] -- tile_width_in_lcu ++// [27:16] -- tile_height_in_lcu ++#define HEVCD_IPP_TOP_TILECONFIG2 (0x3404) ++#define P_HEVCD_IPP_TOP_TILECONFIG2 (volatile unsigned int *)((0x3404 << 2) + 0xff620000) ++// [11:0] -- tile_offset_x_in_lcu ++// [27:16] -- tile_offset_y_in_lcu ++#define HEVCD_IPP_TOP_TILECONFIG3 (0x3405) ++#define P_HEVCD_IPP_TOP_TILECONFIG3 (volatile unsigned int *)((0x3405 << 2) + 0xff620000) ++// [0] -- tiles_enabled_flag ++// [31:1] -- reserved ++#define HEVCD_IPP_TOP_LCUCONFIG (0x3406) ++#define P_HEVCD_IPP_TOP_LCUCONFIG (volatile unsigned int *)((0x3406 << 2) + 0xff620000) ++// [6:0] -- lcu size in pixels ++#define HEVCD_IPP_TOP_FRMCTL (0x3407) ++#define P_HEVCD_IPP_TOP_FRMCTL (volatile unsigned int *)((0x3407 << 2) + 0xff620000) ++// [x] -- start ipp tile decode ++#define HEVCD_IPP_CONFIG (0x3408) ++#define P_HEVCD_IPP_CONFIG (volatile unsigned int *)((0x3408 << 2) + 0xff620000) ++// [0] -- ipp_strong_intra_smoothing_enable_flag ++// [1] -- cfg_ipp_constrained_intra_pred_flag ++// [31:2] -- reserved ++#define HEVCD_IPP_LINEBUFF_BASE (0x3409) ++#define P_HEVCD_IPP_LINEBUFF_BASE (volatile unsigned int *)((0x3409 << 2) + 0xff620000) ++// [31:14] -- intra-prediction line-buffer 16KByte axi address ++// [13:0] -- reserved ++#define HEVCD_IPP_INTR_MASK (0x340a) ++#define P_HEVCD_IPP_INTR_MASK (volatile unsigned int *)((0x340a << 2) + 0xff620000) ++// [0] -- tile/frame ready ++// [1] -- ctb ready ++// [2] -- slice ready ++// [31:3] -- reserved ++#define HEVCD_IPP_AXIIF_CONFIG (0x340b) ++#define P_HEVCD_IPP_AXIIF_CONFIG (volatile unsigned int *)((0x340b << 2) + 0xff620000) ++// [3:0] -- little_endian ++// [5:4] -- address_format 00:linear 01:32x32 10:64x32 ++// [7:6] -- reserved ++// [9:8] -- Linear_LineAlignment 00:16byte 01:32byte 10:64byte ++// [11:10] -- reserved ++// [12] -- CbCr_byte_swap ++// [31:13] -- reserved ++#define HEVCD_IPP_BITDEPTH_CONFIG (0x340c) ++#define P_HEVCD_IPP_BITDEPTH_CONFIG (volatile unsigned int *)((0x340c << 2) + 0xff620000) ++// [1:0] -- bit_depth_luma 00:8 01:9 10:10 ++// [3:2] -- bit_depth_chroma 00:8 01:9 10:10 ++// [31:4] -- reserved ++#define HEVCD_IPP_SWMPREDIF_CONFIG (0x3410) ++#define P_HEVCD_IPP_SWMPREDIF_CONFIG (volatile unsigned int *)((0x3410 << 2) + 0xff620000) ++// [0] -- swmpredif_enable ++// [31:1] -- reserved ++#define HEVCD_IPP_SWMPREDIF_STATUS (0x3411) ++#define P_HEVCD_IPP_SWMPREDIF_STATUS (volatile unsigned int *)((0x3411 << 2) + 0xff620000) ++// [0] -- swmpredif_rdy ++// [7:1] -- reserved ++// [14:8] -- swmpredif_fifospace ++// [31:15] -- reserved ++#define HEVCD_IPP_SWMPREDIF_CTBINFO (0x3412) ++#define P_HEVCD_IPP_SWMPREDIF_CTBINFO (volatile unsigned int *)((0x3412 << 2) + 0xff620000) ++// [10:0] -- swmpredif_ctb_x ++// [15:11] -- reserved ++// [26:16] -- swmpredif_ctb_y ++// [30:27] -- reserved ++// [31] -- swmpredif_newslice ++#define HEVCD_IPP_SWMPREDIF_PUINFO0 (0x3413) ++#define P_HEVCD_IPP_SWMPREDIF_PUINFO0 (volatile unsigned int *)((0x3413 << 2) + 0xff620000) ++// [31:0] -- swmpredif_imp_cmd[31:0] ++#define HEVCD_IPP_SWMPREDIF_PUINFO1 (0x3414) ++#define P_HEVCD_IPP_SWMPREDIF_PUINFO1 (volatile unsigned int *)((0x3414 << 2) + 0xff620000) ++// [31:0] -- swmpredif_imp_cmd[63:32] ++#define HEVCD_IPP_SWMPREDIF_PUINFO2 (0x3415) ++#define P_HEVCD_IPP_SWMPREDIF_PUINFO2 (volatile unsigned int *)((0x3415 << 2) + 0xff620000) ++// [31:0] -- swmpredif_imp_cmd[95:64] ++#define HEVCD_IPP_SWMPREDIF_PUINFO3 (0x3416) ++#define P_HEVCD_IPP_SWMPREDIF_PUINFO3 (volatile unsigned int *)((0x3416 << 2) + 0xff620000) ++// [31:0] -- swmpredif_imp_cmd[127:96] ++#define HEVCD_IPP_SWMPREDIF_PUINFO4 (0x3417) ++#define P_HEVCD_IPP_SWMPREDIF_PUINFO4 (volatile unsigned int *)((0x3417 << 2) + 0xff620000) ++// [31:0] -- swmpredif_imp_cmd[159:128] ++#define HEVCD_IPP_SWMPREDIF_PUINFO5 (0x3418) ++#define P_HEVCD_IPP_SWMPREDIF_PUINFO5 (volatile unsigned int *)((0x3418 << 2) + 0xff620000) ++// [31:0] -- swmpredif_imp_cmd[191:160] ++// writing to HEVCD_IPP_SWMPREDIF_PUINFO5 ++// completes command, should be last to write. ++#define HEVCD_IPP_DYNCLKGATE_CONFIG (0x3420) ++#define P_HEVCD_IPP_DYNCLKGATE_CONFIG (volatile unsigned int *)((0x3420 << 2) + 0xff620000) ++// [0] -- mpp_wpredict_clkgate_disbl ++// [1] -- mpp_ref_fetch_clkgate_disbl ++// [2] -- mpp_interpol_top_clkgate_disbl ++// [3] -- mpp_4x4mcr_clkgate_disbl ++// [4] -- mpp_ref_pack_clkgate_disbl ++// [5] -- mpp_mdec_if_clkgate_disbl ++// [7:6] -- reserved ++// [8] -- ipp_res_fetch_clkgate_disbl ++// [9] -- ipp_iqitIf_clkgate_disbl ++// [10] -- ipp_dblkCmdIf_clkgate_disbl ++// [11] -- ipp_dblkIf_clkgate_disbl ++// [12] -- ipp_cntl_clkgate_disbl ++// [13] -- ipp_nsamples_proc_clkgate_disbl ++// [14] -- ipp_refroute_clkgate_disbl ++// [15] -- ipp_spred_clkgate_disbl ++// [16] -- ipp_reg_clkgate_disbl ++// [17] -- ipp_recon_clkgate_disbl ++// [19:18] -- reserved ++// [20] -- decomp_cntl_clkgate_disbl ++// [21] -- decomp_axiIf_clkgate_disbl ++// [22] -- decomp_dcache_clkgate_disbl ++// [23] -- decomp_hcache_clkgate_disbl ++// [24] -- decomp_gearup_clkgate_disbl ++// [25] -- decomp_cores_clkgate_disbl ++// [26] -- decomp_rdroute_clkgate_disbl ++// [27] -- reserved ++// [28] -- master_decomp_clkgate_disbl ++// [29] -- master_mpp_clkgate_disbl ++// [30] -- master_ipp_clkgate_disbl ++// [31] -- master_ipp_mpp_decomp_clkgate_disbl ++#define HEVCD_IPP_DYNCLKGATE_STATUS (0x3421) ++#define P_HEVCD_IPP_DYNCLKGATE_STATUS (volatile unsigned int *)((0x3421 << 2) + 0xff620000) ++// [0] -- mpp_wpredict_clkgate ++// [1] -- mpp_ref_fetch_clkgate ++// [2] -- mpp_interpol_top_clkgate ++// [3] -- mpp_4x4mcr_clkgate ++// [4] -- mpp_ref_pack_clkgate ++// [5] -- mpp_mdec_if_clkgate ++// [7:6] -- reserved ++// [8] -- ipp_res_fetch_clkgate ++// [9] -- ipp_iqitIf_clkgate ++// [10] -- ipp_dblkCmdIf_clkgate ++// [11] -- ipp_dblkIf_clkgate ++// [12] -- ipp_cntl_clkgate ++// [13] -- ipp_nsamples_proc_clkgate ++// [14] -- ipp_refroute_clkgate ++// [15] -- ipp_spred_clkgate ++// [16] -- ipp_reg_clkgate ++// [17] -- ipp_recon_clkgate ++// [19:18] -- reserved ++// [20] -- decomp_cntl_clkgate ++// [21] -- decomp_axiIf_clkgate ++// [22] -- decomp_dcache_clkgate ++// [23] -- decomp_hcache_clkgate ++// [24] -- decomp_gearup_clkgate ++// [25] -- decomp_cores_clkgate ++// [26] -- decomp_rdroute_clkgate ++// [27] -- reserved ++// [30:28] -- reserved ++// [31] -- mcrcc_axi_clkgate ++#define HEVCD_IPP_DBG_SEL (0x3430) ++#define P_HEVCD_IPP_DBG_SEL (volatile unsigned int *)((0x3430 << 2) + 0xff620000) ++// [3:0] -- module_level_sel ++// [7:4] -- mpp_ipp_top_level ++// [8] -- ipp_sel ++// [31:9] -- reserved ++#define HEVCD_IPP_DBG_DATA (0x3431) ++#define P_HEVCD_IPP_DBG_DATA (volatile unsigned int *)((0x3431 << 2) + 0xff620000) ++// [31:0] -- Debug information ++////////////////////////////////////////////////////////////////////////////// ++///// MPP Registers //////////////////// ++////////////////////////////////////////////////////////////////////////////// ++// Canvas Anchor to Axi-Address translation table ++#define HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR (0x3460) ++#define P_HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR (volatile unsigned int *)((0x3460 << 2) + 0xff620000) ++// [0] -- anc2axi canvas address translation table switch 0:sw 1:hw ++// [1] -- access type 1:wr 0:rd ++// [2] -- auto index increment ++// [7:3] -- reserved ++// [15:8] -- start index ++// [31:16] -- reserved ++//`define HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR 8'h61 ++// [0] -- anc2axi canvas address translation table access type 1:wr 0:rd ++// [15:8] -- anc2axi canvas address translation table access index ++// [31:16] -- anc2axi canvas address translation table access write data, 16KByte axi address ++// -- obsoleted ++//`define HEVCD_MPP_ANC2AXI_TBL_WDATA_ADDR 8'h62 // NU ++// [x] -- not used ++//`define HEVCD_MPP_ANC2AXI_TBL_RDATA_ADDR 8'h63 ++// [15:0] -- anc2axi canvas address translation table access read data ++// -- obsoleted ++#define HEVCD_MPP_ANC2AXI_TBL_DATA (0x3464) ++#define P_HEVCD_MPP_ANC2AXI_TBL_DATA (volatile unsigned int *)((0x3464 << 2) + 0xff620000) ++// [26:0] -- anc2axi address r/w 32byte aligned ++// [31:27] -- reserved ++#define HEVCD_MPP_WEIGHTPRED_CNTL_ADDR (0x347b) ++#define P_HEVCD_MPP_WEIGHTPRED_CNTL_ADDR (volatile unsigned int *)((0x347b << 2) + 0xff620000) ++// [0] -- weighted_pred_flag ++#define HEVCD_MPP_L0_WEIGHT_FLAG_ADDR (0x347c) ++#define P_HEVCD_MPP_L0_WEIGHT_FLAG_ADDR (volatile unsigned int *)((0x347c << 2) + 0xff620000) ++// [15:0] -- luma_weght_flag0[15:0], indexed by refidx0 ++// [31:16] -- chroma_weght_flag0[15:0], indexed by refidx0 ++#define HEVCD_MPP_L1_WEIGHT_FLAG_ADDR (0x347d) ++#define P_HEVCD_MPP_L1_WEIGHT_FLAG_ADDR (volatile unsigned int *)((0x347d << 2) + 0xff620000) ++// [15:0] -- luma_weght_flag1[15:0], indexed by refidx1 ++// [31:16] -- chroma_weght_flag1[15:0], indexed by refidx1 ++#define HEVCD_MPP_YLOG2WGHTDENOM_ADDR (0x347e) ++#define P_HEVCD_MPP_YLOG2WGHTDENOM_ADDR (volatile unsigned int *)((0x347e << 2) + 0xff620000) ++// [3:0] -- luma_log2_weight_denom ++#define HEVCD_MPP_DELTACLOG2WGHTDENOM_ADDR (0x347f) ++#define P_HEVCD_MPP_DELTACLOG2WGHTDENOM_ADDR (volatile unsigned int *)((0x347f << 2) + 0xff620000) ++// [4:0] -- delta_chroma_log2_weight_denom ++#define HEVCD_MPP_WEIGHT_ADDR (0x3480) ++#define P_HEVCD_MPP_WEIGHT_ADDR (volatile unsigned int *)((0x3480 << 2) + 0xff620000) ++// [5:0] -- weight_rw_addr ++// [0] -- DELTA_WEIGHT0 ++// [1] -- OFFSET0 ++// [2] -- DELTA_WEIGHT1 ++// [3] -- OFFSET1 ++// ...... ++// [62] -- DELTA_WEIGHT31 ++// [63] -- OFFSET31 ++#define HEVCD_MPP_WEIGHT_DATA (0x3481) ++#define P_HEVCD_MPP_WEIGHT_DATA (volatile unsigned int *)((0x3481 << 2) + 0xff620000) ++// For DELTA_WEIGHT : ++// [7:0] -- delta_y_weight for refidx0:0 ++// [15:8] -- delta_cb_weight for refidx0:0 ++// [23:16] -- delta_cr_weight for refidx0:0 ++// For OFFSET : ++// [7:0] -- luma_offset for refidx0:0 ++// [17:8] -- delta_cb_offset for refidx0:0 ++// [27:18] -- delta_cr_offset for refidx0:0 ++// ID to Anchor-Canvas-Address table ++// [31:13] reserved ++// [12:8] access_index ++// [7:2] reserved ++// [1] auto_inc_read ++// [0] auto_inc_write ++#define HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR (0x34c0) ++#define P_HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR (volatile unsigned int *)((0x34c0 << 2) + 0xff620000) ++// Id[4:0] --> {AnchorAddrCr[7:0],AnchorAddrCb[7:0],AnchorAddrY[7:0]} ++#define HEVCD_MPP_ANC_CANVAS_DATA_ADDR (0x34c1) ++#define P_HEVCD_MPP_ANC_CANVAS_DATA_ADDR (volatile unsigned int *)((0x34c1 << 2) + 0xff620000) ++// [0] -- decomp_nocompress ++// [1] -- decomp_dcache_bypass ++// [2] -- reserved ++// [3] -- decomp_smem_bdepth888 ++// [4] -- decomp_paged_mem_mode ++// [30:5] -- reserved ++// [31] -- decomp_axif_lbmode888 ++#define HEVCD_MPP_DECOMP_CTL1 (0x34c2) ++#define P_HEVCD_MPP_DECOMP_CTL1 (volatile unsigned int *)((0x34c2 << 2) + 0xff620000) ++// [23:0] -- header1_offset : 32byte address from canvas base ++// [31:24] -- reserved ++#define HEVCD_MPP_DECOMP_CTL2 (0x34c3) ++#define P_HEVCD_MPP_DECOMP_CTL2 (volatile unsigned int *)((0x34c3 << 2) + 0xff620000) ++// [9:0] -- decomp_default_Y ++// [19:10] -- decomp_default_Cb ++// [29:20] -- decomp_dafault_Cr ++// [31:30] -- bitdepth_sel 00:8bit 01:9bit 10:10bit ++#define HEVCD_MPP_DECOMP_CTL3 (0x34c4) ++#define P_HEVCD_MPP_DECOMP_CTL3 (volatile unsigned int *)((0x34c4 << 2) + 0xff620000) ++// HEVCD_MPP_DECOMP_PERFMON_CTL ++// [0] percount_reset ++// [3:1] perfcount_sel ++// [31:4] reserved ++// {1'b0,perfcount_sel[1:0]} perfcount ++// 0 raw_hcache_cnt ++// 1 hit_hcache_cnt ++// 2 raw_dcache_cnt ++// 3 hit_dcache_cnt ++// {1'b1,perfcount_sel[1:0]} perfcount ++// 0 fast_num_compburst ++// 1 slow_num_compburst ++// 2,3 raw_num_ncompburst ++#define HEVCD_MPP_DECOMP_PERFMON_CTL (0x34c5) ++#define P_HEVCD_MPP_DECOMP_PERFMON_CTL (volatile unsigned int *)((0x34c5 << 2) + 0xff620000) ++// HEVCD_MPP_DECOMP_PERFMON_DATA ++// [31:0] percount_data ++#define HEVCD_MPP_DECOMP_PERFMON_DATA (0x34c6) ++#define P_HEVCD_MPP_DECOMP_PERFMON_DATA (volatile unsigned int *)((0x34c6 << 2) + 0xff620000) ++// HEVCD_MPP_DECOMP_AXIURG_CTL ++// [1:0] -- decomp_hdrurg 00:Normal 01:Urgent 10:SuperUrgent ++// [2] -- decomp_fpathurg_en 1->Urgent if below lo_thresh ++// [3] -- decomp_spathurg_en 1->Urgent if below lo_thresh ++// [10:4] -- decomp_fpathurg_lothresh [32byte steps : max 96] ++// [17:11] -- decomp_fpathurg_hithresh [32byte steps : max 96] ++// [24:18] -- decomp_spathurg_lothresh [32byte steps : max 64] ++// [31:25] -- decomp_spathurg_hithresh [32byte steps : max 64] ++#define HEVCD_MPP_DECOMP_AXIURG_CTL (0x34c7) ++#define P_HEVCD_MPP_DECOMP_AXIURG_CTL (volatile unsigned int *)((0x34c7 << 2) + 0xff620000) ++// HEVCD_MPP_VDEC_MCR_CTL ++// [0] -- mcr_mdec_mode : 1:mcr fetch used by vdec:mdec ++// [3:1] -- reserved ++// [4] -- mcr_mdec_8byte_endianess : 1:big 0:little ++// [31:5] -- reserved ++#define HEVCD_MPP_VDEC_MCR_CTL (0x34c8) ++#define P_HEVCD_MPP_VDEC_MCR_CTL (volatile unsigned int *)((0x34c8 << 2) + 0xff620000) ++////////////////////////////////////////////////////////////////////////////// ++///// MCRCC_AXI Registers //////////////////// ++////////////////////////////////////////////////////////////////////////////// ++// HEVCD_MCRCC_CTL1 ++// 31:12 ++// 11:10 // 01: top 10:bot 11:frame ++// 9:8 ++// 7:6 ++// 5:4 ++// 3 ++// 2 // not used for hevc ++// 1 ++// 0 ++#define HEVCD_MCRCC_CTL1 (0x34f0) ++#define P_HEVCD_MCRCC_CTL1 (volatile unsigned int *)((0x34f0 << 2) + 0xff620000) ++// HEVCD_MCRCC_CTL2 ++// 31:24 ++// 23:16 ++// 15:8 ++// 7:0 ++#define HEVCD_MCRCC_CTL2 (0x34f1) ++#define P_HEVCD_MCRCC_CTL2 (volatile unsigned int *)((0x34f1 << 2) + 0xff620000) ++// HEVCD_MCRCC_CTL3 ++// 31:24 ++// 23:16 ++// 15:8 ++// 7:0 ++#define HEVCD_MCRCC_CTL3 (0x34f2) ++#define P_HEVCD_MCRCC_CTL3 (volatile unsigned int *)((0x34f2 << 2) + 0xff620000) ++// HEVCD_MCRCC_PERFMON_CTL ++// [0] percount_reset ++// [3:1] perfcount_sel ++// [31:4] reserved ++// perfcount_sel[2:0] perfcount ++// 0 raw_mcr_cnt ++// 1 hit_mcr_cnt ++// 2 byp_mcr_cnt_nchoutwin ++// 3 byp_mcr_cnt_nchcanv ++// 4 miss_mcr_cnt_0 ++// 5 miss_mcr_cnt_1 ++// 6 hit_mcr_cnt_0 ++// 7 hit_mcr_cnt_1 ++#define HEVCD_MCRCC_PERFMON_CTL (0x34f3) ++#define P_HEVCD_MCRCC_PERFMON_CTL (volatile unsigned int *)((0x34f3 << 2) + 0xff620000) ++// HEVCD_MCRCC_PERFMON_DATA ++// [31:0] percount_data ++#define HEVCD_MCRCC_PERFMON_DATA (0x34f4) ++#define P_HEVCD_MCRCC_PERFMON_DATA (volatile unsigned int *)((0x34f4 << 2) + 0xff620000) ++////////////////////////////////////////////////////////////////////////////// ++///// VP9 Decoder Registers //////////////////// ++////////////////////////////////////////////////////////////////////////////// ++// VP9D_MPP_INTERPOL_CFG0 ++// [2:0] VP9 MC Interpolation type ++ // 0-3:perframe type 4:per partition type ++// [3] reserved ++// [4] V99 MV precision ++ // 1:high precision else mv=mv*2 ++// [31:5] reserved ++#define VP9D_MPP_INTERPOL_CFG0 (0x3440) ++#define P_VP9D_MPP_INTERPOL_CFG0 (volatile unsigned int *)((0x3440 << 2) + 0xff620000) ++// VP9D_MPP_REF_SCALE_ENBL ++// [7:0] VP9 MC reference scaled info ++// [15:0] VP9 MC reference scaled dir 0:Dwn 1:Up ++// [31:16] reserved ++#define VP9D_MPP_REF_SCALE_ENBL (0x3441) ++#define P_VP9D_MPP_REF_SCALE_ENBL (volatile unsigned int *)((0x3441 << 2) + 0xff620000) ++// VP9D_MPP_REFINFO_TBL_ACCCONFIG ++// [1:0] reserved ++// [2] auto_inc_index/field ++// [5:3] reference index 0:last 1:golden 2:altref ++// [8:6] info field 0: 1: ++ // 2: ++ // 4: -- 32byte aligned ++// [31:9] reserved ++#define VP9D_MPP_REFINFO_TBL_ACCCONFIG (0x3442) ++#define P_VP9D_MPP_REFINFO_TBL_ACCCONFIG (volatile unsigned int *)((0x3442 << 2) + 0xff620000) ++// VP9D_MPP_REFINFO_DATA ++// [n:0] refinfo_tbl[index]field] wr_data/rd_data ++#define VP9D_MPP_REFINFO_DATA (0x3443) ++#define P_VP9D_MPP_REFINFO_DATA (volatile unsigned int *)((0x3443 << 2) + 0xff620000) ++// ++// Closing file: hevc_ipp_regs.h ++// ++//------------------------------------------------------------------------------ ++// HEVC_DBLK module level register offset ++//------------------------------------------------------------------------------ ++// ++// Reading file: hevc_dblk_regs.h ++// ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HEVC_DBLK_CBUS_BASE = 0x05 ++// ----------------------------------------------- ++//cfg0[0]; //software_reset ++//cfg0[1]; //status clear, only for axi error or pic_done ++//cfg0[2]; //clock_forced_on_all ++//cfg0[3]; //clock_forced_off_all ++//cfg0[11:8]; //PU FIFO Threshold , 0:16 1:1 ... 1:15 ++//cfg0[15:12]; //TU FIFO Threshold>>4, 0:16<<4 1:1<<4 ... 1:15<<4 ++//cfg0[29:16]; //clock_forced_on_submodules ++#define HEVC_DBLK_CFG0 (0x3500) ++#define P_HEVC_DBLK_CFG0 (volatile unsigned int *)((0x3500 << 2) + 0xff620000) ++//cfg1[1:0]; //ctb_size 0:64x64 1:32x32 2:16x16 ++//cfg1[2]; //ignore_out_of_boundary ++//cfg1[3]; //pcm_loop_filter_disabled_flag ++//cfg1[8:4]; //pps_cb_qp_offset (-12~12,inclusive) ++//cfg1[13:9]; //pps_cr_qp_offset (-12~12,inclusive) ++//cfg1[14]; //ctbx,y swap in pu i/f ++//cfg1[15]; //sao_corner_45_degree_all_software_control ++#define HEVC_DBLK_CFG1 (0x3501) ++#define P_HEVC_DBLK_CFG1 (volatile unsigned int *)((0x3501 << 2) + 0xff620000) ++//cfg2[15:0]; //picture_size_width ++//cfg2[31:16]; //picture_size_height ++#define HEVC_DBLK_CFG2 (0x3502) ++#define P_HEVC_DBLK_CFG2 (volatile unsigned int *)((0x3502 << 2) + 0xff620000) ++//cfg3[3:0]; //parameter_axi_arid ++//cfg3[7:4]; //parameter_axi_awid ++//cfg3[11:8]; //parameter_axi_wid ++//cfg3[12]; //parameter_axi_not_check_write_response ++//cfg3[19:16]; //data_axi_arid ++//cfg3[23:20]; //data_axi_awid ++//cfg3[27:24]; //data_axi_wid ++//cfg3[28]; //data_axi_not_check_write_response ++#define HEVC_DBLK_CFG3 (0x3503) ++#define P_HEVC_DBLK_CFG3 (volatile unsigned int *)((0x3503 << 2) + 0xff620000) ++//cfg4[31:0]; //parameter_axi_start_address ++#define HEVC_DBLK_CFG4 (0x3504) ++#define P_HEVC_DBLK_CFG4 (volatile unsigned int *)((0x3504 << 2) + 0xff620000) ++//cfg5[31:0]; //data_axi_start_address ++#define HEVC_DBLK_CFG5 (0x3505) ++#define P_HEVC_DBLK_CFG5 (volatile unsigned int *)((0x3505 << 2) + 0xff620000) ++//cfg6[9:0]; //tile_ctbx ++//cfg6[25:16]; //tile_ctby ++//cfg6[31]; //tile_enabled ++#define HEVC_DBLK_CFG6 (0x3506) ++#define P_HEVC_DBLK_CFG6 (volatile unsigned int *)((0x3506 << 2) + 0xff620000) ++//cfg7[9:0]; //tile_ctbxsize ++//cfg7[25:16]; //tile_ctbysize ++#define HEVC_DBLK_CFG7 (0x3507) ++#define P_HEVC_DBLK_CFG7 (volatile unsigned int *)((0x3507 << 2) + 0xff620000) ++//cfg8[9:0]; //start_ctbx, normally equals to tile_ctbx ++//cfg8[25:16]; //start_ctby, normally equals to tile_ctby ++//cfg8[31]; //start, self_cleared signal, normally set it at the begin of tile ++#define HEVC_DBLK_CFG8 (0x3508) ++#define P_HEVC_DBLK_CFG8 (volatile unsigned int *)((0x3508 << 2) + 0xff620000) ++//cfg9[0] //loop_filter_across_tiles_enabled_flag ++//cfg9[1] //loop_filter_across_slices_enabled_flag ++//cfg9[2] //deblocking_filter_disabled_flag ++//cfg9[6:3] //beta_offset_div2 (-6~6,inclusive) ++//cfg9[10:7] //tc_offset_div2 (-6~6,inclusive) ++#define HEVC_DBLK_CFG9 (0x3509) ++#define P_HEVC_DBLK_CFG9 (volatile unsigned int *)((0x3509 << 2) + 0xff620000) ++//cfga[4:0] //corner45degree{FIFO_CNT} ++//cfga[31:27] //corner45degree{EN,FIFO_CLR,FIFO_PUSH,DATA,DATA_SEL} ++#define HEVC_DBLK_CFGA (0x350a) ++#define P_HEVC_DBLK_CFGA (volatile unsigned int *)((0x350a << 2) + 0xff620000) ++//cfgb[3:0] //0:HEVC 1:VP9 ... ++#define HEVC_DBLK_CFGB (0x350b) ++#define P_HEVC_DBLK_CFGB (volatile unsigned int *)((0x350b << 2) + 0xff620000) ++//cfgc[31:0] //cfg_addr_y1 ++#define HEVC_DBLK_CFGC (0x350c) ++#define P_HEVC_DBLK_CFGC (volatile unsigned int *)((0x350c << 2) + 0xff620000) ++//TODO description ++#define HEVC_DBLK_STS0 (0x350d) ++#define P_HEVC_DBLK_STS0 (volatile unsigned int *)((0x350d << 2) + 0xff620000) ++//TODO description ++#define HEVC_DBLK_STS1 (0x350e) ++#define P_HEVC_DBLK_STS1 (volatile unsigned int *)((0x350e << 2) + 0xff620000) ++// ++// Closing file: hevc_dblk_regs.h ++// ++//------------------------------------------------------------------------------ ++// HEVC_SAO module level register offset ++//------------------------------------------------------------------------------ ++// ++// Reading file: hevc_sao_regs.h ++// ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HEVC_SAO_CBUS_BASE = 0x06 ++// ----------------------------------------------- ++#define HEVC_SAO_VERSION (0x3600) ++#define P_HEVC_SAO_VERSION (volatile unsigned int *)((0x3600 << 2) + 0xff620000) ++// [31:0] reversion default:32'h00010001 ++#define HEVC_SAO_CTRL0 (0x3601) ++#define P_HEVC_SAO_CTRL0 (volatile unsigned int *)((0x3601 << 2) + 0xff620000) ++// [3:0] lcu_size_log2 ++// [31] above intermedia data compress: 0=no-compress,1=compress;default:1'b0 ++#define HEVC_SAO_CTRL1 (0x3602) ++#define P_HEVC_SAO_CTRL1 (volatile unsigned int *)((0x3602 << 2) + 0xff620000) ++// [31:24] ar_fifo1_axi_thred ++// [23:16] ar_fifo0_axi_thred ++// [15:14] axi_linealign, 0-16bytes, 1-32bytes, 2-64bytes ++// [13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32 ++// [11:08] axi_lendian_C ++// [07:04] axi_lendian_Y ++// [3] reserved ++// [2] clk_forceon ++// [1] dw_disable:disable double write output ++// [0] cm_disable:disable compress output ++#define HEVC_SAO_INT_EN (0x3603) ++#define P_HEVC_SAO_INT_EN (volatile unsigned int *)((0x3603 << 2) + 0xff620000) ++// [0] sao_int_enable ++// [1] sao_int_amrisc_level ++// [2] sao_int_cpu_level ++// [3] slice_done_int_amrisc_enable ++// [4] slice_done_int_cpu_enable ++// [15] disable_sao_int_clock_gating ++#define HEVC_SAO_INT_STATUS (0x3604) ++#define P_HEVC_SAO_INT_STATUS (volatile unsigned int *)((0x3604 << 2) + 0xff620000) ++// [0] slice_done IRQ ++// [31] write "1"=slice start(self clear,read always return "0") ++#define HEVC_SAO_PIC_SIZE (0x3605) ++#define P_HEVC_SAO_PIC_SIZE (volatile unsigned int *)((0x3605 << 2) + 0xff620000) ++// [15:0] pic_width[15:0] ++// [31:16] pic_height[15:0] ++#define HEVC_SAO_PIC_SIZE_LCU (0x3606) ++#define P_HEVC_SAO_PIC_SIZE_LCU (volatile unsigned int *)((0x3606 << 2) + 0xff620000) ++// [15:0] lcu_x_num_1[15:0] (=lcu_x_total-1) ++// [31:16] lcu_y_num_1[15:0] (=lcu_y_total-1) ++#define HEVC_SAO_TILE_START (0x3607) ++#define P_HEVC_SAO_TILE_START (volatile unsigned int *)((0x3607 << 2) + 0xff620000) ++// [15:0] tile_start_lcu_x[15:0] ++// [31:16] tile_start_lcu_y[15:0] ++#define HEVC_SAO_TILE_SIZE_LCU (0x3608) ++#define P_HEVC_SAO_TILE_SIZE_LCU (volatile unsigned int *)((0x3608 << 2) + 0xff620000) ++// [15:0] tile_width_lcu[15:0] ++// [31:16] tile_height_lcu[15:0] ++#define HEVC_SAO_AXI_WCTRL (0x3609) ++#define P_HEVC_SAO_AXI_WCTRL (volatile unsigned int *)((0x3609 << 2) + 0xff620000) ++#define HEVC_SAO_AXI_RCTRL (0x360a) ++#define P_HEVC_SAO_AXI_RCTRL (volatile unsigned int *)((0x360a << 2) + 0xff620000) ++#define HEVC_SAO_Y_START_ADDR (0x360b) ++#define P_HEVC_SAO_Y_START_ADDR (volatile unsigned int *)((0x360b << 2) + 0xff620000) ++#define HEVC_SAO_Y_LENGTH (0x360c) ++#define P_HEVC_SAO_Y_LENGTH (volatile unsigned int *)((0x360c << 2) + 0xff620000) ++#define HEVC_SAO_C_START_ADDR (0x360d) ++#define P_HEVC_SAO_C_START_ADDR (volatile unsigned int *)((0x360d << 2) + 0xff620000) ++#define HEVC_SAO_C_LENGTH (0x360e) ++#define P_HEVC_SAO_C_LENGTH (volatile unsigned int *)((0x360e << 2) + 0xff620000) ++#define HEVC_SAO_Y_WPTR (0x360f) ++#define P_HEVC_SAO_Y_WPTR (volatile unsigned int *)((0x360f << 2) + 0xff620000) ++#define HEVC_SAO_C_WPTR (0x3610) ++#define P_HEVC_SAO_C_WPTR (volatile unsigned int *)((0x3610 << 2) + 0xff620000) ++#define HEVC_SAO_ABV_START_ADDR (0x3611) ++#define P_HEVC_SAO_ABV_START_ADDR (volatile unsigned int *)((0x3611 << 2) + 0xff620000) ++#define HEVC_SAO_VB_WR_START_ADDR (0x3612) ++#define P_HEVC_SAO_VB_WR_START_ADDR (volatile unsigned int *)((0x3612 << 2) + 0xff620000) ++#define HEVC_SAO_VB_RD_START_ADDR (0x3613) ++#define P_HEVC_SAO_VB_RD_START_ADDR (volatile unsigned int *)((0x3613 << 2) + 0xff620000) ++#define HEVC_SAO_ABV_WPTR (0x3614) ++#define P_HEVC_SAO_ABV_WPTR (volatile unsigned int *)((0x3614 << 2) + 0xff620000) ++#define HEVC_SAO_ABV_RPTR (0x3615) ++#define P_HEVC_SAO_ABV_RPTR (volatile unsigned int *)((0x3615 << 2) + 0xff620000) ++#define HEVC_SAO_VB_WPTR (0x3616) ++#define P_HEVC_SAO_VB_WPTR (volatile unsigned int *)((0x3616 << 2) + 0xff620000) ++#define HEVC_SAO_VB_RPTR (0x3617) ++#define P_HEVC_SAO_VB_RPTR (volatile unsigned int *)((0x3617 << 2) + 0xff620000) ++#define HEVC_SAO_DBG_MODE0 (0x361e) ++#define P_HEVC_SAO_DBG_MODE0 (volatile unsigned int *)((0x361e << 2) + 0xff620000) ++#define HEVC_SAO_DBG_MODE1 (0x361f) ++#define P_HEVC_SAO_DBG_MODE1 (volatile unsigned int *)((0x361f << 2) + 0xff620000) ++#define HEVC_SAO_CTRL2 (0x3620) ++#define P_HEVC_SAO_CTRL2 (volatile unsigned int *)((0x3620 << 2) + 0xff620000) ++#define HEVC_SAO_CTRL3 (0x3621) ++#define P_HEVC_SAO_CTRL3 (volatile unsigned int *)((0x3621 << 2) + 0xff620000) ++#define HEVC_SAO_CTRL4 (0x3622) ++#define P_HEVC_SAO_CTRL4 (volatile unsigned int *)((0x3622 << 2) + 0xff620000) ++#define HEVC_SAO_CTRL5 (0x3623) ++#define P_HEVC_SAO_CTRL5 (volatile unsigned int *)((0x3623 << 2) + 0xff620000) ++//[23:22] dw_h1_ctrl default:2'b11 ++//[21:20] dw_h0_ctrl default:2'b11 ++//[19:18] dw_h1_ctrl default:2'b11 ++//[17:16] dw_h0_ctrl default:2'b11 ++#define HEVC_SAO_CTRL6 (0x3624) ++#define P_HEVC_SAO_CTRL6 (volatile unsigned int *)((0x3624 << 2) + 0xff620000) ++#define HEVC_SAO_CTRL7 (0x3625) ++#define P_HEVC_SAO_CTRL7 (volatile unsigned int *)((0x3625 << 2) + 0xff620000) ++#define HEVC_CM_BODY_START_ADDR (0x3626) ++#define P_HEVC_CM_BODY_START_ADDR (volatile unsigned int *)((0x3626 << 2) + 0xff620000) ++#define HEVC_CM_BODY_LENGTH (0x3627) ++#define P_HEVC_CM_BODY_LENGTH (volatile unsigned int *)((0x3627 << 2) + 0xff620000) ++#define HEVC_CM_HEADER_START_ADDR (0x3628) ++#define P_HEVC_CM_HEADER_START_ADDR (volatile unsigned int *)((0x3628 << 2) + 0xff620000) ++#define HEVC_CM_HEADER_LENGTH (0x3629) ++#define P_HEVC_CM_HEADER_LENGTH (volatile unsigned int *)((0x3629 << 2) + 0xff620000) ++#define HEVC_CM_COLOR (0x362a) ++#define P_HEVC_CM_COLOR (volatile unsigned int *)((0x362a << 2) + 0xff620000) ++#define HEVC_CM_HEADER_OFFSET (0x362b) ++#define P_HEVC_CM_HEADER_OFFSET (volatile unsigned int *)((0x362b << 2) + 0xff620000) ++#define HEVC_SAO_CTRL8 (0x362c) ++#define P_HEVC_SAO_CTRL8 (volatile unsigned int *)((0x362c << 2) + 0xff620000) ++#define HEVC_SAO_CTRL9 (0x362d) ++#define P_HEVC_SAO_CTRL9 (volatile unsigned int *)((0x362d << 2) + 0xff620000) ++#define HEVC_SAO_CTRL10 (0x362e) ++#define P_HEVC_SAO_CTRL10 (volatile unsigned int *)((0x362e << 2) + 0xff620000) ++#define HEVC_SAO_CTRL11 (0x362f) ++#define P_HEVC_SAO_CTRL11 (volatile unsigned int *)((0x362f << 2) + 0xff620000) ++#define HEVC_SAO_DBG_DATA_0 (0x3630) ++#define P_HEVC_SAO_DBG_DATA_0 (volatile unsigned int *)((0x3630 << 2) + 0xff620000) ++#define HEVC_SAO_DBG_DATA_1 (0x3631) ++#define P_HEVC_SAO_DBG_DATA_1 (volatile unsigned int *)((0x3631 << 2) + 0xff620000) ++#define HEVC_SAO_DBG_DATA_2 (0x3632) ++#define P_HEVC_SAO_DBG_DATA_2 (volatile unsigned int *)((0x3632 << 2) + 0xff620000) ++#define HEVC_SAO_DBG_DATA_3 (0x3633) ++#define P_HEVC_SAO_DBG_DATA_3 (volatile unsigned int *)((0x3633 << 2) + 0xff620000) ++#define HEVC_SAO_DBG_DATA_4 (0x3634) ++#define P_HEVC_SAO_DBG_DATA_4 (volatile unsigned int *)((0x3634 << 2) + 0xff620000) ++#define HEVC_SAO_DBG_DATA_5 (0x3635) ++#define P_HEVC_SAO_DBG_DATA_5 (volatile unsigned int *)((0x3635 << 2) + 0xff620000) ++#define HEVC_SAO_DBG_DATA_6 (0x3636) ++#define P_HEVC_SAO_DBG_DATA_6 (volatile unsigned int *)((0x3636 << 2) + 0xff620000) ++#define HEVC_SAO_DBG_DATA_7 (0x3637) ++#define P_HEVC_SAO_DBG_DATA_7 (volatile unsigned int *)((0x3637 << 2) + 0xff620000) ++#define HEVC_SAO_MMU_WR (0x3638) ++#define P_HEVC_SAO_MMU_WR (volatile unsigned int *)((0x3638 << 2) + 0xff620000) ++#define HEVC_SAO_MMU_STATUS (0x3639) ++#define P_HEVC_SAO_MMU_STATUS (volatile unsigned int *)((0x3639 << 2) + 0xff620000) ++//Read Only ++//sao_mmu_fifo is 16(depth)x20(bits) ++//[0] mmu_fifo_empty 1=empty,0=not-empty ++//[1] mmu_fifo_full 1=full,0=not-full ++//[7:4] mmu_fifo_depth[3:0] ++//[11:8] mmu_fifo_room[3:0] ++#define HEVC_SAO_MMU_VH0_ADDR (0x363a) ++#define P_HEVC_SAO_MMU_VH0_ADDR (volatile unsigned int *)((0x363a << 2) + 0xff620000) ++#define HEVC_SAO_MMU_VH1_ADDR (0x363b) ++#define P_HEVC_SAO_MMU_VH1_ADDR (volatile unsigned int *)((0x363b << 2) + 0xff620000) ++#define HEVC_SAO_MMU_WPTR (0x363c) ++#define P_HEVC_SAO_MMU_WPTR (volatile unsigned int *)((0x363c << 2) + 0xff620000) ++#define HEVC_SAO_MMU_RPTR (0x363d) ++#define P_HEVC_SAO_MMU_RPTR (volatile unsigned int *)((0x363d << 2) + 0xff620000) ++// ++// Closing file: hevc_sao_regs.h ++// ++//------------------------------------------------------------------------------ ++// HEVC_IQIT module level register offset ++//------------------------------------------------------------------------------ ++// ++// Reading file: hevc_iqit_regs.h ++// ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HEVC_IQIT_CBUS_BASE = 0x07 ++// ----------------------------------------------- ++// [ 2] RW en_freeclk. 0=Auto-gated clock for saving power; ++// 1=Free running clock if something wrong with auto-gating. ++// Default 0. ++// [ 1] RW enable_clk. 0=Disable clock; 1=Enable clock. Default 0. ++#define HEVC_IQIT_CLK_RST_CTRL (0x3700) ++#define P_HEVC_IQIT_CLK_RST_CTRL (volatile unsigned int *)((0x3700 << 2) + 0xff620000) ++// [ 5: 4] RW ctb_size. 0=8x8; 1=16x16; 2=32x32; 3=64x64. Default 0. ++// [ 3] RW itr_skip_mode. For dealing with discrepancy between Spec and C model for transform_skip. ++// 0=Follow Spec; 1=Follow C model. Default 0. ++// [ 2] RW scalelist_mode. Applicable only when scalelist_en=1. ++// 0=Use default scaling factor list; ++// 1=Use scaling factor list define in bit stream. ++// Default 0. ++// [ 1] RW scalelist_en. 0=Use flat scale; 1=Use scaling factor list. Default 0. ++// [ 0] RW diagscan_en. 0=Linear lookup dQ table; 1=Diagonally lookup dQ table. Default 0. ++#define HEVC_IQIT_DEQUANT_CTRL (0x3701) ++#define P_HEVC_IQIT_DEQUANT_CTRL (volatile unsigned int *)((0x3701 << 2) + 0xff620000) ++// [31:10] WR Reserved. Default 0. ++// [ 9: 0] WR scalelut_addr. Default 0. ++#define HEVC_IQIT_SCALELUT_WR_ADDR (0x3702) ++#define P_HEVC_IQIT_SCALELUT_WR_ADDR (volatile unsigned int *)((0x3702 << 2) + 0xff620000) ++// [31:10] RD Reserved. Default 0. ++// [ 9: 0] RD scalelut_addr. Default 0. ++#define HEVC_IQIT_SCALELUT_RD_ADDR (0x3703) ++#define P_HEVC_IQIT_SCALELUT_RD_ADDR (volatile unsigned int *)((0x3703 << 2) + 0xff620000) ++// [ 7: 0] RW LUT data. ++#define HEVC_IQIT_SCALELUT_DATA (0x3704) ++#define P_HEVC_IQIT_SCALELUT_DATA (volatile unsigned int *)((0x3704 << 2) + 0xff620000) ++//--------------------------------------------------- ++// tab_idx [2:0] - ++// 0-5 use custom table index ++// 6 - reserved ++// 7 - use default table ++//--------------------------------------------------- ++// [22:20] 4x4 tab 5 ++// [ 19] reserved ++// [18:16] 4x4 tab 4 ++// [ 15] reserved ++// [14:12] 4x4 tab 3 ++// [ 11] reserved ++// [10: 8] 4x4 tab 2 ++// [ 7] reserved ++// [ 6: 4] 4x4 tab 1 ++// [ 3] reserved ++// [ 2: 0] 4x4 tab 0 ++#define HEVC_IQIT_SCALELUT_IDX_4 (0x3705) ++#define P_HEVC_IQIT_SCALELUT_IDX_4 (volatile unsigned int *)((0x3705 << 2) + 0xff620000) ++// [22:20] 8x8 tab 5 ++// [ 19] reserved ++// [18:16] 8x8 tab 4 ++// [ 15] reserved ++// [14:12] 8x8 tab 3 ++// [ 11] reserved ++// [10: 8] 8x8 tab 2 ++// [ 7] reserved ++// [ 6: 4] 8x8 tab 1 ++// [ 3] reserved ++// [ 2: 0] 8x8 tab 0 ++#define HEVC_IQIT_SCALELUT_IDX_8 (0x3706) ++#define P_HEVC_IQIT_SCALELUT_IDX_8 (volatile unsigned int *)((0x3706 << 2) + 0xff620000) ++// [ 31] reserved ++// [30:28] 32x32 tab 1 ++// [ 27] reserved ++// [26:24] 32x32 tab 0 ++// [ 23] reserved ++// [22:20] 16x16 tab 5 ++// [ 19] reserved ++// [18:16] 16x16 tab 4 ++// [ 15] reserved ++// [14:12] 16x16 tab 3 ++// [ 11] reserved ++// [10: 8] 16x16 tab 2 ++// [ 7] reserved ++// [ 6: 4] 16x16 tab 1 ++// [ 3] reserved ++// [ 2: 0] 16x16 tab 0 ++#define HEVC_IQIT_SCALELUT_IDX_16_32 (0x3707) ++#define P_HEVC_IQIT_SCALELUT_IDX_16_32 (volatile unsigned int *)((0x3707 << 2) + 0xff620000) ++// [ 8: 2] R tuinfo_fifo_cnt. ++// [ 1] R fifo_has_room. ++// [ 0] R mem_init_done. ++#define HEVC_IQIT_STAT_GEN0 (0x3708) ++#define P_HEVC_IQIT_STAT_GEN0 (volatile unsigned int *)((0x3708 << 2) + 0xff620000) ++// [ 23] RW cntl_qp_cr_valid. ++// [21:16] RW cntl_qp_cr. ++// [ 15] RW cntl_qp_cb_valid. ++// [13: 8] RW cntl_qp_cb. ++// [ 7] RW cntl_qp_y_valid. ++// [ 5: 0] RW cntl_qp_y. ++#define HEVC_QP_WRITE (0x3709) ++#define P_HEVC_QP_WRITE (volatile unsigned int *)((0x3709 << 2) + 0xff620000) ++// [31:30] R ipp_size. ++// [28:24] R ipp_mem_ptr. ++// [23:22] R itr2_size. ++// [20:16] R itr2_mem_ptr. ++// [15:14] R itr1_size. ++// [12: 8] R itr1_mem_ptr. ++// [ 7: 6] R iq_size. ++// [ 4: 0] R iq_mem_ptr. ++#define HEVC_IQIT_STAT_GEN1 (0x370a) ++#define P_HEVC_IQIT_STAT_GEN1 (volatile unsigned int *)((0x370a << 2) + 0xff620000) ++// [ 5: 4] RW cntl_bitdepth_c. 0=8-bit; 1=9-bit; 2=10-bit. ++// [ 1: 0] RW cntl_bitdepth_y. 0=8-bit; 1=9-bit; 2=10-bit. ++#define HEVC_IQIT_BITDEPTH (0x370b) ++#define P_HEVC_IQIT_BITDEPTH (volatile unsigned int *)((0x370b << 2) + 0xff620000) ++// [ 10] R ipp_active. ++// [ 9] R itr2_active. ++// [ 8] R itr1_active. ++// [ 5: 0] R mem_spare_num. ++#define HEVC_IQIT_STAT_GEN2 (0x370c) ++#define P_HEVC_IQIT_STAT_GEN2 (volatile unsigned int *)((0x370c << 2) + 0xff620000) ++#define HEVC_IQIT_AVS2_WQP_0123 (0x370d) ++#define P_HEVC_IQIT_AVS2_WQP_0123 (volatile unsigned int *)((0x370d << 2) + 0xff620000) ++#define HEVC_IQIT_AVS2_WQP_45 (0x370e) ++#define P_HEVC_IQIT_AVS2_WQP_45 (volatile unsigned int *)((0x370e << 2) + 0xff620000) ++#define HEVC_IQIT_AVS2_QP_DELTA (0x370f) ++#define P_HEVC_IQIT_AVS2_QP_DELTA (volatile unsigned int *)((0x370f << 2) + 0xff620000) ++// ++// Closing file: hevc_iqit_regs.h ++// ++//------------------------------------------------------------------------------ ++// DOS top-level register offset ++//------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: DOS_TOP_CBUS_BASE = 0x3f ++// ----------------------------------------------- ++// [0] reserved ++// [1] Reset Dos top level registers, except sw_reset0/1/2 which is only reset by external reset_n. ++// [2] VDEC1 Reset assist, mdec's CBUS ++// [3] VDEC1 Reset mdec's VLD ++// [4] VDEC1 Reset mdec's VLD ++// [5] VDEC1 Reset mdec's VLD ++// [6] VDEC1 Reset mdec's IQIDCT ++// [7] VDEC1 Reset mdec's MC ++// [8] VDEC1 Reset mdec's DBLK ++// [9] VDEC1 Reset mdec's PIC_DC ++// [10] VDEC1 Reset mdec's Pscale ++// [11] VDEC1 Reset vcpu's MCPU ++// [12] VDEC1 Reset vcpu's CCPU ++// [13] VDEC1 Reset mmc_pre_arb ++#define DOS_SW_RESET0 (0x3f00) ++#define P_DOS_SW_RESET0 (volatile unsigned int *)((0x3f00 << 2) + 0xff620000) ++// [31:27] reserved ++// [26] hcodec clk_en for henc assist ++// [25:22] reserved ++// [21] hcodec clk_en for henc qdct ++// [20] hcodec clk_en for henc vlc ++// [19] hcodec clk_en for assist and cbus ++// [18] hcodec clk_en for ddr ++// [17] hcodec clk_en for vcpu ++// [16] hcodec clk_en for hdec assist ++// [15] hcodec clk_en for hdec dblk ++// [14] reserved ++// [13] hcodec clk_en for hdec mc ++// [12] hcodec clk_en for hdec pic_dc ++// [11:10] reserved ++// [9] vdec clk_en for vdec assist and cbus ++// [8] vdec clk_en for ddr ++// [7] vdec clk_en for vcpu ++// [6] vdec clk_en for mdec vld ++// [5] vdec clk_en for mdec psc ++// [4] vdec clk_en for mdec pic_dc ++// [3] vdec clk_en for mdec mc ++// [2] vdec clk_en for mdec iqidct ++// [1] vdec clk_en for mdec dblk ++// [0] vdec clk_en for mdec assist ++#define DOS_GCLK_EN0 (0x3f01) ++#define P_DOS_GCLK_EN0 (volatile unsigned int *)((0x3f01 << 2) + 0xff620000) ++#define DOS_GEN_CTRL0 (0x3f02) ++#define P_DOS_GEN_CTRL0 (volatile unsigned int *)((0x3f02 << 2) + 0xff620000) ++#define DOS_APB_ERR_CTRL (0x3f03) ++#define P_DOS_APB_ERR_CTRL (volatile unsigned int *)((0x3f03 << 2) + 0xff620000) ++#define DOS_APB_ERR_STAT (0x3f04) ++#define P_DOS_APB_ERR_STAT (volatile unsigned int *)((0x3f04 << 2) + 0xff620000) ++#define DOS_VDEC_INT_EN (0x3f05) ++#define P_DOS_VDEC_INT_EN (volatile unsigned int *)((0x3f05 << 2) + 0xff620000) ++#define DOS_HCODEC_INT_EN (0x3f06) ++#define P_DOS_HCODEC_INT_EN (volatile unsigned int *)((0x3f06 << 2) + 0xff620000) ++// [0] Reserved ++// [1] Reserved ++// [2] HCODEC Reset assist, hdec's CBUS ++// [3] HCODEC Reset hdec's VLD ++// [4] HCODEC Reset hdec's VLD ++// [5] HCODEC Reset hdec's VLD ++// [6] HCODEC Reset hdec's IQIDCT ++// [7] HCODEC Reset hdec's MC ++// [8] HCODEC Reset hdec's DBLK ++// [9] HCODEC Reset hdec's PIC_DC ++// [10] HCODEC Reset hdec's Pscale ++// [11] HCODEC Reset vcpu's MCPU ++// [12] HCODEC Reset vcpu's CCPU ++// [13] HCODEC Reset mmc_pre_arb ++// [14] HCODEC Reserved ++// [15] HCODEC Reserved ++// [16] HCODEC Reset henc's VLC ++#define DOS_SW_RESET1 (0x3f07) ++#define P_DOS_SW_RESET1 (volatile unsigned int *)((0x3f07 << 2) + 0xff620000) ++// [0] Reserved ++// [1] Reserved ++// [2] VDEC2 Reset assist, mdec's CBUS ++// [3] VDEC2 Reset mdec's VLD ++// [4] VDEC2 Reset mdec's VLD ++// [5] VDEC2 Reset mdec's VLD ++// [6] VDEC2 Reset mdec's IQIDCT ++// [7] VDEC2 Reset mdec's MC ++// [8] VDEC2 Reset mdec's DBLK ++// [9] VDEC2 Reset mdec's PIC_DC ++// [10] VDEC2 Reset mdec's Pscale ++// [11] VDEC2 Reset vcpu's MCPU ++// [12] VDEC2 Reset vcpu's CCPU ++// [13] VDEC2 Reset mmc_pre_arb ++#define DOS_SW_RESET2 (0x3f08) ++#define P_DOS_SW_RESET2 (volatile unsigned int *)((0x3f08 << 2) + 0xff620000) ++// [31:10] Reserved ++// [9] vdec2 clk_en for assist and cbus. ++// [8] vdec2 clk_en for ddr; ++// [7] vdec2 clk_en for vcpu; ++// [6] vdec2 clk_en for mdec vld ++// [5] vdec2 clk_en for mdec psc ++// [4] vdec2 clk_en for mdec pic_dc ++// [3] vdec2 clk_en for mdec mc ++// [2] vdec2 clk_en for mdec iqidct ++// [1] vdec2 clk_en for mdec dblk ++// [0] vdec2 clk_en for mdec assist ++#define DOS_GCLK_EN1 (0x3f09) ++#define P_DOS_GCLK_EN1 (volatile unsigned int *)((0x3f09 << 2) + 0xff620000) ++#define DOS_VDEC2_INT_EN (0x3f0a) ++#define P_DOS_VDEC2_INT_EN (volatile unsigned int *)((0x3f0a << 2) + 0xff620000) ++#define DOS_VDIN_LCNT (0x3f0b) ++#define P_DOS_VDIN_LCNT (volatile unsigned int *)((0x3f0b << 2) + 0xff620000) ++#define DOS_VDIN_FCNT (0x3f0c) ++#define P_DOS_VDIN_FCNT (volatile unsigned int *)((0x3f0c << 2) + 0xff620000) ++#define DOS_VDIN_CCTL (0x3f0d) ++#define P_DOS_VDIN_CCTL (volatile unsigned int *)((0x3f0d << 2) + 0xff620000) ++#define DOS_SCRATCH0 (0x3f10) ++#define P_DOS_SCRATCH0 (volatile unsigned int *)((0x3f10 << 2) + 0xff620000) ++#define DOS_SCRATCH1 (0x3f11) ++#define P_DOS_SCRATCH1 (volatile unsigned int *)((0x3f11 << 2) + 0xff620000) ++#define DOS_SCRATCH2 (0x3f12) ++#define P_DOS_SCRATCH2 (volatile unsigned int *)((0x3f12 << 2) + 0xff620000) ++#define DOS_SCRATCH3 (0x3f13) ++#define P_DOS_SCRATCH3 (volatile unsigned int *)((0x3f13 << 2) + 0xff620000) ++#define DOS_SCRATCH4 (0x3f14) ++#define P_DOS_SCRATCH4 (volatile unsigned int *)((0x3f14 << 2) + 0xff620000) ++#define DOS_SCRATCH5 (0x3f15) ++#define P_DOS_SCRATCH5 (volatile unsigned int *)((0x3f15 << 2) + 0xff620000) ++#define DOS_SCRATCH6 (0x3f16) ++#define P_DOS_SCRATCH6 (volatile unsigned int *)((0x3f16 << 2) + 0xff620000) ++#define DOS_SCRATCH7 (0x3f17) ++#define P_DOS_SCRATCH7 (volatile unsigned int *)((0x3f17 << 2) + 0xff620000) ++#define DOS_SCRATCH8 (0x3f18) ++#define P_DOS_SCRATCH8 (volatile unsigned int *)((0x3f18 << 2) + 0xff620000) ++#define DOS_SCRATCH9 (0x3f19) ++#define P_DOS_SCRATCH9 (volatile unsigned int *)((0x3f19 << 2) + 0xff620000) ++#define DOS_SCRATCH10 (0x3f1a) ++#define P_DOS_SCRATCH10 (volatile unsigned int *)((0x3f1a << 2) + 0xff620000) ++#define DOS_SCRATCH11 (0x3f1b) ++#define P_DOS_SCRATCH11 (volatile unsigned int *)((0x3f1b << 2) + 0xff620000) ++#define DOS_SCRATCH12 (0x3f1c) ++#define P_DOS_SCRATCH12 (volatile unsigned int *)((0x3f1c << 2) + 0xff620000) ++#define DOS_SCRATCH13 (0x3f1d) ++#define P_DOS_SCRATCH13 (volatile unsigned int *)((0x3f1d << 2) + 0xff620000) ++#define DOS_SCRATCH14 (0x3f1e) ++#define P_DOS_SCRATCH14 (volatile unsigned int *)((0x3f1e << 2) + 0xff620000) ++#define DOS_SCRATCH15 (0x3f1f) ++#define P_DOS_SCRATCH15 (volatile unsigned int *)((0x3f1f << 2) + 0xff620000) ++#define DOS_SCRATCH16 (0x3f20) ++#define P_DOS_SCRATCH16 (volatile unsigned int *)((0x3f20 << 2) + 0xff620000) ++#define DOS_SCRATCH17 (0x3f21) ++#define P_DOS_SCRATCH17 (volatile unsigned int *)((0x3f21 << 2) + 0xff620000) ++#define DOS_SCRATCH18 (0x3f22) ++#define P_DOS_SCRATCH18 (volatile unsigned int *)((0x3f22 << 2) + 0xff620000) ++#define DOS_SCRATCH19 (0x3f23) ++#define P_DOS_SCRATCH19 (volatile unsigned int *)((0x3f23 << 2) + 0xff620000) ++#define DOS_SCRATCH20 (0x3f24) ++#define P_DOS_SCRATCH20 (volatile unsigned int *)((0x3f24 << 2) + 0xff620000) ++#define DOS_SCRATCH21 (0x3f25) ++#define P_DOS_SCRATCH21 (volatile unsigned int *)((0x3f25 << 2) + 0xff620000) ++#define DOS_SCRATCH22 (0x3f26) ++#define P_DOS_SCRATCH22 (volatile unsigned int *)((0x3f26 << 2) + 0xff620000) ++#define DOS_SCRATCH23 (0x3f27) ++#define P_DOS_SCRATCH23 (volatile unsigned int *)((0x3f27 << 2) + 0xff620000) ++#define DOS_SCRATCH24 (0x3f28) ++#define P_DOS_SCRATCH24 (volatile unsigned int *)((0x3f28 << 2) + 0xff620000) ++#define DOS_SCRATCH25 (0x3f29) ++#define P_DOS_SCRATCH25 (volatile unsigned int *)((0x3f29 << 2) + 0xff620000) ++#define DOS_SCRATCH26 (0x3f2a) ++#define P_DOS_SCRATCH26 (volatile unsigned int *)((0x3f2a << 2) + 0xff620000) ++#define DOS_SCRATCH27 (0x3f2b) ++#define P_DOS_SCRATCH27 (volatile unsigned int *)((0x3f2b << 2) + 0xff620000) ++#define DOS_SCRATCH28 (0x3f2c) ++#define P_DOS_SCRATCH28 (volatile unsigned int *)((0x3f2c << 2) + 0xff620000) ++#define DOS_SCRATCH29 (0x3f2d) ++#define P_DOS_SCRATCH29 (volatile unsigned int *)((0x3f2d << 2) + 0xff620000) ++#define DOS_SCRATCH30 (0x3f2e) ++#define P_DOS_SCRATCH30 (volatile unsigned int *)((0x3f2e << 2) + 0xff620000) ++#define DOS_SCRATCH31 (0x3f2f) ++#define P_DOS_SCRATCH31 (volatile unsigned int *)((0x3f2f << 2) + 0xff620000) ++#define DOS_MEM_PD_VDEC (0x3f30) ++#define P_DOS_MEM_PD_VDEC (volatile unsigned int *)((0x3f30 << 2) + 0xff620000) ++#define DOS_MEM_PD_VDEC2 (0x3f31) ++#define P_DOS_MEM_PD_VDEC2 (volatile unsigned int *)((0x3f31 << 2) + 0xff620000) ++#define DOS_MEM_PD_HCODEC (0x3f32) ++#define P_DOS_MEM_PD_HCODEC (volatile unsigned int *)((0x3f32 << 2) + 0xff620000) ++#define DOS_MEM_PD_HEVC (0x3f33) ++#define P_DOS_MEM_PD_HEVC (volatile unsigned int *)((0x3f33 << 2) + 0xff620000) ++#define DOS_SW_RESET3 (0x3f34) ++#define P_DOS_SW_RESET3 (volatile unsigned int *)((0x3f34 << 2) + 0xff620000) ++#define DOS_GCLK_EN3 (0x3f35) ++#define P_DOS_GCLK_EN3 (volatile unsigned int *)((0x3f35 << 2) + 0xff620000) ++#define DOS_HEVC_INT_EN (0x3f36) ++#define P_DOS_HEVC_INT_EN (volatile unsigned int *)((0x3f36 << 2) + 0xff620000) ++#define DOS_SW_RESET4 (0x3f37) ++#define P_DOS_SW_RESET4 (volatile unsigned int *)((0x3f37 << 2) + 0xff620000) ++#define DOS_GCLK_EN4 (0x3f38) ++#define P_DOS_GCLK_EN4 (volatile unsigned int *)((0x3f38 << 2) + 0xff620000) ++#define DOS_MEM_PD_VP9DEC (0x3f39) ++#define P_DOS_MEM_PD_VP9DEC (volatile unsigned int *)((0x3f39 << 2) + 0xff620000) ++// bit[31] mcrcc_stall_en ++// bit[30:28] Reserved ++// bit[27:20] target_canvas ++// bit[19:10] target_mby ++// bit[ 9: 0] target_mbx ++#define DOS_VDEC_MCRCC_STALL_CTRL (0x3f40) ++#define P_DOS_VDEC_MCRCC_STALL_CTRL (volatile unsigned int *)((0x3f40 << 2) + 0xff620000) ++#define DOS_VDEC_MCRCC_STALL2_CTRL (0x3f42) ++#define P_DOS_VDEC_MCRCC_STALL2_CTRL (volatile unsigned int *)((0x3f42 << 2) + 0xff620000) ++#define DOS_VDEC2_MCRCC_STALL_CTRL (0x3f41) ++#define P_DOS_VDEC2_MCRCC_STALL_CTRL (volatile unsigned int *)((0x3f41 << 2) + 0xff620000) ++#define DOS_VDEC2_MCRCC_STALL2_CTRL (0x3f43) ++#define P_DOS_VDEC2_MCRCC_STALL2_CTRL (volatile unsigned int *)((0x3f43 << 2) + 0xff620000) ++// bit[1] s_clk off ++// bit[0] m_clk off ++#define DOS_CFG_CMPIF_BRIDGE (0x3f44) ++#define P_DOS_CFG_CMPIF_BRIDGE (volatile unsigned int *)((0x3f44 << 2) + 0xff620000) ++#define DOS_SECURE_CTL_INDEX (0x3f80) ++#define P_DOS_SECURE_CTL_INDEX (volatile unsigned int *)((0x3f80 << 2) + 0xff620000) ++#define DOS_SECURE_CTL_DATA (0x3f81) ++#define P_DOS_SECURE_CTL_DATA (volatile unsigned int *)((0x3f81 << 2) + 0xff620000) ++#define DOS_SECURE_REG_NULL (0x3f82) ++#define P_DOS_SECURE_REG_NULL (volatile unsigned int *)((0x3f82 << 2) + 0xff620000) ++// ++// Closing file: ./dos_param.h ++// ++// ++// Reading file: mdec_regs.h ++// ++//======================================================================== ++// MDEC module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_VDEC_MDEC_CBUS_BASE = 0x09 ++// ----------------------------------------------- ++#define HCODEC_MC_CTRL_REG (0x1900) ++#define P_HCODEC_MC_CTRL_REG (volatile unsigned int *)((0x1900 << 2) + 0xff620000) ++#define HCODEC_MC_MB_INFO (0x1901) ++#define P_HCODEC_MC_MB_INFO (volatile unsigned int *)((0x1901 << 2) + 0xff620000) ++#define HCODEC_MC_PIC_INFO (0x1902) ++#define P_HCODEC_MC_PIC_INFO (volatile unsigned int *)((0x1902 << 2) + 0xff620000) ++#define HCODEC_MC_HALF_PEL_ONE (0x1903) ++#define P_HCODEC_MC_HALF_PEL_ONE (volatile unsigned int *)((0x1903 << 2) + 0xff620000) ++#define HCODEC_MC_HALF_PEL_TWO (0x1904) ++#define P_HCODEC_MC_HALF_PEL_TWO (volatile unsigned int *)((0x1904 << 2) + 0xff620000) ++#define HCODEC_POWER_CTL_MC (0x1905) ++#define P_HCODEC_POWER_CTL_MC (volatile unsigned int *)((0x1905 << 2) + 0xff620000) ++#define HCODEC_MC_CMD (0x1906) ++#define P_HCODEC_MC_CMD (volatile unsigned int *)((0x1906 << 2) + 0xff620000) ++#define HCODEC_MC_CTRL0 (0x1907) ++#define P_HCODEC_MC_CTRL0 (volatile unsigned int *)((0x1907 << 2) + 0xff620000) ++#define HCODEC_MC_PIC_W_H (0x1908) ++#define P_HCODEC_MC_PIC_W_H (volatile unsigned int *)((0x1908 << 2) + 0xff620000) ++#define HCODEC_MC_STATUS0 (0x1909) ++#define P_HCODEC_MC_STATUS0 (volatile unsigned int *)((0x1909 << 2) + 0xff620000) ++#define HCODEC_MC_STATUS1 (0x190a) ++#define P_HCODEC_MC_STATUS1 (volatile unsigned int *)((0x190a << 2) + 0xff620000) ++#define HCODEC_MC_CTRL1 (0x190b) ++#define P_HCODEC_MC_CTRL1 (volatile unsigned int *)((0x190b << 2) + 0xff620000) ++#define HCODEC_MC_MIX_RATIO0 (0x190c) ++#define P_HCODEC_MC_MIX_RATIO0 (volatile unsigned int *)((0x190c << 2) + 0xff620000) ++#define HCODEC_MC_MIX_RATIO1 (0x190d) ++#define P_HCODEC_MC_MIX_RATIO1 (volatile unsigned int *)((0x190d << 2) + 0xff620000) ++#define HCODEC_MC_DP_MB_XY (0x190e) ++#define P_HCODEC_MC_DP_MB_XY (volatile unsigned int *)((0x190e << 2) + 0xff620000) ++#define HCODEC_MC_OM_MB_XY (0x190f) ++#define P_HCODEC_MC_OM_MB_XY (volatile unsigned int *)((0x190f << 2) + 0xff620000) ++#define HCODEC_PSCALE_RST (0x1910) ++#define P_HCODEC_PSCALE_RST (volatile unsigned int *)((0x1910 << 2) + 0xff620000) ++#define HCODEC_PSCALE_CTRL (0x1911) ++#define P_HCODEC_PSCALE_CTRL (volatile unsigned int *)((0x1911 << 2) + 0xff620000) ++#define HCODEC_PSCALE_PICI_W (0x1912) ++#define P_HCODEC_PSCALE_PICI_W (volatile unsigned int *)((0x1912 << 2) + 0xff620000) ++#define HCODEC_PSCALE_PICI_H (0x1913) ++#define P_HCODEC_PSCALE_PICI_H (volatile unsigned int *)((0x1913 << 2) + 0xff620000) ++#define HCODEC_PSCALE_PICO_W (0x1914) ++#define P_HCODEC_PSCALE_PICO_W (volatile unsigned int *)((0x1914 << 2) + 0xff620000) ++#define HCODEC_PSCALE_PICO_H (0x1915) ++#define P_HCODEC_PSCALE_PICO_H (volatile unsigned int *)((0x1915 << 2) + 0xff620000) ++#define HCODEC_PSCALE_PICO_START_X (0x1916) ++#define P_HCODEC_PSCALE_PICO_START_X (volatile unsigned int *)((0x1916 << 2) + 0xff620000) ++#define HCODEC_PSCALE_PICO_START_Y (0x1917) ++#define P_HCODEC_PSCALE_PICO_START_Y (volatile unsigned int *)((0x1917 << 2) + 0xff620000) ++#define HCODEC_PSCALE_DUMMY (0x1918) ++#define P_HCODEC_PSCALE_DUMMY (volatile unsigned int *)((0x1918 << 2) + 0xff620000) ++#define HCODEC_PSCALE_FILT0_COEF0 (0x1919) ++#define P_HCODEC_PSCALE_FILT0_COEF0 (volatile unsigned int *)((0x1919 << 2) + 0xff620000) ++#define HCODEC_PSCALE_FILT0_COEF1 (0x191a) ++#define P_HCODEC_PSCALE_FILT0_COEF1 (volatile unsigned int *)((0x191a << 2) + 0xff620000) ++#define HCODEC_PSCALE_CMD_CTRL (0x191b) ++#define P_HCODEC_PSCALE_CMD_CTRL (volatile unsigned int *)((0x191b << 2) + 0xff620000) ++#define HCODEC_PSCALE_CMD_BLK_X (0x191c) ++#define P_HCODEC_PSCALE_CMD_BLK_X (volatile unsigned int *)((0x191c << 2) + 0xff620000) ++#define HCODEC_PSCALE_CMD_BLK_Y (0x191d) ++#define P_HCODEC_PSCALE_CMD_BLK_Y (volatile unsigned int *)((0x191d << 2) + 0xff620000) ++#define HCODEC_PSCALE_STATUS (0x191e) ++#define P_HCODEC_PSCALE_STATUS (volatile unsigned int *)((0x191e << 2) + 0xff620000) ++#define HCODEC_PSCALE_BMEM_ADDR (0x191f) ++#define P_HCODEC_PSCALE_BMEM_ADDR (volatile unsigned int *)((0x191f << 2) + 0xff620000) ++#define HCODEC_PSCALE_BMEM_DAT (0x1920) ++#define P_HCODEC_PSCALE_BMEM_DAT (volatile unsigned int *)((0x1920 << 2) + 0xff620000) ++#define HCODEC_PSCALE_DRAM_BUF_CTRL (0x1921) ++#define P_HCODEC_PSCALE_DRAM_BUF_CTRL (volatile unsigned int *)((0x1921 << 2) + 0xff620000) ++#define HCODEC_PSCALE_MCMD_CTRL (0x1922) ++#define P_HCODEC_PSCALE_MCMD_CTRL (volatile unsigned int *)((0x1922 << 2) + 0xff620000) ++#define HCODEC_PSCALE_MCMD_XSIZE (0x1923) ++#define P_HCODEC_PSCALE_MCMD_XSIZE (volatile unsigned int *)((0x1923 << 2) + 0xff620000) ++#define HCODEC_PSCALE_MCMD_YSIZE (0x1924) ++#define P_HCODEC_PSCALE_MCMD_YSIZE (volatile unsigned int *)((0x1924 << 2) + 0xff620000) ++#define HCODEC_PSCALE_RBUF_START_BLKX (0x1925) ++#define P_HCODEC_PSCALE_RBUF_START_BLKX (volatile unsigned int *)((0x1925 << 2) + 0xff620000) ++#define HCODEC_PSCALE_RBUF_START_BLKY (0x1926) ++#define P_HCODEC_PSCALE_RBUF_START_BLKY (volatile unsigned int *)((0x1926 << 2) + 0xff620000) ++//`define PSCALE_RBUF_MB_WIDTH 8'h27 ++#define HCODEC_PSCALE_PICO_SHIFT_XY (0x1928) ++#define P_HCODEC_PSCALE_PICO_SHIFT_XY (volatile unsigned int *)((0x1928 << 2) + 0xff620000) ++#define HCODEC_PSCALE_CTRL1 (0x1929) ++#define P_HCODEC_PSCALE_CTRL1 (volatile unsigned int *)((0x1929 << 2) + 0xff620000) ++//Bit 15, wmask enable ++//Bit 14:13, filt0 srckey_less, ++//Bit 12:11, filt1 srckey_less, in the case of the interpolated data is equal distance to ++//key data and normal data, 00: select normal data, 01: select right data, 10: select key data ++//Bit 10:9, srckey mode, 00: equal, 01: less than or equal, 10: great than or equal ++//Bit 8, src key enable ++//Bit 7:0, y src key ++#define HCODEC_PSCALE_SRCKEY_CTRL0 (0x192a) ++#define P_HCODEC_PSCALE_SRCKEY_CTRL0 (volatile unsigned int *)((0x192a << 2) + 0xff620000) ++//Bit 15:8, cb src key ++//Bit 7:0, cr src key ++#define HCODEC_PSCALE_SRCKEY_CTRL1 (0x192b) ++#define P_HCODEC_PSCALE_SRCKEY_CTRL1 (volatile unsigned int *)((0x192b << 2) + 0xff620000) ++//Bit 22:16 canvas_rd_addr2 ++//Bit 14:8 canvas_rd_addr1 ++//Bit 6:0 canvas_rd_addr1 ++#define HCODEC_PSCALE_CANVAS_RD_ADDR (0x192c) ++#define P_HCODEC_PSCALE_CANVAS_RD_ADDR (volatile unsigned int *)((0x192c << 2) + 0xff620000) ++//Bit 22:16 canvas_wr_addr2 ++//Bit 14:8 canvas_wr_addr1 ++//Bit 6:0 canvas_wr_addr1 ++#define HCODEC_PSCALE_CANVAS_WR_ADDR (0x192d) ++#define P_HCODEC_PSCALE_CANVAS_WR_ADDR (volatile unsigned int *)((0x192d << 2) + 0xff620000) ++//bit 13:8 pscale thread ID and token ++//bit 7 disable write response count adding to busy bit ++//bit 5:0 pscale prearbitor burst num ++#define HCODEC_PSCALE_CTRL2 (0x192e) ++#define P_HCODEC_PSCALE_CTRL2 (volatile unsigned int *)((0x192e << 2) + 0xff620000) ++// 31 - use_omem_mb_xy_auto ++//23:16 - omem_max_mb_x ++//15:8 - omem_mb_y_auto ++// 7:0 - omem_mb_x_auto ++#define HCODEC_HDEC_MC_OMEM_AUTO (0x1930) ++#define P_HCODEC_HDEC_MC_OMEM_AUTO (volatile unsigned int *)((0x1930 << 2) + 0xff620000) ++#define HCODEC_HDEC_MC_MBRIGHT_IDX (0x1931) ++#define P_HCODEC_HDEC_MC_MBRIGHT_IDX (volatile unsigned int *)((0x1931 << 2) + 0xff620000) ++#define HCODEC_HDEC_MC_MBRIGHT_RD (0x1932) ++#define P_HCODEC_HDEC_MC_MBRIGHT_RD (volatile unsigned int *)((0x1932 << 2) + 0xff620000) ++#define HCODEC_MC_MPORT_CTRL (0x1940) ++#define P_HCODEC_MC_MPORT_CTRL (volatile unsigned int *)((0x1940 << 2) + 0xff620000) ++#define HCODEC_MC_MPORT_DAT (0x1941) ++#define P_HCODEC_MC_MPORT_DAT (volatile unsigned int *)((0x1941 << 2) + 0xff620000) ++#define HCODEC_MC_WT_PRED_CTRL (0x1942) ++#define P_HCODEC_MC_WT_PRED_CTRL (volatile unsigned int *)((0x1942 << 2) + 0xff620000) ++#define HCODEC_MC_MBBOT_ST_EVEN_ADDR (0x1944) ++#define P_HCODEC_MC_MBBOT_ST_EVEN_ADDR (volatile unsigned int *)((0x1944 << 2) + 0xff620000) ++#define HCODEC_MC_MBBOT_ST_ODD_ADDR (0x1945) ++#define P_HCODEC_MC_MBBOT_ST_ODD_ADDR (volatile unsigned int *)((0x1945 << 2) + 0xff620000) ++#define HCODEC_MC_DPDN_MB_XY (0x1946) ++#define P_HCODEC_MC_DPDN_MB_XY (volatile unsigned int *)((0x1946 << 2) + 0xff620000) ++#define HCODEC_MC_OMDN_MB_XY (0x1947) ++#define P_HCODEC_MC_OMDN_MB_XY (volatile unsigned int *)((0x1947 << 2) + 0xff620000) ++#define HCODEC_MC_HCMDBUF_H (0x1948) ++#define P_HCODEC_MC_HCMDBUF_H (volatile unsigned int *)((0x1948 << 2) + 0xff620000) ++#define HCODEC_MC_HCMDBUF_L (0x1949) ++#define P_HCODEC_MC_HCMDBUF_L (volatile unsigned int *)((0x1949 << 2) + 0xff620000) ++#define HCODEC_MC_HCMD_H (0x194a) ++#define P_HCODEC_MC_HCMD_H (volatile unsigned int *)((0x194a << 2) + 0xff620000) ++#define HCODEC_MC_HCMD_L (0x194b) ++#define P_HCODEC_MC_HCMD_L (volatile unsigned int *)((0x194b << 2) + 0xff620000) ++#define HCODEC_MC_IDCT_DAT (0x194c) ++#define P_HCODEC_MC_IDCT_DAT (volatile unsigned int *)((0x194c << 2) + 0xff620000) ++#define HCODEC_MC_CTRL_GCLK_CTRL (0x194d) ++#define P_HCODEC_MC_CTRL_GCLK_CTRL (volatile unsigned int *)((0x194d << 2) + 0xff620000) ++#define HCODEC_MC_OTHER_GCLK_CTRL (0x194e) ++#define P_HCODEC_MC_OTHER_GCLK_CTRL (volatile unsigned int *)((0x194e << 2) + 0xff620000) ++//Bit 29:24, mbbot thread ID and token ++//Bit 21:16, mc read/write thread ID and token ++//Bit 13:8, mbbot pre-arbitor burst number ++//Bit 5:0, mc pre-arbitor burst number ++#define HCODEC_MC_CTRL2 (0x194f) ++#define P_HCODEC_MC_CTRL2 (volatile unsigned int *)((0x194f << 2) + 0xff620000) ++// `define DBLK_QUANT 8'h76 // ONLY for $ucode/real/amrisc/rv.s, reg value from apollo ++//`define ANC1_CANVAS_ADDR 8'h80 ++//`define ANC2_CANVAS_ADDR 8'h81 ++//`define REC_CANVAS_ADDR 8'h89 ++//`define MDEC_PIC_W 8'h8c ++//`define MDEC_PIC_H 8'h8d ++// mdec_pic_dc_mux_ctrl[31] -- mcr_hevc_mode ++#define HCODEC_MDEC_PIC_DC_MUX_CTRL (0x198d) ++#define P_HCODEC_MDEC_PIC_DC_MUX_CTRL (volatile unsigned int *)((0x198d << 2) + 0xff620000) ++#define HCODEC_MDEC_PIC_DC_CTRL (0x198e) ++#define P_HCODEC_MDEC_PIC_DC_CTRL (volatile unsigned int *)((0x198e << 2) + 0xff620000) ++#define HCODEC_MDEC_PIC_DC_STATUS (0x198f) ++#define P_HCODEC_MDEC_PIC_DC_STATUS (volatile unsigned int *)((0x198f << 2) + 0xff620000) ++#define HCODEC_ANC0_CANVAS_ADDR (0x1990) ++#define P_HCODEC_ANC0_CANVAS_ADDR (volatile unsigned int *)((0x1990 << 2) + 0xff620000) ++#define HCODEC_ANC1_CANVAS_ADDR (0x1991) ++#define P_HCODEC_ANC1_CANVAS_ADDR (volatile unsigned int *)((0x1991 << 2) + 0xff620000) ++#define HCODEC_ANC2_CANVAS_ADDR (0x1992) ++#define P_HCODEC_ANC2_CANVAS_ADDR (volatile unsigned int *)((0x1992 << 2) + 0xff620000) ++#define HCODEC_ANC3_CANVAS_ADDR (0x1993) ++#define P_HCODEC_ANC3_CANVAS_ADDR (volatile unsigned int *)((0x1993 << 2) + 0xff620000) ++#define HCODEC_ANC4_CANVAS_ADDR (0x1994) ++#define P_HCODEC_ANC4_CANVAS_ADDR (volatile unsigned int *)((0x1994 << 2) + 0xff620000) ++#define HCODEC_ANC5_CANVAS_ADDR (0x1995) ++#define P_HCODEC_ANC5_CANVAS_ADDR (volatile unsigned int *)((0x1995 << 2) + 0xff620000) ++#define HCODEC_ANC6_CANVAS_ADDR (0x1996) ++#define P_HCODEC_ANC6_CANVAS_ADDR (volatile unsigned int *)((0x1996 << 2) + 0xff620000) ++#define HCODEC_ANC7_CANVAS_ADDR (0x1997) ++#define P_HCODEC_ANC7_CANVAS_ADDR (volatile unsigned int *)((0x1997 << 2) + 0xff620000) ++#define HCODEC_ANC8_CANVAS_ADDR (0x1998) ++#define P_HCODEC_ANC8_CANVAS_ADDR (volatile unsigned int *)((0x1998 << 2) + 0xff620000) ++#define HCODEC_ANC9_CANVAS_ADDR (0x1999) ++#define P_HCODEC_ANC9_CANVAS_ADDR (volatile unsigned int *)((0x1999 << 2) + 0xff620000) ++#define HCODEC_ANC10_CANVAS_ADDR (0x199a) ++#define P_HCODEC_ANC10_CANVAS_ADDR (volatile unsigned int *)((0x199a << 2) + 0xff620000) ++#define HCODEC_ANC11_CANVAS_ADDR (0x199b) ++#define P_HCODEC_ANC11_CANVAS_ADDR (volatile unsigned int *)((0x199b << 2) + 0xff620000) ++#define HCODEC_ANC12_CANVAS_ADDR (0x199c) ++#define P_HCODEC_ANC12_CANVAS_ADDR (volatile unsigned int *)((0x199c << 2) + 0xff620000) ++#define HCODEC_ANC13_CANVAS_ADDR (0x199d) ++#define P_HCODEC_ANC13_CANVAS_ADDR (volatile unsigned int *)((0x199d << 2) + 0xff620000) ++#define HCODEC_ANC14_CANVAS_ADDR (0x199e) ++#define P_HCODEC_ANC14_CANVAS_ADDR (volatile unsigned int *)((0x199e << 2) + 0xff620000) ++#define HCODEC_ANC15_CANVAS_ADDR (0x199f) ++#define P_HCODEC_ANC15_CANVAS_ADDR (volatile unsigned int *)((0x199f << 2) + 0xff620000) ++#define HCODEC_ANC16_CANVAS_ADDR (0x19a0) ++#define P_HCODEC_ANC16_CANVAS_ADDR (volatile unsigned int *)((0x19a0 << 2) + 0xff620000) ++#define HCODEC_ANC17_CANVAS_ADDR (0x19a1) ++#define P_HCODEC_ANC17_CANVAS_ADDR (volatile unsigned int *)((0x19a1 << 2) + 0xff620000) ++#define HCODEC_ANC18_CANVAS_ADDR (0x19a2) ++#define P_HCODEC_ANC18_CANVAS_ADDR (volatile unsigned int *)((0x19a2 << 2) + 0xff620000) ++#define HCODEC_ANC19_CANVAS_ADDR (0x19a3) ++#define P_HCODEC_ANC19_CANVAS_ADDR (volatile unsigned int *)((0x19a3 << 2) + 0xff620000) ++#define HCODEC_ANC20_CANVAS_ADDR (0x19a4) ++#define P_HCODEC_ANC20_CANVAS_ADDR (volatile unsigned int *)((0x19a4 << 2) + 0xff620000) ++#define HCODEC_ANC21_CANVAS_ADDR (0x19a5) ++#define P_HCODEC_ANC21_CANVAS_ADDR (volatile unsigned int *)((0x19a5 << 2) + 0xff620000) ++#define HCODEC_ANC22_CANVAS_ADDR (0x19a6) ++#define P_HCODEC_ANC22_CANVAS_ADDR (volatile unsigned int *)((0x19a6 << 2) + 0xff620000) ++#define HCODEC_ANC23_CANVAS_ADDR (0x19a7) ++#define P_HCODEC_ANC23_CANVAS_ADDR (volatile unsigned int *)((0x19a7 << 2) + 0xff620000) ++#define HCODEC_ANC24_CANVAS_ADDR (0x19a8) ++#define P_HCODEC_ANC24_CANVAS_ADDR (volatile unsigned int *)((0x19a8 << 2) + 0xff620000) ++#define HCODEC_ANC25_CANVAS_ADDR (0x19a9) ++#define P_HCODEC_ANC25_CANVAS_ADDR (volatile unsigned int *)((0x19a9 << 2) + 0xff620000) ++#define HCODEC_ANC26_CANVAS_ADDR (0x19aa) ++#define P_HCODEC_ANC26_CANVAS_ADDR (volatile unsigned int *)((0x19aa << 2) + 0xff620000) ++#define HCODEC_ANC27_CANVAS_ADDR (0x19ab) ++#define P_HCODEC_ANC27_CANVAS_ADDR (volatile unsigned int *)((0x19ab << 2) + 0xff620000) ++#define HCODEC_ANC28_CANVAS_ADDR (0x19ac) ++#define P_HCODEC_ANC28_CANVAS_ADDR (volatile unsigned int *)((0x19ac << 2) + 0xff620000) ++#define HCODEC_ANC29_CANVAS_ADDR (0x19ad) ++#define P_HCODEC_ANC29_CANVAS_ADDR (volatile unsigned int *)((0x19ad << 2) + 0xff620000) ++#define HCODEC_ANC30_CANVAS_ADDR (0x19ae) ++#define P_HCODEC_ANC30_CANVAS_ADDR (volatile unsigned int *)((0x19ae << 2) + 0xff620000) ++#define HCODEC_ANC31_CANVAS_ADDR (0x19af) ++#define P_HCODEC_ANC31_CANVAS_ADDR (volatile unsigned int *)((0x19af << 2) + 0xff620000) ++#define HCODEC_DBKR_CANVAS_ADDR (0x19b0) ++#define P_HCODEC_DBKR_CANVAS_ADDR (volatile unsigned int *)((0x19b0 << 2) + 0xff620000) ++#define HCODEC_DBKW_CANVAS_ADDR (0x19b1) ++#define P_HCODEC_DBKW_CANVAS_ADDR (volatile unsigned int *)((0x19b1 << 2) + 0xff620000) ++#define HCODEC_REC_CANVAS_ADDR (0x19b2) ++#define P_HCODEC_REC_CANVAS_ADDR (volatile unsigned int *)((0x19b2 << 2) + 0xff620000) ++//28:24, read/write, current canvas idx, used in h264 only now ++//23:0, read only, current canvas address, 23:16, Cr canvas addr, 15:8, Cb canvas addr, 7:0, Y canvas addr ++#define HCODEC_CURR_CANVAS_CTRL (0x19b3) ++#define P_HCODEC_CURR_CANVAS_CTRL (volatile unsigned int *)((0x19b3 << 2) + 0xff620000) ++#define HCODEC_MDEC_PIC_DC_THRESH (0x19b8) ++#define P_HCODEC_MDEC_PIC_DC_THRESH (volatile unsigned int *)((0x19b8 << 2) + 0xff620000) ++#define HCODEC_MDEC_PICR_BUF_STATUS (0x19b9) ++#define P_HCODEC_MDEC_PICR_BUF_STATUS (volatile unsigned int *)((0x19b9 << 2) + 0xff620000) ++#define HCODEC_MDEC_PICW_BUF_STATUS (0x19ba) ++#define P_HCODEC_MDEC_PICW_BUF_STATUS (volatile unsigned int *)((0x19ba << 2) + 0xff620000) ++#define HCODEC_MCW_DBLK_WRRSP_CNT (0x19bb) ++#define P_HCODEC_MCW_DBLK_WRRSP_CNT (volatile unsigned int *)((0x19bb << 2) + 0xff620000) ++#define HCODEC_MC_MBBOT_WRRSP_CNT (0x19bc) ++#define P_HCODEC_MC_MBBOT_WRRSP_CNT (volatile unsigned int *)((0x19bc << 2) + 0xff620000) ++#define HCODEC_MDEC_PICW_BUF2_STATUS (0x19bd) ++#define P_HCODEC_MDEC_PICW_BUF2_STATUS (volatile unsigned int *)((0x19bd << 2) + 0xff620000) ++#define HCODEC_WRRSP_FIFO_PICW_DBK (0x19be) ++#define P_HCODEC_WRRSP_FIFO_PICW_DBK (volatile unsigned int *)((0x19be << 2) + 0xff620000) ++#define HCODEC_WRRSP_FIFO_PICW_MC (0x19bf) ++#define P_HCODEC_WRRSP_FIFO_PICW_MC (volatile unsigned int *)((0x19bf << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_0 (0x19c0) ++#define P_HCODEC_AV_SCRATCH_0 (volatile unsigned int *)((0x19c0 << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_1 (0x19c1) ++#define P_HCODEC_AV_SCRATCH_1 (volatile unsigned int *)((0x19c1 << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_2 (0x19c2) ++#define P_HCODEC_AV_SCRATCH_2 (volatile unsigned int *)((0x19c2 << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_3 (0x19c3) ++#define P_HCODEC_AV_SCRATCH_3 (volatile unsigned int *)((0x19c3 << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_4 (0x19c4) ++#define P_HCODEC_AV_SCRATCH_4 (volatile unsigned int *)((0x19c4 << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_5 (0x19c5) ++#define P_HCODEC_AV_SCRATCH_5 (volatile unsigned int *)((0x19c5 << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_6 (0x19c6) ++#define P_HCODEC_AV_SCRATCH_6 (volatile unsigned int *)((0x19c6 << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_7 (0x19c7) ++#define P_HCODEC_AV_SCRATCH_7 (volatile unsigned int *)((0x19c7 << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_8 (0x19c8) ++#define P_HCODEC_AV_SCRATCH_8 (volatile unsigned int *)((0x19c8 << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_9 (0x19c9) ++#define P_HCODEC_AV_SCRATCH_9 (volatile unsigned int *)((0x19c9 << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_A (0x19ca) ++#define P_HCODEC_AV_SCRATCH_A (volatile unsigned int *)((0x19ca << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_B (0x19cb) ++#define P_HCODEC_AV_SCRATCH_B (volatile unsigned int *)((0x19cb << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_C (0x19cc) ++#define P_HCODEC_AV_SCRATCH_C (volatile unsigned int *)((0x19cc << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_D (0x19cd) ++#define P_HCODEC_AV_SCRATCH_D (volatile unsigned int *)((0x19cd << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_E (0x19ce) ++#define P_HCODEC_AV_SCRATCH_E (volatile unsigned int *)((0x19ce << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_F (0x19cf) ++#define P_HCODEC_AV_SCRATCH_F (volatile unsigned int *)((0x19cf << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_G (0x19d0) ++#define P_HCODEC_AV_SCRATCH_G (volatile unsigned int *)((0x19d0 << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_H (0x19d1) ++#define P_HCODEC_AV_SCRATCH_H (volatile unsigned int *)((0x19d1 << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_I (0x19d2) ++#define P_HCODEC_AV_SCRATCH_I (volatile unsigned int *)((0x19d2 << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_J (0x19d3) ++#define P_HCODEC_AV_SCRATCH_J (volatile unsigned int *)((0x19d3 << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_K (0x19d4) ++#define P_HCODEC_AV_SCRATCH_K (volatile unsigned int *)((0x19d4 << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_L (0x19d5) ++#define P_HCODEC_AV_SCRATCH_L (volatile unsigned int *)((0x19d5 << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_M (0x19d6) ++#define P_HCODEC_AV_SCRATCH_M (volatile unsigned int *)((0x19d6 << 2) + 0xff620000) ++#define HCODEC_AV_SCRATCH_N (0x19d7) ++#define P_HCODEC_AV_SCRATCH_N (volatile unsigned int *)((0x19d7 << 2) + 0xff620000) ++// bit[29:24] A_brst_num_co_mb ++// bit[21:16] A_id_co_mb ++// bit[11:0] wrrsp_count_co_mb ++#define HCODEC_WRRSP_CO_MB (0x19d8) ++#define P_HCODEC_WRRSP_CO_MB (volatile unsigned int *)((0x19d8 << 2) + 0xff620000) ++// bit[29:24] A_brst_num_dcac ++// bit[21:16] A_id_dcac ++// bit[11:0] wrrsp_count_dcac ++#define HCODEC_WRRSP_DCAC (0x19d9) ++#define P_HCODEC_WRRSP_DCAC (volatile unsigned int *)((0x19d9 << 2) + 0xff620000) ++// bit[11:0] wrrsp_count_vld ++#define HCODEC_WRRSP_VLD (0x19da) ++#define P_HCODEC_WRRSP_VLD (volatile unsigned int *)((0x19da << 2) + 0xff620000) ++// doublew_cfg0[0]; // Second Channel Enable, 1:Enable 0:Disable ++// doublew_cfg0[3:1]; // [2:0] Endian Control for Luma ++// doublew_cfg0[5:4]; // [1:0] Pixel sel by horizontal, 0x:1/2 10:left 11:right ++// doublew_cfg0[7:6]; // [1:0] Pixel sel by vertical, 0x:1/2 10:up 11:down ++// doublew_cfg0[8]; // Size by horizontal, 0:original size 1: 1/2 shrunken size ++// doublew_cfg0[9]; // Size by vertical, 0:original size 1: 1/2 shrunken size ++// doublew_cfg0[10]; // 1:Round 0:Truncation ++// doublew_cfg0[11]; // DMA Urgent ++// doublew_cfg0[17:12]; // [5:0] DMA Burst Number ++// doublew_cfg0[23:18]; // [5:0] DMA ID ++// doublew_cfg0[26:24]; // [2:0] Endian Control for Chroma ++// doublew_cfg0[27]; // Source from, 1:MCW 0:DBLK ++// doublew_cfg0[29:28]; // [1:0] 0x:select both top and bottom 10:select top 11:select bottom ++// doublew_cfg0[30]; // 0:no merge 1:automatic merge ++// doublew_cfg0[31]; // 0:Y addr no change 1:Y addr divided to half ++#define HCODEC_MDEC_DOUBLEW_CFG0 (0x19db) ++#define P_HCODEC_MDEC_DOUBLEW_CFG0 (volatile unsigned int *)((0x19db << 2) + 0xff620000) ++// doublew_cfg1[7:0]; // [7:0] DMA Canvas Address for Luma ++// doublew_cfg1[15:8]; // [7:0] DMA Canvas Address for Chroma ++// doublew_cfg1[16]; // Disable 1st Write - ++// doublew_cfg1[17]; // Reverse to original version - ++// doublew_cfg1[18]; // DMA Address Mode - 0:Canvas Mode 1:Non-Canvas Mode ++#define HCODEC_MDEC_DOUBLEW_CFG1 (0x19dc) ++#define P_HCODEC_MDEC_DOUBLEW_CFG1 (volatile unsigned int *)((0x19dc << 2) + 0xff620000) ++// doublew_cfg2[11:0]; //[11:0] vertical flip initial value ++// doublew_cfg2[15]; // vertical flip enable ++// doublew_cfg2[24:16]; // [8:0] horizontal flip initial value ++// doublew_cfg2[31]; // horizontal flip enable ++#define HCODEC_MDEC_DOUBLEW_CFG2 (0x19dd) ++#define P_HCODEC_MDEC_DOUBLEW_CFG2 (volatile unsigned int *)((0x19dd << 2) + 0xff620000) ++// doublew_cfg3[31:0]; //[31:0] non-canvas start address for Luma - ++#define HCODEC_MDEC_DOUBLEW_CFG3 (0x19de) ++#define P_HCODEC_MDEC_DOUBLEW_CFG3 (volatile unsigned int *)((0x19de << 2) + 0xff620000) ++// doublew_cfg4[31:0]; //[31:0] non-canvas start address for Chroma - ++#define HCODEC_MDEC_DOUBLEW_CFG4 (0x19df) ++#define P_HCODEC_MDEC_DOUBLEW_CFG4 (volatile unsigned int *)((0x19df << 2) + 0xff620000) ++// doublew_cfg5[12:0]; //[12:0] non-canvas picture width for Luma - ++// doublew_cfg5[28:16]; //[12:0] non-canvas picture width for Chroma - ++#define HCODEC_MDEC_DOUBLEW_CFG5 (0x19e0) ++#define P_HCODEC_MDEC_DOUBLEW_CFG5 (volatile unsigned int *)((0x19e0 << 2) + 0xff620000) ++// doublew_cfg6: reserved ++#define HCODEC_MDEC_DOUBLEW_CFG6 (0x19e1) ++#define P_HCODEC_MDEC_DOUBLEW_CFG6 (volatile unsigned int *)((0x19e1 << 2) + 0xff620000) ++// doublew_cfg7: reserved ++#define HCODEC_MDEC_DOUBLEW_CFG7 (0x19e2) ++#define P_HCODEC_MDEC_DOUBLEW_CFG7 (volatile unsigned int *)((0x19e2 << 2) + 0xff620000) ++// doublew_status[11:0];//[11:0] wrrsp_count_doublew ++// doublew_status[12]; // doublew_status_busy ++// doublew_status[13]; // doublew_status_error ++#define HCODEC_MDEC_DOUBLEW_STATUS (0x19e3) ++#define P_HCODEC_MDEC_DOUBLEW_STATUS (volatile unsigned int *)((0x19e3 << 2) + 0xff620000) ++#define HCODEC_MDEC_EXTIF_CFG0 (0x19e4) ++#define P_HCODEC_MDEC_EXTIF_CFG0 (volatile unsigned int *)((0x19e4 << 2) + 0xff620000) ++#define HCODEC_MDEC_EXTIF_CFG1 (0x19e5) ++#define P_HCODEC_MDEC_EXTIF_CFG1 (volatile unsigned int *)((0x19e5 << 2) + 0xff620000) ++#define HCODEC_MDEC_EXTIF_STS0 (0x19e6) ++#define P_HCODEC_MDEC_EXTIF_STS0 (volatile unsigned int *)((0x19e6 << 2) + 0xff620000) ++//====================================== ++// MC Control Register Bits ++// ++//====================================== ++// For bits, just copy the defines...don't translate to addresses ++ //`define MC_RESET 16'h0002 ++//====================================== ++// MB Info Register Bits ++// ++//====================================== ++//====================================== ++// MB Info Register Bits ++// ++//====================================== ++//======================================================================== ++// DBLK Register: 12'h950 - 12'h97f ++//======================================================================== ++#define HCODEC_DBLK_RST (0x1950) ++#define P_HCODEC_DBLK_RST (volatile unsigned int *)((0x1950 << 2) + 0xff620000) ++#define HCODEC_DBLK_CTRL (0x1951) ++#define P_HCODEC_DBLK_CTRL (volatile unsigned int *)((0x1951 << 2) + 0xff620000) ++#define HCODEC_DBLK_MB_WID_HEIGHT (0x1952) ++#define P_HCODEC_DBLK_MB_WID_HEIGHT (volatile unsigned int *)((0x1952 << 2) + 0xff620000) ++#define HCODEC_DBLK_STATUS (0x1953) ++#define P_HCODEC_DBLK_STATUS (volatile unsigned int *)((0x1953 << 2) + 0xff620000) ++#define HCODEC_DBLK_CMD_CTRL (0x1954) ++#define P_HCODEC_DBLK_CMD_CTRL (volatile unsigned int *)((0x1954 << 2) + 0xff620000) ++#define HCODEC_DBLK_MB_XY (0x1955) ++#define P_HCODEC_DBLK_MB_XY (volatile unsigned int *)((0x1955 << 2) + 0xff620000) ++#define HCODEC_DBLK_QP (0x1956) ++#define P_HCODEC_DBLK_QP (volatile unsigned int *)((0x1956 << 2) + 0xff620000) ++#define HCODEC_DBLK_Y_BHFILT (0x1957) ++#define P_HCODEC_DBLK_Y_BHFILT (volatile unsigned int *)((0x1957 << 2) + 0xff620000) ++#define HCODEC_DBLK_Y_BHFILT_HIGH (0x1958) ++#define P_HCODEC_DBLK_Y_BHFILT_HIGH (volatile unsigned int *)((0x1958 << 2) + 0xff620000) ++#define HCODEC_DBLK_Y_BVFILT (0x1959) ++#define P_HCODEC_DBLK_Y_BVFILT (volatile unsigned int *)((0x1959 << 2) + 0xff620000) ++#define HCODEC_DBLK_CB_BFILT (0x195a) ++#define P_HCODEC_DBLK_CB_BFILT (volatile unsigned int *)((0x195a << 2) + 0xff620000) ++#define HCODEC_DBLK_CR_BFILT (0x195b) ++#define P_HCODEC_DBLK_CR_BFILT (volatile unsigned int *)((0x195b << 2) + 0xff620000) ++#define HCODEC_DBLK_Y_HFILT (0x195c) ++#define P_HCODEC_DBLK_Y_HFILT (volatile unsigned int *)((0x195c << 2) + 0xff620000) ++#define HCODEC_DBLK_Y_HFILT_HIGH (0x195d) ++#define P_HCODEC_DBLK_Y_HFILT_HIGH (volatile unsigned int *)((0x195d << 2) + 0xff620000) ++#define HCODEC_DBLK_Y_VFILT (0x195e) ++#define P_HCODEC_DBLK_Y_VFILT (volatile unsigned int *)((0x195e << 2) + 0xff620000) ++#define HCODEC_DBLK_CB_FILT (0x195f) ++#define P_HCODEC_DBLK_CB_FILT (volatile unsigned int *)((0x195f << 2) + 0xff620000) ++#define HCODEC_DBLK_CR_FILT (0x1960) ++#define P_HCODEC_DBLK_CR_FILT (volatile unsigned int *)((0x1960 << 2) + 0xff620000) ++#define HCODEC_DBLK_BETAX_QP_SEL (0x1961) ++#define P_HCODEC_DBLK_BETAX_QP_SEL (volatile unsigned int *)((0x1961 << 2) + 0xff620000) ++#define HCODEC_DBLK_CLIP_CTRL0 (0x1962) ++#define P_HCODEC_DBLK_CLIP_CTRL0 (volatile unsigned int *)((0x1962 << 2) + 0xff620000) ++#define HCODEC_DBLK_CLIP_CTRL1 (0x1963) ++#define P_HCODEC_DBLK_CLIP_CTRL1 (volatile unsigned int *)((0x1963 << 2) + 0xff620000) ++#define HCODEC_DBLK_CLIP_CTRL2 (0x1964) ++#define P_HCODEC_DBLK_CLIP_CTRL2 (volatile unsigned int *)((0x1964 << 2) + 0xff620000) ++#define HCODEC_DBLK_CLIP_CTRL3 (0x1965) ++#define P_HCODEC_DBLK_CLIP_CTRL3 (volatile unsigned int *)((0x1965 << 2) + 0xff620000) ++#define HCODEC_DBLK_CLIP_CTRL4 (0x1966) ++#define P_HCODEC_DBLK_CLIP_CTRL4 (volatile unsigned int *)((0x1966 << 2) + 0xff620000) ++#define HCODEC_DBLK_CLIP_CTRL5 (0x1967) ++#define P_HCODEC_DBLK_CLIP_CTRL5 (volatile unsigned int *)((0x1967 << 2) + 0xff620000) ++#define HCODEC_DBLK_CLIP_CTRL6 (0x1968) ++#define P_HCODEC_DBLK_CLIP_CTRL6 (volatile unsigned int *)((0x1968 << 2) + 0xff620000) ++#define HCODEC_DBLK_CLIP_CTRL7 (0x1969) ++#define P_HCODEC_DBLK_CLIP_CTRL7 (volatile unsigned int *)((0x1969 << 2) + 0xff620000) ++#define HCODEC_DBLK_CLIP_CTRL8 (0x196a) ++#define P_HCODEC_DBLK_CLIP_CTRL8 (volatile unsigned int *)((0x196a << 2) + 0xff620000) ++#define HCODEC_DBLK_STATUS1 (0x196b) ++#define P_HCODEC_DBLK_STATUS1 (volatile unsigned int *)((0x196b << 2) + 0xff620000) ++#define HCODEC_DBLK_GCLK_FREE (0x196c) ++#define P_HCODEC_DBLK_GCLK_FREE (volatile unsigned int *)((0x196c << 2) + 0xff620000) ++#define HCODEC_DBLK_GCLK_OFF (0x196d) ++#define P_HCODEC_DBLK_GCLK_OFF (volatile unsigned int *)((0x196d << 2) + 0xff620000) ++#define HCODEC_DBLK_AVSFLAGS (0x196e) ++#define P_HCODEC_DBLK_AVSFLAGS (volatile unsigned int *)((0x196e << 2) + 0xff620000) ++// bit 15:0 ++#define HCODEC_DBLK_CBPY (0x1970) ++#define P_HCODEC_DBLK_CBPY (volatile unsigned int *)((0x1970 << 2) + 0xff620000) ++// bit 11:8 -- deblk_cbpy_bottom ++// bit 7:4 -- deblk_cbpy_left ++// bit 3:0 -- deblk_cbpy_top ++#define HCODEC_DBLK_CBPY_ADJ (0x1971) ++#define P_HCODEC_DBLK_CBPY_ADJ (volatile unsigned int *)((0x1971 << 2) + 0xff620000) ++// bit 7:0 -- deblk_cbpc ++#define HCODEC_DBLK_CBPC (0x1972) ++#define P_HCODEC_DBLK_CBPC (volatile unsigned int *)((0x1972 << 2) + 0xff620000) ++// bit 15 -- bottom_mb ++// bit 14 -- left_mb ++// bit 13 -- top_mb ++// bit 12 -- reserved ++// bit 11:8 -- deblk_cbpc_bottom ++// bit 7:4 -- deblk_cbpc_left ++// bit 3:0 -- deblk_cbpc_top ++#define HCODEC_DBLK_CBPC_ADJ (0x1973) ++#define P_HCODEC_DBLK_CBPC_ADJ (volatile unsigned int *)((0x1973 << 2) + 0xff620000) ++// bit 15:8 -- deblk_hmvd -- {left_1, left_0, below_1, below_0, block3-0} ++// bit 7:0 -- deblk_vmvd -- {top_1, top_0, below_1, below_0, block3-0} ++#define HCODEC_DBLK_VHMVD (0x1974) ++#define P_HCODEC_DBLK_VHMVD (volatile unsigned int *)((0x1974 << 2) + 0xff620000) ++// bit 13:12 -- right_vmvd ++// bit 11 -- right_above_vmvd ++// bit 10 -- left_below_hmvd ++// bit 9 -- disable_dblk_luma ++// bit 8 -- disable_dblk_chroma ++// bit 7 -- bBelowRefDiff ++// bit 6 -- bLeftRefDiff ++// bit 5 -- bAboveRefDiff ++// bit 4 -- reserved ++// bit 3 -- s_below ++// bit 2 -- s_left ++// bit 1 -- s_above ++// bit 0 -- s ++#define HCODEC_DBLK_STRONG (0x1975) ++#define P_HCODEC_DBLK_STRONG (volatile unsigned int *)((0x1975 << 2) + 0xff620000) ++// bit 14:10 -- PQUANT ++// bit 9:5 -- left_PQUANT ++// bit 4:0 -- top_PQUANT ++#define HCODEC_DBLK_RV8_QUANT (0x1976) ++#define P_HCODEC_DBLK_RV8_QUANT (volatile unsigned int *)((0x1976 << 2) + 0xff620000) ++#define HCODEC_DBLK_CBUS_HCMD2 (0x1977) ++#define P_HCODEC_DBLK_CBUS_HCMD2 (volatile unsigned int *)((0x1977 << 2) + 0xff620000) ++#define HCODEC_DBLK_CBUS_HCMD1 (0x1978) ++#define P_HCODEC_DBLK_CBUS_HCMD1 (volatile unsigned int *)((0x1978 << 2) + 0xff620000) ++#define HCODEC_DBLK_CBUS_HCMD0 (0x1979) ++#define P_HCODEC_DBLK_CBUS_HCMD0 (volatile unsigned int *)((0x1979 << 2) + 0xff620000) ++#define HCODEC_DBLK_VLD_HCMD2 (0x197a) ++#define P_HCODEC_DBLK_VLD_HCMD2 (volatile unsigned int *)((0x197a << 2) + 0xff620000) ++#define HCODEC_DBLK_VLD_HCMD1 (0x197b) ++#define P_HCODEC_DBLK_VLD_HCMD1 (volatile unsigned int *)((0x197b << 2) + 0xff620000) ++#define HCODEC_DBLK_VLD_HCMD0 (0x197c) ++#define P_HCODEC_DBLK_VLD_HCMD0 (volatile unsigned int *)((0x197c << 2) + 0xff620000) ++#define HCODEC_DBLK_OST_YBASE (0x197d) ++#define P_HCODEC_DBLK_OST_YBASE (volatile unsigned int *)((0x197d << 2) + 0xff620000) ++#define HCODEC_DBLK_OST_CBCRDIFF (0x197e) ++#define P_HCODEC_DBLK_OST_CBCRDIFF (volatile unsigned int *)((0x197e << 2) + 0xff620000) ++//13:8 dblk thread ID and token ++//5:0 dblk prearbitor burst num ++#define HCODEC_DBLK_CTRL1 (0x197f) ++#define P_HCODEC_DBLK_CTRL1 (volatile unsigned int *)((0x197f << 2) + 0xff620000) ++// MCRCC_CTL1 ++// 31:3 ++// 2 ++// 1 ++// 0 ++#define HCODEC_MCRCC_CTL1 (0x1980) ++#define P_HCODEC_MCRCC_CTL1 (volatile unsigned int *)((0x1980 << 2) + 0xff620000) ++// MCRCC_CTL2 ++// 31:24 ++// 23:16 ++// 15:8 ++// 7:0 ++#define HCODEC_MCRCC_CTL2 (0x1981) ++#define P_HCODEC_MCRCC_CTL2 (volatile unsigned int *)((0x1981 << 2) + 0xff620000) ++// MCRCC_CTL3 ++// 31:24 ++// 23:16 ++// 15:8 ++// 7:0 ++#define HCODEC_MCRCC_CTL3 (0x1982) ++#define P_HCODEC_MCRCC_CTL3 (volatile unsigned int *)((0x1982 << 2) + 0xff620000) ++// bit[31:10] reserved ++// bit[9:0] sw_clock_gating control ++// [9] vdec clk_en for assist and cbus. ++// [8] vdec clk_en for ddr ++// [7] vdec clk_en for vcpu ++// [6] vdec clk_en for assist ++// [5] vdec clk_en for dblk ++// [4] vdec clk_en for iqidct ++// [3] vdec clk_en for mc ++// [2] vdec clk_en for pic_dc ++// [1] vdec clk_en for psc ++// [0] vdec clk_en for vld ++#define HCODEC_GCLK_EN (0x1983) ++#define P_HCODEC_GCLK_EN (volatile unsigned int *)((0x1983 << 2) + 0xff620000) ++// [0] Reserved ++// [1] Reserved ++// [2] Reset assist, mdec's CBUS ++// [3] Reset mdec's VLD ++// [4] Reset mdec's VLD ++// [5] Reset mdec's VLD ++// [6] Reset mdec's IQIDCT ++// [7] Reset mdec's MC ++// [8] Reset mdec's DBLK ++// [9] Reset mdec's PIC_DC ++// [10] Reset mdec's Pscale ++// [11] Reset vcpu's MCPU ++// [12] Reset vcpu's CCPU ++// [13] Reset mmc_pre_arb ++#define HCODEC_MDEC_SW_RESET (0x1984) ++#define P_HCODEC_MDEC_SW_RESET (volatile unsigned int *)((0x1984 << 2) + 0xff620000) ++//DBLK last address 12'h97f ++// ++// Closing file: mdec_regs.h ++// ++// ++// Reading file: mdec_regs.h ++// ++//======================================================================== ++// MDEC module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_VDEC_MDEC_CBUS_BASE = 0x09 ++// ----------------------------------------------- ++#define VDEC2_MC_CTRL_REG (0x2900) ++#define P_VDEC2_MC_CTRL_REG (volatile unsigned int *)((0x2900 << 2) + 0xff620000) ++#define VDEC2_MC_MB_INFO (0x2901) ++#define P_VDEC2_MC_MB_INFO (volatile unsigned int *)((0x2901 << 2) + 0xff620000) ++#define VDEC2_MC_PIC_INFO (0x2902) ++#define P_VDEC2_MC_PIC_INFO (volatile unsigned int *)((0x2902 << 2) + 0xff620000) ++#define VDEC2_MC_HALF_PEL_ONE (0x2903) ++#define P_VDEC2_MC_HALF_PEL_ONE (volatile unsigned int *)((0x2903 << 2) + 0xff620000) ++#define VDEC2_MC_HALF_PEL_TWO (0x2904) ++#define P_VDEC2_MC_HALF_PEL_TWO (volatile unsigned int *)((0x2904 << 2) + 0xff620000) ++#define VDEC2_POWER_CTL_MC (0x2905) ++#define P_VDEC2_POWER_CTL_MC (volatile unsigned int *)((0x2905 << 2) + 0xff620000) ++#define VDEC2_MC_CMD (0x2906) ++#define P_VDEC2_MC_CMD (volatile unsigned int *)((0x2906 << 2) + 0xff620000) ++#define VDEC2_MC_CTRL0 (0x2907) ++#define P_VDEC2_MC_CTRL0 (volatile unsigned int *)((0x2907 << 2) + 0xff620000) ++#define VDEC2_MC_PIC_W_H (0x2908) ++#define P_VDEC2_MC_PIC_W_H (volatile unsigned int *)((0x2908 << 2) + 0xff620000) ++#define VDEC2_MC_STATUS0 (0x2909) ++#define P_VDEC2_MC_STATUS0 (volatile unsigned int *)((0x2909 << 2) + 0xff620000) ++#define VDEC2_MC_STATUS1 (0x290a) ++#define P_VDEC2_MC_STATUS1 (volatile unsigned int *)((0x290a << 2) + 0xff620000) ++#define VDEC2_MC_CTRL1 (0x290b) ++#define P_VDEC2_MC_CTRL1 (volatile unsigned int *)((0x290b << 2) + 0xff620000) ++#define VDEC2_MC_MIX_RATIO0 (0x290c) ++#define P_VDEC2_MC_MIX_RATIO0 (volatile unsigned int *)((0x290c << 2) + 0xff620000) ++#define VDEC2_MC_MIX_RATIO1 (0x290d) ++#define P_VDEC2_MC_MIX_RATIO1 (volatile unsigned int *)((0x290d << 2) + 0xff620000) ++#define VDEC2_MC_DP_MB_XY (0x290e) ++#define P_VDEC2_MC_DP_MB_XY (volatile unsigned int *)((0x290e << 2) + 0xff620000) ++#define VDEC2_MC_OM_MB_XY (0x290f) ++#define P_VDEC2_MC_OM_MB_XY (volatile unsigned int *)((0x290f << 2) + 0xff620000) ++#define VDEC2_PSCALE_RST (0x2910) ++#define P_VDEC2_PSCALE_RST (volatile unsigned int *)((0x2910 << 2) + 0xff620000) ++#define VDEC2_PSCALE_CTRL (0x2911) ++#define P_VDEC2_PSCALE_CTRL (volatile unsigned int *)((0x2911 << 2) + 0xff620000) ++#define VDEC2_PSCALE_PICI_W (0x2912) ++#define P_VDEC2_PSCALE_PICI_W (volatile unsigned int *)((0x2912 << 2) + 0xff620000) ++#define VDEC2_PSCALE_PICI_H (0x2913) ++#define P_VDEC2_PSCALE_PICI_H (volatile unsigned int *)((0x2913 << 2) + 0xff620000) ++#define VDEC2_PSCALE_PICO_W (0x2914) ++#define P_VDEC2_PSCALE_PICO_W (volatile unsigned int *)((0x2914 << 2) + 0xff620000) ++#define VDEC2_PSCALE_PICO_H (0x2915) ++#define P_VDEC2_PSCALE_PICO_H (volatile unsigned int *)((0x2915 << 2) + 0xff620000) ++#define VDEC2_PSCALE_PICO_START_X (0x2916) ++#define P_VDEC2_PSCALE_PICO_START_X (volatile unsigned int *)((0x2916 << 2) + 0xff620000) ++#define VDEC2_PSCALE_PICO_START_Y (0x2917) ++#define P_VDEC2_PSCALE_PICO_START_Y (volatile unsigned int *)((0x2917 << 2) + 0xff620000) ++#define VDEC2_PSCALE_DUMMY (0x2918) ++#define P_VDEC2_PSCALE_DUMMY (volatile unsigned int *)((0x2918 << 2) + 0xff620000) ++#define VDEC2_PSCALE_FILT0_COEF0 (0x2919) ++#define P_VDEC2_PSCALE_FILT0_COEF0 (volatile unsigned int *)((0x2919 << 2) + 0xff620000) ++#define VDEC2_PSCALE_FILT0_COEF1 (0x291a) ++#define P_VDEC2_PSCALE_FILT0_COEF1 (volatile unsigned int *)((0x291a << 2) + 0xff620000) ++#define VDEC2_PSCALE_CMD_CTRL (0x291b) ++#define P_VDEC2_PSCALE_CMD_CTRL (volatile unsigned int *)((0x291b << 2) + 0xff620000) ++#define VDEC2_PSCALE_CMD_BLK_X (0x291c) ++#define P_VDEC2_PSCALE_CMD_BLK_X (volatile unsigned int *)((0x291c << 2) + 0xff620000) ++#define VDEC2_PSCALE_CMD_BLK_Y (0x291d) ++#define P_VDEC2_PSCALE_CMD_BLK_Y (volatile unsigned int *)((0x291d << 2) + 0xff620000) ++#define VDEC2_PSCALE_STATUS (0x291e) ++#define P_VDEC2_PSCALE_STATUS (volatile unsigned int *)((0x291e << 2) + 0xff620000) ++#define VDEC2_PSCALE_BMEM_ADDR (0x291f) ++#define P_VDEC2_PSCALE_BMEM_ADDR (volatile unsigned int *)((0x291f << 2) + 0xff620000) ++#define VDEC2_PSCALE_BMEM_DAT (0x2920) ++#define P_VDEC2_PSCALE_BMEM_DAT (volatile unsigned int *)((0x2920 << 2) + 0xff620000) ++#define VDEC2_PSCALE_DRAM_BUF_CTRL (0x2921) ++#define P_VDEC2_PSCALE_DRAM_BUF_CTRL (volatile unsigned int *)((0x2921 << 2) + 0xff620000) ++#define VDEC2_PSCALE_MCMD_CTRL (0x2922) ++#define P_VDEC2_PSCALE_MCMD_CTRL (volatile unsigned int *)((0x2922 << 2) + 0xff620000) ++#define VDEC2_PSCALE_MCMD_XSIZE (0x2923) ++#define P_VDEC2_PSCALE_MCMD_XSIZE (volatile unsigned int *)((0x2923 << 2) + 0xff620000) ++#define VDEC2_PSCALE_MCMD_YSIZE (0x2924) ++#define P_VDEC2_PSCALE_MCMD_YSIZE (volatile unsigned int *)((0x2924 << 2) + 0xff620000) ++#define VDEC2_PSCALE_RBUF_START_BLKX (0x2925) ++#define P_VDEC2_PSCALE_RBUF_START_BLKX (volatile unsigned int *)((0x2925 << 2) + 0xff620000) ++#define VDEC2_PSCALE_RBUF_START_BLKY (0x2926) ++#define P_VDEC2_PSCALE_RBUF_START_BLKY (volatile unsigned int *)((0x2926 << 2) + 0xff620000) ++//`define PSCALE_RBUF_MB_WIDTH 8'h27 ++#define VDEC2_PSCALE_PICO_SHIFT_XY (0x2928) ++#define P_VDEC2_PSCALE_PICO_SHIFT_XY (volatile unsigned int *)((0x2928 << 2) + 0xff620000) ++#define VDEC2_PSCALE_CTRL1 (0x2929) ++#define P_VDEC2_PSCALE_CTRL1 (volatile unsigned int *)((0x2929 << 2) + 0xff620000) ++//Bit 15, wmask enable ++//Bit 14:13, filt0 srckey_less, ++//Bit 12:11, filt1 srckey_less, in the case of the interpolated data is equal distance to ++//key data and normal data, 00: select normal data, 01: select right data, 10: select key data ++//Bit 10:9, srckey mode, 00: equal, 01: less than or equal, 10: great than or equal ++//Bit 8, src key enable ++//Bit 7:0, y src key ++#define VDEC2_PSCALE_SRCKEY_CTRL0 (0x292a) ++#define P_VDEC2_PSCALE_SRCKEY_CTRL0 (volatile unsigned int *)((0x292a << 2) + 0xff620000) ++//Bit 15:8, cb src key ++//Bit 7:0, cr src key ++#define VDEC2_PSCALE_SRCKEY_CTRL1 (0x292b) ++#define P_VDEC2_PSCALE_SRCKEY_CTRL1 (volatile unsigned int *)((0x292b << 2) + 0xff620000) ++//Bit 22:16 canvas_rd_addr2 ++//Bit 14:8 canvas_rd_addr1 ++//Bit 6:0 canvas_rd_addr1 ++#define VDEC2_PSCALE_CANVAS_RD_ADDR (0x292c) ++#define P_VDEC2_PSCALE_CANVAS_RD_ADDR (volatile unsigned int *)((0x292c << 2) + 0xff620000) ++//Bit 22:16 canvas_wr_addr2 ++//Bit 14:8 canvas_wr_addr1 ++//Bit 6:0 canvas_wr_addr1 ++#define VDEC2_PSCALE_CANVAS_WR_ADDR (0x292d) ++#define P_VDEC2_PSCALE_CANVAS_WR_ADDR (volatile unsigned int *)((0x292d << 2) + 0xff620000) ++//bit 13:8 pscale thread ID and token ++//bit 7 disable write response count adding to busy bit ++//bit 5:0 pscale prearbitor burst num ++#define VDEC2_PSCALE_CTRL2 (0x292e) ++#define P_VDEC2_PSCALE_CTRL2 (volatile unsigned int *)((0x292e << 2) + 0xff620000) ++// 31 - use_omem_mb_xy_auto ++//23:16 - omem_max_mb_x ++//15:8 - omem_mb_y_auto ++// 7:0 - omem_mb_x_auto ++#define VDEC2_HDEC_MC_OMEM_AUTO (0x2930) ++#define P_VDEC2_HDEC_MC_OMEM_AUTO (volatile unsigned int *)((0x2930 << 2) + 0xff620000) ++#define VDEC2_HDEC_MC_MBRIGHT_IDX (0x2931) ++#define P_VDEC2_HDEC_MC_MBRIGHT_IDX (volatile unsigned int *)((0x2931 << 2) + 0xff620000) ++#define VDEC2_HDEC_MC_MBRIGHT_RD (0x2932) ++#define P_VDEC2_HDEC_MC_MBRIGHT_RD (volatile unsigned int *)((0x2932 << 2) + 0xff620000) ++#define VDEC2_MC_MPORT_CTRL (0x2940) ++#define P_VDEC2_MC_MPORT_CTRL (volatile unsigned int *)((0x2940 << 2) + 0xff620000) ++#define VDEC2_MC_MPORT_DAT (0x2941) ++#define P_VDEC2_MC_MPORT_DAT (volatile unsigned int *)((0x2941 << 2) + 0xff620000) ++#define VDEC2_MC_WT_PRED_CTRL (0x2942) ++#define P_VDEC2_MC_WT_PRED_CTRL (volatile unsigned int *)((0x2942 << 2) + 0xff620000) ++#define VDEC2_MC_MBBOT_ST_EVEN_ADDR (0x2944) ++#define P_VDEC2_MC_MBBOT_ST_EVEN_ADDR (volatile unsigned int *)((0x2944 << 2) + 0xff620000) ++#define VDEC2_MC_MBBOT_ST_ODD_ADDR (0x2945) ++#define P_VDEC2_MC_MBBOT_ST_ODD_ADDR (volatile unsigned int *)((0x2945 << 2) + 0xff620000) ++#define VDEC2_MC_DPDN_MB_XY (0x2946) ++#define P_VDEC2_MC_DPDN_MB_XY (volatile unsigned int *)((0x2946 << 2) + 0xff620000) ++#define VDEC2_MC_OMDN_MB_XY (0x2947) ++#define P_VDEC2_MC_OMDN_MB_XY (volatile unsigned int *)((0x2947 << 2) + 0xff620000) ++#define VDEC2_MC_HCMDBUF_H (0x2948) ++#define P_VDEC2_MC_HCMDBUF_H (volatile unsigned int *)((0x2948 << 2) + 0xff620000) ++#define VDEC2_MC_HCMDBUF_L (0x2949) ++#define P_VDEC2_MC_HCMDBUF_L (volatile unsigned int *)((0x2949 << 2) + 0xff620000) ++#define VDEC2_MC_HCMD_H (0x294a) ++#define P_VDEC2_MC_HCMD_H (volatile unsigned int *)((0x294a << 2) + 0xff620000) ++#define VDEC2_MC_HCMD_L (0x294b) ++#define P_VDEC2_MC_HCMD_L (volatile unsigned int *)((0x294b << 2) + 0xff620000) ++#define VDEC2_MC_IDCT_DAT (0x294c) ++#define P_VDEC2_MC_IDCT_DAT (volatile unsigned int *)((0x294c << 2) + 0xff620000) ++#define VDEC2_MC_CTRL_GCLK_CTRL (0x294d) ++#define P_VDEC2_MC_CTRL_GCLK_CTRL (volatile unsigned int *)((0x294d << 2) + 0xff620000) ++#define VDEC2_MC_OTHER_GCLK_CTRL (0x294e) ++#define P_VDEC2_MC_OTHER_GCLK_CTRL (volatile unsigned int *)((0x294e << 2) + 0xff620000) ++//Bit 29:24, mbbot thread ID and token ++//Bit 21:16, mc read/write thread ID and token ++//Bit 13:8, mbbot pre-arbitor burst number ++//Bit 5:0, mc pre-arbitor burst number ++#define VDEC2_MC_CTRL2 (0x294f) ++#define P_VDEC2_MC_CTRL2 (volatile unsigned int *)((0x294f << 2) + 0xff620000) ++// `define DBLK_QUANT 8'h76 // ONLY for $ucode/real/amrisc/rv.s, reg value from apollo ++//`define ANC1_CANVAS_ADDR 8'h80 ++//`define ANC2_CANVAS_ADDR 8'h81 ++//`define REC_CANVAS_ADDR 8'h89 ++//`define MDEC_PIC_W 8'h8c ++//`define MDEC_PIC_H 8'h8d ++// mdec_pic_dc_mux_ctrl[31] -- mcr_hevc_mode ++#define VDEC2_MDEC_PIC_DC_MUX_CTRL (0x298d) ++#define P_VDEC2_MDEC_PIC_DC_MUX_CTRL (volatile unsigned int *)((0x298d << 2) + 0xff620000) ++#define VDEC2_MDEC_PIC_DC_CTRL (0x298e) ++#define P_VDEC2_MDEC_PIC_DC_CTRL (volatile unsigned int *)((0x298e << 2) + 0xff620000) ++#define VDEC2_MDEC_PIC_DC_STATUS (0x298f) ++#define P_VDEC2_MDEC_PIC_DC_STATUS (volatile unsigned int *)((0x298f << 2) + 0xff620000) ++#define VDEC2_ANC0_CANVAS_ADDR (0x2990) ++#define P_VDEC2_ANC0_CANVAS_ADDR (volatile unsigned int *)((0x2990 << 2) + 0xff620000) ++#define VDEC2_ANC1_CANVAS_ADDR (0x2991) ++#define P_VDEC2_ANC1_CANVAS_ADDR (volatile unsigned int *)((0x2991 << 2) + 0xff620000) ++#define VDEC2_ANC2_CANVAS_ADDR (0x2992) ++#define P_VDEC2_ANC2_CANVAS_ADDR (volatile unsigned int *)((0x2992 << 2) + 0xff620000) ++#define VDEC2_ANC3_CANVAS_ADDR (0x2993) ++#define P_VDEC2_ANC3_CANVAS_ADDR (volatile unsigned int *)((0x2993 << 2) + 0xff620000) ++#define VDEC2_ANC4_CANVAS_ADDR (0x2994) ++#define P_VDEC2_ANC4_CANVAS_ADDR (volatile unsigned int *)((0x2994 << 2) + 0xff620000) ++#define VDEC2_ANC5_CANVAS_ADDR (0x2995) ++#define P_VDEC2_ANC5_CANVAS_ADDR (volatile unsigned int *)((0x2995 << 2) + 0xff620000) ++#define VDEC2_ANC6_CANVAS_ADDR (0x2996) ++#define P_VDEC2_ANC6_CANVAS_ADDR (volatile unsigned int *)((0x2996 << 2) + 0xff620000) ++#define VDEC2_ANC7_CANVAS_ADDR (0x2997) ++#define P_VDEC2_ANC7_CANVAS_ADDR (volatile unsigned int *)((0x2997 << 2) + 0xff620000) ++#define VDEC2_ANC8_CANVAS_ADDR (0x2998) ++#define P_VDEC2_ANC8_CANVAS_ADDR (volatile unsigned int *)((0x2998 << 2) + 0xff620000) ++#define VDEC2_ANC9_CANVAS_ADDR (0x2999) ++#define P_VDEC2_ANC9_CANVAS_ADDR (volatile unsigned int *)((0x2999 << 2) + 0xff620000) ++#define VDEC2_ANC10_CANVAS_ADDR (0x299a) ++#define P_VDEC2_ANC10_CANVAS_ADDR (volatile unsigned int *)((0x299a << 2) + 0xff620000) ++#define VDEC2_ANC11_CANVAS_ADDR (0x299b) ++#define P_VDEC2_ANC11_CANVAS_ADDR (volatile unsigned int *)((0x299b << 2) + 0xff620000) ++#define VDEC2_ANC12_CANVAS_ADDR (0x299c) ++#define P_VDEC2_ANC12_CANVAS_ADDR (volatile unsigned int *)((0x299c << 2) + 0xff620000) ++#define VDEC2_ANC13_CANVAS_ADDR (0x299d) ++#define P_VDEC2_ANC13_CANVAS_ADDR (volatile unsigned int *)((0x299d << 2) + 0xff620000) ++#define VDEC2_ANC14_CANVAS_ADDR (0x299e) ++#define P_VDEC2_ANC14_CANVAS_ADDR (volatile unsigned int *)((0x299e << 2) + 0xff620000) ++#define VDEC2_ANC15_CANVAS_ADDR (0x299f) ++#define P_VDEC2_ANC15_CANVAS_ADDR (volatile unsigned int *)((0x299f << 2) + 0xff620000) ++#define VDEC2_ANC16_CANVAS_ADDR (0x29a0) ++#define P_VDEC2_ANC16_CANVAS_ADDR (volatile unsigned int *)((0x29a0 << 2) + 0xff620000) ++#define VDEC2_ANC17_CANVAS_ADDR (0x29a1) ++#define P_VDEC2_ANC17_CANVAS_ADDR (volatile unsigned int *)((0x29a1 << 2) + 0xff620000) ++#define VDEC2_ANC18_CANVAS_ADDR (0x29a2) ++#define P_VDEC2_ANC18_CANVAS_ADDR (volatile unsigned int *)((0x29a2 << 2) + 0xff620000) ++#define VDEC2_ANC19_CANVAS_ADDR (0x29a3) ++#define P_VDEC2_ANC19_CANVAS_ADDR (volatile unsigned int *)((0x29a3 << 2) + 0xff620000) ++#define VDEC2_ANC20_CANVAS_ADDR (0x29a4) ++#define P_VDEC2_ANC20_CANVAS_ADDR (volatile unsigned int *)((0x29a4 << 2) + 0xff620000) ++#define VDEC2_ANC21_CANVAS_ADDR (0x29a5) ++#define P_VDEC2_ANC21_CANVAS_ADDR (volatile unsigned int *)((0x29a5 << 2) + 0xff620000) ++#define VDEC2_ANC22_CANVAS_ADDR (0x29a6) ++#define P_VDEC2_ANC22_CANVAS_ADDR (volatile unsigned int *)((0x29a6 << 2) + 0xff620000) ++#define VDEC2_ANC23_CANVAS_ADDR (0x29a7) ++#define P_VDEC2_ANC23_CANVAS_ADDR (volatile unsigned int *)((0x29a7 << 2) + 0xff620000) ++#define VDEC2_ANC24_CANVAS_ADDR (0x29a8) ++#define P_VDEC2_ANC24_CANVAS_ADDR (volatile unsigned int *)((0x29a8 << 2) + 0xff620000) ++#define VDEC2_ANC25_CANVAS_ADDR (0x29a9) ++#define P_VDEC2_ANC25_CANVAS_ADDR (volatile unsigned int *)((0x29a9 << 2) + 0xff620000) ++#define VDEC2_ANC26_CANVAS_ADDR (0x29aa) ++#define P_VDEC2_ANC26_CANVAS_ADDR (volatile unsigned int *)((0x29aa << 2) + 0xff620000) ++#define VDEC2_ANC27_CANVAS_ADDR (0x29ab) ++#define P_VDEC2_ANC27_CANVAS_ADDR (volatile unsigned int *)((0x29ab << 2) + 0xff620000) ++#define VDEC2_ANC28_CANVAS_ADDR (0x29ac) ++#define P_VDEC2_ANC28_CANVAS_ADDR (volatile unsigned int *)((0x29ac << 2) + 0xff620000) ++#define VDEC2_ANC29_CANVAS_ADDR (0x29ad) ++#define P_VDEC2_ANC29_CANVAS_ADDR (volatile unsigned int *)((0x29ad << 2) + 0xff620000) ++#define VDEC2_ANC30_CANVAS_ADDR (0x29ae) ++#define P_VDEC2_ANC30_CANVAS_ADDR (volatile unsigned int *)((0x29ae << 2) + 0xff620000) ++#define VDEC2_ANC31_CANVAS_ADDR (0x29af) ++#define P_VDEC2_ANC31_CANVAS_ADDR (volatile unsigned int *)((0x29af << 2) + 0xff620000) ++#define VDEC2_DBKR_CANVAS_ADDR (0x29b0) ++#define P_VDEC2_DBKR_CANVAS_ADDR (volatile unsigned int *)((0x29b0 << 2) + 0xff620000) ++#define VDEC2_DBKW_CANVAS_ADDR (0x29b1) ++#define P_VDEC2_DBKW_CANVAS_ADDR (volatile unsigned int *)((0x29b1 << 2) + 0xff620000) ++#define VDEC2_REC_CANVAS_ADDR (0x29b2) ++#define P_VDEC2_REC_CANVAS_ADDR (volatile unsigned int *)((0x29b2 << 2) + 0xff620000) ++//28:24, read/write, current canvas idx, used in h264 only now ++//23:0, read only, current canvas address, 23:16, Cr canvas addr, 15:8, Cb canvas addr, 7:0, Y canvas addr ++#define VDEC2_CURR_CANVAS_CTRL (0x29b3) ++#define P_VDEC2_CURR_CANVAS_CTRL (volatile unsigned int *)((0x29b3 << 2) + 0xff620000) ++#define VDEC2_MDEC_PIC_DC_THRESH (0x29b8) ++#define P_VDEC2_MDEC_PIC_DC_THRESH (volatile unsigned int *)((0x29b8 << 2) + 0xff620000) ++#define VDEC2_MDEC_PICR_BUF_STATUS (0x29b9) ++#define P_VDEC2_MDEC_PICR_BUF_STATUS (volatile unsigned int *)((0x29b9 << 2) + 0xff620000) ++#define VDEC2_MDEC_PICW_BUF_STATUS (0x29ba) ++#define P_VDEC2_MDEC_PICW_BUF_STATUS (volatile unsigned int *)((0x29ba << 2) + 0xff620000) ++#define VDEC2_MCW_DBLK_WRRSP_CNT (0x29bb) ++#define P_VDEC2_MCW_DBLK_WRRSP_CNT (volatile unsigned int *)((0x29bb << 2) + 0xff620000) ++#define VDEC2_MC_MBBOT_WRRSP_CNT (0x29bc) ++#define P_VDEC2_MC_MBBOT_WRRSP_CNT (volatile unsigned int *)((0x29bc << 2) + 0xff620000) ++#define VDEC2_MDEC_PICW_BUF2_STATUS (0x29bd) ++#define P_VDEC2_MDEC_PICW_BUF2_STATUS (volatile unsigned int *)((0x29bd << 2) + 0xff620000) ++#define VDEC2_WRRSP_FIFO_PICW_DBK (0x29be) ++#define P_VDEC2_WRRSP_FIFO_PICW_DBK (volatile unsigned int *)((0x29be << 2) + 0xff620000) ++#define VDEC2_WRRSP_FIFO_PICW_MC (0x29bf) ++#define P_VDEC2_WRRSP_FIFO_PICW_MC (volatile unsigned int *)((0x29bf << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_0 (0x29c0) ++#define P_VDEC2_AV_SCRATCH_0 (volatile unsigned int *)((0x29c0 << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_1 (0x29c1) ++#define P_VDEC2_AV_SCRATCH_1 (volatile unsigned int *)((0x29c1 << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_2 (0x29c2) ++#define P_VDEC2_AV_SCRATCH_2 (volatile unsigned int *)((0x29c2 << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_3 (0x29c3) ++#define P_VDEC2_AV_SCRATCH_3 (volatile unsigned int *)((0x29c3 << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_4 (0x29c4) ++#define P_VDEC2_AV_SCRATCH_4 (volatile unsigned int *)((0x29c4 << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_5 (0x29c5) ++#define P_VDEC2_AV_SCRATCH_5 (volatile unsigned int *)((0x29c5 << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_6 (0x29c6) ++#define P_VDEC2_AV_SCRATCH_6 (volatile unsigned int *)((0x29c6 << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_7 (0x29c7) ++#define P_VDEC2_AV_SCRATCH_7 (volatile unsigned int *)((0x29c7 << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_8 (0x29c8) ++#define P_VDEC2_AV_SCRATCH_8 (volatile unsigned int *)((0x29c8 << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_9 (0x29c9) ++#define P_VDEC2_AV_SCRATCH_9 (volatile unsigned int *)((0x29c9 << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_A (0x29ca) ++#define P_VDEC2_AV_SCRATCH_A (volatile unsigned int *)((0x29ca << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_B (0x29cb) ++#define P_VDEC2_AV_SCRATCH_B (volatile unsigned int *)((0x29cb << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_C (0x29cc) ++#define P_VDEC2_AV_SCRATCH_C (volatile unsigned int *)((0x29cc << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_D (0x29cd) ++#define P_VDEC2_AV_SCRATCH_D (volatile unsigned int *)((0x29cd << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_E (0x29ce) ++#define P_VDEC2_AV_SCRATCH_E (volatile unsigned int *)((0x29ce << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_F (0x29cf) ++#define P_VDEC2_AV_SCRATCH_F (volatile unsigned int *)((0x29cf << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_G (0x29d0) ++#define P_VDEC2_AV_SCRATCH_G (volatile unsigned int *)((0x29d0 << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_H (0x29d1) ++#define P_VDEC2_AV_SCRATCH_H (volatile unsigned int *)((0x29d1 << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_I (0x29d2) ++#define P_VDEC2_AV_SCRATCH_I (volatile unsigned int *)((0x29d2 << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_J (0x29d3) ++#define P_VDEC2_AV_SCRATCH_J (volatile unsigned int *)((0x29d3 << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_K (0x29d4) ++#define P_VDEC2_AV_SCRATCH_K (volatile unsigned int *)((0x29d4 << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_L (0x29d5) ++#define P_VDEC2_AV_SCRATCH_L (volatile unsigned int *)((0x29d5 << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_M (0x29d6) ++#define P_VDEC2_AV_SCRATCH_M (volatile unsigned int *)((0x29d6 << 2) + 0xff620000) ++#define VDEC2_AV_SCRATCH_N (0x29d7) ++#define P_VDEC2_AV_SCRATCH_N (volatile unsigned int *)((0x29d7 << 2) + 0xff620000) ++// bit[29:24] A_brst_num_co_mb ++// bit[21:16] A_id_co_mb ++// bit[11:0] wrrsp_count_co_mb ++#define VDEC2_WRRSP_CO_MB (0x29d8) ++#define P_VDEC2_WRRSP_CO_MB (volatile unsigned int *)((0x29d8 << 2) + 0xff620000) ++// bit[29:24] A_brst_num_dcac ++// bit[21:16] A_id_dcac ++// bit[11:0] wrrsp_count_dcac ++#define VDEC2_WRRSP_DCAC (0x29d9) ++#define P_VDEC2_WRRSP_DCAC (volatile unsigned int *)((0x29d9 << 2) + 0xff620000) ++// bit[11:0] wrrsp_count_vld ++#define VDEC2_WRRSP_VLD (0x29da) ++#define P_VDEC2_WRRSP_VLD (volatile unsigned int *)((0x29da << 2) + 0xff620000) ++// doublew_cfg0[0]; // Second Channel Enable, 1:Enable 0:Disable ++// doublew_cfg0[3:1]; // [2:0] Endian Control for Luma ++// doublew_cfg0[5:4]; // [1:0] Pixel sel by horizontal, 0x:1/2 10:left 11:right ++// doublew_cfg0[7:6]; // [1:0] Pixel sel by vertical, 0x:1/2 10:up 11:down ++// doublew_cfg0[8]; // Size by horizontal, 0:original size 1: 1/2 shrunken size ++// doublew_cfg0[9]; // Size by vertical, 0:original size 1: 1/2 shrunken size ++// doublew_cfg0[10]; // 1:Round 0:Truncation ++// doublew_cfg0[11]; // DMA Urgent ++// doublew_cfg0[17:12]; // [5:0] DMA Burst Number ++// doublew_cfg0[23:18]; // [5:0] DMA ID ++// doublew_cfg0[26:24]; // [2:0] Endian Control for Chroma ++// doublew_cfg0[27]; // Source from, 1:MCW 0:DBLK ++// doublew_cfg0[29:28]; // [1:0] 0x:select both top and bottom 10:select top 11:select bottom ++// doublew_cfg0[30]; // 0:no merge 1:automatic merge ++// doublew_cfg0[31]; // 0:Y addr no change 1:Y addr divided to half ++#define VDEC2_MDEC_DOUBLEW_CFG0 (0x29db) ++#define P_VDEC2_MDEC_DOUBLEW_CFG0 (volatile unsigned int *)((0x29db << 2) + 0xff620000) ++// doublew_cfg1[7:0]; // [7:0] DMA Canvas Address for Luma ++// doublew_cfg1[15:8]; // [7:0] DMA Canvas Address for Chroma ++// doublew_cfg1[16]; // Disable 1st Write - ++// doublew_cfg1[17]; // Reverse to original version - ++// doublew_cfg1[18]; // DMA Address Mode - 0:Canvas Mode 1:Non-Canvas Mode ++#define VDEC2_MDEC_DOUBLEW_CFG1 (0x29dc) ++#define P_VDEC2_MDEC_DOUBLEW_CFG1 (volatile unsigned int *)((0x29dc << 2) + 0xff620000) ++// doublew_cfg2[11:0]; //[11:0] vertical flip initial value ++// doublew_cfg2[15]; // vertical flip enable ++// doublew_cfg2[24:16]; // [8:0] horizontal flip initial value ++// doublew_cfg2[31]; // horizontal flip enable ++#define VDEC2_MDEC_DOUBLEW_CFG2 (0x29dd) ++#define P_VDEC2_MDEC_DOUBLEW_CFG2 (volatile unsigned int *)((0x29dd << 2) + 0xff620000) ++// doublew_cfg3[31:0]; //[31:0] non-canvas start address for Luma - ++#define VDEC2_MDEC_DOUBLEW_CFG3 (0x29de) ++#define P_VDEC2_MDEC_DOUBLEW_CFG3 (volatile unsigned int *)((0x29de << 2) + 0xff620000) ++// doublew_cfg4[31:0]; //[31:0] non-canvas start address for Chroma - ++#define VDEC2_MDEC_DOUBLEW_CFG4 (0x29df) ++#define P_VDEC2_MDEC_DOUBLEW_CFG4 (volatile unsigned int *)((0x29df << 2) + 0xff620000) ++// doublew_cfg5[12:0]; //[12:0] non-canvas picture width for Luma - ++// doublew_cfg5[28:16]; //[12:0] non-canvas picture width for Chroma - ++#define VDEC2_MDEC_DOUBLEW_CFG5 (0x29e0) ++#define P_VDEC2_MDEC_DOUBLEW_CFG5 (volatile unsigned int *)((0x29e0 << 2) + 0xff620000) ++// doublew_cfg6: reserved ++#define VDEC2_MDEC_DOUBLEW_CFG6 (0x29e1) ++#define P_VDEC2_MDEC_DOUBLEW_CFG6 (volatile unsigned int *)((0x29e1 << 2) + 0xff620000) ++// doublew_cfg7: reserved ++#define VDEC2_MDEC_DOUBLEW_CFG7 (0x29e2) ++#define P_VDEC2_MDEC_DOUBLEW_CFG7 (volatile unsigned int *)((0x29e2 << 2) + 0xff620000) ++// doublew_status[11:0];//[11:0] wrrsp_count_doublew ++// doublew_status[12]; // doublew_status_busy ++// doublew_status[13]; // doublew_status_error ++#define VDEC2_MDEC_DOUBLEW_STATUS (0x29e3) ++#define P_VDEC2_MDEC_DOUBLEW_STATUS (volatile unsigned int *)((0x29e3 << 2) + 0xff620000) ++#define VDEC2_MDEC_EXTIF_CFG0 (0x29e4) ++#define P_VDEC2_MDEC_EXTIF_CFG0 (volatile unsigned int *)((0x29e4 << 2) + 0xff620000) ++#define VDEC2_MDEC_EXTIF_CFG1 (0x29e5) ++#define P_VDEC2_MDEC_EXTIF_CFG1 (volatile unsigned int *)((0x29e5 << 2) + 0xff620000) ++#define VDEC2_MDEC_EXTIF_STS0 (0x29e6) ++#define P_VDEC2_MDEC_EXTIF_STS0 (volatile unsigned int *)((0x29e6 << 2) + 0xff620000) ++//====================================== ++// MC Control Register Bits ++// ++//====================================== ++// For bits, just copy the defines...don't translate to addresses ++ //`define MC_RESET 16'h0002 ++//====================================== ++// MB Info Register Bits ++// ++//====================================== ++//====================================== ++// MB Info Register Bits ++// ++//====================================== ++//======================================================================== ++// DBLK Register: 12'h950 - 12'h97f ++//======================================================================== ++#define VDEC2_DBLK_RST (0x2950) ++#define P_VDEC2_DBLK_RST (volatile unsigned int *)((0x2950 << 2) + 0xff620000) ++#define VDEC2_DBLK_CTRL (0x2951) ++#define P_VDEC2_DBLK_CTRL (volatile unsigned int *)((0x2951 << 2) + 0xff620000) ++#define VDEC2_DBLK_MB_WID_HEIGHT (0x2952) ++#define P_VDEC2_DBLK_MB_WID_HEIGHT (volatile unsigned int *)((0x2952 << 2) + 0xff620000) ++#define VDEC2_DBLK_STATUS (0x2953) ++#define P_VDEC2_DBLK_STATUS (volatile unsigned int *)((0x2953 << 2) + 0xff620000) ++#define VDEC2_DBLK_CMD_CTRL (0x2954) ++#define P_VDEC2_DBLK_CMD_CTRL (volatile unsigned int *)((0x2954 << 2) + 0xff620000) ++#define VDEC2_DBLK_MB_XY (0x2955) ++#define P_VDEC2_DBLK_MB_XY (volatile unsigned int *)((0x2955 << 2) + 0xff620000) ++#define VDEC2_DBLK_QP (0x2956) ++#define P_VDEC2_DBLK_QP (volatile unsigned int *)((0x2956 << 2) + 0xff620000) ++#define VDEC2_DBLK_Y_BHFILT (0x2957) ++#define P_VDEC2_DBLK_Y_BHFILT (volatile unsigned int *)((0x2957 << 2) + 0xff620000) ++#define VDEC2_DBLK_Y_BHFILT_HIGH (0x2958) ++#define P_VDEC2_DBLK_Y_BHFILT_HIGH (volatile unsigned int *)((0x2958 << 2) + 0xff620000) ++#define VDEC2_DBLK_Y_BVFILT (0x2959) ++#define P_VDEC2_DBLK_Y_BVFILT (volatile unsigned int *)((0x2959 << 2) + 0xff620000) ++#define VDEC2_DBLK_CB_BFILT (0x295a) ++#define P_VDEC2_DBLK_CB_BFILT (volatile unsigned int *)((0x295a << 2) + 0xff620000) ++#define VDEC2_DBLK_CR_BFILT (0x295b) ++#define P_VDEC2_DBLK_CR_BFILT (volatile unsigned int *)((0x295b << 2) + 0xff620000) ++#define VDEC2_DBLK_Y_HFILT (0x295c) ++#define P_VDEC2_DBLK_Y_HFILT (volatile unsigned int *)((0x295c << 2) + 0xff620000) ++#define VDEC2_DBLK_Y_HFILT_HIGH (0x295d) ++#define P_VDEC2_DBLK_Y_HFILT_HIGH (volatile unsigned int *)((0x295d << 2) + 0xff620000) ++#define VDEC2_DBLK_Y_VFILT (0x295e) ++#define P_VDEC2_DBLK_Y_VFILT (volatile unsigned int *)((0x295e << 2) + 0xff620000) ++#define VDEC2_DBLK_CB_FILT (0x295f) ++#define P_VDEC2_DBLK_CB_FILT (volatile unsigned int *)((0x295f << 2) + 0xff620000) ++#define VDEC2_DBLK_CR_FILT (0x2960) ++#define P_VDEC2_DBLK_CR_FILT (volatile unsigned int *)((0x2960 << 2) + 0xff620000) ++#define VDEC2_DBLK_BETAX_QP_SEL (0x2961) ++#define P_VDEC2_DBLK_BETAX_QP_SEL (volatile unsigned int *)((0x2961 << 2) + 0xff620000) ++#define VDEC2_DBLK_CLIP_CTRL0 (0x2962) ++#define P_VDEC2_DBLK_CLIP_CTRL0 (volatile unsigned int *)((0x2962 << 2) + 0xff620000) ++#define VDEC2_DBLK_CLIP_CTRL1 (0x2963) ++#define P_VDEC2_DBLK_CLIP_CTRL1 (volatile unsigned int *)((0x2963 << 2) + 0xff620000) ++#define VDEC2_DBLK_CLIP_CTRL2 (0x2964) ++#define P_VDEC2_DBLK_CLIP_CTRL2 (volatile unsigned int *)((0x2964 << 2) + 0xff620000) ++#define VDEC2_DBLK_CLIP_CTRL3 (0x2965) ++#define P_VDEC2_DBLK_CLIP_CTRL3 (volatile unsigned int *)((0x2965 << 2) + 0xff620000) ++#define VDEC2_DBLK_CLIP_CTRL4 (0x2966) ++#define P_VDEC2_DBLK_CLIP_CTRL4 (volatile unsigned int *)((0x2966 << 2) + 0xff620000) ++#define VDEC2_DBLK_CLIP_CTRL5 (0x2967) ++#define P_VDEC2_DBLK_CLIP_CTRL5 (volatile unsigned int *)((0x2967 << 2) + 0xff620000) ++#define VDEC2_DBLK_CLIP_CTRL6 (0x2968) ++#define P_VDEC2_DBLK_CLIP_CTRL6 (volatile unsigned int *)((0x2968 << 2) + 0xff620000) ++#define VDEC2_DBLK_CLIP_CTRL7 (0x2969) ++#define P_VDEC2_DBLK_CLIP_CTRL7 (volatile unsigned int *)((0x2969 << 2) + 0xff620000) ++#define VDEC2_DBLK_CLIP_CTRL8 (0x296a) ++#define P_VDEC2_DBLK_CLIP_CTRL8 (volatile unsigned int *)((0x296a << 2) + 0xff620000) ++#define VDEC2_DBLK_STATUS1 (0x296b) ++#define P_VDEC2_DBLK_STATUS1 (volatile unsigned int *)((0x296b << 2) + 0xff620000) ++#define VDEC2_DBLK_GCLK_FREE (0x296c) ++#define P_VDEC2_DBLK_GCLK_FREE (volatile unsigned int *)((0x296c << 2) + 0xff620000) ++#define VDEC2_DBLK_GCLK_OFF (0x296d) ++#define P_VDEC2_DBLK_GCLK_OFF (volatile unsigned int *)((0x296d << 2) + 0xff620000) ++#define VDEC2_DBLK_AVSFLAGS (0x296e) ++#define P_VDEC2_DBLK_AVSFLAGS (volatile unsigned int *)((0x296e << 2) + 0xff620000) ++// bit 15:0 ++#define VDEC2_DBLK_CBPY (0x2970) ++#define P_VDEC2_DBLK_CBPY (volatile unsigned int *)((0x2970 << 2) + 0xff620000) ++// bit 11:8 -- deblk_cbpy_bottom ++// bit 7:4 -- deblk_cbpy_left ++// bit 3:0 -- deblk_cbpy_top ++#define VDEC2_DBLK_CBPY_ADJ (0x2971) ++#define P_VDEC2_DBLK_CBPY_ADJ (volatile unsigned int *)((0x2971 << 2) + 0xff620000) ++// bit 7:0 -- deblk_cbpc ++#define VDEC2_DBLK_CBPC (0x2972) ++#define P_VDEC2_DBLK_CBPC (volatile unsigned int *)((0x2972 << 2) + 0xff620000) ++// bit 15 -- bottom_mb ++// bit 14 -- left_mb ++// bit 13 -- top_mb ++// bit 12 -- reserved ++// bit 11:8 -- deblk_cbpc_bottom ++// bit 7:4 -- deblk_cbpc_left ++// bit 3:0 -- deblk_cbpc_top ++#define VDEC2_DBLK_CBPC_ADJ (0x2973) ++#define P_VDEC2_DBLK_CBPC_ADJ (volatile unsigned int *)((0x2973 << 2) + 0xff620000) ++// bit 15:8 -- deblk_hmvd -- {left_1, left_0, below_1, below_0, block3-0} ++// bit 7:0 -- deblk_vmvd -- {top_1, top_0, below_1, below_0, block3-0} ++#define VDEC2_DBLK_VHMVD (0x2974) ++#define P_VDEC2_DBLK_VHMVD (volatile unsigned int *)((0x2974 << 2) + 0xff620000) ++// bit 13:12 -- right_vmvd ++// bit 11 -- right_above_vmvd ++// bit 10 -- left_below_hmvd ++// bit 9 -- disable_dblk_luma ++// bit 8 -- disable_dblk_chroma ++// bit 7 -- bBelowRefDiff ++// bit 6 -- bLeftRefDiff ++// bit 5 -- bAboveRefDiff ++// bit 4 -- reserved ++// bit 3 -- s_below ++// bit 2 -- s_left ++// bit 1 -- s_above ++// bit 0 -- s ++#define VDEC2_DBLK_STRONG (0x2975) ++#define P_VDEC2_DBLK_STRONG (volatile unsigned int *)((0x2975 << 2) + 0xff620000) ++// bit 14:10 -- PQUANT ++// bit 9:5 -- left_PQUANT ++// bit 4:0 -- top_PQUANT ++#define VDEC2_DBLK_RV8_QUANT (0x2976) ++#define P_VDEC2_DBLK_RV8_QUANT (volatile unsigned int *)((0x2976 << 2) + 0xff620000) ++#define VDEC2_DBLK_CBUS_HCMD2 (0x2977) ++#define P_VDEC2_DBLK_CBUS_HCMD2 (volatile unsigned int *)((0x2977 << 2) + 0xff620000) ++#define VDEC2_DBLK_CBUS_HCMD1 (0x2978) ++#define P_VDEC2_DBLK_CBUS_HCMD1 (volatile unsigned int *)((0x2978 << 2) + 0xff620000) ++#define VDEC2_DBLK_CBUS_HCMD0 (0x2979) ++#define P_VDEC2_DBLK_CBUS_HCMD0 (volatile unsigned int *)((0x2979 << 2) + 0xff620000) ++#define VDEC2_DBLK_VLD_HCMD2 (0x297a) ++#define P_VDEC2_DBLK_VLD_HCMD2 (volatile unsigned int *)((0x297a << 2) + 0xff620000) ++#define VDEC2_DBLK_VLD_HCMD1 (0x297b) ++#define P_VDEC2_DBLK_VLD_HCMD1 (volatile unsigned int *)((0x297b << 2) + 0xff620000) ++#define VDEC2_DBLK_VLD_HCMD0 (0x297c) ++#define P_VDEC2_DBLK_VLD_HCMD0 (volatile unsigned int *)((0x297c << 2) + 0xff620000) ++#define VDEC2_DBLK_OST_YBASE (0x297d) ++#define P_VDEC2_DBLK_OST_YBASE (volatile unsigned int *)((0x297d << 2) + 0xff620000) ++#define VDEC2_DBLK_OST_CBCRDIFF (0x297e) ++#define P_VDEC2_DBLK_OST_CBCRDIFF (volatile unsigned int *)((0x297e << 2) + 0xff620000) ++//13:8 dblk thread ID and token ++//5:0 dblk prearbitor burst num ++#define VDEC2_DBLK_CTRL1 (0x297f) ++#define P_VDEC2_DBLK_CTRL1 (volatile unsigned int *)((0x297f << 2) + 0xff620000) ++// MCRCC_CTL1 ++// 31:3 ++// 2 ++// 1 ++// 0 ++#define VDEC2_MCRCC_CTL1 (0x2980) ++#define P_VDEC2_MCRCC_CTL1 (volatile unsigned int *)((0x2980 << 2) + 0xff620000) ++// MCRCC_CTL2 ++// 31:24 ++// 23:16 ++// 15:8 ++// 7:0 ++#define VDEC2_MCRCC_CTL2 (0x2981) ++#define P_VDEC2_MCRCC_CTL2 (volatile unsigned int *)((0x2981 << 2) + 0xff620000) ++// MCRCC_CTL3 ++// 31:24 ++// 23:16 ++// 15:8 ++// 7:0 ++#define VDEC2_MCRCC_CTL3 (0x2982) ++#define P_VDEC2_MCRCC_CTL3 (volatile unsigned int *)((0x2982 << 2) + 0xff620000) ++// bit[31:10] reserved ++// bit[9:0] sw_clock_gating control ++// [9] vdec clk_en for assist and cbus. ++// [8] vdec clk_en for ddr ++// [7] vdec clk_en for vcpu ++// [6] vdec clk_en for assist ++// [5] vdec clk_en for dblk ++// [4] vdec clk_en for iqidct ++// [3] vdec clk_en for mc ++// [2] vdec clk_en for pic_dc ++// [1] vdec clk_en for psc ++// [0] vdec clk_en for vld ++#define VDEC2_GCLK_EN (0x2983) ++#define P_VDEC2_GCLK_EN (volatile unsigned int *)((0x2983 << 2) + 0xff620000) ++// [0] Reserved ++// [1] Reserved ++// [2] Reset assist, mdec's CBUS ++// [3] Reset mdec's VLD ++// [4] Reset mdec's VLD ++// [5] Reset mdec's VLD ++// [6] Reset mdec's IQIDCT ++// [7] Reset mdec's MC ++// [8] Reset mdec's DBLK ++// [9] Reset mdec's PIC_DC ++// [10] Reset mdec's Pscale ++// [11] Reset vcpu's MCPU ++// [12] Reset vcpu's CCPU ++// [13] Reset mmc_pre_arb ++#define VDEC2_MDEC_SW_RESET (0x2984) ++#define P_VDEC2_MDEC_SW_RESET (volatile unsigned int *)((0x2984 << 2) + 0xff620000) ++//DBLK last address 12'h97f ++// ++// Closing file: mdec_regs.h ++// ++// ++// Reading file: mdec_regs.h ++// ++//======================================================================== ++// MDEC module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_VDEC_MDEC_CBUS_BASE = 0x09 ++// ----------------------------------------------- ++#define HEVC_MC_CTRL_REG (0x3900) ++#define P_HEVC_MC_CTRL_REG (volatile unsigned int *)((0x3900 << 2) + 0xff620000) ++#define HEVC_MC_MB_INFO (0x3901) ++#define P_HEVC_MC_MB_INFO (volatile unsigned int *)((0x3901 << 2) + 0xff620000) ++#define HEVC_MC_PIC_INFO (0x3902) ++#define P_HEVC_MC_PIC_INFO (volatile unsigned int *)((0x3902 << 2) + 0xff620000) ++#define HEVC_MC_HALF_PEL_ONE (0x3903) ++#define P_HEVC_MC_HALF_PEL_ONE (volatile unsigned int *)((0x3903 << 2) + 0xff620000) ++#define HEVC_MC_HALF_PEL_TWO (0x3904) ++#define P_HEVC_MC_HALF_PEL_TWO (volatile unsigned int *)((0x3904 << 2) + 0xff620000) ++#define HEVC_POWER_CTL_MC (0x3905) ++#define P_HEVC_POWER_CTL_MC (volatile unsigned int *)((0x3905 << 2) + 0xff620000) ++#define HEVC_MC_CMD (0x3906) ++#define P_HEVC_MC_CMD (volatile unsigned int *)((0x3906 << 2) + 0xff620000) ++#define HEVC_MC_CTRL0 (0x3907) ++#define P_HEVC_MC_CTRL0 (volatile unsigned int *)((0x3907 << 2) + 0xff620000) ++#define HEVC_MC_PIC_W_H (0x3908) ++#define P_HEVC_MC_PIC_W_H (volatile unsigned int *)((0x3908 << 2) + 0xff620000) ++#define HEVC_MC_STATUS0 (0x3909) ++#define P_HEVC_MC_STATUS0 (volatile unsigned int *)((0x3909 << 2) + 0xff620000) ++#define HEVC_MC_STATUS1 (0x390a) ++#define P_HEVC_MC_STATUS1 (volatile unsigned int *)((0x390a << 2) + 0xff620000) ++#define HEVC_MC_CTRL1 (0x390b) ++#define P_HEVC_MC_CTRL1 (volatile unsigned int *)((0x390b << 2) + 0xff620000) ++#define HEVC_MC_MIX_RATIO0 (0x390c) ++#define P_HEVC_MC_MIX_RATIO0 (volatile unsigned int *)((0x390c << 2) + 0xff620000) ++#define HEVC_MC_MIX_RATIO1 (0x390d) ++#define P_HEVC_MC_MIX_RATIO1 (volatile unsigned int *)((0x390d << 2) + 0xff620000) ++#define HEVC_MC_DP_MB_XY (0x390e) ++#define P_HEVC_MC_DP_MB_XY (volatile unsigned int *)((0x390e << 2) + 0xff620000) ++#define HEVC_MC_OM_MB_XY (0x390f) ++#define P_HEVC_MC_OM_MB_XY (volatile unsigned int *)((0x390f << 2) + 0xff620000) ++#define HEVC_PSCALE_RST (0x3910) ++#define P_HEVC_PSCALE_RST (volatile unsigned int *)((0x3910 << 2) + 0xff620000) ++#define HEVC_PSCALE_CTRL (0x3911) ++#define P_HEVC_PSCALE_CTRL (volatile unsigned int *)((0x3911 << 2) + 0xff620000) ++#define HEVC_PSCALE_PICI_W (0x3912) ++#define P_HEVC_PSCALE_PICI_W (volatile unsigned int *)((0x3912 << 2) + 0xff620000) ++#define HEVC_PSCALE_PICI_H (0x3913) ++#define P_HEVC_PSCALE_PICI_H (volatile unsigned int *)((0x3913 << 2) + 0xff620000) ++#define HEVC_PSCALE_PICO_W (0x3914) ++#define P_HEVC_PSCALE_PICO_W (volatile unsigned int *)((0x3914 << 2) + 0xff620000) ++#define HEVC_PSCALE_PICO_H (0x3915) ++#define P_HEVC_PSCALE_PICO_H (volatile unsigned int *)((0x3915 << 2) + 0xff620000) ++#define HEVC_PSCALE_PICO_START_X (0x3916) ++#define P_HEVC_PSCALE_PICO_START_X (volatile unsigned int *)((0x3916 << 2) + 0xff620000) ++#define HEVC_PSCALE_PICO_START_Y (0x3917) ++#define P_HEVC_PSCALE_PICO_START_Y (volatile unsigned int *)((0x3917 << 2) + 0xff620000) ++#define HEVC_PSCALE_DUMMY (0x3918) ++#define P_HEVC_PSCALE_DUMMY (volatile unsigned int *)((0x3918 << 2) + 0xff620000) ++#define HEVC_PSCALE_FILT0_COEF0 (0x3919) ++#define P_HEVC_PSCALE_FILT0_COEF0 (volatile unsigned int *)((0x3919 << 2) + 0xff620000) ++#define HEVC_PSCALE_FILT0_COEF1 (0x391a) ++#define P_HEVC_PSCALE_FILT0_COEF1 (volatile unsigned int *)((0x391a << 2) + 0xff620000) ++#define HEVC_PSCALE_CMD_CTRL (0x391b) ++#define P_HEVC_PSCALE_CMD_CTRL (volatile unsigned int *)((0x391b << 2) + 0xff620000) ++#define HEVC_PSCALE_CMD_BLK_X (0x391c) ++#define P_HEVC_PSCALE_CMD_BLK_X (volatile unsigned int *)((0x391c << 2) + 0xff620000) ++#define HEVC_PSCALE_CMD_BLK_Y (0x391d) ++#define P_HEVC_PSCALE_CMD_BLK_Y (volatile unsigned int *)((0x391d << 2) + 0xff620000) ++#define HEVC_PSCALE_STATUS (0x391e) ++#define P_HEVC_PSCALE_STATUS (volatile unsigned int *)((0x391e << 2) + 0xff620000) ++#define HEVC_PSCALE_BMEM_ADDR (0x391f) ++#define P_HEVC_PSCALE_BMEM_ADDR (volatile unsigned int *)((0x391f << 2) + 0xff620000) ++#define HEVC_PSCALE_BMEM_DAT (0x3920) ++#define P_HEVC_PSCALE_BMEM_DAT (volatile unsigned int *)((0x3920 << 2) + 0xff620000) ++#define HEVC_PSCALE_DRAM_BUF_CTRL (0x3921) ++#define P_HEVC_PSCALE_DRAM_BUF_CTRL (volatile unsigned int *)((0x3921 << 2) + 0xff620000) ++#define HEVC_PSCALE_MCMD_CTRL (0x3922) ++#define P_HEVC_PSCALE_MCMD_CTRL (volatile unsigned int *)((0x3922 << 2) + 0xff620000) ++#define HEVC_PSCALE_MCMD_XSIZE (0x3923) ++#define P_HEVC_PSCALE_MCMD_XSIZE (volatile unsigned int *)((0x3923 << 2) + 0xff620000) ++#define HEVC_PSCALE_MCMD_YSIZE (0x3924) ++#define P_HEVC_PSCALE_MCMD_YSIZE (volatile unsigned int *)((0x3924 << 2) + 0xff620000) ++#define HEVC_PSCALE_RBUF_START_BLKX (0x3925) ++#define P_HEVC_PSCALE_RBUF_START_BLKX (volatile unsigned int *)((0x3925 << 2) + 0xff620000) ++#define HEVC_PSCALE_RBUF_START_BLKY (0x3926) ++#define P_HEVC_PSCALE_RBUF_START_BLKY (volatile unsigned int *)((0x3926 << 2) + 0xff620000) ++//`define PSCALE_RBUF_MB_WIDTH 8'h27 ++#define HEVC_PSCALE_PICO_SHIFT_XY (0x3928) ++#define P_HEVC_PSCALE_PICO_SHIFT_XY (volatile unsigned int *)((0x3928 << 2) + 0xff620000) ++#define HEVC_PSCALE_CTRL1 (0x3929) ++#define P_HEVC_PSCALE_CTRL1 (volatile unsigned int *)((0x3929 << 2) + 0xff620000) ++//Bit 15, wmask enable ++//Bit 14:13, filt0 srckey_less, ++//Bit 12:11, filt1 srckey_less, in the case of the interpolated data is equal distance to ++//key data and normal data, 00: select normal data, 01: select right data, 10: select key data ++//Bit 10:9, srckey mode, 00: equal, 01: less than or equal, 10: great than or equal ++//Bit 8, src key enable ++//Bit 7:0, y src key ++#define HEVC_PSCALE_SRCKEY_CTRL0 (0x392a) ++#define P_HEVC_PSCALE_SRCKEY_CTRL0 (volatile unsigned int *)((0x392a << 2) + 0xff620000) ++//Bit 15:8, cb src key ++//Bit 7:0, cr src key ++#define HEVC_PSCALE_SRCKEY_CTRL1 (0x392b) ++#define P_HEVC_PSCALE_SRCKEY_CTRL1 (volatile unsigned int *)((0x392b << 2) + 0xff620000) ++//Bit 22:16 canvas_rd_addr2 ++//Bit 14:8 canvas_rd_addr1 ++//Bit 6:0 canvas_rd_addr1 ++#define HEVC_PSCALE_CANVAS_RD_ADDR (0x392c) ++#define P_HEVC_PSCALE_CANVAS_RD_ADDR (volatile unsigned int *)((0x392c << 2) + 0xff620000) ++//Bit 22:16 canvas_wr_addr2 ++//Bit 14:8 canvas_wr_addr1 ++//Bit 6:0 canvas_wr_addr1 ++#define HEVC_PSCALE_CANVAS_WR_ADDR (0x392d) ++#define P_HEVC_PSCALE_CANVAS_WR_ADDR (volatile unsigned int *)((0x392d << 2) + 0xff620000) ++//bit 13:8 pscale thread ID and token ++//bit 7 disable write response count adding to busy bit ++//bit 5:0 pscale prearbitor burst num ++#define HEVC_PSCALE_CTRL2 (0x392e) ++#define P_HEVC_PSCALE_CTRL2 (volatile unsigned int *)((0x392e << 2) + 0xff620000) ++// 31 - use_omem_mb_xy_auto ++//23:16 - omem_max_mb_x ++//15:8 - omem_mb_y_auto ++// 7:0 - omem_mb_x_auto ++#define HEVC_HDEC_MC_OMEM_AUTO (0x3930) ++#define P_HEVC_HDEC_MC_OMEM_AUTO (volatile unsigned int *)((0x3930 << 2) + 0xff620000) ++#define HEVC_HDEC_MC_MBRIGHT_IDX (0x3931) ++#define P_HEVC_HDEC_MC_MBRIGHT_IDX (volatile unsigned int *)((0x3931 << 2) + 0xff620000) ++#define HEVC_HDEC_MC_MBRIGHT_RD (0x3932) ++#define P_HEVC_HDEC_MC_MBRIGHT_RD (volatile unsigned int *)((0x3932 << 2) + 0xff620000) ++#define HEVC_MC_MPORT_CTRL (0x3940) ++#define P_HEVC_MC_MPORT_CTRL (volatile unsigned int *)((0x3940 << 2) + 0xff620000) ++#define HEVC_MC_MPORT_DAT (0x3941) ++#define P_HEVC_MC_MPORT_DAT (volatile unsigned int *)((0x3941 << 2) + 0xff620000) ++#define HEVC_MC_WT_PRED_CTRL (0x3942) ++#define P_HEVC_MC_WT_PRED_CTRL (volatile unsigned int *)((0x3942 << 2) + 0xff620000) ++#define HEVC_MC_MBBOT_ST_EVEN_ADDR (0x3944) ++#define P_HEVC_MC_MBBOT_ST_EVEN_ADDR (volatile unsigned int *)((0x3944 << 2) + 0xff620000) ++#define HEVC_MC_MBBOT_ST_ODD_ADDR (0x3945) ++#define P_HEVC_MC_MBBOT_ST_ODD_ADDR (volatile unsigned int *)((0x3945 << 2) + 0xff620000) ++#define HEVC_MC_DPDN_MB_XY (0x3946) ++#define P_HEVC_MC_DPDN_MB_XY (volatile unsigned int *)((0x3946 << 2) + 0xff620000) ++#define HEVC_MC_OMDN_MB_XY (0x3947) ++#define P_HEVC_MC_OMDN_MB_XY (volatile unsigned int *)((0x3947 << 2) + 0xff620000) ++#define HEVC_MC_HCMDBUF_H (0x3948) ++#define P_HEVC_MC_HCMDBUF_H (volatile unsigned int *)((0x3948 << 2) + 0xff620000) ++#define HEVC_MC_HCMDBUF_L (0x3949) ++#define P_HEVC_MC_HCMDBUF_L (volatile unsigned int *)((0x3949 << 2) + 0xff620000) ++#define HEVC_MC_HCMD_H (0x394a) ++#define P_HEVC_MC_HCMD_H (volatile unsigned int *)((0x394a << 2) + 0xff620000) ++#define HEVC_MC_HCMD_L (0x394b) ++#define P_HEVC_MC_HCMD_L (volatile unsigned int *)((0x394b << 2) + 0xff620000) ++#define HEVC_MC_IDCT_DAT (0x394c) ++#define P_HEVC_MC_IDCT_DAT (volatile unsigned int *)((0x394c << 2) + 0xff620000) ++#define HEVC_MC_CTRL_GCLK_CTRL (0x394d) ++#define P_HEVC_MC_CTRL_GCLK_CTRL (volatile unsigned int *)((0x394d << 2) + 0xff620000) ++#define HEVC_MC_OTHER_GCLK_CTRL (0x394e) ++#define P_HEVC_MC_OTHER_GCLK_CTRL (volatile unsigned int *)((0x394e << 2) + 0xff620000) ++//Bit 29:24, mbbot thread ID and token ++//Bit 21:16, mc read/write thread ID and token ++//Bit 13:8, mbbot pre-arbitor burst number ++//Bit 5:0, mc pre-arbitor burst number ++#define HEVC_MC_CTRL2 (0x394f) ++#define P_HEVC_MC_CTRL2 (volatile unsigned int *)((0x394f << 2) + 0xff620000) ++// `define DBLK_QUANT 8'h76 // ONLY for $ucode/real/amrisc/rv.s, reg value from apollo ++//`define ANC1_CANVAS_ADDR 8'h80 ++//`define ANC2_CANVAS_ADDR 8'h81 ++//`define REC_CANVAS_ADDR 8'h89 ++//`define MDEC_PIC_W 8'h8c ++//`define MDEC_PIC_H 8'h8d ++// mdec_pic_dc_mux_ctrl[31] -- mcr_hevc_mode ++#define HEVC_MDEC_PIC_DC_MUX_CTRL (0x398d) ++#define P_HEVC_MDEC_PIC_DC_MUX_CTRL (volatile unsigned int *)((0x398d << 2) + 0xff620000) ++#define HEVC_MDEC_PIC_DC_CTRL (0x398e) ++#define P_HEVC_MDEC_PIC_DC_CTRL (volatile unsigned int *)((0x398e << 2) + 0xff620000) ++#define HEVC_MDEC_PIC_DC_STATUS (0x398f) ++#define P_HEVC_MDEC_PIC_DC_STATUS (volatile unsigned int *)((0x398f << 2) + 0xff620000) ++#define HEVC_ANC0_CANVAS_ADDR (0x3990) ++#define P_HEVC_ANC0_CANVAS_ADDR (volatile unsigned int *)((0x3990 << 2) + 0xff620000) ++#define HEVC_ANC1_CANVAS_ADDR (0x3991) ++#define P_HEVC_ANC1_CANVAS_ADDR (volatile unsigned int *)((0x3991 << 2) + 0xff620000) ++#define HEVC_ANC2_CANVAS_ADDR (0x3992) ++#define P_HEVC_ANC2_CANVAS_ADDR (volatile unsigned int *)((0x3992 << 2) + 0xff620000) ++#define HEVC_ANC3_CANVAS_ADDR (0x3993) ++#define P_HEVC_ANC3_CANVAS_ADDR (volatile unsigned int *)((0x3993 << 2) + 0xff620000) ++#define HEVC_ANC4_CANVAS_ADDR (0x3994) ++#define P_HEVC_ANC4_CANVAS_ADDR (volatile unsigned int *)((0x3994 << 2) + 0xff620000) ++#define HEVC_ANC5_CANVAS_ADDR (0x3995) ++#define P_HEVC_ANC5_CANVAS_ADDR (volatile unsigned int *)((0x3995 << 2) + 0xff620000) ++#define HEVC_ANC6_CANVAS_ADDR (0x3996) ++#define P_HEVC_ANC6_CANVAS_ADDR (volatile unsigned int *)((0x3996 << 2) + 0xff620000) ++#define HEVC_ANC7_CANVAS_ADDR (0x3997) ++#define P_HEVC_ANC7_CANVAS_ADDR (volatile unsigned int *)((0x3997 << 2) + 0xff620000) ++#define HEVC_ANC8_CANVAS_ADDR (0x3998) ++#define P_HEVC_ANC8_CANVAS_ADDR (volatile unsigned int *)((0x3998 << 2) + 0xff620000) ++#define HEVC_ANC9_CANVAS_ADDR (0x3999) ++#define P_HEVC_ANC9_CANVAS_ADDR (volatile unsigned int *)((0x3999 << 2) + 0xff620000) ++#define HEVC_ANC10_CANVAS_ADDR (0x399a) ++#define P_HEVC_ANC10_CANVAS_ADDR (volatile unsigned int *)((0x399a << 2) + 0xff620000) ++#define HEVC_ANC11_CANVAS_ADDR (0x399b) ++#define P_HEVC_ANC11_CANVAS_ADDR (volatile unsigned int *)((0x399b << 2) + 0xff620000) ++#define HEVC_ANC12_CANVAS_ADDR (0x399c) ++#define P_HEVC_ANC12_CANVAS_ADDR (volatile unsigned int *)((0x399c << 2) + 0xff620000) ++#define HEVC_ANC13_CANVAS_ADDR (0x399d) ++#define P_HEVC_ANC13_CANVAS_ADDR (volatile unsigned int *)((0x399d << 2) + 0xff620000) ++#define HEVC_ANC14_CANVAS_ADDR (0x399e) ++#define P_HEVC_ANC14_CANVAS_ADDR (volatile unsigned int *)((0x399e << 2) + 0xff620000) ++#define HEVC_ANC15_CANVAS_ADDR (0x399f) ++#define P_HEVC_ANC15_CANVAS_ADDR (volatile unsigned int *)((0x399f << 2) + 0xff620000) ++#define HEVC_ANC16_CANVAS_ADDR (0x39a0) ++#define P_HEVC_ANC16_CANVAS_ADDR (volatile unsigned int *)((0x39a0 << 2) + 0xff620000) ++#define HEVC_ANC17_CANVAS_ADDR (0x39a1) ++#define P_HEVC_ANC17_CANVAS_ADDR (volatile unsigned int *)((0x39a1 << 2) + 0xff620000) ++#define HEVC_ANC18_CANVAS_ADDR (0x39a2) ++#define P_HEVC_ANC18_CANVAS_ADDR (volatile unsigned int *)((0x39a2 << 2) + 0xff620000) ++#define HEVC_ANC19_CANVAS_ADDR (0x39a3) ++#define P_HEVC_ANC19_CANVAS_ADDR (volatile unsigned int *)((0x39a3 << 2) + 0xff620000) ++#define HEVC_ANC20_CANVAS_ADDR (0x39a4) ++#define P_HEVC_ANC20_CANVAS_ADDR (volatile unsigned int *)((0x39a4 << 2) + 0xff620000) ++#define HEVC_ANC21_CANVAS_ADDR (0x39a5) ++#define P_HEVC_ANC21_CANVAS_ADDR (volatile unsigned int *)((0x39a5 << 2) + 0xff620000) ++#define HEVC_ANC22_CANVAS_ADDR (0x39a6) ++#define P_HEVC_ANC22_CANVAS_ADDR (volatile unsigned int *)((0x39a6 << 2) + 0xff620000) ++#define HEVC_ANC23_CANVAS_ADDR (0x39a7) ++#define P_HEVC_ANC23_CANVAS_ADDR (volatile unsigned int *)((0x39a7 << 2) + 0xff620000) ++#define HEVC_ANC24_CANVAS_ADDR (0x39a8) ++#define P_HEVC_ANC24_CANVAS_ADDR (volatile unsigned int *)((0x39a8 << 2) + 0xff620000) ++#define HEVC_ANC25_CANVAS_ADDR (0x39a9) ++#define P_HEVC_ANC25_CANVAS_ADDR (volatile unsigned int *)((0x39a9 << 2) + 0xff620000) ++#define HEVC_ANC26_CANVAS_ADDR (0x39aa) ++#define P_HEVC_ANC26_CANVAS_ADDR (volatile unsigned int *)((0x39aa << 2) + 0xff620000) ++#define HEVC_ANC27_CANVAS_ADDR (0x39ab) ++#define P_HEVC_ANC27_CANVAS_ADDR (volatile unsigned int *)((0x39ab << 2) + 0xff620000) ++#define HEVC_ANC28_CANVAS_ADDR (0x39ac) ++#define P_HEVC_ANC28_CANVAS_ADDR (volatile unsigned int *)((0x39ac << 2) + 0xff620000) ++#define HEVC_ANC29_CANVAS_ADDR (0x39ad) ++#define P_HEVC_ANC29_CANVAS_ADDR (volatile unsigned int *)((0x39ad << 2) + 0xff620000) ++#define HEVC_ANC30_CANVAS_ADDR (0x39ae) ++#define P_HEVC_ANC30_CANVAS_ADDR (volatile unsigned int *)((0x39ae << 2) + 0xff620000) ++#define HEVC_ANC31_CANVAS_ADDR (0x39af) ++#define P_HEVC_ANC31_CANVAS_ADDR (volatile unsigned int *)((0x39af << 2) + 0xff620000) ++#define HEVC_DBKR_CANVAS_ADDR (0x39b0) ++#define P_HEVC_DBKR_CANVAS_ADDR (volatile unsigned int *)((0x39b0 << 2) + 0xff620000) ++#define HEVC_DBKW_CANVAS_ADDR (0x39b1) ++#define P_HEVC_DBKW_CANVAS_ADDR (volatile unsigned int *)((0x39b1 << 2) + 0xff620000) ++#define HEVC_REC_CANVAS_ADDR (0x39b2) ++#define P_HEVC_REC_CANVAS_ADDR (volatile unsigned int *)((0x39b2 << 2) + 0xff620000) ++//28:24, read/write, current canvas idx, used in h264 only now ++//23:0, read only, current canvas address, 23:16, Cr canvas addr, 15:8, Cb canvas addr, 7:0, Y canvas addr ++#define HEVC_CURR_CANVAS_CTRL (0x39b3) ++#define P_HEVC_CURR_CANVAS_CTRL (volatile unsigned int *)((0x39b3 << 2) + 0xff620000) ++#define HEVC_MDEC_PIC_DC_THRESH (0x39b8) ++#define P_HEVC_MDEC_PIC_DC_THRESH (volatile unsigned int *)((0x39b8 << 2) + 0xff620000) ++#define HEVC_MDEC_PICR_BUF_STATUS (0x39b9) ++#define P_HEVC_MDEC_PICR_BUF_STATUS (volatile unsigned int *)((0x39b9 << 2) + 0xff620000) ++#define HEVC_MDEC_PICW_BUF_STATUS (0x39ba) ++#define P_HEVC_MDEC_PICW_BUF_STATUS (volatile unsigned int *)((0x39ba << 2) + 0xff620000) ++#define HEVC_MCW_DBLK_WRRSP_CNT (0x39bb) ++#define P_HEVC_MCW_DBLK_WRRSP_CNT (volatile unsigned int *)((0x39bb << 2) + 0xff620000) ++#define HEVC_MC_MBBOT_WRRSP_CNT (0x39bc) ++#define P_HEVC_MC_MBBOT_WRRSP_CNT (volatile unsigned int *)((0x39bc << 2) + 0xff620000) ++#define HEVC_MDEC_PICW_BUF2_STATUS (0x39bd) ++#define P_HEVC_MDEC_PICW_BUF2_STATUS (volatile unsigned int *)((0x39bd << 2) + 0xff620000) ++#define HEVC_WRRSP_FIFO_PICW_DBK (0x39be) ++#define P_HEVC_WRRSP_FIFO_PICW_DBK (volatile unsigned int *)((0x39be << 2) + 0xff620000) ++#define HEVC_WRRSP_FIFO_PICW_MC (0x39bf) ++#define P_HEVC_WRRSP_FIFO_PICW_MC (volatile unsigned int *)((0x39bf << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_0 (0x39c0) ++#define P_HEVC_AV_SCRATCH_0 (volatile unsigned int *)((0x39c0 << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_1 (0x39c1) ++#define P_HEVC_AV_SCRATCH_1 (volatile unsigned int *)((0x39c1 << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_2 (0x39c2) ++#define P_HEVC_AV_SCRATCH_2 (volatile unsigned int *)((0x39c2 << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_3 (0x39c3) ++#define P_HEVC_AV_SCRATCH_3 (volatile unsigned int *)((0x39c3 << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_4 (0x39c4) ++#define P_HEVC_AV_SCRATCH_4 (volatile unsigned int *)((0x39c4 << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_5 (0x39c5) ++#define P_HEVC_AV_SCRATCH_5 (volatile unsigned int *)((0x39c5 << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_6 (0x39c6) ++#define P_HEVC_AV_SCRATCH_6 (volatile unsigned int *)((0x39c6 << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_7 (0x39c7) ++#define P_HEVC_AV_SCRATCH_7 (volatile unsigned int *)((0x39c7 << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_8 (0x39c8) ++#define P_HEVC_AV_SCRATCH_8 (volatile unsigned int *)((0x39c8 << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_9 (0x39c9) ++#define P_HEVC_AV_SCRATCH_9 (volatile unsigned int *)((0x39c9 << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_A (0x39ca) ++#define P_HEVC_AV_SCRATCH_A (volatile unsigned int *)((0x39ca << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_B (0x39cb) ++#define P_HEVC_AV_SCRATCH_B (volatile unsigned int *)((0x39cb << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_C (0x39cc) ++#define P_HEVC_AV_SCRATCH_C (volatile unsigned int *)((0x39cc << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_D (0x39cd) ++#define P_HEVC_AV_SCRATCH_D (volatile unsigned int *)((0x39cd << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_E (0x39ce) ++#define P_HEVC_AV_SCRATCH_E (volatile unsigned int *)((0x39ce << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_F (0x39cf) ++#define P_HEVC_AV_SCRATCH_F (volatile unsigned int *)((0x39cf << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_G (0x39d0) ++#define P_HEVC_AV_SCRATCH_G (volatile unsigned int *)((0x39d0 << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_H (0x39d1) ++#define P_HEVC_AV_SCRATCH_H (volatile unsigned int *)((0x39d1 << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_I (0x39d2) ++#define P_HEVC_AV_SCRATCH_I (volatile unsigned int *)((0x39d2 << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_J (0x39d3) ++#define P_HEVC_AV_SCRATCH_J (volatile unsigned int *)((0x39d3 << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_K (0x39d4) ++#define P_HEVC_AV_SCRATCH_K (volatile unsigned int *)((0x39d4 << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_L (0x39d5) ++#define P_HEVC_AV_SCRATCH_L (volatile unsigned int *)((0x39d5 << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_M (0x39d6) ++#define P_HEVC_AV_SCRATCH_M (volatile unsigned int *)((0x39d6 << 2) + 0xff620000) ++#define HEVC_AV_SCRATCH_N (0x39d7) ++#define P_HEVC_AV_SCRATCH_N (volatile unsigned int *)((0x39d7 << 2) + 0xff620000) ++// bit[29:24] A_brst_num_co_mb ++// bit[21:16] A_id_co_mb ++// bit[11:0] wrrsp_count_co_mb ++#define HEVC_WRRSP_CO_MB (0x39d8) ++#define P_HEVC_WRRSP_CO_MB (volatile unsigned int *)((0x39d8 << 2) + 0xff620000) ++// bit[29:24] A_brst_num_dcac ++// bit[21:16] A_id_dcac ++// bit[11:0] wrrsp_count_dcac ++#define HEVC_WRRSP_DCAC (0x39d9) ++#define P_HEVC_WRRSP_DCAC (volatile unsigned int *)((0x39d9 << 2) + 0xff620000) ++// bit[11:0] wrrsp_count_vld ++#define HEVC_WRRSP_VLD (0x39da) ++#define P_HEVC_WRRSP_VLD (volatile unsigned int *)((0x39da << 2) + 0xff620000) ++// doublew_cfg0[0]; // Second Channel Enable, 1:Enable 0:Disable ++// doublew_cfg0[3:1]; // [2:0] Endian Control for Luma ++// doublew_cfg0[5:4]; // [1:0] Pixel sel by horizontal, 0x:1/2 10:left 11:right ++// doublew_cfg0[7:6]; // [1:0] Pixel sel by vertical, 0x:1/2 10:up 11:down ++// doublew_cfg0[8]; // Size by horizontal, 0:original size 1: 1/2 shrunken size ++// doublew_cfg0[9]; // Size by vertical, 0:original size 1: 1/2 shrunken size ++// doublew_cfg0[10]; // 1:Round 0:Truncation ++// doublew_cfg0[11]; // DMA Urgent ++// doublew_cfg0[17:12]; // [5:0] DMA Burst Number ++// doublew_cfg0[23:18]; // [5:0] DMA ID ++// doublew_cfg0[26:24]; // [2:0] Endian Control for Chroma ++// doublew_cfg0[27]; // Source from, 1:MCW 0:DBLK ++// doublew_cfg0[29:28]; // [1:0] 0x:select both top and bottom 10:select top 11:select bottom ++// doublew_cfg0[30]; // 0:no merge 1:automatic merge ++// doublew_cfg0[31]; // 0:Y addr no change 1:Y addr divided to half ++#define HEVC_MDEC_DOUBLEW_CFG0 (0x39db) ++#define P_HEVC_MDEC_DOUBLEW_CFG0 (volatile unsigned int *)((0x39db << 2) + 0xff620000) ++// doublew_cfg1[7:0]; // [7:0] DMA Canvas Address for Luma ++// doublew_cfg1[15:8]; // [7:0] DMA Canvas Address for Chroma ++// doublew_cfg1[16]; // Disable 1st Write - ++// doublew_cfg1[17]; // Reverse to original version - ++// doublew_cfg1[18]; // DMA Address Mode - 0:Canvas Mode 1:Non-Canvas Mode ++#define HEVC_MDEC_DOUBLEW_CFG1 (0x39dc) ++#define P_HEVC_MDEC_DOUBLEW_CFG1 (volatile unsigned int *)((0x39dc << 2) + 0xff620000) ++// doublew_cfg2[11:0]; //[11:0] vertical flip initial value ++// doublew_cfg2[15]; // vertical flip enable ++// doublew_cfg2[24:16]; // [8:0] horizontal flip initial value ++// doublew_cfg2[31]; // horizontal flip enable ++#define HEVC_MDEC_DOUBLEW_CFG2 (0x39dd) ++#define P_HEVC_MDEC_DOUBLEW_CFG2 (volatile unsigned int *)((0x39dd << 2) + 0xff620000) ++// doublew_cfg3[31:0]; //[31:0] non-canvas start address for Luma - ++#define HEVC_MDEC_DOUBLEW_CFG3 (0x39de) ++#define P_HEVC_MDEC_DOUBLEW_CFG3 (volatile unsigned int *)((0x39de << 2) + 0xff620000) ++// doublew_cfg4[31:0]; //[31:0] non-canvas start address for Chroma - ++#define HEVC_MDEC_DOUBLEW_CFG4 (0x39df) ++#define P_HEVC_MDEC_DOUBLEW_CFG4 (volatile unsigned int *)((0x39df << 2) + 0xff620000) ++// doublew_cfg5[12:0]; //[12:0] non-canvas picture width for Luma - ++// doublew_cfg5[28:16]; //[12:0] non-canvas picture width for Chroma - ++#define HEVC_MDEC_DOUBLEW_CFG5 (0x39e0) ++#define P_HEVC_MDEC_DOUBLEW_CFG5 (volatile unsigned int *)((0x39e0 << 2) + 0xff620000) ++// doublew_cfg6: reserved ++#define HEVC_MDEC_DOUBLEW_CFG6 (0x39e1) ++#define P_HEVC_MDEC_DOUBLEW_CFG6 (volatile unsigned int *)((0x39e1 << 2) + 0xff620000) ++// doublew_cfg7: reserved ++#define HEVC_MDEC_DOUBLEW_CFG7 (0x39e2) ++#define P_HEVC_MDEC_DOUBLEW_CFG7 (volatile unsigned int *)((0x39e2 << 2) + 0xff620000) ++// doublew_status[11:0];//[11:0] wrrsp_count_doublew ++// doublew_status[12]; // doublew_status_busy ++// doublew_status[13]; // doublew_status_error ++#define HEVC_MDEC_DOUBLEW_STATUS (0x39e3) ++#define P_HEVC_MDEC_DOUBLEW_STATUS (volatile unsigned int *)((0x39e3 << 2) + 0xff620000) ++#define HEVC_MDEC_EXTIF_CFG0 (0x39e4) ++#define P_HEVC_MDEC_EXTIF_CFG0 (volatile unsigned int *)((0x39e4 << 2) + 0xff620000) ++#define HEVC_MDEC_EXTIF_CFG1 (0x39e5) ++#define P_HEVC_MDEC_EXTIF_CFG1 (volatile unsigned int *)((0x39e5 << 2) + 0xff620000) ++#define HEVC_MDEC_EXTIF_STS0 (0x39e6) ++#define P_HEVC_MDEC_EXTIF_STS0 (volatile unsigned int *)((0x39e6 << 2) + 0xff620000) ++//====================================== ++// MC Control Register Bits ++// ++//====================================== ++// For bits, just copy the defines...don't translate to addresses ++ //`define MC_RESET 16'h0002 ++//====================================== ++// MB Info Register Bits ++// ++//====================================== ++//====================================== ++// MB Info Register Bits ++// ++//====================================== ++//======================================================================== ++// DBLK Register: 12'h950 - 12'h97f ++//======================================================================== ++#define HEVC_DBLK_RST (0x3950) ++#define P_HEVC_DBLK_RST (volatile unsigned int *)((0x3950 << 2) + 0xff620000) ++#define HEVC_DBLK_CTRL (0x3951) ++#define P_HEVC_DBLK_CTRL (volatile unsigned int *)((0x3951 << 2) + 0xff620000) ++#define HEVC_DBLK_MB_WID_HEIGHT (0x3952) ++#define P_HEVC_DBLK_MB_WID_HEIGHT (volatile unsigned int *)((0x3952 << 2) + 0xff620000) ++#define HEVC_DBLK_STATUS (0x3953) ++#define P_HEVC_DBLK_STATUS (volatile unsigned int *)((0x3953 << 2) + 0xff620000) ++#define HEVC_DBLK_CMD_CTRL (0x3954) ++#define P_HEVC_DBLK_CMD_CTRL (volatile unsigned int *)((0x3954 << 2) + 0xff620000) ++#define HEVC_DBLK_MB_XY (0x3955) ++#define P_HEVC_DBLK_MB_XY (volatile unsigned int *)((0x3955 << 2) + 0xff620000) ++#define HEVC_DBLK_QP (0x3956) ++#define P_HEVC_DBLK_QP (volatile unsigned int *)((0x3956 << 2) + 0xff620000) ++#define HEVC_DBLK_Y_BHFILT (0x3957) ++#define P_HEVC_DBLK_Y_BHFILT (volatile unsigned int *)((0x3957 << 2) + 0xff620000) ++#define HEVC_DBLK_Y_BHFILT_HIGH (0x3958) ++#define P_HEVC_DBLK_Y_BHFILT_HIGH (volatile unsigned int *)((0x3958 << 2) + 0xff620000) ++#define HEVC_DBLK_Y_BVFILT (0x3959) ++#define P_HEVC_DBLK_Y_BVFILT (volatile unsigned int *)((0x3959 << 2) + 0xff620000) ++#define HEVC_DBLK_CB_BFILT (0x395a) ++#define P_HEVC_DBLK_CB_BFILT (volatile unsigned int *)((0x395a << 2) + 0xff620000) ++#define HEVC_DBLK_CR_BFILT (0x395b) ++#define P_HEVC_DBLK_CR_BFILT (volatile unsigned int *)((0x395b << 2) + 0xff620000) ++#define HEVC_DBLK_Y_HFILT (0x395c) ++#define P_HEVC_DBLK_Y_HFILT (volatile unsigned int *)((0x395c << 2) + 0xff620000) ++#define HEVC_DBLK_Y_HFILT_HIGH (0x395d) ++#define P_HEVC_DBLK_Y_HFILT_HIGH (volatile unsigned int *)((0x395d << 2) + 0xff620000) ++#define HEVC_DBLK_Y_VFILT (0x395e) ++#define P_HEVC_DBLK_Y_VFILT (volatile unsigned int *)((0x395e << 2) + 0xff620000) ++#define HEVC_DBLK_CB_FILT (0x395f) ++#define P_HEVC_DBLK_CB_FILT (volatile unsigned int *)((0x395f << 2) + 0xff620000) ++#define HEVC_DBLK_CR_FILT (0x3960) ++#define P_HEVC_DBLK_CR_FILT (volatile unsigned int *)((0x3960 << 2) + 0xff620000) ++#define HEVC_DBLK_BETAX_QP_SEL (0x3961) ++#define P_HEVC_DBLK_BETAX_QP_SEL (volatile unsigned int *)((0x3961 << 2) + 0xff620000) ++#define HEVC_DBLK_CLIP_CTRL0 (0x3962) ++#define P_HEVC_DBLK_CLIP_CTRL0 (volatile unsigned int *)((0x3962 << 2) + 0xff620000) ++#define HEVC_DBLK_CLIP_CTRL1 (0x3963) ++#define P_HEVC_DBLK_CLIP_CTRL1 (volatile unsigned int *)((0x3963 << 2) + 0xff620000) ++#define HEVC_DBLK_CLIP_CTRL2 (0x3964) ++#define P_HEVC_DBLK_CLIP_CTRL2 (volatile unsigned int *)((0x3964 << 2) + 0xff620000) ++#define HEVC_DBLK_CLIP_CTRL3 (0x3965) ++#define P_HEVC_DBLK_CLIP_CTRL3 (volatile unsigned int *)((0x3965 << 2) + 0xff620000) ++#define HEVC_DBLK_CLIP_CTRL4 (0x3966) ++#define P_HEVC_DBLK_CLIP_CTRL4 (volatile unsigned int *)((0x3966 << 2) + 0xff620000) ++#define HEVC_DBLK_CLIP_CTRL5 (0x3967) ++#define P_HEVC_DBLK_CLIP_CTRL5 (volatile unsigned int *)((0x3967 << 2) + 0xff620000) ++#define HEVC_DBLK_CLIP_CTRL6 (0x3968) ++#define P_HEVC_DBLK_CLIP_CTRL6 (volatile unsigned int *)((0x3968 << 2) + 0xff620000) ++#define HEVC_DBLK_CLIP_CTRL7 (0x3969) ++#define P_HEVC_DBLK_CLIP_CTRL7 (volatile unsigned int *)((0x3969 << 2) + 0xff620000) ++#define HEVC_DBLK_CLIP_CTRL8 (0x396a) ++#define P_HEVC_DBLK_CLIP_CTRL8 (volatile unsigned int *)((0x396a << 2) + 0xff620000) ++#define HEVC_DBLK_STATUS1 (0x396b) ++#define P_HEVC_DBLK_STATUS1 (volatile unsigned int *)((0x396b << 2) + 0xff620000) ++#define HEVC_DBLK_GCLK_FREE (0x396c) ++#define P_HEVC_DBLK_GCLK_FREE (volatile unsigned int *)((0x396c << 2) + 0xff620000) ++#define HEVC_DBLK_GCLK_OFF (0x396d) ++#define P_HEVC_DBLK_GCLK_OFF (volatile unsigned int *)((0x396d << 2) + 0xff620000) ++#define HEVC_DBLK_AVSFLAGS (0x396e) ++#define P_HEVC_DBLK_AVSFLAGS (volatile unsigned int *)((0x396e << 2) + 0xff620000) ++// bit 15:0 ++#define HEVC_DBLK_CBPY (0x3970) ++#define P_HEVC_DBLK_CBPY (volatile unsigned int *)((0x3970 << 2) + 0xff620000) ++// bit 11:8 -- deblk_cbpy_bottom ++// bit 7:4 -- deblk_cbpy_left ++// bit 3:0 -- deblk_cbpy_top ++#define HEVC_DBLK_CBPY_ADJ (0x3971) ++#define P_HEVC_DBLK_CBPY_ADJ (volatile unsigned int *)((0x3971 << 2) + 0xff620000) ++// bit 7:0 -- deblk_cbpc ++#define HEVC_DBLK_CBPC (0x3972) ++#define P_HEVC_DBLK_CBPC (volatile unsigned int *)((0x3972 << 2) + 0xff620000) ++// bit 15 -- bottom_mb ++// bit 14 -- left_mb ++// bit 13 -- top_mb ++// bit 12 -- reserved ++// bit 11:8 -- deblk_cbpc_bottom ++// bit 7:4 -- deblk_cbpc_left ++// bit 3:0 -- deblk_cbpc_top ++#define HEVC_DBLK_CBPC_ADJ (0x3973) ++#define P_HEVC_DBLK_CBPC_ADJ (volatile unsigned int *)((0x3973 << 2) + 0xff620000) ++// bit 15:8 -- deblk_hmvd -- {left_1, left_0, below_1, below_0, block3-0} ++// bit 7:0 -- deblk_vmvd -- {top_1, top_0, below_1, below_0, block3-0} ++#define HEVC_DBLK_VHMVD (0x3974) ++#define P_HEVC_DBLK_VHMVD (volatile unsigned int *)((0x3974 << 2) + 0xff620000) ++// bit 13:12 -- right_vmvd ++// bit 11 -- right_above_vmvd ++// bit 10 -- left_below_hmvd ++// bit 9 -- disable_dblk_luma ++// bit 8 -- disable_dblk_chroma ++// bit 7 -- bBelowRefDiff ++// bit 6 -- bLeftRefDiff ++// bit 5 -- bAboveRefDiff ++// bit 4 -- reserved ++// bit 3 -- s_below ++// bit 2 -- s_left ++// bit 1 -- s_above ++// bit 0 -- s ++#define HEVC_DBLK_STRONG (0x3975) ++#define P_HEVC_DBLK_STRONG (volatile unsigned int *)((0x3975 << 2) + 0xff620000) ++// bit 14:10 -- PQUANT ++// bit 9:5 -- left_PQUANT ++// bit 4:0 -- top_PQUANT ++#define HEVC_DBLK_RV8_QUANT (0x3976) ++#define P_HEVC_DBLK_RV8_QUANT (volatile unsigned int *)((0x3976 << 2) + 0xff620000) ++#define HEVC_DBLK_CBUS_HCMD2 (0x3977) ++#define P_HEVC_DBLK_CBUS_HCMD2 (volatile unsigned int *)((0x3977 << 2) + 0xff620000) ++#define HEVC_DBLK_CBUS_HCMD1 (0x3978) ++#define P_HEVC_DBLK_CBUS_HCMD1 (volatile unsigned int *)((0x3978 << 2) + 0xff620000) ++#define HEVC_DBLK_CBUS_HCMD0 (0x3979) ++#define P_HEVC_DBLK_CBUS_HCMD0 (volatile unsigned int *)((0x3979 << 2) + 0xff620000) ++#define HEVC_DBLK_VLD_HCMD2 (0x397a) ++#define P_HEVC_DBLK_VLD_HCMD2 (volatile unsigned int *)((0x397a << 2) + 0xff620000) ++#define HEVC_DBLK_VLD_HCMD1 (0x397b) ++#define P_HEVC_DBLK_VLD_HCMD1 (volatile unsigned int *)((0x397b << 2) + 0xff620000) ++#define HEVC_DBLK_VLD_HCMD0 (0x397c) ++#define P_HEVC_DBLK_VLD_HCMD0 (volatile unsigned int *)((0x397c << 2) + 0xff620000) ++#define HEVC_DBLK_OST_YBASE (0x397d) ++#define P_HEVC_DBLK_OST_YBASE (volatile unsigned int *)((0x397d << 2) + 0xff620000) ++#define HEVC_DBLK_OST_CBCRDIFF (0x397e) ++#define P_HEVC_DBLK_OST_CBCRDIFF (volatile unsigned int *)((0x397e << 2) + 0xff620000) ++//13:8 dblk thread ID and token ++//5:0 dblk prearbitor burst num ++#define HEVC_DBLK_CTRL1 (0x397f) ++#define P_HEVC_DBLK_CTRL1 (volatile unsigned int *)((0x397f << 2) + 0xff620000) ++// MCRCC_CTL1 ++// 31:3 ++// 2 ++// 1 ++// 0 ++#define HEVC_MCRCC_CTL1 (0x3980) ++#define P_HEVC_MCRCC_CTL1 (volatile unsigned int *)((0x3980 << 2) + 0xff620000) ++// MCRCC_CTL2 ++// 31:24 ++// 23:16 ++// 15:8 ++// 7:0 ++#define HEVC_MCRCC_CTL2 (0x3981) ++#define P_HEVC_MCRCC_CTL2 (volatile unsigned int *)((0x3981 << 2) + 0xff620000) ++// MCRCC_CTL3 ++// 31:24 ++// 23:16 ++// 15:8 ++// 7:0 ++#define HEVC_MCRCC_CTL3 (0x3982) ++#define P_HEVC_MCRCC_CTL3 (volatile unsigned int *)((0x3982 << 2) + 0xff620000) ++// bit[31:10] reserved ++// bit[9:0] sw_clock_gating control ++// [9] vdec clk_en for assist and cbus. ++// [8] vdec clk_en for ddr ++// [7] vdec clk_en for vcpu ++// [6] vdec clk_en for assist ++// [5] vdec clk_en for dblk ++// [4] vdec clk_en for iqidct ++// [3] vdec clk_en for mc ++// [2] vdec clk_en for pic_dc ++// [1] vdec clk_en for psc ++// [0] vdec clk_en for vld ++#define HEVC_GCLK_EN (0x3983) ++#define P_HEVC_GCLK_EN (volatile unsigned int *)((0x3983 << 2) + 0xff620000) ++// [0] Reserved ++// [1] Reserved ++// [2] Reset assist, mdec's CBUS ++// [3] Reset mdec's VLD ++// [4] Reset mdec's VLD ++// [5] Reset mdec's VLD ++// [6] Reset mdec's IQIDCT ++// [7] Reset mdec's MC ++// [8] Reset mdec's DBLK ++// [9] Reset mdec's PIC_DC ++// [10] Reset mdec's Pscale ++// [11] Reset vcpu's MCPU ++// [12] Reset vcpu's CCPU ++// [13] Reset mmc_pre_arb ++#define HEVC_MDEC_SW_RESET (0x3984) ++#define P_HEVC_MDEC_SW_RESET (volatile unsigned int *)((0x3984 << 2) + 0xff620000) ++//DBLK last address 12'h97f ++// ++// Closing file: mdec_regs.h ++// ++// ++// Reading file: vld_regs.h ++// ++//======================================================================== ++// VLD module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_VDEC_VLD_CBUS_BASE = 0x0c ++// ----------------------------------------------- ++#define HCODEC_VLD_STATUS_CTRL (0x1c00) ++#define P_HCODEC_VLD_STATUS_CTRL (volatile unsigned int *)((0x1c00 << 2) + 0xff620000) ++// ++// bit 10 -- use_old_shift_en ++// bit 9 -- output_mv_not_pmv ++// bit 8:5 -- force_zigzag ++// bit 4 -- force_zigzag_en ++// bit 3 -- disable_viff_anempty_int ++// bit 2 -- disable_m2_ac_coeff_one_cycle ++// bit 1 -- forced_reset force reset pmv ++// bit 0 -- mpeg_type 0:mpeg1 1: mpeg2 ++#define HCODEC_MPEG1_2_REG (0x1c01) ++#define P_HCODEC_MPEG1_2_REG (volatile unsigned int *)((0x1c01 << 2) + 0xff620000) ++#define HCODEC_F_CODE_REG (0x1c02) ++#define P_HCODEC_F_CODE_REG (volatile unsigned int *)((0x1c02 << 2) + 0xff620000) ++#define HCODEC_PIC_HEAD_INFO (0x1c03) ++#define P_HCODEC_PIC_HEAD_INFO (volatile unsigned int *)((0x1c03 << 2) + 0xff620000) ++#define HCODEC_SLICE_VER_POS_PIC_TYPE (0x1c04) ++#define P_HCODEC_SLICE_VER_POS_PIC_TYPE (volatile unsigned int *)((0x1c04 << 2) + 0xff620000) ++#define HCODEC_QP_VALUE_REG (0x1c05) ++#define P_HCODEC_QP_VALUE_REG (volatile unsigned int *)((0x1c05 << 2) + 0xff620000) ++#define HCODEC_MBA_INC (0x1c06) ++#define P_HCODEC_MBA_INC (volatile unsigned int *)((0x1c06 << 2) + 0xff620000) ++#define HCODEC_MB_MOTION_MODE (0x1c07) ++#define P_HCODEC_MB_MOTION_MODE (volatile unsigned int *)((0x1c07 << 2) + 0xff620000) ++//`define PACKET_BYTE_COUNT 8'h08 ++// bit 15 -- force_search_startcode_en ++// bit 14 -- int_cpu_when_error (before do anything) ++// bit 13 -- vld_error_reset ++// bit 12 -- return_on_slice_header ++// bit 6 -- jpeg_ff00_en ++// bit 5:0 -- vld_power_ctl ++#define HCODEC_POWER_CTL_VLD (0x1c08) ++#define P_HCODEC_POWER_CTL_VLD (volatile unsigned int *)((0x1c08 << 2) + 0xff620000) ++#define HCODEC_MB_WIDTH (0x1c09) ++#define P_HCODEC_MB_WIDTH (volatile unsigned int *)((0x1c09 << 2) + 0xff620000) ++#define HCODEC_SLICE_QP (0x1c0a) ++#define P_HCODEC_SLICE_QP (volatile unsigned int *)((0x1c0a << 2) + 0xff620000) ++// `define MB_X_MB_Y 8'h0b /* current MBX and MBY */ ++#define HCODEC_PRE_START_CODE (0x1c0b) ++#define P_HCODEC_PRE_START_CODE (volatile unsigned int *)((0x1c0b << 2) + 0xff620000) ++#define HCODEC_SLICE_START_BYTE_01 (0x1c0c) ++#define P_HCODEC_SLICE_START_BYTE_01 (volatile unsigned int *)((0x1c0c << 2) + 0xff620000) ++#define HCODEC_SLICE_START_BYTE_23 (0x1c0d) ++#define P_HCODEC_SLICE_START_BYTE_23 (volatile unsigned int *)((0x1c0d << 2) + 0xff620000) ++#define HCODEC_RESYNC_MARKER_LENGTH (0x1c0e) ++#define P_HCODEC_RESYNC_MARKER_LENGTH (volatile unsigned int *)((0x1c0e << 2) + 0xff620000) ++// bit[6:5] - frame/field info, 01 - top, 10 - bottom, 11 - frame ++// bit[4:0] - buffer ID ++// L0_BUFF_ID_0, L0_BUFF_ID_1, L1_BUFF_ID_0, L1_BUFF_ID_1 ++#define HCODEC_DECODER_BUFFER_INFO (0x1c0f) ++#define P_HCODEC_DECODER_BUFFER_INFO (volatile unsigned int *)((0x1c0f << 2) + 0xff620000) ++#define HCODEC_FST_FOR_MV_X (0x1c10) ++#define P_HCODEC_FST_FOR_MV_X (volatile unsigned int *)((0x1c10 << 2) + 0xff620000) ++#define HCODEC_FST_FOR_MV_Y (0x1c11) ++#define P_HCODEC_FST_FOR_MV_Y (volatile unsigned int *)((0x1c11 << 2) + 0xff620000) ++#define HCODEC_SCD_FOR_MV_X (0x1c12) ++#define P_HCODEC_SCD_FOR_MV_X (volatile unsigned int *)((0x1c12 << 2) + 0xff620000) ++#define HCODEC_SCD_FOR_MV_Y (0x1c13) ++#define P_HCODEC_SCD_FOR_MV_Y (volatile unsigned int *)((0x1c13 << 2) + 0xff620000) ++#define HCODEC_FST_BAK_MV_X (0x1c14) ++#define P_HCODEC_FST_BAK_MV_X (volatile unsigned int *)((0x1c14 << 2) + 0xff620000) ++#define HCODEC_FST_BAK_MV_Y (0x1c15) ++#define P_HCODEC_FST_BAK_MV_Y (volatile unsigned int *)((0x1c15 << 2) + 0xff620000) ++#define HCODEC_SCD_BAK_MV_X (0x1c16) ++#define P_HCODEC_SCD_BAK_MV_X (volatile unsigned int *)((0x1c16 << 2) + 0xff620000) ++#define HCODEC_SCD_BAK_MV_Y (0x1c17) ++#define P_HCODEC_SCD_BAK_MV_Y (volatile unsigned int *)((0x1c17 << 2) + 0xff620000) ++// Bit 7:4 -- read_buffer_interlace 0-progressive, 1-interlace, used in VC1 ++// bit 3 -- disable_new_stcode_search_fix // From GXM ++// bit 2 -- weighting_prediction ++// bit 1 -- mb_weighting_flag ++// bit 0 -- slice_weighting_flag ++#define HCODEC_VLD_DECODE_CONTROL (0x1c18) ++#define P_HCODEC_VLD_DECODE_CONTROL (volatile unsigned int *)((0x1c18 << 2) + 0xff620000) ++#define HCODEC_VLD_REVERVED_19 (0x1c19) ++#define P_HCODEC_VLD_REVERVED_19 (volatile unsigned int *)((0x1c19 << 2) + 0xff620000) ++#define HCODEC_VIFF_BIT_CNT (0x1c1a) ++#define P_HCODEC_VIFF_BIT_CNT (volatile unsigned int *)((0x1c1a << 2) + 0xff620000) ++#define HCODEC_BYTE_ALIGN_PEAK_HI (0x1c1b) ++#define P_HCODEC_BYTE_ALIGN_PEAK_HI (volatile unsigned int *)((0x1c1b << 2) + 0xff620000) ++#define HCODEC_BYTE_ALIGN_PEAK_LO (0x1c1c) ++#define P_HCODEC_BYTE_ALIGN_PEAK_LO (volatile unsigned int *)((0x1c1c << 2) + 0xff620000) ++#define HCODEC_NEXT_ALIGN_PEAK (0x1c1d) ++#define P_HCODEC_NEXT_ALIGN_PEAK (volatile unsigned int *)((0x1c1d << 2) + 0xff620000) ++// bit 31 : byte_aligned_zero_23_from_org // From GXM ++// bit 30 : force_shift_out_drop_flag_zero // From GXM ++// bit 29 : en_st_protect_from_org // From GXM ++// bit 28 : enable_halt_decode_start_voff ++// bit 27 : disable_C_pred_check ++// bit 26 : disable_I4_pred_check ++// bit 25 : disable_I16_pred_check ++// bit 24 : check_avs_1st_drop ++// bit 23 : enable_cabac_protect // From GXM ++// bit 22 : enable_avs_drop_more ++// bit 21 : reset_avs_drop_ptr ++// bit 20 : reset_cabac_use_next_at_end_req ++// bit 19 : vc1_inv_intra_co_mb_ref_rd ++// bit 18 : vc1_inv_co_mb_ref_rd ++// bit 17 : vc1_inv_intra_co_mb_ref_wr ++// bit 16 : vc1_inv_co_mb_ref_wr ++// bit 15 : disable_mv_cal_begin_only ++// bit 14 : avs_drop_enable ++// bit 13:12 : avs_drop_ptr ++// bit 11:8 : avs_demu_ctl_reg ++// bit 7 : avs_enable ++// bit 6 : disable_dblk_hcmd ++// bit 5 : disable_mc_hcmd ++// bit 4 : first_mode3_set enable ++// bit 3 : first_mode3 ++// bit 2:1 : vc1_profile 0-SP, 1-MP, 2-reserved, 3-AP ++// bit 0 : vc1_enable ++#define HCODEC_VC1_CONTROL_REG (0x1c1e) ++#define P_HCODEC_VC1_CONTROL_REG (volatile unsigned int *)((0x1c1e << 2) + 0xff620000) ++#define HCODEC_PMV1_X (0x1c20) ++#define P_HCODEC_PMV1_X (volatile unsigned int *)((0x1c20 << 2) + 0xff620000) ++#define HCODEC_PMV1_Y (0x1c21) ++#define P_HCODEC_PMV1_Y (volatile unsigned int *)((0x1c21 << 2) + 0xff620000) ++#define HCODEC_PMV2_X (0x1c22) ++#define P_HCODEC_PMV2_X (volatile unsigned int *)((0x1c22 << 2) + 0xff620000) ++#define HCODEC_PMV2_Y (0x1c23) ++#define P_HCODEC_PMV2_Y (volatile unsigned int *)((0x1c23 << 2) + 0xff620000) ++#define HCODEC_PMV3_X (0x1c24) ++#define P_HCODEC_PMV3_X (volatile unsigned int *)((0x1c24 << 2) + 0xff620000) ++#define HCODEC_PMV3_Y (0x1c25) ++#define P_HCODEC_PMV3_Y (volatile unsigned int *)((0x1c25 << 2) + 0xff620000) ++#define HCODEC_PMV4_X (0x1c26) ++#define P_HCODEC_PMV4_X (volatile unsigned int *)((0x1c26 << 2) + 0xff620000) ++#define HCODEC_PMV4_Y (0x1c27) ++#define P_HCODEC_PMV4_Y (volatile unsigned int *)((0x1c27 << 2) + 0xff620000) ++// Can't use the same address for different defines ++// Therefore, create a single define that covers both ++// Only appears to be used in micro-code since the VLD hardware is ++// hard coded. ++// `define M4_TABLE_SELECT 8'h28 // Does this exist in HW ? Added from register_mp2.h ++// `define M4_TABLE_OUTPUT 8'h28 // Does this exist in HW ? Added from register_mp2.h ++#define HCODEC_M4_TABLE_SELECT (0x1c28) ++#define P_HCODEC_M4_TABLE_SELECT (volatile unsigned int *)((0x1c28 << 2) + 0xff620000) ++#define HCODEC_M4_CONTROL_REG (0x1c29) ++#define P_HCODEC_M4_CONTROL_REG (volatile unsigned int *)((0x1c29 << 2) + 0xff620000) ++#define HCODEC_BLOCK_NUM (0x1c2a) ++#define P_HCODEC_BLOCK_NUM (volatile unsigned int *)((0x1c2a << 2) + 0xff620000) ++#define HCODEC_PATTERN_CODE (0x1c2b) ++#define P_HCODEC_PATTERN_CODE (volatile unsigned int *)((0x1c2b << 2) + 0xff620000) ++#define HCODEC_MB_INFO (0x1c2c) ++#define P_HCODEC_MB_INFO (volatile unsigned int *)((0x1c2c << 2) + 0xff620000) ++#define HCODEC_VLD_DC_PRED (0x1c2d) ++#define P_HCODEC_VLD_DC_PRED (volatile unsigned int *)((0x1c2d << 2) + 0xff620000) ++#define HCODEC_VLD_ERROR_MASK (0x1c2e) ++#define P_HCODEC_VLD_ERROR_MASK (volatile unsigned int *)((0x1c2e << 2) + 0xff620000) ++#define HCODEC_VLD_DC_PRED_C (0x1c2f) ++#define P_HCODEC_VLD_DC_PRED_C (volatile unsigned int *)((0x1c2f << 2) + 0xff620000) ++#define HCODEC_LAST_SLICE_MV_ADDR (0x1c30) ++#define P_HCODEC_LAST_SLICE_MV_ADDR (volatile unsigned int *)((0x1c30 << 2) + 0xff620000) ++#define HCODEC_LAST_MVX (0x1c31) ++#define P_HCODEC_LAST_MVX (volatile unsigned int *)((0x1c31 << 2) + 0xff620000) ++#define HCODEC_LAST_MVY (0x1c32) ++#define P_HCODEC_LAST_MVY (volatile unsigned int *)((0x1c32 << 2) + 0xff620000) ++#define HCODEC_VLD_C38 (0x1c38) ++#define P_HCODEC_VLD_C38 (volatile unsigned int *)((0x1c38 << 2) + 0xff620000) ++#define HCODEC_VLD_C39 (0x1c39) ++#define P_HCODEC_VLD_C39 (volatile unsigned int *)((0x1c39 << 2) + 0xff620000) ++#define HCODEC_VLD_STATUS (0x1c3a) ++#define P_HCODEC_VLD_STATUS (volatile unsigned int *)((0x1c3a << 2) + 0xff620000) ++#define HCODEC_VLD_SHIFT_STATUS (0x1c3b) ++#define P_HCODEC_VLD_SHIFT_STATUS (volatile unsigned int *)((0x1c3b << 2) + 0xff620000) ++// `define VLD_SHIFT_INFO 8'h3b // Does this exist in HW ? used in $ucode/mpeg4 ++#define HCODEC_VOFF_STATUS (0x1c3c) ++#define P_HCODEC_VOFF_STATUS (volatile unsigned int *)((0x1c3c << 2) + 0xff620000) ++#define HCODEC_VLD_C3D (0x1c3d) ++#define P_HCODEC_VLD_C3D (volatile unsigned int *)((0x1c3d << 2) + 0xff620000) ++#define HCODEC_VLD_DBG_INDEX (0x1c3e) ++#define P_HCODEC_VLD_DBG_INDEX (volatile unsigned int *)((0x1c3e << 2) + 0xff620000) ++// vld_buff_info -- (index == 0) ++// Bit11] halt_decode_start_voff ++// Bit10] C_pred_error ++// Bit[9] I4_pred_error ++// Bit[8] I16_pred_error ++// Bit[7:6] mv_UR_ready_cnt; ++// Bit[5] vld_wr_idx ++// Bit[4] iq_rd_idx ++// Bit[3] vld_vi_block_rdy_1 ++// Bit[2] vld_vi_block_rdy_2 ++// Bit[1] voff_empty_1 ++// Bit[0] voff_empty_2 ++// cabac_buff_info_0 -- (index == 1) ++// Bit[31] shift_data_ready ++// Bit[30:29] Reserved ++// Bit[28:24] cabac_buffer_ptr ++// Bit[23:0] cabac_buffer ++// cabac_buff_info_1 -- (index == 2) ++// Bit[31:29] Reserved ++// Bit[28:20] Drange ++// Bit[19:16] bin_count_4 ++// Bit[15:13] Reserved ++// Bit[12:6] context_mem_do ++// Bit[5:3] coeff_state ++// Bit[2:0] mvd_state ++// h264_mv_present -- (index == 3) ++// Bit[31:16] mv_present_l0 ++// Bit[15:0] mv_present_l1 ++// h264_mv_cal_info_0 -- (index == 4) ++// [31:28] mv_cal_state ++// [27:24] direct_spatial_cnt ++// Bit[23:21] Reserved ++// Bit[20] mv_UR_ready_for_mv_cal ++// Bit[19] co_mb_mem_ready_for_mv_cal ++// Bit[18] mc_dblk_cmd_if_busy ++// Bit[17] h264_co_mb_wr_busy ++// Bit[16] H264_cbp_blk_ready ++// Bit[15] mc_hcmd_rrdy ++// Bit[14] mc_hcmd_srdy ++// Bit[13] mc_cmd_if_ready ++// Bit[12] mc_hcmd_mv_available ++// Bit[11:8] mc_cmd_if_state ++// Bit[7] dblk_hcmd_rrdy ++// Bit[6] dblk_hcmd_srdy ++// Bit[5] dblk_cmd_if_ready ++// Bit[4] dblk_hcmd_mv_available ++// Bit[3:0] dblk_cmd_if_state ++// h264_mv_cal_info_1 -- (index == 5) ++// Bit[31:29] Reserved ++// Bit[28:24] total_mvd_num_l0 ++// Bit[23:21] Reserved ++// Bit[20:16] mv_cal_ptr_l0 ++// Bit[15:13] Reserved ++// Bit[12:8] mc_hcmd_ptr_l0 ++// Bit[7:5] Reserved ++// Bit[4:0] dblk_hcmd_ptr_l0 ++// h264_mv_cal_info_2 -- (index == 6) ++// Bit[31:29] Reserved ++// Bit[28:24] total_mvd_num_l1 ++// Bit[23:21] Reserved ++// Bit[20:16] mv_cal_ptr_l1 ++// Bit[15:13] Reserved ++// Bit[12:8] mc_hcmd_ptr_l1 ++// Bit[7:5] Reserved ++// Bit[4:0] dblk_hcmd_ptr_l1 ++// h264_co_mb_info -- (index == 7) ++// Bit[31:26] Reserved ++// Bit[25] mv_scale_cal_busy ++// Bit[24:20] co_mv_count ++// Bit[19:16] co_mv_process_state ++// Bit[15] h264_co_mb_rd_busy ++// Bit[15] h264_co_mb_rd_ready ++// Bit[13:12] co_mv_transfer_block_cnt ++// Bit[11:8] co_mv_transfer_ptr ++// Bit[7] co_mv_POC_l1_busy ++// Bit[6] h264_weight_scale_cal_en ++// Bit[5] weight_cal_busy ++// Bit[4] weight_cal_not_finished ++// Bit[3:0] weight_process_state ++#define HCODEC_VLD_DBG_DATA (0x1c3f) ++#define P_HCODEC_VLD_DBG_DATA (volatile unsigned int *)((0x1c3f << 2) + 0xff620000) ++// -------------------------------------------- ++// VIFIFO DDR Interface ++// -------------------------------------------- ++// The VIFIFO start pointer into DDR memory is a 32-bit number ++// The Start pointer will automatically be truncated to land on ++// an 8-byte boundary. That is, bits [2:0] = 0; ++#define HCODEC_VLD_MEM_VIFIFO_START_PTR (0x1c40) ++#define P_HCODEC_VLD_MEM_VIFIFO_START_PTR (volatile unsigned int *)((0x1c40 << 2) + 0xff620000) ++// The current pointer points so some location between the START and END ++// pointers. The current pointer is a BYTE pointer. That is, you can ++// point to any BYTE address within the START/END range ++#define HCODEC_VLD_MEM_VIFIFO_CURR_PTR (0x1c41) ++#define P_HCODEC_VLD_MEM_VIFIFO_CURR_PTR (volatile unsigned int *)((0x1c41 << 2) + 0xff620000) ++#define HCODEC_VLD_MEM_VIFIFO_END_PTR (0x1c42) ++#define P_HCODEC_VLD_MEM_VIFIFO_END_PTR (volatile unsigned int *)((0x1c42 << 2) + 0xff620000) ++#define HCODEC_VLD_MEM_VIFIFO_BYTES_AVAIL (0x1c43) ++#define P_HCODEC_VLD_MEM_VIFIFO_BYTES_AVAIL (volatile unsigned int *)((0x1c43 << 2) + 0xff620000) ++// VIFIFO FIFO Control ++// bit [31:24] viff_empty_int_enable_cpu[7:0] ++// bit [23:16] viff_empty_int_enable_amrisc[7:0] ++// -bit 23 Video BUFFER < 0x400 Bytes ++// -bit 22 Video BUFFER < 0x200 Bytes ++// -bit 21 Video BUFFER < 0x100 Bytes ++// -bit 20 Video BUFFER < 0x80 Bytes ++// -bit 19 Video BUFFER < 0x40 Bytes ++// -bit 18 Video BUFFER < 0x20 Bytes ++// -bit 17 vififo < 16 double words ++// -bit 16 vififo < 8 double words ++// bit [15:13] unused ++// bit [12] A_urgent ++// bit [11] transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request ++// bit [10] use_level Set this bit to 1 to enable filling of the FIFO controlled by the buffer ++// level control. If this bit is 0, then use bit[1] to control the enabling of filling ++// bit [9] Data Ready. This bit is set when data can be popped ++// bit [8] fill busy This bit will be high when we're fetching data from the DDR memory ++// To reset this module, set cntl_enable = 0, and then wait for busy = 0. ++// After that you can pulse cntl_init to start over ++// bit [7] init_with_cntl_init ++// bit [6] reserved ++// bits [5:3] endian: see $lib/rtl/ddr_endian.v ++// bit [2] cntl_empty_en Set to 1 to enable reading the DDR memory FIFO ++// Set cntl_empty_en = cntl_fill_en = 0 when pulsing cntl_init ++// bit [1] cntl_fill_en Set to 1 to enable reading data from DDR memory ++// bit [0] cntl_init: After setting the read pointers, sizes, channel masks ++// and read masks, set this bit to 1 and then to 0 ++// NOTE: You don't need to pulse cntl_init if only the start address is ++// being changed ++#define HCODEC_VLD_MEM_VIFIFO_CONTROL (0x1c44) ++#define P_HCODEC_VLD_MEM_VIFIFO_CONTROL (volatile unsigned int *)((0x1c44 << 2) + 0xff620000) ++// -------------------------------------------- ++// VIFIFO Buffer Level Manager ++// -------------------------------------------- ++#define HCODEC_VLD_MEM_VIFIFO_WP (0x1c45) ++#define P_HCODEC_VLD_MEM_VIFIFO_WP (volatile unsigned int *)((0x1c45 << 2) + 0xff620000) ++#define HCODEC_VLD_MEM_VIFIFO_RP (0x1c46) ++#define P_HCODEC_VLD_MEM_VIFIFO_RP (volatile unsigned int *)((0x1c46 << 2) + 0xff620000) ++#define HCODEC_VLD_MEM_VIFIFO_LEVEL (0x1c47) ++#define P_HCODEC_VLD_MEM_VIFIFO_LEVEL (volatile unsigned int *)((0x1c47 << 2) + 0xff620000) ++// ++// bit [8] use_parser_video2_wp ++// bit [7] vbuf2_out_manual ++// bit [6] vbuf_out_manual ++// bit [5] empty (ReadOnly) ++// bit [4] full (ReadOnly) ++// bit [3:2] reserved ++// bit [1] manual mode Set to 1 for manual write pointer mode ++// bit [0] Init Set high then low after everything has been initialized ++#define HCODEC_VLD_MEM_VIFIFO_BUF_CNTL (0x1c48) ++#define P_HCODEC_VLD_MEM_VIFIFO_BUF_CNTL (volatile unsigned int *)((0x1c48 << 2) + 0xff620000) ++// bit 31:16 -- drop_bytes ++// bit 15:14 -- drop_status (Read-Only) ++// bit 13:12 -- sync_match_position (Read-Only) ++// bit 11:6 -- reserved ++// bit 5:4 -- TIME_STAMP_NUMBER, 0-32bits, 1-64bits, 2-96bits, 3-128bits ++// bit 3 -- stamp_soft_reset ++// bit 2 -- TIME_STAMP_length_enable ++// bit 1 -- TIME_STAMP_sync64_enable ++// bit 0 -- TIME_STAMP_enable ++#define HCODEC_VLD_TIME_STAMP_CNTL (0x1c49) ++#define P_HCODEC_VLD_TIME_STAMP_CNTL (volatile unsigned int *)((0x1c49 << 2) + 0xff620000) ++// bit 31:0 -- TIME_STAMP_SYNC_CODE_0 ++#define HCODEC_VLD_TIME_STAMP_SYNC_0 (0x1c4a) ++#define P_HCODEC_VLD_TIME_STAMP_SYNC_0 (volatile unsigned int *)((0x1c4a << 2) + 0xff620000) ++// bit 31:0 -- TIME_STAMP_SYNC_CODE_1 ++#define HCODEC_VLD_TIME_STAMP_SYNC_1 (0x1c4b) ++#define P_HCODEC_VLD_TIME_STAMP_SYNC_1 (volatile unsigned int *)((0x1c4b << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_0 ++#define HCODEC_VLD_TIME_STAMP_0 (0x1c4c) ++#define P_HCODEC_VLD_TIME_STAMP_0 (volatile unsigned int *)((0x1c4c << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_1 ++#define HCODEC_VLD_TIME_STAMP_1 (0x1c4d) ++#define P_HCODEC_VLD_TIME_STAMP_1 (volatile unsigned int *)((0x1c4d << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_2 ++#define HCODEC_VLD_TIME_STAMP_2 (0x1c4e) ++#define P_HCODEC_VLD_TIME_STAMP_2 (volatile unsigned int *)((0x1c4e << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_3 ++#define HCODEC_VLD_TIME_STAMP_3 (0x1c4f) ++#define P_HCODEC_VLD_TIME_STAMP_3 (volatile unsigned int *)((0x1c4f << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_LENGTH ++#define HCODEC_VLD_TIME_STAMP_LENGTH (0x1c50) ++#define P_HCODEC_VLD_TIME_STAMP_LENGTH (volatile unsigned int *)((0x1c50 << 2) + 0xff620000) ++// bit 15:0 vififo_rd_count ++#define HCODEC_VLD_MEM_VIFIFO_WRAP_COUNT (0x1c51) ++#define P_HCODEC_VLD_MEM_VIFIFO_WRAP_COUNT (volatile unsigned int *)((0x1c51 << 2) + 0xff620000) ++// bit 29:24 A_brst_num ++// bit 21:16 A_id ++// bit 15:0 level_hold ++#define HCODEC_VLD_MEM_VIFIFO_MEM_CTL (0x1c52) ++#define P_HCODEC_VLD_MEM_VIFIFO_MEM_CTL (volatile unsigned int *)((0x1c52 << 2) + 0xff620000) ++#define HCODEC_VLD_MEM_VBUF_RD_PTR (0x1c53) ++#define P_HCODEC_VLD_MEM_VBUF_RD_PTR (volatile unsigned int *)((0x1c53 << 2) + 0xff620000) ++#define HCODEC_VLD_MEM_VBUF2_RD_PTR (0x1c54) ++#define P_HCODEC_VLD_MEM_VBUF2_RD_PTR (volatile unsigned int *)((0x1c54 << 2) + 0xff620000) ++#define HCODEC_VLD_MEM_SWAP_ADDR (0x1c55) ++#define P_HCODEC_VLD_MEM_SWAP_ADDR (volatile unsigned int *)((0x1c55 << 2) + 0xff620000) ++// bit[23:16] - swap_d_count (Read Only) ++// bit[15:8] - swap_a_count (Read Only) ++// bit [7] - swap busy (Read Only) ++// bit [6:2] - reserved ++// bit [1] - 1 - STORE to Memory, 0 - LOAD from Memory ++// bit [0] - swap active ++#define HCODEC_VLD_MEM_SWAP_CTL (0x1c56) ++#define P_HCODEC_VLD_MEM_SWAP_CTL (volatile unsigned int *)((0x1c56 << 2) + 0xff620000) ++// ++// Closing file: vld_regs.h ++// ++// ++// Reading file: vld_regs.h ++// ++//======================================================================== ++// VLD module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_VDEC_VLD_CBUS_BASE = 0x0c ++// ----------------------------------------------- ++#define VDEC2_VLD_STATUS_CTRL (0x2c00) ++#define P_VDEC2_VLD_STATUS_CTRL (volatile unsigned int *)((0x2c00 << 2) + 0xff620000) ++// ++// bit 10 -- use_old_shift_en ++// bit 9 -- output_mv_not_pmv ++// bit 8:5 -- force_zigzag ++// bit 4 -- force_zigzag_en ++// bit 3 -- disable_viff_anempty_int ++// bit 2 -- disable_m2_ac_coeff_one_cycle ++// bit 1 -- forced_reset force reset pmv ++// bit 0 -- mpeg_type 0:mpeg1 1: mpeg2 ++#define VDEC2_MPEG1_2_REG (0x2c01) ++#define P_VDEC2_MPEG1_2_REG (volatile unsigned int *)((0x2c01 << 2) + 0xff620000) ++#define VDEC2_F_CODE_REG (0x2c02) ++#define P_VDEC2_F_CODE_REG (volatile unsigned int *)((0x2c02 << 2) + 0xff620000) ++#define VDEC2_PIC_HEAD_INFO (0x2c03) ++#define P_VDEC2_PIC_HEAD_INFO (volatile unsigned int *)((0x2c03 << 2) + 0xff620000) ++#define VDEC2_SLICE_VER_POS_PIC_TYPE (0x2c04) ++#define P_VDEC2_SLICE_VER_POS_PIC_TYPE (volatile unsigned int *)((0x2c04 << 2) + 0xff620000) ++#define VDEC2_QP_VALUE_REG (0x2c05) ++#define P_VDEC2_QP_VALUE_REG (volatile unsigned int *)((0x2c05 << 2) + 0xff620000) ++#define VDEC2_MBA_INC (0x2c06) ++#define P_VDEC2_MBA_INC (volatile unsigned int *)((0x2c06 << 2) + 0xff620000) ++#define VDEC2_MB_MOTION_MODE (0x2c07) ++#define P_VDEC2_MB_MOTION_MODE (volatile unsigned int *)((0x2c07 << 2) + 0xff620000) ++//`define PACKET_BYTE_COUNT 8'h08 ++// bit 15 -- force_search_startcode_en ++// bit 14 -- int_cpu_when_error (before do anything) ++// bit 13 -- vld_error_reset ++// bit 12 -- return_on_slice_header ++// bit 6 -- jpeg_ff00_en ++// bit 5:0 -- vld_power_ctl ++#define VDEC2_POWER_CTL_VLD (0x2c08) ++#define P_VDEC2_POWER_CTL_VLD (volatile unsigned int *)((0x2c08 << 2) + 0xff620000) ++#define VDEC2_MB_WIDTH (0x2c09) ++#define P_VDEC2_MB_WIDTH (volatile unsigned int *)((0x2c09 << 2) + 0xff620000) ++#define VDEC2_SLICE_QP (0x2c0a) ++#define P_VDEC2_SLICE_QP (volatile unsigned int *)((0x2c0a << 2) + 0xff620000) ++// `define MB_X_MB_Y 8'h0b /* current MBX and MBY */ ++#define VDEC2_PRE_START_CODE (0x2c0b) ++#define P_VDEC2_PRE_START_CODE (volatile unsigned int *)((0x2c0b << 2) + 0xff620000) ++#define VDEC2_SLICE_START_BYTE_01 (0x2c0c) ++#define P_VDEC2_SLICE_START_BYTE_01 (volatile unsigned int *)((0x2c0c << 2) + 0xff620000) ++#define VDEC2_SLICE_START_BYTE_23 (0x2c0d) ++#define P_VDEC2_SLICE_START_BYTE_23 (volatile unsigned int *)((0x2c0d << 2) + 0xff620000) ++#define VDEC2_RESYNC_MARKER_LENGTH (0x2c0e) ++#define P_VDEC2_RESYNC_MARKER_LENGTH (volatile unsigned int *)((0x2c0e << 2) + 0xff620000) ++// bit[6:5] - frame/field info, 01 - top, 10 - bottom, 11 - frame ++// bit[4:0] - buffer ID ++// L0_BUFF_ID_0, L0_BUFF_ID_1, L1_BUFF_ID_0, L1_BUFF_ID_1 ++#define VDEC2_DECODER_BUFFER_INFO (0x2c0f) ++#define P_VDEC2_DECODER_BUFFER_INFO (volatile unsigned int *)((0x2c0f << 2) + 0xff620000) ++#define VDEC2_FST_FOR_MV_X (0x2c10) ++#define P_VDEC2_FST_FOR_MV_X (volatile unsigned int *)((0x2c10 << 2) + 0xff620000) ++#define VDEC2_FST_FOR_MV_Y (0x2c11) ++#define P_VDEC2_FST_FOR_MV_Y (volatile unsigned int *)((0x2c11 << 2) + 0xff620000) ++#define VDEC2_SCD_FOR_MV_X (0x2c12) ++#define P_VDEC2_SCD_FOR_MV_X (volatile unsigned int *)((0x2c12 << 2) + 0xff620000) ++#define VDEC2_SCD_FOR_MV_Y (0x2c13) ++#define P_VDEC2_SCD_FOR_MV_Y (volatile unsigned int *)((0x2c13 << 2) + 0xff620000) ++#define VDEC2_FST_BAK_MV_X (0x2c14) ++#define P_VDEC2_FST_BAK_MV_X (volatile unsigned int *)((0x2c14 << 2) + 0xff620000) ++#define VDEC2_FST_BAK_MV_Y (0x2c15) ++#define P_VDEC2_FST_BAK_MV_Y (volatile unsigned int *)((0x2c15 << 2) + 0xff620000) ++#define VDEC2_SCD_BAK_MV_X (0x2c16) ++#define P_VDEC2_SCD_BAK_MV_X (volatile unsigned int *)((0x2c16 << 2) + 0xff620000) ++#define VDEC2_SCD_BAK_MV_Y (0x2c17) ++#define P_VDEC2_SCD_BAK_MV_Y (volatile unsigned int *)((0x2c17 << 2) + 0xff620000) ++// Bit 7:4 -- read_buffer_interlace 0-progressive, 1-interlace, used in VC1 ++// bit 3 -- disable_new_stcode_search_fix // From GXM ++// bit 2 -- weighting_prediction ++// bit 1 -- mb_weighting_flag ++// bit 0 -- slice_weighting_flag ++#define VDEC2_VLD_DECODE_CONTROL (0x2c18) ++#define P_VDEC2_VLD_DECODE_CONTROL (volatile unsigned int *)((0x2c18 << 2) + 0xff620000) ++#define VDEC2_VLD_REVERVED_19 (0x2c19) ++#define P_VDEC2_VLD_REVERVED_19 (volatile unsigned int *)((0x2c19 << 2) + 0xff620000) ++#define VDEC2_VIFF_BIT_CNT (0x2c1a) ++#define P_VDEC2_VIFF_BIT_CNT (volatile unsigned int *)((0x2c1a << 2) + 0xff620000) ++#define VDEC2_BYTE_ALIGN_PEAK_HI (0x2c1b) ++#define P_VDEC2_BYTE_ALIGN_PEAK_HI (volatile unsigned int *)((0x2c1b << 2) + 0xff620000) ++#define VDEC2_BYTE_ALIGN_PEAK_LO (0x2c1c) ++#define P_VDEC2_BYTE_ALIGN_PEAK_LO (volatile unsigned int *)((0x2c1c << 2) + 0xff620000) ++#define VDEC2_NEXT_ALIGN_PEAK (0x2c1d) ++#define P_VDEC2_NEXT_ALIGN_PEAK (volatile unsigned int *)((0x2c1d << 2) + 0xff620000) ++// bit 31 : byte_aligned_zero_23_from_org // From GXM ++// bit 30 : force_shift_out_drop_flag_zero // From GXM ++// bit 29 : en_st_protect_from_org // From GXM ++// bit 28 : enable_halt_decode_start_voff ++// bit 27 : disable_C_pred_check ++// bit 26 : disable_I4_pred_check ++// bit 25 : disable_I16_pred_check ++// bit 24 : check_avs_1st_drop ++// bit 23 : enable_cabac_protect // From GXM ++// bit 22 : enable_avs_drop_more ++// bit 21 : reset_avs_drop_ptr ++// bit 20 : reset_cabac_use_next_at_end_req ++// bit 19 : vc1_inv_intra_co_mb_ref_rd ++// bit 18 : vc1_inv_co_mb_ref_rd ++// bit 17 : vc1_inv_intra_co_mb_ref_wr ++// bit 16 : vc1_inv_co_mb_ref_wr ++// bit 15 : disable_mv_cal_begin_only ++// bit 14 : avs_drop_enable ++// bit 13:12 : avs_drop_ptr ++// bit 11:8 : avs_demu_ctl_reg ++// bit 7 : avs_enable ++// bit 6 : disable_dblk_hcmd ++// bit 5 : disable_mc_hcmd ++// bit 4 : first_mode3_set enable ++// bit 3 : first_mode3 ++// bit 2:1 : vc1_profile 0-SP, 1-MP, 2-reserved, 3-AP ++// bit 0 : vc1_enable ++#define VDEC2_VC1_CONTROL_REG (0x2c1e) ++#define P_VDEC2_VC1_CONTROL_REG (volatile unsigned int *)((0x2c1e << 2) + 0xff620000) ++#define VDEC2_PMV1_X (0x2c20) ++#define P_VDEC2_PMV1_X (volatile unsigned int *)((0x2c20 << 2) + 0xff620000) ++#define VDEC2_PMV1_Y (0x2c21) ++#define P_VDEC2_PMV1_Y (volatile unsigned int *)((0x2c21 << 2) + 0xff620000) ++#define VDEC2_PMV2_X (0x2c22) ++#define P_VDEC2_PMV2_X (volatile unsigned int *)((0x2c22 << 2) + 0xff620000) ++#define VDEC2_PMV2_Y (0x2c23) ++#define P_VDEC2_PMV2_Y (volatile unsigned int *)((0x2c23 << 2) + 0xff620000) ++#define VDEC2_PMV3_X (0x2c24) ++#define P_VDEC2_PMV3_X (volatile unsigned int *)((0x2c24 << 2) + 0xff620000) ++#define VDEC2_PMV3_Y (0x2c25) ++#define P_VDEC2_PMV3_Y (volatile unsigned int *)((0x2c25 << 2) + 0xff620000) ++#define VDEC2_PMV4_X (0x2c26) ++#define P_VDEC2_PMV4_X (volatile unsigned int *)((0x2c26 << 2) + 0xff620000) ++#define VDEC2_PMV4_Y (0x2c27) ++#define P_VDEC2_PMV4_Y (volatile unsigned int *)((0x2c27 << 2) + 0xff620000) ++// Can't use the same address for different defines ++// Therefore, create a single define that covers both ++// Only appears to be used in micro-code since the VLD hardware is ++// hard coded. ++// `define M4_TABLE_SELECT 8'h28 // Does this exist in HW ? Added from register_mp2.h ++// `define M4_TABLE_OUTPUT 8'h28 // Does this exist in HW ? Added from register_mp2.h ++#define VDEC2_M4_TABLE_SELECT (0x2c28) ++#define P_VDEC2_M4_TABLE_SELECT (volatile unsigned int *)((0x2c28 << 2) + 0xff620000) ++#define VDEC2_M4_CONTROL_REG (0x2c29) ++#define P_VDEC2_M4_CONTROL_REG (volatile unsigned int *)((0x2c29 << 2) + 0xff620000) ++#define VDEC2_BLOCK_NUM (0x2c2a) ++#define P_VDEC2_BLOCK_NUM (volatile unsigned int *)((0x2c2a << 2) + 0xff620000) ++#define VDEC2_PATTERN_CODE (0x2c2b) ++#define P_VDEC2_PATTERN_CODE (volatile unsigned int *)((0x2c2b << 2) + 0xff620000) ++#define VDEC2_MB_INFO (0x2c2c) ++#define P_VDEC2_MB_INFO (volatile unsigned int *)((0x2c2c << 2) + 0xff620000) ++#define VDEC2_VLD_DC_PRED (0x2c2d) ++#define P_VDEC2_VLD_DC_PRED (volatile unsigned int *)((0x2c2d << 2) + 0xff620000) ++#define VDEC2_VLD_ERROR_MASK (0x2c2e) ++#define P_VDEC2_VLD_ERROR_MASK (volatile unsigned int *)((0x2c2e << 2) + 0xff620000) ++#define VDEC2_VLD_DC_PRED_C (0x2c2f) ++#define P_VDEC2_VLD_DC_PRED_C (volatile unsigned int *)((0x2c2f << 2) + 0xff620000) ++#define VDEC2_LAST_SLICE_MV_ADDR (0x2c30) ++#define P_VDEC2_LAST_SLICE_MV_ADDR (volatile unsigned int *)((0x2c30 << 2) + 0xff620000) ++#define VDEC2_LAST_MVX (0x2c31) ++#define P_VDEC2_LAST_MVX (volatile unsigned int *)((0x2c31 << 2) + 0xff620000) ++#define VDEC2_LAST_MVY (0x2c32) ++#define P_VDEC2_LAST_MVY (volatile unsigned int *)((0x2c32 << 2) + 0xff620000) ++#define VDEC2_VLD_C38 (0x2c38) ++#define P_VDEC2_VLD_C38 (volatile unsigned int *)((0x2c38 << 2) + 0xff620000) ++#define VDEC2_VLD_C39 (0x2c39) ++#define P_VDEC2_VLD_C39 (volatile unsigned int *)((0x2c39 << 2) + 0xff620000) ++#define VDEC2_VLD_STATUS (0x2c3a) ++#define P_VDEC2_VLD_STATUS (volatile unsigned int *)((0x2c3a << 2) + 0xff620000) ++#define VDEC2_VLD_SHIFT_STATUS (0x2c3b) ++#define P_VDEC2_VLD_SHIFT_STATUS (volatile unsigned int *)((0x2c3b << 2) + 0xff620000) ++// `define VLD_SHIFT_INFO 8'h3b // Does this exist in HW ? used in $ucode/mpeg4 ++#define VDEC2_VOFF_STATUS (0x2c3c) ++#define P_VDEC2_VOFF_STATUS (volatile unsigned int *)((0x2c3c << 2) + 0xff620000) ++#define VDEC2_VLD_C3D (0x2c3d) ++#define P_VDEC2_VLD_C3D (volatile unsigned int *)((0x2c3d << 2) + 0xff620000) ++#define VDEC2_VLD_DBG_INDEX (0x2c3e) ++#define P_VDEC2_VLD_DBG_INDEX (volatile unsigned int *)((0x2c3e << 2) + 0xff620000) ++// vld_buff_info -- (index == 0) ++// Bit11] halt_decode_start_voff ++// Bit10] C_pred_error ++// Bit[9] I4_pred_error ++// Bit[8] I16_pred_error ++// Bit[7:6] mv_UR_ready_cnt; ++// Bit[5] vld_wr_idx ++// Bit[4] iq_rd_idx ++// Bit[3] vld_vi_block_rdy_1 ++// Bit[2] vld_vi_block_rdy_2 ++// Bit[1] voff_empty_1 ++// Bit[0] voff_empty_2 ++// cabac_buff_info_0 -- (index == 1) ++// Bit[31] shift_data_ready ++// Bit[30:29] Reserved ++// Bit[28:24] cabac_buffer_ptr ++// Bit[23:0] cabac_buffer ++// cabac_buff_info_1 -- (index == 2) ++// Bit[31:29] Reserved ++// Bit[28:20] Drange ++// Bit[19:16] bin_count_4 ++// Bit[15:13] Reserved ++// Bit[12:6] context_mem_do ++// Bit[5:3] coeff_state ++// Bit[2:0] mvd_state ++// h264_mv_present -- (index == 3) ++// Bit[31:16] mv_present_l0 ++// Bit[15:0] mv_present_l1 ++// h264_mv_cal_info_0 -- (index == 4) ++// [31:28] mv_cal_state ++// [27:24] direct_spatial_cnt ++// Bit[23:21] Reserved ++// Bit[20] mv_UR_ready_for_mv_cal ++// Bit[19] co_mb_mem_ready_for_mv_cal ++// Bit[18] mc_dblk_cmd_if_busy ++// Bit[17] h264_co_mb_wr_busy ++// Bit[16] H264_cbp_blk_ready ++// Bit[15] mc_hcmd_rrdy ++// Bit[14] mc_hcmd_srdy ++// Bit[13] mc_cmd_if_ready ++// Bit[12] mc_hcmd_mv_available ++// Bit[11:8] mc_cmd_if_state ++// Bit[7] dblk_hcmd_rrdy ++// Bit[6] dblk_hcmd_srdy ++// Bit[5] dblk_cmd_if_ready ++// Bit[4] dblk_hcmd_mv_available ++// Bit[3:0] dblk_cmd_if_state ++// h264_mv_cal_info_1 -- (index == 5) ++// Bit[31:29] Reserved ++// Bit[28:24] total_mvd_num_l0 ++// Bit[23:21] Reserved ++// Bit[20:16] mv_cal_ptr_l0 ++// Bit[15:13] Reserved ++// Bit[12:8] mc_hcmd_ptr_l0 ++// Bit[7:5] Reserved ++// Bit[4:0] dblk_hcmd_ptr_l0 ++// h264_mv_cal_info_2 -- (index == 6) ++// Bit[31:29] Reserved ++// Bit[28:24] total_mvd_num_l1 ++// Bit[23:21] Reserved ++// Bit[20:16] mv_cal_ptr_l1 ++// Bit[15:13] Reserved ++// Bit[12:8] mc_hcmd_ptr_l1 ++// Bit[7:5] Reserved ++// Bit[4:0] dblk_hcmd_ptr_l1 ++// h264_co_mb_info -- (index == 7) ++// Bit[31:26] Reserved ++// Bit[25] mv_scale_cal_busy ++// Bit[24:20] co_mv_count ++// Bit[19:16] co_mv_process_state ++// Bit[15] h264_co_mb_rd_busy ++// Bit[15] h264_co_mb_rd_ready ++// Bit[13:12] co_mv_transfer_block_cnt ++// Bit[11:8] co_mv_transfer_ptr ++// Bit[7] co_mv_POC_l1_busy ++// Bit[6] h264_weight_scale_cal_en ++// Bit[5] weight_cal_busy ++// Bit[4] weight_cal_not_finished ++// Bit[3:0] weight_process_state ++#define VDEC2_VLD_DBG_DATA (0x2c3f) ++#define P_VDEC2_VLD_DBG_DATA (volatile unsigned int *)((0x2c3f << 2) + 0xff620000) ++// -------------------------------------------- ++// VIFIFO DDR Interface ++// -------------------------------------------- ++// The VIFIFO start pointer into DDR memory is a 32-bit number ++// The Start pointer will automatically be truncated to land on ++// an 8-byte boundary. That is, bits [2:0] = 0; ++#define VDEC2_VLD_MEM_VIFIFO_START_PTR (0x2c40) ++#define P_VDEC2_VLD_MEM_VIFIFO_START_PTR (volatile unsigned int *)((0x2c40 << 2) + 0xff620000) ++// The current pointer points so some location between the START and END ++// pointers. The current pointer is a BYTE pointer. That is, you can ++// point to any BYTE address within the START/END range ++#define VDEC2_VLD_MEM_VIFIFO_CURR_PTR (0x2c41) ++#define P_VDEC2_VLD_MEM_VIFIFO_CURR_PTR (volatile unsigned int *)((0x2c41 << 2) + 0xff620000) ++#define VDEC2_VLD_MEM_VIFIFO_END_PTR (0x2c42) ++#define P_VDEC2_VLD_MEM_VIFIFO_END_PTR (volatile unsigned int *)((0x2c42 << 2) + 0xff620000) ++#define VDEC2_VLD_MEM_VIFIFO_BYTES_AVAIL (0x2c43) ++#define P_VDEC2_VLD_MEM_VIFIFO_BYTES_AVAIL (volatile unsigned int *)((0x2c43 << 2) + 0xff620000) ++// VIFIFO FIFO Control ++// bit [31:24] viff_empty_int_enable_cpu[7:0] ++// bit [23:16] viff_empty_int_enable_amrisc[7:0] ++// -bit 23 Video BUFFER < 0x400 Bytes ++// -bit 22 Video BUFFER < 0x200 Bytes ++// -bit 21 Video BUFFER < 0x100 Bytes ++// -bit 20 Video BUFFER < 0x80 Bytes ++// -bit 19 Video BUFFER < 0x40 Bytes ++// -bit 18 Video BUFFER < 0x20 Bytes ++// -bit 17 vififo < 16 double words ++// -bit 16 vififo < 8 double words ++// bit [15:13] unused ++// bit [12] A_urgent ++// bit [11] transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request ++// bit [10] use_level Set this bit to 1 to enable filling of the FIFO controlled by the buffer ++// level control. If this bit is 0, then use bit[1] to control the enabling of filling ++// bit [9] Data Ready. This bit is set when data can be popped ++// bit [8] fill busy This bit will be high when we're fetching data from the DDR memory ++// To reset this module, set cntl_enable = 0, and then wait for busy = 0. ++// After that you can pulse cntl_init to start over ++// bit [7] init_with_cntl_init ++// bit [6] reserved ++// bits [5:3] endian: see $lib/rtl/ddr_endian.v ++// bit [2] cntl_empty_en Set to 1 to enable reading the DDR memory FIFO ++// Set cntl_empty_en = cntl_fill_en = 0 when pulsing cntl_init ++// bit [1] cntl_fill_en Set to 1 to enable reading data from DDR memory ++// bit [0] cntl_init: After setting the read pointers, sizes, channel masks ++// and read masks, set this bit to 1 and then to 0 ++// NOTE: You don't need to pulse cntl_init if only the start address is ++// being changed ++#define VDEC2_VLD_MEM_VIFIFO_CONTROL (0x2c44) ++#define P_VDEC2_VLD_MEM_VIFIFO_CONTROL (volatile unsigned int *)((0x2c44 << 2) + 0xff620000) ++// -------------------------------------------- ++// VIFIFO Buffer Level Manager ++// -------------------------------------------- ++#define VDEC2_VLD_MEM_VIFIFO_WP (0x2c45) ++#define P_VDEC2_VLD_MEM_VIFIFO_WP (volatile unsigned int *)((0x2c45 << 2) + 0xff620000) ++#define VDEC2_VLD_MEM_VIFIFO_RP (0x2c46) ++#define P_VDEC2_VLD_MEM_VIFIFO_RP (volatile unsigned int *)((0x2c46 << 2) + 0xff620000) ++#define VDEC2_VLD_MEM_VIFIFO_LEVEL (0x2c47) ++#define P_VDEC2_VLD_MEM_VIFIFO_LEVEL (volatile unsigned int *)((0x2c47 << 2) + 0xff620000) ++// ++// bit [8] use_parser_video2_wp ++// bit [7] vbuf2_out_manual ++// bit [6] vbuf_out_manual ++// bit [5] empty (ReadOnly) ++// bit [4] full (ReadOnly) ++// bit [3:2] reserved ++// bit [1] manual mode Set to 1 for manual write pointer mode ++// bit [0] Init Set high then low after everything has been initialized ++#define VDEC2_VLD_MEM_VIFIFO_BUF_CNTL (0x2c48) ++#define P_VDEC2_VLD_MEM_VIFIFO_BUF_CNTL (volatile unsigned int *)((0x2c48 << 2) + 0xff620000) ++// bit 31:16 -- drop_bytes ++// bit 15:14 -- drop_status (Read-Only) ++// bit 13:12 -- sync_match_position (Read-Only) ++// bit 11:6 -- reserved ++// bit 5:4 -- TIME_STAMP_NUMBER, 0-32bits, 1-64bits, 2-96bits, 3-128bits ++// bit 3 -- stamp_soft_reset ++// bit 2 -- TIME_STAMP_length_enable ++// bit 1 -- TIME_STAMP_sync64_enable ++// bit 0 -- TIME_STAMP_enable ++#define VDEC2_VLD_TIME_STAMP_CNTL (0x2c49) ++#define P_VDEC2_VLD_TIME_STAMP_CNTL (volatile unsigned int *)((0x2c49 << 2) + 0xff620000) ++// bit 31:0 -- TIME_STAMP_SYNC_CODE_0 ++#define VDEC2_VLD_TIME_STAMP_SYNC_0 (0x2c4a) ++#define P_VDEC2_VLD_TIME_STAMP_SYNC_0 (volatile unsigned int *)((0x2c4a << 2) + 0xff620000) ++// bit 31:0 -- TIME_STAMP_SYNC_CODE_1 ++#define VDEC2_VLD_TIME_STAMP_SYNC_1 (0x2c4b) ++#define P_VDEC2_VLD_TIME_STAMP_SYNC_1 (volatile unsigned int *)((0x2c4b << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_0 ++#define VDEC2_VLD_TIME_STAMP_0 (0x2c4c) ++#define P_VDEC2_VLD_TIME_STAMP_0 (volatile unsigned int *)((0x2c4c << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_1 ++#define VDEC2_VLD_TIME_STAMP_1 (0x2c4d) ++#define P_VDEC2_VLD_TIME_STAMP_1 (volatile unsigned int *)((0x2c4d << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_2 ++#define VDEC2_VLD_TIME_STAMP_2 (0x2c4e) ++#define P_VDEC2_VLD_TIME_STAMP_2 (volatile unsigned int *)((0x2c4e << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_3 ++#define VDEC2_VLD_TIME_STAMP_3 (0x2c4f) ++#define P_VDEC2_VLD_TIME_STAMP_3 (volatile unsigned int *)((0x2c4f << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_LENGTH ++#define VDEC2_VLD_TIME_STAMP_LENGTH (0x2c50) ++#define P_VDEC2_VLD_TIME_STAMP_LENGTH (volatile unsigned int *)((0x2c50 << 2) + 0xff620000) ++// bit 15:0 vififo_rd_count ++#define VDEC2_VLD_MEM_VIFIFO_WRAP_COUNT (0x2c51) ++#define P_VDEC2_VLD_MEM_VIFIFO_WRAP_COUNT (volatile unsigned int *)((0x2c51 << 2) + 0xff620000) ++// bit 29:24 A_brst_num ++// bit 21:16 A_id ++// bit 15:0 level_hold ++#define VDEC2_VLD_MEM_VIFIFO_MEM_CTL (0x2c52) ++#define P_VDEC2_VLD_MEM_VIFIFO_MEM_CTL (volatile unsigned int *)((0x2c52 << 2) + 0xff620000) ++#define VDEC2_VLD_MEM_VBUF_RD_PTR (0x2c53) ++#define P_VDEC2_VLD_MEM_VBUF_RD_PTR (volatile unsigned int *)((0x2c53 << 2) + 0xff620000) ++#define VDEC2_VLD_MEM_VBUF2_RD_PTR (0x2c54) ++#define P_VDEC2_VLD_MEM_VBUF2_RD_PTR (volatile unsigned int *)((0x2c54 << 2) + 0xff620000) ++#define VDEC2_VLD_MEM_SWAP_ADDR (0x2c55) ++#define P_VDEC2_VLD_MEM_SWAP_ADDR (volatile unsigned int *)((0x2c55 << 2) + 0xff620000) ++// bit[23:16] - swap_d_count (Read Only) ++// bit[15:8] - swap_a_count (Read Only) ++// bit [7] - swap busy (Read Only) ++// bit [6:2] - reserved ++// bit [1] - 1 - STORE to Memory, 0 - LOAD from Memory ++// bit [0] - swap active ++#define VDEC2_VLD_MEM_SWAP_CTL (0x2c56) ++#define P_VDEC2_VLD_MEM_SWAP_CTL (volatile unsigned int *)((0x2c56 << 2) + 0xff620000) ++// ++// Closing file: vld_regs.h ++// ++// ++// Reading file: vld_regs.h ++// ++//======================================================================== ++// VLD module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_VDEC_VLD_CBUS_BASE = 0x0c ++// ----------------------------------------------- ++#define HEVC_VLD_STATUS_CTRL (0x3c00) ++#define P_HEVC_VLD_STATUS_CTRL (volatile unsigned int *)((0x3c00 << 2) + 0xff620000) ++// ++// bit 10 -- use_old_shift_en ++// bit 9 -- output_mv_not_pmv ++// bit 8:5 -- force_zigzag ++// bit 4 -- force_zigzag_en ++// bit 3 -- disable_viff_anempty_int ++// bit 2 -- disable_m2_ac_coeff_one_cycle ++// bit 1 -- forced_reset force reset pmv ++// bit 0 -- mpeg_type 0:mpeg1 1: mpeg2 ++#define HEVC_MPEG1_2_REG (0x3c01) ++#define P_HEVC_MPEG1_2_REG (volatile unsigned int *)((0x3c01 << 2) + 0xff620000) ++#define HEVC_F_CODE_REG (0x3c02) ++#define P_HEVC_F_CODE_REG (volatile unsigned int *)((0x3c02 << 2) + 0xff620000) ++#define HEVC_PIC_HEAD_INFO (0x3c03) ++#define P_HEVC_PIC_HEAD_INFO (volatile unsigned int *)((0x3c03 << 2) + 0xff620000) ++#define HEVC_SLICE_VER_POS_PIC_TYPE (0x3c04) ++#define P_HEVC_SLICE_VER_POS_PIC_TYPE (volatile unsigned int *)((0x3c04 << 2) + 0xff620000) ++#define HEVC_QP_VALUE_REG (0x3c05) ++#define P_HEVC_QP_VALUE_REG (volatile unsigned int *)((0x3c05 << 2) + 0xff620000) ++#define HEVC_MBA_INC (0x3c06) ++#define P_HEVC_MBA_INC (volatile unsigned int *)((0x3c06 << 2) + 0xff620000) ++#define HEVC_MB_MOTION_MODE (0x3c07) ++#define P_HEVC_MB_MOTION_MODE (volatile unsigned int *)((0x3c07 << 2) + 0xff620000) ++//`define PACKET_BYTE_COUNT 8'h08 ++// bit 15 -- force_search_startcode_en ++// bit 14 -- int_cpu_when_error (before do anything) ++// bit 13 -- vld_error_reset ++// bit 12 -- return_on_slice_header ++// bit 6 -- jpeg_ff00_en ++// bit 5:0 -- vld_power_ctl ++#define HEVC_POWER_CTL_VLD (0x3c08) ++#define P_HEVC_POWER_CTL_VLD (volatile unsigned int *)((0x3c08 << 2) + 0xff620000) ++#define HEVC_MB_WIDTH (0x3c09) ++#define P_HEVC_MB_WIDTH (volatile unsigned int *)((0x3c09 << 2) + 0xff620000) ++#define HEVC_SLICE_QP (0x3c0a) ++#define P_HEVC_SLICE_QP (volatile unsigned int *)((0x3c0a << 2) + 0xff620000) ++// `define MB_X_MB_Y 8'h0b /* current MBX and MBY */ ++#define HEVC_PRE_START_CODE (0x3c0b) ++#define P_HEVC_PRE_START_CODE (volatile unsigned int *)((0x3c0b << 2) + 0xff620000) ++#define HEVC_SLICE_START_BYTE_01 (0x3c0c) ++#define P_HEVC_SLICE_START_BYTE_01 (volatile unsigned int *)((0x3c0c << 2) + 0xff620000) ++#define HEVC_SLICE_START_BYTE_23 (0x3c0d) ++#define P_HEVC_SLICE_START_BYTE_23 (volatile unsigned int *)((0x3c0d << 2) + 0xff620000) ++#define HEVC_RESYNC_MARKER_LENGTH (0x3c0e) ++#define P_HEVC_RESYNC_MARKER_LENGTH (volatile unsigned int *)((0x3c0e << 2) + 0xff620000) ++// bit[6:5] - frame/field info, 01 - top, 10 - bottom, 11 - frame ++// bit[4:0] - buffer ID ++// L0_BUFF_ID_0, L0_BUFF_ID_1, L1_BUFF_ID_0, L1_BUFF_ID_1 ++#define HEVC_DECODER_BUFFER_INFO (0x3c0f) ++#define P_HEVC_DECODER_BUFFER_INFO (volatile unsigned int *)((0x3c0f << 2) + 0xff620000) ++#define HEVC_FST_FOR_MV_X (0x3c10) ++#define P_HEVC_FST_FOR_MV_X (volatile unsigned int *)((0x3c10 << 2) + 0xff620000) ++#define HEVC_FST_FOR_MV_Y (0x3c11) ++#define P_HEVC_FST_FOR_MV_Y (volatile unsigned int *)((0x3c11 << 2) + 0xff620000) ++#define HEVC_SCD_FOR_MV_X (0x3c12) ++#define P_HEVC_SCD_FOR_MV_X (volatile unsigned int *)((0x3c12 << 2) + 0xff620000) ++#define HEVC_SCD_FOR_MV_Y (0x3c13) ++#define P_HEVC_SCD_FOR_MV_Y (volatile unsigned int *)((0x3c13 << 2) + 0xff620000) ++#define HEVC_FST_BAK_MV_X (0x3c14) ++#define P_HEVC_FST_BAK_MV_X (volatile unsigned int *)((0x3c14 << 2) + 0xff620000) ++#define HEVC_FST_BAK_MV_Y (0x3c15) ++#define P_HEVC_FST_BAK_MV_Y (volatile unsigned int *)((0x3c15 << 2) + 0xff620000) ++#define HEVC_SCD_BAK_MV_X (0x3c16) ++#define P_HEVC_SCD_BAK_MV_X (volatile unsigned int *)((0x3c16 << 2) + 0xff620000) ++#define HEVC_SCD_BAK_MV_Y (0x3c17) ++#define P_HEVC_SCD_BAK_MV_Y (volatile unsigned int *)((0x3c17 << 2) + 0xff620000) ++// Bit 7:4 -- read_buffer_interlace 0-progressive, 1-interlace, used in VC1 ++// bit 3 -- disable_new_stcode_search_fix // From GXM ++// bit 2 -- weighting_prediction ++// bit 1 -- mb_weighting_flag ++// bit 0 -- slice_weighting_flag ++#define HEVC_VLD_DECODE_CONTROL (0x3c18) ++#define P_HEVC_VLD_DECODE_CONTROL (volatile unsigned int *)((0x3c18 << 2) + 0xff620000) ++#define HEVC_VLD_REVERVED_19 (0x3c19) ++#define P_HEVC_VLD_REVERVED_19 (volatile unsigned int *)((0x3c19 << 2) + 0xff620000) ++#define HEVC_VIFF_BIT_CNT (0x3c1a) ++#define P_HEVC_VIFF_BIT_CNT (volatile unsigned int *)((0x3c1a << 2) + 0xff620000) ++#define HEVC_BYTE_ALIGN_PEAK_HI (0x3c1b) ++#define P_HEVC_BYTE_ALIGN_PEAK_HI (volatile unsigned int *)((0x3c1b << 2) + 0xff620000) ++#define HEVC_BYTE_ALIGN_PEAK_LO (0x3c1c) ++#define P_HEVC_BYTE_ALIGN_PEAK_LO (volatile unsigned int *)((0x3c1c << 2) + 0xff620000) ++#define HEVC_NEXT_ALIGN_PEAK (0x3c1d) ++#define P_HEVC_NEXT_ALIGN_PEAK (volatile unsigned int *)((0x3c1d << 2) + 0xff620000) ++// bit 31 : byte_aligned_zero_23_from_org // From GXM ++// bit 30 : force_shift_out_drop_flag_zero // From GXM ++// bit 29 : en_st_protect_from_org // From GXM ++// bit 28 : enable_halt_decode_start_voff ++// bit 27 : disable_C_pred_check ++// bit 26 : disable_I4_pred_check ++// bit 25 : disable_I16_pred_check ++// bit 24 : check_avs_1st_drop ++// bit 23 : enable_cabac_protect // From GXM ++// bit 22 : enable_avs_drop_more ++// bit 21 : reset_avs_drop_ptr ++// bit 20 : reset_cabac_use_next_at_end_req ++// bit 19 : vc1_inv_intra_co_mb_ref_rd ++// bit 18 : vc1_inv_co_mb_ref_rd ++// bit 17 : vc1_inv_intra_co_mb_ref_wr ++// bit 16 : vc1_inv_co_mb_ref_wr ++// bit 15 : disable_mv_cal_begin_only ++// bit 14 : avs_drop_enable ++// bit 13:12 : avs_drop_ptr ++// bit 11:8 : avs_demu_ctl_reg ++// bit 7 : avs_enable ++// bit 6 : disable_dblk_hcmd ++// bit 5 : disable_mc_hcmd ++// bit 4 : first_mode3_set enable ++// bit 3 : first_mode3 ++// bit 2:1 : vc1_profile 0-SP, 1-MP, 2-reserved, 3-AP ++// bit 0 : vc1_enable ++#define HEVC_VC1_CONTROL_REG (0x3c1e) ++#define P_HEVC_VC1_CONTROL_REG (volatile unsigned int *)((0x3c1e << 2) + 0xff620000) ++#define HEVC_PMV1_X (0x3c20) ++#define P_HEVC_PMV1_X (volatile unsigned int *)((0x3c20 << 2) + 0xff620000) ++#define HEVC_PMV1_Y (0x3c21) ++#define P_HEVC_PMV1_Y (volatile unsigned int *)((0x3c21 << 2) + 0xff620000) ++#define HEVC_PMV2_X (0x3c22) ++#define P_HEVC_PMV2_X (volatile unsigned int *)((0x3c22 << 2) + 0xff620000) ++#define HEVC_PMV2_Y (0x3c23) ++#define P_HEVC_PMV2_Y (volatile unsigned int *)((0x3c23 << 2) + 0xff620000) ++#define HEVC_PMV3_X (0x3c24) ++#define P_HEVC_PMV3_X (volatile unsigned int *)((0x3c24 << 2) + 0xff620000) ++#define HEVC_PMV3_Y (0x3c25) ++#define P_HEVC_PMV3_Y (volatile unsigned int *)((0x3c25 << 2) + 0xff620000) ++#define HEVC_PMV4_X (0x3c26) ++#define P_HEVC_PMV4_X (volatile unsigned int *)((0x3c26 << 2) + 0xff620000) ++#define HEVC_PMV4_Y (0x3c27) ++#define P_HEVC_PMV4_Y (volatile unsigned int *)((0x3c27 << 2) + 0xff620000) ++// Can't use the same address for different defines ++// Therefore, create a single define that covers both ++// Only appears to be used in micro-code since the VLD hardware is ++// hard coded. ++// `define M4_TABLE_SELECT 8'h28 // Does this exist in HW ? Added from register_mp2.h ++// `define M4_TABLE_OUTPUT 8'h28 // Does this exist in HW ? Added from register_mp2.h ++#define HEVC_M4_TABLE_SELECT (0x3c28) ++#define P_HEVC_M4_TABLE_SELECT (volatile unsigned int *)((0x3c28 << 2) + 0xff620000) ++#define HEVC_M4_CONTROL_REG (0x3c29) ++#define P_HEVC_M4_CONTROL_REG (volatile unsigned int *)((0x3c29 << 2) + 0xff620000) ++#define HEVC_BLOCK_NUM (0x3c2a) ++#define P_HEVC_BLOCK_NUM (volatile unsigned int *)((0x3c2a << 2) + 0xff620000) ++#define HEVC_PATTERN_CODE (0x3c2b) ++#define P_HEVC_PATTERN_CODE (volatile unsigned int *)((0x3c2b << 2) + 0xff620000) ++#define HEVC_MB_INFO (0x3c2c) ++#define P_HEVC_MB_INFO (volatile unsigned int *)((0x3c2c << 2) + 0xff620000) ++#define HEVC_VLD_DC_PRED (0x3c2d) ++#define P_HEVC_VLD_DC_PRED (volatile unsigned int *)((0x3c2d << 2) + 0xff620000) ++#define HEVC_VLD_ERROR_MASK (0x3c2e) ++#define P_HEVC_VLD_ERROR_MASK (volatile unsigned int *)((0x3c2e << 2) + 0xff620000) ++#define HEVC_VLD_DC_PRED_C (0x3c2f) ++#define P_HEVC_VLD_DC_PRED_C (volatile unsigned int *)((0x3c2f << 2) + 0xff620000) ++#define HEVC_LAST_SLICE_MV_ADDR (0x3c30) ++#define P_HEVC_LAST_SLICE_MV_ADDR (volatile unsigned int *)((0x3c30 << 2) + 0xff620000) ++#define HEVC_LAST_MVX (0x3c31) ++#define P_HEVC_LAST_MVX (volatile unsigned int *)((0x3c31 << 2) + 0xff620000) ++#define HEVC_LAST_MVY (0x3c32) ++#define P_HEVC_LAST_MVY (volatile unsigned int *)((0x3c32 << 2) + 0xff620000) ++#define HEVC_VLD_C38 (0x3c38) ++#define P_HEVC_VLD_C38 (volatile unsigned int *)((0x3c38 << 2) + 0xff620000) ++#define HEVC_VLD_C39 (0x3c39) ++#define P_HEVC_VLD_C39 (volatile unsigned int *)((0x3c39 << 2) + 0xff620000) ++#define HEVC_VLD_STATUS (0x3c3a) ++#define P_HEVC_VLD_STATUS (volatile unsigned int *)((0x3c3a << 2) + 0xff620000) ++#define HEVC_VLD_SHIFT_STATUS (0x3c3b) ++#define P_HEVC_VLD_SHIFT_STATUS (volatile unsigned int *)((0x3c3b << 2) + 0xff620000) ++// `define VLD_SHIFT_INFO 8'h3b // Does this exist in HW ? used in $ucode/mpeg4 ++#define HEVC_VOFF_STATUS (0x3c3c) ++#define P_HEVC_VOFF_STATUS (volatile unsigned int *)((0x3c3c << 2) + 0xff620000) ++#define HEVC_VLD_C3D (0x3c3d) ++#define P_HEVC_VLD_C3D (volatile unsigned int *)((0x3c3d << 2) + 0xff620000) ++#define HEVC_VLD_DBG_INDEX (0x3c3e) ++#define P_HEVC_VLD_DBG_INDEX (volatile unsigned int *)((0x3c3e << 2) + 0xff620000) ++// vld_buff_info -- (index == 0) ++// Bit11] halt_decode_start_voff ++// Bit10] C_pred_error ++// Bit[9] I4_pred_error ++// Bit[8] I16_pred_error ++// Bit[7:6] mv_UR_ready_cnt; ++// Bit[5] vld_wr_idx ++// Bit[4] iq_rd_idx ++// Bit[3] vld_vi_block_rdy_1 ++// Bit[2] vld_vi_block_rdy_2 ++// Bit[1] voff_empty_1 ++// Bit[0] voff_empty_2 ++// cabac_buff_info_0 -- (index == 1) ++// Bit[31] shift_data_ready ++// Bit[30:29] Reserved ++// Bit[28:24] cabac_buffer_ptr ++// Bit[23:0] cabac_buffer ++// cabac_buff_info_1 -- (index == 2) ++// Bit[31:29] Reserved ++// Bit[28:20] Drange ++// Bit[19:16] bin_count_4 ++// Bit[15:13] Reserved ++// Bit[12:6] context_mem_do ++// Bit[5:3] coeff_state ++// Bit[2:0] mvd_state ++// h264_mv_present -- (index == 3) ++// Bit[31:16] mv_present_l0 ++// Bit[15:0] mv_present_l1 ++// h264_mv_cal_info_0 -- (index == 4) ++// [31:28] mv_cal_state ++// [27:24] direct_spatial_cnt ++// Bit[23:21] Reserved ++// Bit[20] mv_UR_ready_for_mv_cal ++// Bit[19] co_mb_mem_ready_for_mv_cal ++// Bit[18] mc_dblk_cmd_if_busy ++// Bit[17] h264_co_mb_wr_busy ++// Bit[16] H264_cbp_blk_ready ++// Bit[15] mc_hcmd_rrdy ++// Bit[14] mc_hcmd_srdy ++// Bit[13] mc_cmd_if_ready ++// Bit[12] mc_hcmd_mv_available ++// Bit[11:8] mc_cmd_if_state ++// Bit[7] dblk_hcmd_rrdy ++// Bit[6] dblk_hcmd_srdy ++// Bit[5] dblk_cmd_if_ready ++// Bit[4] dblk_hcmd_mv_available ++// Bit[3:0] dblk_cmd_if_state ++// h264_mv_cal_info_1 -- (index == 5) ++// Bit[31:29] Reserved ++// Bit[28:24] total_mvd_num_l0 ++// Bit[23:21] Reserved ++// Bit[20:16] mv_cal_ptr_l0 ++// Bit[15:13] Reserved ++// Bit[12:8] mc_hcmd_ptr_l0 ++// Bit[7:5] Reserved ++// Bit[4:0] dblk_hcmd_ptr_l0 ++// h264_mv_cal_info_2 -- (index == 6) ++// Bit[31:29] Reserved ++// Bit[28:24] total_mvd_num_l1 ++// Bit[23:21] Reserved ++// Bit[20:16] mv_cal_ptr_l1 ++// Bit[15:13] Reserved ++// Bit[12:8] mc_hcmd_ptr_l1 ++// Bit[7:5] Reserved ++// Bit[4:0] dblk_hcmd_ptr_l1 ++// h264_co_mb_info -- (index == 7) ++// Bit[31:26] Reserved ++// Bit[25] mv_scale_cal_busy ++// Bit[24:20] co_mv_count ++// Bit[19:16] co_mv_process_state ++// Bit[15] h264_co_mb_rd_busy ++// Bit[15] h264_co_mb_rd_ready ++// Bit[13:12] co_mv_transfer_block_cnt ++// Bit[11:8] co_mv_transfer_ptr ++// Bit[7] co_mv_POC_l1_busy ++// Bit[6] h264_weight_scale_cal_en ++// Bit[5] weight_cal_busy ++// Bit[4] weight_cal_not_finished ++// Bit[3:0] weight_process_state ++#define HEVC_VLD_DBG_DATA (0x3c3f) ++#define P_HEVC_VLD_DBG_DATA (volatile unsigned int *)((0x3c3f << 2) + 0xff620000) ++// -------------------------------------------- ++// VIFIFO DDR Interface ++// -------------------------------------------- ++// The VIFIFO start pointer into DDR memory is a 32-bit number ++// The Start pointer will automatically be truncated to land on ++// an 8-byte boundary. That is, bits [2:0] = 0; ++#define HEVC_VLD_MEM_VIFIFO_START_PTR (0x3c40) ++#define P_HEVC_VLD_MEM_VIFIFO_START_PTR (volatile unsigned int *)((0x3c40 << 2) + 0xff620000) ++// The current pointer points so some location between the START and END ++// pointers. The current pointer is a BYTE pointer. That is, you can ++// point to any BYTE address within the START/END range ++#define HEVC_VLD_MEM_VIFIFO_CURR_PTR (0x3c41) ++#define P_HEVC_VLD_MEM_VIFIFO_CURR_PTR (volatile unsigned int *)((0x3c41 << 2) + 0xff620000) ++#define HEVC_VLD_MEM_VIFIFO_END_PTR (0x3c42) ++#define P_HEVC_VLD_MEM_VIFIFO_END_PTR (volatile unsigned int *)((0x3c42 << 2) + 0xff620000) ++#define HEVC_VLD_MEM_VIFIFO_BYTES_AVAIL (0x3c43) ++#define P_HEVC_VLD_MEM_VIFIFO_BYTES_AVAIL (volatile unsigned int *)((0x3c43 << 2) + 0xff620000) ++// VIFIFO FIFO Control ++// bit [31:24] viff_empty_int_enable_cpu[7:0] ++// bit [23:16] viff_empty_int_enable_amrisc[7:0] ++// -bit 23 Video BUFFER < 0x400 Bytes ++// -bit 22 Video BUFFER < 0x200 Bytes ++// -bit 21 Video BUFFER < 0x100 Bytes ++// -bit 20 Video BUFFER < 0x80 Bytes ++// -bit 19 Video BUFFER < 0x40 Bytes ++// -bit 18 Video BUFFER < 0x20 Bytes ++// -bit 17 vififo < 16 double words ++// -bit 16 vififo < 8 double words ++// bit [15:13] unused ++// bit [12] A_urgent ++// bit [11] transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request ++// bit [10] use_level Set this bit to 1 to enable filling of the FIFO controlled by the buffer ++// level control. If this bit is 0, then use bit[1] to control the enabling of filling ++// bit [9] Data Ready. This bit is set when data can be popped ++// bit [8] fill busy This bit will be high when we're fetching data from the DDR memory ++// To reset this module, set cntl_enable = 0, and then wait for busy = 0. ++// After that you can pulse cntl_init to start over ++// bit [7] init_with_cntl_init ++// bit [6] reserved ++// bits [5:3] endian: see $lib/rtl/ddr_endian.v ++// bit [2] cntl_empty_en Set to 1 to enable reading the DDR memory FIFO ++// Set cntl_empty_en = cntl_fill_en = 0 when pulsing cntl_init ++// bit [1] cntl_fill_en Set to 1 to enable reading data from DDR memory ++// bit [0] cntl_init: After setting the read pointers, sizes, channel masks ++// and read masks, set this bit to 1 and then to 0 ++// NOTE: You don't need to pulse cntl_init if only the start address is ++// being changed ++#define HEVC_VLD_MEM_VIFIFO_CONTROL (0x3c44) ++#define P_HEVC_VLD_MEM_VIFIFO_CONTROL (volatile unsigned int *)((0x3c44 << 2) + 0xff620000) ++// -------------------------------------------- ++// VIFIFO Buffer Level Manager ++// -------------------------------------------- ++#define HEVC_VLD_MEM_VIFIFO_WP (0x3c45) ++#define P_HEVC_VLD_MEM_VIFIFO_WP (volatile unsigned int *)((0x3c45 << 2) + 0xff620000) ++#define HEVC_VLD_MEM_VIFIFO_RP (0x3c46) ++#define P_HEVC_VLD_MEM_VIFIFO_RP (volatile unsigned int *)((0x3c46 << 2) + 0xff620000) ++#define HEVC_VLD_MEM_VIFIFO_LEVEL (0x3c47) ++#define P_HEVC_VLD_MEM_VIFIFO_LEVEL (volatile unsigned int *)((0x3c47 << 2) + 0xff620000) ++// ++// bit [8] use_parser_video2_wp ++// bit [7] vbuf2_out_manual ++// bit [6] vbuf_out_manual ++// bit [5] empty (ReadOnly) ++// bit [4] full (ReadOnly) ++// bit [3:2] reserved ++// bit [1] manual mode Set to 1 for manual write pointer mode ++// bit [0] Init Set high then low after everything has been initialized ++#define HEVC_VLD_MEM_VIFIFO_BUF_CNTL (0x3c48) ++#define P_HEVC_VLD_MEM_VIFIFO_BUF_CNTL (volatile unsigned int *)((0x3c48 << 2) + 0xff620000) ++// bit 31:16 -- drop_bytes ++// bit 15:14 -- drop_status (Read-Only) ++// bit 13:12 -- sync_match_position (Read-Only) ++// bit 11:6 -- reserved ++// bit 5:4 -- TIME_STAMP_NUMBER, 0-32bits, 1-64bits, 2-96bits, 3-128bits ++// bit 3 -- stamp_soft_reset ++// bit 2 -- TIME_STAMP_length_enable ++// bit 1 -- TIME_STAMP_sync64_enable ++// bit 0 -- TIME_STAMP_enable ++#define HEVC_VLD_TIME_STAMP_CNTL (0x3c49) ++#define P_HEVC_VLD_TIME_STAMP_CNTL (volatile unsigned int *)((0x3c49 << 2) + 0xff620000) ++// bit 31:0 -- TIME_STAMP_SYNC_CODE_0 ++#define HEVC_VLD_TIME_STAMP_SYNC_0 (0x3c4a) ++#define P_HEVC_VLD_TIME_STAMP_SYNC_0 (volatile unsigned int *)((0x3c4a << 2) + 0xff620000) ++// bit 31:0 -- TIME_STAMP_SYNC_CODE_1 ++#define HEVC_VLD_TIME_STAMP_SYNC_1 (0x3c4b) ++#define P_HEVC_VLD_TIME_STAMP_SYNC_1 (volatile unsigned int *)((0x3c4b << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_0 ++#define HEVC_VLD_TIME_STAMP_0 (0x3c4c) ++#define P_HEVC_VLD_TIME_STAMP_0 (volatile unsigned int *)((0x3c4c << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_1 ++#define HEVC_VLD_TIME_STAMP_1 (0x3c4d) ++#define P_HEVC_VLD_TIME_STAMP_1 (volatile unsigned int *)((0x3c4d << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_2 ++#define HEVC_VLD_TIME_STAMP_2 (0x3c4e) ++#define P_HEVC_VLD_TIME_STAMP_2 (volatile unsigned int *)((0x3c4e << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_3 ++#define HEVC_VLD_TIME_STAMP_3 (0x3c4f) ++#define P_HEVC_VLD_TIME_STAMP_3 (volatile unsigned int *)((0x3c4f << 2) + 0xff620000) ++// bit 31:0 TIME_STAMP_LENGTH ++#define HEVC_VLD_TIME_STAMP_LENGTH (0x3c50) ++#define P_HEVC_VLD_TIME_STAMP_LENGTH (volatile unsigned int *)((0x3c50 << 2) + 0xff620000) ++// bit 15:0 vififo_rd_count ++#define HEVC_VLD_MEM_VIFIFO_WRAP_COUNT (0x3c51) ++#define P_HEVC_VLD_MEM_VIFIFO_WRAP_COUNT (volatile unsigned int *)((0x3c51 << 2) + 0xff620000) ++// bit 29:24 A_brst_num ++// bit 21:16 A_id ++// bit 15:0 level_hold ++#define HEVC_VLD_MEM_VIFIFO_MEM_CTL (0x3c52) ++#define P_HEVC_VLD_MEM_VIFIFO_MEM_CTL (volatile unsigned int *)((0x3c52 << 2) + 0xff620000) ++#define HEVC_VLD_MEM_VBUF_RD_PTR (0x3c53) ++#define P_HEVC_VLD_MEM_VBUF_RD_PTR (volatile unsigned int *)((0x3c53 << 2) + 0xff620000) ++#define HEVC_VLD_MEM_VBUF2_RD_PTR (0x3c54) ++#define P_HEVC_VLD_MEM_VBUF2_RD_PTR (volatile unsigned int *)((0x3c54 << 2) + 0xff620000) ++#define HEVC_VLD_MEM_SWAP_ADDR (0x3c55) ++#define P_HEVC_VLD_MEM_SWAP_ADDR (volatile unsigned int *)((0x3c55 << 2) + 0xff620000) ++// bit[23:16] - swap_d_count (Read Only) ++// bit[15:8] - swap_a_count (Read Only) ++// bit [7] - swap busy (Read Only) ++// bit [6:2] - reserved ++// bit [1] - 1 - STORE to Memory, 0 - LOAD from Memory ++// bit [0] - swap active ++#define HEVC_VLD_MEM_SWAP_CTL (0x3c56) ++#define P_HEVC_VLD_MEM_SWAP_CTL (volatile unsigned int *)((0x3c56 << 2) + 0xff620000) ++// ++// Closing file: vld_regs.h ++// ++// ++// Reading file: iqidct_regs.h ++// ++//======================================================================== ++// IQ/IDCT module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_VDEC_IQIDCT_CBUS_BASE = 0x0e ++// ----------------------------------------------- ++#define HCODEC_VCOP_CTRL_REG (0x1e00) ++#define P_HCODEC_VCOP_CTRL_REG (volatile unsigned int *)((0x1e00 << 2) + 0xff620000) ++#define HCODEC_QP_CTRL_REG (0x1e01) ++#define P_HCODEC_QP_CTRL_REG (volatile unsigned int *)((0x1e01 << 2) + 0xff620000) ++#define HCODEC_INTRA_QUANT_MATRIX (0x1e02) ++#define P_HCODEC_INTRA_QUANT_MATRIX (volatile unsigned int *)((0x1e02 << 2) + 0xff620000) ++#define HCODEC_NON_I_QUANT_MATRIX (0x1e03) ++#define P_HCODEC_NON_I_QUANT_MATRIX (volatile unsigned int *)((0x1e03 << 2) + 0xff620000) ++#define HCODEC_DC_SCALER (0x1e04) ++#define P_HCODEC_DC_SCALER (volatile unsigned int *)((0x1e04 << 2) + 0xff620000) ++#define HCODEC_DC_AC_CTRL (0x1e05) ++#define P_HCODEC_DC_AC_CTRL (volatile unsigned int *)((0x1e05 << 2) + 0xff620000) ++// `define RV_AI_CTRL 8'h05 // ONLY for $ucode/real/amrisc/rv.s reg value from apollo ++#define HCODEC_DC_AC_SCALE_MUL (0x1e06) ++#define P_HCODEC_DC_AC_SCALE_MUL (volatile unsigned int *)((0x1e06 << 2) + 0xff620000) ++#define HCODEC_DC_AC_SCALE_DIV (0x1e07) ++#define P_HCODEC_DC_AC_SCALE_DIV (volatile unsigned int *)((0x1e07 << 2) + 0xff620000) ++// `define DC_AC_SCALE_RESULT 8'h06 ++// `define RESERVED_E07 8'h07 ++#define HCODEC_POWER_CTL_IQIDCT (0x1e08) ++#define P_HCODEC_POWER_CTL_IQIDCT (volatile unsigned int *)((0x1e08 << 2) + 0xff620000) ++#define HCODEC_RV_AI_Y_X (0x1e09) ++#define P_HCODEC_RV_AI_Y_X (volatile unsigned int *)((0x1e09 << 2) + 0xff620000) ++#define HCODEC_RV_AI_U_X (0x1e0a) ++#define P_HCODEC_RV_AI_U_X (volatile unsigned int *)((0x1e0a << 2) + 0xff620000) ++#define HCODEC_RV_AI_V_X (0x1e0b) ++#define P_HCODEC_RV_AI_V_X (volatile unsigned int *)((0x1e0b << 2) + 0xff620000) ++// bit 15:0 will count up when rv_ai_mb finished when non zero ++// and rv_ai_mb_finished_int will be generate when this is not zero ++#define HCODEC_RV_AI_MB_COUNT (0x1e0c) ++#define P_HCODEC_RV_AI_MB_COUNT (volatile unsigned int *)((0x1e0c << 2) + 0xff620000) ++// For H264 I in PB picture Use -- dma type : h264_next_intra_dma ++#define HCODEC_NEXT_INTRA_DMA_ADDRESS (0x1e0d) ++#define P_HCODEC_NEXT_INTRA_DMA_ADDRESS (volatile unsigned int *)((0x1e0d << 2) + 0xff620000) ++// Bit 16 -- dcac_dma_read_cache_disable ++// Bit 15 -- dcac_dma_urgent ++// Bit 14 -- nv21_swap ++// Bit 13 -- nv21_top_dma ++// Bit 12 -- reset_rv_ai_wait_rd_data ++// Bit 11 -- set_rv_ai_wait_rd_data [12:11] = 3 means only dec 1 (For Skipped MB of MBAFF) ++// Bit 10 -- rv_ai_wait_rd_data (Read Only) ++// Bit 9 -- enable_rv_ai_wait_rd_data ++// Bit 8 -- disable_vc1_mv_update ++// Bit 7 -- pred_dc_signed ++// Bit 6 -- inc_vld_ready_count ++// Bit 5 -- dec_vld_ready_count ++// Bit 4 -- disable_ref_bidir_fix ++// Bit 3 -- disable_MV_UL_l1_bot_fix ++// Bit 2 -- disable_mb_aff_fix ++// Bit 1 -- canvas_addr_7 ++// Bit 0 -- constrained_intra_pred_flag for H264 ++#define HCODEC_IQIDCT_CONTROL (0x1e0e) ++#define P_HCODEC_IQIDCT_CONTROL (volatile unsigned int *)((0x1e0e << 2) + 0xff620000) ++// Bit[31:19] Reserved ++// Bit[18] iq_waiting ++// Bit[17] iq_om_wr_idx ++// Bit[16] iq_om_rd_idx ++// Bit[15] iq_om_busy ++// Bit[14] iq_om_2_busy ++// Bit[13] idx_fifo_0 ++// Bit[12] idx_fifo_1 ++// Bit[11] idx_fifo_2 ++// Bit[10] idx_fifo_3 ++// Bit[9] idx_fifo_4 ++// Bit[8] idx_fifo_5 ++// Bit[7] idx_fifo_6 ++// Bit[6] idx_fifo_7 ++// Bit[5:3] idx_fifo_wp ++// Bit[2:0] idx_fifo_rp ++#define HCODEC_IQIDCT_DEBUG_INFO_0 (0x1e0f) ++#define P_HCODEC_IQIDCT_DEBUG_INFO_0 (volatile unsigned int *)((0x1e0f << 2) + 0xff620000) ++// For RTL Simulation Only ++#define HCODEC_DEBLK_CMD (0x1e10) ++#define P_HCODEC_DEBLK_CMD (volatile unsigned int *)((0x1e10 << 2) + 0xff620000) ++// Bit[15+16] ds_mc_valid_2 ++// Bit[14+16] new_idct1_rd_idx_2 ++// Bit[13+16] new_idct1_wr_idx_2 ++// Bit[12+16] idct1_buff0_busy_2 ++// Bit[11+16] idct1_buff1_busy_2 ++// Bit[10+16] new_idct1_busy_2 ++// Bit[9+16] iq_om_8val_2 ++// Bit[8+16] idct1_pipe_busy_2 ++// Bit[7+16] wait_mb_left_finish_hold_2 ++// Bit[6+16] new_idct2_rd_idx_2 ++// Bit[5+16] new_idct2_wr_idx_2 ++// Bit[4+16] idct2_buff0_busy_2 ++// Bit[3+16] idct2_buff1_busy_2 ++// Bit[2+16] idct2_en_2 ++// Bit[1+16] new_idct2_busy_2 ++// Bit[0+16] new_idct1_ready_2 ++// Bit[15] ds_mc_valid_1 ++// Bit[14] new_idct1_rd_idx_1 ++// Bit[13] new_idct1_wr_idx_1 ++// Bit[12] idct1_buff0_busy_1 ++// Bit[11] idct1_buff1_busy_1 ++// Bit[10] new_idct1_busy_1 ++// Bit[9] iq_om_8val_1 ++// Bit[8] idct1_pipe_busy_1 ++// Bit[7] wait_mb_left_finish_hold_1 ++// Bit[6] new_idct2_rd_idx_1 ++// Bit[5] new_idct2_wr_idx_1 ++// Bit[4] idct2_buff0_busy_1 ++// Bit[3] idct2_buff1_busy_1 ++// Bit[2] idct2_en_1 ++// Bit[1] new_idct2_busy_1 ++// Bit[0] new_idct1_ready_1 ++#define HCODEC_IQIDCT_DEBUG_IDCT (0x1e11) ++#define P_HCODEC_IQIDCT_DEBUG_IDCT (volatile unsigned int *)((0x1e11 << 2) + 0xff620000) ++// bit 31 -- convas_enable ++// bit 30:24 -- convas_x_count ( 8 pixels / 64 bits ) ++// bit 23:16 -- convas_y_count ++// bit 15 -- dcac_dma_busy ++// bit 14 -- dcac_dma_read_cache_active ++// bit 13:8 -- dcac_dma_count ++// bit 7 -- dcac_dma_rw ++// bit 6 -- dcac_skip_read_mode ++// bit 5:0 -- dcac_dma_offset ++#define HCODEC_DCAC_DMA_CTRL (0x1e12) ++#define P_HCODEC_DCAC_DMA_CTRL (volatile unsigned int *)((0x1e12 << 2) + 0xff620000) ++// when (convas_enable == 0 ) ++// bit 31:0 dcac_dma_addr ++// when (convas_enable == 1 ) ++// bit 31:25 canvas_addr (7 bits) ++// bit 24:12 convas_y_start ( 13 btis ) ++// bit 11:0 convas_x_start ( 12 btis ) ++#define HCODEC_DCAC_DMA_ADDRESS (0x1e13) ++#define P_HCODEC_DCAC_DMA_ADDRESS (volatile unsigned int *)((0x1e13 << 2) + 0xff620000) ++// bit 7:0 -- dcac_cpu_addr ++#define HCODEC_DCAC_CPU_ADDRESS (0x1e14) ++#define P_HCODEC_DCAC_CPU_ADDRESS (volatile unsigned int *)((0x1e14 << 2) + 0xff620000) ++// bit 31:0 -- dcac_cpu_data ++#define HCODEC_DCAC_CPU_DATA (0x1e15) ++#define P_HCODEC_DCAC_CPU_DATA (volatile unsigned int *)((0x1e15 << 2) + 0xff620000) ++// bit 31:19 -- reserved ++// bit 18:16 -- block_num_reg -- Read-Only ++// bit 15:0 -- dcac_mb_count ++#define HCODEC_DCAC_MB_COUNT (0x1e16) ++#define P_HCODEC_DCAC_MB_COUNT (volatile unsigned int *)((0x1e16 << 2) + 0xff620000) ++// bit 31:18 -- reserved ++// For H264 : ++// bit 17:2 -- h264_quant ++// bit 11:6 -- h264_quant_c ++// bit 5:0 -- h264_quant_c ++// For VC1 : ++// bit 17 -- qindex_GT_8 ++// bit 16 -- HalfQPStep ++// bit 15:12 -- eQuantMode ++// bit 11:6 -- AltPQuant ++// bit 5:0 -- PQuant ++// ++#define HCODEC_IQ_QUANT (0x1e17) ++#define P_HCODEC_IQ_QUANT (volatile unsigned int *)((0x1e17 << 2) + 0xff620000) ++// bit 31:24 -- bitplane_width ++// bit 23:16 -- bitplane_height ++// bit 15:14 -- bitplane_start_x ++// bit 13:12 -- bitplane_start_y ++// bit 11:4 -- reserved ++// bit 3:1 -- bitplane_type ++// bit 0 -- bitplane_busy ++#define HCODEC_VC1_BITPLANE_CTL (0x1e18) ++#define P_HCODEC_VC1_BITPLANE_CTL (volatile unsigned int *)((0x1e18 << 2) + 0xff620000) ++// bit 24:16 -- wq_param1 ++// bit 8: 0 -- wq_param0 ++#define HCODEC_AVSP_IQ_WQ_PARAM_01 (0x1e19) ++#define P_HCODEC_AVSP_IQ_WQ_PARAM_01 (volatile unsigned int *)((0x1e19 << 2) + 0xff620000) ++// bit 24:16 -- wq_param3 ++// bit 8: 0 -- wq_param2 ++#define HCODEC_AVSP_IQ_WQ_PARAM_23 (0x1e1a) ++#define P_HCODEC_AVSP_IQ_WQ_PARAM_23 (volatile unsigned int *)((0x1e1a << 2) + 0xff620000) ++// bit 24:16 -- wq_param5 ++// bit 8: 0 -- wq_param4 ++#define HCODEC_AVSP_IQ_WQ_PARAM_45 (0x1e1b) ++#define P_HCODEC_AVSP_IQ_WQ_PARAM_45 (volatile unsigned int *)((0x1e1b << 2) + 0xff620000) ++// bit 31 -- weight_quant_en ++// bit 17:16 -- current_scene_model ++// bit 12: 8 -- chroma_qp_delta_cr ++// bit 4: 0 -- chroma_qp_delta_cb ++#define HCODEC_AVSP_IQ_CTL (0x1e1c) ++#define P_HCODEC_AVSP_IQ_CTL (volatile unsigned int *)((0x1e1c << 2) + 0xff620000) ++//====================================== ++// VCOP Control Register Bits ++// ++//====================================== ++ //`define IQIDCT_RESET 16'h0001 // Bit 0 ++//====================================== ++// QP Control Register Bits ++// ++//====================================== ++// Duplicate Address: When actually used ++// please move to a different address ++// `define FLD_DCT_TYPE 16'h0100 // Bit 8 0 = Frame DCT; 1 = field DCT ++// ++// Closing file: iqidct_regs.h ++// ++// ++// Reading file: iqidct_regs.h ++// ++//======================================================================== ++// IQ/IDCT module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_VDEC_IQIDCT_CBUS_BASE = 0x0e ++// ----------------------------------------------- ++#define VDEC2_VCOP_CTRL_REG (0x2e00) ++#define P_VDEC2_VCOP_CTRL_REG (volatile unsigned int *)((0x2e00 << 2) + 0xff620000) ++#define VDEC2_QP_CTRL_REG (0x2e01) ++#define P_VDEC2_QP_CTRL_REG (volatile unsigned int *)((0x2e01 << 2) + 0xff620000) ++#define VDEC2_INTRA_QUANT_MATRIX (0x2e02) ++#define P_VDEC2_INTRA_QUANT_MATRIX (volatile unsigned int *)((0x2e02 << 2) + 0xff620000) ++#define VDEC2_NON_I_QUANT_MATRIX (0x2e03) ++#define P_VDEC2_NON_I_QUANT_MATRIX (volatile unsigned int *)((0x2e03 << 2) + 0xff620000) ++#define VDEC2_DC_SCALER (0x2e04) ++#define P_VDEC2_DC_SCALER (volatile unsigned int *)((0x2e04 << 2) + 0xff620000) ++#define VDEC2_DC_AC_CTRL (0x2e05) ++#define P_VDEC2_DC_AC_CTRL (volatile unsigned int *)((0x2e05 << 2) + 0xff620000) ++// `define RV_AI_CTRL 8'h05 // ONLY for $ucode/real/amrisc/rv.s reg value from apollo ++#define VDEC2_DC_AC_SCALE_MUL (0x2e06) ++#define P_VDEC2_DC_AC_SCALE_MUL (volatile unsigned int *)((0x2e06 << 2) + 0xff620000) ++#define VDEC2_DC_AC_SCALE_DIV (0x2e07) ++#define P_VDEC2_DC_AC_SCALE_DIV (volatile unsigned int *)((0x2e07 << 2) + 0xff620000) ++// `define DC_AC_SCALE_RESULT 8'h06 ++// `define RESERVED_E07 8'h07 ++#define VDEC2_POWER_CTL_IQIDCT (0x2e08) ++#define P_VDEC2_POWER_CTL_IQIDCT (volatile unsigned int *)((0x2e08 << 2) + 0xff620000) ++#define VDEC2_RV_AI_Y_X (0x2e09) ++#define P_VDEC2_RV_AI_Y_X (volatile unsigned int *)((0x2e09 << 2) + 0xff620000) ++#define VDEC2_RV_AI_U_X (0x2e0a) ++#define P_VDEC2_RV_AI_U_X (volatile unsigned int *)((0x2e0a << 2) + 0xff620000) ++#define VDEC2_RV_AI_V_X (0x2e0b) ++#define P_VDEC2_RV_AI_V_X (volatile unsigned int *)((0x2e0b << 2) + 0xff620000) ++// bit 15:0 will count up when rv_ai_mb finished when non zero ++// and rv_ai_mb_finished_int will be generate when this is not zero ++#define VDEC2_RV_AI_MB_COUNT (0x2e0c) ++#define P_VDEC2_RV_AI_MB_COUNT (volatile unsigned int *)((0x2e0c << 2) + 0xff620000) ++// For H264 I in PB picture Use -- dma type : h264_next_intra_dma ++#define VDEC2_NEXT_INTRA_DMA_ADDRESS (0x2e0d) ++#define P_VDEC2_NEXT_INTRA_DMA_ADDRESS (volatile unsigned int *)((0x2e0d << 2) + 0xff620000) ++// Bit 16 -- dcac_dma_read_cache_disable ++// Bit 15 -- dcac_dma_urgent ++// Bit 14 -- nv21_swap ++// Bit 13 -- nv21_top_dma ++// Bit 12 -- reset_rv_ai_wait_rd_data ++// Bit 11 -- set_rv_ai_wait_rd_data [12:11] = 3 means only dec 1 (For Skipped MB of MBAFF) ++// Bit 10 -- rv_ai_wait_rd_data (Read Only) ++// Bit 9 -- enable_rv_ai_wait_rd_data ++// Bit 8 -- disable_vc1_mv_update ++// Bit 7 -- pred_dc_signed ++// Bit 6 -- inc_vld_ready_count ++// Bit 5 -- dec_vld_ready_count ++// Bit 4 -- disable_ref_bidir_fix ++// Bit 3 -- disable_MV_UL_l1_bot_fix ++// Bit 2 -- disable_mb_aff_fix ++// Bit 1 -- canvas_addr_7 ++// Bit 0 -- constrained_intra_pred_flag for H264 ++#define VDEC2_IQIDCT_CONTROL (0x2e0e) ++#define P_VDEC2_IQIDCT_CONTROL (volatile unsigned int *)((0x2e0e << 2) + 0xff620000) ++// Bit[31:19] Reserved ++// Bit[18] iq_waiting ++// Bit[17] iq_om_wr_idx ++// Bit[16] iq_om_rd_idx ++// Bit[15] iq_om_busy ++// Bit[14] iq_om_2_busy ++// Bit[13] idx_fifo_0 ++// Bit[12] idx_fifo_1 ++// Bit[11] idx_fifo_2 ++// Bit[10] idx_fifo_3 ++// Bit[9] idx_fifo_4 ++// Bit[8] idx_fifo_5 ++// Bit[7] idx_fifo_6 ++// Bit[6] idx_fifo_7 ++// Bit[5:3] idx_fifo_wp ++// Bit[2:0] idx_fifo_rp ++#define VDEC2_IQIDCT_DEBUG_INFO_0 (0x2e0f) ++#define P_VDEC2_IQIDCT_DEBUG_INFO_0 (volatile unsigned int *)((0x2e0f << 2) + 0xff620000) ++// For RTL Simulation Only ++#define VDEC2_DEBLK_CMD (0x2e10) ++#define P_VDEC2_DEBLK_CMD (volatile unsigned int *)((0x2e10 << 2) + 0xff620000) ++// Bit[15+16] ds_mc_valid_2 ++// Bit[14+16] new_idct1_rd_idx_2 ++// Bit[13+16] new_idct1_wr_idx_2 ++// Bit[12+16] idct1_buff0_busy_2 ++// Bit[11+16] idct1_buff1_busy_2 ++// Bit[10+16] new_idct1_busy_2 ++// Bit[9+16] iq_om_8val_2 ++// Bit[8+16] idct1_pipe_busy_2 ++// Bit[7+16] wait_mb_left_finish_hold_2 ++// Bit[6+16] new_idct2_rd_idx_2 ++// Bit[5+16] new_idct2_wr_idx_2 ++// Bit[4+16] idct2_buff0_busy_2 ++// Bit[3+16] idct2_buff1_busy_2 ++// Bit[2+16] idct2_en_2 ++// Bit[1+16] new_idct2_busy_2 ++// Bit[0+16] new_idct1_ready_2 ++// Bit[15] ds_mc_valid_1 ++// Bit[14] new_idct1_rd_idx_1 ++// Bit[13] new_idct1_wr_idx_1 ++// Bit[12] idct1_buff0_busy_1 ++// Bit[11] idct1_buff1_busy_1 ++// Bit[10] new_idct1_busy_1 ++// Bit[9] iq_om_8val_1 ++// Bit[8] idct1_pipe_busy_1 ++// Bit[7] wait_mb_left_finish_hold_1 ++// Bit[6] new_idct2_rd_idx_1 ++// Bit[5] new_idct2_wr_idx_1 ++// Bit[4] idct2_buff0_busy_1 ++// Bit[3] idct2_buff1_busy_1 ++// Bit[2] idct2_en_1 ++// Bit[1] new_idct2_busy_1 ++// Bit[0] new_idct1_ready_1 ++#define VDEC2_IQIDCT_DEBUG_IDCT (0x2e11) ++#define P_VDEC2_IQIDCT_DEBUG_IDCT (volatile unsigned int *)((0x2e11 << 2) + 0xff620000) ++// bit 31 -- convas_enable ++// bit 30:24 -- convas_x_count ( 8 pixels / 64 bits ) ++// bit 23:16 -- convas_y_count ++// bit 15 -- dcac_dma_busy ++// bit 14 -- dcac_dma_read_cache_active ++// bit 13:8 -- dcac_dma_count ++// bit 7 -- dcac_dma_rw ++// bit 6 -- dcac_skip_read_mode ++// bit 5:0 -- dcac_dma_offset ++#define VDEC2_DCAC_DMA_CTRL (0x2e12) ++#define P_VDEC2_DCAC_DMA_CTRL (volatile unsigned int *)((0x2e12 << 2) + 0xff620000) ++// when (convas_enable == 0 ) ++// bit 31:0 dcac_dma_addr ++// when (convas_enable == 1 ) ++// bit 31:25 canvas_addr (7 bits) ++// bit 24:12 convas_y_start ( 13 btis ) ++// bit 11:0 convas_x_start ( 12 btis ) ++#define VDEC2_DCAC_DMA_ADDRESS (0x2e13) ++#define P_VDEC2_DCAC_DMA_ADDRESS (volatile unsigned int *)((0x2e13 << 2) + 0xff620000) ++// bit 7:0 -- dcac_cpu_addr ++#define VDEC2_DCAC_CPU_ADDRESS (0x2e14) ++#define P_VDEC2_DCAC_CPU_ADDRESS (volatile unsigned int *)((0x2e14 << 2) + 0xff620000) ++// bit 31:0 -- dcac_cpu_data ++#define VDEC2_DCAC_CPU_DATA (0x2e15) ++#define P_VDEC2_DCAC_CPU_DATA (volatile unsigned int *)((0x2e15 << 2) + 0xff620000) ++// bit 31:19 -- reserved ++// bit 18:16 -- block_num_reg -- Read-Only ++// bit 15:0 -- dcac_mb_count ++#define VDEC2_DCAC_MB_COUNT (0x2e16) ++#define P_VDEC2_DCAC_MB_COUNT (volatile unsigned int *)((0x2e16 << 2) + 0xff620000) ++// bit 31:18 -- reserved ++// For H264 : ++// bit 17:2 -- h264_quant ++// bit 11:6 -- h264_quant_c ++// bit 5:0 -- h264_quant_c ++// For VC1 : ++// bit 17 -- qindex_GT_8 ++// bit 16 -- HalfQPStep ++// bit 15:12 -- eQuantMode ++// bit 11:6 -- AltPQuant ++// bit 5:0 -- PQuant ++// ++#define VDEC2_IQ_QUANT (0x2e17) ++#define P_VDEC2_IQ_QUANT (volatile unsigned int *)((0x2e17 << 2) + 0xff620000) ++// bit 31:24 -- bitplane_width ++// bit 23:16 -- bitplane_height ++// bit 15:14 -- bitplane_start_x ++// bit 13:12 -- bitplane_start_y ++// bit 11:4 -- reserved ++// bit 3:1 -- bitplane_type ++// bit 0 -- bitplane_busy ++#define VDEC2_VC1_BITPLANE_CTL (0x2e18) ++#define P_VDEC2_VC1_BITPLANE_CTL (volatile unsigned int *)((0x2e18 << 2) + 0xff620000) ++// bit 24:16 -- wq_param1 ++// bit 8: 0 -- wq_param0 ++#define VDEC2_AVSP_IQ_WQ_PARAM_01 (0x2e19) ++#define P_VDEC2_AVSP_IQ_WQ_PARAM_01 (volatile unsigned int *)((0x2e19 << 2) + 0xff620000) ++// bit 24:16 -- wq_param3 ++// bit 8: 0 -- wq_param2 ++#define VDEC2_AVSP_IQ_WQ_PARAM_23 (0x2e1a) ++#define P_VDEC2_AVSP_IQ_WQ_PARAM_23 (volatile unsigned int *)((0x2e1a << 2) + 0xff620000) ++// bit 24:16 -- wq_param5 ++// bit 8: 0 -- wq_param4 ++#define VDEC2_AVSP_IQ_WQ_PARAM_45 (0x2e1b) ++#define P_VDEC2_AVSP_IQ_WQ_PARAM_45 (volatile unsigned int *)((0x2e1b << 2) + 0xff620000) ++// bit 31 -- weight_quant_en ++// bit 17:16 -- current_scene_model ++// bit 12: 8 -- chroma_qp_delta_cr ++// bit 4: 0 -- chroma_qp_delta_cb ++#define VDEC2_AVSP_IQ_CTL (0x2e1c) ++#define P_VDEC2_AVSP_IQ_CTL (volatile unsigned int *)((0x2e1c << 2) + 0xff620000) ++//====================================== ++// VCOP Control Register Bits ++// ++//====================================== ++ //`define IQIDCT_RESET 16'h0001 // Bit 0 ++//====================================== ++// QP Control Register Bits ++// ++//====================================== ++// Duplicate Address: When actually used ++// please move to a different address ++// `define FLD_DCT_TYPE 16'h0100 // Bit 8 0 = Frame DCT; 1 = field DCT ++// ++// Closing file: iqidct_regs.h ++// ++// ++// Reading file: iqidct_regs.h ++// ++//======================================================================== ++// IQ/IDCT module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_VDEC_IQIDCT_CBUS_BASE = 0x0e ++// ----------------------------------------------- ++#define HEVC_VCOP_CTRL_REG (0x3e00) ++#define P_HEVC_VCOP_CTRL_REG (volatile unsigned int *)((0x3e00 << 2) + 0xff620000) ++#define HEVC_QP_CTRL_REG (0x3e01) ++#define P_HEVC_QP_CTRL_REG (volatile unsigned int *)((0x3e01 << 2) + 0xff620000) ++#define HEVC_INTRA_QUANT_MATRIX (0x3e02) ++#define P_HEVC_INTRA_QUANT_MATRIX (volatile unsigned int *)((0x3e02 << 2) + 0xff620000) ++#define HEVC_NON_I_QUANT_MATRIX (0x3e03) ++#define P_HEVC_NON_I_QUANT_MATRIX (volatile unsigned int *)((0x3e03 << 2) + 0xff620000) ++#define HEVC_DC_SCALER (0x3e04) ++#define P_HEVC_DC_SCALER (volatile unsigned int *)((0x3e04 << 2) + 0xff620000) ++#define HEVC_DC_AC_CTRL (0x3e05) ++#define P_HEVC_DC_AC_CTRL (volatile unsigned int *)((0x3e05 << 2) + 0xff620000) ++// `define RV_AI_CTRL 8'h05 // ONLY for $ucode/real/amrisc/rv.s reg value from apollo ++#define HEVC_DC_AC_SCALE_MUL (0x3e06) ++#define P_HEVC_DC_AC_SCALE_MUL (volatile unsigned int *)((0x3e06 << 2) + 0xff620000) ++#define HEVC_DC_AC_SCALE_DIV (0x3e07) ++#define P_HEVC_DC_AC_SCALE_DIV (volatile unsigned int *)((0x3e07 << 2) + 0xff620000) ++// `define DC_AC_SCALE_RESULT 8'h06 ++// `define RESERVED_E07 8'h07 ++#define HEVC_POWER_CTL_IQIDCT (0x3e08) ++#define P_HEVC_POWER_CTL_IQIDCT (volatile unsigned int *)((0x3e08 << 2) + 0xff620000) ++#define HEVC_RV_AI_Y_X (0x3e09) ++#define P_HEVC_RV_AI_Y_X (volatile unsigned int *)((0x3e09 << 2) + 0xff620000) ++#define HEVC_RV_AI_U_X (0x3e0a) ++#define P_HEVC_RV_AI_U_X (volatile unsigned int *)((0x3e0a << 2) + 0xff620000) ++#define HEVC_RV_AI_V_X (0x3e0b) ++#define P_HEVC_RV_AI_V_X (volatile unsigned int *)((0x3e0b << 2) + 0xff620000) ++// bit 15:0 will count up when rv_ai_mb finished when non zero ++// and rv_ai_mb_finished_int will be generate when this is not zero ++#define HEVC_RV_AI_MB_COUNT (0x3e0c) ++#define P_HEVC_RV_AI_MB_COUNT (volatile unsigned int *)((0x3e0c << 2) + 0xff620000) ++// For H264 I in PB picture Use -- dma type : h264_next_intra_dma ++#define HEVC_NEXT_INTRA_DMA_ADDRESS (0x3e0d) ++#define P_HEVC_NEXT_INTRA_DMA_ADDRESS (volatile unsigned int *)((0x3e0d << 2) + 0xff620000) ++// Bit 16 -- dcac_dma_read_cache_disable ++// Bit 15 -- dcac_dma_urgent ++// Bit 14 -- nv21_swap ++// Bit 13 -- nv21_top_dma ++// Bit 12 -- reset_rv_ai_wait_rd_data ++// Bit 11 -- set_rv_ai_wait_rd_data [12:11] = 3 means only dec 1 (For Skipped MB of MBAFF) ++// Bit 10 -- rv_ai_wait_rd_data (Read Only) ++// Bit 9 -- enable_rv_ai_wait_rd_data ++// Bit 8 -- disable_vc1_mv_update ++// Bit 7 -- pred_dc_signed ++// Bit 6 -- inc_vld_ready_count ++// Bit 5 -- dec_vld_ready_count ++// Bit 4 -- disable_ref_bidir_fix ++// Bit 3 -- disable_MV_UL_l1_bot_fix ++// Bit 2 -- disable_mb_aff_fix ++// Bit 1 -- canvas_addr_7 ++// Bit 0 -- constrained_intra_pred_flag for H264 ++#define HEVC_IQIDCT_CONTROL (0x3e0e) ++#define P_HEVC_IQIDCT_CONTROL (volatile unsigned int *)((0x3e0e << 2) + 0xff620000) ++// Bit[31:19] Reserved ++// Bit[18] iq_waiting ++// Bit[17] iq_om_wr_idx ++// Bit[16] iq_om_rd_idx ++// Bit[15] iq_om_busy ++// Bit[14] iq_om_2_busy ++// Bit[13] idx_fifo_0 ++// Bit[12] idx_fifo_1 ++// Bit[11] idx_fifo_2 ++// Bit[10] idx_fifo_3 ++// Bit[9] idx_fifo_4 ++// Bit[8] idx_fifo_5 ++// Bit[7] idx_fifo_6 ++// Bit[6] idx_fifo_7 ++// Bit[5:3] idx_fifo_wp ++// Bit[2:0] idx_fifo_rp ++#define HEVC_IQIDCT_DEBUG_INFO_0 (0x3e0f) ++#define P_HEVC_IQIDCT_DEBUG_INFO_0 (volatile unsigned int *)((0x3e0f << 2) + 0xff620000) ++// For RTL Simulation Only ++#define HEVC_DEBLK_CMD (0x3e10) ++#define P_HEVC_DEBLK_CMD (volatile unsigned int *)((0x3e10 << 2) + 0xff620000) ++// Bit[15+16] ds_mc_valid_2 ++// Bit[14+16] new_idct1_rd_idx_2 ++// Bit[13+16] new_idct1_wr_idx_2 ++// Bit[12+16] idct1_buff0_busy_2 ++// Bit[11+16] idct1_buff1_busy_2 ++// Bit[10+16] new_idct1_busy_2 ++// Bit[9+16] iq_om_8val_2 ++// Bit[8+16] idct1_pipe_busy_2 ++// Bit[7+16] wait_mb_left_finish_hold_2 ++// Bit[6+16] new_idct2_rd_idx_2 ++// Bit[5+16] new_idct2_wr_idx_2 ++// Bit[4+16] idct2_buff0_busy_2 ++// Bit[3+16] idct2_buff1_busy_2 ++// Bit[2+16] idct2_en_2 ++// Bit[1+16] new_idct2_busy_2 ++// Bit[0+16] new_idct1_ready_2 ++// Bit[15] ds_mc_valid_1 ++// Bit[14] new_idct1_rd_idx_1 ++// Bit[13] new_idct1_wr_idx_1 ++// Bit[12] idct1_buff0_busy_1 ++// Bit[11] idct1_buff1_busy_1 ++// Bit[10] new_idct1_busy_1 ++// Bit[9] iq_om_8val_1 ++// Bit[8] idct1_pipe_busy_1 ++// Bit[7] wait_mb_left_finish_hold_1 ++// Bit[6] new_idct2_rd_idx_1 ++// Bit[5] new_idct2_wr_idx_1 ++// Bit[4] idct2_buff0_busy_1 ++// Bit[3] idct2_buff1_busy_1 ++// Bit[2] idct2_en_1 ++// Bit[1] new_idct2_busy_1 ++// Bit[0] new_idct1_ready_1 ++#define HEVC_IQIDCT_DEBUG_IDCT (0x3e11) ++#define P_HEVC_IQIDCT_DEBUG_IDCT (volatile unsigned int *)((0x3e11 << 2) + 0xff620000) ++// bit 31 -- convas_enable ++// bit 30:24 -- convas_x_count ( 8 pixels / 64 bits ) ++// bit 23:16 -- convas_y_count ++// bit 15 -- dcac_dma_busy ++// bit 14 -- dcac_dma_read_cache_active ++// bit 13:8 -- dcac_dma_count ++// bit 7 -- dcac_dma_rw ++// bit 6 -- dcac_skip_read_mode ++// bit 5:0 -- dcac_dma_offset ++#define HEVC_DCAC_DMA_CTRL (0x3e12) ++#define P_HEVC_DCAC_DMA_CTRL (volatile unsigned int *)((0x3e12 << 2) + 0xff620000) ++// when (convas_enable == 0 ) ++// bit 31:0 dcac_dma_addr ++// when (convas_enable == 1 ) ++// bit 31:25 canvas_addr (7 bits) ++// bit 24:12 convas_y_start ( 13 btis ) ++// bit 11:0 convas_x_start ( 12 btis ) ++#define HEVC_DCAC_DMA_ADDRESS (0x3e13) ++#define P_HEVC_DCAC_DMA_ADDRESS (volatile unsigned int *)((0x3e13 << 2) + 0xff620000) ++// bit 7:0 -- dcac_cpu_addr ++#define HEVC_DCAC_CPU_ADDRESS (0x3e14) ++#define P_HEVC_DCAC_CPU_ADDRESS (volatile unsigned int *)((0x3e14 << 2) + 0xff620000) ++// bit 31:0 -- dcac_cpu_data ++#define HEVC_DCAC_CPU_DATA (0x3e15) ++#define P_HEVC_DCAC_CPU_DATA (volatile unsigned int *)((0x3e15 << 2) + 0xff620000) ++// bit 31:19 -- reserved ++// bit 18:16 -- block_num_reg -- Read-Only ++// bit 15:0 -- dcac_mb_count ++#define HEVC_DCAC_MB_COUNT (0x3e16) ++#define P_HEVC_DCAC_MB_COUNT (volatile unsigned int *)((0x3e16 << 2) + 0xff620000) ++// bit 31:18 -- reserved ++// For H264 : ++// bit 17:2 -- h264_quant ++// bit 11:6 -- h264_quant_c ++// bit 5:0 -- h264_quant_c ++// For VC1 : ++// bit 17 -- qindex_GT_8 ++// bit 16 -- HalfQPStep ++// bit 15:12 -- eQuantMode ++// bit 11:6 -- AltPQuant ++// bit 5:0 -- PQuant ++// ++#define HEVC_IQ_QUANT (0x3e17) ++#define P_HEVC_IQ_QUANT (volatile unsigned int *)((0x3e17 << 2) + 0xff620000) ++// bit 31:24 -- bitplane_width ++// bit 23:16 -- bitplane_height ++// bit 15:14 -- bitplane_start_x ++// bit 13:12 -- bitplane_start_y ++// bit 11:4 -- reserved ++// bit 3:1 -- bitplane_type ++// bit 0 -- bitplane_busy ++#define HEVC_VC1_BITPLANE_CTL (0x3e18) ++#define P_HEVC_VC1_BITPLANE_CTL (volatile unsigned int *)((0x3e18 << 2) + 0xff620000) ++// bit 24:16 -- wq_param1 ++// bit 8: 0 -- wq_param0 ++#define HEVC_AVSP_IQ_WQ_PARAM_01 (0x3e19) ++#define P_HEVC_AVSP_IQ_WQ_PARAM_01 (volatile unsigned int *)((0x3e19 << 2) + 0xff620000) ++// bit 24:16 -- wq_param3 ++// bit 8: 0 -- wq_param2 ++#define HEVC_AVSP_IQ_WQ_PARAM_23 (0x3e1a) ++#define P_HEVC_AVSP_IQ_WQ_PARAM_23 (volatile unsigned int *)((0x3e1a << 2) + 0xff620000) ++// bit 24:16 -- wq_param5 ++// bit 8: 0 -- wq_param4 ++#define HEVC_AVSP_IQ_WQ_PARAM_45 (0x3e1b) ++#define P_HEVC_AVSP_IQ_WQ_PARAM_45 (volatile unsigned int *)((0x3e1b << 2) + 0xff620000) ++// bit 31 -- weight_quant_en ++// bit 17:16 -- current_scene_model ++// bit 12: 8 -- chroma_qp_delta_cr ++// bit 4: 0 -- chroma_qp_delta_cb ++#define HEVC_AVSP_IQ_CTL (0x3e1c) ++#define P_HEVC_AVSP_IQ_CTL (volatile unsigned int *)((0x3e1c << 2) + 0xff620000) ++//====================================== ++// VCOP Control Register Bits ++// ++//====================================== ++ //`define IQIDCT_RESET 16'h0001 // Bit 0 ++//====================================== ++// QP Control Register Bits ++// ++//====================================== ++// Duplicate Address: When actually used ++// please move to a different address ++// `define FLD_DCT_TYPE 16'h0100 // Bit 8 0 = Frame DCT; 1 = field DCT ++// ++// Closing file: iqidct_regs.h ++// ++// ++// Reading file: vcpu_regs.h ++// ++//======================================================================== ++// VCPU module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_VDEC_VCPU_CBUS_BASE = 0x03 ++// ----------------------------------------------- ++#define HCODEC_MSP (0x1300) ++#define P_HCODEC_MSP (volatile unsigned int *)((0x1300 << 2) + 0xff620000) ++#define HCODEC_MPSR (0x1301) ++#define P_HCODEC_MPSR (volatile unsigned int *)((0x1301 << 2) + 0xff620000) ++#define HCODEC_MINT_VEC_BASE (0x1302) ++#define P_HCODEC_MINT_VEC_BASE (volatile unsigned int *)((0x1302 << 2) + 0xff620000) ++#define HCODEC_MCPU_INTR_GRP (0x1303) ++#define P_HCODEC_MCPU_INTR_GRP (volatile unsigned int *)((0x1303 << 2) + 0xff620000) ++#define HCODEC_MCPU_INTR_MSK (0x1304) ++#define P_HCODEC_MCPU_INTR_MSK (volatile unsigned int *)((0x1304 << 2) + 0xff620000) ++#define HCODEC_MCPU_INTR_REQ (0x1305) ++#define P_HCODEC_MCPU_INTR_REQ (volatile unsigned int *)((0x1305 << 2) + 0xff620000) ++#define HCODEC_MPC_P (0x1306) ++#define P_HCODEC_MPC_P (volatile unsigned int *)((0x1306 << 2) + 0xff620000) ++#define HCODEC_MPC_D (0x1307) ++#define P_HCODEC_MPC_D (volatile unsigned int *)((0x1307 << 2) + 0xff620000) ++#define HCODEC_MPC_E (0x1308) ++#define P_HCODEC_MPC_E (volatile unsigned int *)((0x1308 << 2) + 0xff620000) ++#define HCODEC_MPC_W (0x1309) ++#define P_HCODEC_MPC_W (volatile unsigned int *)((0x1309 << 2) + 0xff620000) ++#define HCODEC_MINDEX0_REG (0x130a) ++#define P_HCODEC_MINDEX0_REG (volatile unsigned int *)((0x130a << 2) + 0xff620000) ++#define HCODEC_MINDEX1_REG (0x130b) ++#define P_HCODEC_MINDEX1_REG (volatile unsigned int *)((0x130b << 2) + 0xff620000) ++#define HCODEC_MINDEX2_REG (0x130c) ++#define P_HCODEC_MINDEX2_REG (volatile unsigned int *)((0x130c << 2) + 0xff620000) ++#define HCODEC_MINDEX3_REG (0x130d) ++#define P_HCODEC_MINDEX3_REG (volatile unsigned int *)((0x130d << 2) + 0xff620000) ++#define HCODEC_MINDEX4_REG (0x130e) ++#define P_HCODEC_MINDEX4_REG (volatile unsigned int *)((0x130e << 2) + 0xff620000) ++#define HCODEC_MINDEX5_REG (0x130f) ++#define P_HCODEC_MINDEX5_REG (volatile unsigned int *)((0x130f << 2) + 0xff620000) ++#define HCODEC_MINDEX6_REG (0x1310) ++#define P_HCODEC_MINDEX6_REG (volatile unsigned int *)((0x1310 << 2) + 0xff620000) ++#define HCODEC_MINDEX7_REG (0x1311) ++#define P_HCODEC_MINDEX7_REG (volatile unsigned int *)((0x1311 << 2) + 0xff620000) ++#define HCODEC_MMIN_REG (0x1312) ++#define P_HCODEC_MMIN_REG (volatile unsigned int *)((0x1312 << 2) + 0xff620000) ++#define HCODEC_MMAX_REG (0x1313) ++#define P_HCODEC_MMAX_REG (volatile unsigned int *)((0x1313 << 2) + 0xff620000) ++#define HCODEC_MBREAK0_REG (0x1314) ++#define P_HCODEC_MBREAK0_REG (volatile unsigned int *)((0x1314 << 2) + 0xff620000) ++#define HCODEC_MBREAK1_REG (0x1315) ++#define P_HCODEC_MBREAK1_REG (volatile unsigned int *)((0x1315 << 2) + 0xff620000) ++#define HCODEC_MBREAK2_REG (0x1316) ++#define P_HCODEC_MBREAK2_REG (volatile unsigned int *)((0x1316 << 2) + 0xff620000) ++#define HCODEC_MBREAK3_REG (0x1317) ++#define P_HCODEC_MBREAK3_REG (volatile unsigned int *)((0x1317 << 2) + 0xff620000) ++#define HCODEC_MBREAK_TYPE (0x1318) ++#define P_HCODEC_MBREAK_TYPE (volatile unsigned int *)((0x1318 << 2) + 0xff620000) ++#define HCODEC_MBREAK_CTRL (0x1319) ++#define P_HCODEC_MBREAK_CTRL (volatile unsigned int *)((0x1319 << 2) + 0xff620000) ++#define HCODEC_MBREAK_STAUTS (0x131a) ++#define P_HCODEC_MBREAK_STAUTS (volatile unsigned int *)((0x131a << 2) + 0xff620000) ++#define HCODEC_MDB_ADDR_REG (0x131b) ++#define P_HCODEC_MDB_ADDR_REG (volatile unsigned int *)((0x131b << 2) + 0xff620000) ++#define HCODEC_MDB_DATA_REG (0x131c) ++#define P_HCODEC_MDB_DATA_REG (volatile unsigned int *)((0x131c << 2) + 0xff620000) ++#define HCODEC_MDB_CTRL (0x131d) ++#define P_HCODEC_MDB_CTRL (volatile unsigned int *)((0x131d << 2) + 0xff620000) ++#define HCODEC_MSFTINT0 (0x131e) ++#define P_HCODEC_MSFTINT0 (volatile unsigned int *)((0x131e << 2) + 0xff620000) ++#define HCODEC_MSFTINT1 (0x131f) ++#define P_HCODEC_MSFTINT1 (volatile unsigned int *)((0x131f << 2) + 0xff620000) ++#define HCODEC_CSP (0x1320) ++#define P_HCODEC_CSP (volatile unsigned int *)((0x1320 << 2) + 0xff620000) ++#define HCODEC_CPSR (0x1321) ++#define P_HCODEC_CPSR (volatile unsigned int *)((0x1321 << 2) + 0xff620000) ++#define HCODEC_CINT_VEC_BASE (0x1322) ++#define P_HCODEC_CINT_VEC_BASE (volatile unsigned int *)((0x1322 << 2) + 0xff620000) ++#define HCODEC_CCPU_INTR_GRP (0x1323) ++#define P_HCODEC_CCPU_INTR_GRP (volatile unsigned int *)((0x1323 << 2) + 0xff620000) ++#define HCODEC_CCPU_INTR_MSK (0x1324) ++#define P_HCODEC_CCPU_INTR_MSK (volatile unsigned int *)((0x1324 << 2) + 0xff620000) ++#define HCODEC_CCPU_INTR_REQ (0x1325) ++#define P_HCODEC_CCPU_INTR_REQ (volatile unsigned int *)((0x1325 << 2) + 0xff620000) ++#define HCODEC_CPC_P (0x1326) ++#define P_HCODEC_CPC_P (volatile unsigned int *)((0x1326 << 2) + 0xff620000) ++#define HCODEC_CPC_D (0x1327) ++#define P_HCODEC_CPC_D (volatile unsigned int *)((0x1327 << 2) + 0xff620000) ++#define HCODEC_CPC_E (0x1328) ++#define P_HCODEC_CPC_E (volatile unsigned int *)((0x1328 << 2) + 0xff620000) ++#define HCODEC_CPC_W (0x1329) ++#define P_HCODEC_CPC_W (volatile unsigned int *)((0x1329 << 2) + 0xff620000) ++#define HCODEC_CINDEX0_REG (0x132a) ++#define P_HCODEC_CINDEX0_REG (volatile unsigned int *)((0x132a << 2) + 0xff620000) ++#define HCODEC_CINDEX1_REG (0x132b) ++#define P_HCODEC_CINDEX1_REG (volatile unsigned int *)((0x132b << 2) + 0xff620000) ++#define HCODEC_CINDEX2_REG (0x132c) ++#define P_HCODEC_CINDEX2_REG (volatile unsigned int *)((0x132c << 2) + 0xff620000) ++#define HCODEC_CINDEX3_REG (0x132d) ++#define P_HCODEC_CINDEX3_REG (volatile unsigned int *)((0x132d << 2) + 0xff620000) ++#define HCODEC_CINDEX4_REG (0x132e) ++#define P_HCODEC_CINDEX4_REG (volatile unsigned int *)((0x132e << 2) + 0xff620000) ++#define HCODEC_CINDEX5_REG (0x132f) ++#define P_HCODEC_CINDEX5_REG (volatile unsigned int *)((0x132f << 2) + 0xff620000) ++#define HCODEC_CINDEX6_REG (0x1330) ++#define P_HCODEC_CINDEX6_REG (volatile unsigned int *)((0x1330 << 2) + 0xff620000) ++#define HCODEC_CINDEX7_REG (0x1331) ++#define P_HCODEC_CINDEX7_REG (volatile unsigned int *)((0x1331 << 2) + 0xff620000) ++#define HCODEC_CMIN_REG (0x1332) ++#define P_HCODEC_CMIN_REG (volatile unsigned int *)((0x1332 << 2) + 0xff620000) ++#define HCODEC_CMAX_REG (0x1333) ++#define P_HCODEC_CMAX_REG (volatile unsigned int *)((0x1333 << 2) + 0xff620000) ++#define HCODEC_CBREAK0_REG (0x1334) ++#define P_HCODEC_CBREAK0_REG (volatile unsigned int *)((0x1334 << 2) + 0xff620000) ++#define HCODEC_CBREAK1_REG (0x1335) ++#define P_HCODEC_CBREAK1_REG (volatile unsigned int *)((0x1335 << 2) + 0xff620000) ++#define HCODEC_CBREAK2_REG (0x1336) ++#define P_HCODEC_CBREAK2_REG (volatile unsigned int *)((0x1336 << 2) + 0xff620000) ++#define HCODEC_CBREAK3_REG (0x1337) ++#define P_HCODEC_CBREAK3_REG (volatile unsigned int *)((0x1337 << 2) + 0xff620000) ++#define HCODEC_CBREAK_TYPE (0x1338) ++#define P_HCODEC_CBREAK_TYPE (volatile unsigned int *)((0x1338 << 2) + 0xff620000) ++#define HCODEC_CBREAK_CTRL (0x1339) ++#define P_HCODEC_CBREAK_CTRL (volatile unsigned int *)((0x1339 << 2) + 0xff620000) ++#define HCODEC_CBREAK_STAUTS (0x133a) ++#define P_HCODEC_CBREAK_STAUTS (volatile unsigned int *)((0x133a << 2) + 0xff620000) ++#define HCODEC_CDB_ADDR_REG (0x133b) ++#define P_HCODEC_CDB_ADDR_REG (volatile unsigned int *)((0x133b << 2) + 0xff620000) ++#define HCODEC_CDB_DATA_REG (0x133c) ++#define P_HCODEC_CDB_DATA_REG (volatile unsigned int *)((0x133c << 2) + 0xff620000) ++#define HCODEC_CDB_CTRL (0x133d) ++#define P_HCODEC_CDB_CTRL (volatile unsigned int *)((0x133d << 2) + 0xff620000) ++#define HCODEC_CSFTINT0 (0x133e) ++#define P_HCODEC_CSFTINT0 (volatile unsigned int *)((0x133e << 2) + 0xff620000) ++#define HCODEC_CSFTINT1 (0x133f) ++#define P_HCODEC_CSFTINT1 (volatile unsigned int *)((0x133f << 2) + 0xff620000) ++#define HCODEC_IMEM_DMA_CTRL (0x1340) ++#define P_HCODEC_IMEM_DMA_CTRL (volatile unsigned int *)((0x1340 << 2) + 0xff620000) ++#define HCODEC_IMEM_DMA_ADR (0x1341) ++#define P_HCODEC_IMEM_DMA_ADR (volatile unsigned int *)((0x1341 << 2) + 0xff620000) ++#define HCODEC_IMEM_DMA_COUNT (0x1342) ++#define P_HCODEC_IMEM_DMA_COUNT (volatile unsigned int *)((0x1342 << 2) + 0xff620000) ++// bit[29:24] A_brst_num_imem ++// bit[21:16] A_id_imem ++// bit[11:0] wrrsp_count_imem (reserved) ++#define HCODEC_WRRSP_IMEM (0x1343) ++#define P_HCODEC_WRRSP_IMEM (volatile unsigned int *)((0x1343 << 2) + 0xff620000) ++#define HCODEC_LMEM_DMA_CTRL (0x1350) ++#define P_HCODEC_LMEM_DMA_CTRL (volatile unsigned int *)((0x1350 << 2) + 0xff620000) ++#define HCODEC_LMEM_DMA_ADR (0x1351) ++#define P_HCODEC_LMEM_DMA_ADR (volatile unsigned int *)((0x1351 << 2) + 0xff620000) ++#define HCODEC_LMEM_DMA_COUNT (0x1352) ++#define P_HCODEC_LMEM_DMA_COUNT (volatile unsigned int *)((0x1352 << 2) + 0xff620000) ++// bit[29:24] A_brst_num_lmem ++// bit[21:16] A_id_lmem ++// bit[11:0] wrrsp_count_lmem ++#define HCODEC_WRRSP_LMEM (0x1353) ++#define P_HCODEC_WRRSP_LMEM (volatile unsigned int *)((0x1353 << 2) + 0xff620000) ++#define HCODEC_MAC_CTRL1 (0x1360) ++#define P_HCODEC_MAC_CTRL1 (volatile unsigned int *)((0x1360 << 2) + 0xff620000) ++#define HCODEC_ACC0REG1 (0x1361) ++#define P_HCODEC_ACC0REG1 (volatile unsigned int *)((0x1361 << 2) + 0xff620000) ++#define HCODEC_ACC1REG1 (0x1362) ++#define P_HCODEC_ACC1REG1 (volatile unsigned int *)((0x1362 << 2) + 0xff620000) ++#define HCODEC_MAC_CTRL2 (0x1370) ++#define P_HCODEC_MAC_CTRL2 (volatile unsigned int *)((0x1370 << 2) + 0xff620000) ++#define HCODEC_ACC0REG2 (0x1371) ++#define P_HCODEC_ACC0REG2 (volatile unsigned int *)((0x1371 << 2) + 0xff620000) ++#define HCODEC_ACC1REG2 (0x1372) ++#define P_HCODEC_ACC1REG2 (volatile unsigned int *)((0x1372 << 2) + 0xff620000) ++#define HCODEC_CPU_TRACE (0x1380) ++#define P_HCODEC_CPU_TRACE (volatile unsigned int *)((0x1380 << 2) + 0xff620000) ++// ++// Closing file: vcpu_regs.h ++// ++// ++// Reading file: vcpu_regs.h ++// ++//======================================================================== ++// VCPU module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_VDEC_VCPU_CBUS_BASE = 0x03 ++// ----------------------------------------------- ++#define VDEC2_MSP (0x2300) ++#define P_VDEC2_MSP (volatile unsigned int *)((0x2300 << 2) + 0xff620000) ++#define VDEC2_MPSR (0x2301) ++#define P_VDEC2_MPSR (volatile unsigned int *)((0x2301 << 2) + 0xff620000) ++#define VDEC2_MINT_VEC_BASE (0x2302) ++#define P_VDEC2_MINT_VEC_BASE (volatile unsigned int *)((0x2302 << 2) + 0xff620000) ++#define VDEC2_MCPU_INTR_GRP (0x2303) ++#define P_VDEC2_MCPU_INTR_GRP (volatile unsigned int *)((0x2303 << 2) + 0xff620000) ++#define VDEC2_MCPU_INTR_MSK (0x2304) ++#define P_VDEC2_MCPU_INTR_MSK (volatile unsigned int *)((0x2304 << 2) + 0xff620000) ++#define VDEC2_MCPU_INTR_REQ (0x2305) ++#define P_VDEC2_MCPU_INTR_REQ (volatile unsigned int *)((0x2305 << 2) + 0xff620000) ++#define VDEC2_MPC_P (0x2306) ++#define P_VDEC2_MPC_P (volatile unsigned int *)((0x2306 << 2) + 0xff620000) ++#define VDEC2_MPC_D (0x2307) ++#define P_VDEC2_MPC_D (volatile unsigned int *)((0x2307 << 2) + 0xff620000) ++#define VDEC2_MPC_E (0x2308) ++#define P_VDEC2_MPC_E (volatile unsigned int *)((0x2308 << 2) + 0xff620000) ++#define VDEC2_MPC_W (0x2309) ++#define P_VDEC2_MPC_W (volatile unsigned int *)((0x2309 << 2) + 0xff620000) ++#define VDEC2_MINDEX0_REG (0x230a) ++#define P_VDEC2_MINDEX0_REG (volatile unsigned int *)((0x230a << 2) + 0xff620000) ++#define VDEC2_MINDEX1_REG (0x230b) ++#define P_VDEC2_MINDEX1_REG (volatile unsigned int *)((0x230b << 2) + 0xff620000) ++#define VDEC2_MINDEX2_REG (0x230c) ++#define P_VDEC2_MINDEX2_REG (volatile unsigned int *)((0x230c << 2) + 0xff620000) ++#define VDEC2_MINDEX3_REG (0x230d) ++#define P_VDEC2_MINDEX3_REG (volatile unsigned int *)((0x230d << 2) + 0xff620000) ++#define VDEC2_MINDEX4_REG (0x230e) ++#define P_VDEC2_MINDEX4_REG (volatile unsigned int *)((0x230e << 2) + 0xff620000) ++#define VDEC2_MINDEX5_REG (0x230f) ++#define P_VDEC2_MINDEX5_REG (volatile unsigned int *)((0x230f << 2) + 0xff620000) ++#define VDEC2_MINDEX6_REG (0x2310) ++#define P_VDEC2_MINDEX6_REG (volatile unsigned int *)((0x2310 << 2) + 0xff620000) ++#define VDEC2_MINDEX7_REG (0x2311) ++#define P_VDEC2_MINDEX7_REG (volatile unsigned int *)((0x2311 << 2) + 0xff620000) ++#define VDEC2_MMIN_REG (0x2312) ++#define P_VDEC2_MMIN_REG (volatile unsigned int *)((0x2312 << 2) + 0xff620000) ++#define VDEC2_MMAX_REG (0x2313) ++#define P_VDEC2_MMAX_REG (volatile unsigned int *)((0x2313 << 2) + 0xff620000) ++#define VDEC2_MBREAK0_REG (0x2314) ++#define P_VDEC2_MBREAK0_REG (volatile unsigned int *)((0x2314 << 2) + 0xff620000) ++#define VDEC2_MBREAK1_REG (0x2315) ++#define P_VDEC2_MBREAK1_REG (volatile unsigned int *)((0x2315 << 2) + 0xff620000) ++#define VDEC2_MBREAK2_REG (0x2316) ++#define P_VDEC2_MBREAK2_REG (volatile unsigned int *)((0x2316 << 2) + 0xff620000) ++#define VDEC2_MBREAK3_REG (0x2317) ++#define P_VDEC2_MBREAK3_REG (volatile unsigned int *)((0x2317 << 2) + 0xff620000) ++#define VDEC2_MBREAK_TYPE (0x2318) ++#define P_VDEC2_MBREAK_TYPE (volatile unsigned int *)((0x2318 << 2) + 0xff620000) ++#define VDEC2_MBREAK_CTRL (0x2319) ++#define P_VDEC2_MBREAK_CTRL (volatile unsigned int *)((0x2319 << 2) + 0xff620000) ++#define VDEC2_MBREAK_STAUTS (0x231a) ++#define P_VDEC2_MBREAK_STAUTS (volatile unsigned int *)((0x231a << 2) + 0xff620000) ++#define VDEC2_MDB_ADDR_REG (0x231b) ++#define P_VDEC2_MDB_ADDR_REG (volatile unsigned int *)((0x231b << 2) + 0xff620000) ++#define VDEC2_MDB_DATA_REG (0x231c) ++#define P_VDEC2_MDB_DATA_REG (volatile unsigned int *)((0x231c << 2) + 0xff620000) ++#define VDEC2_MDB_CTRL (0x231d) ++#define P_VDEC2_MDB_CTRL (volatile unsigned int *)((0x231d << 2) + 0xff620000) ++#define VDEC2_MSFTINT0 (0x231e) ++#define P_VDEC2_MSFTINT0 (volatile unsigned int *)((0x231e << 2) + 0xff620000) ++#define VDEC2_MSFTINT1 (0x231f) ++#define P_VDEC2_MSFTINT1 (volatile unsigned int *)((0x231f << 2) + 0xff620000) ++#define VDEC2_CSP (0x2320) ++#define P_VDEC2_CSP (volatile unsigned int *)((0x2320 << 2) + 0xff620000) ++#define VDEC2_CPSR (0x2321) ++#define P_VDEC2_CPSR (volatile unsigned int *)((0x2321 << 2) + 0xff620000) ++#define VDEC2_CINT_VEC_BASE (0x2322) ++#define P_VDEC2_CINT_VEC_BASE (volatile unsigned int *)((0x2322 << 2) + 0xff620000) ++#define VDEC2_CCPU_INTR_GRP (0x2323) ++#define P_VDEC2_CCPU_INTR_GRP (volatile unsigned int *)((0x2323 << 2) + 0xff620000) ++#define VDEC2_CCPU_INTR_MSK (0x2324) ++#define P_VDEC2_CCPU_INTR_MSK (volatile unsigned int *)((0x2324 << 2) + 0xff620000) ++#define VDEC2_CCPU_INTR_REQ (0x2325) ++#define P_VDEC2_CCPU_INTR_REQ (volatile unsigned int *)((0x2325 << 2) + 0xff620000) ++#define VDEC2_CPC_P (0x2326) ++#define P_VDEC2_CPC_P (volatile unsigned int *)((0x2326 << 2) + 0xff620000) ++#define VDEC2_CPC_D (0x2327) ++#define P_VDEC2_CPC_D (volatile unsigned int *)((0x2327 << 2) + 0xff620000) ++#define VDEC2_CPC_E (0x2328) ++#define P_VDEC2_CPC_E (volatile unsigned int *)((0x2328 << 2) + 0xff620000) ++#define VDEC2_CPC_W (0x2329) ++#define P_VDEC2_CPC_W (volatile unsigned int *)((0x2329 << 2) + 0xff620000) ++#define VDEC2_CINDEX0_REG (0x232a) ++#define P_VDEC2_CINDEX0_REG (volatile unsigned int *)((0x232a << 2) + 0xff620000) ++#define VDEC2_CINDEX1_REG (0x232b) ++#define P_VDEC2_CINDEX1_REG (volatile unsigned int *)((0x232b << 2) + 0xff620000) ++#define VDEC2_CINDEX2_REG (0x232c) ++#define P_VDEC2_CINDEX2_REG (volatile unsigned int *)((0x232c << 2) + 0xff620000) ++#define VDEC2_CINDEX3_REG (0x232d) ++#define P_VDEC2_CINDEX3_REG (volatile unsigned int *)((0x232d << 2) + 0xff620000) ++#define VDEC2_CINDEX4_REG (0x232e) ++#define P_VDEC2_CINDEX4_REG (volatile unsigned int *)((0x232e << 2) + 0xff620000) ++#define VDEC2_CINDEX5_REG (0x232f) ++#define P_VDEC2_CINDEX5_REG (volatile unsigned int *)((0x232f << 2) + 0xff620000) ++#define VDEC2_CINDEX6_REG (0x2330) ++#define P_VDEC2_CINDEX6_REG (volatile unsigned int *)((0x2330 << 2) + 0xff620000) ++#define VDEC2_CINDEX7_REG (0x2331) ++#define P_VDEC2_CINDEX7_REG (volatile unsigned int *)((0x2331 << 2) + 0xff620000) ++#define VDEC2_CMIN_REG (0x2332) ++#define P_VDEC2_CMIN_REG (volatile unsigned int *)((0x2332 << 2) + 0xff620000) ++#define VDEC2_CMAX_REG (0x2333) ++#define P_VDEC2_CMAX_REG (volatile unsigned int *)((0x2333 << 2) + 0xff620000) ++#define VDEC2_CBREAK0_REG (0x2334) ++#define P_VDEC2_CBREAK0_REG (volatile unsigned int *)((0x2334 << 2) + 0xff620000) ++#define VDEC2_CBREAK1_REG (0x2335) ++#define P_VDEC2_CBREAK1_REG (volatile unsigned int *)((0x2335 << 2) + 0xff620000) ++#define VDEC2_CBREAK2_REG (0x2336) ++#define P_VDEC2_CBREAK2_REG (volatile unsigned int *)((0x2336 << 2) + 0xff620000) ++#define VDEC2_CBREAK3_REG (0x2337) ++#define P_VDEC2_CBREAK3_REG (volatile unsigned int *)((0x2337 << 2) + 0xff620000) ++#define VDEC2_CBREAK_TYPE (0x2338) ++#define P_VDEC2_CBREAK_TYPE (volatile unsigned int *)((0x2338 << 2) + 0xff620000) ++#define VDEC2_CBREAK_CTRL (0x2339) ++#define P_VDEC2_CBREAK_CTRL (volatile unsigned int *)((0x2339 << 2) + 0xff620000) ++#define VDEC2_CBREAK_STAUTS (0x233a) ++#define P_VDEC2_CBREAK_STAUTS (volatile unsigned int *)((0x233a << 2) + 0xff620000) ++#define VDEC2_CDB_ADDR_REG (0x233b) ++#define P_VDEC2_CDB_ADDR_REG (volatile unsigned int *)((0x233b << 2) + 0xff620000) ++#define VDEC2_CDB_DATA_REG (0x233c) ++#define P_VDEC2_CDB_DATA_REG (volatile unsigned int *)((0x233c << 2) + 0xff620000) ++#define VDEC2_CDB_CTRL (0x233d) ++#define P_VDEC2_CDB_CTRL (volatile unsigned int *)((0x233d << 2) + 0xff620000) ++#define VDEC2_CSFTINT0 (0x233e) ++#define P_VDEC2_CSFTINT0 (volatile unsigned int *)((0x233e << 2) + 0xff620000) ++#define VDEC2_CSFTINT1 (0x233f) ++#define P_VDEC2_CSFTINT1 (volatile unsigned int *)((0x233f << 2) + 0xff620000) ++#define VDEC2_IMEM_DMA_CTRL (0x2340) ++#define P_VDEC2_IMEM_DMA_CTRL (volatile unsigned int *)((0x2340 << 2) + 0xff620000) ++#define VDEC2_IMEM_DMA_ADR (0x2341) ++#define P_VDEC2_IMEM_DMA_ADR (volatile unsigned int *)((0x2341 << 2) + 0xff620000) ++#define VDEC2_IMEM_DMA_COUNT (0x2342) ++#define P_VDEC2_IMEM_DMA_COUNT (volatile unsigned int *)((0x2342 << 2) + 0xff620000) ++// bit[29:24] A_brst_num_imem ++// bit[21:16] A_id_imem ++// bit[11:0] wrrsp_count_imem (reserved) ++#define VDEC2_WRRSP_IMEM (0x2343) ++#define P_VDEC2_WRRSP_IMEM (volatile unsigned int *)((0x2343 << 2) + 0xff620000) ++#define VDEC2_LMEM_DMA_CTRL (0x2350) ++#define P_VDEC2_LMEM_DMA_CTRL (volatile unsigned int *)((0x2350 << 2) + 0xff620000) ++#define VDEC2_LMEM_DMA_ADR (0x2351) ++#define P_VDEC2_LMEM_DMA_ADR (volatile unsigned int *)((0x2351 << 2) + 0xff620000) ++#define VDEC2_LMEM_DMA_COUNT (0x2352) ++#define P_VDEC2_LMEM_DMA_COUNT (volatile unsigned int *)((0x2352 << 2) + 0xff620000) ++// bit[29:24] A_brst_num_lmem ++// bit[21:16] A_id_lmem ++// bit[11:0] wrrsp_count_lmem ++#define VDEC2_WRRSP_LMEM (0x2353) ++#define P_VDEC2_WRRSP_LMEM (volatile unsigned int *)((0x2353 << 2) + 0xff620000) ++#define VDEC2_MAC_CTRL1 (0x2360) ++#define P_VDEC2_MAC_CTRL1 (volatile unsigned int *)((0x2360 << 2) + 0xff620000) ++#define VDEC2_ACC0REG1 (0x2361) ++#define P_VDEC2_ACC0REG1 (volatile unsigned int *)((0x2361 << 2) + 0xff620000) ++#define VDEC2_ACC1REG1 (0x2362) ++#define P_VDEC2_ACC1REG1 (volatile unsigned int *)((0x2362 << 2) + 0xff620000) ++#define VDEC2_MAC_CTRL2 (0x2370) ++#define P_VDEC2_MAC_CTRL2 (volatile unsigned int *)((0x2370 << 2) + 0xff620000) ++#define VDEC2_ACC0REG2 (0x2371) ++#define P_VDEC2_ACC0REG2 (volatile unsigned int *)((0x2371 << 2) + 0xff620000) ++#define VDEC2_ACC1REG2 (0x2372) ++#define P_VDEC2_ACC1REG2 (volatile unsigned int *)((0x2372 << 2) + 0xff620000) ++#define VDEC2_CPU_TRACE (0x2380) ++#define P_VDEC2_CPU_TRACE (volatile unsigned int *)((0x2380 << 2) + 0xff620000) ++// ++// Closing file: vcpu_regs.h ++// ++// ++// Reading file: vcpu_regs.h ++// ++//======================================================================== ++// VCPU module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_VDEC_VCPU_CBUS_BASE = 0x03 ++// ----------------------------------------------- ++#define HEVC_MSP (0x3300) ++#define P_HEVC_MSP (volatile unsigned int *)((0x3300 << 2) + 0xff620000) ++#define HEVC_MPSR (0x3301) ++#define P_HEVC_MPSR (volatile unsigned int *)((0x3301 << 2) + 0xff620000) ++#define HEVC_MINT_VEC_BASE (0x3302) ++#define P_HEVC_MINT_VEC_BASE (volatile unsigned int *)((0x3302 << 2) + 0xff620000) ++#define HEVC_MCPU_INTR_GRP (0x3303) ++#define P_HEVC_MCPU_INTR_GRP (volatile unsigned int *)((0x3303 << 2) + 0xff620000) ++#define HEVC_MCPU_INTR_MSK (0x3304) ++#define P_HEVC_MCPU_INTR_MSK (volatile unsigned int *)((0x3304 << 2) + 0xff620000) ++#define HEVC_MCPU_INTR_REQ (0x3305) ++#define P_HEVC_MCPU_INTR_REQ (volatile unsigned int *)((0x3305 << 2) + 0xff620000) ++#define HEVC_MPC_P (0x3306) ++#define P_HEVC_MPC_P (volatile unsigned int *)((0x3306 << 2) + 0xff620000) ++#define HEVC_MPC_D (0x3307) ++#define P_HEVC_MPC_D (volatile unsigned int *)((0x3307 << 2) + 0xff620000) ++#define HEVC_MPC_E (0x3308) ++#define P_HEVC_MPC_E (volatile unsigned int *)((0x3308 << 2) + 0xff620000) ++#define HEVC_MPC_W (0x3309) ++#define P_HEVC_MPC_W (volatile unsigned int *)((0x3309 << 2) + 0xff620000) ++#define HEVC_MINDEX0_REG (0x330a) ++#define P_HEVC_MINDEX0_REG (volatile unsigned int *)((0x330a << 2) + 0xff620000) ++#define HEVC_MINDEX1_REG (0x330b) ++#define P_HEVC_MINDEX1_REG (volatile unsigned int *)((0x330b << 2) + 0xff620000) ++#define HEVC_MINDEX2_REG (0x330c) ++#define P_HEVC_MINDEX2_REG (volatile unsigned int *)((0x330c << 2) + 0xff620000) ++#define HEVC_MINDEX3_REG (0x330d) ++#define P_HEVC_MINDEX3_REG (volatile unsigned int *)((0x330d << 2) + 0xff620000) ++#define HEVC_MINDEX4_REG (0x330e) ++#define P_HEVC_MINDEX4_REG (volatile unsigned int *)((0x330e << 2) + 0xff620000) ++#define HEVC_MINDEX5_REG (0x330f) ++#define P_HEVC_MINDEX5_REG (volatile unsigned int *)((0x330f << 2) + 0xff620000) ++#define HEVC_MINDEX6_REG (0x3310) ++#define P_HEVC_MINDEX6_REG (volatile unsigned int *)((0x3310 << 2) + 0xff620000) ++#define HEVC_MINDEX7_REG (0x3311) ++#define P_HEVC_MINDEX7_REG (volatile unsigned int *)((0x3311 << 2) + 0xff620000) ++#define HEVC_MMIN_REG (0x3312) ++#define P_HEVC_MMIN_REG (volatile unsigned int *)((0x3312 << 2) + 0xff620000) ++#define HEVC_MMAX_REG (0x3313) ++#define P_HEVC_MMAX_REG (volatile unsigned int *)((0x3313 << 2) + 0xff620000) ++#define HEVC_MBREAK0_REG (0x3314) ++#define P_HEVC_MBREAK0_REG (volatile unsigned int *)((0x3314 << 2) + 0xff620000) ++#define HEVC_MBREAK1_REG (0x3315) ++#define P_HEVC_MBREAK1_REG (volatile unsigned int *)((0x3315 << 2) + 0xff620000) ++#define HEVC_MBREAK2_REG (0x3316) ++#define P_HEVC_MBREAK2_REG (volatile unsigned int *)((0x3316 << 2) + 0xff620000) ++#define HEVC_MBREAK3_REG (0x3317) ++#define P_HEVC_MBREAK3_REG (volatile unsigned int *)((0x3317 << 2) + 0xff620000) ++#define HEVC_MBREAK_TYPE (0x3318) ++#define P_HEVC_MBREAK_TYPE (volatile unsigned int *)((0x3318 << 2) + 0xff620000) ++#define HEVC_MBREAK_CTRL (0x3319) ++#define P_HEVC_MBREAK_CTRL (volatile unsigned int *)((0x3319 << 2) + 0xff620000) ++#define HEVC_MBREAK_STAUTS (0x331a) ++#define P_HEVC_MBREAK_STAUTS (volatile unsigned int *)((0x331a << 2) + 0xff620000) ++#define HEVC_MDB_ADDR_REG (0x331b) ++#define P_HEVC_MDB_ADDR_REG (volatile unsigned int *)((0x331b << 2) + 0xff620000) ++#define HEVC_MDB_DATA_REG (0x331c) ++#define P_HEVC_MDB_DATA_REG (volatile unsigned int *)((0x331c << 2) + 0xff620000) ++#define HEVC_MDB_CTRL (0x331d) ++#define P_HEVC_MDB_CTRL (volatile unsigned int *)((0x331d << 2) + 0xff620000) ++#define HEVC_MSFTINT0 (0x331e) ++#define P_HEVC_MSFTINT0 (volatile unsigned int *)((0x331e << 2) + 0xff620000) ++#define HEVC_MSFTINT1 (0x331f) ++#define P_HEVC_MSFTINT1 (volatile unsigned int *)((0x331f << 2) + 0xff620000) ++#define HEVC_CSP (0x3320) ++#define P_HEVC_CSP (volatile unsigned int *)((0x3320 << 2) + 0xff620000) ++#define HEVC_CPSR (0x3321) ++#define P_HEVC_CPSR (volatile unsigned int *)((0x3321 << 2) + 0xff620000) ++#define HEVC_CINT_VEC_BASE (0x3322) ++#define P_HEVC_CINT_VEC_BASE (volatile unsigned int *)((0x3322 << 2) + 0xff620000) ++#define HEVC_CCPU_INTR_GRP (0x3323) ++#define P_HEVC_CCPU_INTR_GRP (volatile unsigned int *)((0x3323 << 2) + 0xff620000) ++#define HEVC_CCPU_INTR_MSK (0x3324) ++#define P_HEVC_CCPU_INTR_MSK (volatile unsigned int *)((0x3324 << 2) + 0xff620000) ++#define HEVC_CCPU_INTR_REQ (0x3325) ++#define P_HEVC_CCPU_INTR_REQ (volatile unsigned int *)((0x3325 << 2) + 0xff620000) ++#define HEVC_CPC_P (0x3326) ++#define P_HEVC_CPC_P (volatile unsigned int *)((0x3326 << 2) + 0xff620000) ++#define HEVC_CPC_D (0x3327) ++#define P_HEVC_CPC_D (volatile unsigned int *)((0x3327 << 2) + 0xff620000) ++#define HEVC_CPC_E (0x3328) ++#define P_HEVC_CPC_E (volatile unsigned int *)((0x3328 << 2) + 0xff620000) ++#define HEVC_CPC_W (0x3329) ++#define P_HEVC_CPC_W (volatile unsigned int *)((0x3329 << 2) + 0xff620000) ++#define HEVC_CINDEX0_REG (0x332a) ++#define P_HEVC_CINDEX0_REG (volatile unsigned int *)((0x332a << 2) + 0xff620000) ++#define HEVC_CINDEX1_REG (0x332b) ++#define P_HEVC_CINDEX1_REG (volatile unsigned int *)((0x332b << 2) + 0xff620000) ++#define HEVC_CINDEX2_REG (0x332c) ++#define P_HEVC_CINDEX2_REG (volatile unsigned int *)((0x332c << 2) + 0xff620000) ++#define HEVC_CINDEX3_REG (0x332d) ++#define P_HEVC_CINDEX3_REG (volatile unsigned int *)((0x332d << 2) + 0xff620000) ++#define HEVC_CINDEX4_REG (0x332e) ++#define P_HEVC_CINDEX4_REG (volatile unsigned int *)((0x332e << 2) + 0xff620000) ++#define HEVC_CINDEX5_REG (0x332f) ++#define P_HEVC_CINDEX5_REG (volatile unsigned int *)((0x332f << 2) + 0xff620000) ++#define HEVC_CINDEX6_REG (0x3330) ++#define P_HEVC_CINDEX6_REG (volatile unsigned int *)((0x3330 << 2) + 0xff620000) ++#define HEVC_CINDEX7_REG (0x3331) ++#define P_HEVC_CINDEX7_REG (volatile unsigned int *)((0x3331 << 2) + 0xff620000) ++#define HEVC_CMIN_REG (0x3332) ++#define P_HEVC_CMIN_REG (volatile unsigned int *)((0x3332 << 2) + 0xff620000) ++#define HEVC_CMAX_REG (0x3333) ++#define P_HEVC_CMAX_REG (volatile unsigned int *)((0x3333 << 2) + 0xff620000) ++#define HEVC_CBREAK0_REG (0x3334) ++#define P_HEVC_CBREAK0_REG (volatile unsigned int *)((0x3334 << 2) + 0xff620000) ++#define HEVC_CBREAK1_REG (0x3335) ++#define P_HEVC_CBREAK1_REG (volatile unsigned int *)((0x3335 << 2) + 0xff620000) ++#define HEVC_CBREAK2_REG (0x3336) ++#define P_HEVC_CBREAK2_REG (volatile unsigned int *)((0x3336 << 2) + 0xff620000) ++#define HEVC_CBREAK3_REG (0x3337) ++#define P_HEVC_CBREAK3_REG (volatile unsigned int *)((0x3337 << 2) + 0xff620000) ++#define HEVC_CBREAK_TYPE (0x3338) ++#define P_HEVC_CBREAK_TYPE (volatile unsigned int *)((0x3338 << 2) + 0xff620000) ++#define HEVC_CBREAK_CTRL (0x3339) ++#define P_HEVC_CBREAK_CTRL (volatile unsigned int *)((0x3339 << 2) + 0xff620000) ++#define HEVC_CBREAK_STAUTS (0x333a) ++#define P_HEVC_CBREAK_STAUTS (volatile unsigned int *)((0x333a << 2) + 0xff620000) ++#define HEVC_CDB_ADDR_REG (0x333b) ++#define P_HEVC_CDB_ADDR_REG (volatile unsigned int *)((0x333b << 2) + 0xff620000) ++#define HEVC_CDB_DATA_REG (0x333c) ++#define P_HEVC_CDB_DATA_REG (volatile unsigned int *)((0x333c << 2) + 0xff620000) ++#define HEVC_CDB_CTRL (0x333d) ++#define P_HEVC_CDB_CTRL (volatile unsigned int *)((0x333d << 2) + 0xff620000) ++#define HEVC_CSFTINT0 (0x333e) ++#define P_HEVC_CSFTINT0 (volatile unsigned int *)((0x333e << 2) + 0xff620000) ++#define HEVC_CSFTINT1 (0x333f) ++#define P_HEVC_CSFTINT1 (volatile unsigned int *)((0x333f << 2) + 0xff620000) ++#define HEVC_IMEM_DMA_CTRL (0x3340) ++#define P_HEVC_IMEM_DMA_CTRL (volatile unsigned int *)((0x3340 << 2) + 0xff620000) ++#define HEVC_IMEM_DMA_ADR (0x3341) ++#define P_HEVC_IMEM_DMA_ADR (volatile unsigned int *)((0x3341 << 2) + 0xff620000) ++#define HEVC_IMEM_DMA_COUNT (0x3342) ++#define P_HEVC_IMEM_DMA_COUNT (volatile unsigned int *)((0x3342 << 2) + 0xff620000) ++// bit[29:24] A_brst_num_imem ++// bit[21:16] A_id_imem ++// bit[11:0] wrrsp_count_imem (reserved) ++#define HEVC_WRRSP_IMEM (0x3343) ++#define P_HEVC_WRRSP_IMEM (volatile unsigned int *)((0x3343 << 2) + 0xff620000) ++#define HEVC_LMEM_DMA_CTRL (0x3350) ++#define P_HEVC_LMEM_DMA_CTRL (volatile unsigned int *)((0x3350 << 2) + 0xff620000) ++#define HEVC_LMEM_DMA_ADR (0x3351) ++#define P_HEVC_LMEM_DMA_ADR (volatile unsigned int *)((0x3351 << 2) + 0xff620000) ++#define HEVC_LMEM_DMA_COUNT (0x3352) ++#define P_HEVC_LMEM_DMA_COUNT (volatile unsigned int *)((0x3352 << 2) + 0xff620000) ++// bit[29:24] A_brst_num_lmem ++// bit[21:16] A_id_lmem ++// bit[11:0] wrrsp_count_lmem ++#define HEVC_WRRSP_LMEM (0x3353) ++#define P_HEVC_WRRSP_LMEM (volatile unsigned int *)((0x3353 << 2) + 0xff620000) ++#define HEVC_MAC_CTRL1 (0x3360) ++#define P_HEVC_MAC_CTRL1 (volatile unsigned int *)((0x3360 << 2) + 0xff620000) ++#define HEVC_ACC0REG1 (0x3361) ++#define P_HEVC_ACC0REG1 (volatile unsigned int *)((0x3361 << 2) + 0xff620000) ++#define HEVC_ACC1REG1 (0x3362) ++#define P_HEVC_ACC1REG1 (volatile unsigned int *)((0x3362 << 2) + 0xff620000) ++#define HEVC_MAC_CTRL2 (0x3370) ++#define P_HEVC_MAC_CTRL2 (volatile unsigned int *)((0x3370 << 2) + 0xff620000) ++#define HEVC_ACC0REG2 (0x3371) ++#define P_HEVC_ACC0REG2 (volatile unsigned int *)((0x3371 << 2) + 0xff620000) ++#define HEVC_ACC1REG2 (0x3372) ++#define P_HEVC_ACC1REG2 (volatile unsigned int *)((0x3372 << 2) + 0xff620000) ++#define HEVC_CPU_TRACE (0x3380) ++#define P_HEVC_CPU_TRACE (volatile unsigned int *)((0x3380 << 2) + 0xff620000) ++// ++// Closing file: vcpu_regs.h ++// ++// ++// Reading file: henc_regs.h ++// ++//======================================================================== ++// MDEC module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HCODEC_HENC_CBUS_BASE = 0x0a ++// ----------------------------------------------- ++#define HCODEC_HENC_SCRATCH_0 (0x1ac0) ++#define P_HCODEC_HENC_SCRATCH_0 (volatile unsigned int *)((0x1ac0 << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_1 (0x1ac1) ++#define P_HCODEC_HENC_SCRATCH_1 (volatile unsigned int *)((0x1ac1 << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_2 (0x1ac2) ++#define P_HCODEC_HENC_SCRATCH_2 (volatile unsigned int *)((0x1ac2 << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_3 (0x1ac3) ++#define P_HCODEC_HENC_SCRATCH_3 (volatile unsigned int *)((0x1ac3 << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_4 (0x1ac4) ++#define P_HCODEC_HENC_SCRATCH_4 (volatile unsigned int *)((0x1ac4 << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_5 (0x1ac5) ++#define P_HCODEC_HENC_SCRATCH_5 (volatile unsigned int *)((0x1ac5 << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_6 (0x1ac6) ++#define P_HCODEC_HENC_SCRATCH_6 (volatile unsigned int *)((0x1ac6 << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_7 (0x1ac7) ++#define P_HCODEC_HENC_SCRATCH_7 (volatile unsigned int *)((0x1ac7 << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_8 (0x1ac8) ++#define P_HCODEC_HENC_SCRATCH_8 (volatile unsigned int *)((0x1ac8 << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_9 (0x1ac9) ++#define P_HCODEC_HENC_SCRATCH_9 (volatile unsigned int *)((0x1ac9 << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_A (0x1aca) ++#define P_HCODEC_HENC_SCRATCH_A (volatile unsigned int *)((0x1aca << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_B (0x1acb) ++#define P_HCODEC_HENC_SCRATCH_B (volatile unsigned int *)((0x1acb << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_C (0x1acc) ++#define P_HCODEC_HENC_SCRATCH_C (volatile unsigned int *)((0x1acc << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_D (0x1acd) ++#define P_HCODEC_HENC_SCRATCH_D (volatile unsigned int *)((0x1acd << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_E (0x1ace) ++#define P_HCODEC_HENC_SCRATCH_E (volatile unsigned int *)((0x1ace << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_F (0x1acf) ++#define P_HCODEC_HENC_SCRATCH_F (volatile unsigned int *)((0x1acf << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_G (0x1ad0) ++#define P_HCODEC_HENC_SCRATCH_G (volatile unsigned int *)((0x1ad0 << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_H (0x1ad1) ++#define P_HCODEC_HENC_SCRATCH_H (volatile unsigned int *)((0x1ad1 << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_I (0x1ad2) ++#define P_HCODEC_HENC_SCRATCH_I (volatile unsigned int *)((0x1ad2 << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_J (0x1ad3) ++#define P_HCODEC_HENC_SCRATCH_J (volatile unsigned int *)((0x1ad3 << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_K (0x1ad4) ++#define P_HCODEC_HENC_SCRATCH_K (volatile unsigned int *)((0x1ad4 << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_L (0x1ad5) ++#define P_HCODEC_HENC_SCRATCH_L (volatile unsigned int *)((0x1ad5 << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_M (0x1ad6) ++#define P_HCODEC_HENC_SCRATCH_M (volatile unsigned int *)((0x1ad6 << 2) + 0xff620000) ++#define HCODEC_HENC_SCRATCH_N (0x1ad7) ++#define P_HCODEC_HENC_SCRATCH_N (volatile unsigned int *)((0x1ad7 << 2) + 0xff620000) ++// bit [7:0] data_feed_buff_id ++#define HCODEC_IE_DATA_FEED_BUFF_INFO (0x1ad8) ++#define P_HCODEC_IE_DATA_FEED_BUFF_INFO (volatile unsigned int *)((0x1ad8 << 2) + 0xff620000) ++// ++// Closing file: henc_regs.h ++// ++// ++// Reading file: vlc_regs.h ++// ++//======================================================================== ++// VLC module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HCODEC_VLC_CBUS_BASE = 0x0d ++// ----------------------------------------------- ++// Bit[31:28] - henc_status ++// Bit[27:8] - reserved ++// Bit[7] mc_hcmd_buff_enable ++// Bit[6] mc_hcmd_use_mc_hcmd_buff ++// Bit[5] mc_hcmd_use_mc_hcmd_hw_start ++// Bit[4] no_mc_out_null_non_skipped_mb ++// Bit[3] mc_out_even_skipped_mb ++// Bit[2] - hcmd_enable ++// Bit[1] - vlc_control_enable (0 will treat as soft_reset) ++// Bit[0] - vlc_input_enable (enable input interface) ++#define HCODEC_VLC_STATUS_CTRL (0x1d00) ++#define P_HCODEC_VLC_STATUS_CTRL (volatile unsigned int *)((0x1d00 << 2) + 0xff620000) ++// Bit [31] - small_luma_ignore_chroma ++// Bit[30:16] - Reserved ++// Bit [15] - enable_free_clk_mc_hcmd_buff ++// Bit [14] - enable_free_clk_reg ++// Bit [13] - enable_free_clk_stream ++// Bit [12] - enable_free_clk_pre_buff ++// Bit [11] - enable_free_clk_vb_buff ++// Bit [10] - enable_free_clk_dc_input ++// Bit [9] - enable_free_clk_input ++// Bit [8] - enable_free_clk_mv_cal ++// Bit [7] - enable_free_clk_status ++// Bit [6] - enable_free_clk_mc_dblk_cmd_if ++// Bit [5] - disable_mvd_enc_finished ++// Bit [4] - I16MB_share_ipred_mode_with_I4MB ++// Bit [3] - fixed_picture_qp ++// Bit [2] - use_set_b8_mode ( not used now) ++// Bit [1] - use_set_mb_skip_run ++// Bit [0] - pop_coeff_even_all_zero ++#define HCODEC_VLC_CONFIG (0x1d01) ++#define P_HCODEC_VLC_CONFIG (volatile unsigned int *)((0x1d01 << 2) + 0xff620000) ++// -------------------------------------------- ++// Bitstream DDR Interface ++// -------------------------------------------- ++#define HCODEC_VLC_VB_START_PTR (0x1d10) ++#define P_HCODEC_VLC_VB_START_PTR (volatile unsigned int *)((0x1d10 << 2) + 0xff620000) ++#define HCODEC_VLC_VB_END_PTR (0x1d11) ++#define P_HCODEC_VLC_VB_END_PTR (volatile unsigned int *)((0x1d11 << 2) + 0xff620000) ++#define HCODEC_VLC_VB_WR_PTR (0x1d12) ++#define P_HCODEC_VLC_VB_WR_PTR (volatile unsigned int *)((0x1d12 << 2) + 0xff620000) ++// Read Only, VLC_VB_SW_RD_PTR or VLC_VB_HW_RD_PTR ++#define HCODEC_VLC_VB_RD_PTR (0x1d13) ++#define P_HCODEC_VLC_VB_RD_PTR (volatile unsigned int *)((0x1d13 << 2) + 0xff620000) ++#define HCODEC_VLC_VB_SW_RD_PTR (0x1d14) ++#define P_HCODEC_VLC_VB_SW_RD_PTR (volatile unsigned int *)((0x1d14 << 2) + 0xff620000) ++// Read Only ++#define HCODEC_VLC_VB_LEFT (0x1d15) ++#define P_HCODEC_VLC_VB_LEFT (volatile unsigned int *)((0x1d15 << 2) + 0xff620000) ++// VB FIFO Control ++// bit [31:24] vb_full_int_enable_cpu[7:0] ++// bit [23:16] vb_full_int_enable_amrisc[7:0] ++// -bit 23 Video BUFFER LEFT < 0x400 Bytes ++// -bit 22 Video BUFFER LEFT < 0x200 Bytes ++// -bit 21 Video BUFFER LEFT < 0x100 Bytes ++// -bit 20 Video BUFFER LEFT < 0x80 Bytes ++// -bit 19 Video BUFFER LEFT < 0x40 Bytes ++// -bit 18 Video BUFFER LEFT < 0x20 Bytes ++// -bit 17 vbfifo left < 16 double words (8x64bits) ++// -bit 16 vbfifo left < 8 double words (4x64bits) ++// bit [15] wr_ptr_int_enable_cpu ++// bit [14] wr_ptr_int_enable_amrisc ++// bit [13] wr_ptr_int (Read Only, write 1 will clear) ++// bit [12] vb_full_int_enable_cpu(Read Only) ++// bit [11] vb_full_int_enable_amrisc(Read Only) ++// bit [10] reserved ++// bit [9] use_vb_hw_rd_ptr ++// bit [8] vb_always_ready Set to 1 to ignore vb_level blocking DDR write ++// bit [7] vb_ready_for_transfer (Read Only) ++// bit [6] data_ready_for_transfer (Read Only) ++// bits [5:3] vb_endian Set VB Endian inside DDR memory ++// bit [2] vb_write_busy Read Only - indicate DDR write busy ++// bit [1] vb_write_en Set to 1 to enable writing data to DDR memory ++// bit [0] vb_soft_reset Soft reset ++#define HCODEC_VLC_VB_CONTROL (0x1d16) ++#define P_HCODEC_VLC_VB_CONTROL (volatile unsigned int *)((0x1d16 << 2) + 0xff620000) ++// bit 31 transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request // default : 0 ++// bit 30 A_urgent // default : 0 ++// bit 29:24 A_brst_num // default : 0x3f ++// bit 23:22 reserved ++// bit 21:16 A_id // default : 0x20 ++// bit 15:0 vb_left_hold // default : 0 ++#define HCODEC_VLC_VB_MEM_CTL (0x1d17) ++#define P_HCODEC_VLC_VB_MEM_CTL (volatile unsigned int *)((0x1d17 << 2) + 0xff620000) ++// vb_wr_ptr address to generate interrupt ++#define HCODEC_VLC_VB_INT_PTR (0x1d18) ++#define P_HCODEC_VLC_VB_INT_PTR (volatile unsigned int *)((0x1d18 << 2) + 0xff620000) ++// bit[31:12] reserved ++// bit[11:0] vlc_wrrsp_count ++#define HCODEC_VLC_WRRSP (0x1d19) ++#define P_HCODEC_VLC_WRRSP (volatile unsigned int *)((0x1d19 << 2) + 0xff620000) ++#define HCODEC_VLC_TOTAL_BYTES (0x1d1a) ++#define P_HCODEC_VLC_TOTAL_BYTES (volatile unsigned int *)((0x1d1a << 2) + 0xff620000) ++// bit [31:26] reserved ++// bit [25] vb_flush ++// bit [24] vb_reg_ready ++// bit [23:16] vb_buff_left -- Read only ++// bit [15:8] vb_buff_wr_point -- RW ++// bit [7:0] vb_buff_rd_point -- RW ++#define HCODEC_VLC_VB_BUFF (0x1d1b) ++#define P_HCODEC_VLC_VB_BUFF (volatile unsigned int *)((0x1d1b << 2) + 0xff620000) ++// bit[31] flush_vlc_pre_buff ++// bit[30:27] reserved ++// bit[26:24] vb_pre_buff_level ++// bit[23:0] vb_pre_buff_data[55:32] ++#define HCODEC_VLC_VB_PRE_BUFF_HI (0x1d1c) ++#define P_HCODEC_VLC_VB_PRE_BUFF_HI (volatile unsigned int *)((0x1d1c << 2) + 0xff620000) ++// bit[31:0] vb_pre_buff_data[31:0] ++#define HCODEC_VLC_VB_PRE_BUFF_LOW (0x1d1d) ++#define P_HCODEC_VLC_VB_PRE_BUFF_LOW (volatile unsigned int *)((0x1d1d << 2) + 0xff620000) ++// bit[31] stream_encap_enable // 0x0000(00-03) will be changed to 0x000003(00-03) if enabled ++// bit[30:29] stream_encap_delay // delay bytes for encap used ++// bit[28:24] stream_buff_point ++// bit[23:0] stream_buff_data ++#define HCODEC_VLC_STREAM_BUFF (0x1d1e) ++#define P_HCODEC_VLC_STREAM_BUFF (volatile unsigned int *)((0x1d1e << 2) + 0xff620000) ++// bit[31] push_stream_block - Read Only (Will set if vb_buff full) ++// bit[30] push_stream_busy - Read Only (busy when output one byte from stream_buf (max 2 clocks for 8 bits push) ++// bit[29:28] stream_encap_status - Read Only ++// bit[27:21] reserved ++// Long Mode : (Amrisc need movilo and mvihi high to set stream_info) ++// bit[20:16] push_stream_long_length (0 or 31 : Mid or Short mode) ++// bit[15:0] push_stream_data ++// Mid Mode : (Amrisc need movi to set stream_info) ++// bit[15:12]] push_stream_mid_length (1-12 : mid mode active, 0-short mode, 15 - byte align) ++// bit[11:0] push_stream_data ++// Short Mode : (Amrisc can use mtspi to push stream directely) ++// bit[7:5] push_stream_short_length (0-5 : short length, else - invalid) ++// bit[4:0] push_stream_data ++#define HCODEC_VLC_PUSH_STREAM (0x1d1f) ++#define P_HCODEC_VLC_PUSH_STREAM (volatile unsigned int *)((0x1d1f << 2) + 0xff620000) ++// bit[15:8] ELEMENT_LENGTH ++// bit[7:1] reserved ++// bit[0] Write - push start, Read - Push Busy ++#define HCODEC_VLC_PUSH_ELEMENT (0x1d20) ++#define P_HCODEC_VLC_PUSH_ELEMENT (volatile unsigned int *)((0x1d20 << 2) + 0xff620000) ++#define HCODEC_VLC_ELEMENT_DATA (0x1d21) ++#define P_HCODEC_VLC_ELEMENT_DATA (volatile unsigned int *)((0x1d21 << 2) + 0xff620000) ++// bit[7] hcmd_intra_use_sw_info ++// bit[6] hcmd_use_sw_info ++// bit[5] always_use_info_0_cbp_blk ++// bit[4] always_update_info_0_cbp_blk ++// bit[3] reset_left_mb_wr ++// bit[2] reset_top_mb_wr ++// bit[1] set_left_mb_wr ++// bit[0] set_top_mb_wr ++#define HCODEC_VLC_SPECIAL_CTL (0x1d22) ++#define P_HCODEC_VLC_SPECIAL_CTL (volatile unsigned int *)((0x1d22 << 2) + 0xff620000) ++// bit[28] left_intra ++// bit[27:22] left_quant ++// bit[21:16] left_quant_c ++// bit[12] top_intra ++// bit[11:6] top_quant ++// bit[5:0] top_quant_c ++#define HCODEC_VLC_HCMD_T_L_INFO (0x1d23) ++#define P_HCODEC_VLC_HCMD_T_L_INFO (volatile unsigned int *)((0x1d23 << 2) + 0xff620000) ++// bit[12] cur_intra ++// bit[11:6] cur_quant ++// bit[5:0] cur_quant_c ++#define HCODEC_VLC_HCMD_CUR_INFO (0x1d24) ++#define P_HCODEC_VLC_HCMD_CUR_INFO (volatile unsigned int *)((0x1d24 << 2) + 0xff620000) ++// bit[13] top_left_info_in_data_mv_cal ++// bit[12] only_use_info_0_top_left_in_I ++// bit[11] top_left_info_in_data ++// bit[10] early_mix_mc_hcmd ++// bit[9] update_top_left_mix ++// bit[8] p_top_left_mix ++// bit[7] mv_cal_mixed_type ++// bit[6] mc_hcmd_mixed_type ++// bit[5] use_seperate_int_control ++// bit[4] hcmd_intra_use_q_info ++// bit[3] hcmd_left_use_prev_info ++// bit[2] hcmd_use_q_info ++// bit[1] use_q_delta_quant ++// bit[0] detect_I16_from_I4 ++#define HCODEC_VLC_ADV_CONFIG (0x1d25) ++#define P_HCODEC_VLC_ADV_CONFIG (volatile unsigned int *)((0x1d25 << 2) + 0xff620000) ++// 31 - use_hcmd_mb_xy_auto ++//23:16 - hcmd_max_mb_x ++//15:8 - hcmd_mb_y_auto ++// 7:0 - hcmd_mb_x_auto ++#define HCODEC_VLC_HCMD_MBXY_AUTO (0x1d26) ++#define P_HCODEC_VLC_HCMD_MBXY_AUTO (volatile unsigned int *)((0x1d26 << 2) + 0xff620000) ++// bit[31:0] vlc_int_control_inter -- will be used when use_seperate_int_control is set ++#define HCODEC_VLC_INT_CONTROL_INTER (0x1d2f) ++#define P_HCODEC_VLC_INT_CONTROL_INTER (volatile unsigned int *)((0x1d2f << 2) + 0xff620000) ++// -------------------------------------------- ++// Picture VLC ++// -------------------------------------------- ++// (&(int|(~AND_enable))|(|(int&OR_enable))) ++// bit[31] OR interrupt Enable Reserved ++// bit[30] OR interrupt Enable for mv_busy ++// bit[29] OR interrupt Enable for b8_mode_busy ++// bit[28] OR interrupt Enable for mb_skip_run_busy ++// bit[27] OR interrupt Enable for cbp_busy ++// bit[26] OR interrupt Enable for Reserved ++// bit[25] OR interrupt Enable for Reserved ++// bit[24] OR interrupt Enable for mb_info_busy ++// bit[23] AND interrupt Enable Reserved ++// bit[22] AND interrupt Enable for mv_busy ++// bit[21] AND interrupt Enable for b8_mode_busy ++// bit[20] AND interrupt Enable for mb_skip_run_busy ++// bit[19] AND interrupt Enable for cbp_busy ++// bit[18] AND interrupt Enable for Reserved ++// bit[17] AND interrupt Enable for Reserved ++// bit[16] AND interrupt Enable for mb_info_busy ++// bit[15] OR interrupt Enable Reserved ++// bit[14] OR interrupt Enable for mvd ++// bit[13] OR interrupt Enable for b8_mode ++// bit[12] OR interrupt Enable for mb_skip_run ++// bit[11] OR interrupt Enable for cbp_ready ++// bit[10] OR interrupt Enable for c_ipred_mode_ready ++// bit[9] OR interrupt Enable for ipred_mode_ready ++// bit[8] OR interrupt Enable for mb_info_ready ++// bit[7] AND interrupt Enable Reserved ++// bit[6] AND interrupt Enable for mvd ++// bit[5] AND interrupt Enable for b8_mode ++// bit[4] AND interrupt Enable for mb_skip_run ++// bit[3] AND interrupt Enable for cbp_ready ++// bit[2] AND interrupt Enable for c_ipred_mode_ready ++// bit[1] AND interrupt Enable for ipred_mode_ready ++// bit[0] AND interrupt Enable for mb_info_ready ++#define HCODEC_VLC_INT_CONTROL (0x1d30) ++#define P_HCODEC_VLC_INT_CONTROL (volatile unsigned int *)((0x1d30 << 2) + 0xff620000) ++// Bit[31:16] picture_height ++// Bit[15:0] picture_width ++#define HCODEC_VLC_PIC_SIZE (0x1d31) ++#define P_HCODEC_VLC_PIC_SIZE (volatile unsigned int *)((0x1d31 << 2) + 0xff620000) ++// [31:16] Reserved ++// [15:3] pic_width_in_mbs_minus1 ++// [2:0] picture_type ++#define HCODEC_VLC_PIC_INFO (0x1d32) ++#define P_HCODEC_VLC_PIC_INFO (volatile unsigned int *)((0x1d32 << 2) + 0xff620000) ++// Bit[31:16] MB_NR ++// Bit[15:8] MBY ++// Bit[7:0] MBX ++#define HCODEC_VLC_PIC_POSITION (0x1d33) ++#define P_HCODEC_VLC_PIC_POSITION (volatile unsigned int *)((0x1d33 << 2) + 0xff620000) ++// Bit[31] MV_busy ++// Bit[30:6] Reserved ++// Bit[15] Reserved ++// Bit[14] vlc_input_MV_busy ++// Bit[13] vlc_input_b8_mode_busy ++// Bit[12] vlc_input_mb_skip_run_busy ++// Bit[11] vlc_input_cbp_busy ++// Bit[10] Reserved ++// Bit[9] Reserved ++// Bit[8] vlc_input_mb_info_busy ++// Bit[7] Reserved ++// Bit[6] mvd ++// Bit[5] b8_mode ++// Bit[4] mb_skip_run ++// Bit[3] cbp ++// Bit[2] c_ipred_mode ++// Bit[1] ipred_mode ++// Bit[0] mb_info ( mb_type, mb_x, mb_y) ++#define HCODEC_VLC_INPUT_STATUS (0x1d34) ++#define P_HCODEC_VLC_INPUT_STATUS (volatile unsigned int *)((0x1d34 << 2) + 0xff620000) ++// Bit[31:28] detected_mb_type ++// Bit[27:16] mb_y ++// Bit[15:4] mb_x ++// Bit[3:0] mb_type ++#define HCODEC_VLC_MB_INFO (0x1d35) ++#define P_HCODEC_VLC_MB_INFO (volatile unsigned int *)((0x1d35 << 2) + 0xff620000) ++// commnad 0 -- no pending ++// normal command + 1 is pending command ++// ++// bit 31:28 -- pending command 7 ++// bit 27:24 -- pending command 6 ++// bit 23:20 -- pending command 5 ++// bit 19:16 -- pending command 4 ++// bit 15:12 -- pending command 3 ++// bit 11:8 -- pending command 2 ++// bit 7:4 -- pending command 1 ++// bit 3:0 -- pending command 0 ++#define HCODEC_VLC_ENC_PEND_CMD (0x1d36) ++#define P_HCODEC_VLC_ENC_PEND_CMD (volatile unsigned int *)((0x1d36 << 2) + 0xff620000) ++// For I Slice ++// Bit[31:16] Reserved ++// Bit[15:0] IntraType ++#define HCODEC_HENC_TOP_INFO_0 (0x1d37) ++#define P_HCODEC_HENC_TOP_INFO_0 (volatile unsigned int *)((0x1d37 << 2) + 0xff620000) ++#define HCODEC_HENC_LEFT_INFO_0 (0x1d38) ++#define P_HCODEC_HENC_LEFT_INFO_0 (volatile unsigned int *)((0x1d38 << 2) + 0xff620000) ++// For I Slice ++// Bit[31:24] V_nnz ++// Bit[23:16] U_nnz ++// Bit[15:0] Y_nnz ++#define HCODEC_HENC_TOP_INFO_1 (0x1d39) ++#define P_HCODEC_HENC_TOP_INFO_1 (volatile unsigned int *)((0x1d39 << 2) + 0xff620000) ++#define HCODEC_HENC_LEFT_INFO_1 (0x1d3a) ++#define P_HCODEC_HENC_LEFT_INFO_1 (volatile unsigned int *)((0x1d3a << 2) + 0xff620000) ++// bit[63:0] ipred_mode ++#define HCODEC_VLC_IPRED_MODE_HI (0x1d3b) ++#define P_HCODEC_VLC_IPRED_MODE_HI (volatile unsigned int *)((0x1d3b << 2) + 0xff620000) ++#define HCODEC_VLC_IPRED_MODE_LO (0x1d3c) ++#define P_HCODEC_VLC_IPRED_MODE_LO (volatile unsigned int *)((0x1d3c << 2) + 0xff620000) ++// bit[15:8] SE delta quant ++// bit[7:0] UE delta quant ++#define HCODEC_VLC_DELTA_QP (0x1d3d) ++#define P_HCODEC_VLC_DELTA_QP (volatile unsigned int *)((0x1d3d << 2) + 0xff620000) ++// bit[31:16] Reserved ++// bit[15:12] Reserved ++// bit[11:8] c_ipred_mode ++// bit[7:0] cbp ++#define HCODEC_VLC_MB_HEADER_INFO (0x1d3e) ++#define P_HCODEC_VLC_MB_HEADER_INFO (volatile unsigned int *)((0x1d3e << 2) + 0xff620000) ++// bit[31:16] mb_skip_run ++// bit[15:0] b8_mode ++#define HCODEC_VLC_P_MB_HEADER_INFO (0x1d3f) ++#define P_HCODEC_VLC_P_MB_HEADER_INFO (volatile unsigned int *)((0x1d3f << 2) + 0xff620000) ++// bit[31] write_ptr_update ++// bit[30] read_ptr_update ++// bit[29:20] coeff_buf_level ++// bit[19:10] coeff_buf_write_ptr ++// bit[9:0] coeff_buf_read_ptr ++#define HCODEC_VLC_COEFF_BUF_STATUS (0x1d40) ++#define P_HCODEC_VLC_COEFF_BUF_STATUS (volatile unsigned int *)((0x1d40 << 2) + 0xff620000) ++// bit[31:10] Reserved ++// bit[9:0] read_req_addr ++#define HCODEC_VLC_COEFF_RD_REQ (0x1d41) ++#define P_HCODEC_VLC_COEFF_RD_REQ (volatile unsigned int *)((0x1d41 << 2) + 0xff620000) ++// bit[20] - coeff_buf_read_finished ++// bit[19] - coeff_first ++// bit[18:4] - coeff_level ++// bit[3:0] - coeff_run ++#define HCODEC_VLC_COEFF (0x1d42) ++#define P_HCODEC_VLC_COEFF (volatile unsigned int *)((0x1d42 << 2) + 0xff620000) ++// bit[31] - coeff_info_ready ++// bit[30:25] - Reserved ++// bit[24:15] - block_begin_addr ++// bit[14:11] - trailing_one_sign ++// bit[10:6] - total_coeff ++// bit[5:4] - trailing_ones ++// bit[3:0] - total_zeros ++#define HCODEC_VLC_COEFF_INFO (0x1d43) ++#define P_HCODEC_VLC_COEFF_INFO (volatile unsigned int *)((0x1d43 << 2) + 0xff620000) ++// bit[31] write_ptr_update ++// bit[30] read_ptr_update ++// bit[29:25] Reserved ++// bit[24:20] dc_buf_level -- 0-16 ++// bit[19:15] Reserved ++// bit[14:10] dc_buf_write_ptr ++// bit[9:5] Reserved ++// bit[4:0] dc_buf_read_ptr ++#define HCODEC_VLC_DC_BUF_STATUS (0x1d44) ++#define P_HCODEC_VLC_DC_BUF_STATUS (volatile unsigned int *)((0x1d44 << 2) + 0xff620000) ++// bit[31:10] Reserved ++// bit[9:4] Reserved ++// bit[3:0] read_req_addr ++#define HCODEC_VLC_DC_RD_REQ (0x1d45) ++#define P_HCODEC_VLC_DC_RD_REQ (volatile unsigned int *)((0x1d45 << 2) + 0xff620000) ++// bit[31:17] - Reserved ++// bit[16] - dc_first ++// bit[15:1] - dc_level ++// bit[0] - dc_type 0 - CDC, 1 - LDC ++#define HCODEC_VLC_DC (0x1d46) ++#define P_HCODEC_VLC_DC (volatile unsigned int *)((0x1d46 << 2) + 0xff620000) ++// bit[31] - dc_info_ready ++// bit[30:25] - Reserved ++// bit[24:20] - Reserved ++// bit[19:15] - dc_idx_begin_addr ++// bit[14:11] - dc_trailing_one_sign ++// bit[10:6] - dc_total_coeff ++// bit[5:4] - dc_trailing_ones ++// bit[3:0] - dc_total_zeros ++#define HCODEC_VLC_DC_INFO (0x1d47) ++#define P_HCODEC_VLC_DC_INFO (volatile unsigned int *)((0x1d47 << 2) + 0xff620000) ++// bit[31:4] - Reserved ++// bit[3:0] - mv_rw_idx (auto increment when read/write VLC_MV) ++#define HCODEC_VLC_MV_INDEX (0x1d48) ++#define P_HCODEC_VLC_MV_INDEX (volatile unsigned int *)((0x1d48 << 2) + 0xff620000) ++// bit[31:16] - MVY ++// bit[15:0] - MVX ++#define HCODEC_VLC_MV (0x1d49) ++#define P_HCODEC_VLC_MV (volatile unsigned int *)((0x1d49 << 2) + 0xff620000) ++// bit[31:16] - MVY ++// bitp15:0] - MVX ++// Write to HENC_TOP_MV_0 will cause previous U->UL, UR->U, and UR write ++// Read will read U MV only ++#define HCODEC_HENC_TOP_MV_0 (0x1d4a) ++#define P_HCODEC_HENC_TOP_MV_0 (volatile unsigned int *)((0x1d4a << 2) + 0xff620000) ++#define HCODEC_HENC_TOP_MV_1 (0x1d4b) ++#define P_HCODEC_HENC_TOP_MV_1 (volatile unsigned int *)((0x1d4b << 2) + 0xff620000) ++#define HCODEC_HENC_TOP_MV_2 (0x1d4c) ++#define P_HCODEC_HENC_TOP_MV_2 (volatile unsigned int *)((0x1d4c << 2) + 0xff620000) ++#define HCODEC_HENC_TOP_MV_3 (0x1d4d) ++#define P_HCODEC_HENC_TOP_MV_3 (volatile unsigned int *)((0x1d4d << 2) + 0xff620000) ++#define HCODEC_HENC_LEFT_MV_0 (0x1d4e) ++#define P_HCODEC_HENC_LEFT_MV_0 (volatile unsigned int *)((0x1d4e << 2) + 0xff620000) ++#define HCODEC_HENC_LEFT_MV_1 (0x1d4f) ++#define P_HCODEC_HENC_LEFT_MV_1 (volatile unsigned int *)((0x1d4f << 2) + 0xff620000) ++#define HCODEC_HENC_LEFT_MV_2 (0x1d50) ++#define P_HCODEC_HENC_LEFT_MV_2 (volatile unsigned int *)((0x1d50 << 2) + 0xff620000) ++#define HCODEC_HENC_LEFT_MV_3 (0x1d51) ++#define P_HCODEC_HENC_LEFT_MV_3 (volatile unsigned int *)((0x1d51 << 2) + 0xff620000) ++// Bit[31:1] Reserved ++// Bit[0] top_left_mv_ready ++#define HCODEC_TOP_LEFT_READY (0x1d52) ++#define P_HCODEC_TOP_LEFT_READY (volatile unsigned int *)((0x1d52 << 2) + 0xff620000) ++// Bit[31:16] Reserved ++// Bit[15:0] mb_skip_run ++#define HCODEC_MB_SKIP_RUN (0x1d53) ++#define P_HCODEC_MB_SKIP_RUN (volatile unsigned int *)((0x1d53 << 2) + 0xff620000) ++// Bit[31:16] Reserved ++// Bit[15] Reserved ++// Bit[14:13] rd_struct // 00 - frame, 10 - top field, 11 - bottom field ++// Bit[12:11] wr_struct // 00 - frame, 10 - top field, 11 - bottom field ++// Bit[10:5] mv_buff_id ++// Bit[4:0] mv_ref ++#define HCODEC_VLC_HCMD_CONFIG (0x1d54) ++#define P_HCODEC_VLC_HCMD_CONFIG (volatile unsigned int *)((0x1d54 << 2) + 0xff620000) ++// Bit[9:0] h264_dblk_info ++#define HCODEC_VLC_HCMD_DBLK_INFO (0x1d55) ++#define P_HCODEC_VLC_HCMD_DBLK_INFO (volatile unsigned int *)((0x1d55 << 2) + 0xff620000) ++// Bit[3:0] vlc_dbg_idx ++#define HCODEC_VLC_DBG_IDX (0x1d56) ++#define P_HCODEC_VLC_DBG_IDX (volatile unsigned int *)((0x1d56 << 2) + 0xff620000) ++// Read Only ++#define HCODEC_VLC_DBG_READ (0x1d57) ++#define P_HCODEC_VLC_DBG_READ (volatile unsigned int *)((0x1d57 << 2) + 0xff620000) ++// [ 29] RW jpeg_comp2_ac_table_sel. Default 0. ++// [ 28] RW jpeg_comp2_dc_table_sel. Default 0. ++// [26:25] RW jpeg_comp2_cnt_max. Default 0. ++// [ 24] RW jpeg_comp2_en. Set 1 if the scan will include component 2 (Cr). Default 0. ++// [ 21] RW jpeg_comp1_ac_table_sel. Default 0. ++// [ 20] RW jpeg_comp1_dc_table_sel. Default 0. ++// [18:17] RW jpeg_comp1_cnt_max. Default 0. ++// [ 16] RW jpeg_comp1_en. Set 1 if the scan will include component 1 (Cb). Default 0. ++// [ 13] RW jpeg_comp0_ac_table_sel. Default 0. ++// [ 12] RW jpeg_comp0_dc_table_sel. Default 0. ++// [10: 9] RW jpeg_comp0_cnt_max. Default 0. ++// [ 8] RW jpeg_comp0_en. Set 1 if the scan will include component 0 (Y). Default 0. ++// [ 1] W jpeg_coeff_init. Write 1 to this bit to initialize JPEG run length encoder. ++// [ 0] RW jpeg_en. 0=Disable JPEG encoder; 1=Enable JPEG encoder. Default 0. ++#define HCODEC_VLC_JPEG_CTRL (0x1d58) ++#define P_HCODEC_VLC_JPEG_CTRL (volatile unsigned int *)((0x1d58 << 2) + 0xff620000) ++// [ 13] RW jpeg_coeff_buf_overfl. Write this bit to 1 to clear overfl. ++// [ 12] RW jpeg_coeff_buf_undrfl. Write this bit to 1 to clear undrfl. ++// [ 11] R jpeg_coeff_buf_full. ++// [ 10] R jpeg_coeff_buf_empty. ++// [ 8: 0] R jpeg_coeff_buf_level. ++#define HCODEC_VLC_JPEG_COEFF_BUF_STAT (0x1d59) ++#define P_HCODEC_VLC_JPEG_COEFF_BUF_STAT (volatile unsigned int *)((0x1d59 << 2) + 0xff620000) ++// [ 16] RW JPEG HUFFMAN table access mode. 0=Write; 1=Read. Default 1. ++// [ 8: 0] RW JPEG HUFFMAN table addr. Default 0. ++#define HCODEC_VLC_HUFFMAN_ADDR (0x1d5a) ++#define P_HCODEC_VLC_HUFFMAN_ADDR (volatile unsigned int *)((0x1d5a << 2) + 0xff620000) ++// [19: 0] RW JPEG HUFFMAN table data. ++#define HCODEC_VLC_HUFFMAN_DATA (0x1d5b) ++#define P_HCODEC_VLC_HUFFMAN_DATA (volatile unsigned int *)((0x1d5b << 2) + 0xff620000) ++// bit[31:0] enc_mv_bits - including b8_mode and mvd ++#define HCODEC_VLC_ENC_MV_BITS (0x1d5c) ++#define P_HCODEC_VLC_ENC_MV_BITS (volatile unsigned int *)((0x1d5c << 2) + 0xff620000) ++// bit[31:0] enc_coeff_bits - including cbp, token, trailing_sign, coeff_enc, h264_totzeros, h264_run ++#define HCODEC_VLC_ENC_COEFF_BITS (0x1d5d) ++#define P_HCODEC_VLC_ENC_COEFF_BITS (volatile unsigned int *)((0x1d5d << 2) + 0xff620000) ++// ++// Closing file: vlc_regs.h ++// ++// ++// Reading file: qdct_regs.h ++// ++//======================================================================== ++// QDCT module level register offset ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DOS_HCODEC_QDCT_CBUS_BASE = 0x0f ++// ----------------------------------------------- ++// bit[31:28] - mb_info_state ++#define HCODEC_QDCT_STATUS_CTRL (0x1f00) ++#define P_HCODEC_QDCT_STATUS_CTRL (volatile unsigned int *)((0x1f00 << 2) + 0xff620000) ++// bit[18] - enable_free_clk_sad_top ++// bit[17] - enable_free_clk_ie_top ++// bit[16] - enable_free_clk_ie_sub ++// bit[15] - enable_free_clk_mc_out ++// bit[14] - enable_free_clk_i_pred_top ++// bit[13] - enable_free_clk_idct_top ++// bit[12] - enable_free_clk_iq_top ++// bit[11] - enable_free_clk_q_top ++// bit[10] - enable_free_clk_dc_buff_8 ++// bit[9] - enable_free_clk_dct_top ++// bit[8] - enable_free_clk_mb_info ++// bit[7] - enable_free_clk_mb_buff ++// bit[6] - enable_free_clk_reg ++// bit[5] - ignore_1_include_2nd_half_c ++// bit[4] - ignore_1_include_2nd_half ++// bit[3] - ignore_t_p8x8 ++// bit[2] - not_ignore_dc ++// bit[1] - ignore_small_lac_intra ++// bit[0] - disable_fast_zero_block ++#define HCODEC_QDCT_CONFIG (0x1f01) ++#define P_HCODEC_QDCT_CONFIG (volatile unsigned int *)((0x1f01 << 2) + 0xff620000) ++// bit[31] - ignore_lac_coeff_en ++// bit[30:26] - ignore_lac_coeff_else ++// bit[25:21] - ignore_lac_coeff_2 ++// bit[20:16] - ignore_lac_coeff_1 ++// bit[15] - ignore_cac_coeff_en ++// bit[14:10] - ignore_cac_coeff_else ++// bit[9:5] - ignore_cac_coeff_2 ++// bit[4:0] - ignore_cac_coeff_1 ++#define HCODEC_IGNORE_CONFIG (0x1f02) ++#define P_HCODEC_IGNORE_CONFIG (volatile unsigned int *)((0x1f02 << 2) + 0xff620000) ++// bit[31] - ignore_t_lac_coeff_en ++// bit[30:26] - ignore_t_lac_coeff_else ++// bit[25:21] - ignore_t_lac_coeff_2 ++// bit[20:16] - ignore_t_lac_coeff_1 ++// bit[15] - ignore_cdc_coeff_en ++// bit[14] - ignore_t_lac_coeff_else_le_3 ++// bit[13] - ignore_t_lac_coeff_else_le_4 ++// bit[12] - ignore_cdc_only_when_empty_cac_inter ++// bit[11] - ignore_cdc_only_when_one_empty_inter ++// bit[10:9] - ignore_cdc_range_max_inter // 0-0, 1-1, 2,-2, 3-3 ++// bit[8:7] - ignore_cdc_abs_max_inter // 0-1, 1-2, 2,-3, 3-4 ++// bit[6] - reserved ++// bit[5] - ignore_cdc_only_when_empty_cac_intra ++// bit[4] - ignore_cdc_only_when_one_empty_intra ++// bit[3:2] - ignore_cdc_range_max_intra // 0-0, 1-1, 2,-2, 3-3 ++// bit[1:0] - ignore_cdc_abs_max_intra // 0-1, 1-2, 2,-3, 3-4 ++#define HCODEC_IGNORE_CONFIG_2 (0x1f03) ++#define P_HCODEC_IGNORE_CONFIG_2 (volatile unsigned int *)((0x1f03 << 2) + 0xff620000) ++// -------------------------------------------- ++// MB DATA DDR Interface ++// -------------------------------------------- ++#define HCODEC_QDCT_MB_START_PTR (0x1f10) ++#define P_HCODEC_QDCT_MB_START_PTR (volatile unsigned int *)((0x1f10 << 2) + 0xff620000) ++#define HCODEC_QDCT_MB_END_PTR (0x1f11) ++#define P_HCODEC_QDCT_MB_END_PTR (volatile unsigned int *)((0x1f11 << 2) + 0xff620000) ++#define HCODEC_QDCT_MB_WR_PTR (0x1f12) ++#define P_HCODEC_QDCT_MB_WR_PTR (volatile unsigned int *)((0x1f12 << 2) + 0xff620000) ++#define HCODEC_QDCT_MB_RD_PTR (0x1f13) ++#define P_HCODEC_QDCT_MB_RD_PTR (volatile unsigned int *)((0x1f13 << 2) + 0xff620000) ++#define HCODEC_QDCT_MB_LEVEL (0x1f14) ++#define P_HCODEC_QDCT_MB_LEVEL (volatile unsigned int *)((0x1f14 << 2) + 0xff620000) ++// bit [31] disable_mbxy_ie_save ++// bit [30] no_wait_after_q_cdc ++// bit [29] ie_start_int_enable ++// bit [28] ignore_t_p8x8 ++// bit [27] zero_mc_out_null_non_skipped_mb ++// bit [26] no_mc_out_null_non_skipped_mb ++// bit [25] mc_out_even_skipped_mb ++// bit [24] mc_out_wait_cbp_ready ++// bit [23] mc_out_wait_mb_type_ready ++// bit [22] i_pred_int_enable ++// bit [21] intra_sat8_enable ++// bit [20] ie_sub_enable ++// bit [19] i_pred_enable ++// bit [18] iq_enable ++// bit [17] idct_enable ++// bit [16] no_zero_coeff_mb ++// bit [15] add_zero_coeff_block ++// bit [14] mb_pause_enable ++// bit [13] q_enable ++// bit [12] dct_enable ++// bit [11] ignore_magic_word ++// bit [10] mb_info_en ++// bit [9] mb_info_soft_reset ++// bit [8] mb_always_ready Set to 1 to ignore mb_level blocking DDR read ++// bit [7] mb_ready_for_transfer (Read Only) ++// bit [6] data_ready_for_transfer (Read Only) ++// bits [5:3] mb_endian Set MB Endian inside DDR memory ++// bit [2] mb_read_busy Read Only - indicate DDR read busy ++// bit [1] mb_read_en Set to 1 to enable reading data from DDR memory ++// bit [0] mb_soft_reset Soft reset ++#define HCODEC_QDCT_MB_CONTROL (0x1f15) ++#define P_HCODEC_QDCT_MB_CONTROL (volatile unsigned int *)((0x1f15 << 2) + 0xff620000) ++// bit 31 transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request // default : 0 ++// bit 30 A_urgent // default : 0 ++// bit 29:24 A_brst_num // default : 0x3f ++// bit 23 reserved ++// bit 22 read_till_zero ++// bit 21:16 A_id // default : 0x21 ++// bit 15:0 mb_level_hold // default : 0 ++#define HCODEC_QDCT_MB_MEM_CTL (0x1f16) ++#define P_HCODEC_QDCT_MB_MEM_CTL (volatile unsigned int *)((0x1f16 << 2) + 0xff620000) ++// bit [31:24] reserved ++// bit [23:16] vb_buff_level -- Read only ++// bit [15:8] vb_buff_wr_point -- RW ++// bit [7:0] vb_buff_rd_point -- RW ++#define HCODEC_QDCT_MB_BUFF (0x1f17) ++#define P_HCODEC_QDCT_MB_BUFF (volatile unsigned int *)((0x1f17 << 2) + 0xff620000) ++// bit [31:0] mb infor data begin magic word - default : 0xa55aaa55 ++#define HCODEC_QDCT_MB_MAGIC_WORD (0x1f18) ++#define P_HCODEC_QDCT_MB_MAGIC_WORD (volatile unsigned int *)((0x1f18 << 2) + 0xff620000) ++// Read Only Register ++// bit[19] dct_ready_1 ++// bit[18] dct_ready_0 ++// bit[17] dct_rd_idx ++// bit[16] dct_wr_idx ++// bit[15] dct_srdy ++// bit[14] dct_rrdy ++// bit[13] Reserved ++// bit[12:8] dct_block_number ++// bit[7:4] dct_rw_addr ++// bit[3:0] dct_status ++#define HCODEC_QDCT_DCT_STATUS (0x1f19) ++#define P_HCODEC_QDCT_DCT_STATUS (volatile unsigned int *)((0x1f19 << 2) + 0xff620000) ++// bit[24:23] vlc_quant_count ++// bit[22:16] vlc_delta_quant_data ++// bit[15:10] vlc_quant_data ++// bit[9:4] vlc_prev_quant_data ++// bit[3:0] q_status ++#define HCODEC_QDCT_Q_STATUS (0x1f1a) ++#define P_HCODEC_QDCT_Q_STATUS (volatile unsigned int *)((0x1f1a << 2) + 0xff620000) ++// bit[31:3] Reserved ++// bit[2:0] picture_type ++#define HCODEC_QDCT_PIC_INFO (0x1f1b) ++#define P_HCODEC_QDCT_PIC_INFO (volatile unsigned int *)((0x1f1b << 2) + 0xff620000) ++// bit[31:28] Reserved ++// bit[27:22] I_pic_quant_c ++// bit[21:16] I_pic_quant ++// bit[15] reserved ++// bit[14:12] quant_rem_c ++// bit[11:8] quant_per_c ++// bit[7] reserved ++// bit[6:4] quant_rem ++// bit[3:0] quant_per ++#define HCODEC_QDCT_Q_QUANT_I (0x1f1c) ++#define P_HCODEC_QDCT_Q_QUANT_I (volatile unsigned int *)((0x1f1c << 2) + 0xff620000) ++// bit[31:28] Reserved ++// bit[27:22] P_pic_quant_c ++// bit[21:16] P_pic_quant ++// bit[15] reserved ++// bit[14:12] quant_rem_c ++// bit[11:8] quant_per_c ++// bit[7] reserved ++// bit[6:4] quant_rem ++// bit[3:0] quant_per ++#define HCODEC_QDCT_Q_QUANT_P (0x1f1d) ++#define P_HCODEC_QDCT_Q_QUANT_P (volatile unsigned int *)((0x1f1d << 2) + 0xff620000) ++// bit[31] mb_info_pause ++// bit[30:16] pause_mby ++// bit[15:0] pause_mbx ++#define HCODEC_QDCT_MB_PAUSE_CTL (0x1f1e) ++#define P_HCODEC_QDCT_MB_PAUSE_CTL (volatile unsigned int *)((0x1f1e << 2) + 0xff620000) ++// bit[31] top_control_ready_i_pred ++// bit[30:28]top_dma_status ++// bit[27] top_control_ready_ie ++// bit[26:24]Reserved ++// bit[23] ul_mb ++// bit[22] right_mb ++// bit[21] top_mb ++// bit[20] left_mb ++// bit[19:8] mb_x ++// bit[7:6] i_pred_ref_idx_L ++// bit[5:4] i_pred_ref_idx_UL ++// bit[3:2] i_pred_ref_idx_U ++// bit[1:0] i_pred_ref_idx_UR ++#define HCODEC_QDCT_TOP_CONTROL (0x1f1f) ++#define P_HCODEC_QDCT_TOP_CONTROL (volatile unsigned int *)((0x1f1f << 2) + 0xff620000) ++// bit[31:0] top_base_addr - DDR Memory start address for save top Pixel ++#define HCODEC_QDCT_TOP_BASE_MEM (0x1f20) ++#define P_HCODEC_QDCT_TOP_BASE_MEM (volatile unsigned int *)((0x1f20 << 2) + 0xff620000) ++// bit 15:13 Reserved ++// bit 12 A_urgent // default : 0 ++// bit 11:6 A_brst_num // default : 0x3f ++// bit 5:0 A_id // default : 0x22 ++#define HCODEC_QDCT_TOP_MEM_CTL (0x1f21) ++#define P_HCODEC_QDCT_TOP_MEM_CTL (volatile unsigned int *)((0x1f21 << 2) + 0xff620000) ++// bit [11:0] top_wrrsp_count ++#define HCODEC_QDCT_TOP_WRRSP (0x1f22) ++#define P_HCODEC_QDCT_TOP_WRRSP (volatile unsigned int *)((0x1f22 << 2) + 0xff620000) ++// Bit[3:0] qdct_dbg_idx ++#define HCODEC_QDCT_DBG_IDX (0x1f23) ++#define P_HCODEC_QDCT_DBG_IDX (volatile unsigned int *)((0x1f23 << 2) + 0xff620000) ++// Read Only ++#define HCODEC_QDCT_DBG_READ (0x1f24) ++#define P_HCODEC_QDCT_DBG_READ (volatile unsigned int *)((0x1f24 << 2) + 0xff620000) ++// [19:18] RW jdct_inflow_ctrl. JPEG DCT input flow control. Default 0. ++// 0=No halt; ++// 1=DCT halts request at end of each 8x8 block; ++// 2=DCT halts request at end of each MCU. ++// [17:16] RW jpeg_coeff_last_sel. Default 0. ++// Select at which point to finish processing, give update to AmRISC so it can control the next step. ++// 0=Mark last coeff at the end of an 8x8 block; ++// 1=Mark at the end of an MCU; ++// 2=Mark at the end of a scan. ++// [ 15] RW jpeg_quant_sel_comp2. 0=Comp2 select Quantization table 0; 1=Select table 1. Default 0. ++// [ 14] RW jpeg_v_factor_comp2. Component 2's vertical sampling factor. Default 0. ++// [ 13] RW jpeg_h_factor_comp2. Component 2's horizontal sampling factor. Default 0. ++// [ 12] RW jpeg_comp2_en. Set 1 if the scan will include component 2 (Cr). Default 0. ++// [ 11] RW jpeg_quant_sel_comp1. 0=Comp1 select Quantization table 0; 1=Select table 1. Default 0. ++// [ 10] RW jpeg_v_factor_comp1. Component 1's vertical sampling factor. Default 0. ++// [ 9] RW jpeg_h_factor_comp1. Component 1's horizontal sampling factor. Default 0. ++// [ 8] RW jpeg_comp1_en. Set 1 if the scan will include component 1 (Cb). Default 0. ++// [ 7] RW jpeg_quant_sel_comp0. 0=Comp0 select Quantization table 0; 1=Select table 1. Default 0. ++// [ 6] RW jpeg_v_factor_comp0. Component 0's vertical sampling factor. Default 0. ++// [ 5] RW jpeg_h_factor_comp0. Component 0's horizontal sampling factor. Default 0. ++// [ 4] RW jpeg_comp0_en. Set 1 if the scan will include component 0 (Y). Default 0. ++// [ 3: 1] RW jdct_intr_sel. JPEG DCT interrupt select. Default 0. ++// 0=Disable intr; ++// 1=Intr at end of each 8x8 block of DCT input; ++// 2=Intr at end of each MCU of DCT input; ++// 3=Intr at end of a scan of DCT input; ++// 4=Intr at end of each 8x8 block of DCT output; ++// 5=Intr at end of each MCU of DCT output; ++// 6=Intr at end of a scan of DCT output. ++// [ 0] RW jpeg_en. 0=Disable JPEG QDCT; 1=Enable JPEG QDCT. Default 0. ++#define HCODEC_QDCT_JPEG_CTRL (0x1f25) ++#define P_HCODEC_QDCT_JPEG_CTRL (volatile unsigned int *)((0x1f25 << 2) + 0xff620000) ++// [29:16] RW jpeg_x_end. Picture X end. Default 0. ++// [13: 0] RW jpeg_x_start. Picture X start. Default 0. ++#define HCODEC_QDCT_JPEG_X_START_END (0x1f26) ++#define P_HCODEC_QDCT_JPEG_X_START_END (volatile unsigned int *)((0x1f26 << 2) + 0xff620000) ++// [29:16] RW jpeg_y_end. Picture Y end. Default 0. ++// [13: 0] RW jpeg_y_start. Picture Y start. Default 0. ++#define HCODEC_QDCT_JPEG_Y_START_END (0x1f27) ++#define P_HCODEC_QDCT_JPEG_Y_START_END (volatile unsigned int *)((0x1f27 << 2) + 0xff620000) ++// [ 8] RW JPEG QUANT table access mode. 0=Write; 1=Read. Default 1. ++// [ 5: 0] RW JPEG QUANT table addr. Default 0. ++#define HCODEC_QDCT_JPEG_QUANT_ADDR (0x1f28) ++#define P_HCODEC_QDCT_JPEG_QUANT_ADDR (volatile unsigned int *)((0x1f28 << 2) + 0xff620000) ++// [31: 0] RW JPEG QUANT table data. ++#define HCODEC_QDCT_JPEG_QUANT_DATA (0x1f29) ++#define P_HCODEC_QDCT_JPEG_QUANT_DATA (volatile unsigned int *)((0x1f29 << 2) + 0xff620000) ++// [ 1] W resume_jdct. ++// Write 1 to this bit will resume JPEG input engine when previously ++// it is halted by QDCT_JPEG_CTRL.jdct_inflow_ctrl. ++// [ 0] W jpeg_sof. ++// Write 1 to this bit will start JPEG input engine. ++#define HCODEC_QDCT_JPEG_SOF_RESUME (0x1f2a) ++#define P_HCODEC_QDCT_JPEG_SOF_RESUME (volatile unsigned int *)((0x1f2a << 2) + 0xff620000) ++// [31:30] R dct_st. jdct_ctrl state. 0=IDLE; 1=WAIT; 2=DCT_REQ. ++// [29:28] R mfdin_comp. Current component at pixel request to MFDIN. ++// [27:14] R mfdin_y. Current Y at pixel request to MFDIN. ++// [13: 0] R mfdin_x. Current X at pixel request to MFDIN. ++#define HCODEC_QDCT_JPEG_DCT_STATUS0 (0x1f2b) ++#define P_HCODEC_QDCT_JPEG_DCT_STATUS0 (volatile unsigned int *)((0x1f2b << 2) + 0xff620000) ++// [15:12] R JPEG Quant read MEM select. ++// [11: 8] R JPEG DCT2 write MEM select. ++// [ 7: 4] R JPEG DCT2 read MEM select. ++// [ 3: 0] R JPEG DCT1 write MEM select. ++#define HCODEC_QDCT_JPEG_DCT_STATUS1 (0x1f2c) ++#define P_HCODEC_QDCT_JPEG_DCT_STATUS1 (volatile unsigned int *)((0x1f2c << 2) + 0xff620000) ++// [28:16] RW jdct_coeff1. Default 13'h1D90; // 7568 = 4096 * sqrt(2) * (cos(Pi/8) + sin(Pi/8)) // 7569 ++// [12: 0] RW jdct_coeff0. Default 13'h16A1; // 5793 = 4096 * sqrt(2) ++#define HCODEC_QDCT_JPEG_DCT_COEFF01 (0x1f2d) ++#define P_HCODEC_QDCT_JPEG_DCT_COEFF01 (volatile unsigned int *)((0x1f2d << 2) + 0xff620000) ++// [28:16] RW jdct_coeff3. Default 13'h0C3F; // 3135 = 4096 * sqrt(2) * (cos(Pi/8) - sin(Pi/8)) ++// [12: 0] RW jdct_coeff2. Default 13'h08A9; // 2217 = 4096 * sqrt(2) * sin(Pi/8) // 2215 ++#define HCODEC_QDCT_JPEG_DCT_COEFF23 (0x1f2e) ++#define P_HCODEC_QDCT_JPEG_DCT_COEFF23 (volatile unsigned int *)((0x1f2e << 2) + 0xff620000) ++// [28:16] RW jdct_coeff5. Default 13'h046A; // 1130 = 4096 * (cos(3Pi/16) - sin(3Pi/16)) ++// [12: 0] RW jdct_coeff4. Default 13'h1631; // 5681 = 4096 * (cos(3Pi/16) + sin(3Pi/16)) // 5682 ++#define HCODEC_QDCT_JPEG_DCT_COEFF45 (0x1f2f) ++#define P_HCODEC_QDCT_JPEG_DCT_COEFF45 (volatile unsigned int *)((0x1f2f << 2) + 0xff620000) ++// [28:16] RW jdct_coeff7. Default 13'h0C92; // 3218 = 4096 * (cos(Pi/16) - sin(Pi/16)) ++// [12: 0] RW jdct_coeff6. Default 13'h12D0; // 4816 = 4096 * (cos(Pi/16) + sin(Pi/16)) ++#define HCODEC_QDCT_JPEG_DCT_COEFF67 (0x1f30) ++#define P_HCODEC_QDCT_JPEG_DCT_COEFF67 (volatile unsigned int *)((0x1f30 << 2) + 0xff620000) ++// [28:16] RW jdct_coeff9. Default 13'h0FB1; // 4017 = 4096 * cos(Pi/16) ++// [12: 0] RW jdct_coeff8. Default 13'h0D4E; // 3406 = 4096 * cos(3Pi/16) ++#define HCODEC_QDCT_JPEG_DCT_COEFF89 (0x1f31) ++#define P_HCODEC_QDCT_JPEG_DCT_COEFF89 (volatile unsigned int *)((0x1f31 << 2) + 0xff620000) ++#define HCODEC_QDCT_I_PRED_REF_WR_IDX (0x1f32) ++#define P_HCODEC_QDCT_I_PRED_REF_WR_IDX (volatile unsigned int *)((0x1f32 << 2) + 0xff620000) ++#define HCODEC_QDCT_I_PRED_REF_WR_DATA (0x1f33) ++#define P_HCODEC_QDCT_I_PRED_REF_WR_DATA (volatile unsigned int *)((0x1f33 << 2) + 0xff620000) ++// bit[29] mb_info_latch_no_I16_pred_mode ++// bit[28] ie_dma_mbxy_use_i_pred ++// bit[27] ie_dma_read_write_use_ip_idx ++// bit[26] ie_start_use_top_dma_count ++// bit[25] i_pred_top_dma_rd_mbbot ++// bit[24] i_pred_top_dma_wr_disable ++// bit[23] i_pred_mix ++// bit[22] me_ab_rd_when_intra_in_p ++// bit[21] force_mb_skip_run_when_intra ++// bit[20] mc_out_mixed_type ++// bit[19] ie_start_when_quant_not_full ++// bit[18] mb_info_state_mix ++// bit[17] mb_type_use_mix_result ++// bit[16] me_cb_ie_read_enable ++// bit[15] ie_cur_data_from_me ++// bit[14] rem_per_use_table ++// bit[13] q_latch_int_enable ++// bit[12] q_use_table ++// bit[11] q_start_wait ++// bit[10] LUMA_16_LEFT_use_cur ++// bit[9] DC_16_LEFT_SUM_use_cur ++// bit[8] c_ref_ie_sel_cur ++// bit[7] c_ipred_perfect_mode ++// bit[6] ref_ie_ul_sel 0-old, 1-use next_set ++// bit[5] mb_type_use_ie_result ++// bit[4] detect_I16_from_I4 ++// bit[3] ie_not_wait_ref_busy ++// bit[2] ie_I16_enable ++// bit[1:0] ie_done_sel (0, 1, 2, -1) ++#define HCODEC_QDCT_ADV_CONFIG (0x1f34) ++#define P_HCODEC_QDCT_ADV_CONFIG (volatile unsigned int *)((0x1f34 << 2) + 0xff620000) ++// bit [31:16] I16x16_weight ++// bit [15:0] I4x4_weight ++#define HCODEC_IE_WEIGHT (0x1f35) ++#define P_HCODEC_IE_WEIGHT (volatile unsigned int *)((0x1f35 << 2) + 0xff620000) ++// bit [31] reserved ++// bit [30] q_I16MB ++// bit [29] reserved ++// bit [28] reserved ++// bit [27:23] quant_table_addr I4MB:[0,7], I16MB:[8:15], INTER:[16:23], Reserved:[24:31] ++// bit [22] quant_table_addr_update(when notupdate_rem_per) (read is arb_result : q_intra) ++// bit [21:19] quant_rem_c ++// bit [18:16] quant_rem_y ++// bit [15:12] quant_per_c ++// bit [11:8] quant_per_y ++// bit [7:2] quant ++// bit [1] update_rem_per ++// bit [0] clear_wait_status ++#define HCODEC_Q_QUANT_CONTROL (0x1f36) ++#define P_HCODEC_Q_QUANT_CONTROL (volatile unsigned int *)((0x1f36 << 2) + 0xff620000) ++#define HCODEC_MBBOT_EVEN_ADDR (0x1f37) ++#define P_HCODEC_MBBOT_EVEN_ADDR (volatile unsigned int *)((0x1f37 << 2) + 0xff620000) ++#define HCODEC_MBBOT_ODD_ADDR (0x1f38) ++#define P_HCODEC_MBBOT_ODD_ADDR (volatile unsigned int *)((0x1f38 << 2) + 0xff620000) ++// bit [29:24] quant_table_data_3 ++// bit [21:16] quant_table_data_2 ++// bit [13:8] quant_table_data_1 ++// bit [5:0] quant_table_data_0 ++#define HCODEC_QUANT_TABLE_DATA (0x1f39) ++#define P_HCODEC_QUANT_TABLE_DATA (volatile unsigned int *)((0x1f39 << 2) + 0xff620000) ++// bit [31:16] ie_sad_offset_I16 ++// bit [15:0] ie_sad_offset_I4 ++#define HCODEC_SAD_CONTROL_0 (0x1f3a) ++#define P_HCODEC_SAD_CONTROL_0 (volatile unsigned int *)((0x1f3a << 2) + 0xff620000) ++// bit [31] sad_soft_reset ++// bit [30:27] reserved ++// bit [26:24] ie_sad_shift_I16 ++// bit [22:20] ie_sad_shift_I4 ++// bit [18:16] me_sad_shift_INTER ++// bit [15:0] me_sad_offset_INTER ++#define HCODEC_SAD_CONTROL_1 (0x1f3b) ++#define P_HCODEC_SAD_CONTROL_1 (volatile unsigned int *)((0x1f3b << 2) + 0xff620000) ++// bit [31] vlc_quant_rd_ptr ++// bit [30] vlc_quant_rd_ptr_update ++// bit [29] vlc_quant_wr_ptr ++// bit [28] vlc_quant_wr_ptr_update ++// bit [27:26] reserved ++// bit [25:19] vlc_delta_quant_1 ++// bit [18:13] vlc_quant_1 ++// bit [12:6] vlc_delta_quant_0 ++// bit [5:0] vlc_quant_0 ++#define HCODEC_QDCT_VLC_QUANT_CTL_0 (0x1f3c) ++#define P_HCODEC_QDCT_VLC_QUANT_CTL_0 (volatile unsigned int *)((0x1f3c << 2) + 0xff620000) ++// bit [31:30] me_sad_rd_idx ++// bit [29] me_sad_rd_idx_update ++// bit [28:27] me_sad_wr_idx ++// bit [26] me_sad_wr_idx_update ++// bit [25:24] ie_sad_rd_idx ++// bit [23] ie_sad_rd_idx_update ++// bit [22:21] ie_sad_wr_idx ++// bit [20] ie_sad_wr_idx_update ++// bit [19:12] Reserved ++// bit [11:6] vlc_max_delta_q_neg ++// bit [5:0] vlc_max_delta_q_pos ++#define HCODEC_QDCT_VLC_QUANT_CTL_1 (0x1f3d) ++#define P_HCODEC_QDCT_VLC_QUANT_CTL_1 (volatile unsigned int *)((0x1f3d << 2) + 0xff620000) ++// bit[4] jdct_int ++// bit[3] quant_latch ++// bit[2] me_done ++// bit[1] ie_start ++// bit[0] i_pred_start ++#define HCODEC_QDCT_INT_STATUS (0x1f3e) ++#define P_HCODEC_QDCT_INT_STATUS (volatile unsigned int *)((0x1f3e << 2) + 0xff620000) ++// bit[3] mix_i_pred_wait_left_en ++// bit[2:0] mc_pending_mb_count ++#define HCODEC_QDCT_MIX_I_PRED_STATUS (0x1f3f) ++#define P_HCODEC_QDCT_MIX_I_PRED_STATUS (volatile unsigned int *)((0x1f3f << 2) + 0xff620000) ++// IE/ME share same cbus_base as QDCT ++// ++// bit[31] active_ur_block ++// bit[30] active_ul_block ++// bit[21] disable_HENC_V_PRED_16 ++// bit[20] disable_HENC_H_PRED_16 ++// bit[19] disable_HENC_DC_PRED_16 ++// bit[18] disable_HENC_HENC_HOR_UP_PRED ++// bit[17] disable_HENC_VERT_LEFT_PRED ++// bit[16] disable_HENC_HENC_HOR_DOWN_PRED ++// bit[15] disable_HENC_VERT_RIGHT_PRED ++// bit[14] disable_HENC_DIAG_DOWN_RIGHT_PRED ++// bit[13] disable_HENC_DIAG_DOWN_LEFT_PRED ++// bit[12] disable_HENC_DC_PRED ++// bit[11] disable_HENC_HOR_PRED ++// bit[10] disable_HENC_VERT_PRED ++// bit[9] ie_c_wait_ie_pause ++// bit[8:4] max_ie_result_buff_count ++// bit[3] ie_wait_for_ie_result // use for (max_ie_result_buff_count == 0) to wait every block ++// bit[2] reserved ++// bit[1] ie_enable ++// bit[0] ie_soft_reset ++#define HCODEC_IE_CONTROL (0x1f40) ++#define P_HCODEC_IE_CONTROL (volatile unsigned int *)((0x1f40 << 2) + 0xff620000) ++// bit[31:12] Reserved ++// bit[11:0] mb_y ++#define HCODEC_IE_MB_POSITION (0x1f41) ++#define P_HCODEC_IE_MB_POSITION (volatile unsigned int *)((0x1f41 << 2) + 0xff620000) ++// bit[31:16] me_skip_run ++// bit[15:8] reserved ++// bit [7:4] me_b8_mode ++// bit [3:0] ie_me_mb_type ++#define HCODEC_IE_ME_MB_INFO (0x1f42) ++#define P_HCODEC_IE_ME_MB_INFO (volatile unsigned int *)((0x1f42 << 2) + 0xff620000) ++// bit[3] ie_result_buff_enable ++// bit[2] ie_result_buff_soft_reset ++// bit[1] sad_enable ++// bit[0] ie_sad_soft_reset ++#define HCODEC_SAD_CONTROL (0x1f43) ++#define P_HCODEC_SAD_CONTROL (volatile unsigned int *)((0x1f43 << 2) + 0xff620000) ++// bit[31:16] - ie_result_buff_count - read only ++// bit[14:12] -current_ie_result (pred_mode) - read only ++// bit[11] top_control_data_buff_wr_ptr - rd/wr ++// bit[10] top_control_data_buff_rd_ptr - rd/wr ++// bit[9:5] ie_result_buff_wr_ptr - rd/wr ++// bit[4:0] ie_result_buff_rd_ptr - rd/wr ++#define HCODEC_IE_RESULT_BUFFER (0x1f44) ++#define P_HCODEC_IE_RESULT_BUFFER (volatile unsigned int *)((0x1f44 << 2) + 0xff620000) ++// bit[63:0] ie_i4_pred_mode ++#define HCODEC_IE_I4_PRED_MODE_HI (0x1f45) ++#define P_HCODEC_IE_I4_PRED_MODE_HI (volatile unsigned int *)((0x1f45 << 2) + 0xff620000) ++#define HCODEC_IE_I4_PRED_MODE_LO (0x1f46) ++#define P_HCODEC_IE_I4_PRED_MODE_LO (volatile unsigned int *)((0x1f46 << 2) + 0xff620000) ++// bit [31:9] reserved ++// bit [8:4] i_pred_block_number ++// bit [3:0] ie_c_pred_mode ++#define HCODEC_IE_C_PRED_MODE (0x1f47) ++#define P_HCODEC_IE_C_PRED_MODE (volatile unsigned int *)((0x1f47 << 2) + 0xff620000) ++// 31:16 - Left, 0-select ie_pixel, 1-select mc_data_out ++// 15:0 - Top, 0-select ie_pixel, 1-select mc_data_out ++#define HCODEC_IE_CUR_REF_SEL (0x1f48) ++#define P_HCODEC_IE_CUR_REF_SEL (volatile unsigned int *)((0x1f48 << 2) + 0xff620000) ++// bit[31] enable_f_skip_1_step_3 ++// bit[30] enable_f_skip_1_step_2 ++// bit[29] enable_f_skip_1_step_1 ++// bit[28] step_3_enable ++// bit[27] step_2_sub_pixel ++// bit[26] always_f_skip_step_3 ++// bit[25] always_f_skip_step_2 ++// bit[24] always_f_skip_step_1 ++// bit[23] half_pixel_only ++// bit[22:13] reserved ++// bit[12] adv_mv_enable ++// bit[11] sad_short_valid ++// bit[10:9] mv_flexable_ctl 00:0x40, 01:0x80, 10:0xc0, 11 : 0x100 ++// bit[8] no_md_ab_rd ++// bit[7] use_dct_state ++// bit[6] enable_free_clk_me_ctl ++// bit[5] enable_free_clk_me_ab ++// bit[4] enable_free_clk_me_cb ++// bit[3] reserved ++// bit[2] me_done_int_enable ++// bit[1] me_enable ++// bit[0] me_soft_reset ++#define HCODEC_ME_CONTROL (0x1f49) ++#define P_HCODEC_ME_CONTROL (volatile unsigned int *)((0x1f49 << 2) + 0xff620000) ++// bit[31:28] Reserved ++// bit[27:16] me_start_mby ++// bit[15:12] Reserved ++// bit[11:0] me_start_mbx ++#define HCODEC_ME_START_POSITION (0x1f4a) ++#define P_HCODEC_ME_START_POSITION (volatile unsigned int *)((0x1f4a << 2) + 0xff620000) ++// bit [31:28] me_status - Read only ++// bit [27:24] me_cb_status // current buffer ++// bit [23:20] me_ab_status // anc buffer ++// bit [19] Reserved ++// bit [18:16] me_ab_wr_ptr // read only ++// bit [15:4] me_last_mbx ++// bit [3:1] me_ab_rd_ptr // read only ++// bit [0] me_action ++#define HCODEC_ME_STATUS (0x1f4b) ++#define P_HCODEC_ME_STATUS (volatile unsigned int *)((0x1f4b << 2) + 0xff620000) ++// all Read-only ++// bit [31:28] Reserved ++// bit [27:16] me_ab_mbx ++// bit [15:14] me_cb_wr_ptr ++// bit [13:12] me_cb_rd_ptr ++// bit [11:0] me_cb_mbx ++#define HCODEC_ME_DEBUG (0x1f4c) ++#define P_HCODEC_ME_DEBUG (volatile unsigned int *)((0x1f4c << 2) + 0xff620000) ++// bit[29:24] step_3_skip_line ++// bit[23:18] step_2_skip_line ++// bit[17:12] step_1_skip_line ++// bit[11:6] step_0_skip_line ++// bit[5:0] read_skip_line ++#define HCODEC_ME_SKIP_LINE (0x1f4d) ++#define P_HCODEC_ME_SKIP_LINE (volatile unsigned int *)((0x1f4d << 2) + 0xff620000) ++// bit 15:13 Reserved ++// bit 12 A_urgent // default : 0 ++// bit 11:6 A_brst_num // default : 0x3f ++// bit 5:0 A_id // default : 0x23 ++#define HCODEC_ME_AB_MEM_CTL (0x1f4e) ++#define P_HCODEC_ME_AB_MEM_CTL (volatile unsigned int *)((0x1f4e << 2) + 0xff620000) ++// bit[31:24] anc_pic_canvas ++// bit[23:12] max_me_mby_num ++// bit[11:0] max_me_mbx_num ++#define HCODEC_ME_PIC_INFO (0x1f4f) ++#define P_HCODEC_ME_PIC_INFO (volatile unsigned int *)((0x1f4f << 2) + 0xff620000) ++// bit [23:12] me_sad_enough_1 ++// bit [11:0] me_sad_enough_0 ++#define HCODEC_ME_SAD_ENOUGH_01 (0x1f50) ++#define P_HCODEC_ME_SAD_ENOUGH_01 (volatile unsigned int *)((0x1f50 << 2) + 0xff620000) ++// bit [25:12] adv_mv_8x8_enough ++// bit [11:0] me_sad_enough_2 ++#define HCODEC_ME_SAD_ENOUGH_23 (0x1f51) ++#define P_HCODEC_ME_SAD_ENOUGH_23 (volatile unsigned int *)((0x1f51 << 2) + 0xff620000) ++// bit [21:10] me_step0_big_sad ++// bit [9:5] me_step0_close_mv_y ++// bit [4:0] me_step0_close_mv_x ++#define HCODEC_ME_STEP0_CLOSE_MV (0x1f52) ++#define P_HCODEC_ME_STEP0_CLOSE_MV (volatile unsigned int *)((0x1f52 << 2) + 0xff620000) ++// bit[31:24] force_skip_sad_3 ++// bit[23:16] force_skip_sad_2 ++// bit[15:08] force_skip_sad_1 ++// bit[07:00] force_skip_sad_0 ++#define HCODEC_ME_F_SKIP_SAD (0x1f53) ++#define P_HCODEC_ME_F_SKIP_SAD (volatile unsigned int *)((0x1f53 << 2) + 0xff620000) ++// bit[31:24] force_skip_weight_3 ++// bit[23:16] force_skip_weight_2 ++// bit[15:08] force_skip_weight_1 ++// bit[07:00] force_skip_weight_0 ++#define HCODEC_ME_F_SKIP_WEIGHT (0x1f54) ++#define P_HCODEC_ME_F_SKIP_WEIGHT (volatile unsigned int *)((0x1f54 << 2) + 0xff620000) ++// Merge when ( ++// (flex & me_merge_flex_en) | ++// (big_sad & me_merge_sad_en)| ++// ((~me_merge_flex_en)&(~me_merge_sad_en)) ++// ) & ++// ( small_mv_diff |(~me_merge_small_mv_en)) ++// & (me_merge_flex_en | me_merge_sad_en | me_merge_small_mv_en) ++// bit[31] me_merge_mv_en_16 ++// bit[30] me_merge_small_mv_en_16 ++// bit[29] me_merge_flex_en_16 ++// bit[28] me_merge_sad_en_16 ++// bit[27] me_merge_mv_en_8 ++// bit[26] me_merge_small_mv_en_8 ++// bit[25] me_merge_flex_en_8 ++// bit[24] me_merge_sad_en_8 ++// bit[23:18] me_merge_mv_diff_16 ++// bit[17:12] me_merge_mv_diff_8 ++// bit[11:0] me_merge_min_sad ++#define HCODEC_ME_MV_MERGE_CTL (0x1f55) ++#define P_HCODEC_ME_MV_MERGE_CTL (volatile unsigned int *)((0x1f55 << 2) + 0xff620000) ++// bit[31:24] mv_step_weight_1 ++// bit[23:16] mv_pre_weight_1 ++// bit [15:0] mv_step_weight_0 ++// bit[7:0] mv_pre_weight_0 ++#define HCODEC_ME_MV_WEIGHT_01 (0x1f56) ++#define P_HCODEC_ME_MV_WEIGHT_01 (volatile unsigned int *)((0x1f56 << 2) + 0xff620000) ++// bit[31:24] mv_step_weight_3 (mv_step_weight_1_2nd) ++// bit[23:16] mv_pre_weight_3 (mv_pre_weight_1_2nd) ++// bit[15:8] mv_step_weight_2 ++// bit[7:0] mv_pre_weight_2 ++#define HCODEC_ME_MV_WEIGHT_23 (0x1f57) ++#define P_HCODEC_ME_MV_WEIGHT_23 (volatile unsigned int *)((0x1f57 << 2) + 0xff620000) ++// bit[31:24] me_sad_range_inc_3 ++// bit[23:16] me_sad_range_inc_2 ++// bit[15:8] me_sad_range_inc_1 ++// bit[7:0] me_sad_range_inc_0 ++#define HCODEC_ME_SAD_RANGE_INC (0x1f58) ++#define P_HCODEC_ME_SAD_RANGE_INC (volatile unsigned int *)((0x1f58 << 2) + 0xff620000) ++// bit[31:19] reserved ++// bit[18] sub_relative_any_1_en ++// bit[17] sub_relative_any_2_en ++// bit[16] sub_relative_any_3_en ++// bit[15] sub_relative_any_4_en ++// bit[14] sub_relative_any_h_en ++// bit[13] sub_make_non_flex_fix ++// bit[12] sub_make_big_non_flex_fix ++// bit[11:8] sub_normal_mv_diff_16 ++// bit[7:4] sub_normal_mv_diff_8 ++// bit[3:2] Reserved ++// bit[1] sub_merge_enable_16 ++// bit[0] sub_merge_enable_8 ++#define HCODEC_ME_SUB_MERGE_CTL (0x1f59) ++#define P_HCODEC_ME_SUB_MERGE_CTL (volatile unsigned int *)((0x1f59 << 2) + 0xff620000) ++// bit[31:28] sub_ref_mv_diff_near ++// bit[27:24] sub_ref_mv_diff_near_flex ++// bit[23:20] sub_ref_mv_diff ++// bit[19:16] sub_ref_mv_diff_flex ++// bit[15:8] sub_ref_mv_near_weight ++// bit[7:0] sub_ref_mv_weight ++#define HCODEC_ME_SUB_REF_MV_CTL (0x1f5a) ++#define P_HCODEC_ME_SUB_REF_MV_CTL (volatile unsigned int *)((0x1f5a << 2) + 0xff620000) ++// bit[31:24] sub_weight_max_sad ++// bit[23:16] sub_any_range_sad ++// bit[15:8] sub_any_min_sad ++// bit[7:0] sub_any_max_sad ++#define HCODEC_ME_SUB_ANY_WEIGHT_SAD (0x1f5b) ++#define P_HCODEC_ME_SUB_ANY_WEIGHT_SAD (volatile unsigned int *)((0x1f5b << 2) + 0xff620000) ++// bit[31:24] sub_fix_sad ++// bit[23:16] sub_fix_diff_sad ++// bit[15:8] sub_sad_flex_adj ++// bit[7:0] sub_big_non_flex_fix_sad ++#define HCODEC_ME_SUB_FIX_SAD (0x1f5c) ++#define P_HCODEC_ME_SUB_FIX_SAD (volatile unsigned int *)((0x1f5c << 2) + 0xff620000) ++// bit[31:24] sub_fix_min_sad ++// bit[23:16] sub_fix_min_diff_sad ++// bit[15:8] sub_fix_min_sad_2 ++// bit[7:0] sub_fix_min_diff_sad_2 ++#define HCODEC_ME_SUB_FIX_MIN_SAD (0x1f5d) ++#define P_HCODEC_ME_SUB_FIX_MIN_SAD (volatile unsigned int *)((0x1f5d << 2) + 0xff620000) ++// bit[31:24] sub_snap_to_ref_max_sad ++// bit[23] sub_snap_to_ref_non_flex ++// bit[22:16] sub_snap_to_ref_mv_diff ++// bit[15:4] sub_glitch_mv_sad ++// bit[3:0] sub_glitch_mv_diff ++#define HCODEC_ME_SUB_SNAP_GLITCH (0x1f5e) ++#define P_HCODEC_ME_SUB_SNAP_GLITCH (volatile unsigned int *)((0x1f5e << 2) + 0xff620000) ++// bit[31:20] sad_act_limit ++// bit[19:8] s_a_any_sad ++// bit[7] Reserved ++// bit[6:5] sub_merge_method ++// bit[4] use_sub_act_result ++// bit[3] s_a_rnd ++// bit[2] Reserved ++// bit[1] sub_act_en_16 ++// bit[0] sub_act_en ++#define HCODEC_ME_SUB_ACT_CTL (0x1f5f) ++#define P_HCODEC_ME_SUB_ACT_CTL (volatile unsigned int *)((0x1f5f << 2) + 0xff620000) ++// bit[31:16] reserved ++// bit[15:0] me_weight ++#define HCODEC_ME_WEIGHT (0x1f60) ++#define P_HCODEC_ME_WEIGHT (volatile unsigned int *)((0x1f60 << 2) + 0xff620000) ++// bit[31] ready_update ++// bit[30] data_update ++// bit[29:28] reserved ++// bit[27:22] me_quant_0 ++// bit[21] ie_sad_ready_0 ++// bit[20:18] Reserved ++// bit[17:16] me_sad_mv_type_0 ++// bit[15:0] me_sad_0 ++#define HCODEC_ME_SAD_0 (0x1f61) ++#define P_HCODEC_ME_SAD_0 (volatile unsigned int *)((0x1f61 << 2) + 0xff620000) ++// bit[31] ready_update ++// bit[30] data_update ++// bit[29:28] reserved ++// bit[27:22] me_quant_1 ++// bit[21] me_sad_ready_1 ++// bit[20:18] Reserved ++// bit[17:16] me_sad_mv_type_1 ++// bit[15:0] me_sad_1 ++#define HCODEC_ME_SAD_1 (0x1f62) ++#define P_HCODEC_ME_SAD_1 (volatile unsigned int *)((0x1f62 << 2) + 0xff620000) ++// bit[31] ready_update ++// bit[30] data_update ++// bit[29:28] reserved ++// bit[27:22] me_quant_2 ++// bit[21] me_sad_ready_2 ++// bit[20:18] Reserved ++// bit[17:16] me_sad_mv_type_2 ++// bit[15:0] me_sad_2 ++#define HCODEC_ME_SAD_2 (0x1f63) ++#define P_HCODEC_ME_SAD_2 (volatile unsigned int *)((0x1f63 << 2) + 0xff620000) ++// bit[31] ready_update ++// bit[30] data_update ++// bit[29:28] reserved ++// bit[27:22] me_quant_3 ++// bit[21] me_sad_ready_3 ++// bit[20:18] Reserved ++// bit[17:16] me_sad_mv_type_3 ++// bit[15:0] me_sad_3 ++#define HCODEC_ME_SAD_3 (0x1f64) ++#define P_HCODEC_ME_SAD_3 (volatile unsigned int *)((0x1f64 << 2) + 0xff620000) ++// bit[31] ready_update ++// bit[30] data_update ++// bit[29:28] reserved ++// bit[27:22] ie_quant_0 ++// bit[21] ie_sad_ready_0 ++// bit[20] I4/I16 (0-I4MB, 1-I16MB) ++// bit[19:0] ie_sad_0 ++#define HCODEC_IE_SAD_0 (0x1f65) ++#define P_HCODEC_IE_SAD_0 (volatile unsigned int *)((0x1f65 << 2) + 0xff620000) ++// bit[31] ready_update ++// bit[30] data_update ++// bit[29:28] reserved ++// bit[27:22] ie_quant_1 ++// bit[21] ie_sad_ready_1 ++// bit[20] I4/I16 (0-I4MB, 1-I16MB) ++// bit[19:0] ie_sad_1 ++#define HCODEC_IE_SAD_1 (0x1f66) ++#define P_HCODEC_IE_SAD_1 (volatile unsigned int *)((0x1f66 << 2) + 0xff620000) ++// bit[31] ready_update ++// bit[30] data_update ++// bit[29:28] reserved ++// bit[27:22] ie_quant_2 ++// bit[21] ie_sad_ready_2 ++// bit[20] I4/I16 (0-I4MB, 1-I16MB) ++// bit[19:0] ie_sad_2 ++#define HCODEC_IE_SAD_2 (0x1f67) ++#define P_HCODEC_IE_SAD_2 (volatile unsigned int *)((0x1f67 << 2) + 0xff620000) ++// bit[31] ready_update ++// bit[30] data_update ++// bit[29:28] reserved ++// bit[27:22] ie_quant_3 ++// bit[21] ie_sad_ready_3 ++// bit[20] I4/I16 (0-I4MB, 1-I16MB) ++// bit[19:0] ie_sad_3 ++#define HCODEC_IE_SAD_3 (0x1f68) ++#define P_HCODEC_IE_SAD_3 (volatile unsigned int *)((0x1f68 << 2) + 0xff620000) ++// bit[31] enable_large_diff_16x8 ++// bit[30] enable_large_diff_8x16 ++// bit[29:16] adv_mv_8x8_weight ++// bit[15:14] reserved ++// bit[13:0] adv_mv_4x4x4_weight ++#define HCODEC_ADV_MV_CTL0 (0x1f69) ++#define P_HCODEC_ADV_MV_CTL0 (volatile unsigned int *)((0x1f69 << 2) + 0xff620000) ++// bit[31:16] adv_mv_16x16_weight ++// bit[15] enable_large_diff_16x16 ++// bit[14:0] adv_mv_16_8_weight ++#define HCODEC_ADV_MV_CTL1 (0x1f6a) ++#define P_HCODEC_ADV_MV_CTL1 (volatile unsigned int *)((0x1f6a << 2) + 0xff620000) ++#define HCODEC_ADV_MV_CTL2 (0x1f6b) ++#define P_HCODEC_ADV_MV_CTL2 (volatile unsigned int *)((0x1f6b << 2) + 0xff620000) ++// bit[31] v3_skip_enable ++// bit[30] v3_step_1_weight_enable // for step1, will only use pre_weight for block0, only step_weight for block 1,2,3 ++// bit[29] v3_l2_skip_only_use_l2_sad // set to 1 may allow l1 maybe not skip ++// bit[28] v3_mv_sad_weight_enable ++// bit[27] v3_ipred_type_enable ++// bit[25:12] force_skip_sad_1 ++// bit[11:0] force_skip_sad_0 ++#define HCODEC_V3_SKIP_CONTROL (0x1f6c) ++#define P_HCODEC_V3_SKIP_CONTROL (volatile unsigned int *)((0x1f6c << 2) + 0xff620000) ++// bit[18:16] top_ipred_type_count ++// bit[15:14] Reserved ++// bit[13:12] top_ipred_type_rd_idx ++// bit[11:10] top_ipred_type_wr_idx ++// bit[9] left_ipred_type_ready ++// bit[8] top_ipred_type_ready ++// bit[7:6] left_mv_idx ++// bit[5:4] top_mv_idx ++// bit[3] - left_mv_ready ++// bit[2:0] top_mv_ready ++#define HCODEC_V3_TOP_LEFT_CTL (0x1f6d) ++#define P_HCODEC_V3_TOP_LEFT_CTL (volatile unsigned int *)((0x1f6d << 2) + 0xff620000) ++#define HCODEC_V3_TOP_MV (0x1f6e) ++#define P_HCODEC_V3_TOP_MV (volatile unsigned int *)((0x1f6e << 2) + 0xff620000) ++#define HCODEC_V3_LEFT_MV (0x1f6f) ++#define P_HCODEC_V3_LEFT_MV (volatile unsigned int *)((0x1f6f << 2) + 0xff620000) ++// bit[31:30] reserved ++// bit[29:16] v3_skip_weight_1 ++// bit[15:12] reserved ++// bit[11:0] v3_skip_weight_0 ++#define HCODEC_V3_SKIP_WEIGHT (0x1f70) ++#define P_HCODEC_V3_SKIP_WEIGHT (volatile unsigned int *)((0x1f70 << 2) + 0xff620000) ++// bit[31:28] reserved ++// bit[27:16] v3_l1_f_skip_max_sad ++// bit[15:12] reserved ++// bit[11:0] v3_l1_skip_max_sad ++#define HCODEC_V3_L1_SKIP_MAX_SAD (0x1f71) ++#define P_HCODEC_V3_L1_SKIP_MAX_SAD (volatile unsigned int *)((0x1f71 << 2) + 0xff620000) ++// bit[31:16] force_skip_sad_2 ++// bit[15:0] v3_skip_weight_2 ++#define HCODEC_V3_L2_SKIP_WEIGHT (0x1f72) ++#define P_HCODEC_V3_L2_SKIP_WEIGHT (volatile unsigned int *)((0x1f72 << 2) + 0xff620000) ++// bit[21:16] v3_mv_sad_table_addr 0-15 table_step_0 ++// bit[11:0] v3_mv_sad ++#define HCODEC_V3_MV_SAD_TABLE (0x1f73) ++#define P_HCODEC_V3_MV_SAD_TABLE (volatile unsigned int *)((0x1f73 << 2) + 0xff620000) ++// [31:16] v3_ie_f_zero_sad_i16 ++// [15:0] v3_ie_f_zero_sad_i4 ++#define HCODEC_V3_F_ZERO_CTL_0 (0x1f74) ++#define P_HCODEC_V3_F_ZERO_CTL_0 (volatile unsigned int *)((0x1f74 << 2) + 0xff620000) ++// [25] v3_no_ver_when_top_zero_en ++// [24] v3_no_hor_when_left_zero_en ++// [23:16] v3_max_I16_H_num // 0 means no break ++// [15:0] v3_me_f_zero_sad ++#define HCODEC_V3_F_ZERO_CTL_1 (0x1f75) ++#define P_HCODEC_V3_F_ZERO_CTL_1 (volatile unsigned int *)((0x1f75 << 2) + 0xff620000) ++#define HCODEC_V3_TOP_INTRA_INFO (0x1f76) ++#define P_HCODEC_V3_TOP_INTRA_INFO (volatile unsigned int *)((0x1f76 << 2) + 0xff620000) ++#define HCODEC_V3_LEFT_INTRA_INFO (0x1f77) ++#define P_HCODEC_V3_LEFT_INTRA_INFO (volatile unsigned int *)((0x1f77 << 2) + 0xff620000) ++// [31:24] C_ipred_weight_H ++// [23:16] C_ipred_weight_V ++// [15:8] I4_ipred_weight_else ++// [7:0] I4_ipred_weight_most ++#define HCODEC_V3_IPRED_TYPE_WEIGHT_0 (0x1f78) ++#define P_HCODEC_V3_IPRED_TYPE_WEIGHT_0 (volatile unsigned int *)((0x1f78 << 2) + 0xff620000) ++// [31:24] I16_ipred_weight_DC ++// [23:16] I16_ipred_weight_H ++// [15:8] I16_ipred_weight_V ++// [7:0] C_ipred_weight_DC ++#define HCODEC_V3_IPRED_TYPE_WEIGHT_1 (0x1f79) ++#define P_HCODEC_V3_IPRED_TYPE_WEIGHT_1 (volatile unsigned int *)((0x1f79 << 2) + 0xff620000) ++// [31:16] v3_left_small_max_me_sad ++// [15:0] v3_left_small_max_ie_sad ++#define HCODEC_V3_LEFT_SMALL_MAX_SAD (0x1f7a) ++#define P_HCODEC_V3_LEFT_SMALL_MAX_SAD (volatile unsigned int *)((0x1f7a << 2) + 0xff620000) ++// (qr==7) & (qp==15) means force zero block ++// [31:26] v4_force_q_r_intra ++// [25:20] v4_force_q_r_inter ++// [19] v4_force_q_y_enable ++// [18:16] v4_force_qr_y ++// [15:12] v4_force_qp_y ++// [11:0] v4_force_skip_sad ++#define HCODEC_V4_FORCE_SKIP_CFG (0x1f7b) ++#define P_HCODEC_V4_FORCE_SKIP_CFG (volatile unsigned int *)((0x1f7b << 2) + 0xff620000) ++// v5 Complexity // Y(256 pixel per MB) and C(128 pixel per MB) ++// For every 4x4 block, calculate average and Add abs(pixel-average) together ++// bit[31:16] v5_diff_sum_C ++// bit[15:0] v5_diff_sum_Y ++#define HCODEC_V5_MB_DIFF_SUM (0x1f7c) ++#define P_HCODEC_V5_MB_DIFF_SUM (volatile unsigned int *)((0x1f7c << 2) + 0xff620000) ++// bit[31:24] v5_small_diff_cnt_C ++// bit[23:16] v5_small_diff_C ++// bit[15:8] v5_small_diff_cnt_Y ++// bit[7:0] v5_small_diff_Y ++#define HCODEC_V5_SMALL_DIFF_CNT (0x1f7d) ++#define P_HCODEC_V5_SMALL_DIFF_CNT (volatile unsigned int *)((0x1f7d << 2) + 0xff620000) ++// bit[31:29] Reserved ++// bit[28:24] v5_simple_block_cnt // 0 -15 Y 16-23 C ++// bit[23:20] v5_simple_pixel_cnt ++// bit[19:18] v5_simple_dq_wr_ptr ++// bit[17:16] v5_simple_dq_rd_ptr ++// bit[15:12] v5_simple_dq (Read Only) ++// bit[11:8] v5_simple_me_weight(Read Only) ++// bit[7] v5_use_small_diff_cnt ++// bit[6] v5_simple_mb_inter_all_en ++// bit[5] v5_simple_mb_inter_8x8_en ++// bit[4] v5_simple_mb_inter_16_8_en ++// bit[3] v5_simple_mb_inter_16x16_en ++// bit[2] v5_simple_mb_intra_en ++// bit[1] v5_simple_mb_C_en ++// bit[0] v5_simple_mb_Y_en ++#define HCODEC_V5_SIMPLE_MB_CTL (0x1f7e) ++#define P_HCODEC_V5_SIMPLE_MB_CTL (volatile unsigned int *)((0x1f7e << 2) + 0xff620000) ++// bit[31:28] v5_simple_dq_shift ++// bit[27:24] v5_simple_dq_6(-7 to +7) ++// bit[23:20] v5_simple_dq_5(-7 to +7) ++// bit[19:16] v5_simple_dq_4(-7 to +7) ++// bit[15:12] v5_simple_dq_3(-7 to +7) ++// bit[11:08] v5_simple_dq_2(-7 to +7) ++// bit[07:04] v5_simple_dq_1(-7 to +7) ++// bit[03:00] v5_simple_dq_0(-7 to +7) ++#define HCODEC_V5_SIMPLE_MB_DQUANT (0x1f7f) ++#define P_HCODEC_V5_SIMPLE_MB_DQUANT (volatile unsigned int *)((0x1f7f << 2) + 0xff620000) ++// bit[31:28] v5_simple_me_weight_shift ++// bit[27:24] v5_simple_me_weight_6(-7 to +7) ++// bit[23:20] v5_simple_me_weight_5(-7 to +7) ++// bit[19:16] v5_simple_me_weight_4(-7 to +7) ++// bit[15:12] v5_simple_me_weight_3(-7 to +7) ++// bit[11:08] v5_simple_me_weight_2(-7 to +7) ++// bit[07:04] v5_simple_me_weight_1(-7 to +7) ++// bit[03:00] v5_simple_me_weight_0(-7 to +7) ++#define HCODEC_V5_SIMPLE_MB_ME_WEIGHT (0x1f80) ++#define P_HCODEC_V5_SIMPLE_MB_ME_WEIGHT (volatile unsigned int *)((0x1f80 << 2) + 0xff620000) ++// ++// Closing file: qdct_regs.h ++// ++ ++#endif // DOS_REGISTER_H ++ ++#if 0 ++#define Wr(addr, data) *(volatile uint32_t *)(addr)=(data) ++#define Rd(addr) *(volatile uint32_t *)(addr) ++#define Wr_reg_bits(reg, val, start, len) \ ++ Wr(reg, ((Rd(reg) & ~(((1L<<(len))-1)<<(start))) | ((uint32_t)(val) << (start)))) ++#endif ++ ++// ++// Reading file: ./register_map.h ++// ++// synopsys translate_off ++// synopsys translate_on ++// ++// Reading file: stb_define.h ++// ++// synopsys translate_off ++// synopsys translate_on ++// ----------------------------------------------- ++// CBUS_BASE: STB_CBUS_BASE = 0x18 ++// ----------------------------------------------- ++// There are two instantiations under one CBUS slave. Each CBUS slave can support ++// 256 registers. Each demux is allocated 128 registers so set the offset in ++// the middle ++// Copy this define but don't add a base address ++#define SECOND_DEMUX_OFFSET_0 0x50 ++#define THIRD_DEMUX_OFFSET_0 0xa0 ++//======================================================================== ++// STB TOP Registers (8'hf0 - 8'hf7) ++//======================================================================== ++// bit 30:28 -- ciplus_o_sel ++// bit 27:26 -- ciplus_i_sel ++// bit 25 -- use FAIL fro TS2 ++// bit 24 -- use FAIL fro TS1 ++// bit 23 -- use FAIL fro TS0 ++// bit 22 -- invert fec_error for S2P1 ++// bit 21 -- invert fec_data for S2P1 ++// bit 20 -- invert fec_sync for S2P1 ++// bit 19 -- invert fec_valid for S2P1 ++// bit 18 -- invert fec_clk for S2P1 ++// bit 17:16 -- fec_s_sel for S2P1 00 - select TS0, 01 -- select TS1, 10 -- select TS2, 11 - reserved ++// Bit 15 -- enable_des_pl_clk ++// Bit 14:13 -- reserved ++// Bit 12:10 -- ts_out_select, 0-TS0, 1-TS1, 2-TS2, 3,4-Reserved, 5-S2P1, 6-S2P0, 7-File ++// bit 9:8 -- des_i_sel 00 -- select_fec_0, 01 -- select_fec_1, 10 -- select_fec_2, 11 - reserved ++// bit 7 -- enable_des_pl ++// bit 6 -- invert fec_error for S2P0 ++// bit 5 -- invert fec_data for S2P0 ++// bit 4 -- invert fec_sync for S2P0 ++// bit 3 -- invert fec_valid for S2P0 ++// bit 2 -- invert fec_clk for S2P0 ++// bit 1:0 -- fec_s_sel for S2P0 00 - select TS0, 01 -- select TS1, 10 -- select TS2, 11 - reserved ++#define STB_TOP_CONFIG (0x18f0) ++#define P_STB_TOP_CONFIG (volatile unsigned int *)((0x18f0 << 2) + 0xffd00000) ++// 31:28 - s2p1_clk_div ++// 27:24 - s2p0_clk_div ++// 23 - s2p1_disable ++// 22 - s2p0_disable ++// 21 - Reserved ++// 20 -- TS_OUT_error_INVERT ++// 19 -- TS_OUT_data_INVERT ++// 18 -- TS_OUT_sync_INVERT ++// 17 -- TS_OUT_valid_INVERT ++// 16 -- TS_OUT_clk_INVERT ++// 15:8 -- TS_package_length_sub_1 (default : 187) ++// 7:0 -- fec_sync_byte (default : 0x47) ++#define TS_TOP_CONFIG (0x18f1) ++#define P_TS_TOP_CONFIG (volatile unsigned int *)((0x18f1 << 2) + 0xffd00000) ++// Bit 25:24 -- transport_scrambling_control_odd_2 // should be 3 ++// Bit 23:16 -- file_m2ts_skip_bytes ++// Bit 15:8 -- des_out_dly ++// Bit 7:6 -- transport_scrambling_control_odd // should be 3 ++// Bit 5 -- ts_hiu_enable ++// Bit 4:0 -- fec_clk_div ++#define TS_FILE_CONFIG (0x18f2) ++#define P_TS_FILE_CONFIG (volatile unsigned int *)((0x18f2 << 2) + 0xffd00000) ++// Bit 19:14 -- des_2 ts pl state -- Read Only ++// Bit 13:8 -- des ts pl state -- Read Only ++// Bit 3:0 PID index to 8 PID to get key-set ++// auto increse after TS_PL_PID_DATA read/write ++#define TS_PL_PID_INDEX (0x18f3) ++#define P_TS_PL_PID_INDEX (volatile unsigned int *)((0x18f3 << 2) + 0xffd00000) ++// Bit 13 -- PID match disble ++// Bit 12:0 -- PID ++#define TS_PL_PID_DATA (0x18f4) ++#define P_TS_PL_PID_DATA (volatile unsigned int *)((0x18f4 << 2) + 0xffd00000) ++#define COMM_DESC_KEY0 (0x18f5) ++#define P_COMM_DESC_KEY0 (volatile unsigned int *)((0x18f5 << 2) + 0xffd00000) ++#define COMM_DESC_KEY1 (0x18f6) ++#define P_COMM_DESC_KEY1 (volatile unsigned int *)((0x18f6 << 2) + 0xffd00000) ++#define COMM_DESC_KEY_RW (0x18f7) ++#define P_COMM_DESC_KEY_RW (volatile unsigned int *)((0x18f7 << 2) + 0xffd00000) ++// CI+ Register defines ++// Bits[31:0] of the key ++#define CIPLUS_KEY0 (0x18f8) ++#define P_CIPLUS_KEY0 (volatile unsigned int *)((0x18f8 << 2) + 0xffd00000) ++// Bits[63:32] of the key ++#define CIPLUS_KEY1 (0x18f9) ++#define P_CIPLUS_KEY1 (volatile unsigned int *)((0x18f9 << 2) + 0xffd00000) ++// Bits[95:64] of the key ++#define CIPLUS_KEY2 (0x18fa) ++#define P_CIPLUS_KEY2 (volatile unsigned int *)((0x18fa << 2) + 0xffd00000) ++// Bits[127:96] of the key ++#define CIPLUS_KEY3 (0x18fb) ++#define P_CIPLUS_KEY3 (volatile unsigned int *)((0x18fb << 2) + 0xffd00000) ++// bit[5] write AES IV B value ++// bit[4] write AES IV A value ++// bit[3] write AES B key ++// bit[2] write AES A key ++// bit[1] write DES B key ++// bit[0] write DES A key ++#define CIPLUS_KEY_WR (0x18fc) ++#define P_CIPLUS_KEY_WR (volatile unsigned int *)((0x18fc << 2) + 0xffd00000) ++// [15:8] TS out delay. This controls the rate at which the CIplus module drives TS out ++// [3] General enable for the ciplus module ++// [2] AES CBC disable (default should be 0 to enable AES CBC) ++// [1] AES Enable ++// [0] DES Eanble ++#define CIPLUS_CONFIG (0x18fd) ++#define P_CIPLUS_CONFIG (volatile unsigned int *)((0x18fd << 2) + 0xffd00000) ++// bit[31:28] AES IV endian ++// bit[27:24] AES message out endian ++// bit[23:20] AES message in endian ++// bit[19:16] AES key endian ++// bit[15:11] unused ++// bit[10:8] DES message out endian ++// bit[6:4] DES message in endian ++// bit[2:0] DES key endian ++#define CIPLUS_ENDIAN (0x18fe) ++#define P_CIPLUS_ENDIAN (volatile unsigned int *)((0x18fe << 2) + 0xffd00000) ++// bit 15:8 - des_out_dly_2 ++// bit 7 - reserved ++// Bit 6-- enable_des_pl_clk_2 ++// bit 5 - enable_des_pl_2 ++// bit 4:2 -- use_des_2 bit[2] -- demux0, bit[3] -- demux1, bit[4] -- demux2 ++// bit 1:0 -- des_i_sel_2 00 -- select_fec_0, 01 -- select_fec_1, 10 -- select_fec_2, 11 - reserved ++#define COMM_DESC_2_CTL (0x18ff) ++#define P_COMM_DESC_2_CTL (volatile unsigned int *)((0x18ff << 2) + 0xffd00000) ++// ++// NOTE: Don't process the demux registers using the standard create_headers.... perl script. ++// Instead, since the demux has multiple instances (and many registers) use a separate ++// script to create a separate stb_define.h for C-code. ++//======================================================================== ++// STB Registers (8'h00 - 8'h4f) ++// ++//======================================================================== ++// STB registers are 8'h0x ++// Bit 15:0 -- version number : 0x0002 (v0.01) ++// Bit 15 -- fec_core_select 1 - select descramble output ++// Bit 14:12 - fec_select 0-TS0, 1-TS1, 2-TS2, 3,4-Reserved, 5-S2P1, 6-S2P0, 7-File ++// Bit 11 -- FEC_CLK ++// Bit 10 -- SOP ++// Bit 9 -- D_VALID ++// Bit 8 -- D_FAIL ++// Bit 7:0 -- D_DATA 7:0 ++// bit 31 -- enable_free_clk_fec_data_valid ++// bit 30 -- enable_free_clk_stb_reg ++// bit 29 -- always_use_pes_package_length ++// bit 28 -- disable_pre_incomplete_section_fix ++// bit 27 -- pointer_field_multi_pre_en ++// bit 26 -- ignore_pre_incomplete_section ++// bit 25 -- video2_enable ++// bit 24:22 -- video2_type ++// bit 21 -- do_not_trust_pes_package_length ++// bit 20 (bit 4) -- Bypass use recoder path ++// bit 19 (bit 3) -- clear_PID_continuity_counter_valid ++// bit 18 (bit 2) -- Disable Splicing ++// bit 17 (bit 1) -- Insert PES_STRONG_SYNC in Audio PES ++// bit 16 (bit 0) -- Insert PES_STRONG_SYNC in Video PES ++// Bit 15 - do not trust section length ++// Bit 14 - om cmd push even zero ++// Bit 13 - set_buff_ready_even_not_busy ++// Bit 12 - SUB, OTHER PES interrupt at beginning of PES ++// Bit 11 - discard_av_package -- for ts_recorder use only ++// Bit 10 - ts_recorder_select 0:after PID filter 1:before PID filter ++// Bit 9 - ts_recorder_enable ++// Bit 8 - (table_id == 0xff) means section_end ++// Bit 7 - do not send uncomplete section ++// Bit 6 - do not discard duplicate package ++// Bit 5 - search SOP when trasport_error_indicator ++// Bit 4 - stb demux enable ++// Bit 3 - do not reset state machine on SOP ++// Bit 2 - search SOP when error happened ( when ignore_fail_n_sop, will have this case) ++// Bit 1 - do not use SOP input ( check FEC sync byte instead ) ++// Bit 0 - ignore fec_error bit when non sop ( check error on SOP only) ++// bit 15:8 demux package length - 1 ( default : 187 ) ++// bit 7:0 default is 0x47 ++// bit 31:16 -- filter memory write data hi[31:16] ++// bit 15:0 -- filter memory write data low [15:0] ++// bit 31:24 -- advanced setting hi ++// bit 23:16 -- advanced setting low ++// bit 15 -- filter memory write data request ++// bit 7:0 -- filter memory write addr ++// bit 13:8 demux state -- read only ++// bit 7:4 -- maxnum section filter compare address ++// bit 3:0 -- maxnum PID filter compare address ++// bit 15 - transport_error_indicator ++// bit 14 - payload_unit_start_indicator ++// bit 13 - transport_priority ++// bit 12:0 - PID ++// bit 7:6 transport_scrambling_control ++// bit 5:4 adaptation_field_control ++// bit 3:0 continuity_counter ++// bit 15:12 -- om_cmd_count (read only) ++// bit 11:9 -- overflow_count // bit 11:9 -- om_cmd_wr_ptr (read only) ++// bit 8:6 -- om_overwrite_count // bit 8:6 -- om_cmd_rd_ptr (read only) ++// bit 5:3 -- type_stb_om_w_rd (read only) ++// bit 2 -- unit_start_stb_om_w_rd (read only) ++// bit 1 -- om_cmd_overflow (read only) ++// bit 0 -- om_cmd_pending (read) ++// bit 0 -- om_cmd_read_finished (write) ++// bit 15:9 // bit 14:8 -- count_stb_om_w_rd (read only) ++// bit 8:0 // bit 7:0 -- start_stb_om_wa_rd (read only) ++// bit 11:0 -- offset for section data ++// bit 31:16 -- base address for section buffer group 0 (*0x400 to get real address) ++// bit 15:0 -- base address for section buffer group 1 (*0x400 to get real address) ++// bit 31:16 -- ba2e address for section buffer group 2 (*0x400 to get real address) ++// bit 15:0 -- base address for section buffer group 3 (*0x400 to get real address) ++// bit 3:0 -- section buffer size for group 0 (bit used, for example, 10 means 1K) ++// bit 7:4 -- section buffer size for group 1 ++// bit 11:8 -- section buffer size for group 2 ++// bit 15:12 -- section buffer size for group 3 ++// section buffer busy status for buff 31:0 ( Read Only ) ++// section buffer write status for buff 31:0 -- Read ++// clear buffer status ( buff READY and BUSY ) -- write ++// bit 4:0 -- SEC_BUFFER_INDEX RW ++// bit 12:8 -- SEC_BUFFER_NUMBER for the INDEX buffer Read_Only ++// bit 14 -- output_section_buffer_valid ++// bit 15 -- section_reset_busy (Read Only) ++// bit 9:5 -- BYPASS PID number ++// bit 4:0 -- PCR PID number ++// bit 15:0 -- stream_id filter bit enable ++// bit 7:0 -- stream_id filter target ++// bit 12 -- PCR_EN ++// bit 11:0 -- PCR90K_DIV ++// bit 31:0 -- PCR[31:0] R/W ++// bit 31:0 -- VPTS[31:0] R/W ++// bit 31:0 -- VDTS[31:0] R/W ++// bit 31:0 -- APTS[31:0] R/W ++// bit 31:0 -- SPTS[31:0] R/W ++// read -- status, write 1 clear status ++// bit 15 -- SUB_PTS[32] ++// bit 14 -- AUDIO_PTS[32] ++// bit 13 -- VIDEO_DTS[32] ++// bit 12 -- VIDEO_PTS[32] ++// bit 3 -- sub_pts_ready ++// bit 2 -- audio_pts_ready ++// bit 1 -- video_dts_ready ++// bit 0 -- video_pts_ready ++// bit 3:0 -- ++// 0 -- adaptation_field_length[7:0], adaption_field_byte_1[7:0] ++// 1 -- stream_id[7:0], pes_header_bytes_left[7:0] ++// 2 -- pes_package_bytes_left[15:0] ++// 3 -- pes_ctr_byte[7:0], pes_flag_byte[7:0] ++// ++// read only ++// bit[31] -- no_match_record_en ++// bit[30:16] - reserved ++// default : 0x807f ++// bit 15:9 -- MAX OM DMA COUNT (default: 0x40) ++// bit 8:0 -- LAST ADDR OF OM ADDR (default: 127) ++// 15:0 WRITE 1 CLEAR to clear interrupt source ++//12 -- INPUT_TIME_OUT ++//11 -- PCR_ready ++//10 -- audio_splicing_point ++// 9 -- video_splicing_point ++// 8 -- other_PES_int ++// 7 -- sub_PES_int ++// 6 -- discontinuity ++// 5 -- duplicated_pack_found ++// 4 -- New PDTS ready ++// 3 -- om_cmd_buffer ready for access ++// 2 -- section buffer ready ++// 1 -- transport_error_indicator ++// 0 -- TS ERROR PIN ++// Bit 5:3 - demux om write endian control for bypass ++// Bit 2:0 - demux om write endian control for section ++// When Bit 31 - 1 write will indicate all type use sepertate endian (Write Only) ++// Bit 23:21 - demux om write endian control for OTHER_PES_PACKET ++// Bit 20:18 - demux om write endian control for SCR_ONLY_PACKET ++// Bit 17:15 - demux om write endian control for SUB_PACKET ++// Bit 14:12 - demux om write endian control for AUDIO_PACKET ++// Bit 11:9 - demux om write endian control for VIDEO_PACKET ++// ++// When Bit 31 - 0 write will indicate all type else use Bit 8:6 ++// Bit 8:6 - demux om write endian control for else ++// Bit 15:8 -- last_burst_threshold ++// Bit 7 -- use hi_bsf interface ++// Bit 6:2 - fec_clk_div ++// Bit 1 ts_source_sel ++// Bit 0 - Hiu TS generate enable ++// bit 15:0 -- base address for section buffer start (*0x10000 to get real base) ++// bit 11 -- mask bit for OTHER_PES_AHB_DMA_EN ++// bit 10 -- mask bit for SUB_AHB_DMA_EN ++// bit 9 -- mask bit for BYPASS_AHB_DMA_EN ++// bit 8 -- mask bit for SECTION_AHB_DMA_EN ++// bit 7 -- mask bit for recoder stream ++// bit 6:0 -- mask bit for each type ++// bit 31:0 -- vb_wr_ptr for video PDTS ++// bit 31:0 -- ab_wr_ptr for audio PDTS ++// bit 20:0 -- SB_WRITE_PTR (sb_wr_ptr << 3 == byte write position) ++// bit 19:0 -- SB_START (sb_start << 12 == byte address); ++// bit 20:0 -- SB_SIZE (sb_size << 3 == byte size, 16M maximun) ++// bit 31:0 -- sb_wr_ptr for sub PES ++// bit 31:16 -- ob_wr_ptr for other PES ++// bit 20:0 -- OB_WRITE_PTR (ob_wr_ptr << 3 == byte write position) ++// bit 19:0 -- OB_START (ob_start << 12 == byte address); ++// bit 20:0 -- OB_SIZE (ob_size << 3 == byte size, 16M maximun) ++// bit 31:0 -- ob_wr_ptr for sub PES ++// 15:0 DEMUX interrupt MASK ++// 9 -- splicing_point ++// 8 -- other_PES_int ++// 7 -- sub_PES_int ++// 6 -- discontinuity ++// 5 -- duplicated_pack_found ++// 4 -- New PDTS ready ++// 3 -- om_cmd_buffer ready for access ++// 2 -- section buffer ready ++// 1 -- transport_error_indicator ++// 0 -- TS ERROR PIN ++// 31:16 VIDEO PID filter data ++//15 -- splicing VIDEO PID change enable ++//14:10 -- VIDEO PID FILTER ADDRESS ++// 9 -- PES splicing active (Read Only) ++// 8 -- splicing active (Read Only) ++// 7:0 splicing countdown (Read Only) ++// 31:16 AUDIO PID filter data ++//15 -- splicing AUDIO PID change enable ++//14:10 -- AUDIO PID FILTER ADDRESS ++// 9 -- PES splicing active (Read Only) ++// 8 -- splicing active (Read Only) ++// 7:0 splicing countdown (Read Only) ++// 23:16 M2TS_SKIP_BYTES ++// 15:8 LAST TS PACKAGE BYTE COUNT (Read Only) ++// 7:0 PACKAGE BYTE COUNT (Read Only) ++// 15:0 2 bytes strong sync add to PES ++// bit 15 -- stb_om_ren ++// bit 14:11 -- reserved ++// bit 10:0 -- OM_DATA_RD_ADDR ++// bit 15:0 -- OM_DATA_RD ++// AUTO STOP SETTING for 32 channels ++// 4-nbits per channel ++// when write ++// bit 3 -- set section active ++// bit 2:0 -- auto stop after count (0 means never stop) ++// when read ++// bit 3 -- current active status (1 - active, 0 - stopped ) ++// bit 2:0 -- count down to auto stop ++// section 31:24 ++// section 23:16 ++// section 15:8 ++// section 7:0 ++// bit 31:0 reset channel status - each bit reset each channel ++// read -- 32 channel status ++// bit 4 -- video_stamp_use_dts ++// bit 3 -- audio_stamp_sync_1_en ++// bit 2 -- audio_stamp_insert_en ++// bit 1 -- video_stamp_sync_1_en ++// bit 0 -- video_stamp_insert_en ++// Write : Bit[4:0] secter filter number for reset ++// Read : select according to output_section_buffer_valid : ++// per bit per section buffer valid status ++// or section_buffer_ignore ++// bit[31:0] - channel_reset_timeout_disable ++// bit[31] - no_match_reset_timeout_disable ++// bit[30:0] input_time_out_int_cnt (0 -- means disable) Wr-setting, Rd-count ++// bit[31:0] - channel_packet_count_disable ++// bit[31] - no_match_packet_count_disable ++// bit[30:0] input_packet_count ++// bit[31:0] channel_record_enable ++// bit[31:0] channel_process_enable ++// bit[31:24] small_sec_size ((n+1) * 256 Bytes) ++// bit[23:16] small_sec_rd_ptr ++// bit[15:8] small_sec_wr_ptr ++// bit[7:2] reserved ++// bit[1] small_sec_wr_ptr_wr_enable ++// bit[0] small_section_enable ++// bit[31:0] small_sec_start_addr ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: stb_define.h ++// ++// ++// Reading file: periphs_reg.h ++// ++// $periphs/rtl/periphs_core register defines for the ++// APB bus ++// ------------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: SC_CBUS_BASE = 0x94 ++// ----------------------------------------------- ++#define SMARTCARD_REG0 (0x9400) ++#define P_SMARTCARD_REG0 (volatile unsigned int *)((0x9400 << 2) + 0xffd00000) ++#define SMARTCARD_REG1 (0x9401) ++#define P_SMARTCARD_REG1 (volatile unsigned int *)((0x9401 << 2) + 0xffd00000) ++#define SMARTCARD_REG2 (0x9402) ++#define P_SMARTCARD_REG2 (volatile unsigned int *)((0x9402 << 2) + 0xffd00000) ++#define SMARTCARD_STATUS (0x9403) ++#define P_SMARTCARD_STATUS (volatile unsigned int *)((0x9403 << 2) + 0xffd00000) ++#define SMARTCARD_INTR (0x9404) ++#define P_SMARTCARD_INTR (volatile unsigned int *)((0x9404 << 2) + 0xffd00000) ++#define SMARTCARD_REG5 (0x9405) ++#define P_SMARTCARD_REG5 (volatile unsigned int *)((0x9405 << 2) + 0xffd00000) ++#define SMARTCARD_REG6 (0x9406) ++#define P_SMARTCARD_REG6 (volatile unsigned int *)((0x9406 << 2) + 0xffd00000) ++#define SMARTCARD_FIFO (0x9407) ++#define P_SMARTCARD_FIFO (volatile unsigned int *)((0x9407 << 2) + 0xffd00000) ++#define SMARTCARD_REG8 (0x9408) ++#define P_SMARTCARD_REG8 (volatile unsigned int *)((0x9408 << 2) + 0xffd00000) ++// ------------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: UART0_CBUS_BASE = 0x90 ++// ----------------------------------------------- ++#define UART0_WFIFO (0x9000) ++#define P_UART0_WFIFO (volatile unsigned int *)((0x9000 << 2) + 0xffd00000) ++#define UART0_RFIFO (0x9001) ++#define P_UART0_RFIFO (volatile unsigned int *)((0x9001 << 2) + 0xffd00000) ++#define UART0_CONTROL (0x9002) ++#define P_UART0_CONTROL (volatile unsigned int *)((0x9002 << 2) + 0xffd00000) ++#define UART0_STATUS (0x9003) ++#define P_UART0_STATUS (volatile unsigned int *)((0x9003 << 2) + 0xffd00000) ++#define UART0_MISC (0x9004) ++#define P_UART0_MISC (volatile unsigned int *)((0x9004 << 2) + 0xffd00000) ++#define UART0_REG5 (0x9005) ++#define P_UART0_REG5 (volatile unsigned int *)((0x9005 << 2) + 0xffd00000) ++// ------------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: UART1_CBUS_BASE = 0x8c ++// ----------------------------------------------- ++#define UART1_WFIFO (0x8c00) ++#define P_UART1_WFIFO (volatile unsigned int *)((0x8c00 << 2) + 0xffd00000) ++#define UART1_RFIFO (0x8c01) ++#define P_UART1_RFIFO (volatile unsigned int *)((0x8c01 << 2) + 0xffd00000) ++#define UART1_CONTROL (0x8c02) ++#define P_UART1_CONTROL (volatile unsigned int *)((0x8c02 << 2) + 0xffd00000) ++#define UART1_STATUS (0x8c03) ++#define P_UART1_STATUS (volatile unsigned int *)((0x8c03 << 2) + 0xffd00000) ++#define UART1_MISC (0x8c04) ++#define P_UART1_MISC (volatile unsigned int *)((0x8c04 << 2) + 0xffd00000) ++#define UART1_REG5 (0x8c05) ++#define P_UART1_REG5 (volatile unsigned int *)((0x8c05 << 2) + 0xffd00000) ++// ------------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: UART2_CBUS_BASE = 0x88 ++// ----------------------------------------------- ++#define UART2_WFIFO (0x8800) ++#define P_UART2_WFIFO (volatile unsigned int *)((0x8800 << 2) + 0xffd00000) ++#define UART2_RFIFO (0x8801) ++#define P_UART2_RFIFO (volatile unsigned int *)((0x8801 << 2) + 0xffd00000) ++#define UART2_CONTROL (0x8802) ++#define P_UART2_CONTROL (volatile unsigned int *)((0x8802 << 2) + 0xffd00000) ++#define UART2_STATUS (0x8803) ++#define P_UART2_STATUS (volatile unsigned int *)((0x8803 << 2) + 0xffd00000) ++#define UART2_MISC (0x8804) ++#define P_UART2_MISC (volatile unsigned int *)((0x8804 << 2) + 0xffd00000) ++#define UART2_REG5 (0x8805) ++#define P_UART2_REG5 (volatile unsigned int *)((0x8805 << 2) + 0xffd00000) ++// ------------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: UART3_CBUS_BASE = 0x84 ++// ----------------------------------------------- ++#define UART3_DF_REG_A73 (0x8400) ++#define P_UART3_DF_REG_A73 (volatile unsigned int *)((0x8400 << 2) + 0xffd00000) ++#define UART3_DF_REG_A74 (0x8401) ++#define P_UART3_DF_REG_A74 (volatile unsigned int *)((0x8401 << 2) + 0xffd00000) ++#define UART3_DF_REG_A75 (0x8402) ++#define P_UART3_DF_REG_A75 (volatile unsigned int *)((0x8402 << 2) + 0xffd00000) ++#define UART3_DF_REG_A76 (0x8403) ++#define P_UART3_DF_REG_A76 (volatile unsigned int *)((0x8403 << 2) + 0xffd00000) ++#define UART3_DF_REG_A77 (0x8404) ++#define P_UART3_DF_REG_A77 (volatile unsigned int *)((0x8404 << 2) + 0xffd00000) ++#define UART3_DF_REG_A78 (0x8405) ++#define P_UART3_DF_REG_A78 (volatile unsigned int *)((0x8405 << 2) + 0xffd00000) ++#define UART3_DF_REG_A79 (0x8406) ++#define P_UART3_DF_REG_A79 (volatile unsigned int *)((0x8406 << 2) + 0xffd00000) ++#define UART3_DF_REG_A80 (0x8407) ++#define P_UART3_DF_REG_A80 (volatile unsigned int *)((0x8407 << 2) + 0xffd00000) ++#define UART3_DF_REG_A81 (0x8408) ++#define P_UART3_DF_REG_A81 (volatile unsigned int *)((0x8408 << 2) + 0xffd00000) ++#define UART3_DF_REG_A82 (0x8409) ++#define P_UART3_DF_REG_A82 (volatile unsigned int *)((0x8409 << 2) + 0xffd00000) ++#define UART3_DF_REG_A83 (0x8410) ++#define P_UART3_DF_REG_A83 (volatile unsigned int *)((0x8410 << 2) + 0xffd00000) ++#define UART3_DF_REG_A84 (0x8411) ++#define P_UART3_DF_REG_A84 (volatile unsigned int *)((0x8411 << 2) + 0xffd00000) ++#define UART3_DF_REG_A85 (0x8412) ++#define P_UART3_DF_REG_A85 (volatile unsigned int *)((0x8412 << 2) + 0xffd00000) ++#define UART3_DF_REG_A86 (0x8413) ++#define P_UART3_DF_REG_A86 (volatile unsigned int *)((0x8413 << 2) + 0xffd00000) ++#define UART3_DF_REG_A87 (0x8414) ++#define P_UART3_DF_REG_A87 (volatile unsigned int *)((0x8414 << 2) + 0xffd00000) ++#define UART3_DF_REG_A88 (0x8415) ++#define P_UART3_DF_REG_A88 (volatile unsigned int *)((0x8415 << 2) + 0xffd00000) ++#define UART3_DF_REG_A89 (0x8416) ++#define P_UART3_DF_REG_A89 (volatile unsigned int *)((0x8416 << 2) + 0xffd00000) ++#define UART3_DF_REG_A96 (0x8417) ++#define P_UART3_DF_REG_A96 (volatile unsigned int *)((0x8417 << 2) + 0xffd00000) ++#define UART3_DF_REG_A97 (0x8418) ++#define P_UART3_DF_REG_A97 (volatile unsigned int *)((0x8418 << 2) + 0xffd00000) ++#define UART3_DF_REG_A128 (0x8420) ++#define P_UART3_DF_REG_A128 (volatile unsigned int *)((0x8420 << 2) + 0xffd00000) ++#define UART3_DF_REG_A129 (0x8421) ++#define P_UART3_DF_REG_A129 (volatile unsigned int *)((0x8421 << 2) + 0xffd00000) ++#define UART3_DF_REG_A130 (0x8422) ++#define P_UART3_DF_REG_A130 (volatile unsigned int *)((0x8422 << 2) + 0xffd00000) ++#define UART3_DF_REG_A131 (0x8423) ++#define P_UART3_DF_REG_A131 (volatile unsigned int *)((0x8423 << 2) + 0xffd00000) ++#define UART3_DF_REG_A132 (0x8424) ++#define P_UART3_DF_REG_A132 (volatile unsigned int *)((0x8424 << 2) + 0xffd00000) ++#define UART3_DF_REG_A133 (0x8425) ++#define P_UART3_DF_REG_A133 (volatile unsigned int *)((0x8425 << 2) + 0xffd00000) ++#define UART3_DF_REG_A134 (0x8426) ++#define P_UART3_DF_REG_A134 (volatile unsigned int *)((0x8426 << 2) + 0xffd00000) ++#define UART3_DF_REG_A135 (0x8427) ++#define P_UART3_DF_REG_A135 (volatile unsigned int *)((0x8427 << 2) + 0xffd00000) ++#define UART3_DF_REG_A136 (0x8428) ++#define P_UART3_DF_REG_A136 (volatile unsigned int *)((0x8428 << 2) + 0xffd00000) ++// ---------------------------- ++// SANA (Stream Analyzer) ++// ---------------------------- ++// ------------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: SANA_CBUS_BASE = 0x30 ++// ----------------------------------------------- ++// [31:16] - ddr_setting ++// [15] - disable_stream_clock_gating ++// [14:13] - mem_pd_ctl_sana ++// [6:4] - stream_fetch_endian ++// [3] - use_parser_vbuf_wp ++// [2] - use_parser_vbuf2_wp ++// [1] - stream_fetch_busy - Read Only ++// [0] - stream_fetch_enable ++#define SANA_STREAM_CONTROL (0x3020) ++#define P_SANA_STREAM_CONTROL (volatile unsigned int *)((0x3020 << 2) + 0xffd00000) ++#define SANA_STREAM_START_ADDR (0x3021) ++#define P_SANA_STREAM_START_ADDR (volatile unsigned int *)((0x3021 << 2) + 0xffd00000) ++#define SANA_STREAM_END_ADDR (0x3022) ++#define P_SANA_STREAM_END_ADDR (volatile unsigned int *)((0x3022 << 2) + 0xffd00000) ++// SW stream_buffer_wr_ptr ++#define SANA_STREAM_WR_PTR (0x3023) ++#define P_SANA_STREAM_WR_PTR (volatile unsigned int *)((0x3023 << 2) + 0xffd00000) ++#define SANA_STREAM_RD_PTR (0x3024) ++#define P_SANA_STREAM_RD_PTR (volatile unsigned int *)((0x3024 << 2) + 0xffd00000) ++//[31:0] stream_buffer_level - read only ++#define SANA_STREAM_LEVEL (0x3025) ++#define P_SANA_STREAM_LEVEL (volatile unsigned int *)((0x3025 << 2) + 0xffd00000) ++// [31:29] stream_buffer_hole 256*(4^0) bytes ++// [28:23] stream_fifo_hole ++// [22:16] stream_fifo_level ++// [15] stream_fifo_wr_ptr_update_en ++// [14:8] stream_fifo_wr_ptr ++// [7] stream_fifo_rd_ptr_update_en ++// [6:0] stream_fifo_rd_ptr ++#define SANA_STREAM_FIFO_CTL (0x3026) ++#define P_SANA_STREAM_FIFO_CTL (volatile unsigned int *)((0x3026 << 2) + 0xffd00000) ++// [31:18] - Reserved ++// [17] - sana_int_enable ++// [16] - sana_int_level (default : 0(pulse)) ++// [15] - disable_shift_clock_gating ++// [14] - startcode_protect -- TODO ++// [8:6] - sft_valid_wr_position (default : 3 (at least 24 bits available)) ++// [5:4] - emulate_code_length_sub_1(Default : 2) ++// [3] - emulation_auto_on_startcode(Default : 0) ++// [2:1] - start_code_length_sub_1(Default : 2) ++// [0] - stream_shift_enable(Default : 0) ++#define SANA_SHIFT_CONTROL (0x3027) ++#define P_SANA_SHIFT_CONTROL (volatile unsigned int *)((0x3027 << 2) + 0xffd00000) ++// [31:0] - max 4-bytes start code (Default : 0x00000100) ++#define SANA_SHIFT_STARTCODE (0x3028) ++#define P_SANA_SHIFT_STARTCODE (volatile unsigned int *)((0x3028 << 2) + 0xffd00000) ++// [31:0] - max 4-bytes emulate code (Default : 0x00000300) ++#define SANA_SHIFT_EMULATECODE (0x3029) ++#define P_SANA_SHIFT_EMULATECODE (volatile unsigned int *)((0x3029 << 2) + 0xffd00000) ++// [3] - sana_int ++// [2] - startcode_searching ++// [1] - emulation_check_on ++// [0] - startcode_check_on ++#define SANA_SHIFT_STATUS (0x302a) ++#define P_SANA_SHIFT_STATUS (volatile unsigned int *)((0x302a << 2) + 0xffd00000) ++// [31:0] sana_shifted_data - read only ++#define SANA_SHIFTED_DATA (0x302b) ++#define P_SANA_SHIFTED_DATA (volatile unsigned int *)((0x302b << 2) + 0xffd00000) ++// [31:0] shift_byte_count[31:0] ++#define SANA_SHIFT_BYTE_COUNT (0x302c) ++#define P_SANA_SHIFT_BYTE_COUNT (volatile unsigned int *)((0x302c << 2) + 0xffd00000) ++// [31:28] - shift_byte_count[35:32] ++// [27:20] - element_read_data[31:24] ++// [10] - bytealign ++// [9] - signed_element ++// [8] - start_element_read ++// [7] - shift_busy ++// [6:0] - shift_bits ++#define SANA_SHIFT_COMMAND (0x302d) ++#define P_SANA_SHIFT_COMMAND (volatile unsigned int *)((0x302d << 2) + 0xffd00000) ++// 31:8 - element_read_data[23:0] ++// 7:2 - element_read_length ++// 1:0 - element_read_state ++#define SANA_ELEMENT_RESULT (0x302e) ++#define P_SANA_ELEMENT_RESULT (volatile unsigned int *)((0x302e << 2) + 0xffd00000) ++// support up to 8 masters, one bit per master ++// 23:16 - lock_release (Write 1 to release) ++// 15:8 - lock_req (write 1 to request) ++// 7:0 - lock_result (Read Only) ++#define ATOM_LOCK (0x302f) ++#define P_ATOM_LOCK (volatile unsigned int *)((0x302f << 2) + 0xffd00000) ++// ------------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: I2C_M_0_CBUS_BASE = 0x7c ++// ----------------------------------------------- ++#define I2C_M_0_CONTROL_REG (0x7c00) ++#define P_I2C_M_0_CONTROL_REG (volatile unsigned int *)((0x7c00 << 2) + 0xffd00000) ++ #define I2C_M_MANUAL_SDA_I 26 ++ #define I2C_M_MANUAL_SCL_I 25 ++ #define I2C_M_MANUAL_SDA_O 24 ++ #define I2C_M_MANUAL_SCL_O 23 ++ #define I2C_M_MANUAL_EN 22 ++ #define I2C_M_DELAY_MSB 21 ++ #define I2C_M_DELAY_LSB 12 ++ #define I2C_M_DATA_CNT_MSB 11 ++ #define I2C_M_DATA_CNT_LSB 8 ++ #define I2C_M_CURR_TOKEN_MSB 7 ++ #define I2C_M_CURR_TOKEN_LSB 4 ++ #define I2C_M_ERROR 3 ++ #define I2C_M_STATUS 2 ++ #define I2C_M_ACK_IGNORE 1 ++ #define I2C_M_START 0 ++#define I2C_M_0_SLAVE_ADDR (0x7c01) ++#define P_I2C_M_0_SLAVE_ADDR (volatile unsigned int *)((0x7c01 << 2) + 0xffd00000) ++#define I2C_M_0_TOKEN_LIST0 (0x7c02) ++#define P_I2C_M_0_TOKEN_LIST0 (volatile unsigned int *)((0x7c02 << 2) + 0xffd00000) ++#define I2C_M_0_TOKEN_LIST1 (0x7c03) ++#define P_I2C_M_0_TOKEN_LIST1 (volatile unsigned int *)((0x7c03 << 2) + 0xffd00000) ++#define I2C_M_0_WDATA_REG0 (0x7c04) ++#define P_I2C_M_0_WDATA_REG0 (volatile unsigned int *)((0x7c04 << 2) + 0xffd00000) ++#define I2C_M_0_WDATA_REG1 (0x7c05) ++#define P_I2C_M_0_WDATA_REG1 (volatile unsigned int *)((0x7c05 << 2) + 0xffd00000) ++#define I2C_M_0_RDATA_REG0 (0x7c06) ++#define P_I2C_M_0_RDATA_REG0 (volatile unsigned int *)((0x7c06 << 2) + 0xffd00000) ++#define I2C_M_0_RDATA_REG1 (0x7c07) ++#define P_I2C_M_0_RDATA_REG1 (volatile unsigned int *)((0x7c07 << 2) + 0xffd00000) ++// ----------------------------------------------- ++// CBUS_BASE: I2C_M_1_CBUS_BASE = 0x78 ++// ----------------------------------------------- ++#define I2C_M_1_CONTROL_REG (0x7800) ++#define P_I2C_M_1_CONTROL_REG (volatile unsigned int *)((0x7800 << 2) + 0xffd00000) ++#define I2C_M_1_SLAVE_ADDR (0x7801) ++#define P_I2C_M_1_SLAVE_ADDR (volatile unsigned int *)((0x7801 << 2) + 0xffd00000) ++#define I2C_M_1_TOKEN_LIST0 (0x7802) ++#define P_I2C_M_1_TOKEN_LIST0 (volatile unsigned int *)((0x7802 << 2) + 0xffd00000) ++#define I2C_M_1_TOKEN_LIST1 (0x7803) ++#define P_I2C_M_1_TOKEN_LIST1 (volatile unsigned int *)((0x7803 << 2) + 0xffd00000) ++#define I2C_M_1_WDATA_REG0 (0x7804) ++#define P_I2C_M_1_WDATA_REG0 (volatile unsigned int *)((0x7804 << 2) + 0xffd00000) ++#define I2C_M_1_WDATA_REG1 (0x7805) ++#define P_I2C_M_1_WDATA_REG1 (volatile unsigned int *)((0x7805 << 2) + 0xffd00000) ++#define I2C_M_1_RDATA_REG0 (0x7806) ++#define P_I2C_M_1_RDATA_REG0 (volatile unsigned int *)((0x7806 << 2) + 0xffd00000) ++#define I2C_M_1_RDATA_REG1 (0x7807) ++#define P_I2C_M_1_RDATA_REG1 (volatile unsigned int *)((0x7807 << 2) + 0xffd00000) ++// ------------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: I2C_M_2_CBUS_BASE = 0x74 ++// ----------------------------------------------- ++#define I2C_M_2_CONTROL_REG (0x7400) ++#define P_I2C_M_2_CONTROL_REG (volatile unsigned int *)((0x7400 << 2) + 0xffd00000) ++#define I2C_M_2_SLAVE_ADDR (0x7401) ++#define P_I2C_M_2_SLAVE_ADDR (volatile unsigned int *)((0x7401 << 2) + 0xffd00000) ++#define I2C_M_2_TOKEN_LIST0 (0x7402) ++#define P_I2C_M_2_TOKEN_LIST0 (volatile unsigned int *)((0x7402 << 2) + 0xffd00000) ++#define I2C_M_2_TOKEN_LIST1 (0x7403) ++#define P_I2C_M_2_TOKEN_LIST1 (volatile unsigned int *)((0x7403 << 2) + 0xffd00000) ++#define I2C_M_2_WDATA_REG0 (0x7404) ++#define P_I2C_M_2_WDATA_REG0 (volatile unsigned int *)((0x7404 << 2) + 0xffd00000) ++#define I2C_M_2_WDATA_REG1 (0x7405) ++#define P_I2C_M_2_WDATA_REG1 (volatile unsigned int *)((0x7405 << 2) + 0xffd00000) ++#define I2C_M_2_RDATA_REG0 (0x7406) ++#define P_I2C_M_2_RDATA_REG0 (volatile unsigned int *)((0x7406 << 2) + 0xffd00000) ++#define I2C_M_2_RDATA_REG1 (0x7407) ++#define P_I2C_M_2_RDATA_REG1 (volatile unsigned int *)((0x7407 << 2) + 0xffd00000) ++// ------------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: I2C_M_3_CBUS_BASE = 0x70 ++// ----------------------------------------------- ++#define I2C_M_3_CONTROL_REG (0x7000) ++#define P_I2C_M_3_CONTROL_REG (volatile unsigned int *)((0x7000 << 2) + 0xffd00000) ++#define I2C_M_3_SLAVE_ADDR (0x7001) ++#define P_I2C_M_3_SLAVE_ADDR (volatile unsigned int *)((0x7001 << 2) + 0xffd00000) ++#define I2C_M_3_TOKEN_LIST0 (0x7002) ++#define P_I2C_M_3_TOKEN_LIST0 (volatile unsigned int *)((0x7002 << 2) + 0xffd00000) ++#define I2C_M_3_TOKEN_LIST1 (0x7003) ++#define P_I2C_M_3_TOKEN_LIST1 (volatile unsigned int *)((0x7003 << 2) + 0xffd00000) ++#define I2C_M_3_WDATA_REG0 (0x7004) ++#define P_I2C_M_3_WDATA_REG0 (volatile unsigned int *)((0x7004 << 2) + 0xffd00000) ++#define I2C_M_3_WDATA_REG1 (0x7005) ++#define P_I2C_M_3_WDATA_REG1 (volatile unsigned int *)((0x7005 << 2) + 0xffd00000) ++#define I2C_M_3_RDATA_REG0 (0x7006) ++#define P_I2C_M_3_RDATA_REG0 (volatile unsigned int *)((0x7006 << 2) + 0xffd00000) ++#define I2C_M_3_RDATA_REG1 (0x7007) ++#define P_I2C_M_3_RDATA_REG1 (volatile unsigned int *)((0x7007 << 2) + 0xffd00000) ++// ------------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: PWM_AB_CBUS_BASE = 0x6c ++// ----------------------------------------------- ++#define PWM_PWM_A (0x6c00) ++#define P_PWM_PWM_A (volatile unsigned int *)((0x6c00 << 2) + 0xffd00000) ++#define PWM_PWM_B (0x6c01) ++#define P_PWM_PWM_B (volatile unsigned int *)((0x6c01 << 2) + 0xffd00000) ++#define PWM_MISC_REG_AB (0x6c02) ++#define P_PWM_MISC_REG_AB (volatile unsigned int *)((0x6c02 << 2) + 0xffd00000) ++#define PWM_DELTA_SIGMA_AB (0x6c03) ++#define P_PWM_DELTA_SIGMA_AB (volatile unsigned int *)((0x6c03 << 2) + 0xffd00000) ++#define PWM_TIME_AB (0x6c04) ++#define P_PWM_TIME_AB (volatile unsigned int *)((0x6c04 << 2) + 0xffd00000) ++#define PWM_A2 (0x6c05) ++#define P_PWM_A2 (volatile unsigned int *)((0x6c05 << 2) + 0xffd00000) ++#define PWM_B2 (0x6c06) ++#define P_PWM_B2 (volatile unsigned int *)((0x6c06 << 2) + 0xffd00000) ++#define PWM_BLINK_AB (0x6c07) ++#define P_PWM_BLINK_AB (volatile unsigned int *)((0x6c07 << 2) + 0xffd00000) ++// ------------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: PWM_CD_CBUS_BASE = 0x68 ++// ----------------------------------------------- ++#define PWM_PWM_C (0x6800) ++#define P_PWM_PWM_C (volatile unsigned int *)((0x6800 << 2) + 0xffd00000) ++#define PWM_PWM_D (0x6801) ++#define P_PWM_PWM_D (volatile unsigned int *)((0x6801 << 2) + 0xffd00000) ++#define PWM_MISC_REG_CD (0x6802) ++#define P_PWM_MISC_REG_CD (volatile unsigned int *)((0x6802 << 2) + 0xffd00000) ++#define PWM_DELTA_SIGMA_CD (0x6803) ++#define P_PWM_DELTA_SIGMA_CD (volatile unsigned int *)((0x6803 << 2) + 0xffd00000) ++#define PWM_TIME_CD (0x6804) ++#define P_PWM_TIME_CD (volatile unsigned int *)((0x6804 << 2) + 0xffd00000) ++#define PWM_C2 (0x6805) ++#define P_PWM_C2 (volatile unsigned int *)((0x6805 << 2) + 0xffd00000) ++#define PWM_D2 (0x6806) ++#define P_PWM_D2 (volatile unsigned int *)((0x6806 << 2) + 0xffd00000) ++#define PWM_BLINK_CD (0x6807) ++#define P_PWM_BLINK_CD (volatile unsigned int *)((0x6807 << 2) + 0xffd00000) ++// ------------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: PWM_EF_CBUS_BASE = 0x64 ++// ----------------------------------------------- ++#define PWM_PWM_E (0x6400) ++#define P_PWM_PWM_E (volatile unsigned int *)((0x6400 << 2) + 0xffd00000) ++#define PWM_PWM_F (0x6401) ++#define P_PWM_PWM_F (volatile unsigned int *)((0x6401 << 2) + 0xffd00000) ++#define PWM_MISC_REG_EF (0x6402) ++#define P_PWM_MISC_REG_EF (volatile unsigned int *)((0x6402 << 2) + 0xffd00000) ++#define PWM_DELTA_SIGMA_EF (0x6403) ++#define P_PWM_DELTA_SIGMA_EF (volatile unsigned int *)((0x6403 << 2) + 0xffd00000) ++#define PWM_TIME_EF (0x6404) ++#define P_PWM_TIME_EF (volatile unsigned int *)((0x6404 << 2) + 0xffd00000) ++#define PWM_E2 (0x6405) ++#define P_PWM_E2 (volatile unsigned int *)((0x6405 << 2) + 0xffd00000) ++#define PWM_F2 (0x6406) ++#define P_PWM_F2 (volatile unsigned int *)((0x6406 << 2) + 0xffd00000) ++#define PWM_BLINK_EF (0x6407) ++#define P_PWM_BLINK_EF (volatile unsigned int *)((0x6407 << 2) + 0xffd00000) ++// ------------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: MSR_CLK_CBUS_BASE = 0x60 ++// ----------------------------------------------- ++#define MSR_CLK_DUTY (0x6000) ++#define P_MSR_CLK_DUTY (volatile unsigned int *)((0x6000 << 2) + 0xffd00000) ++#define MSR_CLK_REG0 (0x6001) ++#define P_MSR_CLK_REG0 (volatile unsigned int *)((0x6001 << 2) + 0xffd00000) ++#define MSR_CLK_REG1 (0x6002) ++#define P_MSR_CLK_REG1 (volatile unsigned int *)((0x6002 << 2) + 0xffd00000) ++#define MSR_CLK_REG2 (0x6003) ++#define P_MSR_CLK_REG2 (volatile unsigned int *)((0x6003 << 2) + 0xffd00000) ++#define MSR_CLK_REG3 (0x6004) ++#define P_MSR_CLK_REG3 (volatile unsigned int *)((0x6004 << 2) + 0xffd00000) ++#define MSR_CLK_REG4 (0x6005) ++#define P_MSR_CLK_REG4 (volatile unsigned int *)((0x6005 << 2) + 0xffd00000) ++#define MSR_CLK_REG5 (0x6006) ++#define P_MSR_CLK_REG5 (volatile unsigned int *)((0x6006 << 2) + 0xffd00000) ++// ------------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: STEAM_CBUS_BASE = 0x2c ++// ----------------------------------------------- ++// bit 31:24 -- event_length ++// bit 23:22 -- bus_1st_sel_1 //00-gpio, 01-reserved, 10-addr, 11-data ++// bit 21:20 -- bus_2nd_sel_1 ++// bit 19:18 -- bus_1st_sel_0 ++// bit 17:16 -- bus_2nd_sel_0 ++// bit 15:0 -- set output value (output 1 will read according to external input) ++#define STREAM_EVENT_INFO (0x2c00) ++#define P_STREAM_EVENT_INFO (volatile unsigned int *)((0x2c00 << 2) + 0xffd00000) ++// bit 31 -- force_parity_1 ++// bit 30 -- LSB_first ++// bit 31:20 -- reserved ++// bit 19:16 -- toggle point index ++// bit 15:8 -- output togle point1 ++// bit 7:0 -- output togle point0 (0xff means input) ++#define STREAM_OUTPUT_CONFIG (0x2c01) ++#define P_STREAM_OUTPUT_CONFIG (volatile unsigned int *)((0x2c01 << 2) + 0xffd00000) ++// bit 31:24 -- clock_divide_ext ++// bit 23:20 -- s_bus_start ( sclk, sdataout, sdatain) // 0 means no s_bus used ++// bit 19 -- no_sclk_on_pin // will use internal write clock and read clock (like RS232) ++// bit 18 -- invert_sclk_in ++// bit 17 -- sdata_send_busy // indicate one data is sending -- read only ++// bit 16 -- one_sdata_received // set when one sdata is received, can write 0 to clear ++// bit 15 -- sdata_parity // (write -- 0-even, 1-odd) (read -- received parity check) ++// bit 14 -- sdata_send_type // 0 -- 8 bits 1 -- 32 bits ( for fujitsu only ) ++// bit 13 -- sdata_receive_type // 0 -- 8 bits only 1 -- 8/32 bits ++// bit 12 -- invert_request_out ++// bit 11:8 -- request_out_sel // 0 means disable output ++// bit 7:0 -- stop_request_count ++#define C_D_BUS_CONTROL (0x2c02) ++#define P_C_D_BUS_CONTROL (volatile unsigned int *)((0x2c02 << 2) + 0xffd00000) ++// bit 31:0 -- serial data (write: output one data, read: input data) ++#define C_DATA (0x2c03) ++#define P_C_DATA (volatile unsigned int *)((0x2c03 << 2) + 0xffd00000) ++// bit 31:28 bus_width_1 ++// bit 27:24 bus_start_pin_1 ++// bit 23:16 bus_sel_chang_point_1 ++// bit 15:12 bus_width_0 ++// bit 11:08 bus_start_pin_0 ++// bit 07:00 bus_sel_chang_point_0 ++#define STREAM_BUS_CONFIG (0x2c04) ++#define P_STREAM_BUS_CONFIG (volatile unsigned int *)((0x2c04 << 2) + 0xffd00000) ++// bit 31:24 clock_divide ++// bit 23:20 clock_output_sel -- 0 means disable clock output ++// bit 19 -- inc_event_addr ++// bit 18 -- async_fifo_endian ++// bit 17 -- send_to_async_fifo ++// bit 16 -- data_in_serial_lsb ++// bit 15 -- invert_no_wait_condition_0 ++// bit 14 -- invert_no_wait_condition_1 ++// bit 13 -- invert_no_wait_condition_2 ++// bit 12 -- invert_data_bus ++// bit 11 -- invert_clock_in ++// bit 10 -- event_wait_clk_en ++// bit 9 -- data_in_serial ++// bit 8 -- invert_data_in_clk ++// bit 7:4 -- data_in_begin ++// bit 3:0 -- data_in_clk_sel ++#define STREAM_DATA_IN_CONFIG (0x2c05) ++#define P_STREAM_DATA_IN_CONFIG (volatile unsigned int *)((0x2c05 << 2) + 0xffd00000) ++// wait condition and irq should not be connected to 0, 0 means disable) ++// bit 31:28 -- no_wait_condition_0 (0 means disable this condition) ++// bit 27:24 -- no_wait_condition_1 (0 means disable this condition) ++// bit 23:20 -- no_wait_condition_2 (0 means disable this condition) ++// bit 19:16 -- irq_input_sel (0 means disable this interrupt) ++// bit 15:13 -- interrupt_status (read) clear status (write) (ext 0, ext 1, transfer end) ++// bit 12 -- enable_sdata_irq ++// bit 11 -- invert_irq_0 ++// bit 10 -- invert_irq_1 ++// bit 9 -- enable_transfer_end_irq ++// bit 8 -- enable_second_ext_irq ++// bit 7:0 -- no_wait_condition_check_point (0xff means no check) ++#define STREAM_WAIT_IRQ_CONFIG (0x2c06) ++#define P_STREAM_WAIT_IRQ_CONFIG (volatile unsigned int *)((0x2c06 << 2) + 0xffd00000) ++// bit 31:24 -- event address ++// bit 23:16 -- event data ++// bit 15:1 -- event repeat times (0 means one time event) ++// bit 0 -- Start Event (write) event_busy (read) ++#define STREAM_EVENT_CTL (0x2c07) ++#define P_STREAM_EVENT_CTL (volatile unsigned int *)((0x2c07 << 2) + 0xffd00000) ++// ------------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: SYNC_FIFO_CBUS_BASE = 0x28 ++// ----------------------------------------------- ++#define ASYNC_FIFO_REG0 (0x2800) ++#define P_ASYNC_FIFO_REG0 (volatile unsigned int *)((0x2800 << 2) + 0xffd00000) ++#define ASYNC_FIFO_REG1 (0x2801) ++#define P_ASYNC_FIFO_REG1 (volatile unsigned int *)((0x2801 << 2) + 0xffd00000) ++ #define ASYNC_FIFO_FLUSH_STATUS 31 ++ #define ASYNC_FIFO_ERR 30 ++ #define ASYNC_FIFO_FIFO_EMPTY 29 ++ #define ASYNC_FIFO_TO_HIU 24 ++ #define ASYNC_FIFO_FLUSH 23 ++ #define ASYNC_FIFO_RESET 22 ++ #define ASYNC_FIFO_WRAP_EN 21 ++ #define ASYNC_FIFO_FLUSH_EN 20 ++ #define ASYNC_FIFO_RESIDUAL_MSB 19 ++ #define ASYNC_FIFO_RESIDUAL_LSB 15 ++ #define ASYNC_FIFO_FLUSH_CNT_MSB 14 ++ #define ASYNC_FIFO_FLUSH_CNT_LSB 0 ++#define ASYNC_FIFO_REG2 (0x2802) ++#define P_ASYNC_FIFO_REG2 (volatile unsigned int *)((0x2802 << 2) + 0xffd00000) ++ #define ASYNC_FIFO_FIFO_FULL 26 ++ #define ASYNC_FIFO_FILL_STATUS 25 ++ #define ASYNC_FIFO_SOURCE_MSB 24 ++ #define ASYNC_FIFO_SOURCE_LSB 23 ++ #define ASYNC_FIFO_ENDIAN_MSB 22 ++ #define ASYNC_FIFO_ENDIAN_LSB 21 ++ #define ASYNC_FIFO_FILL_EN 20 ++ #define ASYNC_FIFO_FILL_CNT_MSB 19 ++ #define ASYNC_FIFO_FILL_CNT_LSB 0 ++#define ASYNC_FIFO_REG3 (0x2803) ++#define P_ASYNC_FIFO_REG3 (volatile unsigned int *)((0x2803 << 2) + 0xffd00000) ++ #define ASYNC_FLUSH_SIZE_IRQ_MSB 15 ++ #define ASYNC_FLUSH_SIZE_IRQ_LSB 0 ++#define ASYNC_FIFO_REG4 (0x2804) ++#define P_ASYNC_FIFO_REG4 (volatile unsigned int *)((0x2804 << 2) + 0xffd00000) ++#define ASYNC_FIFO_REG5 (0x2805) ++#define P_ASYNC_FIFO_REG5 (volatile unsigned int *)((0x2805 << 2) + 0xffd00000) ++// ------------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: SYNC_FIFO2_CBUS_BASE = 0x24 ++// ----------------------------------------------- ++#define ASYNC_FIFO2_REG0 (0x2400) ++#define P_ASYNC_FIFO2_REG0 (volatile unsigned int *)((0x2400 << 2) + 0xffd00000) ++#define ASYNC_FIFO2_REG1 (0x2401) ++#define P_ASYNC_FIFO2_REG1 (volatile unsigned int *)((0x2401 << 2) + 0xffd00000) ++#define ASYNC_FIFO2_REG2 (0x2402) ++#define P_ASYNC_FIFO2_REG2 (volatile unsigned int *)((0x2402 << 2) + 0xffd00000) ++#define ASYNC_FIFO2_REG3 (0x2403) ++#define P_ASYNC_FIFO2_REG3 (volatile unsigned int *)((0x2403 << 2) + 0xffd00000) ++#define ASYNC_FIFO2_REG4 (0x2404) ++#define P_ASYNC_FIFO2_REG4 (volatile unsigned int *)((0x2404 << 2) + 0xffd00000) ++#define ASYNC_FIFO2_REG5 (0x2405) ++#define P_ASYNC_FIFO2_REG5 (volatile unsigned int *)((0x2405 << 2) + 0xffd00000) ++// ------------------------------------------------------------------------------------ ++// ----------------------------------------------- ++// CBUS_BASE: SPIFC_CBUS_BASE = 0x50 ++// ----------------------------------------------- ++#define SPI_FLASH_CMD (0x5000) ++#define P_SPI_FLASH_CMD (volatile unsigned int *)((0x5000 << 2) + 0xffd00000) ++ #define SPI_FLASH_READ 31 ++ #define SPI_FLASH_WREN 30 ++ #define SPI_FLASH_WRDI 29 ++ #define SPI_FLASH_RDID 28 ++ #define SPI_FLASH_RDSR 27 ++ #define SPI_FLASH_WRSR 26 ++ #define SPI_FLASH_PP 25 ++ #define SPI_FLASH_SE 24 ++ #define SPI_FLASH_BE 23 ++ #define SPI_FLASH_CE 22 ++ #define SPI_FLASH_DP 21 ++ #define SPI_FLASH_RES 20 ++ #define SPI_HPM 19 ++ #define SPI_FLASH_USR 18 ++ #define SPI_FLASH_USR_ADDR 15 ++ #define SPI_FLASH_USR_DUMMY 14 ++ #define SPI_FLASH_USR_DIN 13 ++ #define SPI_FLASH_USR_DOUT 12 ++ #define SPI_FLASH_USR_DUMMY_BLEN 10 ++ #define SPI_FLASH_USR_CMD 0 ++#define SPI_FLASH_ADDR (0x5001) ++#define P_SPI_FLASH_ADDR (volatile unsigned int *)((0x5001 << 2) + 0xffd00000) ++ #define SPI_FLASH_BYTES_LEN 24 ++ #define SPI_FLASH_ADDR_START 0 ++#define SPI_FLASH_CTRL (0x5002) ++#define P_SPI_FLASH_CTRL (volatile unsigned int *)((0x5002 << 2) + 0xffd00000) ++ #define SPI_ENABLE_AHB 17 ++ #define SPI_SST_AAI 16 ++ #define SPI_RES_RID 15 ++ #define SPI_FREAD_DUAL 14 ++ #define SPI_READ_READ_EN 13 ++ #define SPI_CLK_DIV0 12 ++ #define SPI_CLKCNT_N 8 ++ #define SPI_CLKCNT_H 4 ++ #define SPI_CLKCNT_L 0 ++#define SPI_FLASH_CTRL1 (0x5003) ++#define P_SPI_FLASH_CTRL1 (volatile unsigned int *)((0x5003 << 2) + 0xffd00000) ++#define SPI_FLASH_STATUS (0x5004) ++#define P_SPI_FLASH_STATUS (volatile unsigned int *)((0x5004 << 2) + 0xffd00000) ++#define SPI_FLASH_CTRL2 (0x5005) ++#define P_SPI_FLASH_CTRL2 (volatile unsigned int *)((0x5005 << 2) + 0xffd00000) ++#define SPI_FLASH_CLOCK (0x5006) ++#define P_SPI_FLASH_CLOCK (volatile unsigned int *)((0x5006 << 2) + 0xffd00000) ++#define SPI_FLASH_USER (0x5007) ++#define P_SPI_FLASH_USER (volatile unsigned int *)((0x5007 << 2) + 0xffd00000) ++#define SPI_FLASH_USER1 (0x5008) ++#define P_SPI_FLASH_USER1 (volatile unsigned int *)((0x5008 << 2) + 0xffd00000) ++#define SPI_FLASH_USER2 (0x5009) ++#define P_SPI_FLASH_USER2 (volatile unsigned int *)((0x5009 << 2) + 0xffd00000) ++#define SPI_FLASH_USER3 (0x500a) ++#define P_SPI_FLASH_USER3 (volatile unsigned int *)((0x500a << 2) + 0xffd00000) ++#define SPI_FLASH_USER4 (0x500b) ++#define P_SPI_FLASH_USER4 (volatile unsigned int *)((0x500b << 2) + 0xffd00000) ++#define SPI_FLASH_SLAVE (0x500c) ++#define P_SPI_FLASH_SLAVE (volatile unsigned int *)((0x500c << 2) + 0xffd00000) ++#define SPI_FLASH_SLAVE1 (0x500d) ++#define P_SPI_FLASH_SLAVE1 (volatile unsigned int *)((0x500d << 2) + 0xffd00000) ++#define SPI_FLASH_SLAVE2 (0x500e) ++#define P_SPI_FLASH_SLAVE2 (volatile unsigned int *)((0x500e << 2) + 0xffd00000) ++#define SPI_FLASH_SLAVE3 (0x500f) ++#define P_SPI_FLASH_SLAVE3 (volatile unsigned int *)((0x500f << 2) + 0xffd00000) ++#define SPI_FLASH_C0 (0x5010) ++#define P_SPI_FLASH_C0 (volatile unsigned int *)((0x5010 << 2) + 0xffd00000) ++#define SPI_FLASH_C1 (0x5011) ++#define P_SPI_FLASH_C1 (volatile unsigned int *)((0x5011 << 2) + 0xffd00000) ++#define SPI_FLASH_C2 (0x5012) ++#define P_SPI_FLASH_C2 (volatile unsigned int *)((0x5012 << 2) + 0xffd00000) ++#define SPI_FLASH_C3 (0x5013) ++#define P_SPI_FLASH_C3 (volatile unsigned int *)((0x5013 << 2) + 0xffd00000) ++#define SPI_FLASH_C4 (0x5014) ++#define P_SPI_FLASH_C4 (volatile unsigned int *)((0x5014 << 2) + 0xffd00000) ++#define SPI_FLASH_C5 (0x5015) ++#define P_SPI_FLASH_C5 (volatile unsigned int *)((0x5015 << 2) + 0xffd00000) ++#define SPI_FLASH_C6 (0x5016) ++#define P_SPI_FLASH_C6 (volatile unsigned int *)((0x5016 << 2) + 0xffd00000) ++#define SPI_FLASH_C7 (0x5017) ++#define P_SPI_FLASH_C7 (volatile unsigned int *)((0x5017 << 2) + 0xffd00000) ++#define SPI_FLASH_B8 (0x5018) ++#define P_SPI_FLASH_B8 (volatile unsigned int *)((0x5018 << 2) + 0xffd00000) ++#define SPI_FLASH_B9 (0x5019) ++#define P_SPI_FLASH_B9 (volatile unsigned int *)((0x5019 << 2) + 0xffd00000) ++#define SPI_FLASH_B10 (0x501a) ++#define P_SPI_FLASH_B10 (volatile unsigned int *)((0x501a << 2) + 0xffd00000) ++#define SPI_FLASH_B11 (0x501b) ++#define P_SPI_FLASH_B11 (volatile unsigned int *)((0x501b << 2) + 0xffd00000) ++#define SPI_FLASH_B12 (0x501c) ++#define P_SPI_FLASH_B12 (volatile unsigned int *)((0x501c << 2) + 0xffd00000) ++#define SPI_FLASH_B13 (0x501d) ++#define P_SPI_FLASH_B13 (volatile unsigned int *)((0x501d << 2) + 0xffd00000) ++#define SPI_FLASH_B14 (0x501e) ++#define P_SPI_FLASH_B14 (volatile unsigned int *)((0x501e << 2) + 0xffd00000) ++#define SPI_FLASH_B15 (0x501f) ++#define P_SPI_FLASH_B15 (volatile unsigned int *)((0x501f << 2) + 0xffd00000) ++// ------------------------------------------------------------------------------------ ++//spicc 0 ++// ----------------------------------------------- ++// CBUS_BASE: SPICC0_CBUS_BASE = 0x4c ++// ----------------------------------------------- ++#define SPICC0_RXDATA (0x4c00) ++#define P_SPICC0_RXDATA (volatile unsigned int *)((0x4c00 << 2) + 0xffd00000) ++#define SPICC0_TXDATA (0x4c01) ++#define P_SPICC0_TXDATA (volatile unsigned int *)((0x4c01 << 2) + 0xffd00000) ++#define SPICC0_CONREG (0x4c02) ++#define P_SPICC0_CONREG (volatile unsigned int *)((0x4c02 << 2) + 0xffd00000) ++#define SPICC0_INTREG (0x4c03) ++#define P_SPICC0_INTREG (volatile unsigned int *)((0x4c03 << 2) + 0xffd00000) ++#define SPICC0_DMAREG (0x4c04) ++#define P_SPICC0_DMAREG (volatile unsigned int *)((0x4c04 << 2) + 0xffd00000) ++#define SPICC0_STATREG (0x4c05) ++#define P_SPICC0_STATREG (volatile unsigned int *)((0x4c05 << 2) + 0xffd00000) ++#define SPICC0_PERIODREG (0x4c06) ++#define P_SPICC0_PERIODREG (volatile unsigned int *)((0x4c06 << 2) + 0xffd00000) ++#define SPICC0_TESTREG (0x4c07) ++#define P_SPICC0_TESTREG (volatile unsigned int *)((0x4c07 << 2) + 0xffd00000) ++#define SPICC0_DRADDR (0x4c08) ++#define P_SPICC0_DRADDR (volatile unsigned int *)((0x4c08 << 2) + 0xffd00000) ++#define SPICC0_DWADDR (0x4c09) ++#define P_SPICC0_DWADDR (volatile unsigned int *)((0x4c09 << 2) + 0xffd00000) ++#define SPICC0_LD_CNTL0 (0x4c0a) ++#define P_SPICC0_LD_CNTL0 (volatile unsigned int *)((0x4c0a << 2) + 0xffd00000) ++#define SPICC0_LD_CNTL1 (0x4c0b) ++#define P_SPICC0_LD_CNTL1 (volatile unsigned int *)((0x4c0b << 2) + 0xffd00000) ++#define SPICC0_LD_RADDR (0x4c0c) ++#define P_SPICC0_LD_RADDR (volatile unsigned int *)((0x4c0c << 2) + 0xffd00000) ++#define SPICC0_LD_WADDR (0x4c0d) ++#define P_SPICC0_LD_WADDR (volatile unsigned int *)((0x4c0d << 2) + 0xffd00000) ++#define SPICC0_ENHANCE_CNTL (0x4c0e) ++#define P_SPICC0_ENHANCE_CNTL (volatile unsigned int *)((0x4c0e << 2) + 0xffd00000) ++// ------------------------------------------------------------------------------------ ++//spicc 1 ++// ----------------------------------------------- ++// CBUS_BASE: SPICC1_CBUS_BASE = 0x54 ++// ----------------------------------------------- ++#define SPICC1_RXDATA (0x5400) ++#define P_SPICC1_RXDATA (volatile unsigned int *)((0x5400 << 2) + 0xffd00000) ++#define SPICC1_TXDATA (0x5401) ++#define P_SPICC1_TXDATA (volatile unsigned int *)((0x5401 << 2) + 0xffd00000) ++#define SPICC1_CONREG (0x5402) ++#define P_SPICC1_CONREG (volatile unsigned int *)((0x5402 << 2) + 0xffd00000) ++#define SPICC1_INTREG (0x5403) ++#define P_SPICC1_INTREG (volatile unsigned int *)((0x5403 << 2) + 0xffd00000) ++#define SPICC1_DMAREG (0x5404) ++#define P_SPICC1_DMAREG (volatile unsigned int *)((0x5404 << 2) + 0xffd00000) ++#define SPICC1_STATREG (0x5405) ++#define P_SPICC1_STATREG (volatile unsigned int *)((0x5405 << 2) + 0xffd00000) ++#define SPICC1_PERIODREG (0x5406) ++#define P_SPICC1_PERIODREG (volatile unsigned int *)((0x5406 << 2) + 0xffd00000) ++#define SPICC1_TESTREG (0x5407) ++#define P_SPICC1_TESTREG (volatile unsigned int *)((0x5407 << 2) + 0xffd00000) ++#define SPICC1_DRADDR (0x5408) ++#define P_SPICC1_DRADDR (volatile unsigned int *)((0x5408 << 2) + 0xffd00000) ++#define SPICC1_DWADDR (0x5409) ++#define P_SPICC1_DWADDR (volatile unsigned int *)((0x5409 << 2) + 0xffd00000) ++#define SPICC1_LD_CNTL0 (0x540a) ++#define P_SPICC1_LD_CNTL0 (volatile unsigned int *)((0x540a << 2) + 0xffd00000) ++#define SPICC1_LD_CNTL1 (0x540b) ++#define P_SPICC1_LD_CNTL1 (volatile unsigned int *)((0x540b << 2) + 0xffd00000) ++#define SPICC1_LD_RADDR (0x540c) ++#define P_SPICC1_LD_RADDR (volatile unsigned int *)((0x540c << 2) + 0xffd00000) ++#define SPICC1_LD_WADDR (0x540d) ++#define P_SPICC1_LD_WADDR (volatile unsigned int *)((0x540d << 2) + 0xffd00000) ++#define SPICC1_ENHANCE_CNTL (0x540e) ++#define P_SPICC1_ENHANCE_CNTL (volatile unsigned int *)((0x540e << 2) + 0xffd00000) ++// ++//// ------------------------------------------------------------------- ++//// PSEL Group #1: 0x400 ~ 0x7FF ++//// ------------------------------------------------------------------- ++//`define PERIPHS1_CBUS_BASE 8'h28 ++// ++// ++// ++//// ---------------------------- ++//// IR Remote (8) ++//// ---------------------------- ++//`define IR_DEC_LDR_ACTIVE 8'h20 ++//`define IR_DEC_LDR_IDLE 8'h21 ++//`define IR_DEC_LDR_REPEAT 8'h22 ++//`define IR_DEC_BIT_0 8'h23 ++//`define IR_DEC_REG0 8'h24 ++//`define IR_DEC_FRAME 8'h25 ++//`define IR_DEC_STATUS 8'h26 ++//`define IR_DEC_REG1 8'h27 ++// ++//// ---------------------------- ++//// Demod Sampling ++//// ---------------------------- ++//`define DEMOD_ADC_SAMPLING 8'h2d ++//// ---------------------------- ++//// WIFI ++//// ---------------------------- ++//// `define WIFI_ADC_SAMPLING 8'h2e ++//// `define WIFI_ADC_READBACK 8'h2f ++// ++// ++//// --------------------------- ++//// EFUSE (4) ++//// ---------------------------- ++//// Moved to the Secure APB3 bus ++//// `define EFUSE_CNTL0 8'h58 ++//// `define EFUSE_CNTL1 8'h59 ++//// `define EFUSE_CNTL2 8'h5a ++//// `define EFUSE_CNTL3 8'h5b ++//// `define EFUSE_CNTL4 8'h5c ++// ++//// --------------------------------------------- ++//// Separate APB slave that shares the CBUS/APB ++//// register space of the static registers ++//// --------------------------------------------- ++// ++//`define ATAPI_IDEREG0 8'h60 ++// `define IDE_UDMA_PIO_STATE 15 ++// `define IDE_BUSY 14 ++// `define IDE_ERROR_BIT 13 ++// `define IDE_DMARQ_BIT 12 ++// `define IDE_IORDY_BIT 11 ++// `define IDE_IORDY_EN_BIT 10 ++// `define IDE_DIS_CSEL_BIT 9 ++// `define IDE_CSEL_BIT 8 ++// `define IDE_IRQ14 2 ++// `define IDE_ATAPI_GPIO_EN 3 ++// `define IDE_DMARQ_FULL 1 ++// `define IDE_ENABLE 0 ++//`define ATAPI_IDEREG1 8'h61 ++//`define ATAPI_IDEREG2 8'h62 ++// `define IDE_XFER_CNT_MSB_BIT 18 ++// `define IDE_XFER_CNT_LSB_BIT 0 ++//`define ATAPI_CYCTIME 8'h63 ++//`define ATAPI_IDETIME 8'h64 ++//`define ATAPI_PIO_TIMING 8'h65 ++//`define ATAPI_TABLE_ADD_REG 8'h66 ++//`define ATAPI_IDEREG3 8'h67 ++//`define ATAPI_UDMA_REG0 8'h68 ++//`define ATAPI_UDMA_REG1 8'h69 ++// ++//// Room for registers here ++// ++//`define TRANS_PWMA_REG0 8'h70 ++//`define TRANS_PWMA_REG1 8'h71 ++//`define TRANS_PWMA_MUX0 8'h72 ++//`define TRANS_PWMA_MUX1 8'h73 ++//`define TRANS_PWMA_MUX2 8'h74 ++//`define TRANS_PWMA_MUX3 8'h75 ++//`define TRANS_PWMA_MUX4 8'h76 ++//`define TRANS_PWMA_MUX5 8'h77 ++// ++//`define TRANS_PWMB_REG0 8'h78 ++//`define TRANS_PWMB_REG1 8'h79 ++//`define TRANS_PWMB_MUX0 8'h7a ++//`define TRANS_PWMB_MUX1 8'h7b ++//`define TRANS_PWMB_MUX2 8'h7c ++//`define TRANS_PWMB_MUX3 8'h7d ++//`define TRANS_PWMB_MUX4 8'h7e ++//`define TRANS_PWMB_MUX5 8'h7f ++// ++// ++// ++//// ---------------------------- ++//// NAND (21) ++//// ---------------------------- ++//`define NAND_START 8'h80 ++//`define NAND_ADR_CMD 8'h8a ++//`define NAND_ADR_STS 8'h8b ++//`define NAND_END 8'h8f ++// ++//// ---------------------------- ++//// ISP_FLASH_LED_CTRL ++//// ---------------------------- ++////bit 31, reg_led_en //rising pulse start, falling pulse stop for torch mode ++////bit 30, reg_inc_i_st_lat //for as3685, dynamic increase current during st_latch ++////bit 29:28, reg_inv_en_pol //bit[29], invert en1, bit [28], invert en2 ++////bit 27, reg_switch_en1en2 //switch output en1 and en2. For IS3231: en1 is EN, en2 is mode. ++////bit 26, reg_force_off_mode //1: reset state machine at the falling edge no matter which state it is in ++////bit 25, reg_hold_nonstd_off_mode //hold the non-std led_off signal input before state "OFF" ++////bit 24, reg_flash_mode_timeout_en //force to exit the Tlat state when time out, for flash mode protection ++////bit 23, reg_en1_st_ini_level //en1 level during state ST_INI ++////bit 22, reg_en2_st_set_mp_level //en2 level during state ST_SET_MP_HI, ST_SET_MP_LO ++////bit 21, reg_en1_st_off_level //en1 level during state ST_OFF ++////bit 20, reg_en2_st_off_level //en2 level during state ST_OFF ++////bit 19:12, reg_en1_mp_num //en1 multi pulse number, up to 256 step current control ++////bit 10:0, reg_t_st_ini //Max: 85.2 us under 24M clock input ++//`define ISP_LED_CTRL 8'h98 ++// ++////bit 31:21, reg_t_en1_inc_i_st_lat_cnt //Max: 85.2us under 24M. for as3685, dynamic increase current during st_latch ++////bit 20:10, reg_t_en2_lo_st_ini //Max: 85.2 us under 24M clock input ++////bit 9:0, reg_t_en2_hi1_st_lat_cnt //42.62us @24M, EN2 can output hi-lo-hi during ST_LATCH, this is the first lo -duration ++//`define ISP_LED_TIMING1 8'h99 ++// ++////bit 31:21, reg_t_en1_mp_hi_cnt //Max: 85.2 us under 24M clock input, mp means multi pulse ++////bit 20:10, reg_t_en1_mp_lo_cnt //Max: 85.2 us under 24M clock input, mp means multi pulse ++////bit 9:0, reg_t_en2_lo1_st_lat_cnt //42.62us @24M, EN2 can output hi-lo-hi during ST_LATCH, this is the first lo -duration ++//`define ISP_LED_TIMING2 8'h9a ++// ++////bit 30:28, RO state ++////bit 25:0, reg_flash_mode_timeout_cnt //up to 2.79s at 24Mhz clk input ++//`define ISP_LED_TIMING3 8'h9b ++// ++////bit 25:0, reg_t_st_lat_cnt //up to 2.79s, keep the led on if it's 26'h3ffffff under torch mode ++//`define ISP_LED_TIMING4 8'h9c ++// ++////bit 31:26, reg_t_st_off_cnt[5:0] //up to 85.2us OFF state. ++////bit 25:0, reg_t_en2_hi2_st_lat_cnt //EN2 can output hi-lo-hi during ST_LATCH, this is the second hi -duration ++//`define ISP_LED_TIMING5 8'h9d ++// ++////bit 30:26, reg_t_st_off_cnt[10:6] //up to 85.2us OFF state. ++////bit 25:0, reg_t_en1_st_lat_hold_cnt //to make sure Tlat to meat it's minimum request 500us (since non-std led_off signal may comes in anytime) ++//`define ISP_LED_TIMING6 8'h9e ++//// ---------------------------- ++//// SAR ADC (16) ++//// ---------------------------- ++////`define SAR_ADC_REG0 8'ha0 ++////`define SAR_ADC_CHAN_LIST 8'ha1 ++////`define SAR_ADC_AVG_CNTL 8'ha2 ++////`define SAR_ADC_REG3 8'ha3 ++////`define SAR_ADC_DELAY 8'ha4 ++////`define SAR_ADC_LAST_RD 8'ha5 ++////`define SAR_ADC_FIFO_RD 8'ha6 ++////`define SAR_ADC_AUX_SW 8'ha7 ++////`define SAR_ADC_CHAN_10_SW 8'ha8 ++////`define SAR_ADC_DETECT_IDLE_SW 8'ha9 ++////`define SAR_ADC_DELTA_10 8'haa ++////`define SAR_ADC_REG11 8'hab ++////`define SAR_ADC_REG12 8'hac ++////`define SAR_ADC_REG13 8'had ++// ++//// ---------------------------- ++//// CTouch (16) ++//// ---------------------------- ++// ++// ++//// --------------------------- ++//// RTC (4) ++//// --------------------------- ++//`define RTC_ADDR0 8'hd0 ++//`define RTC_ADDR1 8'hd1 ++//`define RTC_ADDR2 8'hd2 ++//`define RTC_ADDR3 8'hd3 ++//`define RTC_ADDR4 8'hd4 ++//// ---------------------------- ++//// clock measure (4) ++//// ---------------------------- ++// ++// ++// ++//// ------------------------------------------------------------------- ++//// PSEL Group #2: 0x800 ~ 0xbFF ++//// ------------------------------------------------------------------- ++//`define PERIPHS2_CBUS_BASE 8'h2c ++// ++//`define USB_ADDR0 8'h00 ++//`define USB_ADDR1 8'h01 ++//`define USB_ADDR2 8'h02 ++//`define USB_ADDR3 8'h03 ++//`define USB_ADDR4 8'h04 ++//`define USB_ADDR5 8'h05 ++//`define USB_ADDR6 8'h06 ++//`define USB_ADDR7 8'h07 ++//`define USB_ADDR8 8'h08 ++//`define USB_ADDR9 8'h09 ++//`define USB_ADDR10 8'h0a ++//`define USB_ADDR11 8'h0b ++//`define USB_ADDR12 8'h0c ++//`define USB_ADDR13 8'h0d ++//`define USB_ADDR14 8'h0e ++//`define USB_ADDR15 8'h0f ++// ++//`define USB_ADDR16 8'h10 ++//`define USB_ADDR17 8'h11 ++//`define USB_ADDR18 8'h12 ++//`define USB_ADDR19 8'h13 ++//`define USB_ADDR20 8'h14 ++//`define USB_ADDR21 8'h15 ++//`define USB_ADDR22 8'h16 ++//`define USB_ADDR23 8'h17 ++//`define USB_ADDR24 8'h18 ++//`define USB_ADDR25 8'h19 ++//`define USB_ADDR26 8'h1a ++//`define USB_ADDR27 8'h1b ++//`define USB_ADDR28 8'h1c ++//`define USB_ADDR29 8'h1d ++//`define USB_ADDR30 8'h1e ++//`define USB_ADDR31 8'h1f ++// ++// ++// ++// ++// ++//// ------------------------------------------------------------------- ++//// PSEL Group #3: 0xc00 ~ 0xFFF ++//// ------------------------------------------------------------------- ++//`define PERIPHS3_CBUS_BASE 8'h30 ++// ++//// --------------------------- ++//// SDIO (8) ++//// --------------------------- ++//// `define C_SDIO_HIGH16 8'h00 ++//// bit 31:0 -- cmd_argument/MS_SHORT_DATA_WRITE ++//`define CMD_ARGUMENT 8'h08 ++//// bit 31:24 -- repeat_package_times/MS_SHORT_DATA_WRITE_NUMBER ++//// bit 21 -- use_int_window ++//// bit 20 -- cmd_send_data/MS_HAVE_LONG_DATA_WRITE ++//// bit 19 -- check_busy_on_dat0 (used for R1b response) ++//// bit 18 -- response_crc7_from_8 ++//// bit 17 -- response_have_data/MS_HAVE_LONG_DATA_READ ++//// bit 16 -- response_do_not_have_crc7/MS_SHORT_DATA_DO_NOT_HAVE_CRC16 ++//// bit 15:8 -- cmd_response_bits (00 means no response) /MS_SHORT_DATA_READ_NUMBER ++//// bit 7:0 -- cmd_command/MS_TPC ++//`define CMD_SEND 8'h09 ++//// bit 31:29 -- sdio_write_CRC_ok_status ++//// bit 28:23 -- sdio_write_Nwr ++//// bit 22:21 -- m_endian ++//// bit 20 -- bus_width ++//// bit 19 -- data_latch_at_negedge (normally at posedge) ++//// bit 18 -- do_not_delay_data (normally delay one clock) ++//// bit 17:12 -- cmd_argument_bits (before CRC, normally : 39) ++//// bit 11 -- cmd_out_at_posedge (normally at negedge) ++//// bit 10 -- cmd_disable_CRC ++//// bit 9:0 -- cmd_clk_divide ++//`define SDIO_CONFIG 8'h0a ++//// bit 31:19 -- sdio_timing_out_count ++//// bit 18 -- arc_timing_out_int_en ++//// bit 17 -- amrisc_timing_out_int_en ++//// bit 16 -- sdio_timig_out_int -- write 1 clear this int bit ++//// bit 15:12 -- sdio_status_info -- used for change infor between ARC and Amrisc ++//// bit 11 -- sdio_set_soft_int -- write 1 to this bit will set sdio_soft_int , read out is m_req_sdio ++//// bit 10 -- sdio_soft_int -- write 1 clear this int bit ++//// bit 9 -- sdio_cmd_int -- write 1 clear this int bit ++//// bit 8 -- sdio_if_int -- write 1 clear this int bit ++//// bit 7 -- sdio_data_write_crc16_ok -- Read-Only ++//// bit 6 -- sdio_data_read_crc16_ok -- Read-Only ++//// bit 5 -- sdio_response_crc7_ok -- Read-Only ++//// bit 4 -- sdio_cmd_busy -- Read-Only ++//// bit 3:0 -- sdio_status -- Read-Only ++//`define SDIO_STATUS_IRQ 8'h0b ++//// bit 31 -- halt_hole 0 -- 8 bits 1 -- 16 bits ++//// bit 30 -- force_halt ++//// bit 29:24 -- sdio_force_data_read (read_only) ++//// bit 23:22 -- disable_mem_halt (write and read) ++//// bit 21:16 -- sdio_force_output_en ++//// bit 15 -- soft_reset ++//// bit 14 -- sdio_force_enable ++//// bit 13:8 -- sdio_force_data/sdio_read_data ++//// bit 7:6 -- sdio_if_int_config ++//// bit 5 -- arc_soft_int_en ++//// bit 4 -- arc_cmd_int_en ++//// bit 3 -- arc_if_int_en ++//// bit 2 -- amrisc_soft_int_en ++//// bit 1 -- amrisc_cmd_int_en ++//// bit 0 -- amrisc_if_int_en ++//`define SDIO_IRQ_CONFIG 8'h0c ++//// bit 27:16 -- data_catch_finish_point ++//// ( ++//// bit 15:12 -- response_read_index ++//// bit 9 -- data_catch_readout_en ++//// bit 8 -- write_read_out_index ++//// ) this bits only write when write_read_out_index = 1 ++//// bit 11 -- sdio_1_data_swap01 ++//// bit 10 -- sdio_0_data_on_1 ++//// bit 7:6 -- data_catch_level ++//// bit 5 -- stream_8_bits_mode ++//// bit 4 -- stream_enable ++//// bit 3 -- ms_sclk_always ++//// bit 2 -- ms_enable ++//// bit 1:0 -- SDIO_port_sel //00-sdio1, 01-sdio2, 02-sdio3 ++//`define SDIO_MULT_CONFIG 8'h0d ++//// bit 31:0 -- m_addr_sdio ++//`define SDIO_M_ADDR 8'h0e ++//// bit 31 -- CRC_status_4line ++//// bit 30 -- data_rw_do_not_have_crc16/MS_LONG_DATA_DO_NOT_HAVE_CRC16 ++//// bit 29:16 -- data_rw_number/MS_LONG_DATA_NUMBER ++//// bit 15:0 -- cmd_argument_ext/MS_SHORT_DATA_EXTENSION ++//`define SDIO_EXTENSION 8'h0f ++//// ---------------------------- ++//// SDIO_AHB_CBUS (2) ++//// ---------------------------- ++//// bit 17 -- arc_ahb_cbus_int_en ++//// bit 16 -- amrisc_ahb_cbus_int_en ++//// bit 15:8 -- SDIO_FIFO_count ++//// bit 7:4 -- m_req_count ++//// bit 3 -- reserved ++//// bit 2 -- m_write_cbus ++//// bit 1 -- m_req_cbus ++//// bit 0 -- sdio_ahb_cbus_enable ++//`define SDIO_AHB_CBUS_CTRL 8'h18 ++//// m_rd_data[31:0] when (m_write_cbus == 0) CBUS write ++//// m_wr_data[31:0] when (m_write_cbus == 1) CBUS read ++//`define SDIO_AHB_CBUS_M_DATA 8'h19 ++// ++// ++//// ---------------------------- ++//// SDHC (SDIO #2) ++//// ---------------------------- ++//`define SD_REG0_ARGU 8'h80 ++//`define SD_REG1_SEND 8'h81 ++//`define SD_REG2_CNTL 8'h82 ++//`define SD_REG3_STAT 8'h83 ++//`define SD_REG4_CLKC 8'h84 ++//`define SD_REG5_ADDR 8'h85 ++//`define SD_REG6_PDMA 8'h86 ++//`define SD_REG7_MISC 8'h87 ++//`define SD_REG8_DATA 8'h88 ++//`define SD_REG9_ICTL 8'h89 ++//`define SD_REGA_ISTA 8'h8a ++//`define SD_REGB_SRST 8'h8b ++//`define SD_REGC_ESTA 8'h8c ++//`define SD_REGD_ENHC 8'h8d ++//`define SD_REGE_CLK2 8'h8e ++// ++// ++// Closing file: periphs_reg.h ++// ++// ++// Reading file: isa_reg.h ++// ++// $isa/rtl/isa_core register defines for the APB bus ++// CBUS base slave address ++// ----------------------------------------------- ++// CBUS_BASE: ISA_CBUS_BASE = 0x3c ++// ----------------------------------------------- ++// Up to 256 registers for this base ++#define ISA_DEBUG_REG0 (0x3c00) ++#define P_ISA_DEBUG_REG0 (volatile unsigned int *)((0x3c00 << 2) + 0xffd00000) ++#define ISA_DEBUG_REG1 (0x3c01) ++#define P_ISA_DEBUG_REG1 (volatile unsigned int *)((0x3c01 << 2) + 0xffd00000) ++#define ISA_DEBUG_REG2 (0x3c02) ++#define P_ISA_DEBUG_REG2 (volatile unsigned int *)((0x3c02 << 2) + 0xffd00000) ++#define ISA_DEBUG_REG3 (0x3c03) ++#define P_ISA_DEBUG_REG3 (volatile unsigned int *)((0x3c03 << 2) + 0xffd00000) ++#define ISA_PLL_CLK_SIM0 (0x3c08) ++#define P_ISA_PLL_CLK_SIM0 (volatile unsigned int *)((0x3c08 << 2) + 0xffd00000) ++#define ISA_CNTL_REG0 (0x3c09) ++#define P_ISA_CNTL_REG0 (volatile unsigned int *)((0x3c09 << 2) + 0xffd00000) ++// ----------------------------------------------------------- ++#define AO_CPU_IRQ_IN0_INTR_STAT (0x3c10) ++#define P_AO_CPU_IRQ_IN0_INTR_STAT (volatile unsigned int *)((0x3c10 << 2) + 0xffd00000) ++#define AO_CPU_IRQ_IN0_INTR_STAT_CLR (0x3c11) ++#define P_AO_CPU_IRQ_IN0_INTR_STAT_CLR (volatile unsigned int *)((0x3c11 << 2) + 0xffd00000) ++#define AO_CPU_IRQ_IN0_INTR_MASK (0x3c12) ++#define P_AO_CPU_IRQ_IN0_INTR_MASK (volatile unsigned int *)((0x3c12 << 2) + 0xffd00000) ++#define AO_CPU_IRQ_IN0_INTR_FIRQ_SEL (0x3c13) ++#define P_AO_CPU_IRQ_IN0_INTR_FIRQ_SEL (volatile unsigned int *)((0x3c13 << 2) + 0xffd00000) ++// define MEDIA_CPU_IRQ_IN1_INTR_STAT 8'h14 ++// define MEDIA_CPU_IRQ_IN1_INTR_STAT_CLR 8'h15 ++// define MEDIA_CPU_IRQ_IN1_INTR_MASK 8'h16 ++// define MEDIA_CPU_IRQ_IN1_INTR_FIRQ_SEL 8'h17 ++// ++// define MEDIA_CPU_IRQ_IN2_INTR_STAT 8'h18 ++// define MEDIA_CPU_IRQ_IN2_INTR_STAT_CLR 8'h19 ++// define MEDIA_CPU_IRQ_IN2_INTR_MASK 8'h1a ++// define MEDIA_CPU_IRQ_IN2_INTR_FIRQ_SEL 8'h1b ++// ++// define MEDIA_CPU_IRQ_IN3_INTR_STAT 8'h1c ++// define MEDIA_CPU_IRQ_IN3_INTR_STAT_CLR 8'h1d ++// define MEDIA_CPU_IRQ_IN3_INTR_MASK 8'h1e ++// define MEDIA_CPU_IRQ_IN3_INTR_FIRQ_SEL 8'h1f ++#define GPIO_INTR_EDGE_POL (0x3c20) ++#define P_GPIO_INTR_EDGE_POL (volatile unsigned int *)((0x3c20 << 2) + 0xffd00000) ++#define GPIO_INTR_GPIO_SEL0 (0x3c21) ++#define P_GPIO_INTR_GPIO_SEL0 (volatile unsigned int *)((0x3c21 << 2) + 0xffd00000) ++#define GPIO_INTR_GPIO_SEL1 (0x3c22) ++#define P_GPIO_INTR_GPIO_SEL1 (volatile unsigned int *)((0x3c22 << 2) + 0xffd00000) ++#define GPIO_INTR_FILTER_SEL0 (0x3c23) ++#define P_GPIO_INTR_FILTER_SEL0 (volatile unsigned int *)((0x3c23 << 2) + 0xffd00000) ++// `define GLOBAL_INTR_DISABLE 8'h24 never used ++#define CVBS_IRQ0_CNTL (0x3c24) ++#define P_CVBS_IRQ0_CNTL (volatile unsigned int *)((0x3c24 << 2) + 0xffd00000) ++#define CVBS_IRQ1_CNTL (0x3c25) ++#define P_CVBS_IRQ1_CNTL (volatile unsigned int *)((0x3c25 << 2) + 0xffd00000) ++#define CVBS_IRQ0_COUNTER (0x3c26) ++#define P_CVBS_IRQ0_COUNTER (volatile unsigned int *)((0x3c26 << 2) + 0xffd00000) ++#define CVBS_IRQ1_COUNTER (0x3c27) ++#define P_CVBS_IRQ1_COUNTER (volatile unsigned int *)((0x3c27 << 2) + 0xffd00000) ++#define MEDIA_CPU_INTR_STAT (0x3c28) ++#define P_MEDIA_CPU_INTR_STAT (volatile unsigned int *)((0x3c28 << 2) + 0xffd00000) ++#define MEDIA_CPU_INTR_STAT_CLR (0x3c29) ++#define P_MEDIA_CPU_INTR_STAT_CLR (volatile unsigned int *)((0x3c29 << 2) + 0xffd00000) ++#define MEDIA_CPU_INTR_MASK (0x3c2a) ++#define P_MEDIA_CPU_INTR_MASK (volatile unsigned int *)((0x3c2a << 2) + 0xffd00000) ++#define MEDIA_CPU_INTR_FIRQ_SEL (0x3c2b) ++#define P_MEDIA_CPU_INTR_FIRQ_SEL (volatile unsigned int *)((0x3c2b << 2) + 0xffd00000) ++// ----------------------------------------------------------- ++#define ISA_BIST_REG0 (0x3c30) ++#define P_ISA_BIST_REG0 (volatile unsigned int *)((0x3c30 << 2) + 0xffd00000) ++#define ISA_BIST_REG1 (0x3c31) ++#define P_ISA_BIST_REG1 (volatile unsigned int *)((0x3c31 << 2) + 0xffd00000) ++// ----------------------------------------------------------- ++#define WATCHDOG_CNTL (0x3c34) ++#define P_WATCHDOG_CNTL (volatile unsigned int *)((0x3c34 << 2) + 0xffd00000) ++#define WATCHDOG_CNTL1 (0x3c35) ++#define P_WATCHDOG_CNTL1 (volatile unsigned int *)((0x3c35 << 2) + 0xffd00000) ++#define WATCHDOG_TCNT (0x3c36) ++#define P_WATCHDOG_TCNT (volatile unsigned int *)((0x3c36 << 2) + 0xffd00000) ++#define WATCHDOG_RST (0x3c37) ++#define P_WATCHDOG_RST (volatile unsigned int *)((0x3c37 << 2) + 0xffd00000) ++// ----------------------------------------------------------- ++#define AHB_ARBITER_REG (0x3c42) ++#define P_AHB_ARBITER_REG (volatile unsigned int *)((0x3c42 << 2) + 0xffd00000) ++#define AHB_ARBDEC_REG (0x3c43) ++#define P_AHB_ARBDEC_REG (volatile unsigned int *)((0x3c43 << 2) + 0xffd00000) ++#define AHB_ARBITER2_REG (0x3c4a) ++#define P_AHB_ARBITER2_REG (volatile unsigned int *)((0x3c4a << 2) + 0xffd00000) ++#define DEVICE_MMCP_CNTL (0x3c4b) ++#define P_DEVICE_MMCP_CNTL (volatile unsigned int *)((0x3c4b << 2) + 0xffd00000) ++#define AUDIO_MMCP_CNTL (0x3c4c) ++#define P_AUDIO_MMCP_CNTL (volatile unsigned int *)((0x3c4c << 2) + 0xffd00000) ++// ----------------------------------------------------------- ++#define ISA_TIMER_MUX (0x3c50) ++#define P_ISA_TIMER_MUX (volatile unsigned int *)((0x3c50 << 2) + 0xffd00000) ++#define ISA_TIMERA (0x3c51) ++#define P_ISA_TIMERA (volatile unsigned int *)((0x3c51 << 2) + 0xffd00000) ++#define ISA_TIMERB (0x3c52) ++#define P_ISA_TIMERB (volatile unsigned int *)((0x3c52 << 2) + 0xffd00000) ++#define ISA_TIMERC (0x3c53) ++#define P_ISA_TIMERC (volatile unsigned int *)((0x3c53 << 2) + 0xffd00000) ++#define ISA_TIMERD (0x3c54) ++#define P_ISA_TIMERD (volatile unsigned int *)((0x3c54 << 2) + 0xffd00000) ++#define FBUF_ADDR (0x3c56) ++#define P_FBUF_ADDR (volatile unsigned int *)((0x3c56 << 2) + 0xffd00000) ++ #define VIDEO_FRM_BUF_MSB_BIT 23 ++ #define VIDEO_FRM_BUF_LSB_BIT 2 ++#define SDRAM_CTL0 (0x3c57) ++#define P_SDRAM_CTL0 (volatile unsigned int *)((0x3c57 << 2) + 0xffd00000) ++#define SDRAM_CTL2 (0x3c58) ++#define P_SDRAM_CTL2 (volatile unsigned int *)((0x3c58 << 2) + 0xffd00000) ++//`define AO_CPU_CTL 8'h59 ++#define SDRAM_CTL4 (0x3c5a) ++#define P_SDRAM_CTL4 (volatile unsigned int *)((0x3c5a << 2) + 0xffd00000) ++#define SDRAM_CTL5 (0x3c5b) ++#define P_SDRAM_CTL5 (volatile unsigned int *)((0x3c5b << 2) + 0xffd00000) ++#define SDRAM_CTL6 (0x3c5c) ++#define P_SDRAM_CTL6 (volatile unsigned int *)((0x3c5c << 2) + 0xffd00000) ++#define SDRAM_CTL7 (0x3c5d) ++#define P_SDRAM_CTL7 (volatile unsigned int *)((0x3c5d << 2) + 0xffd00000) ++#define SDRAM_CTL8 (0x3c5e) ++#define P_SDRAM_CTL8 (volatile unsigned int *)((0x3c5e << 2) + 0xffd00000) ++#define AHB_MP4_MC_CTL (0x3c5f) ++#define P_AHB_MP4_MC_CTL (volatile unsigned int *)((0x3c5f << 2) + 0xffd00000) ++#define MEDIA_CPU_PCR (0x3c60) ++#define P_MEDIA_CPU_PCR (volatile unsigned int *)((0x3c60 << 2) + 0xffd00000) ++#define MEDIA_CPU_CTL (0x3c61) ++#define P_MEDIA_CPU_CTL (volatile unsigned int *)((0x3c61 << 2) + 0xffd00000) ++#define ISA_TIMERE (0x3c62) ++#define P_ISA_TIMERE (volatile unsigned int *)((0x3c62 << 2) + 0xffd00000) ++#define ISA_TIMERE_HI (0x3c63) ++#define P_ISA_TIMERE_HI (volatile unsigned int *)((0x3c63 << 2) + 0xffd00000) ++#define ISA_TIMER_MUX1 (0x3c64) ++#define P_ISA_TIMER_MUX1 (volatile unsigned int *)((0x3c64 << 2) + 0xffd00000) ++#define ISA_TIMERF (0x3c65) ++#define P_ISA_TIMERF (volatile unsigned int *)((0x3c65 << 2) + 0xffd00000) ++#define ISA_TIMERG (0x3c66) ++#define P_ISA_TIMERG (volatile unsigned int *)((0x3c66 << 2) + 0xffd00000) ++#define ISA_TIMERH (0x3c67) ++#define P_ISA_TIMERH (volatile unsigned int *)((0x3c67 << 2) + 0xffd00000) ++#define ISA_TIMERI (0x3c68) ++#define P_ISA_TIMERI (volatile unsigned int *)((0x3c68 << 2) + 0xffd00000) ++// --------------------------------------------- ++#define ABUF_WR_CTL0 (0x3c70) ++#define P_ABUF_WR_CTL0 (volatile unsigned int *)((0x3c70 << 2) + 0xffd00000) ++ #define ABUF_WR_INT_EN 31 ++ #define ABUF_WR_INT_POS_MSB 30 ++ #define ABUF_WR_INT_POS_LSB 16 ++ #define ABUF_WR_BLK_SIZE_MSB 14 ++ #define ABUF_WR_BLK_SIZE_LSB 0 ++#define ABUF_WR_CTL1 (0x3c71) ++#define P_ABUF_WR_CTL1 (volatile unsigned int *)((0x3c71 << 2) + 0xffd00000) ++ #define ABUF_WR_INT_EN 31 ++ #define ABUF_WR_INT_POS_MSB 30 ++ #define ABUF_WR_INT_POS_LSB 16 ++ #define ABUF_WR_BLK_SIZE_MSB 14 ++ #define ABUF_WR_BLK_SIZE_LSB 0 ++#define ABUF_WR_CTL2 (0x3c72) ++#define P_ABUF_WR_CTL2 (volatile unsigned int *)((0x3c72 << 2) + 0xffd00000) ++ #define ABUF_WR_CUR_FF_CNT_MSB 21 ++ #define ABUF_WR_CUR_FF_CNT_LSB 16 ++ #define ABUF_WR_CUR_BLK_MSB 14 ++ #define ABUF_WR_CUR_BLK_LSB 0 ++#define ABUF_WR_CTL3 (0x3c73) ++#define P_ABUF_WR_CTL3 (volatile unsigned int *)((0x3c73 << 2) + 0xffd00000) ++ #define ABUF_WR_AHB_RST_PLS 3 ++ #define ABUF_WR_FF_CLR_PLS 2 ++ #define ABUF_WR_PLY_RPT_LVL 1 ++ #define ABUF_WR_FF_PAUSE_LVL 0 ++#define ABUF_RD_CTL0 (0x3c74) ++#define P_ABUF_RD_CTL0 (volatile unsigned int *)((0x3c74 << 2) + 0xffd00000) ++#define ABUF_RD_CTL1 (0x3c75) ++#define P_ABUF_RD_CTL1 (volatile unsigned int *)((0x3c75 << 2) + 0xffd00000) ++ #define ABUF_RD_INT_EN 31 ++ #define ABUF_RD_INT_POS_MSB 30 ++ #define ABUF_RD_INT_POS_LSB 16 ++ #define ABUF_RD_BLK_SIZE_MSB 14 ++ #define ABUF_RD_BLK_SIZE_LSB 0 ++#define ABUF_RD_CTL2 (0x3c76) ++#define P_ABUF_RD_CTL2 (volatile unsigned int *)((0x3c76 << 2) + 0xffd00000) ++ #define ABUF_RD_CUR_FF_CNT_MSB 21 ++ #define ABUF_RD_CUR_FF_CNT_LSB 16 ++ #define ABUF_RD_CUR_BLK_MSB 14 ++ #define ABUF_RD_CUR_BLK_LSB 0 ++#define ABUF_RD_CTL3 (0x3c77) ++#define P_ABUF_RD_CTL3 (volatile unsigned int *)((0x3c77 << 2) + 0xffd00000) ++ #define ABUF_RD_PLY_ONCE_PLS 4 ++ #define ABUF_RD_AHB_RST_PLS 3 ++ #define ABUF_RD_FF_CLR_PLS 2 ++ #define ABUF_RD_PLY_RPT_LVL 1 ++ #define ABUF_RD_FF_PAUSE_LVL 0 ++#define ABUF_ARB_CTL0 (0x3c78) ++#define P_ABUF_ARB_CTL0 (volatile unsigned int *)((0x3c78 << 2) + 0xffd00000) ++#define ABUF_FIFO_CTL0 (0x3c79) ++#define P_ABUF_FIFO_CTL0 (volatile unsigned int *)((0x3c79 << 2) + 0xffd00000) ++ #define AIUout_FIFO_THRESHOLD_MSB 11 ++ #define AIUout_FIFO_THRESHOLD_LSB 6 ++ #define AIUin_FIFO_THRESHOLD_MSB 5 ++ #define AIUin_FIFO_THRESHOLD_LSB 0 ++// --------------------------------------------- ++#define AHB_BRIDGE_CNTL_WR (0x3c80) ++#define P_AHB_BRIDGE_CNTL_WR (volatile unsigned int *)((0x3c80 << 2) + 0xffd00000) ++#define AHB_BRIDGE_REMAP0 (0x3c81) ++#define P_AHB_BRIDGE_REMAP0 (volatile unsigned int *)((0x3c81 << 2) + 0xffd00000) ++#define AHB_BRIDGE_REMAP1 (0x3c82) ++#define P_AHB_BRIDGE_REMAP1 (volatile unsigned int *)((0x3c82 << 2) + 0xffd00000) ++#define AHB_BRIDGE_REMAP2 (0x3c83) ++#define P_AHB_BRIDGE_REMAP2 (volatile unsigned int *)((0x3c83 << 2) + 0xffd00000) ++#define AHB_BRIDGE_REMAP3 (0x3c84) ++#define P_AHB_BRIDGE_REMAP3 (volatile unsigned int *)((0x3c84 << 2) + 0xffd00000) ++#define AHB_BRIDGE_CNTL_REG1 (0x3c85) ++#define P_AHB_BRIDGE_CNTL_REG1 (volatile unsigned int *)((0x3c85 << 2) + 0xffd00000) ++#define AHB_BRIDGE_CNTL_REG2 (0x3c86) ++#define P_AHB_BRIDGE_CNTL_REG2 (volatile unsigned int *)((0x3c86 << 2) + 0xffd00000) ++// --------------------------------------------- ++// ---------------------------------------------- ++// `define SYS_CPU_0_IRQ_IN0_INTR_STAT 8'h90 ++// `define SYS_CPU_0_IRQ_IN0_INTR_STAT_CLR 8'h91 ++// `define SYS_CPU_0_IRQ_IN0_INTR_MASK 8'h92 ++// `define SYS_CPU_0_IRQ_IN0_INTR_FIRQ_SEL 8'h93 ++// `define SYS_CPU_0_IRQ_IN1_INTR_STAT 8'h94 ++// `define SYS_CPU_0_IRQ_IN1_INTR_STAT_CLR 8'h95 ++// `define SYS_CPU_0_IRQ_IN1_INTR_MASK 8'h96 ++// `define SYS_CPU_0_IRQ_IN1_INTR_FIRQ_SEL 8'h97 ++// `define SYS_CPU_0_IRQ_IN2_INTR_STAT 8'h98 ++// `define SYS_CPU_0_IRQ_IN2_INTR_STAT_CLR 8'h99 ++// `define SYS_CPU_0_IRQ_IN2_INTR_MASK 8'h9a ++// `define SYS_CPU_0_IRQ_IN2_INTR_FIRQ_SEL 8'h9b ++// `define SYS_CPU_0_IRQ_IN3_INTR_STAT 8'h9c ++// `define SYS_CPU_0_IRQ_IN3_INTR_STAT_CLR 8'h9d ++// `define SYS_CPU_0_IRQ_IN3_INTR_MASK 8'h9e ++// `define SYS_CPU_0_IRQ_IN3_INTR_FIRQ_SEL 8'h9f ++// ---------------------------------------------- ++// `define SYS_CPU_1_IRQ_IN0_INTR_STAT 8'ha0 ++// `define SYS_CPU_1_IRQ_IN0_INTR_STAT_CLR 8'ha1 ++// `define SYS_CPU_1_IRQ_IN0_INTR_MASK 8'ha2 ++// `define SYS_CPU_1_IRQ_IN0_INTR_FIRQ_SEL 8'ha3 ++// ++// `define SYS_CPU_1_IRQ_IN1_INTR_STAT 8'ha4 ++// `define SYS_CPU_1_IRQ_IN1_INTR_STAT_CLR 8'ha5 ++// `define SYS_CPU_1_IRQ_IN1_INTR_MASK 8'ha6 ++// `define SYS_CPU_1_IRQ_IN1_INTR_FIRQ_SEL 8'ha7 ++// ++// `define SYS_CPU_1_IRQ_IN2_INTR_STAT 8'ha8 ++// `define SYS_CPU_1_IRQ_IN2_INTR_STAT_CLR 8'ha9 ++// `define SYS_CPU_1_IRQ_IN2_INTR_MASK 8'haa ++// `define SYS_CPU_1_IRQ_IN2_INTR_FIRQ_SEL 8'hab ++// ++// `define SYS_CPU_1_IRQ_IN3_INTR_STAT 8'hac ++// `define SYS_CPU_1_IRQ_IN3_INTR_STAT_CLR 8'had ++// `define SYS_CPU_1_IRQ_IN3_INTR_MASK 8'hae ++// `define SYS_CPU_1_IRQ_IN3_INTR_FIRQ_SEL 8'haf ++// ---------------------------------------------- ++// `define MEDIA_CPU_IRQ_IN4_INTR_STAT 8'hb0 ++// `define MEDIA_CPU_IRQ_IN4_INTR_STAT_CLR 8'hb1 ++// `define MEDIA_CPU_IRQ_IN4_INTR_MASK 8'hb2 ++// `define MEDIA_CPU_IRQ_IN4_INTR_FIRQ_SEL 8'hb3 ++// `define SYS_CPU_0_IRQ_IN4_INTR_STAT 8'hb4 ++// `define SYS_CPU_0_IRQ_IN4_INTR_STAT_CLR 8'hb5 ++// `define SYS_CPU_0_IRQ_IN4_INTR_MASK 8'hb6 ++// `define SYS_CPU_0_IRQ_IN4_INTR_FIRQ_SEL 8'hb7 ++// `define SYS_CPU_1_IRQ_IN4_INTR_STAT 8'hb8 ++// `define SYS_CPU_1_IRQ_IN4_INTR_STAT_CLR 8'hb9 ++// `define SYS_CPU_1_IRQ_IN4_INTR_MASK 8'hba ++// `define SYS_CPU_1_IRQ_IN4_INTR_FIRQ_SEL 8'hbb ++// `define SYS_CPU_2_IRQ_IN4_INTR_STAT 8'hbc ++// `define SYS_CPU_2_IRQ_IN4_INTR_STAT_CLR 8'hbd ++// `define SYS_CPU_2_IRQ_IN4_INTR_MASK 8'hbe ++// `define SYS_CPU_2_IRQ_IN4_INTR_FIRQ_SEL 8'hbf ++// ---------------------------------------------- ++// `define SYS_CPU_2_IRQ_IN0_INTR_STAT 8'hc0 ++// `define SYS_CPU_2_IRQ_IN0_INTR_STAT_CLR 8'hc1 ++// `define SYS_CPU_2_IRQ_IN0_INTR_MASK 8'hc2 ++// `define SYS_CPU_2_IRQ_IN0_INTR_FIRQ_SEL 8'hc3 ++// `define SYS_CPU_2_IRQ_IN1_INTR_STAT 8'hc4 ++// `define SYS_CPU_2_IRQ_IN1_INTR_STAT_CLR 8'hc5 ++// `define SYS_CPU_2_IRQ_IN1_INTR_MASK 8'hc6 ++// `define SYS_CPU_2_IRQ_IN1_INTR_FIRQ_SEL 8'hc7 ++// `define SYS_CPU_2_IRQ_IN2_INTR_STAT 8'hc8 ++// `define SYS_CPU_2_IRQ_IN2_INTR_STAT_CLR 8'hc9 ++// `define SYS_CPU_2_IRQ_IN2_INTR_MASK 8'hca ++// `define SYS_CPU_2_IRQ_IN2_INTR_FIRQ_SEL 8'hcb ++// `define SYS_CPU_2_IRQ_IN3_INTR_STAT 8'hcc ++// `define SYS_CPU_2_IRQ_IN3_INTR_STAT_CLR 8'hcd ++// `define SYS_CPU_2_IRQ_IN3_INTR_MASK 8'hce ++// `define SYS_CPU_2_IRQ_IN3_INTR_FIRQ_SEL 8'hcf ++// ---------------------------------------------- ++// `define SYS_CPU_3_IRQ_IN0_INTR_STAT 8'hd0 ++// `define SYS_CPU_3_IRQ_IN0_INTR_STAT_CLR 8'hd1 ++// `define SYS_CPU_3_IRQ_IN0_INTR_MASK 8'hd2 ++// `define SYS_CPU_3_IRQ_IN0_INTR_FIRQ_SEL 8'hd3 ++// `define SYS_CPU_3_IRQ_IN1_INTR_STAT 8'hd4 ++// `define SYS_CPU_3_IRQ_IN1_INTR_STAT_CLR 8'hd5 ++// `define SYS_CPU_3_IRQ_IN1_INTR_MASK 8'hd6 ++// `define SYS_CPU_3_IRQ_IN1_INTR_FIRQ_SEL 8'hd7 ++// `define SYS_CPU_3_IRQ_IN2_INTR_STAT 8'hd8 ++// `define SYS_CPU_3_IRQ_IN2_INTR_STAT_CLR 8'hd9 ++// `define SYS_CPU_3_IRQ_IN2_INTR_MASK 8'hda ++// `define SYS_CPU_3_IRQ_IN2_INTR_FIRQ_SEL 8'hdb ++// `define SYS_CPU_3_IRQ_IN3_INTR_STAT 8'hdc ++// `define SYS_CPU_3_IRQ_IN3_INTR_STAT_CLR 8'hdd ++// `define SYS_CPU_3_IRQ_IN3_INTR_MASK 8'hde ++// `define SYS_CPU_3_IRQ_IN3_INTR_FIRQ_SEL 8'hdf ++// ---------------------------------------------- ++// `define SYS_CPU_3_IRQ_IN4_INTR_STAT 8'he0 ++// `define SYS_CPU_3_IRQ_IN4_INTR_STAT_CLR 8'he1 ++// `define SYS_CPU_3_IRQ_IN4_INTR_MASK 8'he2 ++// `define SYS_CPU_3_IRQ_IN4_INTR_FIRQ_SEL 8'he3 ++// `define MEDIA_CPU_IRQ_IN5_INTR_STAT 8'he4 ++// `define MEDIA_CPU_IRQ_IN5_INTR_STAT_CLR 8'he5 ++// `define MEDIA_CPU_IRQ_IN5_INTR_MASK 8'he6 ++// `define MEDIA_CPU_IRQ_IN5_INTR_FIRQ_SEL 8'he7 ++// `define SYS_CPU_0_IRQ_IN5_INTR_STAT 8'he8 ++// `define SYS_CPU_0_IRQ_IN5_INTR_STAT_CLR 8'he9 ++// `define SYS_CPU_0_IRQ_IN5_INTR_MASK 8'hea ++// `define SYS_CPU_0_IRQ_IN5_INTR_FIRQ_SEL 8'heb ++// ++// Closing file: isa_reg.h ++// ++//`include "bt656_reg.h" ++//`include "pdm_reg.h" ++//======================================================================== ++// Global Control Registers (12'h000 - 12'h0ff) ++// ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: RESET_CBUS_BASE = 0x04 ++// ----------------------------------------------- ++#define VERSION_CTRL (0x0400) ++#define P_VERSION_CTRL (volatile unsigned int *)((0x0400 << 2) + 0xffd00000) ++#define RESET0_REGISTER (0x0401) ++#define P_RESET0_REGISTER (volatile unsigned int *)((0x0401 << 2) + 0xffd00000) ++#define RESET1_REGISTER (0x0402) ++#define P_RESET1_REGISTER (volatile unsigned int *)((0x0402 << 2) + 0xffd00000) ++#define RESET2_REGISTER (0x0403) ++#define P_RESET2_REGISTER (volatile unsigned int *)((0x0403 << 2) + 0xffd00000) ++#define RESET3_REGISTER (0x0404) ++#define P_RESET3_REGISTER (volatile unsigned int *)((0x0404 << 2) + 0xffd00000) ++#define RESET4_REGISTER (0x0405) ++#define P_RESET4_REGISTER (volatile unsigned int *)((0x0405 << 2) + 0xffd00000) ++#define RESET5_REGISTER (0x0406) ++#define P_RESET5_REGISTER (volatile unsigned int *)((0x0406 << 2) + 0xffd00000) ++#define RESET6_REGISTER (0x0407) ++#define P_RESET6_REGISTER (volatile unsigned int *)((0x0407 << 2) + 0xffd00000) ++#define RESET7_REGISTER (0x0408) ++#define P_RESET7_REGISTER (volatile unsigned int *)((0x0408 << 2) + 0xffd00000) ++#define RESET0_MASK (0x0410) ++#define P_RESET0_MASK (volatile unsigned int *)((0x0410 << 2) + 0xffd00000) ++#define RESET1_MASK (0x0411) ++#define P_RESET1_MASK (volatile unsigned int *)((0x0411 << 2) + 0xffd00000) ++#define RESET2_MASK (0x0412) ++#define P_RESET2_MASK (volatile unsigned int *)((0x0412 << 2) + 0xffd00000) ++#define RESET3_MASK (0x0413) ++#define P_RESET3_MASK (volatile unsigned int *)((0x0413 << 2) + 0xffd00000) ++#define RESET4_MASK (0x0414) ++#define P_RESET4_MASK (volatile unsigned int *)((0x0414 << 2) + 0xffd00000) ++#define RESET5_MASK (0x0415) ++#define P_RESET5_MASK (volatile unsigned int *)((0x0415 << 2) + 0xffd00000) ++#define RESET6_MASK (0x0416) ++#define P_RESET6_MASK (volatile unsigned int *)((0x0416 << 2) + 0xffd00000) ++#define CRT_MASK (0x0417) ++#define P_CRT_MASK (volatile unsigned int *)((0x0417 << 2) + 0xffd00000) ++#define RESET7_MASK (0x0418) ++#define P_RESET7_MASK (volatile unsigned int *)((0x0418 << 2) + 0xffd00000) ++#define RESET0_LEVEL (0x0420) ++#define P_RESET0_LEVEL (volatile unsigned int *)((0x0420 << 2) + 0xffd00000) ++#define RESET1_LEVEL (0x0421) ++#define P_RESET1_LEVEL (volatile unsigned int *)((0x0421 << 2) + 0xffd00000) ++#define RESET2_LEVEL (0x0422) ++#define P_RESET2_LEVEL (volatile unsigned int *)((0x0422 << 2) + 0xffd00000) ++#define RESET3_LEVEL (0x0423) ++#define P_RESET3_LEVEL (volatile unsigned int *)((0x0423 << 2) + 0xffd00000) ++#define RESET4_LEVEL (0x0424) ++#define P_RESET4_LEVEL (volatile unsigned int *)((0x0424 << 2) + 0xffd00000) ++#define RESET5_LEVEL (0x0425) ++#define P_RESET5_LEVEL (volatile unsigned int *)((0x0425 << 2) + 0xffd00000) ++#define RESET6_LEVEL (0x0426) ++#define P_RESET6_LEVEL (volatile unsigned int *)((0x0426 << 2) + 0xffd00000) ++#define RESET7_LEVEL (0x0427) ++#define P_RESET7_LEVEL (volatile unsigned int *)((0x0427 << 2) + 0xffd00000) ++//====================================== ++// Reset Register Bits ++// ++//====================================== ++ #define HIU_RESET 0x0001 ++ #define VLD_RESET 0x0002 ++ #define IQIDCT_RESET 0x0004 ++ #define MC_RESET 0x0008 ++ #define DCU_RESET 0x0010 ++ #define VIU_RESET 0x0020 ++ #define AIU_RESET 0x0040 ++ #define CPU_RESET 0x0080 ++ #define AC3_RESET 0x0100 ++ #define MPEG_RESET 0x0200 ++//----------------------------------------------------------- ++// PARSER ++//----------------------------------------------------------- ++// ----------------------------------------------- ++// CBUS_BASE: PARSER_CBUS_BASE = 0x38 ++// ----------------------------------------------- ++// bit 31:8 -- es_pack_size ++// bit 7:6 -- es_type 00-Video, 01-Audio, 10-Subtitle ++// bit 5 -- es_write ++// bit 4 -- es_passthrough ++// bit 3 -- insert_before_es_write ++// bit 2 -- discard_cmd ++// bit 1 -- search_cmd ++// bit 0 -- Parser Busy ++#define PARSER_CONTROL (0x3860) ++#define P_PARSER_CONTROL (volatile unsigned int *)((0x3860 << 2) + 0xffd00000) ++// Write ++// bit 31:0 begin address for parser fetch ++// Read ++// 32 bit current fetch address ++#define PARSER_FETCH_ADDR (0x3861) ++#define P_PARSER_FETCH_ADDR (volatile unsigned int *)((0x3861 << 2) + 0xffd00000) ++// Write ++// bit 31 circle buffer indicator ++// bit 30 check_buffer_stop_addr ++// bit 29:27 fetch endian ++// bit 26:0 buffer size ( Bytes ) ++// Special command: ++// when bit 26:0 == 27'h0 ++// then bit 29 -- stream_passthrough_enable ++// bit 28:27 -- stream_passthrough_type ++// Read ++// 6:5 cmd_rd_ptr ++// 4:3 cmd_wr_ptr ++// 2:0 cmd_number ++#define PARSER_FETCH_CMD (0x3862) ++#define P_PARSER_FETCH_CMD (volatile unsigned int *)((0x3862 << 2) + 0xffd00000) ++// 31:0 stop_fetch_addr ++#define PARSER_FETCH_STOP_ADDR (0x3863) ++#define P_PARSER_FETCH_STOP_ADDR (volatile unsigned int *)((0x3863 << 2) + 0xffd00000) ++// 31:0 stop_fetch_addr - current_write_addr // read only ++#define PARSER_FETCH_LEVEL (0x3864) ++#define P_PARSER_FETCH_LEVEL (volatile unsigned int *)((0x3864 << 2) + 0xffd00000) ++// bit 31 - fetch_dma_urgent ++// bit 30 - stream_dma_urgent ++// bit 29 - force_pfifo_ren ++// bit 28 - pfifo_peak_enable ++// bit 27 - enable_free_clk_parser_reg ++// bit 26 - ++// bit 25:24 - parser_src_sel (00 - fetch, 01 - aux1, 10 - aux2 11 - aux3) ++// bit 23:16 - pfifo_empty_count ++// bit 15:12 - max_es_write_cycle (x16x64bits) ++// 11:10 - start code width ( 00-8bits, 01-16bits, 10-24bits, 11-32bits ) ++// 9:8 - pfifo data access width ( 00-8bits, 01-16bits, 10-24bits, 11-32bits ) ++// 7:0 - empty room for fetch data ( max_fetch_cycle ) x64 bits ++#define PARSER_CONFIG (0x3865) ++#define P_PARSER_CONFIG (volatile unsigned int *)((0x3865 << 2) + 0xffd00000) ++// bit 24:16 -- pfifo_level ++// bit 9:0 -- point to byte address ++#define PFIFO_WR_PTR (0x3866) ++#define P_PFIFO_WR_PTR (volatile unsigned int *)((0x3866 << 2) + 0xffd00000) ++// bit 9:0 -- point to byte address ++#define PFIFO_RD_PTR (0x3867) ++#define P_PFIFO_RD_PTR (volatile unsigned int *)((0x3867 << 2) + 0xffd00000) ++// bit 31:0 -- 8/16/24/32 bits data acording to pfifo_data_width ++#define PFIFO_DATA (0x3868) ++#define P_PFIFO_DATA (volatile unsigned int *)((0x3868 << 2) + 0xffd00000) ++// bit 31:0 -- parser search pattern ++#define PARSER_SEARCH_PATTERN (0x3869) ++#define P_PARSER_SEARCH_PATTERN (volatile unsigned int *)((0x3869 << 2) + 0xffd00000) ++// bit 31:0 -- parser search mask ( 0 - disable bit match test ) ++#define PARSER_SEARCH_MASK (0x386a) ++#define P_PARSER_SEARCH_MASK (volatile unsigned int *)((0x386a << 2) + 0xffd00000) ++// bit 31:16 -- parser_int_disable_count ++// bit 15:8 -- Parser interrupt enable for host cpu ++// bit 7:0 -- Parser interrupt enable for Amrisc ++#define PARSER_INT_ENABLE (0x386b) ++#define P_PARSER_INT_ENABLE (volatile unsigned int *)((0x386b << 2) + 0xffd00000) ++// Bit 7 -- fetch_cmd_finished ++// Bit 6:5 -- reserved ++// Bit 4 -- parse finished ++// Bit 3 -- discard finished ++// Bit 2 -- insert zero finished ++// Bit 1 -- Action Finished Except Search Start Code ++// Bit 0 -- Search match interrupt (StartCode found) ++// Read 7:0 int status ++// Write will clear (bit based) ++#define PARSER_INT_STATUS (0x386c) ++#define P_PARSER_INT_STATUS (volatile unsigned int *)((0x386c << 2) + 0xffd00000) ++// 15 - SCR_32_READ_OUT (Read Only) ++// 14 - SCR_32_data_valid ++// 13 - SCR_32_data ++// 12 - SCR_count_en ++// 11:0 - SCR90K_DIV ++#define PARSER_SCR_CTL (0x386d) ++#define P_PARSER_SCR_CTL (volatile unsigned int *)((0x386d << 2) + 0xffd00000) ++// bit 31:0 SCR value ++#define PARSER_SCR (0x386e) ++#define P_PARSER_SCR (volatile unsigned int *)((0x386e << 2) + 0xffd00000) ++// bit 31:24 -- insert_loop_number ++// bit 23:21 -- ++// bit 20:16 -- insert_byte_number ++// bit 15:0 -- discard number ++#define PARSER_PARAMETER (0x386f) ++#define P_PARSER_PARAMETER (volatile unsigned int *)((0x386f << 2) + 0xffd00000) ++// bit 31:0 -- insert data // write only ++// write to PARSER_CONTROL will reset the write position ++// continous write to this address can write upto 16 bytes ++#define PARSER_INSERT_DATA (0x3870) ++#define P_PARSER_INSERT_DATA (volatile unsigned int *)((0x3870 << 2) + 0xffd00000) ++// Bit 31:24 -- Reserved Stream_ID ++// Bit 23:16 -- Sub Stream_ID ++// Bit 15:8 -- Audio Stream_ID ++// Bit 7:0 -- Video Stream_ID ++#define VAS_STREAM_ID (0x3871) ++#define P_VAS_STREAM_ID (volatile unsigned int *)((0x3871 << 2) + 0xffd00000) ++// Bit 31:0 -- VIDEO_DTS ++#define VIDEO_DTS (0x3872) ++#define P_VIDEO_DTS (volatile unsigned int *)((0x3872 << 2) + 0xffd00000) ++// Bit 31:0 -- VIDEO_PTS ++#define VIDEO_PTS (0x3873) ++#define P_VIDEO_PTS (volatile unsigned int *)((0x3873 << 2) + 0xffd00000) ++// Bit 31:0 -- VIDEO_PTS_DTS_WR_PTR ++#define VIDEO_PTS_DTS_WR_PTR (0x3874) ++#define P_VIDEO_PTS_DTS_WR_PTR (volatile unsigned int *)((0x3874 << 2) + 0xffd00000) ++// Bit 31:0 -- AUDIO_PTS ++#define AUDIO_PTS (0x3875) ++#define P_AUDIO_PTS (volatile unsigned int *)((0x3875 << 2) + 0xffd00000) ++// Bit 31:0 -- AUDIO_PTS_WR_PTR ++#define AUDIO_PTS_WR_PTR (0x3876) ++#define P_AUDIO_PTS_WR_PTR (volatile unsigned int *)((0x3876 << 2) + 0xffd00000) ++// bit 31:20 -- stream_es_count ( Read Only) ++// bit 19 -- req_pending ( parser ddr_A_fifo ) (Read Only) ++// bit 18 -- stream_es_passthrough_enable ++// bit 17:16 -- stream_es_passthrough_type ++// bit 15:13 -- VIDEO2 Ees_write Endian ++// bit 12 -- VIDEO2 using manual read point ++// bit 11:9 -- SUB Ees_write Endian ++// bit 8 -- SUB using manual read point ++// bit 7:5 -- AUDIO Ees_write Endian ++// bit 4 -- AUDIO using manual read point ++// bit 3:1 -- VIDEO Ees_write Endian ++// bit 0 -- VIDEO using manual read point ++#define PARSER_ES_CONTROL (0x3877) ++#define P_PARSER_ES_CONTROL (volatile unsigned int *)((0x3877 << 2) + 0xffd00000) ++// Bit 31:0 PFIFO_MONITOR ++#define PFIFO_MONITOR (0x3878) ++#define P_PFIFO_MONITOR (volatile unsigned int *)((0x3878 << 2) + 0xffd00000) ++// -------------------------------------------- ++// PARSER_VIDEO DDR Interface ++// -------------------------------------------- ++// The PARSER_VIDEO start pointer into DDR memory is a 32-bit number ++// The Start pointer will automatically be truncated to land on ++// an 8-byte boundary. That is, bits [2:0] = 0; ++#define PARSER_VIDEO_START_PTR (0x3880) ++#define P_PARSER_VIDEO_START_PTR (volatile unsigned int *)((0x3880 << 2) + 0xffd00000) ++#define PARSER_VIDEO_END_PTR (0x3881) ++#define P_PARSER_VIDEO_END_PTR (volatile unsigned int *)((0x3881 << 2) + 0xffd00000) ++// -------------------------------------------- ++// PARSER_VIDEO Buffer Level Manager ++// -------------------------------------------- ++#define PARSER_VIDEO_WP (0x3882) ++#define P_PARSER_VIDEO_WP (volatile unsigned int *)((0x3882 << 2) + 0xffd00000) ++#define PARSER_VIDEO_RP (0x3883) ++#define P_PARSER_VIDEO_RP (volatile unsigned int *)((0x3883 << 2) + 0xffd00000) ++#define PARSER_VIDEO_HOLE (0x3884) ++#define P_PARSER_VIDEO_HOLE (volatile unsigned int *)((0x3884 << 2) + 0xffd00000) ++// -------------------------------------------- ++// PARSER_AUDIO DDR Interface ++// -------------------------------------------- ++// The PARSER_AUDIO start pointer into DDR memory is a 32-bit number ++// The Start pointer will automatically be truncated to land on ++// an 8-byte boundary. That is, bits [2:0] = 0; ++#define PARSER_AUDIO_START_PTR (0x3885) ++#define P_PARSER_AUDIO_START_PTR (volatile unsigned int *)((0x3885 << 2) + 0xffd00000) ++#define PARSER_AUDIO_END_PTR (0x3886) ++#define P_PARSER_AUDIO_END_PTR (volatile unsigned int *)((0x3886 << 2) + 0xffd00000) ++// -------------------------------------------- ++// PARSER_AUDIO Buffer Level Manager ++// -------------------------------------------- ++#define PARSER_AUDIO_WP (0x3887) ++#define P_PARSER_AUDIO_WP (volatile unsigned int *)((0x3887 << 2) + 0xffd00000) ++#define PARSER_AUDIO_RP (0x3888) ++#define P_PARSER_AUDIO_RP (volatile unsigned int *)((0x3888 << 2) + 0xffd00000) ++#define PARSER_AUDIO_HOLE (0x3889) ++#define P_PARSER_AUDIO_HOLE (volatile unsigned int *)((0x3889 << 2) + 0xffd00000) ++// -------------------------------------------- ++// PARSER_SUB DDR Interface ++// -------------------------------------------- ++// The PARSER_SUB start pointer into DDR memory is a 32-bit number ++// The Start pointer will automatically be truncated to land on ++// an 8-byte boundary. That is, bits [2:0] = 0; ++#define PARSER_SUB_START_PTR (0x388a) ++#define P_PARSER_SUB_START_PTR (volatile unsigned int *)((0x388a << 2) + 0xffd00000) ++#define PARSER_SUB_END_PTR (0x388b) ++#define P_PARSER_SUB_END_PTR (volatile unsigned int *)((0x388b << 2) + 0xffd00000) ++// -------------------------------------------- ++// PARSER_SUB Buffer Level Manager ++// -------------------------------------------- ++#define PARSER_SUB_WP (0x388c) ++#define P_PARSER_SUB_WP (volatile unsigned int *)((0x388c << 2) + 0xffd00000) ++#define PARSER_SUB_RP (0x388d) ++#define P_PARSER_SUB_RP (volatile unsigned int *)((0x388d << 2) + 0xffd00000) ++#define PARSER_SUB_HOLE (0x388e) ++#define P_PARSER_SUB_HOLE (volatile unsigned int *)((0x388e << 2) + 0xffd00000) ++// Bit[31] dma_busy ++// Bit[30] cur_fetch_or_es_write ++// Bit[29:28] reserved ++// Bit[27:24] fetch_status ++// Bit[23:0] buffer_cycles_left ++#define PARSER_FETCH_INFO (0x388f) ++#define P_PARSER_FETCH_INFO (volatile unsigned int *)((0x388f << 2) + 0xffd00000) ++// Bit[31:28] ctl_status ++// Bit[27:24] insert_byte_offset ++// Bit[23:0] es_pack_left_cycle ++#define PARSER_STATUS (0x3890) ++#define P_PARSER_STATUS (volatile unsigned int *)((0x3890 << 2) + 0xffd00000) ++// Bit [31:16] AUDIO_wrap_count ++// Bit [15:0] VIDEO_wrap_count ++#define PARSER_AV_WRAP_COUNT (0x3891) ++#define P_PARSER_AV_WRAP_COUNT (volatile unsigned int *)((0x3891 << 2) + 0xffd00000) ++// bit[29:24] A_brst_num_parser ++// bit[21:16] A_id_parser ++// bit[11:0] wrrsp_count_parser ++#define WRRSP_PARSER (0x3892) ++#define P_WRRSP_PARSER (volatile unsigned int *)((0x3892 << 2) + 0xffd00000) ++// `define CSS_cmd 12'h200 // address of css command and indirect register ++// `define CSS_cntl 12'h201 // css control register ++// `define CSS_data 12'h202 // indirect register ++// `define CSS_id1_data 12'h203 // ID data for the first and second bytes ++// `define CSS_id2_data 12'h204 // ID data for the third and fourth bytes ++//CPPM registers ++// `define CPPM_IFIFO_CTRL 12'h210 //CPPM input FIFO control ++// `define CPPM_C2BC_KEY 12'h211 //CPPM C2 Block Cipher Key register ++// `define CPPM_C2BC_DIN 12'h212 //CPPM C2 Block Cipher data input register ++// `define CPPM_C2BC_DOUT 12'h213 //CPPM C2 Block Cipher data result register ++// `define CPPM_CMD 12'h214 //CPPM command and control register ++// `define CPPM_CTRL_STATUS 12'h215 //CPPM control status, mainly for debug ++// `define CPPM_IFIFO_DATA 12'h216 //CPPM input FIFO data pop port, just for debug ++// -------------------------------------------- ++// PARSER_VIDEO2 DDR Interface ++// -------------------------------------------- ++// The PARSER_VIDEO2 start pointer into DDR memory is a 32-bit number ++// The Start pointer will automatically be truncated to land on ++// an 8-byte boundary. That is, bits [2:0] = 0; ++#define PARSER_VIDEO2_START_PTR (0x3893) ++#define P_PARSER_VIDEO2_START_PTR (volatile unsigned int *)((0x3893 << 2) + 0xffd00000) ++#define PARSER_VIDEO2_END_PTR (0x3894) ++#define P_PARSER_VIDEO2_END_PTR (volatile unsigned int *)((0x3894 << 2) + 0xffd00000) ++// -------------------------------------------- ++// PARSER_VIDEO2 Buffer Level Manager ++// -------------------------------------------- ++#define PARSER_VIDEO2_WP (0x3895) ++#define P_PARSER_VIDEO2_WP (volatile unsigned int *)((0x3895 << 2) + 0xffd00000) ++#define PARSER_VIDEO2_RP (0x3896) ++#define P_PARSER_VIDEO2_RP (volatile unsigned int *)((0x3896 << 2) + 0xffd00000) ++#define PARSER_VIDEO2_HOLE (0x3897) ++#define P_PARSER_VIDEO2_HOLE (volatile unsigned int *)((0x3897 << 2) + 0xffd00000) ++// Bit [31:16] AUDIO_wrap_count ++// Bit [15:0] VIDEO2_wrap_count ++#define PARSER_AV2_WRAP_COUNT (0x3898) ++#define P_PARSER_AV2_WRAP_COUNT (volatile unsigned int *)((0x3898 << 2) + 0xffd00000) ++// DDR registers ++//`define USE_DDR2 ++//======================================================================== ++// DVIN Registers (12'h2e0 - 12'h2ef) ++// ++//======================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DVIN_CBUS_BASE = 0x08 ++// ----------------------------------------------- ++// Bit 31:12 Rsrv ++// Bit 11:10 RW, vs_hs_tim_ctrl: Controls which edge of HS/VS the active pixel/line is related: ++// bit[0]=0: start of active pixel is counted from the rising edge of HS; ++// bit[0]=1: start of active pixel is counted from the falling edge of HS; ++// bit[1]=0: start of active line is counted from the rising edge of VS; ++// bit[1]=1: start of active line is counted from the falling edge of VS. ++// Bit 9 RW, sample_clk_neg: 1=invert input dvin_clk ++// Bit 8: 7 RW, mode_422to444: 0=No convertion; 1=Rsrv; 2=Convert 422 to 444, use previous C value; 3=Convert 422 to 444, use average C value. ++// Bit 6: 5 RW, de_mode: 0x=ignore input DE signal, use internal detection to to determine active pixel; ++// 10=during active pixel, if DE is low, replace input data with the last good data before DE goes low; ++// 11=Active pixel is determined by DE, no internal detection. ++// Bit 4 RW, ext_field_sel: 1=Select external input Field, 0=Use internal detected Field. ++// Bit 3 RW, field_pol_inv: set to 1 if input Field is low active and ext_field_sel=1 ++// Bit 2 RW, de_pol_inv: set to 1 if input DE is low active ++// Bit 1 RW, vs_pol_inv: set to 1 if input VS is low active ++// Bit 0 RW, hs_pol_inv: set to 1 if input HS is low active ++#define DVIN_FRONT_END_CTRL (0x08e0) ++#define P_DVIN_FRONT_END_CTRL (volatile unsigned int *)((0x08e0 << 2) + 0xffd00000) ++// Bit 31:28 Reserved ++// Bit 27:16 RW, hs_lead_vs_odd_max: Criteria for HW detecting odd/even Field internally: max clock cycles allowed for HS ++// active edge to lead before VS active edge, in odd field. Failing it the field is even. ++// Bit 15:12 Reserved ++// Bit 11: 0 RW, hs_lead_vs_odd_min: Criteria for HW detecting odd/even Field internally -- min clock cycles allowed for HS ++// active edge to lead before VS active edge, in odd field. Failing it the field is even. ++#define DVIN_HS_LEAD_VS_ODD (0x08e1) ++#define P_DVIN_HS_LEAD_VS_ODD (volatile unsigned int *)((0x08e1 << 2) + 0xffd00000) ++// Bit 31:28 Reserved ++// Bit 27:16 RW, active_start_pix_fo ++// Bit 15:12 Reserved ++// Bit 11: 0 RW, active_start_pix_fe ++#define DVIN_ACTIVE_START_PIX (0x08e2) ++#define P_DVIN_ACTIVE_START_PIX (volatile unsigned int *)((0x08e2 << 2) + 0xffd00000) ++// Bit 31:28 Reserved ++// Bit 27:16 RW, active_start_line_fo ++// Bit 15:12 Reserved ++// Bit 11: 0 RW, active_start_line_fe ++#define DVIN_ACTIVE_START_LINE (0x08e3) ++#define P_DVIN_ACTIVE_START_LINE (volatile unsigned int *)((0x08e3 << 2) + 0xffd00000) ++// Bit 31:28 Reserved ++// Bit 27:16 RW, field_height_m1 ++// Bit 15:12 Reserved ++// Bit 11: 0 RW, line_width_m1 ++#define DVIN_DISPLAY_SIZE (0x08e4) ++#define P_DVIN_DISPLAY_SIZE (volatile unsigned int *)((0x08e4 << 2) + 0xffd00000) ++// Bit 31 Rsrv ++// Bit 30 R, vs_in_polarity: 0=active high; 1=active low. ++// Bit 29 R, hs_in_polarity: 0=active high; 1=active low. ++// Bit 28 R, field_odd ++// Bit 27:16 R, hs_lead_vs_cnt ++// Bit 15: 4 Rsrv ++// Bit 3: 1 RW, data_comp_map: Re-map input data to form YCbCr. ++// 0=YCbCr is {[29:20], [19:10], [ 9: 0]}; ++// 1=YCbCr is {[29:20], [ 9: 0], [19:10]}; ++// 2=YCbCr is {[ 9: 0], [29:20], [19:10]}; ++// 3=YCbCr is {[19:10], [29:20], [ 9: 0]}; ++// 4=YCbCr is {[19:10], [ 9: 0], [29:20]}; ++// 5=YCbCr is {[ 9: 0], [19:10], [29:20]}; ++// 6,7=Rsrv ++// Bit 0 RW, dvin_enable ++#define DVIN_CTRL_STAT (0x08e5) ++#define P_DVIN_CTRL_STAT (volatile unsigned int *)((0x08e5 << 2) + 0xffd00000) ++//======================================================================== ++// DOS registers APB allocation from 32'hd0050000 ++// ++//======================================================================== ++//======================================================================= ++// XIF module ++// `include "xregs.h" ++ #define X_INT_ADR 0x400 ++ #define GPIO_ADR 0x401 ++ #define GPIO_ADR_H8 0x402 ++ #define WFIFO_DEPTH 8 ++ #define WFIFO_PointerWidth 3 ++ #define WFIFO_WORDSIZE 32 ++// MAC module ++// move them to cpu domain. ++//`define CLR_ACC_MAC 12'h410 ++//`define CLR_ACC_MAC2 12'h411 ++//`define ACC_0 12'h412 ++//`define ACC_1 12'h413 ++//`define ACC_2 12'h414 ++//`define ACC_3 12'h415 ++//======================================================================== ++// Audio EQ DRC Interface (15'h1400 - 15'h14ff) ++// ++//======================================================================== ++// ++// Reading file: audio_eq_drc.h ++// ++// ----------------------------------------------- ++// CBUS_BASE: AED_CBUS_BASE = 0x10 ++// ----------------------------------------------- ++ ++/* defined in g12a secure_apb.h */ ++#if 0 ++#define AED_EQ_CH1_COEF00 (0x1000) ++#define P_AED_EQ_CH1_COEF00 (volatile unsigned int *)((0x1000 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF01 (0x1001) ++#define P_AED_EQ_CH1_COEF01 (volatile unsigned int *)((0x1001 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF02 (0x1002) ++#define P_AED_EQ_CH1_COEF02 (volatile unsigned int *)((0x1002 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF03 (0x1003) ++#define P_AED_EQ_CH1_COEF03 (volatile unsigned int *)((0x1003 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF04 (0x1004) ++#define P_AED_EQ_CH1_COEF04 (volatile unsigned int *)((0x1004 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF10 (0x1005) ++#define P_AED_EQ_CH1_COEF10 (volatile unsigned int *)((0x1005 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF11 (0x1006) ++#define P_AED_EQ_CH1_COEF11 (volatile unsigned int *)((0x1006 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF12 (0x1007) ++#define P_AED_EQ_CH1_COEF12 (volatile unsigned int *)((0x1007 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF13 (0x1008) ++#define P_AED_EQ_CH1_COEF13 (volatile unsigned int *)((0x1008 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF14 (0x1009) ++#define P_AED_EQ_CH1_COEF14 (volatile unsigned int *)((0x1009 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF20 (0x100a) ++#define P_AED_EQ_CH1_COEF20 (volatile unsigned int *)((0x100a << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF21 (0x100b) ++#define P_AED_EQ_CH1_COEF21 (volatile unsigned int *)((0x100b << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF22 (0x100c) ++#define P_AED_EQ_CH1_COEF22 (volatile unsigned int *)((0x100c << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF23 (0x100d) ++#define P_AED_EQ_CH1_COEF23 (volatile unsigned int *)((0x100d << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF24 (0x100e) ++#define P_AED_EQ_CH1_COEF24 (volatile unsigned int *)((0x100e << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF30 (0x100f) ++#define P_AED_EQ_CH1_COEF30 (volatile unsigned int *)((0x100f << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF31 (0x1010) ++#define P_AED_EQ_CH1_COEF31 (volatile unsigned int *)((0x1010 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF32 (0x1011) ++#define P_AED_EQ_CH1_COEF32 (volatile unsigned int *)((0x1011 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF33 (0x1012) ++#define P_AED_EQ_CH1_COEF33 (volatile unsigned int *)((0x1012 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF34 (0x1013) ++#define P_AED_EQ_CH1_COEF34 (volatile unsigned int *)((0x1013 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF40 (0x1014) ++#define P_AED_EQ_CH1_COEF40 (volatile unsigned int *)((0x1014 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF41 (0x1015) ++#define P_AED_EQ_CH1_COEF41 (volatile unsigned int *)((0x1015 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF42 (0x1016) ++#define P_AED_EQ_CH1_COEF42 (volatile unsigned int *)((0x1016 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF43 (0x1017) ++#define P_AED_EQ_CH1_COEF43 (volatile unsigned int *)((0x1017 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF44 (0x1018) ++#define P_AED_EQ_CH1_COEF44 (volatile unsigned int *)((0x1018 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF50 (0x1019) ++#define P_AED_EQ_CH1_COEF50 (volatile unsigned int *)((0x1019 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF51 (0x101a) ++#define P_AED_EQ_CH1_COEF51 (volatile unsigned int *)((0x101a << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF52 (0x101b) ++#define P_AED_EQ_CH1_COEF52 (volatile unsigned int *)((0x101b << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF53 (0x101c) ++#define P_AED_EQ_CH1_COEF53 (volatile unsigned int *)((0x101c << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF54 (0x101d) ++#define P_AED_EQ_CH1_COEF54 (volatile unsigned int *)((0x101d << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF60 (0x101e) ++#define P_AED_EQ_CH1_COEF60 (volatile unsigned int *)((0x101e << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF61 (0x101f) ++#define P_AED_EQ_CH1_COEF61 (volatile unsigned int *)((0x101f << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF62 (0x1020) ++#define P_AED_EQ_CH1_COEF62 (volatile unsigned int *)((0x1020 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF63 (0x1021) ++#define P_AED_EQ_CH1_COEF63 (volatile unsigned int *)((0x1021 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF64 (0x1022) ++#define P_AED_EQ_CH1_COEF64 (volatile unsigned int *)((0x1022 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF70 (0x1023) ++#define P_AED_EQ_CH1_COEF70 (volatile unsigned int *)((0x1023 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF71 (0x1024) ++#define P_AED_EQ_CH1_COEF71 (volatile unsigned int *)((0x1024 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF72 (0x1025) ++#define P_AED_EQ_CH1_COEF72 (volatile unsigned int *)((0x1025 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF73 (0x1026) ++#define P_AED_EQ_CH1_COEF73 (volatile unsigned int *)((0x1026 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF74 (0x1027) ++#define P_AED_EQ_CH1_COEF74 (volatile unsigned int *)((0x1027 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF80 (0x1028) ++#define P_AED_EQ_CH1_COEF80 (volatile unsigned int *)((0x1028 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF81 (0x1029) ++#define P_AED_EQ_CH1_COEF81 (volatile unsigned int *)((0x1029 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF82 (0x102a) ++#define P_AED_EQ_CH1_COEF82 (volatile unsigned int *)((0x102a << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF83 (0x102b) ++#define P_AED_EQ_CH1_COEF83 (volatile unsigned int *)((0x102b << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF84 (0x102c) ++#define P_AED_EQ_CH1_COEF84 (volatile unsigned int *)((0x102c << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF90 (0x102d) ++#define P_AED_EQ_CH1_COEF90 (volatile unsigned int *)((0x102d << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF91 (0x102e) ++#define P_AED_EQ_CH1_COEF91 (volatile unsigned int *)((0x102e << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF92 (0x102f) ++#define P_AED_EQ_CH1_COEF92 (volatile unsigned int *)((0x102f << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF93 (0x1030) ++#define P_AED_EQ_CH1_COEF93 (volatile unsigned int *)((0x1030 << 2) + 0xffd00000) ++#define AED_EQ_CH1_COEF94 (0x1031) ++#define P_AED_EQ_CH1_COEF94 (volatile unsigned int *)((0x1031 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF00 (0x1032) ++#define P_AED_EQ_CH2_COEF00 (volatile unsigned int *)((0x1032 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF01 (0x1033) ++#define P_AED_EQ_CH2_COEF01 (volatile unsigned int *)((0x1033 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF02 (0x1034) ++#define P_AED_EQ_CH2_COEF02 (volatile unsigned int *)((0x1034 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF03 (0x1035) ++#define P_AED_EQ_CH2_COEF03 (volatile unsigned int *)((0x1035 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF04 (0x1036) ++#define P_AED_EQ_CH2_COEF04 (volatile unsigned int *)((0x1036 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF10 (0x1037) ++#define P_AED_EQ_CH2_COEF10 (volatile unsigned int *)((0x1037 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF11 (0x1038) ++#define P_AED_EQ_CH2_COEF11 (volatile unsigned int *)((0x1038 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF12 (0x1039) ++#define P_AED_EQ_CH2_COEF12 (volatile unsigned int *)((0x1039 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF13 (0x103a) ++#define P_AED_EQ_CH2_COEF13 (volatile unsigned int *)((0x103a << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF14 (0x103b) ++#define P_AED_EQ_CH2_COEF14 (volatile unsigned int *)((0x103b << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF20 (0x103c) ++#define P_AED_EQ_CH2_COEF20 (volatile unsigned int *)((0x103c << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF21 (0x103d) ++#define P_AED_EQ_CH2_COEF21 (volatile unsigned int *)((0x103d << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF22 (0x103e) ++#define P_AED_EQ_CH2_COEF22 (volatile unsigned int *)((0x103e << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF23 (0x103f) ++#define P_AED_EQ_CH2_COEF23 (volatile unsigned int *)((0x103f << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF24 (0x1040) ++#define P_AED_EQ_CH2_COEF24 (volatile unsigned int *)((0x1040 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF30 (0x1041) ++#define P_AED_EQ_CH2_COEF30 (volatile unsigned int *)((0x1041 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF31 (0x1042) ++#define P_AED_EQ_CH2_COEF31 (volatile unsigned int *)((0x1042 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF32 (0x1043) ++#define P_AED_EQ_CH2_COEF32 (volatile unsigned int *)((0x1043 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF33 (0x1044) ++#define P_AED_EQ_CH2_COEF33 (volatile unsigned int *)((0x1044 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF34 (0x1045) ++#define P_AED_EQ_CH2_COEF34 (volatile unsigned int *)((0x1045 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF40 (0x1046) ++#define P_AED_EQ_CH2_COEF40 (volatile unsigned int *)((0x1046 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF41 (0x1047) ++#define P_AED_EQ_CH2_COEF41 (volatile unsigned int *)((0x1047 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF42 (0x1048) ++#define P_AED_EQ_CH2_COEF42 (volatile unsigned int *)((0x1048 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF43 (0x1049) ++#define P_AED_EQ_CH2_COEF43 (volatile unsigned int *)((0x1049 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF44 (0x104a) ++#define P_AED_EQ_CH2_COEF44 (volatile unsigned int *)((0x104a << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF50 (0x104b) ++#define P_AED_EQ_CH2_COEF50 (volatile unsigned int *)((0x104b << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF51 (0x104c) ++#define P_AED_EQ_CH2_COEF51 (volatile unsigned int *)((0x104c << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF52 (0x104d) ++#define P_AED_EQ_CH2_COEF52 (volatile unsigned int *)((0x104d << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF53 (0x104e) ++#define P_AED_EQ_CH2_COEF53 (volatile unsigned int *)((0x104e << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF54 (0x104f) ++#define P_AED_EQ_CH2_COEF54 (volatile unsigned int *)((0x104f << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF60 (0x1050) ++#define P_AED_EQ_CH2_COEF60 (volatile unsigned int *)((0x1050 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF61 (0x1051) ++#define P_AED_EQ_CH2_COEF61 (volatile unsigned int *)((0x1051 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF62 (0x1052) ++#define P_AED_EQ_CH2_COEF62 (volatile unsigned int *)((0x1052 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF63 (0x1053) ++#define P_AED_EQ_CH2_COEF63 (volatile unsigned int *)((0x1053 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF64 (0x1054) ++#define P_AED_EQ_CH2_COEF64 (volatile unsigned int *)((0x1054 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF70 (0x1055) ++#define P_AED_EQ_CH2_COEF70 (volatile unsigned int *)((0x1055 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF71 (0x1056) ++#define P_AED_EQ_CH2_COEF71 (volatile unsigned int *)((0x1056 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF72 (0x1057) ++#define P_AED_EQ_CH2_COEF72 (volatile unsigned int *)((0x1057 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF73 (0x1058) ++#define P_AED_EQ_CH2_COEF73 (volatile unsigned int *)((0x1058 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF74 (0x1059) ++#define P_AED_EQ_CH2_COEF74 (volatile unsigned int *)((0x1059 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF80 (0x105a) ++#define P_AED_EQ_CH2_COEF80 (volatile unsigned int *)((0x105a << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF81 (0x105b) ++#define P_AED_EQ_CH2_COEF81 (volatile unsigned int *)((0x105b << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF82 (0x105c) ++#define P_AED_EQ_CH2_COEF82 (volatile unsigned int *)((0x105c << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF83 (0x105d) ++#define P_AED_EQ_CH2_COEF83 (volatile unsigned int *)((0x105d << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF84 (0x105e) ++#define P_AED_EQ_CH2_COEF84 (volatile unsigned int *)((0x105e << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF90 (0x105f) ++#define P_AED_EQ_CH2_COEF90 (volatile unsigned int *)((0x105f << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF91 (0x1060) ++#define P_AED_EQ_CH2_COEF91 (volatile unsigned int *)((0x1060 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF92 (0x1061) ++#define P_AED_EQ_CH2_COEF92 (volatile unsigned int *)((0x1061 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF93 (0x1062) ++#define P_AED_EQ_CH2_COEF93 (volatile unsigned int *)((0x1062 << 2) + 0xffd00000) ++#define AED_EQ_CH2_COEF94 (0x1063) ++#define P_AED_EQ_CH2_COEF94 (volatile unsigned int *)((0x1063 << 2) + 0xffd00000) ++#define AED_EQ_EN (0x1064) ++#define P_AED_EQ_EN (volatile unsigned int *)((0x1064 << 2) + 0xffd00000) ++#define AED_EQ_VOLUME (0x1065) ++#define P_AED_EQ_VOLUME (volatile unsigned int *)((0x1065 << 2) + 0xffd00000) ++#define AED_EQ_VOLUME_SLEW_CNT (0x1066) ++#define P_AED_EQ_VOLUME_SLEW_CNT (volatile unsigned int *)((0x1066 << 2) + 0xffd00000) ++#define AED_MUTE (0x1067) ++#define P_AED_MUTE (volatile unsigned int *)((0x1067 << 2) + 0xffd00000) ++#define AED_DRC_EN (0x1070) ++#define P_AED_DRC_EN (volatile unsigned int *)((0x1070 << 2) + 0xffd00000) ++#define AED_DRC_AE (0x1071) ++#define P_AED_DRC_AE (volatile unsigned int *)((0x1071 << 2) + 0xffd00000) ++#define AED_DRC_AA (0x1072) ++#define P_AED_DRC_AA (volatile unsigned int *)((0x1072 << 2) + 0xffd00000) ++#define AED_DRC_AD (0x1073) ++#define P_AED_DRC_AD (volatile unsigned int *)((0x1073 << 2) + 0xffd00000) ++#define AED_DRC_AE_1M (0x1074) ++#define P_AED_DRC_AE_1M (volatile unsigned int *)((0x1074 << 2) + 0xffd00000) ++#define AED_DRC_AA_1M (0x1075) ++#define P_AED_DRC_AA_1M (volatile unsigned int *)((0x1075 << 2) + 0xffd00000) ++#define AED_DRC_AD_1M (0x1076) ++#define P_AED_DRC_AD_1M (volatile unsigned int *)((0x1076 << 2) + 0xffd00000) ++#define AED_DRC_OFFSET0 (0x1077) ++#define P_AED_DRC_OFFSET0 (volatile unsigned int *)((0x1077 << 2) + 0xffd00000) ++#define AED_DRC_OFFSET1 (0x1078) ++#define P_AED_DRC_OFFSET1 (volatile unsigned int *)((0x1078 << 2) + 0xffd00000) ++#define AED_DRC_THD0 (0x1079) ++#define P_AED_DRC_THD0 (volatile unsigned int *)((0x1079 << 2) + 0xffd00000) ++#define AED_DRC_THD1 (0x107a) ++#define P_AED_DRC_THD1 (volatile unsigned int *)((0x107a << 2) + 0xffd00000) ++#define AED_DRC_K0 (0x107b) ++#define P_AED_DRC_K0 (volatile unsigned int *)((0x107b << 2) + 0xffd00000) ++#define AED_DRC_K1 (0x107c) ++#define P_AED_DRC_K1 (volatile unsigned int *)((0x107c << 2) + 0xffd00000) ++#define AED_CLIP_THD (0x107d) ++#define P_AED_CLIP_THD (volatile unsigned int *)((0x107d << 2) + 0xffd00000) ++#define AED_NG_THD0 (0x107e) ++#define P_AED_NG_THD0 (volatile unsigned int *)((0x107e << 2) + 0xffd00000) ++#define AED_NG_THD1 (0x107f) ++#define P_AED_NG_THD1 (volatile unsigned int *)((0x107f << 2) + 0xffd00000) ++#define AED_NG_CNT_THD (0x1080) ++#define P_AED_NG_CNT_THD (volatile unsigned int *)((0x1080 << 2) + 0xffd00000) ++#define AED_NG_CTL (0x1081) ++#define P_AED_NG_CTL (volatile unsigned int *)((0x1081 << 2) + 0xffd00000) ++#define AED_ED_CTL (0x1082) ++#define P_AED_ED_CTL (volatile unsigned int *)((0x1082 << 2) + 0xffd00000) ++#define AED_DEBUG0 (0x1083) ++#define P_AED_DEBUG0 (volatile unsigned int *)((0x1083 << 2) + 0xffd00000) ++#define AED_DEBUG1 (0x1084) ++#define P_AED_DEBUG1 (volatile unsigned int *)((0x1084 << 2) + 0xffd00000) ++#define AED_DEBUG2 (0x1085) ++#define P_AED_DEBUG2 (volatile unsigned int *)((0x1085 << 2) + 0xffd00000) ++#define AED_DEBUG3 (0x1086) ++#define P_AED_DEBUG3 (volatile unsigned int *)((0x1086 << 2) + 0xffd00000) ++#define AED_DEBUG4 (0x1087) ++#define P_AED_DEBUG4 (volatile unsigned int *)((0x1087 << 2) + 0xffd00000) ++#define AED_DEBUG5 (0x1088) ++#define P_AED_DEBUG5 (volatile unsigned int *)((0x1088 << 2) + 0xffd00000) ++#define AED_DEBUG6 (0x1089) ++#define P_AED_DEBUG6 (volatile unsigned int *)((0x1089 << 2) + 0xffd00000) ++#define AED_TOP_CTL (0x1090) ++#define P_AED_TOP_CTL (volatile unsigned int *)((0x1090 << 2) + 0xffd00000) ++#endif ++ ++// ++// Closing file: audio_eq_drc.h ++// ++//======================================================================== ++// Audio Interface (12'h500 - 12'h5ff) ++// ++//======================================================================== ++// ++// Reading file: aregs.h ++// ++//======================================================================== ++// Audio Interface (8'h00 - 8'hff) ++// Modified : Xuyun Chen Jan 2001 ++//======================================================================== ++// Number of bytes expected per NON-PCM frame, including the header. ++// 16 bits. ++// ----------------------------------------------- ++// CBUS_BASE: AIU_CBUS_BASE = 0x14 ++// ----------------------------------------------- ++#define AIU_958_BPF (0x1400) ++#define P_AIU_958_BPF (volatile unsigned int *)((0x1400 << 2) + 0xffd00000) ++// Value of burst_info used in IEC958 preamble for a NON-PCM frame. See ++// ATSC AC-3 spec Annex B. 16 bits. ++#define AIU_958_BRST (0x1401) ++#define P_AIU_958_BRST (volatile unsigned int *)((0x1401 << 2) + 0xffd00000) ++// Value of length_code used in IEC958 preamble for an NON-PCM frame. See ++// ATSC AC-3 spec Annex B. 16 bits. ++#define AIU_958_LENGTH (0x1402) ++#define P_AIU_958_LENGTH (volatile unsigned int *)((0x1402 << 2) + 0xffd00000) ++// How many subframes to padd around the NON-PCM frame. This will ++// be set to 'd3072 if it is a AC-3 audio stream. ++// 16 bits ++#define AIU_958_PADDSIZE (0x1403) ++#define P_AIU_958_PADDSIZE (volatile unsigned int *)((0x1403 << 2) + 0xffd00000) ++// 16'd3072 ++// Misc. control settings for IEC958 interface ++// Bit 15:14 pcm_sample_ctl, 00-pcm_no_sample, 01-pcm_sample_up, 10-pcm_sample_down, 11-pcm_sample_down_drop ++// Bit 13: if true, force each audio data to left or right according to the bit attached with the audio data ++// This bit should be used with Register AIU_958_force_left(0x505) together ++// Bit 12: if true, the U(user data) is from the stream otherwise it is filled by ++// zero while encoding iec958 frame ++// Bit 11 : if true big endian(highword,lowword) otherwise little endian(lowword,highword) ++// for 32bit mode ++// Bit 10:8 : shift number for 32 bit mode ++// Bit 7 : 32 bit mode turn on while This bit is true and Bit 1 is true ++// Bit 6:5 : Specifies output alignment for 16 bit pcm data. ++// 00 : dout = {8'b0, din}; ++// 01 : dout = {4'b0, din, 4'b0}; ++// 10 : dout = { din, 8'b0}; ++// Bit 4 : True if data should be sent out MSB first. LSB first is the ++// default in the spec. ++// Bit 3 : True if msb should be extended (only used with 16 bit pcm data.) ++// Bit 2 : True if msb of PCM data should be inverted. ++// Bit 1 : True if PCM data is 16 bits wide. False if 24 bit or 32bit mode. ++// Bit 0 : True if source data is non-PCM data. False if it is PCM data. ++#define AIU_958_MISC (0x1404) ++#define P_AIU_958_MISC (volatile unsigned int *)((0x1404 << 2) + 0xffd00000) ++// 14'b0_0_0_000_0_0000001 ++// A write to this register specifies that the next pcm sample sent out ++// of the iec958 interface should go into the _left_ channel. ++#define AIU_958_FORCE_LEFT (0x1405) ++#define P_AIU_958_FORCE_LEFT (volatile unsigned int *)((0x1405 << 2) + 0xffd00000) ++//Read Only ++//bit 6:0 how many data discarded in the last dma after one frame data finish transfering to AIU ++// should used together with register AIU_958_dcu_ff_ctrl ++#define AIU_958_DISCARD_NUM (0x1406) ++#define P_AIU_958_DISCARD_NUM (volatile unsigned int *)((0x1406 << 2) + 0xffd00000) ++//bit 15:8 : A read from this register indicates the IEC958 FIFO count value ++//bit 7 : ai_958_req_size if ture, set to 8 bits interface, used to handle odd frame continous read ++//bit 6 : continue seeking and dont discard the rest data in one dma after frame end ++//bit 5 : if true, byte by byte seeking, otherwise word by word seeking ++//bit 4 : if true, the function for sync head seeking is enabled ++//bit 3:2 : IEC958 interrupt mode ++// There are two conditions to generate interrupt. The First condition is that one frame data ++// have been finished writing into FIFO. The second condition is at least some data of the current ++// frame have been read out(refer to Register AIU_958_ffrdout_thd) ++// 00: interrupt is not generated ++// 10: interrupt is generated if the first condition is true ++// 01: interrupt is generated if the second condition is true ++// 11: interrupt is generated if both of the conditions are true ++//bit 1: fifo auto disable, High means after one frame data put into the FIFO, the FIFO ++// will automatically disabled ++//bit 0: fifo enable ++#define AIU_958_DCU_FF_CTRL (0x1407) ++#define P_AIU_958_DCU_FF_CTRL (volatile unsigned int *)((0x1407 << 2) + 0xffd00000) ++// 'b0_0_1_11_1_0 ++// channel status registers for Left channel ++// chstat_l0[15:0] contains bits 15:0 of the channel status word. Note ++// that bit zero of the channel status word is sent out first. ++// chstat_l1[15:0] contains bits 31:16 of the channel status word. ++#define AIU_958_CHSTAT_L0 (0x1408) ++#define P_AIU_958_CHSTAT_L0 (volatile unsigned int *)((0x1408 << 2) + 0xffd00000) ++#define AIU_958_CHSTAT_L1 (0x1409) ++#define P_AIU_958_CHSTAT_L1 (volatile unsigned int *)((0x1409 << 2) + 0xffd00000) ++// Control register for IEC958 interface ++// Bit 9:8 what to do if there is a fifo underrun ++// 00 => insert 24'h000000 ++// 01 => insert mute constant as defined below ++// 10 => repeat last l/r samples ++// Bit 7:5 mute constant ++// 000 => 24'h000000 ++// 001 => 24'h800000 ++// 010 => 24'h080000 ++// 011 => 24'h008000 ++// 100 => 24'h000001 ++// 101 => 24'h000010 ++// 110 => 24'h000100 ++// Bit 4 mute left speaker ++// Bit 3 mute right speaker ++// Bit 2:1 swap channels ++// 00 : L R => L R ++// 01 : L R => L L ++// 10 : L R => R R ++// 11 : L R => R L ++// Bit 0 Set this bit to hold iec958 interface after the current ++// subframe has been completely transmitted. ++#define AIU_958_CTRL (0x140a) ++#define P_AIU_958_CTRL (volatile unsigned int *)((0x140a << 2) + 0xffd00000) ++// 10'b00_000_00_00_0 ++// A write operation to this register will cause one of the output samples ++// to be repeated. This can be used to switch the left and the right ++// channels. ++#define AIU_958_RPT (0x140b) ++#define P_AIU_958_RPT (volatile unsigned int *)((0x140b << 2) + 0xffd00000) ++// Channel swap and mute control register. ++// Bit 15: Mute extra left channel ++// Bit 14: Mute extra right channel ++// Bit 13: Mute center ++// Bit 12: Mute subwoofer ++// Bit 11: Mute surround left ++// Bit 10: Mute surround right ++// Bit 9: Mute left ++// Bit 8: Mute right ++// Bit 7:6 Channel swap for xtra dac ++// Bit 5:4 Channel swap for sub/center dac ++// Bit 3:2 Channel swap for surround dac ++// Bit 1:0 Channel swap for main l/r dac ++// Channel swap possibilities: ++// 00 : L R => L R ++// 01 : L R => L L ++// 10 : L R => R R ++// 11 : L R => R L ++#define AIU_I2S_MUTE_SWAP (0x140c) ++#define P_AIU_I2S_MUTE_SWAP (volatile unsigned int *)((0x140c << 2) + 0xffd00000) ++// 16'b0 ++// Bit 0 : 0=> single two channel stream ++// 1=> four two channel streams ++#define AIU_I2S_SOURCE_DESC (0x140d) ++#define P_AIU_I2S_SOURCE_DESC (volatile unsigned int *)((0x140d << 2) + 0xffd00000) ++// Median filter control register ++// Bit 1: 0=> data is offset binary ++// 1=> data is signed ++// Bit 0: enable median filter ++#define AIU_I2S_MED_CTRL (0x140e) ++#define P_AIU_I2S_MED_CTRL (volatile unsigned int *)((0x140e << 2) + 0xffd00000) ++// 2'b10 ++// Median filter threshold constant ++// 16 bits ++#define AIU_I2S_MED_THRESH (0x140f) ++#define P_AIU_I2S_MED_THRESH (volatile unsigned int *)((0x140f << 2) + 0xffd00000) ++// 16'h8000 ++// Describes dac's connected to I2S interface ++// Bit 7: sign extend sample before downshift. ++// Bit 6:4 payload downshift constant ++// Bit 3: mute constant ++// 0 => 'h0000000 ++// 1 => 'h800000 ++// Bit 2: send msb first ++// Bit 1:0 Size of payload ++// Note that this parameter used to be called "size of dacs" ++// It is now called the payload size since a 24 bit payload can ++// actually be connected to any size of dac. The dac will simply ++// disregard the extra bits. ++// 00 => 16 bit, alrclk = aoclk/32 ++// 01 => 20 bit, alrclk = aoclk/40 ++// 10 => 24 bit, alrclk = aoclk/48 ++// 11 => 24 bit, but alrclk = aoclk/64 ++#define AIU_I2S_DAC_CFG (0x1410) ++#define P_AIU_I2S_DAC_CFG (volatile unsigned int *)((0x1410 << 2) + 0xffd00000) ++// 8'b0_000_1_1_10 ++// A write to this register will cause the interface to repeat the current ++// sample. Can be used to regain synchronization. ++// A read from this register indicates that the next sample to be sent ++// out of the interface should go into the _left_ channel of the dac. ++#define AIU_I2S_SYNC (0x1411) ++#define P_AIU_I2S_SYNC (volatile unsigned int *)((0x1411 << 2) + 0xffd00000) ++// Misc regs ++// Bit 4 if true, force each audio data to left or right according to the bit attached with the audio data ++// This bit should be used with Register AIU_i2s_sync(0x511) together ++// Bit 3: Same Audio source for IEC958 and I2s stream 0, both from i2s buffer ++// Bit 2: Set this bit to put i2s interface in hold mode ++// Bit 1:0 How to handle underruns ++// 00 => send zeros ++// 01 => send 'h800000 ++// 10 => repeat last samples ++#define AIU_I2S_MISC (0x1412) ++#define P_AIU_I2S_MISC (volatile unsigned int *)((0x1412 << 2) + 0xffd00000) ++// 5'b0 ++// Bit 7:0 Audio output config. ++// 2 bits for each dac, 7:6 for dac3, 5:4 for dac2, ++// 3:2 for dac1, 1:0 for dac0 ++// For each 2bits: 00: connect channel0-1 to the dac ++// 01: connect channel2-3 to the dac ++// 10: connect channel4-5 to the dac ++// 11: connect channel6-7 to the dac ++#define AIU_I2S_OUT_CFG (0x1413) ++#define P_AIU_I2S_OUT_CFG (volatile unsigned int *)((0x1413 << 2) + 0xffd00000) ++// 8'b0_000000_0 ++#define AIU_I2S_FF_CTRL (0x1414) ++#define P_AIU_I2S_FF_CTRL (volatile unsigned int *)((0x1414 << 2) + 0xffd00000) ++// A write to this register resets the AIU ++//Bit 3 reset slow domain iec958 ++//Bit 2 soft reset iec958 fast domain ++//Bit 1 reset slow domain i2s ++//Bit 0 soft reset i2s fast domain ++#define AIU_RST_SOFT (0x1415) ++#define P_AIU_RST_SOFT (volatile unsigned int *)((0x1415 << 2) + 0xffd00000) ++// Clock generation control register ++// Bit 15: enable_ddr_arb, set low to reset ++// Bit 14:13 parser_A_addr_sel 00-A_addr_aififo2, 01-A_addr_iec958, 10-A_addr_aififo, 11-A_addr_i2s ++// Bit 12: 958 divisor more, if true, divided by 2, 4, 6, 8 ++// Bit 11: amclk output divisor ++// 0 => dont divide ++// 1 => divide by 2 ++// Bit 10: clock source selection ++// 0 => aiclk from pin ++// 1 => ai_pll_clk from pll ++// Bit 9:8 alrclk skew ++// 00 => alrclk transitions at the same time msb is sent ++// 01 => alrclk transitions on the cycle before msb is sent ++// 10 => alrclk transitions on the cycle after msb is sent ++// Bit 7: invert alrclk ++// Bit 6: invert aoclk ++// Bit 5:4 958 divisor ++// 00 => divide by 1 ++// 01 => divide by 2 ++// 10 => divide by 3 ++// 11 => divide by 4 ++// Bit 3:2 i2s divisor. NOTE: this value is ignored if AIU_clk_ctrl_more[5:0] != 0 ++// 00 => divide by 1 ++// 01 => divide by 2 ++// 10 => divide by 4 ++// 11 => divide by 8 ++// Bit 1: enable 958 divider ++// Bit 0: enable i2s divider ++#define AIU_CLK_CTRL (0x1416) ++#define P_AIU_CLK_CTRL (volatile unsigned int *)((0x1416 << 2) + 0xffd00000) ++// 13'b0_0_1_01_1_1_10_11_0_0 ++// Misc settings that determine the type of adc that is ++// connected to the AIU. Reverb mode is deleted. ++// Bit 12: selects adc input ++// Bit 11:10 adc size ++// 00 => 16 bits ++// 01 => 18 bits ++// 10 => 20 bits ++// 11 => 24 bits ++// Bit 9:8 adc l/r swap mode ++// 00 => stereo ++// 01 => send the right adc input to both l and r speakers ++// 01 => send the left adc input to both l and r speakers ++// 11 => sum the left and right inputs and forward to ++// both speakers ++// Bit 7:5 adata/lrclk skew mode ++// Bit 4 1=>invert the adc's lrclk (This is the lrclk going _out_ ++// of the chip. ++// Bit 3 1=>Latch the data on the positive edge of the _internal_ ++// aoclk. ++// Bit 2 1=>adc data is in signed 2's complement mode ++#define AIU_MIX_ADCCFG (0x1417) ++#define P_AIU_MIX_ADCCFG (volatile unsigned int *)((0x1417 << 2) + 0xffd00000) ++// 12'b01_00_001_1_0_1_00 ++// Control register that can be changed dynamically. These control ++// signals are synchronized internally. ++// Bit 12: if true, toggle each mixed audio data to left or right channel ++// Bit 11: abuf din left selection, if true, select bit 24 of the data from abuf ++// otherwise select bit 25 of the data from abuf ++// Bit 10:9 mix sync select, when music, mic and abuf are mixed togather, the main ++// sync source can be selected ++// 00: not sync source ++// 01: music data is the main sync source ++// 10: abuf input data is the main sync source ++// 11: music and abuf togather as the sync source ++// Bit 8: 0=> data from abuf is offset binary ++// 1=> data from abuf is signed ++// Bit 7:6 the source for data from aiu to abuf ++// 00 => mic ++// 01 => mic saled + abuf scaled ++// 10 => mic scaled + abuf scaled + music scaled ++// 11 => music ++// Bit 5 channel from aiu to abuf is on ++// Bit 4 channel from abuf to aiu is on ++// Bit 3 mic is on ++// Bit 2 music is on ++// Bit 1 if true the mixed data are outputed to i2s dac channel, ++// otherwise the mixed data are outputed to IEC958 output ++// Bit 0 if true music source for mixing is from i2s buffer, ++// otherwise music source is from iec958 buffer ++#define AIU_MIX_CTRL (0x1418) ++#define P_AIU_MIX_CTRL (volatile unsigned int *)((0x1418 << 2) + 0xffd00000) ++// 11'b01_1_01_0_0_0_1_1_1 ++// Bit 15 invert_audin_sclk. ++// Bit 14 enable_adc_sclk. ++// Bit 13: 8 divisor_adc_sclk. ++// Bit 7 invert_acodec_adc_sclk. ++// Bit 6 hdmitx_sel_aoclkx2: 0=Select cts_clk_i958 as AIU clk to hdmi_tx_audio_master_clk; 1=Select cts_aoclkx2_int as AIU clk to hdmi_tx_audio_master_clk; ++// Bit 5: 0 More control on i2s divisor. For backward compatiblity, this value is ignored if is 0, ++// if non-zero, it takes effect over AIU_clk_ctrl[3:2]. ++// 0=i2s divisor will use the old value in AIU_clk_ctrl[3:2] (divide by 1/2/4/8) ++// 1=divide by 2; ++// 2=divide by 3; ++// 3=divide by 4; ++// ... and so on ... ++// 63=divide by 64. ++#define AIU_CLK_CTRL_MORE (0x1419) ++#define P_AIU_CLK_CTRL_MORE (volatile unsigned int *)((0x1419 << 2) + 0xffd00000) ++// A read from this register pops 16 bits of data off the 958 ++// fifo. A write has no effect. ++#define AIU_958_POP (0x141a) ++#define P_AIU_958_POP (volatile unsigned int *)((0x141a << 2) + 0xffd00000) ++//gain register for mixing ++// for each gain, ++// 00000: x 0 ++// 00001: x 1 ++// 00010: x 2 ++// 00011: x 3 ++// 00100: x 4 ++// 00101: x 5 ++// 00110: x 6 ++// ...... ++// 01110: x14 ++// 01111: x15 ++// 10000: x 0 ++// 10001: x 1/16 ++// 10010: x 2/16 ++// 10011: x 3/16 ++// 10100: x 4/16 ++// ...... ++// 11110: x 14/16 ++// 11111: x 15/16 ++//Bit 14:10 mic gain ++//Bit 9:5 abuf gain ++//Bit 4:0 music gain ++#define AIU_MIX_GAIN (0x141b) ++#define P_AIU_MIX_GAIN (volatile unsigned int *)((0x141b << 2) + 0xffd00000) ++// 15'b00001_00001_00001 ++//sync head seeking is supported. The maxinium length of sync head is ++//48-bit-wide.(in byte by byte seeking mode, the maximium is 44-bit-wide). ++//It is consisted of 3 words (synword1_synword2_syncword3). ++//You can configure the sync head pattern by using sync mask(mask1_mask2_mask3). ++//For example. AC-3 sync head is a 16-bit word(0b77), so syncword1 is set as 0b77, ++//mask1 is 0000(not set), mask2 and mask3 is all masked. ++#define AIU_958_SYNWORD1 (0x141c) ++#define P_AIU_958_SYNWORD1 (volatile unsigned int *)((0x141c << 2) + 0xffd00000) ++//16'h0b77 //ac-3 sync head ++#define AIU_958_SYNWORD2 (0x141d) ++#define P_AIU_958_SYNWORD2 (volatile unsigned int *)((0x141d << 2) + 0xffd00000) ++//16'h0000 ++#define AIU_958_SYNWORD3 (0x141e) ++#define P_AIU_958_SYNWORD3 (volatile unsigned int *)((0x141e << 2) + 0xffd00000) ++//16'h0000 ++#define AIU_958_SYNWORD1_MASK (0x141f) ++#define P_AIU_958_SYNWORD1_MASK (volatile unsigned int *)((0x141f << 2) + 0xffd00000) ++//16'h0000 //16-bit ac-3 sync_head ++#define AIU_958_SYNWORD2_MASK (0x1420) ++#define P_AIU_958_SYNWORD2_MASK (volatile unsigned int *)((0x1420 << 2) + 0xffd00000) ++//16'hffff ++#define AIU_958_SYNWORD3_MASK (0x1421) ++#define P_AIU_958_SYNWORD3_MASK (volatile unsigned int *)((0x1421 << 2) + 0xffd00000) ++//16'hffff ++//fifo read-out threshold, one condition to generate interrupt is met after fifo readout counter ++//reach this value in a frame, please refer to register AIU_958_dcu_ff_ctrl ++#define AIU_958_FFRDOUT_THD (0x1422) ++#define P_AIU_958_FFRDOUT_THD (volatile unsigned int *)((0x1422 << 2) + 0xffd00000) ++//'h0004 ++//For pause burst sequence adding, one pause burst sequence is consist of a serious ++// pause burst. ++//This register defines the length of each pause burst in a pause burst sequence. The size of the ++//preamble(Pa, Pb, Pc, Pd) is not counted, but the size of stuff data is counted. ++#define AIU_958_LENGTH_PER_PAUSE (0x1423) ++#define P_AIU_958_LENGTH_PER_PAUSE (volatile unsigned int *)((0x1423 << 2) + 0xffd00000) ++//'h0000 ++//This reigster defines the number of pause burst in a pause burst sequence. ++//Bit 15 if true, one pause burst sequence will be added ++//Bit 14:0 the number of pause burst in a pause burst sequence ++#define AIU_958_PAUSE_NUM (0x1424) ++#define P_AIU_958_PAUSE_NUM (volatile unsigned int *)((0x1424 << 2) + 0xffd00000) ++//'h0000 ++//The first 16-bit in the payload of pause burst sequence (gap_length) ++#define AIU_958_PAUSE_PAYLOAD (0x1425) ++#define P_AIU_958_PAUSE_PAYLOAD (volatile unsigned int *)((0x1425 << 2) + 0xffd00000) ++//'h0000 ++//For auto pause function, when enabled, pause burst sequence will be automatically added if the data in ++// 958 fifo is less than auto_pause threshold and if fifo is disabled. ++//Bit 15 if true, auto pause function enable ++//Bit 14 pause pack option, just for debugging and adding one option ++//Bit 7:0 auto_pause threshold ++#define AIU_958_AUTO_PAUSE (0x1426) ++#define P_AIU_958_AUTO_PAUSE (volatile unsigned int *)((0x1426 << 2) + 0xffd00000) ++//'h0000 ++//pause burst sequence payload length( = AIU_958_pause_num * AIU_958_length_per_pause) ++#define AIU_958_PAUSE_PD_LENGTH (0x1427) ++#define P_AIU_958_PAUSE_PD_LENGTH (volatile unsigned int *)((0x1427 << 2) + 0xffd00000) ++//'h0000 ++// Bit 15:12 Rsrv. ++// Bit 11: 0 dac_lrclk_div: Default is 48-1=47, which means lrclk is sclk divide by 48. ++#define AIU_CODEC_DAC_LRCLK_CTRL (0x1428) ++#define P_AIU_CODEC_DAC_LRCLK_CTRL (volatile unsigned int *)((0x1428 << 2) + 0xffd00000) ++//'h002f ++// Bit 15:14 Rsrv. ++// Bit 13 inv_audin_lrclk: whether to invert lrclk before output to Audin ++// Bit 12 inv_acodec_adc_lrclk: whether to invert lrclk before output to Audio Codec ++// Bit 11: 0 adc_lrclk_div: Default is 48-1=47, which means lrclk is sclk divide by 48. ++#define AIU_CODEC_ADC_LRCLK_CTRL (0x1429) ++#define P_AIU_CODEC_ADC_LRCLK_CTRL (volatile unsigned int *)((0x1429 << 2) + 0xffd00000) ++//'h002f ++// Bit 15:6 Rsrv. ++// Bit 5: 4 hdmi_data_sel: 00=output 0, disable hdmi data; 01=Select pcm data; 10=Select AIU I2S data; 11=Not allowed. ++// Bit 3: 2 Rsrv. ++// Bit 1: 0 hdmi_clk_sel: 00=Disable output hdmi clock; 01=Select pcm clock; 10=Select AIU clk; 11=Not allowed. ++#define AIU_HDMI_CLK_DATA_CTRL (0x142a) ++#define P_AIU_HDMI_CLK_DATA_CTRL (volatile unsigned int *)((0x142a << 2) + 0xffd00000) ++//'h0000 ++// Bit 15:6 Rsrv. ++// Bit 5: 4 acodec_data_sel: 00=output 0, disable acodec_sdin; 01=Select pcm data; 10=Select AIU I2S data; 11=Not allowed. ++// Bit 3: 2 Rsrv. ++// Bit 1: 0 acodec_clk_sel: 00=Disable output acodec_sclk; 01=Select pcm clock; 10=Select AIU aoclk; 11=Not allowed. ++#define AIU_CODEC_CLK_DATA_CTRL (0x142b) ++#define P_AIU_CODEC_CLK_DATA_CTRL (volatile unsigned int *)((0x142b << 2) + 0xffd00000) ++//'h0000 ++#define AIU_ACODEC_CTRL (0x142c) ++#define P_AIU_ACODEC_CTRL (volatile unsigned int *)((0x142c << 2) + 0xffd00000) ++// channel status registers for right channel ++// chstat_r0[15:0] contains bits 15:0 of the channel status word. Note ++// that bit zero of the channel status word is sent out first. ++// chstat_r1[15:0] contains bits 31:16 of the channel status word. ++#define AIU_958_CHSTAT_R0 (0x1430) ++#define P_AIU_958_CHSTAT_R0 (volatile unsigned int *)((0x1430 << 2) + 0xffd00000) ++#define AIU_958_CHSTAT_R1 (0x1431) ++#define P_AIU_958_CHSTAT_R1 (volatile unsigned int *)((0x1431 << 2) + 0xffd00000) ++//Bit 1 if true, turn on Digital output Valid control ++//Bit 0 0: output 0, 1: output 1 to the valid bit in audio digital output when Bit 1 is true ++#define AIU_958_VALID_CTRL (0x1432) ++#define P_AIU_958_VALID_CTRL (volatile unsigned int *)((0x1432 << 2) + 0xffd00000) ++//----------------------------------------------------------------------------- ++// Audio Amplifier controls ++//----------------------------------------------------------------------------- ++#define AIU_AUDIO_AMP_REG0 (0x143c) ++#define P_AIU_AUDIO_AMP_REG0 (volatile unsigned int *)((0x143c << 2) + 0xffd00000) ++#define AIU_AUDIO_AMP_REG1 (0x143d) ++#define P_AIU_AUDIO_AMP_REG1 (volatile unsigned int *)((0x143d << 2) + 0xffd00000) ++#define AIU_AUDIO_AMP_REG2 (0x143e) ++#define P_AIU_AUDIO_AMP_REG2 (volatile unsigned int *)((0x143e << 2) + 0xffd00000) ++#define AIU_AUDIO_AMP_REG3 (0x143f) ++#define P_AIU_AUDIO_AMP_REG3 (volatile unsigned int *)((0x143f << 2) + 0xffd00000) ++//----------------------------------------------------------------------------- ++//add for AIFIFO2 channel ++//----------------------------------------------------------------------------- ++//Bit 3 CRC pop aififo2 enable ++//Bit 2 writing to this bit to 1 causes CRC module reset ++//Bit 1 unused ++//Bit 0 writing to this bit to 1 causes AIFIFO2 soft reset ++#define AIU_AIFIFO2_CTRL (0x1440) ++#define P_AIU_AIFIFO2_CTRL (volatile unsigned int *)((0x1440 << 2) + 0xffd00000) ++//'h0000 ++//AIFIFO2 status register ++//Bit 4:0 //how many bits left in the first pop register ++#define AIU_AIFIFO2_STATUS (0x1441) ++#define P_AIU_AIFIFO2_STATUS (volatile unsigned int *)((0x1441 << 2) + 0xffd00000) ++//Same fucntion as the AIGBIT of AIFIFO in CDROM module ++//write to this register how many bits wanna pop, ++//and reading this register gets the corresponding bits data ++#define AIU_AIFIFO2_GBIT (0x1442) ++#define P_AIU_AIFIFO2_GBIT (volatile unsigned int *)((0x1442 << 2) + 0xffd00000) ++//Same function as the AICLB of AIFIFO in CDROM module ++//return the leading zeros by reading this registers ++#define AIU_AIFIFO2_CLB (0x1443) ++#define P_AIU_AIFIFO2_CLB (volatile unsigned int *)((0x1443 << 2) + 0xffd00000) ++//CRC control register, read/write ++//Bit 0 CRC caculation start ++//Bit 1 CRC core soft reset ++//Bit 2 CRC input register clear ++//Bit 3 CRC pop data from FIFO enable ++//Bit 13:8 CRC polynomial equation order, between 1 to 32 ++#define AIU_CRC_CTRL (0x1444) ++#define P_AIU_CRC_CTRL (volatile unsigned int *)((0x1444 << 2) + 0xffd00000) ++//16'h1000 ++//CRC status register, read only ++//Bit 7:4 CRC internal shift register bit select, just for debug purpose ++//Bit 3 CRC internal shift register data valid, just for debug purpose ++//Bit 2 CRC input register data valid ++//Bit 1 CRC result, 1: CRC not correct, 0: CRC correct ++//Bit 0 CRC state, 1: CRC busy, 0: CRC idle ++#define AIU_CRC_STATUS (0x1445) ++#define P_AIU_CRC_STATUS (volatile unsigned int *)((0x1445 << 2) + 0xffd00000) ++//CRC internal shift register, read only, for debug purpose ++#define AIU_CRC_SHIFT_REG (0x1446) ++#define P_AIU_CRC_SHIFT_REG (volatile unsigned int *)((0x1446 << 2) + 0xffd00000) ++//CRC data input register, read/write ++#define AIU_CRC_IREG (0x1447) ++#define P_AIU_CRC_IREG (volatile unsigned int *)((0x1447 << 2) + 0xffd00000) ++//16'h0000 ++//CRC calculation register high-bit part [31:16], read/write ++#define AIU_CRC_CAL_REG1 (0x1448) ++#define P_AIU_CRC_CAL_REG1 (volatile unsigned int *)((0x1448 << 2) + 0xffd00000) ++//CRC calculation register low-bit part [15:0], read/write ++#define AIU_CRC_CAL_REG0 (0x1449) ++#define P_AIU_CRC_CAL_REG0 (volatile unsigned int *)((0x1449 << 2) + 0xffd00000) ++//32'h00000000 ++//CRC polynomial coefficient high-bit part [31:16], read/write ++#define AIU_CRC_POLY_COEF1 (0x144a) ++#define P_AIU_CRC_POLY_COEF1 (volatile unsigned int *)((0x144a << 2) + 0xffd00000) ++//CRC polynomial coefficient low-bit part [15:0], read/write ++#define AIU_CRC_POLY_COEF0 (0x144b) ++#define P_AIU_CRC_POLY_COEF0 (volatile unsigned int *)((0x144b << 2) + 0xffd00000) ++//32'h80050000 default CRC-16 ++//CRC frame size, high-bit part [19:16], read/write ++#define AIU_CRC_BIT_SIZE1 (0x144c) ++#define P_AIU_CRC_BIT_SIZE1 (volatile unsigned int *)((0x144c << 2) + 0xffd00000) ++//CRC frame size, low-bit part [15:0], read/write ++#define AIU_CRC_BIT_SIZE0 (0x144d) ++#define P_AIU_CRC_BIT_SIZE0 (volatile unsigned int *)((0x144d << 2) + 0xffd00000) ++//20'hfffff ++//how many bits have been processed right now in the current frame, read only ++//high-bit part [19:16] ++#define AIU_CRC_BIT_CNT1 (0x144e) ++#define P_AIU_CRC_BIT_CNT1 (volatile unsigned int *)((0x144e << 2) + 0xffd00000) ++//low-bit part [15:0] ++#define AIU_CRC_BIT_CNT0 (0x144f) ++#define P_AIU_CRC_BIT_CNT0 (volatile unsigned int *)((0x144f << 2) + 0xffd00000) ++// ------------------------------------- ++// AMCLK Measurement ++// ------------------------------------- ++// Used to measure the amclk frequency ++#define AIU_AMCLK_GATE_HI (0x1450) ++#define P_AIU_AMCLK_GATE_HI (volatile unsigned int *)((0x1450 << 2) + 0xffd00000) ++#define AIU_AMCLK_GATE_LO (0x1451) ++#define P_AIU_AMCLK_GATE_LO (volatile unsigned int *)((0x1451 << 2) + 0xffd00000) ++#define AIU_AMCLK_MSR (0x1452) ++#define P_AIU_AMCLK_MSR (volatile unsigned int *)((0x1452 << 2) + 0xffd00000) ++#define AIU_AUDAC_CTRL0 (0x1453) ++#define P_AIU_AUDAC_CTRL0 (volatile unsigned int *)((0x1453 << 2) + 0xffd00000) ++// ------------------------------------- ++// Super Simple Delta Sigma DAC ++// ------------------------------------- ++// bit 15 1 = invert the clock to the analog filter ++// bit 14 1 = digital mute ++// bit 13 1 = enable analog mute (in the analog block) ++// bit 12 1 = enable Right channel 3 in the analog block ++// bit 11 1 = enable Left channel 3 in the analog block ++// bit 10 1 = enable Right channel 2 in the analog block ++// bit 9 1 = enable Left channel 2 in the analog block ++// bit 8 1 = enable Right channel 1 in the analog block ++// bit 7 1 = enable Left channel 1 in the analog block ++// bit 6 1 = enable Right channel 0 in the analog block ++// bit 5 1 = enable Left channel 0 in the analog block ++// bit 4: bit select for serial input data ++// bit 3: invert alrclk used by the delta-sigma DAC ++// bit 2: 1 = use serial I2S data. 0 = use parallel audio data ++// bits 1:0 Which data to send to the delta-sigma DAC ++// 11 = use channel 3 data ++// 10 = use channel 2 data ++// 01 = use channel 1 data ++// 00 = use channel 0 data ++#define AIU_DELTA_SIGMA0 (0x1455) ++#define P_AIU_DELTA_SIGMA0 (volatile unsigned int *)((0x1455 << 2) + 0xffd00000) ++// Delta Sigma MUTE Value ++#define AIU_DELTA_SIGMA1 (0x1456) ++#define P_AIU_DELTA_SIGMA1 (volatile unsigned int *)((0x1456 << 2) + 0xffd00000) ++// Additional Audio filter controls ++#define AIU_DELTA_SIGMA2 (0x1457) ++#define P_AIU_DELTA_SIGMA2 (volatile unsigned int *)((0x1457 << 2) + 0xffd00000) ++//Bit 14, left channel Delta Sigma modulator soft reset ++//Bit 13, right channel Delta Sigma modulator soft reset ++//Bit 12, left channel Delta Sigma modulator internal state clear enable when it is unstable ++//Bit 11, right channel Delta Sigma modulator internal state clear enable when it is unstable ++//Bit 10, left channel Delta Sigma detect unstable state enable ++//Bit 9, right channel Delta Sigma detect unstable state enable ++//Bit 8, dither high pass filter enable in the Delta Sigma loop ++//Bit 7:6, reserved ++//Bit 5:0, Delta Sigma input data gain 0/32 ~ 63/32 ++//default: 16'h3 ++#define AIU_DELTA_SIGMA3 (0x1458) ++#define P_AIU_DELTA_SIGMA3 (volatile unsigned int *)((0x1458 << 2) + 0xffd00000) ++//15:8, Added Delta Sigma DC level, range:+-1/2, minimium: +-1/128 (assume max is -1 ~ +1) ++//7:0, max same sequence number, used for unstable detection ++//default: 16'h0 ++#define AIU_DELTA_SIGMA4 (0x1459) ++#define P_AIU_DELTA_SIGMA4 (volatile unsigned int *)((0x1459 << 2) + 0xffd00000) ++//Bit 15:8, square wave divide num ++//Bit 7:0, square wave amplitude, -1/4 ~ 1/4, minimium: +-1/1024 ++//default: 16'h0 ++#define AIU_DELTA_SIGMA5 (0x145a) ++#define P_AIU_DELTA_SIGMA5 (volatile unsigned int *)((0x145a << 2) + 0xffd00000) ++//Bit 11:8, loop dither amplitude2, 0/32 ~ 15/32 ++//Bit 7:4, loop dither amplitude1, 0/32 ~ 15/32 ++//Bit 3:0, loop dither amplitude0, 0/32 ~ 15/32 ++//default: 16'h0 ++#define AIU_DELTA_SIGMA6 (0x145b) ++#define P_AIU_DELTA_SIGMA6 (volatile unsigned int *)((0x145b << 2) + 0xffd00000) ++//Bit 15:8, loop dithering threshold1 0, 1/512, 2/512 ... 1/2 ++//Bit 7:0, loop dithering threshold0 0, 1/512, 2/512 ... 1/2 ++//default: 16'h0 ++#define AIU_DELTA_SIGMA7 (0x145c) ++#define P_AIU_DELTA_SIGMA7 (volatile unsigned int *)((0x145c << 2) + 0xffd00000) ++//read only ++//Bit 15:8 left channel Delta Sigma clear counter number, how many times Delta Sigma has been reseted ++// It will saturate to 255, if more than 255 time ++//Bit 7:0 left channel max same sequence number ++#define AIU_DELTA_SIGMA_LCNTS (0x145d) ++#define P_AIU_DELTA_SIGMA_LCNTS (volatile unsigned int *)((0x145d << 2) + 0xffd00000) ++//read only ++//Bit 15:8 right channel Delta Sigma clear counter number, how many times Delta Sigma has been reseted ++// It will saturate to 255, if more than 255 time ++//Bit 7:0 right channel max same sequence number ++#define AIU_DELTA_SIGMA_RCNTS (0x145e) ++#define P_AIU_DELTA_SIGMA_RCNTS (volatile unsigned int *)((0x145e << 2) + 0xffd00000) ++// -------------------------------------------- ++// I2S DDR Interface ++// -------------------------------------------- ++// The I2S start pointer into DDR memory is a 32-bit number ++#define AIU_MEM_I2S_START_PTR (0x1460) ++#define P_AIU_MEM_I2S_START_PTR (volatile unsigned int *)((0x1460 << 2) + 0xffd00000) ++#define AIU_MEM_I2S_RD_PTR (0x1461) ++#define P_AIU_MEM_I2S_RD_PTR (volatile unsigned int *)((0x1461 << 2) + 0xffd00000) ++#define AIU_MEM_I2S_END_PTR (0x1462) ++#define P_AIU_MEM_I2S_END_PTR (volatile unsigned int *)((0x1462 << 2) + 0xffd00000) ++// There are two masks that control how data is read: ++// [31:16] IRQ block. ++// [15:8] chan_mem_mask. Each bit indicates which channels exist in memory ++// [7:0] chan_rd_mask. Each bit indicates which channels are READ from memory ++#define AIU_MEM_I2S_MASKS (0x1463) ++#define P_AIU_MEM_I2S_MASKS (volatile unsigned int *)((0x1463 << 2) + 0xffd00000) ++// I2S FIFO Control ++// bits [11:10] Select which hardware pointer to use to control the buffer ++// level: ++// 00 = parser ++// 01 = audin_fifo0_wrpt ++// 1x = audin_fifo1_wrpt ++// bit [9] Use level control: 1 = use buffer level control ++// bit [8] Read Only. This bit is 1 when there is data available for reading ++// bit [7] Read only. This bit will be high when we're fetching data from the DDR memory ++// To reset this module, set cntl_enable = 0, and then wait for busy = 0. ++// After that you can pulse cntl_init to start over ++// bit [6] cntl_mode_16bit:Set to 1 for 16 bit storage format in DDR ++// bits [5:3] endian: see $lib/rtl/ddr_endian.v ++// bit [2] cntl_empty_en Set to 1 to enable reading data from the FIFO ++// bit [1] cntl_fill_en Set to 1 to enable reading data from DDR memory ++// bit [0] cntl_init: After setting the read pointers, sizes, channel masks ++// and read masks, set this bit to 1 and then to 0 ++#define AIU_MEM_I2S_CONTROL (0x1464) ++#define P_AIU_MEM_I2S_CONTROL (volatile unsigned int *)((0x1464 << 2) + 0xffd00000) ++// -------------------------------------------- ++// IEC958 DDR Interface ++// -------------------------------------------- ++// The IEC958 start pointer into DDR memory is a 32-bit number ++#define AIU_MEM_IEC958_START_PTR (0x1465) ++#define P_AIU_MEM_IEC958_START_PTR (volatile unsigned int *)((0x1465 << 2) + 0xffd00000) ++#define AIU_MEM_IEC958_RD_PTR (0x1466) ++#define P_AIU_MEM_IEC958_RD_PTR (volatile unsigned int *)((0x1466 << 2) + 0xffd00000) ++#define AIU_MEM_IEC958_END_PTR (0x1467) ++#define P_AIU_MEM_IEC958_END_PTR (volatile unsigned int *)((0x1467 << 2) + 0xffd00000) ++// There are two masks that control how data is read: ++// [15:8] chan_mem_mask. Each bit indicates which channels exist in memory ++// [7:0] chan_rd_mask. Each bit indicates which channels are READ from memory ++#define AIU_MEM_IEC958_MASKS (0x1468) ++#define P_AIU_MEM_IEC958_MASKS (volatile unsigned int *)((0x1468 << 2) + 0xffd00000) ++// IEC958 FIFO Control ++// bit [31] A_urgent ++// bit [30] ch_always_8 ++// bit [29:24] rdata_rd_base_begin ( used for select from different channel ) ++// bit [23:14] reserved ++// bit [13] cntl_sim_en ++// bit [12] cntl_use_level ++// bit [11] Read only. This bit will be set to 1 when there is data in the FIFO to process ++// bit [10] Read only. This bit will be high when we're fetching data from the DDR memory ++// To reset this module, set cntl_enable = 0, and then wait for busy = 0. ++// After that you can pulse cntl_init to start over ++// bit [9] cntl_endian_jic Just in case endian. last minute byte swap of the data out of ++// the FIFO to the rest of the IEC958 logic ++// bit [8] mode_raw: Set this bit to 1 to tell the IEC958 FIFO to read ++// and process data linearly for raw data. ++// bit [7] cntl_mode_16bit:Set to 1 for 16 bit storage format in DDR. Only valid when mode_raw = 0 ++// bit [6] cntl_rd_ddr Set this bit to read if you want AIU_MEM_IEC958_RD_PTR and ++// AIU_MEM_IEC958_RD_PTR_HIGH to refer to the pointer into DDR memory. ++// Otherwise, the curr_ptr registers refer to the byte address of the data ++// at the output of the FIFO to the rest of the IEC958 logic ++// bits [5:3] endian: see $lib/rtl/ddr_endian.v ++// bit [2] cntl_empty_en Set to 1 to enable reading the DDR memory FIFO and filling the pipeline to get-bit ++// Set cntl_empty_en = cntl_fill_en = 0 when pulsing cntl_init ++// bit [1] cntl_fill_en Set to 1 to enable reading data from DDR memory ++// bit [0] cntl_init: After setting the read pointers, sizes, channel masks ++// and read masks, set this bit to 1 and then to 0 ++#define AIU_MEM_IEC958_CONTROL (0x1469) ++#define P_AIU_MEM_IEC958_CONTROL (volatile unsigned int *)((0x1469 << 2) + 0xffd00000) ++// -------------------------------------------- ++// AIFIFO2 DDR Interface ++// -------------------------------------------- ++// The AIFIFO2 start pointer into DDR memory is a 32-bit number ++// The Start pointer will automatically be truncated to land on ++// an 8-byte boundary. That is, bits [2:0] = 0; ++#define AIU_MEM_AIFIFO2_START_PTR (0x146a) ++#define P_AIU_MEM_AIFIFO2_START_PTR (volatile unsigned int *)((0x146a << 2) + 0xffd00000) ++// The current pointer points so some location between the START and END ++// pointers. The current pointer is a BYTE pointer. That is, you can ++// point to any BYTE address within the START/END range ++#define AIU_MEM_AIFIFO2_CURR_PTR (0x146b) ++#define P_AIU_MEM_AIFIFO2_CURR_PTR (volatile unsigned int *)((0x146b << 2) + 0xffd00000) ++#define AIU_MEM_AIFIFO2_END_PTR (0x146c) ++#define P_AIU_MEM_AIFIFO2_END_PTR (volatile unsigned int *)((0x146c << 2) + 0xffd00000) ++#define AIU_MEM_AIFIFO2_BYTES_AVAIL (0x146d) ++#define P_AIU_MEM_AIFIFO2_BYTES_AVAIL (volatile unsigned int *)((0x146d << 2) + 0xffd00000) ++// AIFIFO2 FIFO Control ++// bit [15:11] unused ++// bit [10] use_level Set this bit to 1 to enable filling of the FIFO controlled by the buffer ++// level control. If this bit is 0, then use bit[1] to control the enabling of filling ++// bit [9] Data Ready. This bit is set when data can be popped ++// bit [8] fill busy This bit will be high when we're fetching data from the DDR memory ++// To reset this module, set cntl_enable = 0, and then wait for busy = 0. ++// After that you can pulse cntl_init to start over ++// bit [7] cntl_endian_jic Just in case endian. last minute byte swap of the data out of ++// the FIFO to getbit ++// bit [6] unused ++// bits [5:3] endian: see $lib/rtl/ddr_endian.v ++// bit [2] cntl_empty_en Set to 1 to enable reading the DDR memory FIFO and filling the pipeline to get-bit ++// Set cntl_empty_en = cntl_fill_en = 0 when pulsing cntl_init ++// bit [1] cntl_fill_en Set to 1 to enable reading data from DDR memory ++// bit [0] cntl_init: After setting the read pointers, sizes, channel masks ++// and read masks, set this bit to 1 and then to 0 ++// NOTE: You don't need to pulse cntl_init if only the start address is ++// being changed ++#define AIU_MEM_AIFIFO2_CONTROL (0x146e) ++#define P_AIU_MEM_AIFIFO2_CONTROL (volatile unsigned int *)((0x146e << 2) + 0xffd00000) ++// -------------------------------------------- ++// AIFIFO2 Buffer Level Manager ++// -------------------------------------------- ++#define AIU_MEM_AIFIFO2_MAN_WP (0x146f) ++#define P_AIU_MEM_AIFIFO2_MAN_WP (volatile unsigned int *)((0x146f << 2) + 0xffd00000) ++#define AIU_MEM_AIFIFO2_MAN_RP (0x1470) ++#define P_AIU_MEM_AIFIFO2_MAN_RP (volatile unsigned int *)((0x1470 << 2) + 0xffd00000) ++#define AIU_MEM_AIFIFO2_LEVEL (0x1471) ++#define P_AIU_MEM_AIFIFO2_LEVEL (volatile unsigned int *)((0x1471 << 2) + 0xffd00000) ++// ++// bit [1] manual mode Set to 1 for manual write pointer mode ++// bit [0] Init Set high then low after everything has been initialized ++#define AIU_MEM_AIFIFO2_BUF_CNTL (0x1472) ++#define P_AIU_MEM_AIFIFO2_BUF_CNTL (volatile unsigned int *)((0x1472 << 2) + 0xffd00000) ++// -------------------------------------------- ++// I2S Buffer Level Manager ++// -------------------------------------------- ++#define AIU_MEM_I2S_MAN_WP (0x1473) ++#define P_AIU_MEM_I2S_MAN_WP (volatile unsigned int *)((0x1473 << 2) + 0xffd00000) ++#define AIU_MEM_I2S_MAN_RP (0x1474) ++#define P_AIU_MEM_I2S_MAN_RP (volatile unsigned int *)((0x1474 << 2) + 0xffd00000) ++#define AIU_MEM_I2S_LEVEL (0x1475) ++#define P_AIU_MEM_I2S_LEVEL (volatile unsigned int *)((0x1475 << 2) + 0xffd00000) ++// ++// bit [1] mode 0 = parser (or audin_fifo0 or audin_fifo1), ++// 1 for manual write pointer ++// bit [0] Init Set high then low after everything has been initialized ++#define AIU_MEM_I2S_BUF_CNTL (0x1476) ++#define P_AIU_MEM_I2S_BUF_CNTL (volatile unsigned int *)((0x1476 << 2) + 0xffd00000) ++#define AIU_MEM_I2S_BUF_WRAP_COUNT (0x1477) ++#define P_AIU_MEM_I2S_BUF_WRAP_COUNT (volatile unsigned int *)((0x1477 << 2) + 0xffd00000) ++// bit 29:24 A_brst_num ++// bit 21:16 A_id ++// bit 15:0 level_hold ++#define AIU_MEM_I2S_MEM_CTL (0x1478) ++#define P_AIU_MEM_I2S_MEM_CTL (volatile unsigned int *)((0x1478 << 2) + 0xffd00000) ++//----------------------------------------------------------------------------- ++// Additional IEC958 registers (new feature) ++//----------------------------------------------------------------------------- ++// bit 29:24 A_brst_num ++// bit 21:16 A_id ++// bit 15:0 level_hold ++#define AIU_MEM_IEC958_MEM_CTL (0x1479) ++#define P_AIU_MEM_IEC958_MEM_CTL (volatile unsigned int *)((0x1479 << 2) + 0xffd00000) ++#define AIU_MEM_IEC958_WRAP_COUNT (0x147a) ++#define P_AIU_MEM_IEC958_WRAP_COUNT (volatile unsigned int *)((0x147a << 2) + 0xffd00000) ++#define AIU_MEM_IEC958_IRQ_LEVEL (0x147b) ++#define P_AIU_MEM_IEC958_IRQ_LEVEL (volatile unsigned int *)((0x147b << 2) + 0xffd00000) ++#define AIU_MEM_IEC958_MAN_WP (0x147c) ++#define P_AIU_MEM_IEC958_MAN_WP (volatile unsigned int *)((0x147c << 2) + 0xffd00000) ++#define AIU_MEM_IEC958_MAN_RP (0x147d) ++#define P_AIU_MEM_IEC958_MAN_RP (volatile unsigned int *)((0x147d << 2) + 0xffd00000) ++#define AIU_MEM_IEC958_LEVEL (0x147e) ++#define P_AIU_MEM_IEC958_LEVEL (volatile unsigned int *)((0x147e << 2) + 0xffd00000) ++#define AIU_MEM_IEC958_BUF_CNTL (0x147f) ++#define P_AIU_MEM_IEC958_BUF_CNTL (volatile unsigned int *)((0x147f << 2) + 0xffd00000) ++//----------------------------------------------------------------------------- ++// add for AIFIFO channel (old $cdrom/rtl/cdr_top/getbit) ++//----------------------------------------------------------------------------- ++// Bit 3 CRC pop aififo enable ++// Bit 2 writing to this bit to 1 causes CRC module reset ++// Bit 1 enable aififo ++// Bit 0 writing to this bit to 1 causes aififo soft reset ++#define AIU_AIFIFO_CTRL (0x1480) ++#define P_AIU_AIFIFO_CTRL (volatile unsigned int *)((0x1480 << 2) + 0xffd00000) ++//'h0000 ++// AIFIFO status register ++// Bit 13 //aififo request to dcu status ++// Bit 12 //dcu select status ++// Bit 11:5 //aififo word counter number ++// Bit 4:0 //how many bits left in the first pop register ++#define AIU_AIFIFO_STATUS (0x1481) ++#define P_AIU_AIFIFO_STATUS (volatile unsigned int *)((0x1481 << 2) + 0xffd00000) ++// Same fucntion as the AIGBIT of AIFIFO in CDROM module ++// write to this register how many bits wanna pop, ++// and reading this register gets the corresponding bits data ++#define AIU_AIFIFO_GBIT (0x1482) ++#define P_AIU_AIFIFO_GBIT (volatile unsigned int *)((0x1482 << 2) + 0xffd00000) ++// Same function as the AICLB of AIFIFO in CDROM module ++// return the leading zeros by reading this registers ++#define AIU_AIFIFO_CLB (0x1483) ++#define P_AIU_AIFIFO_CLB (volatile unsigned int *)((0x1483 << 2) + 0xffd00000) ++// -------------------------------------------- ++// AIFIFO DDR Interface ++// -------------------------------------------- ++// The AIFIFO start pointer into DDR memory is a 32-bit number ++// The Start pointer will automatically be truncated to land on ++// an 8-byte boundary. That is, bits [2:0] = 0; ++#define AIU_MEM_AIFIFO_START_PTR (0x1484) ++#define P_AIU_MEM_AIFIFO_START_PTR (volatile unsigned int *)((0x1484 << 2) + 0xffd00000) ++// The current pointer points so some location between the START and END ++// pointers. The current pointer is a BYTE pointer. That is, you can ++// point to any BYTE address within the START/END range ++#define AIU_MEM_AIFIFO_CURR_PTR (0x1485) ++#define P_AIU_MEM_AIFIFO_CURR_PTR (volatile unsigned int *)((0x1485 << 2) + 0xffd00000) ++#define AIU_MEM_AIFIFO_END_PTR (0x1486) ++#define P_AIU_MEM_AIFIFO_END_PTR (volatile unsigned int *)((0x1486 << 2) + 0xffd00000) ++#define AIU_MEM_AIFIFO_BYTES_AVAIL (0x1487) ++#define P_AIU_MEM_AIFIFO_BYTES_AVAIL (volatile unsigned int *)((0x1487 << 2) + 0xffd00000) ++// AIFIFO FIFO Control ++// bit [15:11] unused ++// bit [10] use_level Set this bit to 1 to enable filling of the FIFO controlled by the buffer ++// level control. If this bit is 0, then use bit[1] to control the enabling of filling ++// bit [9] Data Ready. This bit is set when data can be popped ++// bit [8] fill busy This bit will be high when we're fetching data from the DDR memory ++// To reset this module, set cntl_enable = 0, and then wait for busy = 0. ++// After that you can pulse cntl_init to start over ++// bit [7] cntl_endian_jic Just in case endian. last minute byte swap of the data out of ++// the FIFO to getbit ++// bit [6] unused ++// bits [5:3] endian: see $lib/rtl/ddr_endian.v ++// bit [2] cntl_empty_en Set to 1 to enable reading the DDR memory FIFO and filling the pipeline to get-bit ++// Set cntl_empty_en = cntl_fill_en = 0 when pulsing cntl_init ++// bit [1] cntl_fill_en Set to 1 to enable reading data from DDR memory ++// bit [0] cntl_init: After setting the read pointers, sizes, channel masks ++// and read masks, set this bit to 1 and then to 0 ++// NOTE: You don't need to pulse cntl_init if only the start address is ++// being changed ++#define AIU_MEM_AIFIFO_CONTROL (0x1488) ++#define P_AIU_MEM_AIFIFO_CONTROL (volatile unsigned int *)((0x1488 << 2) + 0xffd00000) ++// -------------------------------------------- ++// AIFIFO Buffer Level Manager ++// -------------------------------------------- ++#define AIU_MEM_AIFIFO_MAN_WP (0x1489) ++#define P_AIU_MEM_AIFIFO_MAN_WP (volatile unsigned int *)((0x1489 << 2) + 0xffd00000) ++#define AIU_MEM_AIFIFO_MAN_RP (0x148a) ++#define P_AIU_MEM_AIFIFO_MAN_RP (volatile unsigned int *)((0x148a << 2) + 0xffd00000) ++#define AIU_MEM_AIFIFO_LEVEL (0x148b) ++#define P_AIU_MEM_AIFIFO_LEVEL (volatile unsigned int *)((0x148b << 2) + 0xffd00000) ++// ++// bit [1] manual mode Set to 1 for manual write pointer mode ++// bit [0] Init Set high then low after everything has been initialized ++#define AIU_MEM_AIFIFO_BUF_CNTL (0x148c) ++#define P_AIU_MEM_AIFIFO_BUF_CNTL (volatile unsigned int *)((0x148c << 2) + 0xffd00000) ++#define AIU_MEM_AIFIFO_BUF_WRAP_COUNT (0x148d) ++#define P_AIU_MEM_AIFIFO_BUF_WRAP_COUNT (volatile unsigned int *)((0x148d << 2) + 0xffd00000) ++#define AIU_MEM_AIFIFO2_BUF_WRAP_COUNT (0x148e) ++#define P_AIU_MEM_AIFIFO2_BUF_WRAP_COUNT (volatile unsigned int *)((0x148e << 2) + 0xffd00000) ++// bit 29:24 A_brst_num ++// bit 21:16 A_id ++// bit 15:0 level_hold ++#define AIU_MEM_AIFIFO_MEM_CTL (0x148f) ++#define P_AIU_MEM_AIFIFO_MEM_CTL (volatile unsigned int *)((0x148f << 2) + 0xffd00000) ++// bit 31:16 -- drop_bytes ++// bit 15:14 -- drop_status (Read-Only) ++// bit 13:12 -- sync_match_position (Read-Only) ++// bit 11:6 -- reserved ++// bit 5:4 -- TIME_STAMP_NUMBER, 0-32bits, 1-64bits, 2-96bits, 3-128bits ++// bit 3 -- stamp_soft_reset ++// bit 2 -- TIME_STAMP_length_enable ++// bit 1 -- TIME_STAMP_sync64_enable ++// bit 0 -- TIME_STAMP_enable ++#define AIFIFO_TIME_STAMP_CNTL (0x1490) ++#define P_AIFIFO_TIME_STAMP_CNTL (volatile unsigned int *)((0x1490 << 2) + 0xffd00000) ++// bit 31:0 -- TIME_STAMP_SYNC_CODE_0 ++#define AIFIFO_TIME_STAMP_SYNC_0 (0x1491) ++#define P_AIFIFO_TIME_STAMP_SYNC_0 (volatile unsigned int *)((0x1491 << 2) + 0xffd00000) ++// bit 31:0 -- TIME_STAMP_SYNC_CODE_1 ++#define AIFIFO_TIME_STAMP_SYNC_1 (0x1492) ++#define P_AIFIFO_TIME_STAMP_SYNC_1 (volatile unsigned int *)((0x1492 << 2) + 0xffd00000) ++// bit 31:0 TIME_STAMP_0 ++#define AIFIFO_TIME_STAMP_0 (0x1493) ++#define P_AIFIFO_TIME_STAMP_0 (volatile unsigned int *)((0x1493 << 2) + 0xffd00000) ++// bit 31:0 TIME_STAMP_1 ++#define AIFIFO_TIME_STAMP_1 (0x1494) ++#define P_AIFIFO_TIME_STAMP_1 (volatile unsigned int *)((0x1494 << 2) + 0xffd00000) ++// bit 31:0 TIME_STAMP_2 ++#define AIFIFO_TIME_STAMP_2 (0x1495) ++#define P_AIFIFO_TIME_STAMP_2 (volatile unsigned int *)((0x1495 << 2) + 0xffd00000) ++// bit 31:0 TIME_STAMP_3 ++#define AIFIFO_TIME_STAMP_3 (0x1496) ++#define P_AIFIFO_TIME_STAMP_3 (volatile unsigned int *)((0x1496 << 2) + 0xffd00000) ++// bit 31:0 TIME_STAMP_LENGTH ++#define AIFIFO_TIME_STAMP_LENGTH (0x1497) ++#define P_AIFIFO_TIME_STAMP_LENGTH (volatile unsigned int *)((0x1497 << 2) + 0xffd00000) ++// bit 31:16 -- drop_bytes ++// bit 15:14 -- drop_status (Read-Only) ++// bit 13:12 -- sync_match_position (Read-Only) ++// bit 11:6 -- reserved ++// bit 5:4 -- TIME_STAMP_NUMBER, 0-32bits, 1-64bits, 2-96bits, 3-128bits ++// bit 3 -- stamp_soft_reset ++// bit 2 -- TIME_STAMP_length_enable ++// bit 1 -- TIME_STAMP_sync64_enable ++// bit 0 -- TIME_STAMP_enable ++#define AIFIFO2_TIME_STAMP_CNTL (0x1498) ++#define P_AIFIFO2_TIME_STAMP_CNTL (volatile unsigned int *)((0x1498 << 2) + 0xffd00000) ++// bit 31:0 -- TIME_STAMP_SYNC_CODE_0 ++#define AIFIFO2_TIME_STAMP_SYNC_0 (0x1499) ++#define P_AIFIFO2_TIME_STAMP_SYNC_0 (volatile unsigned int *)((0x1499 << 2) + 0xffd00000) ++// bit 31:0 -- TIME_STAMP_SYNC_CODE_1 ++#define AIFIFO2_TIME_STAMP_SYNC_1 (0x149a) ++#define P_AIFIFO2_TIME_STAMP_SYNC_1 (volatile unsigned int *)((0x149a << 2) + 0xffd00000) ++// bit 31:0 TIME_STAMP_0 ++#define AIFIFO2_TIME_STAMP_0 (0x149b) ++#define P_AIFIFO2_TIME_STAMP_0 (volatile unsigned int *)((0x149b << 2) + 0xffd00000) ++// bit 31:0 TIME_STAMP_1 ++#define AIFIFO2_TIME_STAMP_1 (0x149c) ++#define P_AIFIFO2_TIME_STAMP_1 (volatile unsigned int *)((0x149c << 2) + 0xffd00000) ++// bit 31:0 TIME_STAMP_2 ++#define AIFIFO2_TIME_STAMP_2 (0x149d) ++#define P_AIFIFO2_TIME_STAMP_2 (volatile unsigned int *)((0x149d << 2) + 0xffd00000) ++// bit 31:0 TIME_STAMP_3 ++#define AIFIFO2_TIME_STAMP_3 (0x149e) ++#define P_AIFIFO2_TIME_STAMP_3 (volatile unsigned int *)((0x149e << 2) + 0xffd00000) ++// bit 31:0 TIME_STAMP_LENGTH ++#define AIFIFO2_TIME_STAMP_LENGTH (0x149f) ++#define P_AIFIFO2_TIME_STAMP_LENGTH (volatile unsigned int *)((0x149f << 2) + 0xffd00000) ++// bit 31:16 -- drop_bytes ++// bit 15:14 -- drop_status (Read-Only) ++// bit 13:12 -- sync_match_position (Read-Only) ++// bit 11:6 -- reserved ++// bit 5:4 -- TIME_STAMP_NUMBER, 0-32bits, 1-64bits, 2-96bits, 3-128bits ++// bit 3 -- stamp_soft_reset ++// bit 2 -- TIME_STAMP_length_enable ++// bit 1 -- TIME_STAMP_sync64_enable ++// bit 0 -- TIME_STAMP_enable ++#define IEC958_TIME_STAMP_CNTL (0x14a0) ++#define P_IEC958_TIME_STAMP_CNTL (volatile unsigned int *)((0x14a0 << 2) + 0xffd00000) ++// bit 31:0 -- TIME_STAMP_SYNC_CODE_0 ++#define IEC958_TIME_STAMP_SYNC_0 (0x14a1) ++#define P_IEC958_TIME_STAMP_SYNC_0 (volatile unsigned int *)((0x14a1 << 2) + 0xffd00000) ++// bit 31:0 -- TIME_STAMP_SYNC_CODE_1 ++#define IEC958_TIME_STAMP_SYNC_1 (0x14a2) ++#define P_IEC958_TIME_STAMP_SYNC_1 (volatile unsigned int *)((0x14a2 << 2) + 0xffd00000) ++// bit 31:0 TIME_STAMP_0 ++#define IEC958_TIME_STAMP_0 (0x14a3) ++#define P_IEC958_TIME_STAMP_0 (volatile unsigned int *)((0x14a3 << 2) + 0xffd00000) ++// bit 31:0 TIME_STAMP_1 ++#define IEC958_TIME_STAMP_1 (0x14a4) ++#define P_IEC958_TIME_STAMP_1 (volatile unsigned int *)((0x14a4 << 2) + 0xffd00000) ++// bit 31:0 TIME_STAMP_2 ++#define IEC958_TIME_STAMP_2 (0x14a5) ++#define P_IEC958_TIME_STAMP_2 (volatile unsigned int *)((0x14a5 << 2) + 0xffd00000) ++// bit 31:0 TIME_STAMP_3 ++#define IEC958_TIME_STAMP_3 (0x14a6) ++#define P_IEC958_TIME_STAMP_3 (volatile unsigned int *)((0x14a6 << 2) + 0xffd00000) ++// bit 31:0 TIME_STAMP_LENGTH ++#define IEC958_TIME_STAMP_LENGTH (0x14a7) ++#define P_IEC958_TIME_STAMP_LENGTH (volatile unsigned int *)((0x14a7 << 2) + 0xffd00000) ++// bit 29:24 A_brst_num ++// bit 21:16 A_id ++// bit 15:0 level_hold ++#define AIU_MEM_AIFIFO2_MEM_CTL (0x14a8) ++#define P_AIU_MEM_AIFIFO2_MEM_CTL (volatile unsigned int *)((0x14a8 << 2) + 0xffd00000) ++// -------------------------------------------- ++// CBUS_DDR interface for I2S_FAST ++// -------------------------------------------- ++// bit[31:26] unused ++// bit[25] A_req level ++// bit[24] data_req If this bit is 1, then (a_req_cnt != 'h0) ++// bit[23:16] a_req_cnt This value corresponds to the number of 32-bit words ++// requested by the i2s_fast() module ++// bit[15:7] unused ++// bit[6] Set this bit to mux in the cbus_ddr_interface ++// bit[5] Set this bit to allow back to back A_req's to be serviced ++// bit[4] Set this bit to generate an IRQ on the first A_req ++// If this bit is 0, then an IRQ is generated after all requests ++// are completed and how many 32-bit words to send is calculated. ++// bit[3:1] Endian ++// bit[0] Set this bit enable the cbus_ddr_interface ++#define AIU_I2S_CBUS_DDR_CNTL (0x14a9) ++#define P_AIU_I2S_CBUS_DDR_CNTL (volatile unsigned int *)((0x14a9 << 2) + 0xffd00000) ++// 32-bit data to write to the cbus_ddr interface ++#define AIU_I2S_CBUS_DDR_WDATA (0x14aa) ++#define P_AIU_I2S_CBUS_DDR_WDATA (volatile unsigned int *)((0x14aa << 2) + 0xffd00000) ++// First address associated with the first request by the i2s_fast() to read DDR data ++#define AIU_I2S_CBUS_DDR_ADDR (0x14ab) ++#define P_AIU_I2S_CBUS_DDR_ADDR (volatile unsigned int *)((0x14ab << 2) + 0xffd00000) ++// ++// Closing file: aregs.h ++// ++//======================================================================== ++// CDROM Interface (12'h600 - 12'h6ff) ++// ++//======================================================================== ++//======================================================================== ++// registers for ge2d (12'h8a0 - 12'h8ff) ++//======================================================================== ++////`include "ge2d_regs.h" // not in cbus domain any more, it is located in vapb3 bus now ++//======================================================================== ++// DSP Co-Processor Registers ( 8'he00 - 12'hfff) ++// ++//======================================================================== ++// Duplicate Address: When actually used ++// please move to a different address ++// `define AUDIO_COP_CTL1 12'hf00 // r & w; r-> 6'h00,bsmod[2:0],acmod[2:0],lfeon,nfchans[2:0] ++// ++// Incorrect format....should be 8'bits only ++// ++// Removed by Chris Maslyar `define AUDIO_COP_CTL2 12'hf01 // r & w; r-> frame_size[12:0],dsurmod[1:0] ++// Removed by Chris Maslyar ++// Removed by Chris Maslyar // f02 -f0d are special regs , not in ac3_reg.h, but used by CPU for AC3 operations ++// Removed by Chris Maslyar ++// Removed by Chris Maslyar `define OPERAND_M_CTL 12'hf02 ++// Removed by Chris Maslyar `define OPERAND1_ADDR 12'hf03 ++// Removed by Chris Maslyar `define OPERAND2_ADDR 12'hf04 ++// Removed by Chris Maslyar `define RESULT_M_CTL 12'hf05 ++// Removed by Chris Maslyar `define RESULT1_ADDR 12'hf06 ++// Removed by Chris Maslyar `define RESULT2_ADDR 12'hf07 ++// Removed by Chris Maslyar `define ADD_SHFT_CTL 12'hf08 ++// Removed by Chris Maslyar `define OPERAND_ONE_H 12'hf09 ++// Removed by Chris Maslyar `define OPERAND_ONE_L 12'hf0a ++// Removed by Chris Maslyar `define OPERAND_TWO_H 12'hf0b ++// Removed by Chris Maslyar `define OPERAND_TWO_L 12'hf0c ++// Removed by Chris Maslyar `define RESULT_H 12'hf0d ++// Removed by Chris Maslyar ++// Removed by Chris Maslyar ++// Removed by Chris Maslyar `define RESULT_M 12'hf0e // r & w; ac3_reg_14 ++// Removed by Chris Maslyar ++// Removed by Chris Maslyar // special reg ++// Removed by Chris Maslyar `define RESULT_L 12'hf0f ++// Removed by Chris Maslyar ++// Removed by Chris Maslyar // ++// Removed by Chris Maslyar `define WMEM_R_PTR 12'hf10 // r & w ; endmant0 &1 ++// Removed by Chris Maslyar ++// Removed by Chris Maslyar `define WMEM_W_PTR 12'hf11 ++// Removed by Chris Maslyar `define AUDIO_LAYER 12'hf20 ++// Removed by Chris Maslyar `define AC3_DECODING 12'hf21 ++// Removed by Chris Maslyar `define AC3_DYNAMIC 12'hf22 ++// Removed by Chris Maslyar `define AC3_MELODY 12'hf23 ++// Removed by Chris Maslyar `define AC3_VOCAL 12'hf24 ++//====================================== ++// CPU Assist module ++// ++//====================================== ++// ----------------------------------------------- ++// CBUS_BASE: ASSIST_CBUS_BASE = 0x20 ++// ----------------------------------------------- ++//`define ASSIST_AMR_MBOX1_INT 8'h4d ++//`define ASSIST_AMR_MBOX2_INT 8'h4e ++#define ASSIST_AMR_SCRATCH0 (0x204f) ++#define P_ASSIST_AMR_SCRATCH0 (volatile unsigned int *)((0x204f << 2) + 0xffd00000) ++#define ASSIST_AMR_SCRATCH1 (0x2050) ++#define P_ASSIST_AMR_SCRATCH1 (volatile unsigned int *)((0x2050 << 2) + 0xffd00000) ++#define ASSIST_AMR_SCRATCH2 (0x2051) ++#define P_ASSIST_AMR_SCRATCH2 (volatile unsigned int *)((0x2051 << 2) + 0xffd00000) ++#define ASSIST_AMR_SCRATCH3 (0x2052) ++#define P_ASSIST_AMR_SCRATCH3 (volatile unsigned int *)((0x2052 << 2) + 0xffd00000) ++#define ASSIST_HW_REV (0x2053) ++#define P_ASSIST_HW_REV (volatile unsigned int *)((0x2053 << 2) + 0xffd00000) ++//`define ASSIST_CBUS_ARB 8'h54 ++#define ASSIST_POR_CONFIG (0x2055) ++#define P_ASSIST_POR_CONFIG (volatile unsigned int *)((0x2055 << 2) + 0xffd00000) ++#define ASSIST_SPARE16_REG1 (0x2056) ++#define P_ASSIST_SPARE16_REG1 (volatile unsigned int *)((0x2056 << 2) + 0xffd00000) ++#define ASSIST_SPARE16_REG2 (0x2057) ++#define P_ASSIST_SPARE16_REG2 (volatile unsigned int *)((0x2057 << 2) + 0xffd00000) ++#define ASSIST_SPARE8_REG1 (0x2058) ++#define P_ASSIST_SPARE8_REG1 (volatile unsigned int *)((0x2058 << 2) + 0xffd00000) ++#define ASSIST_SPARE8_REG2 (0x2059) ++#define P_ASSIST_SPARE8_REG2 (volatile unsigned int *)((0x2059 << 2) + 0xffd00000) ++// Duplicate Address...when used please move to a new address ++// `define TO_AMRISC_REG 8'h59 // for amrisc ++#define ASSIST_SPARE8_REG3 (0x205a) ++#define P_ASSIST_SPARE8_REG3 (volatile unsigned int *)((0x205a << 2) + 0xffd00000) ++// Duplicate Address...when used please move to a new address ++// `define FROM_AMRISC_REG 8'h5a // for amrisc ++// Duplicate Address...when used please move to a new address ++// `define MPEG2_DECODER_CONTROL 8'h5b // for amrisc ++#define AC3_CTRL_REG1 (0x205b) ++#define P_AC3_CTRL_REG1 (volatile unsigned int *)((0x205b << 2) + 0xffd00000) ++#define AC3_CTRL_REG2 (0x205c) ++#define P_AC3_CTRL_REG2 (volatile unsigned int *)((0x205c << 2) + 0xffd00000) ++#define AC3_CTRL_REG3 (0x205d) ++#define P_AC3_CTRL_REG3 (volatile unsigned int *)((0x205d << 2) + 0xffd00000) ++#define AC3_CTRL_REG4 (0x205e) ++#define P_AC3_CTRL_REG4 (volatile unsigned int *)((0x205e << 2) + 0xffd00000) ++//`define ASSIST_PMEM_SPLIT 8'h5f ++#define ASSIST_GEN_CNTL (0x2068) ++#define P_ASSIST_GEN_CNTL (volatile unsigned int *)((0x2068 << 2) + 0xffd00000) ++#define EE_ASSIST_MBOX0_IRQ_REG (0x2070) ++#define P_EE_ASSIST_MBOX0_IRQ_REG (volatile unsigned int *)((0x2070 << 2) + 0xffd00000) ++#define EE_ASSIST_MBOX0_CLR_REG (0x2071) ++#define P_EE_ASSIST_MBOX0_CLR_REG (volatile unsigned int *)((0x2071 << 2) + 0xffd00000) ++#define EE_ASSIST_MBOX0_MASK (0x2072) ++#define P_EE_ASSIST_MBOX0_MASK (volatile unsigned int *)((0x2072 << 2) + 0xffd00000) ++#define EE_ASSIST_MBOX0_FIQ_SEL (0x2073) ++#define P_EE_ASSIST_MBOX0_FIQ_SEL (volatile unsigned int *)((0x2073 << 2) + 0xffd00000) ++#define EE_ASSIST_MBOX1_IRQ_REG (0x2074) ++#define P_EE_ASSIST_MBOX1_IRQ_REG (volatile unsigned int *)((0x2074 << 2) + 0xffd00000) ++#define EE_ASSIST_MBOX1_CLR_REG (0x2075) ++#define P_EE_ASSIST_MBOX1_CLR_REG (volatile unsigned int *)((0x2075 << 2) + 0xffd00000) ++#define EE_ASSIST_MBOX1_MASK (0x2076) ++#define P_EE_ASSIST_MBOX1_MASK (volatile unsigned int *)((0x2076 << 2) + 0xffd00000) ++#define EE_ASSIST_MBOX1_FIQ_SEL (0x2077) ++#define P_EE_ASSIST_MBOX1_FIQ_SEL (volatile unsigned int *)((0x2077 << 2) + 0xffd00000) ++#define EE_ASSIST_MBOX2_IRQ_REG (0x2078) ++#define P_EE_ASSIST_MBOX2_IRQ_REG (volatile unsigned int *)((0x2078 << 2) + 0xffd00000) ++#define EE_ASSIST_MBOX2_CLR_REG (0x2079) ++#define P_EE_ASSIST_MBOX2_CLR_REG (volatile unsigned int *)((0x2079 << 2) + 0xffd00000) ++#define EE_ASSIST_MBOX2_MASK (0x207a) ++#define P_EE_ASSIST_MBOX2_MASK (volatile unsigned int *)((0x207a << 2) + 0xffd00000) ++#define EE_ASSIST_MBOX2_FIQ_SEL (0x207b) ++#define P_EE_ASSIST_MBOX2_FIQ_SEL (volatile unsigned int *)((0x207b << 2) + 0xffd00000) ++#define EE_ASSIST_MBOX3_IRQ_REG (0x207c) ++#define P_EE_ASSIST_MBOX3_IRQ_REG (volatile unsigned int *)((0x207c << 2) + 0xffd00000) ++#define EE_ASSIST_MBOX3_CLR_REG (0x207d) ++#define P_EE_ASSIST_MBOX3_CLR_REG (volatile unsigned int *)((0x207d << 2) + 0xffd00000) ++#define EE_ASSIST_MBOX3_MASK (0x207e) ++#define P_EE_ASSIST_MBOX3_MASK (volatile unsigned int *)((0x207e << 2) + 0xffd00000) ++#define EE_ASSIST_MBOX3_FIQ_SEL (0x207f) ++#define P_EE_ASSIST_MBOX3_FIQ_SEL (volatile unsigned int *)((0x207f << 2) + 0xffd00000) ++// ----------------------------------------------- ++// CBUS_BASE: AUD_CBUS_BASE = 0x34 ++// ----------------------------------------------- ++// ---------------------------- ++// AUDIN (64) ++// ---------------------------- ++#define AUDIN_SPDIF_MODE (0x3400) ++#define P_AUDIN_SPDIF_MODE (volatile unsigned int *)((0x3400 << 2) + 0xffd00000) ++ #define SPDIF_EN 31 ++ #define SPDIF_INT_EN 30 ++ #define SPDIF_BURST_PRE_INT_EN 29 ++ #define SPDIF_TIE_0 24 ++ #define SPDIF_SAMPLE_SEL 23 ++ #define SPDIF_REVERSE_EN 22 ++ #define SPDIF_BIT_ORDER 20 ++ #define SPDIF_CHNL_ORDER 19 ++ #define SPDIF_DATA_TYPE_SEL 18 ++ #define SPDIF_XTDCLK_UPD_ITVL 14 //16:14 ++ #define SPDIF_CLKNUM_54U 0 //13:0 ++#define AUDIN_SPDIF_FS_CLK_RLTN (0x3401) ++#define P_AUDIN_SPDIF_FS_CLK_RLTN (volatile unsigned int *)((0x3401 << 2) + 0xffd00000) ++ #define SPDIF_CLKNUM_192K 24 //29:24 ++ #define SPDIF_CLKNUM_96K 18 //23:18 ++ #define SPDIF_CLKNUM_48K 12 //17:12 ++ #define SPDIF_CLKNUM_44K 6 // 11:6 ++ #define SPDIF_CLKNUM_32K 0 // 5:0 ++#define AUDIN_SPDIF_CHNL_STS_A (0x3402) ++#define P_AUDIN_SPDIF_CHNL_STS_A (volatile unsigned int *)((0x3402 << 2) + 0xffd00000) ++#define AUDIN_SPDIF_CHNL_STS_B (0x3403) ++#define P_AUDIN_SPDIF_CHNL_STS_B (volatile unsigned int *)((0x3403 << 2) + 0xffd00000) ++#define AUDIN_SPDIF_MISC (0x3404) ++#define P_AUDIN_SPDIF_MISC (volatile unsigned int *)((0x3404 << 2) + 0xffd00000) ++#define AUDIN_SPDIF_NPCM_PCPD (0x3405) ++#define P_AUDIN_SPDIF_NPCM_PCPD (volatile unsigned int *)((0x3405 << 2) + 0xffd00000) ++#define AUDIN_SPDIF_END (0x340f) ++#define P_AUDIN_SPDIF_END (volatile unsigned int *)((0x340f << 2) + 0xffd00000) ++#define AUDIN_I2SIN_CTRL (0x3410) ++#define P_AUDIN_I2SIN_CTRL (volatile unsigned int *)((0x3410 << 2) + 0xffd00000) ++ #define I2SIN_DIR 0 // I2S CLK and LRCLK direction. 0 : input 1 : output. ++ #define I2SIN_CLK_SEL 1 // I2S clk selection : 0 : from pad input. 1 : from AIU. ++ #define I2SIN_LRCLK_SEL 2 ++ #define I2SIN_POS_SYNC 3 ++ #define I2SIN_LRCLK_SKEW 4 // 6:4 ++ #define I2SIN_LRCLK_INVT 7 ++ #define I2SIN_SIZE 8 //9:8 : 0 16 bit. 1 : 18 bits 2 : 20 bits 3 : 24bits. ++ #define I2SIN_CHAN_EN 10 //13:10. ++ #define I2SIN_EN 15 ++// Bit 31:15 Rsrv. ++// Bit 14:12 RW HDMI-RX SPDIF channel status select to report on AUDIN_DECODE_CHANNEL_STATUS_A_*: 0=select channel 1; 1=channel 2; ...; 7=channel 8. ++// Bit 11: 8 RW HDMI-RX SPDIF channel status extraction enable, 1-bit per channel pair. To enable, SPDIF input source also must select 1. ++// Bit 7: 6 Rsrv. ++// Bit 5: 4 RW SPDIF input source select. 0=Default, select chip external; 1=select HDMI RX output; 2/3=Rsrv. ++// Bit 3: 2 Rsrv. ++// Bit 1: 0 RW I2S input source select. 0=Default, select chip external; 1=select audio codec output; 2=select HDMI RX output; 3=Rsrv. ++#define AUDIN_SOURCE_SEL (0x3411) ++#define P_AUDIN_SOURCE_SEL (volatile unsigned int *)((0x3411 << 2) + 0xffd00000) ++// The following registers control the new alternative decoder -- hdmi_tx_audio_decoder, in audin module ++// Bit 31:25 Rsrv. ++// Bit 24 RW SPDIF enable. ++// Bit 23:22 Rsrv. ++// Bit 21:20 RW i2s_block_start_src: 0=left channel 0 is approved as block start generator, ..., 3=left channel 3 is the block start generator. ++// Bit 19:17 Rsrv. ++// Bit 16 RW I2S enable. ++// Bit 15: 8 RW audio_channel_alloc: Usage indication of up to 8 channels. If the correspoinding bit is 1, then this channel is used. ++// E.g.: In 2-channel audio, it is 00000011 ++// Bit 7 RW hdmi_tx_audio_decoder input sel: 0=SPDIF; 1=I2S. ++// Bit 6 RW i2s_channel_config: 0=2-channel; 1=8-channel. ++// Bit 5: 4 RW i2s_format_select: 0=left-justify; 1=right-justify; 2=I2S format; 3=DSP format. ++// Bit 3: 2 RW i2s_bit_width: 0=16-bit; 1=18-bit; 2=20-bit; 3=24-bit. ++// Bit 1 RW ws polarity: 0=0 is left, 1 is right; 1=1 is left, 0 is right. ++// Bit 0 RW For SPDIF mode, 0=use channel status from input data; 1=use channel status from registers; ++// For I2S mode, 0=one-bit audio; 1=I2S. ++#define AUDIN_DECODE_FORMAT (0x3412) ++#define P_AUDIN_DECODE_FORMAT (volatile unsigned int *)((0x3412 << 2) + 0xffd00000) ++// Bit 31:25 Rsrv. ++// Bit 24 R channel_status stablility indicator. ++// Bit 23:16 RW Valid bits for audio sample packet. [7] for valid_sp3_right, [6] for valid_sp3_left, ..., [1] for valid_sp0_right, [0] for valid_sp0_left. ++// Bit 15: 8 RW User bits for audio sample packet. [7] for user_sp3_right, [6] for user_sp3_left, ..., [1] for user_sp0_right, [0] for user_sp0_left. ++// Bit 7: 4 RW cntl_init_discard: Number of initial hdmi_tx_audio_decoder samples to discard from reset. ++// Bit 3 RW cntl_invert_i2s_lrclk: Invert WS before input to hdmi_tx_audio_decoder. ++// Bit 2 RW audio_valid_overwrite: Valid bit selection in audio packet. 0=use input data; 1=use ++// Bit 1 RW audio_user_overwrite: User bit selection in audio packet. 0=use input data; 1=use ++// Bit 0 RW audio_sample_valid: sample non-flat indication. 0=flat, non-valid; 1=non-flat, valid. ++#define AUDIN_DECODE_CONTROL_STATUS (0x3413) ++#define P_AUDIN_DECODE_CONTROL_STATUS (volatile unsigned int *)((0x3413 << 2) + 0xffd00000) ++// IEC958 192-bit channel status: muxed between 8 channels, channel selection by AUDIN_SOURCE_SEL[14:12] ++#define AUDIN_DECODE_CHANNEL_STATUS_A_0 (0x3414) ++#define P_AUDIN_DECODE_CHANNEL_STATUS_A_0 (volatile unsigned int *)((0x3414 << 2) + 0xffd00000) ++#define AUDIN_DECODE_CHANNEL_STATUS_A_1 (0x3415) ++#define P_AUDIN_DECODE_CHANNEL_STATUS_A_1 (volatile unsigned int *)((0x3415 << 2) + 0xffd00000) ++#define AUDIN_DECODE_CHANNEL_STATUS_A_2 (0x3416) ++#define P_AUDIN_DECODE_CHANNEL_STATUS_A_2 (volatile unsigned int *)((0x3416 << 2) + 0xffd00000) ++#define AUDIN_DECODE_CHANNEL_STATUS_A_3 (0x3417) ++#define P_AUDIN_DECODE_CHANNEL_STATUS_A_3 (volatile unsigned int *)((0x3417 << 2) + 0xffd00000) ++#define AUDIN_DECODE_CHANNEL_STATUS_A_4 (0x3418) ++#define P_AUDIN_DECODE_CHANNEL_STATUS_A_4 (volatile unsigned int *)((0x3418 << 2) + 0xffd00000) ++#define AUDIN_DECODE_CHANNEL_STATUS_A_5 (0x3419) ++#define P_AUDIN_DECODE_CHANNEL_STATUS_A_5 (volatile unsigned int *)((0x3419 << 2) + 0xffd00000) ++#define AUDIN_FIFO0_START (0x3420) ++#define P_AUDIN_FIFO0_START (volatile unsigned int *)((0x3420 << 2) + 0xffd00000) ++#define AUDIN_FIFO0_END (0x3421) ++#define P_AUDIN_FIFO0_END (volatile unsigned int *)((0x3421 << 2) + 0xffd00000) ++#define AUDIN_FIFO0_PTR (0x3422) ++#define P_AUDIN_FIFO0_PTR (volatile unsigned int *)((0x3422 << 2) + 0xffd00000) ++#define AUDIN_FIFO0_INTR (0x3423) ++#define P_AUDIN_FIFO0_INTR (volatile unsigned int *)((0x3423 << 2) + 0xffd00000) ++#define AUDIN_FIFO0_RDPTR (0x3424) ++#define P_AUDIN_FIFO0_RDPTR (volatile unsigned int *)((0x3424 << 2) + 0xffd00000) ++#define AUDIN_FIFO0_CTRL (0x3425) ++#define P_AUDIN_FIFO0_CTRL (volatile unsigned int *)((0x3425 << 2) + 0xffd00000) ++ #define AUDIN_FIFO0_EN 0 ++ #define AUDIN_FIFO0_RST 1 ++ #define AUDIN_FIFO0_LOAD 2 //write 1 to load address to AUDIN_FIFO0. ++ ++ #define AUDIN_FIFO0_DIN_SEL 3 ++ // 0 spdifIN ++ // 1 i2Sin ++ // 2 PCMIN ++ // 3 HDMI in ++ // 4 DEMODULATOR IN ++ #define AUDIN_FIFO0_ENDIAN 8 //10:8 data endian control. ++ #define AUDIN_FIFO0_CHAN 11 //14:11 channel number. in M1 suppose there's only 1 channel and 2 channel. ++ #define AUDIN_FIFO0_UG 15 // urgent request enable. ++ #define AUDIN_FIFO0_HOLD0_EN 19 ++ #define AUDIN_FIFO0_HOLD1_EN 20 ++ #define AUDIN_FIFO0_HOLD2_EN 21 ++ #define AUDIN_FIFO0_HOLD0_SEL 22 // 23:22 ++ #define AUDIN_FIFO0_HOLD1_SEL 24 // 25:24 ++ #define AUDIN_FIFO0_HOLD2_SEL 26 // 27:26 ++ #define AUDIN_FIFO0_HOLD_LVL 28 // 27:26 ++ ++ ++#define AUDIN_FIFO0_CTRL1 (0x3426) ++#define P_AUDIN_FIFO0_CTRL1 (volatile unsigned int *)((0x3426 << 2) + 0xffd00000) ++#define AUDIN_FIFO0_LVL0 (0x3427) ++#define P_AUDIN_FIFO0_LVL0 (volatile unsigned int *)((0x3427 << 2) + 0xffd00000) ++#define AUDIN_FIFO0_LVL1 (0x3428) ++#define P_AUDIN_FIFO0_LVL1 (volatile unsigned int *)((0x3428 << 2) + 0xffd00000) ++#define AUDIN_FIFO0_LVL2 (0x3429) ++#define P_AUDIN_FIFO0_LVL2 (volatile unsigned int *)((0x3429 << 2) + 0xffd00000) ++#define AUDIN_FIFO0_REQID (0x3430) ++#define P_AUDIN_FIFO0_REQID (volatile unsigned int *)((0x3430 << 2) + 0xffd00000) ++#define AUDIN_FIFO0_WRAP (0x3431) ++#define P_AUDIN_FIFO0_WRAP (volatile unsigned int *)((0x3431 << 2) + 0xffd00000) ++#define AUDIN_FIFO1_START (0x3433) ++#define P_AUDIN_FIFO1_START (volatile unsigned int *)((0x3433 << 2) + 0xffd00000) ++#define AUDIN_FIFO1_END (0x3434) ++#define P_AUDIN_FIFO1_END (volatile unsigned int *)((0x3434 << 2) + 0xffd00000) ++#define AUDIN_FIFO1_PTR (0x3435) ++#define P_AUDIN_FIFO1_PTR (volatile unsigned int *)((0x3435 << 2) + 0xffd00000) ++#define AUDIN_FIFO1_INTR (0x3436) ++#define P_AUDIN_FIFO1_INTR (volatile unsigned int *)((0x3436 << 2) + 0xffd00000) ++#define AUDIN_FIFO1_RDPTR (0x3437) ++#define P_AUDIN_FIFO1_RDPTR (volatile unsigned int *)((0x3437 << 2) + 0xffd00000) ++#define AUDIN_FIFO1_CTRL (0x3438) ++#define P_AUDIN_FIFO1_CTRL (volatile unsigned int *)((0x3438 << 2) + 0xffd00000) ++ #define AUDIN_FIFO1_EN 0 ++ #define AUDIN_FIFO1_RST 1 ++ #define AUDIN_FIFO1_LOAD 2 //write 1 to load address to AUDIN_FIFO0. ++ ++ #define AUDIN_FIFO1_DIN_SEL 3 ++ // 0 spdifIN ++ // 1 i2Sin ++ // 2 PCMIN ++ // 3 HDMI in ++ // 4 DEMODULATOR IN ++ #define AUDIN_FIFO1_ENDIAN 8 //10:8 data endian control. ++ #define AUDIN_FIFO1_CHAN 11 //14:11 channel number. in M1 suppose there's only 1 channel and 2 channel. ++ #define AUDIN_FIFO1_UG 15 // urgent request enable. ++ #define AUDIN_FIFO1_HOLD0_EN 19 ++ #define AUDIN_FIFO1_HOLD1_EN 20 ++ #define AUDIN_FIFO1_HOLD2_EN 21 ++ #define AUDIN_FIFO1_HOLD0_SEL 22 // 23:22 ++ #define AUDIN_FIFO1_HOLD1_SEL 24 // 25:24 ++ #define AUDIN_FIFO1_HOLD2_SEL 26 // 27:26 ++ #define AUDIN_FIFO1_HOLD_LVL 28 // 27:26 ++#define AUDIN_FIFO1_CTRL1 (0x3439) ++#define P_AUDIN_FIFO1_CTRL1 (volatile unsigned int *)((0x3439 << 2) + 0xffd00000) ++#define AUDIN_FIFO1_LVL0 (0x3440) ++#define P_AUDIN_FIFO1_LVL0 (volatile unsigned int *)((0x3440 << 2) + 0xffd00000) ++#define AUDIN_FIFO1_LVL1 (0x3441) ++#define P_AUDIN_FIFO1_LVL1 (volatile unsigned int *)((0x3441 << 2) + 0xffd00000) ++#define AUDIN_FIFO1_LVL2 (0x3442) ++#define P_AUDIN_FIFO1_LVL2 (volatile unsigned int *)((0x3442 << 2) + 0xffd00000) ++#define AUDIN_FIFO1_REQID (0x3443) ++#define P_AUDIN_FIFO1_REQID (volatile unsigned int *)((0x3443 << 2) + 0xffd00000) ++#define AUDIN_FIFO1_WRAP (0x3444) ++#define P_AUDIN_FIFO1_WRAP (volatile unsigned int *)((0x3444 << 2) + 0xffd00000) ++#define AUDIN_FIFO2_START (0x3445) ++#define P_AUDIN_FIFO2_START (volatile unsigned int *)((0x3445 << 2) + 0xffd00000) ++#define AUDIN_FIFO2_END (0x3446) ++#define P_AUDIN_FIFO2_END (volatile unsigned int *)((0x3446 << 2) + 0xffd00000) ++#define AUDIN_FIFO2_PTR (0x3447) ++#define P_AUDIN_FIFO2_PTR (volatile unsigned int *)((0x3447 << 2) + 0xffd00000) ++#define AUDIN_FIFO2_INTR (0x3448) ++#define P_AUDIN_FIFO2_INTR (volatile unsigned int *)((0x3448 << 2) + 0xffd00000) ++#define AUDIN_FIFO2_RDPTR (0x3449) ++#define P_AUDIN_FIFO2_RDPTR (volatile unsigned int *)((0x3449 << 2) + 0xffd00000) ++#define AUDIN_FIFO2_CTRL (0x344a) ++#define P_AUDIN_FIFO2_CTRL (volatile unsigned int *)((0x344a << 2) + 0xffd00000) ++#define AUDIN_FIFO2_CTRL1 (0x344b) ++#define P_AUDIN_FIFO2_CTRL1 (volatile unsigned int *)((0x344b << 2) + 0xffd00000) ++#define AUDIN_FIFO2_LVL0 (0x344c) ++#define P_AUDIN_FIFO2_LVL0 (volatile unsigned int *)((0x344c << 2) + 0xffd00000) ++#define AUDIN_FIFO2_LVL1 (0x344d) ++#define P_AUDIN_FIFO2_LVL1 (volatile unsigned int *)((0x344d << 2) + 0xffd00000) ++#define AUDIN_FIFO2_LVL2 (0x344e) ++#define P_AUDIN_FIFO2_LVL2 (volatile unsigned int *)((0x344e << 2) + 0xffd00000) ++#define AUDIN_FIFO2_REQID (0x344f) ++#define P_AUDIN_FIFO2_REQID (volatile unsigned int *)((0x344f << 2) + 0xffd00000) ++#define AUDIN_FIFO2_WRAP (0x3450) ++#define P_AUDIN_FIFO2_WRAP (volatile unsigned int *)((0x3450 << 2) + 0xffd00000) ++#define AUDIN_INT_CTRL (0x3451) ++#define P_AUDIN_INT_CTRL (volatile unsigned int *)((0x3451 << 2) + 0xffd00000) ++#define AUDIN_FIFO_INT (0x3452) ++#define P_AUDIN_FIFO_INT (volatile unsigned int *)((0x3452 << 2) + 0xffd00000) ++#define PCMIN_CTRL0 (0x3460) ++#define P_PCMIN_CTRL0 (volatile unsigned int *)((0x3460 << 2) + 0xffd00000) ++#define PCMIN_CTRL1 (0x3461) ++#define P_PCMIN_CTRL1 (volatile unsigned int *)((0x3461 << 2) + 0xffd00000) ++#define PCMIN_CTRL2 (0x3462) ++#define P_PCMIN_CTRL2 (volatile unsigned int *)((0x3462 << 2) + 0xffd00000) ++//`define PCMIN1_CTRL0 8'h62 ++//`define PCMIN1_CTRL1 8'h63 ++#define PCMOUT_CTRL0 (0x3470) ++#define P_PCMOUT_CTRL0 (volatile unsigned int *)((0x3470 << 2) + 0xffd00000) ++#define PCMOUT_CTRL1 (0x3471) ++#define P_PCMOUT_CTRL1 (volatile unsigned int *)((0x3471 << 2) + 0xffd00000) ++#define PCMOUT_CTRL2 (0x3472) ++#define P_PCMOUT_CTRL2 (volatile unsigned int *)((0x3472 << 2) + 0xffd00000) ++#define PCMOUT_CTRL3 (0x3473) ++#define P_PCMOUT_CTRL3 (volatile unsigned int *)((0x3473 << 2) + 0xffd00000) ++#define PCMOUT_CTRL4 (0x3474) ++#define P_PCMOUT_CTRL4 (volatile unsigned int *)((0x3474 << 2) + 0xffd00000) ++//`define PCMOUT1_CTRL0 8'h74 ++//`define PCMOUT1_CTRL1 8'h75 ++//`define PCMOUT1_CTRL2 8'h76 ++//`define PCMOUT1_CTRL3 8'h77 ++#define AUDOUT_CTRL (0x3480) ++#define P_AUDOUT_CTRL (volatile unsigned int *)((0x3480 << 2) + 0xffd00000) ++#define AUDOUT_CTRL1 (0x3481) ++#define P_AUDOUT_CTRL1 (volatile unsigned int *)((0x3481 << 2) + 0xffd00000) ++#define AUDOUT_BUF0_STA (0x3482) ++#define P_AUDOUT_BUF0_STA (volatile unsigned int *)((0x3482 << 2) + 0xffd00000) ++#define AUDOUT_BUF0_EDA (0x3483) ++#define P_AUDOUT_BUF0_EDA (volatile unsigned int *)((0x3483 << 2) + 0xffd00000) ++#define AUDOUT_BUF0_WPTR (0x3484) ++#define P_AUDOUT_BUF0_WPTR (volatile unsigned int *)((0x3484 << 2) + 0xffd00000) ++#define AUDOUT_BUF1_STA (0x3485) ++#define P_AUDOUT_BUF1_STA (volatile unsigned int *)((0x3485 << 2) + 0xffd00000) ++#define AUDOUT_BUF1_EDA (0x3486) ++#define P_AUDOUT_BUF1_EDA (volatile unsigned int *)((0x3486 << 2) + 0xffd00000) ++#define AUDOUT_BUF1_WPTR (0x3487) ++#define P_AUDOUT_BUF1_WPTR (volatile unsigned int *)((0x3487 << 2) + 0xffd00000) ++#define AUDOUT_FIFO_RPTR (0x3488) ++#define P_AUDOUT_FIFO_RPTR (volatile unsigned int *)((0x3488 << 2) + 0xffd00000) ++#define AUDOUT_INTR_PTR (0x3489) ++#define P_AUDOUT_INTR_PTR (volatile unsigned int *)((0x3489 << 2) + 0xffd00000) ++#define AUDOUT_FIFO_STS (0x348a) ++#define P_AUDOUT_FIFO_STS (volatile unsigned int *)((0x348a << 2) + 0xffd00000) ++//`define AUDOUT1_CTRL 8'h90 ++//`define AUDOUT1_CTRL1 8'h91 ++//`define AUDOUT1_BUF0_STA 8'h92 ++//`define AUDOUT1_BUF0_EDA 8'h93 ++//`define AUDOUT1_BUF0_WPTR 8'h94 ++//`define AUDOUT1_BUF1_STA 8'h95 ++//`define AUDOUT1_BUF1_EDA 8'h96 ++//`define AUDOUT1_BUF1_WPTR 8'h97 ++//`define AUDOUT1_FIFO_RPTR 8'h98 ++//`define AUDOUT1_INTR_PTR 8'h99 ++//`define AUDOUT1_FIFO_STS 8'h9a ++//// Bit 31: 0 RW cntl_mute_val: Use this value during mute, if cntl_mute_mode=2. ++//`define AUDIN_MUTE_VAL 8'h35 ++#define AUDIN_HDMI_MEAS_CTRL (0x34a0) ++#define P_AUDIN_HDMI_MEAS_CTRL (volatile unsigned int *)((0x34a0 << 2) + 0xffd00000) ++#define AUDIN_HDMI_MEAS_CYCLES_M1 (0x34a1) ++#define P_AUDIN_HDMI_MEAS_CYCLES_M1 (volatile unsigned int *)((0x34a1 << 2) + 0xffd00000) ++#define AUDIN_HDMI_MEAS_INTR_MASKN (0x34a2) ++#define P_AUDIN_HDMI_MEAS_INTR_MASKN (volatile unsigned int *)((0x34a2 << 2) + 0xffd00000) ++#define AUDIN_HDMI_MEAS_INTR_STAT (0x34a3) ++#define P_AUDIN_HDMI_MEAS_INTR_STAT (volatile unsigned int *)((0x34a3 << 2) + 0xffd00000) ++#define AUDIN_HDMI_REF_CYCLES_STAT_0 (0x34a4) ++#define P_AUDIN_HDMI_REF_CYCLES_STAT_0 (volatile unsigned int *)((0x34a4 << 2) + 0xffd00000) ++#define AUDIN_HDMI_REF_CYCLES_STAT_1 (0x34a5) ++#define P_AUDIN_HDMI_REF_CYCLES_STAT_1 (volatile unsigned int *)((0x34a5 << 2) + 0xffd00000) ++#define AUDIN_HDMIRX_AFIFO_STAT (0x34a6) ++#define P_AUDIN_HDMIRX_AFIFO_STAT (volatile unsigned int *)((0x34a6 << 2) + 0xffd00000) ++#define AUDIN_MEM_PD (0x34aa) ++#define P_AUDIN_MEM_PD (volatile unsigned int *)((0x34aa << 2) + 0xffd00000) ++#define AUDIN_FIFO0_PIO_STS (0x34b0) ++#define P_AUDIN_FIFO0_PIO_STS (volatile unsigned int *)((0x34b0 << 2) + 0xffd00000) ++#define AUDIN_FIFO0_PIO_RDL (0x34b1) ++#define P_AUDIN_FIFO0_PIO_RDL (volatile unsigned int *)((0x34b1 << 2) + 0xffd00000) ++#define AUDIN_FIFO0_PIO_RDH (0x34b2) ++#define P_AUDIN_FIFO0_PIO_RDH (volatile unsigned int *)((0x34b2 << 2) + 0xffd00000) ++#define AUDIN_FIFO1_PIO_STS (0x34b3) ++#define P_AUDIN_FIFO1_PIO_STS (volatile unsigned int *)((0x34b3 << 2) + 0xffd00000) ++#define AUDIN_FIFO1_PIO_RDL (0x34b4) ++#define P_AUDIN_FIFO1_PIO_RDL (volatile unsigned int *)((0x34b4 << 2) + 0xffd00000) ++#define AUDIN_FIFO1_PIO_RDH (0x34b5) ++#define P_AUDIN_FIFO1_PIO_RDH (volatile unsigned int *)((0x34b5 << 2) + 0xffd00000) ++#define AUDIN_FIFO2_PIO_STS (0x34b6) ++#define P_AUDIN_FIFO2_PIO_STS (volatile unsigned int *)((0x34b6 << 2) + 0xffd00000) ++#define AUDIN_FIFO2_PIO_RDL (0x34b7) ++#define P_AUDIN_FIFO2_PIO_RDL (volatile unsigned int *)((0x34b7 << 2) + 0xffd00000) ++#define AUDIN_FIFO2_PIO_RDH (0x34b8) ++#define P_AUDIN_FIFO2_PIO_RDH (volatile unsigned int *)((0x34b8 << 2) + 0xffd00000) ++#define AUDOUT_FIFO_PIO_STS (0x34b9) ++#define P_AUDOUT_FIFO_PIO_STS (volatile unsigned int *)((0x34b9 << 2) + 0xffd00000) ++#define AUDOUT_FIFO_PIO_WRL (0x34ba) ++#define P_AUDOUT_FIFO_PIO_WRL (volatile unsigned int *)((0x34ba << 2) + 0xffd00000) ++#define AUDOUT_FIFO_PIO_WRH (0x34bb) ++#define P_AUDOUT_FIFO_PIO_WRH (volatile unsigned int *)((0x34bb << 2) + 0xffd00000) ++//`define AUDOUT1_FIFO_PIO_STS 8'hbc ++//`define AUDOUT1_FIFO_PIO_WRL 8'hbd ++//`define AUDOUT1_FIFO_PIO_WRH 8'hbe ++#define AUD_RESAMPLE_CTRL0 (0x34bf) ++#define P_AUD_RESAMPLE_CTRL0 (volatile unsigned int *)((0x34bf << 2) + 0xffd00000) ++#define AUD_RESAMPLE_CTRL1 (0x34c0) ++#define P_AUD_RESAMPLE_CTRL1 (volatile unsigned int *)((0x34c0 << 2) + 0xffd00000) ++#define AUD_RESAMPLE_STATUS (0x34c1) ++#define P_AUD_RESAMPLE_STATUS (volatile unsigned int *)((0x34c1 << 2) + 0xffd00000) ++#define AUD_RESAMPLE_CTRL2 (0x34c2) ++#define P_AUD_RESAMPLE_CTRL2 (volatile unsigned int *)((0x34c2 << 2) + 0xffd00000) ++#define AUD_RESAMPLE_COEF0 (0x34c3) ++#define P_AUD_RESAMPLE_COEF0 (volatile unsigned int *)((0x34c3 << 2) + 0xffd00000) ++#define AUD_RESAMPLE_COEF1 (0x34c4) ++#define P_AUD_RESAMPLE_COEF1 (volatile unsigned int *)((0x34c4 << 2) + 0xffd00000) ++#define AUD_RESAMPLE_COEF2 (0x34c5) ++#define P_AUD_RESAMPLE_COEF2 (volatile unsigned int *)((0x34c5 << 2) + 0xffd00000) ++#define AUD_RESAMPLE_COEF3 (0x34c6) ++#define P_AUD_RESAMPLE_COEF3 (volatile unsigned int *)((0x34c6 << 2) + 0xffd00000) ++#define AUD_RESAMPLE_COEF4 (0x34c7) ++#define P_AUD_RESAMPLE_COEF4 (volatile unsigned int *)((0x34c7 << 2) + 0xffd00000) ++#define AUDIN_ADDR_END (0x34c8) ++#define P_AUDIN_ADDR_END (volatile unsigned int *)((0x34c8 << 2) + 0xffd00000) ++#define AUDIN_ATV_DEMOD_CTRL (0x34d0) ++#define P_AUDIN_ATV_DEMOD_CTRL (volatile unsigned int *)((0x34d0 << 2) + 0xffd00000) ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: ./register_map.h ++// ++// ++// Reading file: ./vcbus_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++//=========================================================================== ++//`define RDMA_VCBUS_BASE 8'h11 ++//=========================================================================== ++// ++// Reading file: rdma_regs.h ++// ++//=========================================================================== ++// RDMA registers 0x00 - 0xff ++//=========================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: RDMA_VCBUS_BASE = 0x11 ++// ----------------------------------------------- ++// Bit 31: 0 RW AHB start address for manual start DMA ++#define RDMA_AHB_START_ADDR_MAN (0x1100) ++#define P_RDMA_AHB_START_ADDR_MAN (volatile unsigned int *)((0x1100 << 2) + 0xff900000) ++// Bit 31: 0 RW AHB end address for manual start DMA ++#define RDMA_AHB_END_ADDR_MAN (0x1101) ++#define P_RDMA_AHB_END_ADDR_MAN (volatile unsigned int *)((0x1101 << 2) + 0xff900000) ++// Bit 31: 0 RW AHB start address for auto start source 1 ++#define RDMA_AHB_START_ADDR_1 (0x1102) ++#define P_RDMA_AHB_START_ADDR_1 (volatile unsigned int *)((0x1102 << 2) + 0xff900000) ++// Bit 31: 0 RW AHB end address for auto start source 1 ++#define RDMA_AHB_END_ADDR_1 (0x1103) ++#define P_RDMA_AHB_END_ADDR_1 (volatile unsigned int *)((0x1103 << 2) + 0xff900000) ++// Bit 31: 0 RW AHB start address for auto start source 2 ++#define RDMA_AHB_START_ADDR_2 (0x1104) ++#define P_RDMA_AHB_START_ADDR_2 (volatile unsigned int *)((0x1104 << 2) + 0xff900000) ++// Bit 31: 0 RW AHB end address for auto start source 2 ++#define RDMA_AHB_END_ADDR_2 (0x1105) ++#define P_RDMA_AHB_END_ADDR_2 (volatile unsigned int *)((0x1105 << 2) + 0xff900000) ++// Bit 31: 0 RW AHB start address for auto start source 3 ++#define RDMA_AHB_START_ADDR_3 (0x1106) ++#define P_RDMA_AHB_START_ADDR_3 (volatile unsigned int *)((0x1106 << 2) + 0xff900000) ++// Bit 31: 0 RW AHB end address for auto start source 3 ++#define RDMA_AHB_END_ADDR_3 (0x1107) ++#define P_RDMA_AHB_END_ADDR_3 (volatile unsigned int *)((0x1107 << 2) + 0xff900000) ++// Bit 31: 0 RW AHB start address for auto start source 4 ++#define RDMA_AHB_START_ADDR_4 (0x1108) ++#define P_RDMA_AHB_START_ADDR_4 (volatile unsigned int *)((0x1108 << 2) + 0xff900000) ++// Bit 31: 0 RW AHB end address for auto start source 4 ++#define RDMA_AHB_END_ADDR_4 (0x1109) ++#define P_RDMA_AHB_END_ADDR_4 (volatile unsigned int *)((0x1109 << 2) + 0xff900000) ++// Bit 31: 0 RW AHB start address for auto start source 5 ++#define RDMA_AHB_START_ADDR_5 (0x110a) ++#define P_RDMA_AHB_START_ADDR_5 (volatile unsigned int *)((0x110a << 2) + 0xff900000) ++// Bit 31: 0 RW AHB end address for auto start source 5 ++#define RDMA_AHB_END_ADDR_5 (0x110b) ++#define P_RDMA_AHB_END_ADDR_5 (volatile unsigned int *)((0x110b << 2) + 0xff900000) ++// Bit 31: 0 RW AHB start address for auto start source 6 ++#define RDMA_AHB_START_ADDR_6 (0x110c) ++#define P_RDMA_AHB_START_ADDR_6 (volatile unsigned int *)((0x110c << 2) + 0xff900000) ++// Bit 31: 0 RW AHB end address for auto start source 6 ++#define RDMA_AHB_END_ADDR_6 (0x110d) ++#define P_RDMA_AHB_END_ADDR_6 (volatile unsigned int *)((0x110d << 2) + 0xff900000) ++// Bit 31: 0 RW AHB start address for auto start source 7 ++#define RDMA_AHB_START_ADDR_7 (0x110e) ++#define P_RDMA_AHB_START_ADDR_7 (volatile unsigned int *)((0x110e << 2) + 0xff900000) ++// Bit 31: 0 RW AHB end address for auto start source 7 ++#define RDMA_AHB_END_ADDR_7 (0x110f) ++#define P_RDMA_AHB_END_ADDR_7 (volatile unsigned int *)((0x110f << 2) + 0xff900000) ++// Auto start DMA control: ++// Bit 31:24 RW ctrl_enable_int_3. Interrupt inputs enable mask for source 3. ++// Bit 23:16 RW ctrl_enable_int_2. Interrupt inputs enable mask for source 2. ++// Bit 15: 8 RW ctrl_enable_int_1. Interrupt inputs enable mask for source 1. ++// Bit 7 RW ctrl_cbus_write_3. Register read/write mode for auto-start 3. 1=Register write; 0=Register read. ++// Bit 6 RW ctrl_cbus_write_3. Register read/write mode for auto-start 2. 1=Register write; 0=Register read. ++// Bit 5 RW ctrl_cbus_write_3. Register read/write mode for auto-start 1. 1=Register write; 0=Register read. ++// Bit 4 R Rsrv. ++// Bit 3 RW ctrl_cbus_addr_incr_3. 1=Incremental register access for auto-start 3; 0=Non-incremental (individual) register access. ++// Bit 2 RW ctrl_cbus_addr_incr_2. 1=Incremental register access for auto-start 2; 0=Non-incremental (individual) register access. ++// Bit 1 RW ctrl_cbus_addr_incr_1. 1=Incremental register access for auto-start 1; 0=Non-incremental (individual) register access. ++// Bit 0 R Rsrv. ++#define RDMA_ACCESS_AUTO (0x1110) ++#define P_RDMA_ACCESS_AUTO (volatile unsigned int *)((0x1110 << 2) + 0xff900000) ++#define RDMA_ACCESS_AUTO2 (0x1111) ++#define P_RDMA_ACCESS_AUTO2 (volatile unsigned int *)((0x1111 << 2) + 0xff900000) ++#define RDMA_ACCESS_AUTO3 (0x1112) ++#define P_RDMA_ACCESS_AUTO3 (volatile unsigned int *)((0x1112 << 2) + 0xff900000) ++// Manual start DMA control: ++// Bit 31: 3 R Rsrv. ++// Bit 2 RW ctrl_cbus_write_man. Register read/write mode for manual-start. 1=Register write; 0=Register read. ++// Bit 1 RW ctrl_cbus_addr_incr_man. 1=Incremental register access for manual-start; 0=Non-incremental (individual) register access. ++// Bit 0 W ctrl_start_man. Write 1 to this bit to manual-start DMA. This bit always read back 0. ++#define RDMA_ACCESS_MAN (0x1113) ++#define P_RDMA_ACCESS_MAN (volatile unsigned int *)((0x1113 << 2) + 0xff900000) ++// RDMA general control: ++// Bit 31:25 R Rsrv. ++// Bit 24 W ctrl_clr_rdma_done_int. Write 1 to reset rdma_int level to 0. No need to clear this bit. ++// Bit 23:19 R Rsrv. ++// Bit 18:13 R Rsrv. ++// Bit 12: 7 R Rsrv. ++// Bit 6 RW ctrl_ddr_urgent. ++// Bit 5: 4 RW ctrl_ahb_wr_burst_size. 0=ABH write request burst size 16; ++// 1=ABH write request burst size 24; ++// 2=ABH write request burst size 32; ++// 3=ABH write request burst size 48. ++// Bit 3: 2 RW ctrl_ahb_rd_burst_size. 0=ABH read request burst size 16; ++// 1=ABH read request burst size 24; ++// 2=ABH read request burst size 32; ++// 3=ABH read request burst size 48. ++// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logics except register. ++// Bit 0 RW ctrl_free_clk_enable. 0=Default, Enable clock gating. 1=No clock gating, enable free clock. ++#define RDMA_CTRL (0x1114) ++#define P_RDMA_CTRL (volatile unsigned int *)((0x1114 << 2) + 0xff900000) ++// Read only. ++// Bit 31:29 R Rsrv. ++// Bit 28 R rdma_done_int. ++// Bit 27:25 R Rsrv. ++// Bit 24:18 R ahb_wrfifo_cnt. FIFO for buffering CBus read data to be sent to AHB ++// Bit 17:11 R ahb_rdfifo_cnt. FIFO for buffering data read from AHB. ++// Bit 10: 8 R ddr_req_st. =0 -- Idle; !=0 -- AHB interfacing ongoing. ++// Bit 7: 4 R curr_req. Latest requests that is being/been serviced. E.g. 0000=Idle; 0010=Latest serviced request is Req 1. ++// Bit 3: 0 R req_latch. Requests that are yet to be serviced. E.g. 0000=No request; 0001=Req 0 waiting; 1100=Req 2 and 3 waiting. ++#define RDMA_STATUS (0x1115) ++#define P_RDMA_STATUS (volatile unsigned int *)((0x1115 << 2) + 0xff900000) ++#define RDMA_STATUS2 (0x1116) ++#define P_RDMA_STATUS2 (volatile unsigned int *)((0x1116 << 2) + 0xff900000) ++#define RDMA_STATUS3 (0x1117) ++#define P_RDMA_STATUS3 (volatile unsigned int *)((0x1117 << 2) + 0xff900000) ++#define RDMA_ACCESS_AUTO4 (0x1118) ++#define P_RDMA_ACCESS_AUTO4 (volatile unsigned int *)((0x1118 << 2) + 0xff900000) ++#define RDMA_SRAM_CNTL (0x1120) ++#define P_RDMA_SRAM_CNTL (volatile unsigned int *)((0x1120 << 2) + 0xff900000) ++#define RDMA_SRAM_REGADDR (0x1121) ++#define P_RDMA_SRAM_REGADDR (volatile unsigned int *)((0x1121 << 2) + 0xff900000) ++#define RDMA_SRAM_REGDATA (0x1122) ++#define P_RDMA_SRAM_REGDATA (volatile unsigned int *)((0x1122 << 2) + 0xff900000) ++// ++// Closing file: rdma_regs.h ++// ++//=========================================================================== ++// VDIN ++//=========================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: VDIN_VCBUS_BASE = 0x12 ++// ----------------------------------------------- ++//VDIN0 8'h00 - 8'h7f ++//VDIN1 8'h80 - 8'hef ++#define VDIN0_OFFSET 0x00 ++#define VDIN1_OFFSET 0x80 ++ ++#define VDIN_SCALE_COEF_IDX (0x1200) ++#define P_VDIN_SCALE_COEF_IDX (volatile unsigned int *)((0x1200 << 2) + 0xff900000) ++#define VDIN_SCALE_COEF (0x1201) ++#define P_VDIN_SCALE_COEF (volatile unsigned int *)((0x1201 << 2) + 0xff900000) ++//bit 31, mpeg_to_vdin_sel, 0: mpeg source to NR directly, 1: mpeg source pass through here ++//bit 30, mpeg_field info which can be written by software ++//Bit 29, force go_field, pulse signal ++//Bit 28, force go_line, pulse signal ++//Bit 27, enable mpeg_go_field input signal ++//Bit 26:20, hold lines ++//Bit 19, delay go_field function enable ++//Bit 18:12, delay go_field line number ++//Bit 11:10, component2 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in ++//Bit 9:8, component1 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in ++//Bit 7:6, component0 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in ++//Bit 5, input window selection function enable ++//Bit 4, enable VDIN common data input, otherwise there will be no video data input ++//Bit 3:0 vdin selection, 1: mpeg_in from dram, 2: bt656 input, 3: component input, 4: tvdecoder input, 5: hdmi rx input, 6: digtial video input, 7: loopback from Viu1, 8: MIPI. ++#define VDIN_COM_CTRL0 (0x1202) ++#define P_VDIN_COM_CTRL0 (volatile unsigned int *)((0x1202 << 2) + 0xff900000) ++//Bit 28:16 active_max_pix_cnt, readonly ++//Bit 12:0 active_max_pix_cnt_shadow, readonly ++#define VDIN_ACTIVE_MAX_PIX_CNT_STATUS (0x1203) ++#define P_VDIN_ACTIVE_MAX_PIX_CNT_STATUS (volatile unsigned int *)((0x1203 << 2) + 0xff900000) ++//Bit 28:16 go_line_cnt, readonly ++//Bit 12:0 active_line_cnt, readonly ++#define VDIN_LCNT_STATUS (0x1204) ++#define P_VDIN_LCNT_STATUS (volatile unsigned int *)((0x1204 << 2) + 0xff900000) ++//Readonly ++//Bit [14:3] lfifo_buf_cnt ++//Bit 2, vdin_direct_done status ++//Bit 1, vdin_nr_done status ++//Bit 0, field ++#define VDIN_COM_STATUS0 (0x1205) ++#define P_VDIN_COM_STATUS0 (volatile unsigned int *)((0x1205 << 2) + 0xff900000) ++//Readonly ++//Bit 31, vdi4 fifo overflow ++//Bit 29:24, vdi3_asfifo_cnt ++//Bit 23, vdi3 fifo overflow ++//Bit 21:16, vdi3_asfifo_cnt ++//Bit 15, vdi2 fifo overflow ++//Bit 13:8, vdi2_asfifo_cnt ++//Bit 7, vdi1 fifo overflow ++//Bit 5:0, vdi1_asfifo_cnt ++#define VDIN_COM_STATUS1 (0x1206) ++#define P_VDIN_COM_STATUS1 (volatile unsigned int *)((0x1206 << 2) + 0xff900000) ++//Bit 28:16 go_line_cnt_shadow, readonly ++//Bit 12:0 active_line_cnt_shadow, readonly ++#define VDIN_LCNT_SHADOW_STATUS (0x1207) ++#define P_VDIN_LCNT_SHADOW_STATUS (volatile unsigned int *)((0x1207 << 2) + 0xff900000) ++//each 8bit asfifo_ctrl is following: ++//Bit 7, DE enable ++//Bit 6, go field enable ++//Bit 5, go line enable ++//Bit 4, if true, negative active input vsync ++//Bit 3, if true, negative active input hsync ++//Bit 2, vsync soft reset fifo enable ++//Bit 1, overflow status clear ++//Bit 0 asfifo soft reset, level signal ++//Bit 7:0 vdi1 asfifo_ctrl ++//Bit 23:16 vdi2 asfifo_ctrl ++#define VDIN_ASFIFO_CTRL0 (0x1208) ++#define P_VDIN_ASFIFO_CTRL0 (volatile unsigned int *)((0x1208 << 2) + 0xff900000) ++//Bit 7:0 vdi3 asfifo_ctrl ++//Bit 23:16 vdi4 asfifo_ctrl ++#define VDIN_ASFIFO_CTRL1 (0x1209) ++#define P_VDIN_ASFIFO_CTRL1 (volatile unsigned int *)((0x1209 << 2) + 0xff900000) ++//Bit 28:16 input width minus 1, after the window function ++//Bit 12:0 output width minus 1 ++#define VDIN_WIDTHM1I_WIDTHM1O (0x120a) ++#define P_VDIN_WIDTHM1I_WIDTHM1O (volatile unsigned int *)((0x120a << 2) + 0xff900000) ++//Bit 20:17 prehsc_mode, bit 3:2, prehsc odd line interp mode, bit 1:0, prehsc even line interp mode, ++// each 2bit, 00: pix0+pix1/2, average, 01: pix1, 10: pix0 ++//Bit 16:15 sp422_mode, special mode for the component1 and component2, 00: normal case, 01: 32 64 32, 10: 0 64 64 0, 11: 16 96 16 ++//Bit 14:8, hsc_ini_pixi_ptr, signed data, only useful when short_lineo_en is true ++//Bit 7, prehsc_en ++//Bit 6, hsc_en, ++//Bit 5, hsc_short_lineo_en, short line output enable ++//Bit 4, hsc_nearest_en ++//Bit 3, hsc_phase0_always_en ++//Bit 2:0, hsc_bank_length ++#define VDIN_SC_MISC_CTRL (0x120b) ++#define P_VDIN_SC_MISC_CTRL (volatile unsigned int *)((0x120b << 2) + 0xff900000) ++//Bit 28:24, integer portion ++//Bit 23:0, fraction portion ++#define VDIN_HSC_PHASE_STEP (0x120c) ++#define P_VDIN_HSC_PHASE_STEP (volatile unsigned int *)((0x120c << 2) + 0xff900000) ++//Bit 30:29 hscale rpt_p0_num ++//Bit 28:24 hscale ini_rcv_num ++//Bit 23:0 hscale ini_phase ++#define VDIN_HSC_INI_CTRL (0x120d) ++#define P_VDIN_HSC_INI_CTRL (volatile unsigned int *)((0x120d << 2) + 0xff900000) ++//Read only ++//Bit 23, vdi7 fifo overflow ++//Bit 21:16, vdi7_asfifo_cnt ++//Bit 15, vdi6 fifo overflow ++//Bit 13:8, vdi6_asfifo_cnt ++//Bit 7, vdi5 fifo overflow ++//Bit 5:0, vdi5_asfifo_cnt ++#define VDIN_COM_STATUS2 (0x120e) ++#define P_VDIN_COM_STATUS2 (volatile unsigned int *)((0x120e << 2) + 0xff900000) ++//Bit 25:16 asfifo decimate control ++//Bit 25, if true, decimation counter sync with first valid DE in the field, ++//otherwise the decimation counter is not sync with external signal ++//Bit 24, decimation de enable ++//Bit 23:20, decimation phase, which counter value use to decimate, ++//Bit 19:16, decimation number, 0: not decimation, 1: decimation 2, 2: decimation 3 .... ++//Bit 7:0 vdi5 asfifo_ctrl ++#define VDIN_ASFIFO_CTRL2 (0x120f) ++#define P_VDIN_ASFIFO_CTRL2 (volatile unsigned int *)((0x120f << 2) + 0xff900000) ++//Bit 7, highlight_en ++//Bit 6 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix ++//Bit 5:4 probe_sel, 00: select matrix 0, 01: select matrix 1, otherwise select nothing ++//Bit 3:2, matrix coef idx selection, 00: select mat0, 01: select mat1, otherwise slect nothing ++//Bit 1 mat1 conversion matrix enable ++//Bit 0 mat0 conversion matrix enable ++#define VDIN_MATRIX_CTRL (0x1210) ++#define P_VDIN_MATRIX_CTRL (volatile unsigned int *)((0x1210 << 2) + 0xff900000) ++//Bit 28:16 coef00 ++//Bit 12:0 coef01 ++#define VDIN_MATRIX_COEF00_01 (0x1211) ++#define P_VDIN_MATRIX_COEF00_01 (volatile unsigned int *)((0x1211 << 2) + 0xff900000) ++//Bit 28:16 coef02 ++//Bit 12:0 coef10 ++#define VDIN_MATRIX_COEF02_10 (0x1212) ++#define P_VDIN_MATRIX_COEF02_10 (volatile unsigned int *)((0x1212 << 2) + 0xff900000) ++//Bit 28:16 coef11 ++//Bit 12:0 coef12 ++#define VDIN_MATRIX_COEF11_12 (0x1213) ++#define P_VDIN_MATRIX_COEF11_12 (volatile unsigned int *)((0x1213 << 2) + 0xff900000) ++//Bit 28:16 coef20 ++//Bit 12:0 coef21 ++#define VDIN_MATRIX_COEF20_21 (0x1214) ++#define P_VDIN_MATRIX_COEF20_21 (volatile unsigned int *)((0x1214 << 2) + 0xff900000) ++//BIt 18:16 conv_rs ++//Bit 12:0 coef22 ++#define VDIN_MATRIX_COEF22 (0x1215) ++#define P_VDIN_MATRIX_COEF22 (volatile unsigned int *)((0x1215 << 2) + 0xff900000) ++//Bit 26:16 offset0 ++//Bit 10:0 offset1 ++#define VDIN_MATRIX_OFFSET0_1 (0x1216) ++#define P_VDIN_MATRIX_OFFSET0_1 (volatile unsigned int *)((0x1216 << 2) + 0xff900000) ++//Bit 10:0 offset2 ++#define VDIN_MATRIX_OFFSET2 (0x1217) ++#define P_VDIN_MATRIX_OFFSET2 (volatile unsigned int *)((0x1217 << 2) + 0xff900000) ++//Bit 26:16 pre_offset0 ++//Bit 10:0 pre_offset1 ++#define VDIN_MATRIX_PRE_OFFSET0_1 (0x1218) ++#define P_VDIN_MATRIX_PRE_OFFSET0_1 (volatile unsigned int *)((0x1218 << 2) + 0xff900000) ++//Bit 10:0 pre_offset2 ++#define VDIN_MATRIX_PRE_OFFSET2 (0x1219) ++#define P_VDIN_MATRIX_PRE_OFFSET2 (volatile unsigned int *)((0x1219 << 2) + 0xff900000) ++//12:0 lfifo_buf_size ++#define VDIN_LFIFO_CTRL (0x121a) ++#define P_VDIN_LFIFO_CTRL (volatile unsigned int *)((0x121a << 2) + 0xff900000) ++#define VDIN_COM_GCLK_CTRL (0x121b) ++#define P_VDIN_COM_GCLK_CTRL (volatile unsigned int *)((0x121b << 2) + 0xff900000) ++//12:0 VDIN input interface width minus 1, before the window function, after the de decimation ++#define VDIN_INTF_WIDTHM1 (0x121c) ++#define P_VDIN_INTF_WIDTHM1 (volatile unsigned int *)((0x121c << 2) + 0xff900000) ++//Bit 15 //default== 0, urgent_ctrl_en ++//Bit 14 //default== 0, urgent_wr, if true for write buffer ++//Bit 13 //default== 0, out_inv_en ++//Bit 12 //default == 0, urgent_ini_value ++//Bit 11:6 //default == 0, up_th up threshold ++//Bit 5:0 //default == 0, dn_th dn threshold ++#define VDIN_LFIFO_URG_CTRL (0x121e) ++#define P_VDIN_LFIFO_URG_CTRL (volatile unsigned int *)((0x121e << 2) + 0xff900000) ++//Bit 8, 1: discard data before line fifo, 0: normal mode ++//Bit 7:0 Write chroma canvas address ++#define VDIN_WR_CTRL2 (0x121f) ++#define P_VDIN_WR_CTRL2 (volatile unsigned int *)((0x121f << 2) + 0xff900000) ++//Bit 31:30 hconv_mode, Applicable only to bit[13:12]=0 or 2. 0: Output every even pixels' CbCr; ++// 1: Output every odd pixels' CbCr; ++// 2: Output an average value per even&odd pair of pixels; ++// 3: Output all CbCr. (This does NOT apply to bit[13:12]=0 -- 4:2:2 mode.) ++//Bit 29 no_clk_gate: disable vid_wr_mif clock gating function. ++//Bit 28 clear write response counter in the vdin write memory interface ++//Bit 27 eol_sel, 1: use eol as the line end indication, 0: use width as line end indication in the vdin write memory interface ++//Bit 26 vcp_nr_en. Only used in VDIN0. NOT used in VDIN1. ++//Bit 25 vcp_wr_en. Only used in VDIN0. NOT used in VDIN1. ++//Bit 24 vcp_in_en. Only used in VDIN0. NOT used in VDIN1. ++//Bit 23 vdin frame reset enble, if true, it will provide frame reset during go_field(vsync) to the modules after that ++//Bit 22 vdin line fifo soft reset enable, meaning, if true line fifo will reset during go_field (vsync) ++//Bit 21 vdin direct write done status clear bit ++//Bit 20 vdin NR write done status clear bit ++//Bit 18 swap_cbcr. Applicable only to bit[13:12]=2. 0: Output CbCr (NV12); 1: Output CrCb (NV21). ++//Bit 17:16 vconv_mode, Applicable only to bit[13:12]=2. 0: Output every even lines' CbCr; ++// 1: Output every odd lines' CbCr; ++// 2: Reserved; ++// 3: Output all CbCr. ++//Bit 13:12 vdin write format, 0: 4:2:2 to luma canvas, 1: 4:4:4 to luma canvas, ++// 2: Y to luma canvas, CbCr to chroma canvas. For NV12/21, also define Bit 31:30, 17:16, and bit 18. ++//Bit 11 vdin write canvas double buffer enable, means the canvas address will be latched by vsync before using ++//Bit 10 1: disable ctrl_reg write pulse which will reset internal counter. when bit 11 is 1, this bit should be 1. ++//Bit 9 vdin write request urgent ++//Bit 8 vdin write request enable ++//Bit 7:0 Write luma canvas address ++#define VDIN_WR_CTRL (0x1220) ++#define P_VDIN_WR_CTRL (volatile unsigned int *)((0x1220 << 2) + 0xff900000) ++//Bit 29, if true, horizontal reverse ++//Bit 28:16 start ++//Bit 12:0 end ++#define VDIN_WR_H_START_END (0x1221) ++#define P_VDIN_WR_H_START_END (volatile unsigned int *)((0x1221 << 2) + 0xff900000) ++//Bit 29, if true, vertical reverse ++//Bit 28:16 start ++//Bit 12:0 end ++#define VDIN_WR_V_START_END (0x1222) ++#define P_VDIN_WR_V_START_END (volatile unsigned int *)((0x1222 << 2) + 0xff900000) ++//Bit 24:20, integer portion ++//Bit 19:0, fraction portion ++#define VDIN_VSC_PHASE_STEP (0x1223) ++#define P_VDIN_VSC_PHASE_STEP (volatile unsigned int *)((0x1223 << 2) + 0xff900000) ++//Bit 23, vsc_en, vertical scaler enable ++//Bit 21 vsc_phase0_always_en, when scale up, you have to set it to 1 ++//Bit 20:16 ini skip_line_num ++//Bit 15:0 vscaler ini_phase ++#define VDIN_VSC_INI_CTRL (0x1224) ++#define P_VDIN_VSC_INI_CTRL (volatile unsigned int *)((0x1224 << 2) + 0xff900000) ++//Bit 28:16, vshrink input height minus 1 ++//Bit 12:0, scaler input height minus 1 ++#define VDIN_SCIN_HEIGHTM1 (0x1225) ++#define P_VDIN_SCIN_HEIGHTM1 (volatile unsigned int *)((0x1225 << 2) + 0xff900000) ++//Bit 23:16, dummy component 0 ++//Bit 15:8, dummy component 1 ++//Bit 7:0, dummy component 2 ++#define VDIN_DUMMY_DATA (0x1226) ++#define P_VDIN_DUMMY_DATA (volatile unsigned int *)((0x1226 << 2) + 0xff900000) ++//Read only ++//Bit 29:20 component 0 ++//Bit 19:10 component 1 ++//Bit 9:0 component 2 ++#define VDIN_MATRIX_PROBE_COLOR (0x1228) ++#define P_VDIN_MATRIX_PROBE_COLOR (volatile unsigned int *)((0x1228 << 2) + 0xff900000) ++//Bit 23:16 component 0 ++//Bit 15:8 component 1 ++//Bit 7:0 component 2 ++#define VDIN_MATRIX_HL_COLOR (0x1229) ++#define P_VDIN_MATRIX_HL_COLOR (volatile unsigned int *)((0x1229 << 2) + 0xff900000) ++//28:16 probe x, postion ++//12:0 probe y, position ++#define VDIN_MATRIX_PROBE_POS (0x122a) ++#define P_VDIN_MATRIX_PROBE_POS (volatile unsigned int *)((0x122a << 2) + 0xff900000) ++#define VDIN_CHROMA_ADDR_PORT (0x122b) ++#define P_VDIN_CHROMA_ADDR_PORT (volatile unsigned int *)((0x122b << 2) + 0xff900000) ++#define VDIN_CHROMA_DATA_PORT (0x122c) ++#define P_VDIN_CHROMA_DATA_PORT (volatile unsigned int *)((0x122c << 2) + 0xff900000) ++// ++#define VDIN_CM_BRI_CON_CTRL (0x122d) ++#define P_VDIN_CM_BRI_CON_CTRL (volatile unsigned int *)((0x122d << 2) + 0xff900000) ++//Bit 17 clk_cyc_cnt_clr, if true, clear this register ++//Bit 16 if true, use vpu clock to count one line, otherwise use actually hsync to count line_cnt ++//Bit 15:0 line width using vpu clk ++#define VDIN_GO_LINE_CTRL (0x122f) ++#define P_VDIN_GO_LINE_CTRL (volatile unsigned int *)((0x122f << 2) + 0xff900000) ++//Bit 31:24 hist_pix_white_th, larger than this th is counted as white pixel ++//Bit 23:16 hist_pix_black_th, less than this th is counted as black pixel ++//Bit 11 hist_34bin_only, 34 bin only mode, including white/black ++//Bit 10:9 ldim_stts_din_sel, 00: from matrix0 dout, 01: from vsc_dout, 10: from matrix1 dout, 11: form matrix1 din ++//Bit 8 ldim_stts_en ++//Bit 6:5 hist_dnlp_low the real pixels in each bins got by VDIN_DNLP_HISTXX should multiple with 2^(dnlp_low+3) ++//Bit 3:2 hist_din_sel the source used for hist statistics. 00: from matrix0 dout, 01: from vsc_dout, 10: from matrix1 dout, 11: form matrix1 din ++//Bit 1 hist_win_en 1'b0: hist used for full picture; 1'b1: hist used for pixels within hist window ++//Bit 0 hist_spl_en 1'b0: disable hist readback; 1'b1: enable hist readback ++#define VDIN_HIST_CTRL (0x1230) ++#define P_VDIN_HIST_CTRL (volatile unsigned int *)((0x1230 << 2) + 0xff900000) ++//Bit 28:16 hist_hstart horizontal start value to define hist window ++//Bit 12:0 hist_hend horizontal end value to define hist window ++#define VDIN_HIST_H_START_END (0x1231) ++#define P_VDIN_HIST_H_START_END (volatile unsigned int *)((0x1231 << 2) + 0xff900000) ++//Bit 28:16 hist_vstart vertical start value to define hist window ++//Bit 12:0 hist_vend vertical end value to define hist window ++#define VDIN_HIST_V_START_END (0x1232) ++#define P_VDIN_HIST_V_START_END (volatile unsigned int *)((0x1232 << 2) + 0xff900000) ++//Bit 15:8 hist_max maximum value ++//Bit 7:0 hist_min minimum value ++//read only ++#define VDIN_HIST_MAX_MIN (0x1233) ++#define P_VDIN_HIST_MAX_MIN (volatile unsigned int *)((0x1233 << 2) + 0xff900000) ++//Bit 31:0 hist_spl_rd ++//counts for the total luma value ++//read only ++#define VDIN_HIST_SPL_VAL (0x1234) ++#define P_VDIN_HIST_SPL_VAL (volatile unsigned int *)((0x1234 << 2) + 0xff900000) ++//Bit 21:0 hist_spl_pixel_count ++//counts for the total calculated pixels ++//read only ++#define VDIN_HIST_SPL_PIX_CNT (0x1235) ++#define P_VDIN_HIST_SPL_PIX_CNT (volatile unsigned int *)((0x1235 << 2) + 0xff900000) ++//Bit 31:0 hist_chroma_sum ++//counts for the total chroma value ++//read only ++#define VDIN_HIST_CHROMA_SUM (0x1236) ++#define P_VDIN_HIST_CHROMA_SUM (volatile unsigned int *)((0x1236 << 2) + 0xff900000) ++//Bit 31:16 higher hist bin ++//Bit 15:0 lower hist bin ++//0-255 are splited to 64 bins evenly, and VDIN_DNLP_HISTXX ++//are the statistic number of pixels that within each bin. ++//VDIN_DNLP_HIST00[15:0] counts for the first bin ++//VDIN_DNLP_HIST00[31:16] counts for the second bin ++//VDIN_DNLP_HIST01[15:0] counts for the third bin ++//VDIN_DNLP_HIST01[31:16] counts for the fourth bin ++//etc... ++//read only ++#define VDIN_DNLP_HIST00 (0x1237) ++#define P_VDIN_DNLP_HIST00 (volatile unsigned int *)((0x1237 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST01 (0x1238) ++#define P_VDIN_DNLP_HIST01 (volatile unsigned int *)((0x1238 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST02 (0x1239) ++#define P_VDIN_DNLP_HIST02 (volatile unsigned int *)((0x1239 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST03 (0x123a) ++#define P_VDIN_DNLP_HIST03 (volatile unsigned int *)((0x123a << 2) + 0xff900000) ++#define VDIN_DNLP_HIST04 (0x123b) ++#define P_VDIN_DNLP_HIST04 (volatile unsigned int *)((0x123b << 2) + 0xff900000) ++#define VDIN_DNLP_HIST05 (0x123c) ++#define P_VDIN_DNLP_HIST05 (volatile unsigned int *)((0x123c << 2) + 0xff900000) ++#define VDIN_DNLP_HIST06 (0x123d) ++#define P_VDIN_DNLP_HIST06 (volatile unsigned int *)((0x123d << 2) + 0xff900000) ++#define VDIN_DNLP_HIST07 (0x123e) ++#define P_VDIN_DNLP_HIST07 (volatile unsigned int *)((0x123e << 2) + 0xff900000) ++#define VDIN_DNLP_HIST08 (0x123f) ++#define P_VDIN_DNLP_HIST08 (volatile unsigned int *)((0x123f << 2) + 0xff900000) ++#define VDIN_DNLP_HIST09 (0x1240) ++#define P_VDIN_DNLP_HIST09 (volatile unsigned int *)((0x1240 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST10 (0x1241) ++#define P_VDIN_DNLP_HIST10 (volatile unsigned int *)((0x1241 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST11 (0x1242) ++#define P_VDIN_DNLP_HIST11 (volatile unsigned int *)((0x1242 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST12 (0x1243) ++#define P_VDIN_DNLP_HIST12 (volatile unsigned int *)((0x1243 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST13 (0x1244) ++#define P_VDIN_DNLP_HIST13 (volatile unsigned int *)((0x1244 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST14 (0x1245) ++#define P_VDIN_DNLP_HIST14 (volatile unsigned int *)((0x1245 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST15 (0x1246) ++#define P_VDIN_DNLP_HIST15 (volatile unsigned int *)((0x1246 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST16 (0x1247) ++#define P_VDIN_DNLP_HIST16 (volatile unsigned int *)((0x1247 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST17 (0x1248) ++#define P_VDIN_DNLP_HIST17 (volatile unsigned int *)((0x1248 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST18 (0x1249) ++#define P_VDIN_DNLP_HIST18 (volatile unsigned int *)((0x1249 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST19 (0x124a) ++#define P_VDIN_DNLP_HIST19 (volatile unsigned int *)((0x124a << 2) + 0xff900000) ++#define VDIN_DNLP_HIST20 (0x124b) ++#define P_VDIN_DNLP_HIST20 (volatile unsigned int *)((0x124b << 2) + 0xff900000) ++#define VDIN_DNLP_HIST21 (0x124c) ++#define P_VDIN_DNLP_HIST21 (volatile unsigned int *)((0x124c << 2) + 0xff900000) ++#define VDIN_DNLP_HIST22 (0x124d) ++#define P_VDIN_DNLP_HIST22 (volatile unsigned int *)((0x124d << 2) + 0xff900000) ++#define VDIN_DNLP_HIST23 (0x124e) ++#define P_VDIN_DNLP_HIST23 (volatile unsigned int *)((0x124e << 2) + 0xff900000) ++#define VDIN_DNLP_HIST24 (0x124f) ++#define P_VDIN_DNLP_HIST24 (volatile unsigned int *)((0x124f << 2) + 0xff900000) ++#define VDIN_DNLP_HIST25 (0x1250) ++#define P_VDIN_DNLP_HIST25 (volatile unsigned int *)((0x1250 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST26 (0x1251) ++#define P_VDIN_DNLP_HIST26 (volatile unsigned int *)((0x1251 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST27 (0x1252) ++#define P_VDIN_DNLP_HIST27 (volatile unsigned int *)((0x1252 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST28 (0x1253) ++#define P_VDIN_DNLP_HIST28 (volatile unsigned int *)((0x1253 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST29 (0x1254) ++#define P_VDIN_DNLP_HIST29 (volatile unsigned int *)((0x1254 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST30 (0x1255) ++#define P_VDIN_DNLP_HIST30 (volatile unsigned int *)((0x1255 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST31 (0x1256) ++#define P_VDIN_DNLP_HIST31 (volatile unsigned int *)((0x1256 << 2) + 0xff900000) ++//Bit 31, local dimming statistic enable ++//Bit 28, eol enable ++//Bit 27:25, vertical line overlap number for max finding ++//Bit 24:22, horizontal pixel overlap number, 0: 17 pix, 1: 9 pix, 2: 5 pix, 3: 3 pix, 4: 0 pix ++//Bit 20, 1,2,1 low pass filter enable before max/hist statistic ++//Bit 19:16, region H/V position index, refer to VDIN_LDIM_STTS_HIST_SET_REGION ++//Bit 15, 1: region read index auto increase per read to VDIN_LDIM_STTS_HIST_READ_REGION ++//Bit 6:0, region read index ++#define VDIN_LDIM_STTS_HIST_REGION_IDX (0x1257) ++#define P_VDIN_LDIM_STTS_HIST_REGION_IDX (volatile unsigned int *)((0x1257 << 2) + 0xff900000) ++//Bit 28:0, if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h0: read/write hvstart0 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h1: read/write hend01 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h2: read/write vend01 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h3: read/write hend23 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h4: read/write vend23 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h5: read/write hend45 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h6: read/write vend45 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'd7: read/write hend67 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h8: read/write vend67 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h9: read/write hend89 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'ha: read/write vend89 ++//hvstart0, Bit 28:16 row0 vstart, Bit 12:0 col0 hstart ++//hend01, Bit 28:16 col1 hend, Bit 12:0 col0 hend ++//vend01, Bit 28:16 row1 vend, Bit 12:0 row0 vend ++//hend23, Bit 28:16 col3 hend, Bit 12:0 col2 hend ++//vend23, Bit 28:16 row3 vend, Bit 12:0 row2 vend ++//hend45, Bit 28:16 col5 hend, Bit 12:0 col4 hend ++//vend45, Bit 28:16 row5 vend, Bit 12:0 row4 vend ++//hend67, Bit 28:16 col7 hend, Bit 12:0 col6 hend ++//vend67, Bit 28:16 row7 vend, Bit 12:0 row6 vend ++//hend89, Bit 28:16 col9 hend, Bit 12:0 col8 hend ++//vend89, Bit 28:16 row9 vend, Bit 12:0 row8 vend ++#define VDIN_LDIM_STTS_HIST_SET_REGION (0x1258) ++#define P_VDIN_LDIM_STTS_HIST_SET_REGION (volatile unsigned int *)((0x1258 << 2) + 0xff900000) ++//REGION STATISTIC DATA READ OUT PORT, bit 29:20 max_comp2, bit 19:10 max_comp1, bit 9:0 max_comp0 ++#define VDIN_LDIM_STTS_HIST_READ_REGION (0x1259) ++#define P_VDIN_LDIM_STTS_HIST_READ_REGION (volatile unsigned int *)((0x1259 << 2) + 0xff900000) ++//Bit 18, reset bit, high active ++//Bit 17, if true, widen hs/vs pulse ++//Bit 16 vsync total counter always accumulating enable ++//Bit 14:12, select hs/vs of video input channel to measure, 0: no selection, 1: vdi1, 2: vid2, 3: vid3, 4:vid4, 5:vdi5, 6:vid6, 7:vdi7, 8: vdi8 ++//Bit 11:4, vsync_span, define how many vsync span need to measure ++//Bit 2:0 meas_hs_index, index to select which HS counter/range ++#define VDIN_MEAS_CTRL0 (0x125a) ++#define P_VDIN_MEAS_CTRL0 (volatile unsigned int *)((0x125a << 2) + 0xff900000) ++//Read only ++//19:16 meas_ind_total_count_n, every number of sync_span vsyncs, this count add 1 ++//15:0 high bit portion of vsync total counter ++#define VDIN_MEAS_VS_COUNT_HI (0x125b) ++#define P_VDIN_MEAS_VS_COUNT_HI (volatile unsigned int *)((0x125b << 2) + 0xff900000) ++//Read only ++//31:0, low bit portion of vsync total counter ++#define VDIN_MEAS_VS_COUNT_LO (0x125c) ++#define P_VDIN_MEAS_VS_COUNT_LO (volatile unsigned int *)((0x125c << 2) + 0xff900000) ++//according to the meas_hs_index in register VDIN_MEAS_CTRL0 ++//meas_hs_index == 0, first hs range ++//meas_hs_index == 1, second hs range ++//meas_hs_index == 2, third hs range ++//meas_hs_index == 3, fourth hs range ++//bit 28:16 count_start ++//bit 12:0 count_end ++#define VDIN_MEAS_HS_RANGE (0x125d) ++#define P_VDIN_MEAS_HS_RANGE (volatile unsigned int *)((0x125d << 2) + 0xff900000) ++//Read only ++//according to the meas_hs_index in register VDIN_MEAS_CTRL0, ++//meas_hs_index == 0, first range hs counter, ++//meas_hs_index == 1, second range hs coutner ++//meas_hs_index == 2, third range hs coutner ++//meas_hs_index == 3, fourth range hs coutner ++//23:0 ++#define VDIN_MEAS_HS_COUNT (0x125e) ++#define P_VDIN_MEAS_HS_COUNT (volatile unsigned int *)((0x125e << 2) + 0xff900000) ++//Bit 8 white_enable ++//Bit 7:0 blkbar_white_level ++#define VDIN_BLKBAR_CTRL1 (0x125f) ++#define P_VDIN_BLKBAR_CTRL1 (volatile unsigned int *)((0x125f << 2) + 0xff900000) ++// Bit 31:24 blkbar_black_level threshold to judge a black point ++// Bit 23:21 Reserved ++// Bit 20:8 blkbar_hwidth left and right region width ++// Bit 7:5 blkbar_comp_sel select yin or uin or vin to be the valid input ++// Bit 4 blkbar_sw_statistic_en enable software statistic of each block black points number ++// Bit 3 blkbar_det_en ++// Bit 2:1 blkbar_din_sel ++// bit blkbar_det_top_en ++#define VDIN_BLKBAR_CTRL0 (0x1260) ++#define P_VDIN_BLKBAR_CTRL0 (volatile unsigned int *)((0x1260 << 2) + 0xff900000) ++// Bit 31:29 Reserved ++// Bit 28:16 blkbar_hstart. Left region start ++// Bit 15:13 Reserved ++// Bit 12:0 blkbar_hend. Right region end ++#define VDIN_BLKBAR_H_START_END (0x1261) ++#define P_VDIN_BLKBAR_H_START_END (volatile unsigned int *)((0x1261 << 2) + 0xff900000) ++// Bit 31:29 Reserved ++// Bit 28:16 blkbar_vstart ++// Bit 15:13 Reserved ++// Bit 12:0 blkbar_vend ++#define VDIN_BLKBAR_V_START_END (0x1262) ++#define P_VDIN_BLKBAR_V_START_END (volatile unsigned int *)((0x1262 << 2) + 0xff900000) ++// Bit 31:20 Reserved ++// Bit 19:0 blkbar_cnt_threshold. threshold to judge whether a block is totally black ++#define VDIN_BLKBAR_CNT_THRESHOLD (0x1263) ++#define P_VDIN_BLKBAR_CNT_THRESHOLD (volatile unsigned int *)((0x1263 << 2) + 0xff900000) ++// Bit 31:29 Reserved ++// Bit 28:16 blkbar_row_th1. //threshold of the top blackbar ++// Bit 15:13 Reserved ++// bit 12:0 blkbar_row_th2 //threshold of the bottom blackbar ++#define VDIN_BLKBAR_ROW_TH1_TH2 (0x1264) ++#define P_VDIN_BLKBAR_ROW_TH1_TH2 (volatile unsigned int *)((0x1264 << 2) + 0xff900000) ++//Readonly ++// Bit 31:29 Reserved ++// Bit 28:16 blkbar_ind_left_start. horizontal start of the left region in the current searching ++// Bit 15:13 Reserved ++// Bit 12:0 blkbar_ind_left_end. horizontal end of the left region in the current searching ++#define VDIN_BLKBAR_IND_LEFT_START_END (0x1265) ++#define P_VDIN_BLKBAR_IND_LEFT_START_END (volatile unsigned int *)((0x1265 << 2) + 0xff900000) ++//Readonly ++// Bit 31:29 Reserved ++// Bit 28:16 blkbar_ind_right_start.horizontal start of the right region in the current searching ++// Bit 15:13 Reserved ++// Bit 12:0 blkbar_ind_right_end. horizontal end of the right region in the current searching ++#define VDIN_BLKBAR_IND_RIGHT_START_END (0x1266) ++#define P_VDIN_BLKBAR_IND_RIGHT_START_END (volatile unsigned int *)((0x1266 << 2) + 0xff900000) ++//Readonly ++// Bit 31:20 Reserved ++// Bit 19:0 blkbar_ind_left1_cnt. Black pixel counter. left part of the left region ++#define VDIN_BLKBAR_IND_LEFT1_CNT (0x1267) ++#define P_VDIN_BLKBAR_IND_LEFT1_CNT (volatile unsigned int *)((0x1267 << 2) + 0xff900000) ++//Readonly ++// Bit 31:20 Reserved ++// Bit 19:0 blkbar_ind_left2_cnt. Black pixel counter. right part of the left region ++#define VDIN_BLKBAR_IND_LEFT2_CNT (0x1268) ++#define P_VDIN_BLKBAR_IND_LEFT2_CNT (volatile unsigned int *)((0x1268 << 2) + 0xff900000) ++//Readonly ++// Bit 31:20 Reserved ++// Bit 19:0 blkbar_ind_right1_cnt. Black pixel counter. left part of the right region ++#define VDIN_BLKBAR_IND_RIGHT1_CNT (0x1269) ++#define P_VDIN_BLKBAR_IND_RIGHT1_CNT (volatile unsigned int *)((0x1269 << 2) + 0xff900000) ++//Readonly ++// Bit 31:20 Reserved ++// Bit 19:0 blkbar_ind_right2_cnt. Black pixel counter. right part of the right region ++#define VDIN_BLKBAR_IND_RIGHT2_CNT (0x126a) ++#define P_VDIN_BLKBAR_IND_RIGHT2_CNT (volatile unsigned int *)((0x126a << 2) + 0xff900000) ++//Readonly ++// Bit 31:30 Resersed ++// Bit 29 blkbar_ind_black_det_done. LEFT/RIGHT Black detection done ++// Bit 28:16 blkbar_top_pos. Top black bar position ++// Bit 15:13 Reserved. ++// Bit 12:0 blkbar_bot_pos. Bottom black bar position ++#define VDIN_BLKBAR_STATUS0 (0x126b) ++#define P_VDIN_BLKBAR_STATUS0 (volatile unsigned int *)((0x126b << 2) + 0xff900000) ++//Readonly ++// Bit 31:29 Reserved ++// Bit 28:16 blkbar_left_pos. Left black bar posiont ++// Bit 15:13 Reserved ++// Bit 12:0 blkbar_right_pos. Right black bar position ++#define VDIN_BLKBAR_STATUS1 (0x126c) ++#define P_VDIN_BLKBAR_STATUS1 (volatile unsigned int *)((0x126c << 2) + 0xff900000) ++//Bit 28:16 input window H start ++//Bit 12:0 input window H end ++#define VDIN_WIN_H_START_END (0x126d) ++#define P_VDIN_WIN_H_START_END (volatile unsigned int *)((0x126d << 2) + 0xff900000) ++//Bit 28:16 input window H start ++//Bit 12:0 input window V start ++#define VDIN_WIN_V_START_END (0x126e) ++#define P_VDIN_WIN_V_START_END (volatile unsigned int *)((0x126e << 2) + 0xff900000) ++//Bit 23:16 vdi8 asfifo_ctrl ++//Bit 15:8 vdi7 asfifo_ctrl ++//Bit 7:0 vdi6 asfifo_ctrl ++#define VDIN_ASFIFO_CTRL3 (0x126f) ++#define P_VDIN_ASFIFO_CTRL3 (volatile unsigned int *)((0x126f << 2) + 0xff900000) ++//Bit 3:2 vshrk_clk2_ctrl ++//Bit 1:0 vshrk_clk1_ctrl ++#define VDIN_COM_GCLK_CTRL2 (0x1270) ++#define P_VDIN_COM_GCLK_CTRL2 (volatile unsigned int *)((0x1270 << 2) + 0xff900000) ++//Bit 27 vshrk_en ++//Bit 26:25 vshrk_mode ++//Bit 24 vshrk_lpf_mode ++//Bit 23:0 vshrk_dummy ++#define VDIN_VSHRK_CTRL (0x1271) ++#define P_VDIN_VSHRK_CTRL (volatile unsigned int *)((0x1271 << 2) + 0xff900000) ++#define VDIN_DNLP_HIST32 (0x1272) ++#define P_VDIN_DNLP_HIST32 (volatile unsigned int *)((0x1272 << 2) + 0xff900000) ++//Read only ++//Bit 7, vdi9 fifo overflow ++//Bit 5:0, vdi9_asfifo_cnt ++#define VDIN_COM_STATUS3 (0x1273) ++#define P_VDIN_COM_STATUS3 (volatile unsigned int *)((0x1273 << 2) + 0xff900000) ++#define VDIN_SYNC_MASK (0x1274) ++#define P_VDIN_SYNC_MASK (volatile unsigned int *)((0x1274 << 2) + 0xff900000) ++//Bit 7:0, hsync_mask_num ++//Bit 15:8, vsync_mask_num ++//Bit 16, hsync_mask_enable ++//Bit 17, vsync_mask_num ++//dolby vdin ++#define VDIN_DOLBY_DSC_CTRL0 (0x1275) ++#define P_VDIN_DOLBY_DSC_CTRL0 (volatile unsigned int *)((0x1275 << 2) + 0xff900000) ++#define VDIN_DOLBY_DSC_CTRL1 (0x1276) ++#define P_VDIN_DOLBY_DSC_CTRL1 (volatile unsigned int *)((0x1276 << 2) + 0xff900000) ++#define VDIN_DOLBY_DSC_CTRL2 (0x1277) ++#define P_VDIN_DOLBY_DSC_CTRL2 (volatile unsigned int *)((0x1277 << 2) + 0xff900000) ++#define VDIN_DOLBY_DSC_CTRL3 (0x1278) ++#define P_VDIN_DOLBY_DSC_CTRL3 (volatile unsigned int *)((0x1278 << 2) + 0xff900000) ++#define VDIN_DOLBY_AXI_CTRL0 (0x1279) ++#define P_VDIN_DOLBY_AXI_CTRL0 (volatile unsigned int *)((0x1279 << 2) + 0xff900000) ++#define VDIN_DOLBY_AXI_CTRL1 (0x127a) ++#define P_VDIN_DOLBY_AXI_CTRL1 (volatile unsigned int *)((0x127a << 2) + 0xff900000) ++#define VDIN_DOLBY_AXI_CTRL2 (0x127b) ++#define P_VDIN_DOLBY_AXI_CTRL2 (volatile unsigned int *)((0x127b << 2) + 0xff900000) ++#define VDIN_DOLBY_AXI_CTRL3 (0x127c) ++#define P_VDIN_DOLBY_AXI_CTRL3 (volatile unsigned int *)((0x127c << 2) + 0xff900000) ++#define VDIN_DOLBY_DSC_STATUS0 (0x127d) ++#define P_VDIN_DOLBY_DSC_STATUS0 (volatile unsigned int *)((0x127d << 2) + 0xff900000) ++#define VDIN_DOLBY_DSC_STATUS1 (0x127e) ++#define P_VDIN_DOLBY_DSC_STATUS1 (volatile unsigned int *)((0x127e << 2) + 0xff900000) ++#define VDIN_DOLBY_DSC_STATUS2 (0x127f) ++#define P_VDIN_DOLBY_DSC_STATUS2 (volatile unsigned int *)((0x127f << 2) + 0xff900000) ++#define VDIN_DOLBY_DSC_STATUS3 (0x121d) ++#define P_VDIN_DOLBY_DSC_STATUS3 (volatile unsigned int *)((0x121d << 2) + 0xff900000) ++ ++//8'h72 occupied by histogram 32 ++//VDIN0 8'h00 - 8'h7f ++#define VDIN0_SCALE_COEF_IDX ((VDIN0_OFFSET << 2) + VDIN_SCALE_COEF_IDX ) ++#define VDIN0_SCALE_COEF ((VDIN0_OFFSET << 2) + VDIN_SCALE_COEF ) ++#define VDIN0_COM_CTRL0 ((VDIN0_OFFSET << 2) + VDIN_COM_CTRL0 ) ++#define VDIN0_ACTIVE_MAX_PIX_CNT_STATUS ((VDIN0_OFFSET << 2) + VDIN_ACTIVE_MAX_PIX_CNT_STATUS ) ++#define VDIN0_LCNT_STATUS ((VDIN0_OFFSET << 2) + VDIN_LCNT_STATUS ) ++#define VDIN0_COM_STATUS0 ((VDIN0_OFFSET << 2) + VDIN_COM_STATUS0 ) ++#define VDIN0_COM_STATUS1 ((VDIN0_OFFSET << 2) + VDIN_COM_STATUS1 ) ++#define VDIN0_LCNT_SHADOW_STATUS ((VDIN0_OFFSET << 2) + VDIN_LCNT_SHADOW_STATUS ) ++#define VDIN0_ASFIFO_CTRL0 ((VDIN0_OFFSET << 2) + VDIN_ASFIFO_CTRL0 ) ++#define VDIN0_ASFIFO_CTRL1 ((VDIN0_OFFSET << 2) + VDIN_ASFIFO_CTRL1 ) ++#define VDIN0_WIDTHM1I_WIDTHM1O ((VDIN0_OFFSET << 2) + VDIN_WIDTHM1I_WIDTHM1O ) ++#define VDIN0_SC_MISC_CTRL ((VDIN0_OFFSET << 2) + VDIN_SC_MISC_CTRL ) ++#define VDIN0_HSC_PHASE_STEP ((VDIN0_OFFSET << 2) + VDIN_HSC_PHASE_STEP ) ++#define VDIN0_HSC_INI_CTRL ((VDIN0_OFFSET << 2) + VDIN_HSC_INI_CTRL ) ++#define VDIN0_COM_STATUS2 ((VDIN0_OFFSET << 2) + VDIN_COM_STATUS2 ) ++#define VDIN0_COM_STATUS3 ((VDIN0_OFFSET << 2) + VDIN_COM_STATUS3 ) ++#define VDIN0_ASFIFO_CTRL2 ((VDIN0_OFFSET << 2) + VDIN_ASFIFO_CTRL2 ) ++#define VDIN0_MATRIX_CTRL ((VDIN0_OFFSET << 2) + VDIN_MATRIX_CTRL ) ++#define VDIN0_MATRIX_COEF00_01 ((VDIN0_OFFSET << 2) + VDIN_MATRIX_COEF00_01 ) ++#define VDIN0_MATRIX_COEF02_10 ((VDIN0_OFFSET << 2) + VDIN_MATRIX_COEF02_10 ) ++#define VDIN0_MATRIX_COEF11_12 ((VDIN0_OFFSET << 2) + VDIN_MATRIX_COEF11_12 ) ++#define VDIN0_MATRIX_COEF20_21 ((VDIN0_OFFSET << 2) + VDIN_MATRIX_COEF20_21 ) ++#define VDIN0_MATRIX_COEF22 ((VDIN0_OFFSET << 2) + VDIN_MATRIX_COEF22 ) ++#define VDIN0_MATRIX_OFFSET0_1 ((VDIN0_OFFSET << 2) + VDIN_MATRIX_OFFSET0_1 ) ++#define VDIN0_MATRIX_OFFSET2 ((VDIN0_OFFSET << 2) + VDIN_MATRIX_OFFSET2 ) ++#define VDIN0_MATRIX_PRE_OFFSET0_1 ((VDIN0_OFFSET << 2) + VDIN_MATRIX_PRE_OFFSET0_1 ) ++#define VDIN0_MATRIX_PRE_OFFSET2 ((VDIN0_OFFSET << 2) + VDIN_MATRIX_PRE_OFFSET2 ) ++#define VDIN0_LFIFO_CTRL ((VDIN0_OFFSET << 2) + VDIN_LFIFO_CTRL ) ++#define VDIN0_COM_GCLK_CTRL ((VDIN0_OFFSET << 2) + VDIN_COM_GCLK_CTRL ) ++#define VDIN0_INTF_WIDTHM1 ((VDIN0_OFFSET << 2) + VDIN_INTF_WIDTHM1 ) ++#define VDIN0_WR_CTRL2 ((VDIN0_OFFSET << 2) + VDIN_WR_CTRL2 ) ++#define VDIN0_WR_CTRL ((VDIN0_OFFSET << 2) + VDIN_WR_CTRL ) ++#define VDIN0_WR_H_START_END ((VDIN0_OFFSET << 2) + VDIN_WR_H_START_END ) ++#define VDIN0_WR_V_START_END ((VDIN0_OFFSET << 2) + VDIN_WR_V_START_END ) ++#define VDIN0_VSC_PHASE_STEP ((VDIN0_OFFSET << 2) + VDIN_VSC_PHASE_STEP ) ++#define VDIN0_VSC_INI_CTRL ((VDIN0_OFFSET << 2) + VDIN_VSC_INI_CTRL ) ++#define VDIN0_SCIN_HEIGHTM1 ((VDIN0_OFFSET << 2) + VDIN_SCIN_HEIGHTM1 ) ++#define VDIN0_DUMMY_DATA ((VDIN0_OFFSET << 2) + VDIN_DUMMY_DATA ) ++#define VDIN0_MATRIX_PROBE_COLOR ((VDIN0_OFFSET << 2) + VDIN_MATRIX_PROBE_COLOR ) ++#define VDIN0_MATRIX_HL_COLOR ((VDIN0_OFFSET << 2) + VDIN_MATRIX_HL_COLOR ) ++#define VDIN0_MATRIX_PROBE_POS ((VDIN0_OFFSET << 2) + VDIN_MATRIX_PROBE_POS ) ++#define VDIN0_CHROMA_ADDR_PORT ((VDIN0_OFFSET << 2) + VDIN_CHROMA_ADDR_PORT ) ++#define VDIN0_CHROMA_DATA_PORT ((VDIN0_OFFSET << 2) + VDIN_CHROMA_DATA_PORT ) ++#define VDIN0_CM_BRI_CON_CTRL ((VDIN0_OFFSET << 2) + VDIN_CM_BRI_CON_CTRL ) ++#define VDIN0_HIST_CTRL ((VDIN0_OFFSET << 2) + VDIN_HIST_CTRL ) ++#define VDIN0_HIST_H_START_END ((VDIN0_OFFSET << 2) + VDIN_HIST_H_START_END ) ++#define VDIN0_HIST_V_START_END ((VDIN0_OFFSET << 2) + VDIN_HIST_V_START_END ) ++#define VDIN0_HIST_MAX_MIN ((VDIN0_OFFSET << 2) + VDIN_HIST_MAX_MIN ) ++#define VDIN0_HIST_SPL_VAL ((VDIN0_OFFSET << 2) + VDIN_HIST_SPL_VAL ) ++#define VDIN0_HIST_SPL_PIX_CNT ((VDIN0_OFFSET << 2) + VDIN_HIST_SPL_PIX_CNT ) ++#define VDIN0_HIST_CHROMA_SUM ((VDIN0_OFFSET << 2) + VDIN_HIST_CHROMA_SUM ) ++#define VDIN0_DNLP_HIST00 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST00 ) ++#define VDIN0_DNLP_HIST01 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST01 ) ++#define VDIN0_DNLP_HIST02 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST02 ) ++#define VDIN0_DNLP_HIST03 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST03 ) ++#define VDIN0_DNLP_HIST04 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST04 ) ++#define VDIN0_DNLP_HIST05 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST05 ) ++#define VDIN0_DNLP_HIST06 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST06 ) ++#define VDIN0_DNLP_HIST07 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST07 ) ++#define VDIN0_DNLP_HIST08 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST08 ) ++#define VDIN0_DNLP_HIST09 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST09 ) ++#define VDIN0_DNLP_HIST10 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST10 ) ++#define VDIN0_DNLP_HIST11 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST11 ) ++#define VDIN0_DNLP_HIST12 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST12 ) ++#define VDIN0_DNLP_HIST13 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST13 ) ++#define VDIN0_DNLP_HIST14 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST14 ) ++#define VDIN0_DNLP_HIST15 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST15 ) ++#define VDIN0_DNLP_HIST16 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST16 ) ++#define VDIN0_DNLP_HIST17 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST17 ) ++#define VDIN0_DNLP_HIST18 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST18 ) ++#define VDIN0_DNLP_HIST19 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST19 ) ++#define VDIN0_DNLP_HIST20 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST20 ) ++#define VDIN0_DNLP_HIST21 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST21 ) ++#define VDIN0_DNLP_HIST22 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST22 ) ++#define VDIN0_DNLP_HIST23 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST23 ) ++#define VDIN0_DNLP_HIST24 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST24 ) ++#define VDIN0_DNLP_HIST25 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST25 ) ++#define VDIN0_DNLP_HIST26 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST26 ) ++#define VDIN0_DNLP_HIST27 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST27 ) ++#define VDIN0_DNLP_HIST28 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST28 ) ++#define VDIN0_DNLP_HIST29 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST29 ) ++#define VDIN0_DNLP_HIST30 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST30 ) ++#define VDIN0_DNLP_HIST31 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST31 ) ++#define VDIN0_DNLP_HIST32 ((VDIN0_OFFSET << 2) + VDIN_DNLP_HIST32 ) ++#define VDIN0_LDIM_STTS_HIST_REGION_IDX ((VDIN0_OFFSET << 2) + VDIN_LDIM_STTS_HIST_REGION_IDX ) ++#define VDIN0_LDIM_STTS_HIST_SET_REGION ((VDIN0_OFFSET << 2) + VDIN_LDIM_STTS_HIST_SET_REGION ) ++#define VDIN0_LDIM_STTS_HIST_READ_REGION ((VDIN0_OFFSET << 2) + VDIN_LDIM_STTS_HIST_READ_REGION ) ++#define VDIN0_MEAS_CTRL0 ((VDIN0_OFFSET << 2) + VDIN_MEAS_CTRL0 ) ++#define VDIN0_MEAS_VS_COUNT_HI ((VDIN0_OFFSET << 2) + VDIN_MEAS_VS_COUNT_HI ) ++#define VDIN0_MEAS_VS_COUNT_LO ((VDIN0_OFFSET << 2) + VDIN_MEAS_VS_COUNT_LO ) ++#define VDIN0_MEAS_HS_RANGE ((VDIN0_OFFSET << 2) + VDIN_MEAS_HS_RANGE ) ++#define VDIN0_MEAS_HS_COUNT ((VDIN0_OFFSET << 2) + VDIN_MEAS_HS_COUNT ) ++#define VDIN0_BLKBAR_CTRL1 ((VDIN0_OFFSET << 2) + VDIN_BLKBAR_CTRL1 ) ++#define VDIN0_BLKBAR_CTRL0 ((VDIN0_OFFSET << 2) + VDIN_BLKBAR_CTRL0 ) ++#define VDIN0_BLKBAR_H_START_END ((VDIN0_OFFSET << 2) + VDIN_BLKBAR_H_START_END ) ++#define VDIN0_BLKBAR_V_START_END ((VDIN0_OFFSET << 2) + VDIN_BLKBAR_V_START_END ) ++#define VDIN0_BLKBAR_CNT_THRESHOLD ((VDIN0_OFFSET << 2) + VDIN_BLKBAR_CNT_THRESHOLD ) ++#define VDIN0_BLKBAR_ROW_TH1_TH2 ((VDIN0_OFFSET << 2) + VDIN_BLKBAR_ROW_TH1_TH2 ) ++#define VDIN0_BLKBAR_IND_LEFT_START_END ((VDIN0_OFFSET << 2) + VDIN_BLKBAR_IND_LEFT_START_END ) ++#define VDIN0_BLKBAR_IND_RIGHT_START_END ((VDIN0_OFFSET << 2) + VDIN_BLKBAR_IND_RIGHT_START_END ) ++#define VDIN0_BLKBAR_IND_LEFT1_CNT ((VDIN0_OFFSET << 2) + VDIN_BLKBAR_IND_LEFT1_CNT ) ++#define VDIN0_BLKBAR_IND_LEFT2_CNT ((VDIN0_OFFSET << 2) + VDIN_BLKBAR_IND_LEFT2_CNT ) ++#define VDIN0_BLKBAR_IND_RIGHT1_CNT ((VDIN0_OFFSET << 2) + VDIN_BLKBAR_IND_RIGHT1_CNT ) ++#define VDIN0_BLKBAR_IND_RIGHT2_CNT ((VDIN0_OFFSET << 2) + VDIN_BLKBAR_IND_RIGHT2_CNT ) ++#define VDIN0_BLKBAR_STATUS0 ((VDIN0_OFFSET << 2) + VDIN_BLKBAR_STATUS0 ) ++#define VDIN0_BLKBAR_STATUS1 ((VDIN0_OFFSET << 2) + VDIN_BLKBAR_STATUS1 ) ++#define VDIN0_WIN_H_START_END ((VDIN0_OFFSET << 2) + VDIN_WIN_H_START_END ) ++#define VDIN0_WIN_V_START_END ((VDIN0_OFFSET << 2) + VDIN_WIN_V_START_END ) ++#define VDIN0_ASFIFO_CTRL3 ((VDIN0_OFFSET << 2) + VDIN_ASFIFO_CTRL3 ) ++#define VDIN0_COM_GCLK_CTRL2 ((VDIN0_OFFSET << 2) + VDIN_COM_GCLK_CTRL2 ) ++#define VDIN0_VSHRK_CTRL ((VDIN0_OFFSET << 2) + VDIN_VSHRK_CTRL ) ++#define VDIN0_SYNC_MASK ((VDIN0_OFFSET << 2) + VDIN_SYNC_MASK ) ++#define VDIN0_DOLBY_DSC_CTRL0 ((VDIN0_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL0 ) ++#define VDIN0_DOLBY_DSC_CTRL1 ((VDIN0_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL1 ) ++#define VDIN0_DOLBY_DSC_CTRL2 ((VDIN0_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL2 ) ++#define VDIN0_DOLBY_DSC_CTRL3 ((VDIN0_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL3 ) ++#define VDIN0_DOLBY_AXI_CTRL0 ((VDIN0_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL0 ) ++#define VDIN0_DOLBY_AXI_CTRL1 ((VDIN0_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL1 ) ++#define VDIN0_DOLBY_AXI_CTRL2 ((VDIN0_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL2 ) ++#define VDIN0_DOLBY_AXI_CTRL3 ((VDIN0_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL3 ) ++#define VDIN0_DOLBY_DSC_STATUS0 ((VDIN0_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS0) ++#define VDIN0_DOLBY_DSC_STATUS1 ((VDIN0_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS1) ++#define VDIN0_DOLBY_DSC_STATUS2 ((VDIN0_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS2) ++#define VDIN0_DOLBY_DSC_STATUS3 ((VDIN0_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS3) ++ ++ ++//VDIN1 8'h80 - 8'hef ++#define VDIN1_SCALE_COEF_IDX ((VDIN1_OFFSET << 2) + VDIN_SCALE_COEF_IDX ) ++#define VDIN1_SCALE_COEF ((VDIN1_OFFSET << 2) + VDIN_SCALE_COEF ) ++#define VDIN1_COM_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_COM_CTRL0 ) ++#define VDIN1_ACTIVE_MAX_PIX_CNT_STATUS ((VDIN1_OFFSET << 2) + VDIN_ACTIVE_MAX_PIX_CNT_STATUS ) ++#define VDIN1_LCNT_STATUS ((VDIN1_OFFSET << 2) + VDIN_LCNT_STATUS ) ++#define VDIN1_COM_STATUS0 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS0 ) ++#define VDIN1_COM_STATUS1 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS1 ) ++#define VDIN1_LCNT_SHADOW_STATUS ((VDIN1_OFFSET << 2) + VDIN_LCNT_SHADOW_STATUS ) ++#define VDIN1_ASFIFO_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL0 ) ++#define VDIN1_ASFIFO_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL1 ) ++#define VDIN1_WIDTHM1I_WIDTHM1O ((VDIN1_OFFSET << 2) + VDIN_WIDTHM1I_WIDTHM1O ) ++#define VDIN1_SC_MISC_CTRL ((VDIN1_OFFSET << 2) + VDIN_SC_MISC_CTRL ) ++#define VDIN1_HSC_PHASE_STEP ((VDIN1_OFFSET << 2) + VDIN_HSC_PHASE_STEP ) ++#define VDIN1_HSC_INI_CTRL ((VDIN1_OFFSET << 2) + VDIN_HSC_INI_CTRL ) ++#define VDIN1_COM_STATUS2 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS2 ) ++#define VDIN1_COM_STATUS3 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS3 ) ++#define VDIN1_ASFIFO_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL2 ) ++#define VDIN1_MATRIX_CTRL ((VDIN1_OFFSET << 2) + VDIN_MATRIX_CTRL ) ++#define VDIN1_MATRIX_COEF00_01 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF00_01 ) ++#define VDIN1_MATRIX_COEF02_10 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF02_10 ) ++#define VDIN1_MATRIX_COEF11_12 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF11_12 ) ++#define VDIN1_MATRIX_COEF20_21 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF20_21 ) ++#define VDIN1_MATRIX_COEF22 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF22 ) ++#define VDIN1_MATRIX_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_OFFSET0_1 ) ++#define VDIN1_MATRIX_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_OFFSET2 ) ++#define VDIN1_MATRIX_PRE_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PRE_OFFSET0_1 ) ++#define VDIN1_MATRIX_PRE_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PRE_OFFSET2 ) ++#define VDIN1_LFIFO_CTRL ((VDIN1_OFFSET << 2) + VDIN_LFIFO_CTRL ) ++#define VDIN1_COM_GCLK_CTRL ((VDIN1_OFFSET << 2) + VDIN_COM_GCLK_CTRL ) ++#define VDIN1_INTF_WIDTHM1 ((VDIN1_OFFSET << 2) + VDIN_INTF_WIDTHM1 ) ++#define VDIN1_WR_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_WR_CTRL2 ) ++#define VDIN1_WR_CTRL ((VDIN1_OFFSET << 2) + VDIN_WR_CTRL ) ++#define VDIN1_WR_H_START_END ((VDIN1_OFFSET << 2) + VDIN_WR_H_START_END ) ++#define VDIN1_WR_V_START_END ((VDIN1_OFFSET << 2) + VDIN_WR_V_START_END ) ++#define VDIN1_VSC_PHASE_STEP ((VDIN1_OFFSET << 2) + VDIN_VSC_PHASE_STEP ) ++#define VDIN1_VSC_INI_CTRL ((VDIN1_OFFSET << 2) + VDIN_VSC_INI_CTRL ) ++#define VDIN1_SCIN_HEIGHTM1 ((VDIN1_OFFSET << 2) + VDIN_SCIN_HEIGHTM1 ) ++#define VDIN1_DUMMY_DATA ((VDIN1_OFFSET << 2) + VDIN_DUMMY_DATA ) ++#define VDIN1_MATRIX_PROBE_COLOR ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PROBE_COLOR ) ++#define VDIN1_MATRIX_HL_COLOR ((VDIN1_OFFSET << 2) + VDIN_MATRIX_HL_COLOR ) ++#define VDIN1_MATRIX_PROBE_POS ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PROBE_POS ) ++#define VDIN1_CHROMA_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_CHROMA_ADDR_PORT ) ++#define VDIN1_CHROMA_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_CHROMA_DATA_PORT ) ++#define VDIN1_CM_BRI_CON_CTRL ((VDIN1_OFFSET << 2) + VDIN_CM_BRI_CON_CTRL ) ++#define VDIN1_HIST_CTRL ((VDIN1_OFFSET << 2) + VDIN_HIST_CTRL ) ++#define VDIN1_HIST_H_START_END ((VDIN1_OFFSET << 2) + VDIN_HIST_H_START_END ) ++#define VDIN1_HIST_V_START_END ((VDIN1_OFFSET << 2) + VDIN_HIST_V_START_END ) ++#define VDIN1_HIST_MAX_MIN ((VDIN1_OFFSET << 2) + VDIN_HIST_MAX_MIN ) ++#define VDIN1_HIST_SPL_VAL ((VDIN1_OFFSET << 2) + VDIN_HIST_SPL_VAL ) ++#define VDIN1_HIST_SPL_PIX_CNT ((VDIN1_OFFSET << 2) + VDIN_HIST_SPL_PIX_CNT ) ++#define VDIN1_HIST_CHROMA_SUM ((VDIN1_OFFSET << 2) + VDIN_HIST_CHROMA_SUM ) ++#define VDIN1_DNLP_HIST00 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST00 ) ++#define VDIN1_DNLP_HIST01 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST01 ) ++#define VDIN1_DNLP_HIST02 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST02 ) ++#define VDIN1_DNLP_HIST03 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST03 ) ++#define VDIN1_DNLP_HIST04 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST04 ) ++#define VDIN1_DNLP_HIST05 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST05 ) ++#define VDIN1_DNLP_HIST06 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST06 ) ++#define VDIN1_DNLP_HIST07 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST07 ) ++#define VDIN1_DNLP_HIST08 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST08 ) ++#define VDIN1_DNLP_HIST09 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST09 ) ++#define VDIN1_DNLP_HIST10 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST10 ) ++#define VDIN1_DNLP_HIST11 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST11 ) ++#define VDIN1_DNLP_HIST12 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST12 ) ++#define VDIN1_DNLP_HIST13 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST13 ) ++#define VDIN1_DNLP_HIST14 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST14 ) ++#define VDIN1_DNLP_HIST15 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST15 ) ++#define VDIN1_DNLP_HIST16 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST16 ) ++#define VDIN1_DNLP_HIST17 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST17 ) ++#define VDIN1_DNLP_HIST18 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST18 ) ++#define VDIN1_DNLP_HIST19 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST19 ) ++#define VDIN1_DNLP_HIST20 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST20 ) ++#define VDIN1_DNLP_HIST21 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST21 ) ++#define VDIN1_DNLP_HIST22 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST22 ) ++#define VDIN1_DNLP_HIST23 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST23 ) ++#define VDIN1_DNLP_HIST24 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST24 ) ++#define VDIN1_DNLP_HIST25 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST25 ) ++#define VDIN1_DNLP_HIST26 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST26 ) ++#define VDIN1_DNLP_HIST27 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST27 ) ++#define VDIN1_DNLP_HIST28 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST28 ) ++#define VDIN1_DNLP_HIST29 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST29 ) ++#define VDIN1_DNLP_HIST30 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST30 ) ++#define VDIN1_DNLP_HIST31 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST31 ) ++#define VDIN1_DNLP_HIST32 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST32 ) ++#define VDIN1_LDIM_STTS_HIST_REGION_IDX ((VDIN1_OFFSET << 2) + VDIN_LDIM_STTS_HIST_REGION_IDX ) ++#define VDIN1_LDIM_STTS_HIST_SET_REGION ((VDIN1_OFFSET << 2) + VDIN_LDIM_STTS_HIST_SET_REGION ) ++#define VDIN1_LDIM_STTS_HIST_READ_REGION ((VDIN1_OFFSET << 2) + VDIN_LDIM_STTS_HIST_READ_REGION ) ++#define VDIN1_MEAS_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_MEAS_CTRL0 ) ++#define VDIN1_MEAS_VS_COUNT_HI ((VDIN1_OFFSET << 2) + VDIN_MEAS_VS_COUNT_HI ) ++#define VDIN1_MEAS_VS_COUNT_LO ((VDIN1_OFFSET << 2) + VDIN_MEAS_VS_COUNT_LO ) ++#define VDIN1_MEAS_HS_RANGE ((VDIN1_OFFSET << 2) + VDIN_MEAS_HS_RANGE ) ++#define VDIN1_MEAS_HS_COUNT ((VDIN1_OFFSET << 2) + VDIN_MEAS_HS_COUNT ) ++#define VDIN1_BLKBAR_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_CTRL1 ) ++#define VDIN1_BLKBAR_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_CTRL0 ) ++#define VDIN1_BLKBAR_H_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_H_START_END ) ++#define VDIN1_BLKBAR_V_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_V_START_END ) ++#define VDIN1_BLKBAR_CNT_THRESHOLD ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_CNT_THRESHOLD ) ++#define VDIN1_BLKBAR_ROW_TH1_TH2 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_ROW_TH1_TH2 ) ++#define VDIN1_BLKBAR_IND_LEFT_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_LEFT_START_END ) ++#define VDIN1_BLKBAR_IND_RIGHT_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_RIGHT_START_END ) ++#define VDIN1_BLKBAR_IND_LEFT1_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_LEFT1_CNT ) ++#define VDIN1_BLKBAR_IND_LEFT2_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_LEFT2_CNT ) ++#define VDIN1_BLKBAR_IND_RIGHT1_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_RIGHT1_CNT ) ++#define VDIN1_BLKBAR_IND_RIGHT2_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_RIGHT2_CNT ) ++#define VDIN1_BLKBAR_STATUS0 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_STATUS0 ) ++#define VDIN1_BLKBAR_STATUS1 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_STATUS1 ) ++#define VDIN1_WIN_H_START_END ((VDIN1_OFFSET << 2) + VDIN_WIN_H_START_END ) ++#define VDIN1_WIN_V_START_END ((VDIN1_OFFSET << 2) + VDIN_WIN_V_START_END ) ++#define VDIN1_ASFIFO_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL3 ) ++#define VDIN1_COM_GCLK_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_COM_GCLK_CTRL2 ) ++#define VDIN1_VSHRK_CTRL ((VDIN1_OFFSET << 2) + VDIN_VSHRK_CTRL ) ++#define VDIN1_SYNC_MASK ((VDIN1_OFFSET << 2) + VDIN_SYNC_MASK ) ++#define VDIN1_DOLBY_DSC_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL0 ) ++#define VDIN1_DOLBY_DSC_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL1 ) ++#define VDIN1_DOLBY_DSC_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL2 ) ++#define VDIN1_DOLBY_DSC_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL3 ) ++#define VDIN1_DOLBY_AXI_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL0 ) ++#define VDIN1_DOLBY_AXI_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL1 ) ++#define VDIN1_DOLBY_AXI_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL2 ) ++#define VDIN1_DOLBY_AXI_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL3 ) ++#define VDIN1_DOLBY_DSC_STATUS0 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS0) ++#define VDIN1_DOLBY_DSC_STATUS1 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS1) ++#define VDIN1_DOLBY_DSC_STATUS2 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS2) ++#define VDIN1_DOLBY_DSC_STATUS3 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS3) ++ ++//`define LCD_VCBUS_BASE 8'h14 ++// ++// Reading file: lcd_regs.h ++// ++// ----------------------------------------------- ++// CBUS_BASE: LCD_VCBUS_BASE = 0x14 ++// ----------------------------------------------- ++//======================================================================== ++//LCD DRV 12'h480~12'h4ef ++//======================================================================= ++#define L_GAMMA_CNTL_PORT (0x1400) ++#define P_L_GAMMA_CNTL_PORT (volatile unsigned int *)((0x1400 << 2) + 0xff900000) ++#define L_GAMMA_DATA_PORT (0x1401) ++#define P_L_GAMMA_DATA_PORT (volatile unsigned int *)((0x1401 << 2) + 0xff900000) ++#define L_GAMMA_ADDR_PORT (0x1402) ++#define P_L_GAMMA_ADDR_PORT (volatile unsigned int *)((0x1402 << 2) + 0xff900000) ++#define L_GAMMA_VCOM_HSWITCH_ADDR (0x1403) ++#define P_L_GAMMA_VCOM_HSWITCH_ADDR (volatile unsigned int *)((0x1403 << 2) + 0xff900000) ++#define L_RGB_BASE_ADDR (0x1405) ++#define P_L_RGB_BASE_ADDR (volatile unsigned int *)((0x1405 << 2) + 0xff900000) ++#define L_RGB_COEFF_ADDR (0x1406) ++#define P_L_RGB_COEFF_ADDR (volatile unsigned int *)((0x1406 << 2) + 0xff900000) ++#define L_POL_CNTL_ADDR (0x1407) ++#define P_L_POL_CNTL_ADDR (volatile unsigned int *)((0x1407 << 2) + 0xff900000) ++#define L_DITH_CNTL_ADDR (0x1408) ++#define P_L_DITH_CNTL_ADDR (volatile unsigned int *)((0x1408 << 2) + 0xff900000) ++#define L_GAMMA_PROBE_CTRL (0x1409) ++#define P_L_GAMMA_PROBE_CTRL (volatile unsigned int *)((0x1409 << 2) + 0xff900000) ++//read only ++#define L_GAMMA_PROBE_COLOR_L (0x140a) ++#define P_L_GAMMA_PROBE_COLOR_L (volatile unsigned int *)((0x140a << 2) + 0xff900000) ++#define L_GAMMA_PROBE_COLOR_H (0x140b) ++#define P_L_GAMMA_PROBE_COLOR_H (volatile unsigned int *)((0x140b << 2) + 0xff900000) ++#define L_GAMMA_PROBE_HL_COLOR (0x140c) ++#define P_L_GAMMA_PROBE_HL_COLOR (volatile unsigned int *)((0x140c << 2) + 0xff900000) ++#define L_GAMMA_PROBE_POS_X (0x140d) ++#define P_L_GAMMA_PROBE_POS_X (volatile unsigned int *)((0x140d << 2) + 0xff900000) ++#define L_GAMMA_PROBE_POS_Y (0x140e) ++#define P_L_GAMMA_PROBE_POS_Y (volatile unsigned int *)((0x140e << 2) + 0xff900000) ++#define L_STH1_HS_ADDR (0x1410) ++#define P_L_STH1_HS_ADDR (volatile unsigned int *)((0x1410 << 2) + 0xff900000) ++#define L_STH1_HE_ADDR (0x1411) ++#define P_L_STH1_HE_ADDR (volatile unsigned int *)((0x1411 << 2) + 0xff900000) ++#define L_STH1_VS_ADDR (0x1412) ++#define P_L_STH1_VS_ADDR (volatile unsigned int *)((0x1412 << 2) + 0xff900000) ++#define L_STH1_VE_ADDR (0x1413) ++#define P_L_STH1_VE_ADDR (volatile unsigned int *)((0x1413 << 2) + 0xff900000) ++#define L_STH2_HS_ADDR (0x1414) ++#define P_L_STH2_HS_ADDR (volatile unsigned int *)((0x1414 << 2) + 0xff900000) ++#define L_STH2_HE_ADDR (0x1415) ++#define P_L_STH2_HE_ADDR (volatile unsigned int *)((0x1415 << 2) + 0xff900000) ++#define L_STH2_VS_ADDR (0x1416) ++#define P_L_STH2_VS_ADDR (volatile unsigned int *)((0x1416 << 2) + 0xff900000) ++#define L_STH2_VE_ADDR (0x1417) ++#define P_L_STH2_VE_ADDR (volatile unsigned int *)((0x1417 << 2) + 0xff900000) ++#define L_OEH_HS_ADDR (0x1418) ++#define P_L_OEH_HS_ADDR (volatile unsigned int *)((0x1418 << 2) + 0xff900000) ++#define L_OEH_HE_ADDR (0x1419) ++#define P_L_OEH_HE_ADDR (volatile unsigned int *)((0x1419 << 2) + 0xff900000) ++#define L_OEH_VS_ADDR (0x141a) ++#define P_L_OEH_VS_ADDR (volatile unsigned int *)((0x141a << 2) + 0xff900000) ++#define L_OEH_VE_ADDR (0x141b) ++#define P_L_OEH_VE_ADDR (volatile unsigned int *)((0x141b << 2) + 0xff900000) ++#define L_VCOM_HSWITCH_ADDR (0x141c) ++#define P_L_VCOM_HSWITCH_ADDR (volatile unsigned int *)((0x141c << 2) + 0xff900000) ++#define L_VCOM_VS_ADDR (0x141d) ++#define P_L_VCOM_VS_ADDR (volatile unsigned int *)((0x141d << 2) + 0xff900000) ++#define L_VCOM_VE_ADDR (0x141e) ++#define P_L_VCOM_VE_ADDR (volatile unsigned int *)((0x141e << 2) + 0xff900000) ++#define L_CPV1_HS_ADDR (0x141f) ++#define P_L_CPV1_HS_ADDR (volatile unsigned int *)((0x141f << 2) + 0xff900000) ++#define L_CPV1_HE_ADDR (0x1420) ++#define P_L_CPV1_HE_ADDR (volatile unsigned int *)((0x1420 << 2) + 0xff900000) ++#define L_CPV1_VS_ADDR (0x1421) ++#define P_L_CPV1_VS_ADDR (volatile unsigned int *)((0x1421 << 2) + 0xff900000) ++#define L_CPV1_VE_ADDR (0x1422) ++#define P_L_CPV1_VE_ADDR (volatile unsigned int *)((0x1422 << 2) + 0xff900000) ++#define L_CPV2_HS_ADDR (0x1423) ++#define P_L_CPV2_HS_ADDR (volatile unsigned int *)((0x1423 << 2) + 0xff900000) ++#define L_CPV2_HE_ADDR (0x1424) ++#define P_L_CPV2_HE_ADDR (volatile unsigned int *)((0x1424 << 2) + 0xff900000) ++#define L_CPV2_VS_ADDR (0x1425) ++#define P_L_CPV2_VS_ADDR (volatile unsigned int *)((0x1425 << 2) + 0xff900000) ++#define L_CPV2_VE_ADDR (0x1426) ++#define P_L_CPV2_VE_ADDR (volatile unsigned int *)((0x1426 << 2) + 0xff900000) ++#define L_STV1_HS_ADDR (0x1427) ++#define P_L_STV1_HS_ADDR (volatile unsigned int *)((0x1427 << 2) + 0xff900000) ++#define L_STV1_HE_ADDR (0x1428) ++#define P_L_STV1_HE_ADDR (volatile unsigned int *)((0x1428 << 2) + 0xff900000) ++#define L_STV1_VS_ADDR (0x1429) ++#define P_L_STV1_VS_ADDR (volatile unsigned int *)((0x1429 << 2) + 0xff900000) ++#define L_STV1_VE_ADDR (0x142a) ++#define P_L_STV1_VE_ADDR (volatile unsigned int *)((0x142a << 2) + 0xff900000) ++#define L_STV2_HS_ADDR (0x142b) ++#define P_L_STV2_HS_ADDR (volatile unsigned int *)((0x142b << 2) + 0xff900000) ++#define L_STV2_HE_ADDR (0x142c) ++#define P_L_STV2_HE_ADDR (volatile unsigned int *)((0x142c << 2) + 0xff900000) ++#define L_STV2_VS_ADDR (0x142d) ++#define P_L_STV2_VS_ADDR (volatile unsigned int *)((0x142d << 2) + 0xff900000) ++#define L_STV2_VE_ADDR (0x142e) ++#define P_L_STV2_VE_ADDR (volatile unsigned int *)((0x142e << 2) + 0xff900000) ++#define L_OEV1_HS_ADDR (0x142f) ++#define P_L_OEV1_HS_ADDR (volatile unsigned int *)((0x142f << 2) + 0xff900000) ++#define L_OEV1_HE_ADDR (0x1430) ++#define P_L_OEV1_HE_ADDR (volatile unsigned int *)((0x1430 << 2) + 0xff900000) ++#define L_OEV1_VS_ADDR (0x1431) ++#define P_L_OEV1_VS_ADDR (volatile unsigned int *)((0x1431 << 2) + 0xff900000) ++#define L_OEV1_VE_ADDR (0x1432) ++#define P_L_OEV1_VE_ADDR (volatile unsigned int *)((0x1432 << 2) + 0xff900000) ++#define L_OEV2_HS_ADDR (0x1433) ++#define P_L_OEV2_HS_ADDR (volatile unsigned int *)((0x1433 << 2) + 0xff900000) ++#define L_OEV2_HE_ADDR (0x1434) ++#define P_L_OEV2_HE_ADDR (volatile unsigned int *)((0x1434 << 2) + 0xff900000) ++#define L_OEV2_VS_ADDR (0x1435) ++#define P_L_OEV2_VS_ADDR (volatile unsigned int *)((0x1435 << 2) + 0xff900000) ++#define L_OEV2_VE_ADDR (0x1436) ++#define P_L_OEV2_VE_ADDR (volatile unsigned int *)((0x1436 << 2) + 0xff900000) ++#define L_OEV3_HS_ADDR (0x1437) ++#define P_L_OEV3_HS_ADDR (volatile unsigned int *)((0x1437 << 2) + 0xff900000) ++#define L_OEV3_HE_ADDR (0x1438) ++#define P_L_OEV3_HE_ADDR (volatile unsigned int *)((0x1438 << 2) + 0xff900000) ++#define L_OEV3_VS_ADDR (0x1439) ++#define P_L_OEV3_VS_ADDR (volatile unsigned int *)((0x1439 << 2) + 0xff900000) ++#define L_OEV3_VE_ADDR (0x143a) ++#define P_L_OEV3_VE_ADDR (volatile unsigned int *)((0x143a << 2) + 0xff900000) ++#define L_LCD_PWR_ADDR (0x143b) ++#define P_L_LCD_PWR_ADDR (volatile unsigned int *)((0x143b << 2) + 0xff900000) ++#define L_LCD_PWM0_LO_ADDR (0x143c) ++#define P_L_LCD_PWM0_LO_ADDR (volatile unsigned int *)((0x143c << 2) + 0xff900000) ++#define L_LCD_PWM0_HI_ADDR (0x143d) ++#define P_L_LCD_PWM0_HI_ADDR (volatile unsigned int *)((0x143d << 2) + 0xff900000) ++#define L_LCD_PWM1_LO_ADDR (0x143e) ++#define P_L_LCD_PWM1_LO_ADDR (volatile unsigned int *)((0x143e << 2) + 0xff900000) ++#define L_LCD_PWM1_HI_ADDR (0x143f) ++#define P_L_LCD_PWM1_HI_ADDR (volatile unsigned int *)((0x143f << 2) + 0xff900000) ++#define L_INV_CNT_ADDR (0x1440) ++#define P_L_INV_CNT_ADDR (volatile unsigned int *)((0x1440 << 2) + 0xff900000) ++#define L_TCON_MISC_SEL_ADDR (0x1441) ++#define P_L_TCON_MISC_SEL_ADDR (volatile unsigned int *)((0x1441 << 2) + 0xff900000) ++#define L_DUAL_PORT_CNTL_ADDR (0x1442) ++#define P_L_DUAL_PORT_CNTL_ADDR (volatile unsigned int *)((0x1442 << 2) + 0xff900000) ++#define MLVDS_CLK_CTL1_HI (0x1443) ++#define P_MLVDS_CLK_CTL1_HI (volatile unsigned int *)((0x1443 << 2) + 0xff900000) ++#define MLVDS_CLK_CTL1_LO (0x1444) ++#define P_MLVDS_CLK_CTL1_LO (volatile unsigned int *)((0x1444 << 2) + 0xff900000) ++// [31:30] enable mlvds clocks ++// [24] mlvds_clk_half_delay 24 // Bit 0 ++// [23:0] mlvds_clk_pattern 0 // Bit 23:0 ++#define L_TCON_DOUBLE_CTL (0x1449) ++#define P_L_TCON_DOUBLE_CTL (volatile unsigned int *)((0x1449 << 2) + 0xff900000) ++#define L_TCON_PATTERN_HI (0x144a) ++#define P_L_TCON_PATTERN_HI (volatile unsigned int *)((0x144a << 2) + 0xff900000) ++#define L_TCON_PATTERN_LO (0x144b) ++#define P_L_TCON_PATTERN_LO (volatile unsigned int *)((0x144b << 2) + 0xff900000) ++#define LDIM_BL_ADDR_PORT (0x144e) ++#define P_LDIM_BL_ADDR_PORT (volatile unsigned int *)((0x144e << 2) + 0xff900000) ++#define LDIM_BL_DATA_PORT (0x144f) ++#define P_LDIM_BL_DATA_PORT (volatile unsigned int *)((0x144f << 2) + 0xff900000) ++#define L_DE_HS_ADDR (0x1451) ++#define P_L_DE_HS_ADDR (volatile unsigned int *)((0x1451 << 2) + 0xff900000) ++#define L_DE_HE_ADDR (0x1452) ++#define P_L_DE_HE_ADDR (volatile unsigned int *)((0x1452 << 2) + 0xff900000) ++#define L_DE_VS_ADDR (0x1453) ++#define P_L_DE_VS_ADDR (volatile unsigned int *)((0x1453 << 2) + 0xff900000) ++#define L_DE_VE_ADDR (0x1454) ++#define P_L_DE_VE_ADDR (volatile unsigned int *)((0x1454 << 2) + 0xff900000) ++#define L_HSYNC_HS_ADDR (0x1455) ++#define P_L_HSYNC_HS_ADDR (volatile unsigned int *)((0x1455 << 2) + 0xff900000) ++#define L_HSYNC_HE_ADDR (0x1456) ++#define P_L_HSYNC_HE_ADDR (volatile unsigned int *)((0x1456 << 2) + 0xff900000) ++#define L_HSYNC_VS_ADDR (0x1457) ++#define P_L_HSYNC_VS_ADDR (volatile unsigned int *)((0x1457 << 2) + 0xff900000) ++#define L_HSYNC_VE_ADDR (0x1458) ++#define P_L_HSYNC_VE_ADDR (volatile unsigned int *)((0x1458 << 2) + 0xff900000) ++#define L_VSYNC_HS_ADDR (0x1459) ++#define P_L_VSYNC_HS_ADDR (volatile unsigned int *)((0x1459 << 2) + 0xff900000) ++#define L_VSYNC_HE_ADDR (0x145a) ++#define P_L_VSYNC_HE_ADDR (volatile unsigned int *)((0x145a << 2) + 0xff900000) ++#define L_VSYNC_VS_ADDR (0x145b) ++#define P_L_VSYNC_VS_ADDR (volatile unsigned int *)((0x145b << 2) + 0xff900000) ++#define L_VSYNC_VE_ADDR (0x145c) ++#define P_L_VSYNC_VE_ADDR (volatile unsigned int *)((0x145c << 2) + 0xff900000) ++// bit 8 -- vfifo_mcu_enable ++// bit 7 -- halt_vs_de ++// bit 6 -- R8G8B8_format ++// bit 5 -- R6G6B6_format (round to 6 bits) ++// bit 4 -- R5G6B5_format ++// bit 3 -- dac_dith_sel ++// bit 2 -- lcd_mcu_enable_de -- ReadOnly ++// bit 1 -- lcd_mcu_enable_vsync -- ReadOnly ++// bit 0 -- lcd_mcu_enable ++#define L_LCD_MCU_CTL (0x145d) ++#define P_L_LCD_MCU_CTL (volatile unsigned int *)((0x145d << 2) + 0xff900000) ++//************************************************************************** ++//* Dual port mLVDS registers ++//************************************************************************** ++// bit 3 - enable_u_dual_mlvds_dp_clk ++// bit 2 - enable_u_map_mlvds_r_clk ++// bit 1 - enable_u_map_mlvds_l_clk ++// bit 0 - dual_mlvds_en ++//`define DUAL_MLVDS_CTL 8'h60 ++// bit[12:0] - dual_mlvds_line_start ++//`define DUAL_MLVDS_LINE_START 8'h61 ++// bit[12:0] - dual_mlvds_line_end ++//`define DUAL_MLVDS_LINE_END 8'h62 ++// bit[12:0] - dual_mlvds_w_pixel_start_l ++//`define DUAL_MLVDS_PIXEL_W_START_L 8'h63 ++// bit[12:0] - dual_mlvds_w_pixel_end_l ++//`define DUAL_MLVDS_PIXEL_W_END_L 8'h64 ++// bit[12:0] - dual_mlvds_w_pixel_start_r ++//`define DUAL_MLVDS_PIXEL_W_START_R 8'h65 ++// bit[12:0] - dual_mlvds_w_pixel_end_r ++//`define DUAL_MLVDS_PIXEL_W_END_R 8'h66 ++// bit[12:0] - dual_mlvds_r_pixel_start_l ++//`define DUAL_MLVDS_PIXEL_R_START_L 8'h67 ++// bit[12:0] - dual_mlvds_r_pixel_cnt_l ++//`define DUAL_MLVDS_PIXEL_R_CNT_L 8'h68 ++// bit[12:0] - dual_mlvds_r_pixel_start_r ++//`define DUAL_MLVDS_PIXEL_R_START_R 8'h69 ++// bit[12:0] - dual_mlvds_r_pixel_cnt_r ++//`define DUAL_MLVDS_PIXEL_R_CNT_R 8'h6a ++// bit[15] - v_inversion_en ++// bit[12:0] - v_inversion_pixel ++//`define V_INVERSION_PIXEL 8'h70 ++// bit[15] - v_inversion_sync_en ++// bit[12:0] - v_inversion_line ++//`define V_INVERSION_LINE 8'h71 ++// bit[15:12] - v_loop_r ++// bit[11:10] - v_pattern_1_r ++// bit[9:8] - v_pattern_0_r ++// bit[7:4] - v_loop_l ++// bit[3:2] - v_pattern_1_l ++// bit[1:0] - v_pattern_0_l ++//`define V_INVERSION_CONTROL 8'h72 ++//`define MLVDS2_CONTROL 8'h74 ++ #define mLVDS2_RESERVED 15 // 15 ++ #define mLVDS2_double_pattern 14 // 14 ++ #define mLVDS2_ins_reset 8 // 13:8 // each channel has one bit ++ #define mLVDS2_dual_gate 7 ++ #define mLVDS2_bit_num 6 // 0-6Bits, 1-8Bits ++ #define mLVDS2_pair_num 5 // 0-3Pairs, 1-6Pairs ++ #define mLVDS2_msb_first 4 ++ #define mLVDS2_PORT_SWAP 3 ++ #define mLVDS2_MLSB_SWAP 2 ++ #define mLVDS2_PN_SWAP 1 ++ #define mLVDS2_en 0 ++//`define MLVDS2_CONFIG_HI 8'h75 ++//`define MLVDS2_CONFIG_LO 8'h76 ++ #define mLVDS2_reset_offset 29 // Bit 31:29 ++ #define mLVDS2_reset_length 23 // Bit 28:23 ++ #define mLVDS2_config_reserved 20 // Bit 22:20 ++ #define mLVDS2_reset_start_bit12 19 // Bit 19 ++ #define mLVDS2_data_write_toggle 18 ++ #define mLVDS2_data_write_ini 17 ++ #define mLVDS2_data_latch_1_toggle 16 ++ #define mLVDS2_data_latch_1_ini 15 ++ #define mLVDS2_data_latch_0_toggle 14 ++ #define mLVDS2_data_latch_0_ini 13 ++ #define mLVDS2_reset_1_select 12 // 0 - same as reset_0, 1 - 1 clock delay of reset_0 ++ #define mLVDS2_reset_start 0 // Bit 11:0 ++//`define MLVDS2_DUAL_GATE_WR_START 8'h77 ++// `define mlvds2_dual_gate_wr_start 0 // Bit 12:0 ++//`define MLVDS2_DUAL_GATE_WR_END 8'h78 ++// `define mlvds2_dual_gate_wr_end 0 // Bit 12:0 ++// ++//`define MLVDS2_DUAL_GATE_RD_START 8'h79 ++// `define mlvds2_dual_gate_rd_start 0 // Bit 12:0 ++//`define MLVDS2_DUAL_GATE_RD_END 8'h7a ++// `define mlvds2_dual_gate_rd_end 0 // Bit 12:0 ++//`define MLVDS2_SECOND_RESET_CTL 8'h7b ++// `define mLVDS2_2nd_reset_start 0 // Bit 12:0 ++// ++//`define MLVDS2_DUAL_GATE_CTL_HI 8'h7c ++//`define MLVDS2_DUAL_GATE_CTL_LO 8'h7d ++// `define mlvds2_tcon_field_en 24 // Bit 7:0 ++// `define mlvds2_dual_gate_reserved 21 // Bit 2:0 ++// `define mlvds2_scan_mode_start_line_bit12 20 // Bit 0 ++// `define mlvds2_scan_mode_odd 16 // Bit 3:0 ++// `define mlvds2_scan_mode_even 12 // Bit 3:0 ++// `define mlvds2_scan_mode_start_line 0 // Bit 11:0 ++// ++//`define MLVDS2_RESET_CONFIG_HI 8'h7e ++//`define MLVDS2_RESET_CONFIG_LO 8'h7f ++// `define mLVDS2_reset_range_enable 31 // Bit 0 ++// `define mLVDS2_reset_range_inv 30 // Bit 0 ++// `define mLVDS2_reset_config_res1 29 // Bit 0 ++// `define mLVDS2_reset_range_line_0 16 // Bit 11:0 ++// `define mLVDS2_reset_config_res3 13 // Bit 2:0 ++// `define mLVDS2_reset_range_line_1 0 // Bit 11:0 ++// ++//************************************************************************** ++//* Vbyone registers (Note: no MinLVDS in G9tv, share the register) ++//************************************************************************** ++#define VBO_CTRL_L (0x1460) ++#define P_VBO_CTRL_L (volatile unsigned int *)((0x1460 << 2) + 0xff900000) ++#define VBO_CTRL_H (0x1461) ++#define P_VBO_CTRL_H (volatile unsigned int *)((0x1461 << 2) + 0xff900000) ++#define VBO_SOFT_RST (0x1462) ++#define P_VBO_SOFT_RST (volatile unsigned int *)((0x1462 << 2) + 0xff900000) ++#define VBO_LANES (0x1463) ++#define P_VBO_LANES (volatile unsigned int *)((0x1463 << 2) + 0xff900000) ++#define VBO_VIN_CTRL (0x1464) ++#define P_VBO_VIN_CTRL (volatile unsigned int *)((0x1464 << 2) + 0xff900000) ++#define VBO_ACT_VSIZE (0x1465) ++#define P_VBO_ACT_VSIZE (volatile unsigned int *)((0x1465 << 2) + 0xff900000) ++#define VBO_REGION_00 (0x1466) ++#define P_VBO_REGION_00 (volatile unsigned int *)((0x1466 << 2) + 0xff900000) ++#define VBO_REGION_01 (0x1467) ++#define P_VBO_REGION_01 (volatile unsigned int *)((0x1467 << 2) + 0xff900000) ++#define VBO_REGION_02 (0x1468) ++#define P_VBO_REGION_02 (volatile unsigned int *)((0x1468 << 2) + 0xff900000) ++#define VBO_REGION_03 (0x1469) ++#define P_VBO_REGION_03 (volatile unsigned int *)((0x1469 << 2) + 0xff900000) ++#define VBO_VBK_CTRL_0 (0x146a) ++#define P_VBO_VBK_CTRL_0 (volatile unsigned int *)((0x146a << 2) + 0xff900000) ++#define VBO_VBK_CTRL_1 (0x146b) ++#define P_VBO_VBK_CTRL_1 (volatile unsigned int *)((0x146b << 2) + 0xff900000) ++#define VBO_HBK_CTRL (0x146c) ++#define P_VBO_HBK_CTRL (volatile unsigned int *)((0x146c << 2) + 0xff900000) ++#define VBO_PXL_CTRL (0x146d) ++#define P_VBO_PXL_CTRL (volatile unsigned int *)((0x146d << 2) + 0xff900000) ++#define VBO_LANE_SKEW_L (0x146e) ++#define P_VBO_LANE_SKEW_L (volatile unsigned int *)((0x146e << 2) + 0xff900000) ++#define VBO_LANE_SKEW_H (0x146f) ++#define P_VBO_LANE_SKEW_H (volatile unsigned int *)((0x146f << 2) + 0xff900000) ++#define VBO_GCLK_LANE_L (0x1470) ++#define P_VBO_GCLK_LANE_L (volatile unsigned int *)((0x1470 << 2) + 0xff900000) ++#define VBO_GCLK_LANE_H (0x1471) ++#define P_VBO_GCLK_LANE_H (volatile unsigned int *)((0x1471 << 2) + 0xff900000) ++#define VBO_GCLK_MAIN (0x1472) ++#define P_VBO_GCLK_MAIN (volatile unsigned int *)((0x1472 << 2) + 0xff900000) ++#define VBO_STATUS_L (0x1473) ++#define P_VBO_STATUS_L (volatile unsigned int *)((0x1473 << 2) + 0xff900000) ++#define VBO_STATUS_H (0x1474) ++#define P_VBO_STATUS_H (volatile unsigned int *)((0x1474 << 2) + 0xff900000) ++#define VBO_LANE_OUTPUT (0x1475) ++#define P_VBO_LANE_OUTPUT (volatile unsigned int *)((0x1475 << 2) + 0xff900000) ++#define LCD_PORT_SWAP (0x1476) ++#define P_LCD_PORT_SWAP (volatile unsigned int *)((0x1476 << 2) + 0xff900000) ++#define VBO_TMCHK_THRD_L (0x1478) ++#define P_VBO_TMCHK_THRD_L (volatile unsigned int *)((0x1478 << 2) + 0xff900000) ++#define VBO_TMCHK_THRD_H (0x1479) ++#define P_VBO_TMCHK_THRD_H (volatile unsigned int *)((0x1479 << 2) + 0xff900000) ++#define VBO_FSM_HOLDER_L (0x147a) ++#define P_VBO_FSM_HOLDER_L (volatile unsigned int *)((0x147a << 2) + 0xff900000) ++#define VBO_FSM_HOLDER_H (0x147b) ++#define P_VBO_FSM_HOLDER_H (volatile unsigned int *)((0x147b << 2) + 0xff900000) ++#define VBO_INTR_STATE_CTRL (0x147c) ++#define P_VBO_INTR_STATE_CTRL (volatile unsigned int *)((0x147c << 2) + 0xff900000) ++#define VBO_INTR_UNMASK (0x147d) ++#define P_VBO_INTR_UNMASK (volatile unsigned int *)((0x147d << 2) + 0xff900000) ++#define VBO_TMCHK_HSYNC_STATE_L (0x147e) ++#define P_VBO_TMCHK_HSYNC_STATE_L (volatile unsigned int *)((0x147e << 2) + 0xff900000) ++#define VBO_TMCHK_HSYNC_STATE_H (0x147f) ++#define P_VBO_TMCHK_HSYNC_STATE_H (volatile unsigned int *)((0x147f << 2) + 0xff900000) ++#define VBO_TMCHK_VSYNC_STATE_L (0x14f4) ++#define P_VBO_TMCHK_VSYNC_STATE_L (volatile unsigned int *)((0x14f4 << 2) + 0xff900000) ++#define VBO_TMCHK_VSYNC_STATE_H (0x14f5) ++#define P_VBO_TMCHK_VSYNC_STATE_H (volatile unsigned int *)((0x14f5 << 2) + 0xff900000) ++#define VBO_TMCHK_VDE_STATE_L (0x14f6) ++#define P_VBO_TMCHK_VDE_STATE_L (volatile unsigned int *)((0x14f6 << 2) + 0xff900000) ++#define VBO_TMCHK_VDE_STATE_H (0x14f7) ++#define P_VBO_TMCHK_VDE_STATE_H (volatile unsigned int *)((0x14f7 << 2) + 0xff900000) ++#define VBO_INTR_STATE (0x14f8) ++#define P_VBO_INTR_STATE (volatile unsigned int *)((0x14f8 << 2) + 0xff900000) ++#define VBO_INFILTER_CTRL (0x14f9) ++#define P_VBO_INFILTER_CTRL (volatile unsigned int *)((0x14f9 << 2) + 0xff900000) ++#define VBO_INSGN_CTRL (0x14fa) ++#define P_VBO_INSGN_CTRL (volatile unsigned int *)((0x14fa << 2) + 0xff900000) ++//************************************************************************** ++//* NOTE:: When Programming the Gamma, please turn off the IRQ service * ++//************************************************************************** ++#define GAMMA_CNTL_PORT (0x1480) ++#define P_GAMMA_CNTL_PORT (volatile unsigned int *)((0x1480 << 2) + 0xff900000) ++ #define GAMMA_VCOM_POL 7 //RW ++ #define GAMMA_RVS_OUT 6 //RW ++ #define ADR_RDY 5 //Read Only ++ #define WR_RDY 4 //Read Only ++ #define RD_RDY 3 //Read Only ++ #define GAMMA_TR 2 //RW ++ #define GAMMA_SET 1 //RW ++ #define GAMMA_EN 0 //RW ++#define GAMMA_DATA_PORT (0x1481) ++#define P_GAMMA_DATA_PORT (volatile unsigned int *)((0x1481 << 2) + 0xff900000) ++#define GAMMA_ADDR_PORT (0x1482) ++#define P_GAMMA_ADDR_PORT (volatile unsigned int *)((0x1482 << 2) + 0xff900000) ++ #define H_RD 12 ++ #define H_AUTO_INC 11 ++ #define H_SEL_R 10 ++ #define H_SEL_G 9 ++ #define H_SEL_B 8 ++ #define HADR_MSB 7 //7:0 ++ #define HADR 0 //7:0 ++#define GAMMA_VCOM_HSWITCH_ADDR (0x1483) ++#define P_GAMMA_VCOM_HSWITCH_ADDR (volatile unsigned int *)((0x1483 << 2) + 0xff900000) ++#define RGB_BASE_ADDR (0x1485) ++#define P_RGB_BASE_ADDR (volatile unsigned int *)((0x1485 << 2) + 0xff900000) ++#define RGB_COEFF_ADDR (0x1486) ++#define P_RGB_COEFF_ADDR (volatile unsigned int *)((0x1486 << 2) + 0xff900000) ++#define POL_CNTL_ADDR (0x1487) ++#define P_POL_CNTL_ADDR (volatile unsigned int *)((0x1487 << 2) + 0xff900000) ++ #define DCLK_SEL 14 //FOR DCLK OUTPUT ++ #define TCON_VSYNC_SEL_DVI 11 //FOR RGB format DVI output ++ #define TCON_HSYNC_SEL_DVI 10 //FOR RGB format DVI output ++ #define TCON_DE_SEL_DVI 9 //FOR RGB format DVI output ++ #define CPH3_POL 8 ++ #define CPH2_POL 7 ++ #define CPH1_POL 6 ++ #define TCON_DE_SEL 5 ++ #define TCON_VS_SEL 4 ++ #define TCON_HS_SEL 3 ++ #define DE_POL 2 ++ #define VS_POL 1 ++ #define HS_POL 0 ++#define DITH_CNTL_ADDR (0x1488) ++#define P_DITH_CNTL_ADDR (volatile unsigned int *)((0x1488 << 2) + 0xff900000) ++ #define DITH10_EN 10 ++ #define DITH8_EN 9 ++ #define DITH_MD 8 ++ #define DITH10_CNTL_MSB 7 //7:4 ++ #define DITH10_CNTL 4 //7:4 ++ #define DITH8_CNTL_MSB 3 //3:0 ++ #define DITH8_CNTL 0 //3:0 ++//Bit 1 highlight_en ++//Bit 0 probe_en ++#define GAMMA_PROBE_CTRL (0x1489) ++#define P_GAMMA_PROBE_CTRL (volatile unsigned int *)((0x1489 << 2) + 0xff900000) ++//read only ++//Bit [15:0] probe_color[15:0] ++#define GAMMA_PROBE_COLOR_L (0x148a) ++#define P_GAMMA_PROBE_COLOR_L (volatile unsigned int *)((0x148a << 2) + 0xff900000) ++//Read only ++//Bit 15: if true valid probed color ++//Bit [13:0] probe_color[29:16] ++#define GAMMA_PROBE_COLOR_H (0x148b) ++#define P_GAMMA_PROBE_COLOR_H (volatile unsigned int *)((0x148b << 2) + 0xff900000) ++//bit 15:0, 5:6:5 color ++#define GAMMA_PROBE_HL_COLOR (0x148c) ++#define P_GAMMA_PROBE_HL_COLOR (volatile unsigned int *)((0x148c << 2) + 0xff900000) ++//12:0 pos_x ++#define GAMMA_PROBE_POS_X (0x148d) ++#define P_GAMMA_PROBE_POS_X (volatile unsigned int *)((0x148d << 2) + 0xff900000) ++//12:0 pos_y ++#define GAMMA_PROBE_POS_Y (0x148e) ++#define P_GAMMA_PROBE_POS_Y (volatile unsigned int *)((0x148e << 2) + 0xff900000) ++#define STH1_HS_ADDR (0x1490) ++#define P_STH1_HS_ADDR (volatile unsigned int *)((0x1490 << 2) + 0xff900000) ++#define STH1_HE_ADDR (0x1491) ++#define P_STH1_HE_ADDR (volatile unsigned int *)((0x1491 << 2) + 0xff900000) ++#define STH1_VS_ADDR (0x1492) ++#define P_STH1_VS_ADDR (volatile unsigned int *)((0x1492 << 2) + 0xff900000) ++#define STH1_VE_ADDR (0x1493) ++#define P_STH1_VE_ADDR (volatile unsigned int *)((0x1493 << 2) + 0xff900000) ++#define STH2_HS_ADDR (0x1494) ++#define P_STH2_HS_ADDR (volatile unsigned int *)((0x1494 << 2) + 0xff900000) ++#define STH2_HE_ADDR (0x1495) ++#define P_STH2_HE_ADDR (volatile unsigned int *)((0x1495 << 2) + 0xff900000) ++#define STH2_VS_ADDR (0x1496) ++#define P_STH2_VS_ADDR (volatile unsigned int *)((0x1496 << 2) + 0xff900000) ++#define STH2_VE_ADDR (0x1497) ++#define P_STH2_VE_ADDR (volatile unsigned int *)((0x1497 << 2) + 0xff900000) ++#define OEH_HS_ADDR (0x1498) ++#define P_OEH_HS_ADDR (volatile unsigned int *)((0x1498 << 2) + 0xff900000) ++#define OEH_HE_ADDR (0x1499) ++#define P_OEH_HE_ADDR (volatile unsigned int *)((0x1499 << 2) + 0xff900000) ++#define OEH_VS_ADDR (0x149a) ++#define P_OEH_VS_ADDR (volatile unsigned int *)((0x149a << 2) + 0xff900000) ++#define OEH_VE_ADDR (0x149b) ++#define P_OEH_VE_ADDR (volatile unsigned int *)((0x149b << 2) + 0xff900000) ++#define VCOM_HSWITCH_ADDR (0x149c) ++#define P_VCOM_HSWITCH_ADDR (volatile unsigned int *)((0x149c << 2) + 0xff900000) ++#define VCOM_VS_ADDR (0x149d) ++#define P_VCOM_VS_ADDR (volatile unsigned int *)((0x149d << 2) + 0xff900000) ++#define VCOM_VE_ADDR (0x149e) ++#define P_VCOM_VE_ADDR (volatile unsigned int *)((0x149e << 2) + 0xff900000) ++#define CPV1_HS_ADDR (0x149f) ++#define P_CPV1_HS_ADDR (volatile unsigned int *)((0x149f << 2) + 0xff900000) ++#define CPV1_HE_ADDR (0x14a0) ++#define P_CPV1_HE_ADDR (volatile unsigned int *)((0x14a0 << 2) + 0xff900000) ++#define CPV1_VS_ADDR (0x14a1) ++#define P_CPV1_VS_ADDR (volatile unsigned int *)((0x14a1 << 2) + 0xff900000) ++#define CPV1_VE_ADDR (0x14a2) ++#define P_CPV1_VE_ADDR (volatile unsigned int *)((0x14a2 << 2) + 0xff900000) ++#define CPV2_HS_ADDR (0x14a3) ++#define P_CPV2_HS_ADDR (volatile unsigned int *)((0x14a3 << 2) + 0xff900000) ++#define CPV2_HE_ADDR (0x14a4) ++#define P_CPV2_HE_ADDR (volatile unsigned int *)((0x14a4 << 2) + 0xff900000) ++#define CPV2_VS_ADDR (0x14a5) ++#define P_CPV2_VS_ADDR (volatile unsigned int *)((0x14a5 << 2) + 0xff900000) ++#define CPV2_VE_ADDR (0x14a6) ++#define P_CPV2_VE_ADDR (volatile unsigned int *)((0x14a6 << 2) + 0xff900000) ++#define STV1_HS_ADDR (0x14a7) ++#define P_STV1_HS_ADDR (volatile unsigned int *)((0x14a7 << 2) + 0xff900000) ++#define STV1_HE_ADDR (0x14a8) ++#define P_STV1_HE_ADDR (volatile unsigned int *)((0x14a8 << 2) + 0xff900000) ++#define STV1_VS_ADDR (0x14a9) ++#define P_STV1_VS_ADDR (volatile unsigned int *)((0x14a9 << 2) + 0xff900000) ++#define STV1_VE_ADDR (0x14aa) ++#define P_STV1_VE_ADDR (volatile unsigned int *)((0x14aa << 2) + 0xff900000) ++#define STV2_HS_ADDR (0x14ab) ++#define P_STV2_HS_ADDR (volatile unsigned int *)((0x14ab << 2) + 0xff900000) ++#define STV2_HE_ADDR (0x14ac) ++#define P_STV2_HE_ADDR (volatile unsigned int *)((0x14ac << 2) + 0xff900000) ++#define STV2_VS_ADDR (0x14ad) ++#define P_STV2_VS_ADDR (volatile unsigned int *)((0x14ad << 2) + 0xff900000) ++#define STV2_VE_ADDR (0x14ae) ++#define P_STV2_VE_ADDR (volatile unsigned int *)((0x14ae << 2) + 0xff900000) ++#define OEV1_HS_ADDR (0x14af) ++#define P_OEV1_HS_ADDR (volatile unsigned int *)((0x14af << 2) + 0xff900000) ++#define OEV1_HE_ADDR (0x14b0) ++#define P_OEV1_HE_ADDR (volatile unsigned int *)((0x14b0 << 2) + 0xff900000) ++#define OEV1_VS_ADDR (0x14b1) ++#define P_OEV1_VS_ADDR (volatile unsigned int *)((0x14b1 << 2) + 0xff900000) ++#define OEV1_VE_ADDR (0x14b2) ++#define P_OEV1_VE_ADDR (volatile unsigned int *)((0x14b2 << 2) + 0xff900000) ++#define OEV2_HS_ADDR (0x14b3) ++#define P_OEV2_HS_ADDR (volatile unsigned int *)((0x14b3 << 2) + 0xff900000) ++#define OEV2_HE_ADDR (0x14b4) ++#define P_OEV2_HE_ADDR (volatile unsigned int *)((0x14b4 << 2) + 0xff900000) ++#define OEV2_VS_ADDR (0x14b5) ++#define P_OEV2_VS_ADDR (volatile unsigned int *)((0x14b5 << 2) + 0xff900000) ++#define OEV2_VE_ADDR (0x14b6) ++#define P_OEV2_VE_ADDR (volatile unsigned int *)((0x14b6 << 2) + 0xff900000) ++#define OEV3_HS_ADDR (0x14b7) ++#define P_OEV3_HS_ADDR (volatile unsigned int *)((0x14b7 << 2) + 0xff900000) ++#define OEV3_HE_ADDR (0x14b8) ++#define P_OEV3_HE_ADDR (volatile unsigned int *)((0x14b8 << 2) + 0xff900000) ++#define OEV3_VS_ADDR (0x14b9) ++#define P_OEV3_VS_ADDR (volatile unsigned int *)((0x14b9 << 2) + 0xff900000) ++#define OEV3_VE_ADDR (0x14ba) ++#define P_OEV3_VE_ADDR (volatile unsigned int *)((0x14ba << 2) + 0xff900000) ++#define LCD_PWR_ADDR (0x14bb) ++#define P_LCD_PWR_ADDR (volatile unsigned int *)((0x14bb << 2) + 0xff900000) ++ #define LCD_VDD 5 ++ #define LCD_VBL 4 ++ #define LCD_GPI_MSB 3 ++ #define LCD_GPIO 0 ++#define LCD_PWM0_LO_ADDR (0x14bc) ++#define P_LCD_PWM0_LO_ADDR (volatile unsigned int *)((0x14bc << 2) + 0xff900000) ++#define LCD_PWM0_HI_ADDR (0x14bd) ++#define P_LCD_PWM0_HI_ADDR (volatile unsigned int *)((0x14bd << 2) + 0xff900000) ++#define LCD_PWM1_LO_ADDR (0x14be) ++#define P_LCD_PWM1_LO_ADDR (volatile unsigned int *)((0x14be << 2) + 0xff900000) ++#define LCD_PWM1_HI_ADDR (0x14bf) ++#define P_LCD_PWM1_HI_ADDR (volatile unsigned int *)((0x14bf << 2) + 0xff900000) ++#define INV_CNT_ADDR (0x14c0) ++#define P_INV_CNT_ADDR (volatile unsigned int *)((0x14c0 << 2) + 0xff900000) ++ #define INV_EN 4 ++ #define INV_CNT_MSB 3 ++ #define INV_CNT 0 ++#define TCON_MISC_SEL_ADDR (0x14c1) ++#define P_TCON_MISC_SEL_ADDR (volatile unsigned int *)((0x14c1 << 2) + 0xff900000) ++ #define STH2_SEL 12 ++ #define STH1_SEL 11 ++ #define OEH_SEL 10 ++ #define VCOM_SEL 9 ++ #define DB_LINE_SW 8 ++ #define CPV2_SEL 7 ++ #define CPV1_SEL 6 ++ #define STV2_SEL 5 ++ #define STV1_SEL 4 ++ #define OEV_UNITE 3 ++ #define OEV3_SEL 2 ++ #define OEV2_SEL 1 ++ #define OEV1_SEL 0 ++#define DUAL_PORT_CNTL_ADDR (0x14c2) ++#define P_DUAL_PORT_CNTL_ADDR (volatile unsigned int *)((0x14c2 << 2) + 0xff900000) ++ #define OUTPUT_YUV 15 ++ #define DUAL_IDF 12 // 14:12 ++ #define DUAL_ISF 9 // 11:9 ++ #define LCD_ANALOG_SEL_CPH3 8 ++ #define LCD_ANALOG_3PHI_CLK_SEL 7 ++ #define LCD_LVDS_SEL54 6 ++ #define LCD_LVDS_SEL27 5 ++ #define LCD_TTL_SEL 4 ++ #define DUAL_LVDC_EN 3 ++ #define PORT_SWP 2 ++ #define RGB_SWP 1 ++ #define BIT_SWP 0 ++#define MLVDS_CONTROL (0x14c3) ++#define P_MLVDS_CONTROL (volatile unsigned int *)((0x14c3 << 2) + 0xff900000) ++ #define mLVDS_RESERVED 15 // 15 ++ #define mLVDS_double_pattern 14 // 14 ++ #define mLVDS_ins_reset 8 // 13:8 // each channel has one bit ++ #define mLVDS_dual_gate 7 ++ #define mLVDS_bit_num 6 // 0-6Bits, 1-8Bits ++ #define mLVDS_pair_num 5 // 0-3Pairs, 1-6Pairs ++ #define mLVDS_msb_first 4 ++ #define mLVDS_PORT_SWAP 3 ++ #define mLVDS_MLSB_SWAP 2 ++ #define mLVDS_PN_SWAP 1 ++ #define mLVDS_en 0 ++#define MLVDS_RESET_PATTERN_HI (0x14c4) ++#define P_MLVDS_RESET_PATTERN_HI (volatile unsigned int *)((0x14c4 << 2) + 0xff900000) ++#define MLVDS_RESET_PATTERN_LO (0x14c5) ++#define P_MLVDS_RESET_PATTERN_LO (volatile unsigned int *)((0x14c5 << 2) + 0xff900000) ++ #define mLVDS_reset_pattern 0 // Bit 47:16 ++#define MLVDS_RESET_PATTERN_EXT (0x14c6) ++#define P_MLVDS_RESET_PATTERN_EXT (volatile unsigned int *)((0x14c6 << 2) + 0xff900000) ++ #define mLVDS_reset_pattern_ext 0 // Bit 15:0 ++#define MLVDS_CONFIG_HI (0x14c7) ++#define P_MLVDS_CONFIG_HI (volatile unsigned int *)((0x14c7 << 2) + 0xff900000) ++#define MLVDS_CONFIG_LO (0x14c8) ++#define P_MLVDS_CONFIG_LO (volatile unsigned int *)((0x14c8 << 2) + 0xff900000) ++ #define mLVDS_reset_offset 29 // Bit 31:29 ++ #define mLVDS_reset_length 23 // Bit 28:23 ++ #define mLVDS_config_reserved 20 // Bit 22:20 ++ #define mLVDS_reset_start_bit12 19 // Bit 19 ++ #define mLVDS_data_write_toggle 18 ++ #define mLVDS_data_write_ini 17 ++ #define mLVDS_data_latch_1_toggle 16 ++ #define mLVDS_data_latch_1_ini 15 ++ #define mLVDS_data_latch_0_toggle 14 ++ #define mLVDS_data_latch_0_ini 13 ++ #define mLVDS_reset_1_select 12 // 0 - same as reset_0, 1 - 1 clock delay of reset_0 ++ #define mLVDS_reset_start 0 // Bit 11:0 ++#define TCON_DOUBLE_CTL (0x14c9) ++#define P_TCON_DOUBLE_CTL (volatile unsigned int *)((0x14c9 << 2) + 0xff900000) ++ #define tcon_double_ini 8 // Bit 7:0 ++ #define tcon_double_inv 0 // Bit 7:0 ++#define TCON_PATTERN_HI (0x14ca) ++#define P_TCON_PATTERN_HI (volatile unsigned int *)((0x14ca << 2) + 0xff900000) ++#define TCON_PATTERN_LO (0x14cb) ++#define P_TCON_PATTERN_LO (volatile unsigned int *)((0x14cb << 2) + 0xff900000) ++ #define tcon_pattern_loop_data 16 // Bit 15:0 ++ #define tcon_pattern_loop_start 12 // Bit 3:0 ++ #define tcon_pattern_loop_end 8 // Bit 3:0 ++ #define tcon_pattern_enable 0 // Bit 7:0 ++#define TCON_CONTROL_HI (0x14cc) ++#define P_TCON_CONTROL_HI (volatile unsigned int *)((0x14cc << 2) + 0xff900000) ++#define TCON_CONTROL_LO (0x14cd) ++#define P_TCON_CONTROL_LO (volatile unsigned int *)((0x14cd << 2) + 0xff900000) ++ #define tcon_pclk_enable 26 // Bit 5:0 (enable pclk on TCON channel 7 to 2) ++ #define tcon_pclk_div 24 // Bit 1:0 (control phy clok divide 2,4,6,8) ++ #define tcon_delay 0 // Bit 23:0 (3 bit for each channel) ++#define LVDS_BLANK_DATA_HI (0x14ce) ++#define P_LVDS_BLANK_DATA_HI (volatile unsigned int *)((0x14ce << 2) + 0xff900000) ++#define LVDS_BLANK_DATA_LO (0x14cf) ++#define P_LVDS_BLANK_DATA_LO (volatile unsigned int *)((0x14cf << 2) + 0xff900000) ++ #define LVDS_blank_data_reserved 30 // 31:30 ++ #define LVDS_blank_data_r 20 // 29:20 ++ #define LVDS_blank_data_g 10 // 19:10 ++ #define LVDS_blank_data_b 0 // 9:0 ++#define LVDS_PACK_CNTL_ADDR (0x14d0) ++#define P_LVDS_PACK_CNTL_ADDR (volatile unsigned int *)((0x14d0 << 2) + 0xff900000) ++ #define LVDS_USE_TCON 7 ++ #define LVDS_DUAL 6 ++ #define PN_SWP 5 ++ #define LSB_FIRST 4 ++ #define LVDS_RESV 3 ++ #define ODD_EVEN_SWP 2 ++ #define LVDS_REPACK 0 ++// New from M3 : ++// Bit 15:12 -- Enable OFFSET Double Generate(TOCN7-TCON4) ++// Bit 11:0 -- de_hs(old tcon) second offset_hs (new tcon) ++#define DE_HS_ADDR (0x14d1) ++#define P_DE_HS_ADDR (volatile unsigned int *)((0x14d1 << 2) + 0xff900000) ++// New from M3 : ++// Bit 15:12 -- Enable OFFSET Double Generate(TOCN3-TCON0) ++#define DE_HE_ADDR (0x14d2) ++#define P_DE_HE_ADDR (volatile unsigned int *)((0x14d2 << 2) + 0xff900000) ++#define DE_VS_ADDR (0x14d3) ++#define P_DE_VS_ADDR (volatile unsigned int *)((0x14d3 << 2) + 0xff900000) ++#define DE_VE_ADDR (0x14d4) ++#define P_DE_VE_ADDR (volatile unsigned int *)((0x14d4 << 2) + 0xff900000) ++#define HSYNC_HS_ADDR (0x14d5) ++#define P_HSYNC_HS_ADDR (volatile unsigned int *)((0x14d5 << 2) + 0xff900000) ++#define HSYNC_HE_ADDR (0x14d6) ++#define P_HSYNC_HE_ADDR (volatile unsigned int *)((0x14d6 << 2) + 0xff900000) ++#define HSYNC_VS_ADDR (0x14d7) ++#define P_HSYNC_VS_ADDR (volatile unsigned int *)((0x14d7 << 2) + 0xff900000) ++#define HSYNC_VE_ADDR (0x14d8) ++#define P_HSYNC_VE_ADDR (volatile unsigned int *)((0x14d8 << 2) + 0xff900000) ++#define VSYNC_HS_ADDR (0x14d9) ++#define P_VSYNC_HS_ADDR (volatile unsigned int *)((0x14d9 << 2) + 0xff900000) ++#define VSYNC_HE_ADDR (0x14da) ++#define P_VSYNC_HE_ADDR (volatile unsigned int *)((0x14da << 2) + 0xff900000) ++#define VSYNC_VS_ADDR (0x14db) ++#define P_VSYNC_VS_ADDR (volatile unsigned int *)((0x14db << 2) + 0xff900000) ++#define VSYNC_VE_ADDR (0x14dc) ++#define P_VSYNC_VE_ADDR (volatile unsigned int *)((0x14dc << 2) + 0xff900000) ++// bit 8 -- vfifo_mcu_enable ++// bit 7 -- halt_vs_de ++// bit 6 -- R8G8B8_format ++// bit 5 -- R6G6B6_format (round to 6 bits) ++// bit 4 -- R5G6B5_format ++// bit 3 -- dac_dith_sel ++// bit 2 -- lcd_mcu_enable_de -- ReadOnly ++// bit 1 -- lcd_mcu_enable_vsync -- ReadOnly ++// bit 0 -- lcd_mcu_enable ++#define LCD_MCU_CTL (0x14dd) ++#define P_LCD_MCU_CTL (volatile unsigned int *)((0x14dd << 2) + 0xff900000) ++// ReadOnly ++// R5G6B5 when R5G6B5_format ++// G8R8 when R8G8B8_format ++// G5R10 Other ++#define LCD_MCU_DATA_0 (0x14de) ++#define P_LCD_MCU_DATA_0 (volatile unsigned int *)((0x14de << 2) + 0xff900000) ++// ReadOnly ++// G8B8 when R8G8B8_format ++// G5B10 Other ++#define LCD_MCU_DATA_1 (0x14df) ++#define P_LCD_MCU_DATA_1 (volatile unsigned int *)((0x14df << 2) + 0xff900000) ++// LVDS ++#define LVDS_GEN_CNTL (0x14e0) ++#define P_LVDS_GEN_CNTL (volatile unsigned int *)((0x14e0 << 2) + 0xff900000) ++#define LVDS_PHY_CNTL0 (0x14e1) ++#define P_LVDS_PHY_CNTL0 (volatile unsigned int *)((0x14e1 << 2) + 0xff900000) ++#define LVDS_PHY_CNTL1 (0x14e2) ++#define P_LVDS_PHY_CNTL1 (volatile unsigned int *)((0x14e2 << 2) + 0xff900000) ++#define LVDS_PHY_CNTL2 (0x14e3) ++#define P_LVDS_PHY_CNTL2 (volatile unsigned int *)((0x14e3 << 2) + 0xff900000) ++#define LVDS_PHY_CNTL3 (0x14e4) ++#define P_LVDS_PHY_CNTL3 (volatile unsigned int *)((0x14e4 << 2) + 0xff900000) ++#define LVDS_PHY_CNTL4 (0x14e5) ++#define P_LVDS_PHY_CNTL4 (volatile unsigned int *)((0x14e5 << 2) + 0xff900000) ++#define LVDS_PHY_CNTL5 (0x14e6) ++#define P_LVDS_PHY_CNTL5 (volatile unsigned int *)((0x14e6 << 2) + 0xff900000) ++#define LVDS_SRG_TEST (0x14e8) ++#define P_LVDS_SRG_TEST (volatile unsigned int *)((0x14e8 << 2) + 0xff900000) ++#define LVDS_BIST_MUX0 (0x14e9) ++#define P_LVDS_BIST_MUX0 (volatile unsigned int *)((0x14e9 << 2) + 0xff900000) ++#define LVDS_BIST_MUX1 (0x14ea) ++#define P_LVDS_BIST_MUX1 (volatile unsigned int *)((0x14ea << 2) + 0xff900000) ++#define LVDS_BIST_FIXED0 (0x14eb) ++#define P_LVDS_BIST_FIXED0 (volatile unsigned int *)((0x14eb << 2) + 0xff900000) ++#define LVDS_BIST_FIXED1 (0x14ec) ++#define P_LVDS_BIST_FIXED1 (volatile unsigned int *)((0x14ec << 2) + 0xff900000) ++#define LVDS_BIST_CNTL0 (0x14ed) ++#define P_LVDS_BIST_CNTL0 (volatile unsigned int *)((0x14ed << 2) + 0xff900000) ++#define LVDS_CLKB_CLKA (0x14ee) ++#define P_LVDS_CLKB_CLKA (volatile unsigned int *)((0x14ee << 2) + 0xff900000) ++#define LVDS_PHY_CLK_CNTL (0x14ef) ++#define P_LVDS_PHY_CLK_CNTL (volatile unsigned int *)((0x14ef << 2) + 0xff900000) ++#define LVDS_SER_EN (0x14f0) ++#define P_LVDS_SER_EN (volatile unsigned int *)((0x14f0 << 2) + 0xff900000) ++#define LVDS_PHY_CNTL6 (0x14f1) ++#define P_LVDS_PHY_CNTL6 (volatile unsigned int *)((0x14f1 << 2) + 0xff900000) ++#define LVDS_PHY_CNTL7 (0x14f2) ++#define P_LVDS_PHY_CNTL7 (volatile unsigned int *)((0x14f2 << 2) + 0xff900000) ++#define LVDS_PHY_CNTL8 (0x14f3) ++#define P_LVDS_PHY_CNTL8 (volatile unsigned int *)((0x14f3 << 2) + 0xff900000) ++//`define MLVDS_CLK_CTL0_HI 8'hf4 ++//`define MLVDS_CLK_CTL0_LO 8'hf5 ++// `define mlvds_clk_pattern_reserved 31 // Bit 31 ++// `define mpclk_dly 28 // Bit 2:0 ++// `define mpclk_div 26 // Bit 1:0 (control phy clok divide 2,4,6,8) ++// `define use_mpclk 25 // Bit 0 ++// `define mlvds_clk_half_delay 24 // Bit 0 ++// `define mlvds_clk_pattern 0 // Bit 23:0 ++//`define MLVDS_DUAL_GATE_WR_START 8'hf6 ++// `define mlvds_dual_gate_wr_start 0 // Bit 12:0 ++//`define MLVDS_DUAL_GATE_WR_END 8'hf7 ++// `define mlvds_dual_gate_wr_end 0 // Bit 12:0 ++// ++//`define MLVDS_DUAL_GATE_RD_START 8'hf8 ++// `define mlvds_dual_gate_rd_start 0 // Bit 12:0 ++//`define MLVDS_DUAL_GATE_RD_END 8'hf9 ++// `define mlvds_dual_gate_rd_end 0 // Bit 12:0 ++//`define MLVDS_SECOND_RESET_CTL 8'hfa ++// `define mLVDS_2nd_reset_start 0 // Bit 12:0 ++// ++#define MLVDS_DUAL_GATE_CTL_HI (0x14fb) ++#define P_MLVDS_DUAL_GATE_CTL_HI (volatile unsigned int *)((0x14fb << 2) + 0xff900000) ++#define MLVDS_DUAL_GATE_CTL_LO (0x14fc) ++#define P_MLVDS_DUAL_GATE_CTL_LO (volatile unsigned int *)((0x14fc << 2) + 0xff900000) ++// `define mlvds_tcon_field_en 24 // Bit 7:0 ++// `define mlvds_dual_gate_reserved 21 // Bit 2:0 ++// `define mlvds_scan_mode_start_line_bit12 20 // Bit 0 ++// `define mlvds_scan_mode_odd 16 // Bit 3:0 ++// `define mlvds_scan_mode_even 12 // Bit 3:0 ++// `define mlvds_scan_mode_start_line 0 // Bit 11:0 ++// ++//`define MLVDS_RESET_CONFIG_HI 8'hfd ++//`define MLVDS_RESET_CONFIG_LO 8'hfe ++// `define mLVDS_reset_range_enable 31 // Bit 0 ++// `define mLVDS_reset_range_inv 30 // Bit 0 ++// `define mLVDS_reset_config_res1 29 // Bit 0 ++// `define mLVDS_reset_range_line_0 16 // Bit 11:0 ++// `define mLVDS_reset_config_res3 13 // Bit 2:0 ++// `define mLVDS_reset_range_line_1 0 // Bit 11:0 ++//=============================================================== ++//LCD DRIVER BASE END ++//=============================================================== ++// ++// Closing file: lcd_regs.h ++// ++//`define MAD_VCBUS_BASE 8'h17 ++// ++// Reading file: mad_regs.h ++// ++//DEINTERLACE module start from 8'h90 end to 8'hff ++// ----------------------------------------------- ++// CBUS_BASE: MAD_VCBUS_BASE = 0x17 ++// ----------------------------------------------- ++#define DI_PRE_CTRL (0x1700) ++#define P_DI_PRE_CTRL (volatile unsigned int *)((0x1700 << 2) + 0xff900000) ++// bit 31, cbus_pre_frame_rst ++// bit 30, cbus_pre_soft_rst ++// bit 29, pre_field_num ++// bit 27:26, mode_444c422 ++// bit 25, di_cont_read_en ++// bit 24:23, mode_422c444 ++// bit 22, mtn_after_nr ++// bit 21:16, pre_hold_fifo_lines ++// bit 15, nr_wr_by ++// bit 14, use_vdin_go_line ++// bit 13, di_prevdin_en ++// bit 12, di_pre_viu_link ++// bit 11, di_pre_repeat ++// bit 10, di_pre_drop_1st ++// bit 9, di_buf2_en ++// bit 8, di_chan2_en ++// bit 7, prenr_hist_en ++// bit 6, chan2_hist_en ++// bit 5, hist_check_en ++// bit 4, check_after_nr ++// bit 3, check222p_en ++// bit 2, check322p_en ++// bit 1, mtn_en ++// bit 0, nr_en ++#define DI_POST_CTRL (0x1701) ++#define P_DI_POST_CTRL (volatile unsigned int *)((0x1701 << 2) + 0xff900000) ++// bit 31, cbus_post_frame_rst ++// bit 30, cbus_post_soft_rst ++// bit 29, post_field_num ++// bit 21:16, post_hold_fifo_lines ++// bit 13, prepost_link ++// bit 12, di_post_viu_link ++// bit 11, di_post_repeat ++// bit 10, di_post_drop_1st ++// bit 9, mif0_to_vpp_en ++// bit 8, di_vpp_out_en ++// bit 7, di_wr_bk_en ++// bit 6, di_mux_en ++// bit 5, di_blend_en ++// bit 4, di_mtnp_read_en ++// bit 3, di_mtn_buf_en ++// bit 2, di_ei_en ++// bit 1, di_buf1_en ++// bit 0, di_buf0_en ++#define DI_POST_SIZE (0x1702) ++#define P_DI_POST_SIZE (volatile unsigned int *)((0x1702 << 2) + 0xff900000) ++//bit 28:16, vsize1post ++//bit 12:0, hsize1post ++#define DI_PRE_SIZE (0x1703) ++#define P_DI_PRE_SIZE (volatile unsigned int *)((0x1703 << 2) + 0xff900000) ++//bit 28:16, vsize1pre ++//bit 12:0, hsize1pre ++#define DI_EI_CTRL0 (0x1704) ++#define P_DI_EI_CTRL0 (volatile unsigned int *)((0x1704 << 2) + 0xff900000) ++//bit 23:16, ei0_filter[2:+] abs_diff_left>filter && ...right>filter && ...top>filter && ...bot>filter -> filter ++//bit 15:8, ei0_threshold[2:+] ++//bit 3, ei0_vertical ++//bit 2, ei0_bpscf2 ++//bit 1, ei0_bpsfar1 ++#define DI_EI_CTRL1 (0x1705) ++#define P_DI_EI_CTRL1 (volatile unsigned int *)((0x1705 << 2) + 0xff900000) ++//bit 31:24, ei0_diff ++//bit 23:16, ei0_angle45 ++//bit 15:8, ei0_peak ++//bit 7:0, ei0_cross ++#define DI_EI_CTRL2 (0x1706) ++#define P_DI_EI_CTRL2 (volatile unsigned int *)((0x1706 << 2) + 0xff900000) ++//bit 31:24, ei0_close2 ++//bit 23:16, ei0_close1 ++//bit 15:8, ei0_far2 ++//bit 7:0, ei0_far1 ++#define DI_NR_CTRL0 (0x1707) ++#define P_DI_NR_CTRL0 (volatile unsigned int *)((0x1707 << 2) + 0xff900000) ++//bit 26, nr_cue_en ++//bit 25, nr2_en ++#define DI_NR_CTRL1 (0x1708) ++#define P_DI_NR_CTRL1 (volatile unsigned int *)((0x1708 << 2) + 0xff900000) ++//bit 31:30, mot_p1txtcore_mode ++//bit 29:24, mot_p1txtcore_clmt ++//bit 21:16, mot_p1txtcore_ylmt ++//bit 15:8, mot_p1txtcore_crate ++//bit 7:0, mot_p1txtcore_yrate ++#define DI_NR_CTRL2 (0x1709) ++#define P_DI_NR_CTRL2 (volatile unsigned int *)((0x1709 << 2) + 0xff900000) ++//bit 29:24, mot_curtxtcore_clmt ++//bit 21:16, mot_curtxtcore_ylmt ++//bit 15:8, mot_curtxtcore_crate ++//bit 7:0, mot_curtxtcore_yrate ++//`define DI_NR_CTRL3 8'h0a ++//no use ++//`define DI_MTN_CTRL 8'h0b ++//no use ++#define DI_CANVAS_URGENT0 (0x170a) ++#define P_DI_CANVAS_URGENT0 (volatile unsigned int *)((0x170a << 2) + 0xff900000) ++#define DI_CANVAS_URGENT1 (0x170b) ++#define P_DI_CANVAS_URGENT1 (volatile unsigned int *)((0x170b << 2) + 0xff900000) ++#define DI_MTN_CTRL1 (0x170c) ++#define P_DI_MTN_CTRL1 (volatile unsigned int *)((0x170c << 2) + 0xff900000) ++//bit 13 , me enable ++//bit 12 , me autoenable ++//bit 11:8, mtn_paramtnthd ++//bit 7:0, mtn_parafltthd ++#define DI_BLEND_CTRL (0x170d) ++#define P_DI_BLEND_CTRL (volatile unsigned int *)((0x170d << 2) + 0xff900000) ++//bit 31, blend_1_en ++//bit 30, blend_mtn_lpf ++//bit 28, post_mb_en ++//bit 27, blend_mtn3p_max ++//bit 26, blend_mtn3p_min ++//bit 25, blend_mtn3p_ave ++//bit 24, blend_mtn3p_maxtb ++//bit 23, blend_mtn_flt_en ++//bit 22, blend_data_flt_en ++//bit 21:20, blend_top_mode ++//bit 19, blend_reg3_enable ++//bit 18, blend_reg2_enable ++//bit 17, blend_reg1_enable ++//bit 16, blend_reg0_enable ++//bit 15:14, blend_reg3_mode ++//bit 13:12, blend_reg2_mode ++//bit 11:10, blend_reg1_mode ++//bit 9:8, blend_reg0_mode ++//bit 7:0, kdeint ++//`define DI_BLEND_CTRL1 8'h0e ++//no use ++#define DI_CANVAS_URGENT2 (0x170e) ++#define P_DI_CANVAS_URGENT2 (volatile unsigned int *)((0x170e << 2) + 0xff900000) ++//`define DI_BLEND_CTRL2 8'h0f ++//no use ++#define DI_ARB_CTRL (0x170f) ++#define P_DI_ARB_CTRL (volatile unsigned int *)((0x170f << 2) + 0xff900000) ++//bit 31:26, di_arb_thd1 ++//bit 25:20, di_arb_thd0 ++//bit 19, di_arb_tid_mode ++//bit 18, di_arb_arb_mode ++//bit 17, di_arb_acq_en ++//bit 16, di_arb_disable_clk ++//bit 15:0, di_arb_req_en ++#define DI_BLEND_REG0_X (0x1710) ++#define P_DI_BLEND_REG0_X (volatile unsigned int *)((0x1710 << 2) + 0xff900000) ++//bit 27:16, blend_reg0_startx ++//bit 11:0, blend_reg0_endx ++#define DI_BLEND_REG0_Y (0x1711) ++#define P_DI_BLEND_REG0_Y (volatile unsigned int *)((0x1711 << 2) + 0xff900000) ++#define DI_BLEND_REG1_X (0x1712) ++#define P_DI_BLEND_REG1_X (volatile unsigned int *)((0x1712 << 2) + 0xff900000) ++#define DI_BLEND_REG1_Y (0x1713) ++#define P_DI_BLEND_REG1_Y (volatile unsigned int *)((0x1713 << 2) + 0xff900000) ++#define DI_BLEND_REG2_X (0x1714) ++#define P_DI_BLEND_REG2_X (volatile unsigned int *)((0x1714 << 2) + 0xff900000) ++#define DI_BLEND_REG2_Y (0x1715) ++#define P_DI_BLEND_REG2_Y (volatile unsigned int *)((0x1715 << 2) + 0xff900000) ++#define DI_BLEND_REG3_X (0x1716) ++#define P_DI_BLEND_REG3_X (volatile unsigned int *)((0x1716 << 2) + 0xff900000) ++#define DI_BLEND_REG3_Y (0x1717) ++#define P_DI_BLEND_REG3_Y (volatile unsigned int *)((0x1717 << 2) + 0xff900000) ++#define DI_CLKG_CTRL (0x1718) ++#define P_DI_CLKG_CTRL (volatile unsigned int *)((0x1718 << 2) + 0xff900000) ++//bit 31:24, pre_gclk_ctrl no clk gate control. if ==1, module clk is not gated (always on). [3] for pulldown,[2] for mtn_1,[1] for mtn_0,[0] for nr ++//bit 23:16, post_gclk_ctrl no clk gate control. [4] for ei_1, [3] for ei_0,[2] for ei_top, [1] for blend_1, [0] for blend_0 ++//bit 1, di_gate_all clk shut down. if ==1 , all di clock shut down ++//bit 0, di_no_clk_gate no clk gate control. if di_gated_all==0 and di_no_clk_gate ==1, all di clock is always working. ++#define DI_EI_CTRL3 (0x1719) ++#define P_DI_EI_CTRL3 (volatile unsigned int *)((0x1719 << 2) + 0xff900000) ++//bit 31, reg_ei_1 ++//bit 30, reg_demon_en ++//bit 26:24, reg_demon_mux ++//bit 23:20, reg_right_win ++//bit 19:16, reg_left_win ++//bit 7:4, reg_ei_sadm_quatize_margin ++//bit 1:0, reg_ei_sad_relative_mode ++#define DI_EI_CTRL4 (0x171a) ++#define P_DI_EI_CTRL4 (volatile unsigned int *)((0x171a << 2) + 0xff900000) ++//bit 29, reg_ei_caldrt_ambliike2_biasvertical ++//bit 28:24, reg_ei_caldrt_addxla2list_drtmax ++//bit 22:20, reg_ei_caldrt_addxla2list_signm0th ++//bit 19, reg_ei_caldrt_addxla2list_mode ++//bit 18:16, reg_ei_signm_sad_cor_rate ++//bit 15:12, reg_ei_signm_sadi_cor_rate ++//bit 11:6, reg_ei_signm_sadi_cor_ofst ++//bit 5:0, reg_ei_signm_sad_ofst ++#define DI_EI_CTRL5 (0x171b) ++#define P_DI_EI_CTRL5 (volatile unsigned int *)((0x171b << 2) + 0xff900000) ++//bit 30:28, reg_ei_caldrt_cnflcctchk_frcverthrd ++//bit 26:24, reg_ei_caldrt_cnflctchk_mg ++//bit 23:22, reg_ei_caldrt_cnflctchk_ws ++//bit 21, reg_ei_caldrt_cnflctchk_en ++//bit 20, reg_ei_caldrt_verfrc_final_en ++//bit 19, reg_ei_caldrt_verfrc_retimflt_en ++//bit 18:16, reg_ei_caldrt_verftc_eithratemth ++//bit 15, reg_ei_caldrt_verfrc_retiming_en ++//bit 14:12, reg_ei_caldrt_verfrc_bothratemth ++//bit 11:9, reg_ei_caldrt_ver_thrd ++//bit 8:4, reg_ei_caldrt_addxla2list_drtmin ++//bit 3:0, reg_ei_caldrt_addxla2list_drtlimit ++#define DI_EI_CTRL6 (0x171c) ++#define P_DI_EI_CTRL6 (volatile unsigned int *)((0x171c << 2) + 0xff900000) ++//bit 31:24, reg_ei_caldrt_abext_sad12thhig ++//bit 23:16, reg_ei_caldrt_abext_sad00thlow ++//bit 15:8, reg_ei_caldrt_abext_sad12thlow ++//bit 6:4, reg_ei_caldrt_abext_ratemth ++//bit 2:0, reg_ei_caldrt_abext_drtthrd ++#define DI_EI_CTRL7 (0x171d) ++#define P_DI_EI_CTRL7 (volatile unsigned int *)((0x171d << 2) + 0xff900000) ++//bit 29, reg_ei_caldrt_xlanopeak_codien ++//bit 28:24, reg_ei_caldrt_xlanopeak_drtmax ++//bit 23, reg_ei_caldrt_xlanopeak_en ++//bit 28:24, reg_ei_caldrt_abext_monotrnd_alpha ++//bit 28:24, reg_ei_caldrt_abext_mononum12_thrd ++//bit 28:24, reg_ei_caldrt_abext_mononum00_thrd ++//bit 28:24, reg_ei_caldrt_abext_sad00rate ++//bit 28:24, reg_ei_caldrt_abext_sad12rate ++//bit 28:24, reg_ei_caldrt_abext_sad00thhig ++#define DI_EI_CTRL8 (0x171e) ++#define P_DI_EI_CTRL8 (volatile unsigned int *)((0x171e << 2) + 0xff900000) ++//bit 30:28, reg_ei_assign_headtail_magin ++//bit 26:24, reg_ei_retime_lastcurpncnfltchk_mode ++//bit 22:21, reg_ei_retime_lastcurpncnfltchk_drtth ++//bit 20, reg_ei_caldrt_histchk_cnfid ++//bit 19:16, reg_ei_caldrt_histchk_thrd ++//bit 15, reg_ei_caldrt_histchk_abext ++//bit 14, reg_ei_caldrt_histchk_npen ++//bit 13:11, reg_ei_caldrt_amblike2_drtmg ++//bit 10:8, reg_ei_caldrt_amblike2_valmg ++//bit 7:4, reg_ei_caldrt_amblike2_alpha ++//bit 3:0, reg_ei_caldrt_amblike2_drtth ++#define DI_EI_CTRL9 (0x171f) ++#define P_DI_EI_CTRL9 (volatile unsigned int *)((0x171f << 2) + 0xff900000) ++//bit 31:28, reg_ei_caldrt_hcnfcheck_frcvert_xla_th3 ++//bit 27, reg_ei_caldrt_hcnfcheck_frcvert_xla_en ++//bit 26:24, reg_ei_caldrt_conf_drtth ++//bit 23:20, reg_ei_caldrt_conf_absdrtth ++//bit 19:18, reg_ei_caldrt_abcheck_mode1 ++//bit 17:16, reg_ei_caldrt_abcheck_mode0 ++//bit 15:12, reg_ei_caldrt_abcheck_drth1 ++//bit 11:8, reg_ei_caldrt_abcheck_drth0 ++//bit 6:4, reg_ei_caldrt_abpnchk1_th ++//bit 1, reg_ei_caldrt_abpnchk1_en ++//bit 0, reg_ei_caldrt_abpnchk0_en ++// DEINTERLACE mode check. ++#define DI_MC_REG0_X (0x1720) ++#define P_DI_MC_REG0_X (volatile unsigned int *)((0x1720 << 2) + 0xff900000) ++//bit 27:16, mc_reg0_start_x ++//bit 11:0, mc_reg0_end_x ++#define DI_MC_REG0_Y (0x1721) ++#define P_DI_MC_REG0_Y (volatile unsigned int *)((0x1721 << 2) + 0xff900000) ++#define DI_MC_REG1_X (0x1722) ++#define P_DI_MC_REG1_X (volatile unsigned int *)((0x1722 << 2) + 0xff900000) ++#define DI_MC_REG1_Y (0x1723) ++#define P_DI_MC_REG1_Y (volatile unsigned int *)((0x1723 << 2) + 0xff900000) ++#define DI_MC_REG2_X (0x1724) ++#define P_DI_MC_REG2_X (volatile unsigned int *)((0x1724 << 2) + 0xff900000) ++#define DI_MC_REG2_Y (0x1725) ++#define P_DI_MC_REG2_Y (volatile unsigned int *)((0x1725 << 2) + 0xff900000) ++#define DI_MC_REG3_X (0x1726) ++#define P_DI_MC_REG3_X (volatile unsigned int *)((0x1726 << 2) + 0xff900000) ++#define DI_MC_REG3_Y (0x1727) ++#define P_DI_MC_REG3_Y (volatile unsigned int *)((0x1727 << 2) + 0xff900000) ++#define DI_MC_REG4_X (0x1728) ++#define P_DI_MC_REG4_X (volatile unsigned int *)((0x1728 << 2) + 0xff900000) ++#define DI_MC_REG4_Y (0x1729) ++#define P_DI_MC_REG4_Y (volatile unsigned int *)((0x1729 << 2) + 0xff900000) ++#define DI_MC_32LVL0 (0x172a) ++#define P_DI_MC_32LVL0 (volatile unsigned int *)((0x172a << 2) + 0xff900000) ++//bit 31:24, mc_reg2_32lvl ++//bit 23:16, mc_reg1_32lvl ++//bit 15:8, mc_reg0_32lvl ++//bit 7:0, field_32lvl ++#define DI_MC_32LVL1 (0x172b) ++#define P_DI_MC_32LVL1 (volatile unsigned int *)((0x172b << 2) + 0xff900000) ++//bit 15:8, mc_reg3_32lvl ++//bit 7:0, mc_reg4_32lvl ++#define DI_MC_22LVL0 (0x172c) ++#define P_DI_MC_22LVL0 (volatile unsigned int *)((0x172c << 2) + 0xff900000) ++//bit 31:16, mc_reg0_22lvl ++//bit 15:0, field_22lvl ++#define DI_MC_22LVL1 (0x172d) ++#define P_DI_MC_22LVL1 (volatile unsigned int *)((0x172d << 2) + 0xff900000) ++//bit 31:16, mc_reg2_22lvl ++//bit 15:0, mc_reg1_22lvl ++#define DI_MC_22LVL2 (0x172e) ++#define P_DI_MC_22LVL2 (volatile unsigned int *)((0x172e << 2) + 0xff900000) ++//bit 31:16, mc_reg4_22lvl ++//bit 15:0, mc_reg3_22lvl ++#define DI_MC_CTRL (0x172f) ++#define P_DI_MC_CTRL (volatile unsigned int *)((0x172f << 2) + 0xff900000) ++//bit 4, mc_reg4_en ++//bit 3, mc_reg3_en ++//bit 2, mc_reg2_en ++//bit 1, mc_reg1_en ++//bit 0, mc_reg0_en ++#define DI_INTR_CTRL (0x1730) ++#define P_DI_INTR_CTRL (volatile unsigned int *)((0x1730 << 2) + 0xff900000) ++#define DI_INFO_ADDR (0x1731) ++#define P_DI_INFO_ADDR (volatile unsigned int *)((0x1731 << 2) + 0xff900000) ++#define DI_INFO_DATA (0x1732) ++#define P_DI_INFO_DATA (volatile unsigned int *)((0x1732 << 2) + 0xff900000) ++#define DI_PRE_HOLD (0x1733) ++#define P_DI_PRE_HOLD (volatile unsigned int *)((0x1733 << 2) + 0xff900000) ++//// DET 3D REG DEFINE BEGIN //// ++//// 8'h34~8'h3f ++// `define DET3D_MOTN_CFG 8'h34 ++// //Bit 16, reg_det3d_intr_en Det3d interrupt enable ++// //Bit 9:8, reg_Det3D_Motion_Mode U2 Different mode for Motion Calculation of Luma and Chroma: ++// // 0: MotY, 1: (2*MotY + (MotU + MotV))/4; 2: Max(MotY, MotU,MotV); 3:Max(MotY, (MotU+MotV)/2) ++// //Bit 7:4, reg_Det3D_Motion_Core_Rate U4 K Rate to Edge (HV) details for coring of Motion Calculations, normalized to 32 ++// //Bit 3:0, reg_Det3D_Motion_Core_Thrd U4 2X: static coring value for Motion Detection. ++// ++// `define DET3D_CB_CFG 8'h35 ++// //Bit 7:4, reg_Det3D_ChessBd_NHV_ofst U4, Noise immune offset for NON-Horizotnal or vertical combing detection. ++// //Bit 3:0, reg_Det3D_ChessBd_HV_ofst U4, Noise immune offset for Horizotnal or vertical combing detection. ++// ++// `define DET3D_SPLT_CFG 8'h36 ++// //Bit 7:4, reg_Det3D_SplitValid_ratio U4, Ratio between max_value and the avg_value of the edge mapping for split line valid detection. ++// // The smaller of this value, the easier of the split line detected. ++// //Bit 3:0, reg_Det3D_AvgIdx_ratio U4, Ratio to the avg_value of the edge mapping for split line position estimation. ++// // The smaller of this value, the more samples will be added to the estimation. ++// ++// `define DET3D_HV_MUTE 8'h37 ++// //Bit 23:20, reg_Det3D_Edge_Ver_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Top and Bottom border part. ++// //Bit 19:16, reg_Det3D_Edge_Hor_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Left and right border part. ++// //Bit 15:12, reg_Det3D_ChessBd_Ver_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part ++// //Bit 11:8, reg_Det3D_ChessBd_Hor_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part ++// //Bit 7:4, reg_Det3D_STA8X8_Ver_Mute U4 1X: Vertical pixels to be mute from 8x8 statistics calculation in each block. ++// //Bit 3:0, reg_Det3D_STA8X8_Hor_Mute U4 1X: Horizontal pixels to be mute from 8x8 statistics calculation in each block. ++// ++// `define DET3D_MAT_STA_P1M1 8'h38 ++// //Bit 31:24, reg_Det3D_STA8X8_P1_K0_R8 U8 SAD to SAI ratio to decide P1, normalized to 256 (0.8) ++// //Bit 23:16, reg_Det3D_STA8X8_P1_K1_R7 U8 SAD to ENG ratio to decide P1, normalized to 128 (0.5) ++// //Bit 15:8, reg_Det3D_STA8X8_M1_K0_R6 U8 SAD to SAI ratio to decide M1, normalized to 64 (1.1) ++// //Bit 7:0, reg_Det3D_STA8X8_M1_K1_R6 U8 SAD to ENG ratio to decide M1, normalized to 64 (0.8) ++// ++// `define DET3D_MAT_STA_P1TH 8'h39 ++// //Bit 23:16, reg_Det3D_STAYUV_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (100) ++// //Bit 15:8, reg_Det3D_STAEDG_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (80) ++// //Bit 7:0, reg_Det3D_STAMOT_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (48) ++// ++// `define DET3D_MAT_STA_M1TH 8'h3a ++// //Bit 23:16, reg_Det3D_STAYUV_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (100) ++// //Bit 15:8, reg_Det3D_STAEDG_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (80) ++// //Bit 7:0, reg_Det3D_STAMOT_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (64) ++// ++// `define DET3D_MAT_STA_RSFT 8'h3b ++// //Bit 5:4, reg_Det3D_STAYUV_RSHFT U2 YUV statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping: ++// // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions ++// //Bit 3:2, reg_Det3D_STAEDG_RSHFT U2 Horizontal and Vertical Edge Statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping: ++// // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions ++// //Bit 1:0, reg_Det3D_STAMOT_RSHFT U2 Motion SAD and SAI calculation result right shift bits to accommodate the 12bits clipping: ++// // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions ++// ++// `define DET3D_MAT_SYMTC_TH 8'h3c ++// //Bit 31:24, reg_Det3D_STALUM_symtc_Th U8 threshold to decide if the Luma statistics is TB or LR symmetric. ++// //Bit 23:16, reg_Det3D_STACHR_symtc_Th U8 threshold to decide if the Chroma (UV) statistics is TB or LR symmetric. ++// //Bit 15:8, reg_Det3D_STAEDG_symtc_Th U8 threshold to decide if the Horizontal and Vertical Edge statistics is TB or LR symmetric. ++// //Bit 7:0, reg_Det3D_STAMOT_symtc_Th U8 threshold to decide if the Motion statistics is TB or LR symmetric. ++// ++// `define DET3D_RO_DET_CB_HOR 8'h3d ++// //Bit 31:16, RO_Det3D_ChessBd_NHor_value U16 X64: number of Pixels of Horizontally Surely NOT matching Chessboard pattern. ++// //Bit 15:0, RO_Det3D_ChessBd_Hor_value U16 X64: number of Pixels of Horizontally Surely matching Chessboard pattern. ++// ++// `define DET3D_RO_DET_CB_VER 8'h3e ++// //Bit 31:16, RO_Det3D_ChessBd_NVer_value U16 X64: number of Pixels of Vertically Surely NOT matching Chessboard pattern. ++// //Bit 15:0, RO_Det3D_ChessBd_Ver_value U16 X64: number of Pixels of Vertically Surely matching Chessboard pattern. ++// ++// `define DET3D_RO_SPLT_HT 8'h3f ++// //Bit 24, RO_Det3D_Split_HT_valid U1 horizontal LR split border detected valid signal for top half picture ++// //Bit 20:16, RO_Det3D_Split_HT_pxnum U5 number of pixels included for the LR split position estimation for top half picture ++// //Bit 9:0, RO_Det3D_Split_HT_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture ++// ++// //// DET 3D REG DEFINE END //// ++#define DI_MTN_1_CTRL1 (0x1740) ++#define P_DI_MTN_1_CTRL1 (volatile unsigned int *)((0x1740 << 2) + 0xff900000) ++//bit 31, mtn_1_en ++//bit 30, mtn_init ++//bit 29, di2nr_txt_en ++//bit 28, reserved ++//bit 27:24, mtn_def ++//bit 23:16, mtn_adp_yc ++//bit 15:8, mtn_adp_2c ++//bit 7:0, mtn_adp_2y ++#define DI_MTN_1_CTRL2 (0x1741) ++#define P_DI_MTN_1_CTRL2 (volatile unsigned int *)((0x1741 << 2) + 0xff900000) ++//bit 31:24, mtn_ykinter ++//bit 23:16, mtn_ckinter ++//bit 15:8, mtn_ykintra ++//bit 7:0, mtn_ckintra ++#define DI_MTN_1_CTRL3 (0x1742) ++#define P_DI_MTN_1_CTRL3 (volatile unsigned int *)((0x1742 << 2) + 0xff900000) ++//bit 31:24, mtn_tyrate ++//bit 23:16, mtn_tcrate ++//bit 15: 8, mtn_mxcmby ++//bit 7: 0, mtn_mxcmbc ++#define DI_MTN_1_CTRL4 (0x1743) ++#define P_DI_MTN_1_CTRL4 (volatile unsigned int *)((0x1743 << 2) + 0xff900000) ++//bit 31:24, mtn_tcorey ++//bit 23:16, mtn_tcorec ++//bit 15: 8, mtn_minth ++//bit 7: 0, mtn_maxth ++#define DI_MTN_1_CTRL5 (0x1744) ++#define P_DI_MTN_1_CTRL5 (volatile unsigned int *)((0x1744 << 2) + 0xff900000) ++//bit 31:28, mtn_m1b_extnd ++//bit 27:24, mtn_m1b_errod ++//bit 21:20, mtn_mot_txt_mode ++//bit 19:18, mtn_replace_cbyy ++//bit 17:16, mtn_replace_ybyc ++//bit 15: 8, mtn_core_ykinter ++//bit 7: 0, mtn_core_ckinter ++//// NR2 REG DEFINE BEGIN//// ++#define NR2_MET_NM_CTRL (0x1745) ++#define P_NR2_MET_NM_CTRL (volatile unsigned int *)((0x1745 << 2) + 0xff900000) ++//Bit 28, reg_NM_reset Reset to the status of the Loop filter. ++//Bit 27:24, reg_NM_calc_length Length mode of the Noise measurement sample number for statistics. ++// 0: 256 samples; 1: 512 samples; 2: 1024 samples; 隆颅X: 2^(8+x) samples ++//Bit 23:20, reg_NM_inc_step Loop filter input gain increase step. ++//Bit 19:16, reg_NM_dec_step Loop filter input gain decrease step. ++//Bit 15:8, reg_NM_YHPmot_thrd Luma channel HP portion motion for condition of pixels included in Luma Noise measurement. ++//Bit 7:0, reg_NM_CHPmot_thrd Chroma channel HP portion motion for condition of pixels included in Chroma Noise measurement. ++#define NR2_MET_NM_YCTRL (0x1746) ++#define P_NR2_MET_NM_YCTRL (volatile unsigned int *)((0x1746 << 2) + 0xff900000) ++//Bit 31:28, reg_NM_YPLL_target Target rate of NM_Ynoise_thrd to mean of the Luma Noise ++//Bit 27:24, reg_NM_YLPmot_thrd Luma channel LP portion motion for condition of pixels included in Luma Noise measurement. ++//Bit 23:16, reg_NM_YHPmot_thrd_min Minimum threshold for Luma channel HP portion motion to decide whether the pixel will be included in Luma noise measurement. ++//Bit 15:8, reg_NM_YHPmot_thrd_max Maximum threshold for Luma channel HP portion motion to decide whether the pixel will be included in Luma noise measurement. ++//Bit 7:0, reg_NM_Ylock_rate Rate to decide whether the Luma noise measurement is lock or not. ++#define NR2_MET_NM_CCTRL (0x1747) ++#define P_NR2_MET_NM_CCTRL (volatile unsigned int *)((0x1747 << 2) + 0xff900000) ++//Bit 31:28, reg_NM_CPLL_target Target rate of NM_Cnoise_thrd to mean of the Chroma Noise ++//Bit 27:24, reg_NM_CLPmot_thrd Chroma channel LP portion motion for condition of pixels included in Chroma Noise measurement. ++//Bit 23:16, reg_NM_CHPmot_thrd_min Minimum threshold for Chroma channel HP portion motion to decide whether the pixel will be included in Chroma noise measurement. ++//Bit 15:8, reg_NM_CHPmot_thrd_max Maximum threshold for Chroma channel HP portion motion to decide whether the pixel will be included in Chroma noise measurement. ++//Bit 7:0, reg_NM_Clock_rate Rate to decide whether the Chroma noise measurement is lock or not; ++#define NR2_MET_NM_TNR (0x1748) ++#define P_NR2_MET_NM_TNR (volatile unsigned int *)((0x1748 << 2) + 0xff900000) ++//Bit 25, ro_NM_TNR_Ylock Read-only register to tell ifLuma channel noise measurement is locked or not. ++//Bit 24, ro_NM_TNR_Clock Read-only register to tell if Chroma channel noise measurement is locked or not. ++//Bit 23:12, ro_NM_TNR_Ylevel Read-only register to give Luma channel noise level. It was 16x of pixel difference in 8 bits of YHPmot. ++//Bit 11:0, ro_NM_TNR_Clevel Read-only register to give Chroma channel noise level. It was 16x of pixel difference in 8 bits of CHPmot. ++#define NR2_MET_NMFRM_TNR_YLEV (0x1749) ++#define P_NR2_MET_NMFRM_TNR_YLEV (volatile unsigned int *)((0x1749 << 2) + 0xff900000) ++//Bit 28:0, ro_NMFrm_TNR_Ylevel Frame based Read-only register to give Luma channel noise level within one frame/field. ++#define NR2_MET_NMFRM_TNR_YCNT (0x174a) ++#define P_NR2_MET_NMFRM_TNR_YCNT (volatile unsigned int *)((0x174a << 2) + 0xff900000) ++//Bit 23:0, ro_NMFrm_TNR_Ycount Number ofLuma channel pixels included in Frame/Field based noise level measurement. ++#define NR2_MET_NMFRM_TNR_CLEV (0x174b) ++#define P_NR2_MET_NMFRM_TNR_CLEV (volatile unsigned int *)((0x174b << 2) + 0xff900000) ++//Bit 28:0, ro_NMFrm_TNR_Clevel Frame based Read-only register to give Chroma channel noise level within one frame/field. ++#define NR2_MET_NMFRM_TNR_CCNT (0x174c) ++#define P_NR2_MET_NMFRM_TNR_CCNT (volatile unsigned int *)((0x174c << 2) + 0xff900000) ++//Bit 23:0, ro_NMFrm_TNR_Ccount Number of Chroma channel pixels included in Frame/Field based noise level measurement. ++#define NR2_3DEN_MODE (0x174d) ++#define P_NR2_3DEN_MODE (volatile unsigned int *)((0x174d << 2) + 0xff900000) ++//Bit 6:4, Blend_3dnr_en_r ++//Bit 2:0, Blend_3dnr_en_l ++// `define NR2_IIR_CTRL 8'h4e ++// //Bit 15:14, reg_LP_IIR_8bit_mode LP IIR membitwidth mode:0: 10bits will be store in memory;1: 9bits will be store in memory; ++// // 2: 8bits will be store in memory;3: 7bits will be store in memory; ++// //Bit 13:12, reg_LP_IIR_mute_mode Mode for the LP IIR mute, ++// //Bit 11:8, reg_LP_IIR_mute_thrd Threshold of LP IIR mute to avoid ghost: ++// //Bit 7:6, reg_HP_IIR_8bit_mode IIR membitwidth mode:0: 10bits will be store in memory;1: 9bits will be store in memory; ++// // 2: 8bits will be store in memory;3: 7bits will be store in memory; ++// //Bit 5:4, reg_HP_IIR_mute_mode Mode for theLP IIR mute ++// //Bit 3:0, reg_HP_IIR_mute_thrd Threshold of HP IIR mute to avoid ghost ++// // ++#define NR2_SW_EN (0x174f) ++#define P_NR2_SW_EN (volatile unsigned int *)((0x174f << 2) + 0xff900000) ++//Bit 17:8, Clk_gate_ctrl ++//Bit 7, Cfr_enable ++//Bit 5, Det3d_en ++//Bit 4, Nr2_proc_en ++//Bit 0, Nr2_sw_en ++#define NR2_FRM_SIZE (0x1750) ++#define P_NR2_FRM_SIZE (volatile unsigned int *)((0x1750 << 2) + 0xff900000) ++//Bit 27:16, Frm_heigh Frame/field height ++//Bit 11: 0, Frm_width Frame/field width ++// `define NR2_SNR_SAD_CFG 8'h51 ++// //Bit 12, reg_MATNR_SNR_SAD_CenRPL U1, Enable signal for Current pixel position SAD to be replaced by SAD_min.0: do not replace Current pixel position SAD by SAD_min;1: do replacements ++// //Bit 11:8, reg_MATNR_SNR_SAD_coring Coring value of the intra-frame SAD. sum = (sum - reg_MATNR_SNR_SAD_coring);sum = (sum<0) ? 0: (sum>255)? 255: sum; ++// //Bit 6:5, reg_MATNR_SNR_SAD_WinMod Unsigned, Intra-frame SAD matching window mode:0: 1x1; 1: [1 1 1] 2: [1 2 1]; 3: [1 2 2 2 1]; ++// //Bit 4:0, Sad_coef_num Sad coeffient ++// ++// `define NR2_MATNR_SNR_OS 8'h52 ++// //Bit 7:4, reg_MATNR_SNR_COS SNR Filter overshoot control margin for UV channel (X2 to u10 scale) ++// //Bit 3:0, reg_MATNR_SNR_YOS SNR Filter overshoot control margin for luma channel (X2 to u10 scale) ++// ++// `define NR2_MATNR_SNR_NRM_CFG 8'h53 ++// //Bit 23:16, reg_MATNR_SNR_NRM_ofst Edge based SNR boosting normalization offset to SAD_max ; ++// //Bit 15:8, reg_MATNR_SNR_NRM_max Edge based SNR boosting normalization Max value ++// //Bit 7:0, reg_MATNR_SNR_NRM_min Edge based SNR boosting normalization Min value ++// ++// `define NR2_MATNR_SNR_NRM_GAIN 8'h54 ++// //Bit 15:8, reg_MATNR_SNR_NRM_Cgain Edge based SNR boosting normalization Gain for Chrm channel (norm 32 as 1) ++// //Bit 7:0, reg_MATNR_SNR_NRM_Ygain Edge based SNR boosting normalization Gain for Luma channel (norm 32 as 1) ++// ++// `define NR2_MATNR_SNR_LPF_CFG 8'h55 ++// //Bit 23:16,reg_MATNR_SNRLPF_SADmaxTH U8, Threshold to SADmax to use TNRLPF to replace SNRLPF. i.e.if (SAD_max msb ++//22:20 prehsc pattern start ++//18:16 prehsc pattern end ++//15:8 pattern, each patten 1 bit, from lsb -> msb ++//6:4 pattern start ++//2:0 pattern end ++#define VPP2_HSC_INI_PAT_CTRL (0x1935) ++#define P_VPP2_HSC_INI_PAT_CTRL (volatile unsigned int *)((0x1935 << 2) + 0xff900000) ++//Bit 3 minus black level enable for vadj2 ++//Bit 2 Video adjustment enable for vadj2 ++//Bit 1 minus black level enable for vadj1 ++//Bit 0 Video adjustment enable for vadj1 ++#define VPP2_VADJ_CTRL (0x1940) ++#define P_VPP2_VADJ_CTRL (volatile unsigned int *)((0x1940 << 2) + 0xff900000) ++//Bit 16:8 brightness, signed value ++//Bit 7:0 contrast, unsigned value, contrast from 0 <= contrast <2 ++#define VPP2_VADJ1_Y (0x1941) ++#define P_VPP2_VADJ1_Y (volatile unsigned int *)((0x1941 << 2) + 0xff900000) ++//cb' = cb*ma + cr*mb ++//cr' = cb*mc + cr*md ++//all are bit 9:0, signed value, -2 < ma/mb/mc/md < 2 ++#define VPP2_VADJ1_MA_MB (0x1942) ++#define P_VPP2_VADJ1_MA_MB (volatile unsigned int *)((0x1942 << 2) + 0xff900000) ++#define VPP2_VADJ1_MC_MD (0x1943) ++#define P_VPP2_VADJ1_MC_MD (volatile unsigned int *)((0x1943 << 2) + 0xff900000) ++//Bit 16:8 brightness, signed value ++//Bit 7:0 contrast, unsigned value, contrast from 0 <= contrast <2 ++#define VPP2_VADJ2_Y (0x1944) ++#define P_VPP2_VADJ2_Y (volatile unsigned int *)((0x1944 << 2) + 0xff900000) ++//cb' = cb*ma + cr*mb ++//cr' = cb*mc + cr*md ++//all are bit 9:0, signed value, -2 < ma/mb/mc/md < 2 ++#define VPP2_VADJ2_MA_MB (0x1945) ++#define P_VPP2_VADJ2_MA_MB (volatile unsigned int *)((0x1945 << 2) + 0xff900000) ++#define VPP2_VADJ2_MC_MD (0x1946) ++#define P_VPP2_VADJ2_MC_MD (volatile unsigned int *)((0x1946 << 2) + 0xff900000) ++//Read only ++//Bit 31, if it is true, it means this probe is valid in the last field/frame ++//Bit 29:20 component 0 ++//Bit 19:10 component 1 ++//Bit 9:0 component 2 ++#define VPP2_MATRIX_PROBE_COLOR (0x195c) ++#define P_VPP2_MATRIX_PROBE_COLOR (volatile unsigned int *)((0x195c << 2) + 0xff900000) ++//Bit 23:16 component 0 ++//Bit 15:8 component 1 ++//Bit 7:0 component 2 ++#define VPP2_MATRIX_HL_COLOR (0x195d) ++#define P_VPP2_MATRIX_HL_COLOR (volatile unsigned int *)((0x195d << 2) + 0xff900000) ++//28:16 probe x, postion ++//12:0 probe y, position ++#define VPP2_MATRIX_PROBE_POS (0x195e) ++#define P_VPP2_MATRIX_PROBE_POS (volatile unsigned int *)((0x195e << 2) + 0xff900000) ++//Bit 16, highlight_en ++//Bit 15 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix ++//Bit 14:12 probe_sel, 000: select post matrix, 001: select vd1 matrix, ++//Bit 9:8 matrix coef idx selection, 00: select post matrix, 01: select vd1 matrix ++//Bit 5 vd1 conversion matrix enable ++//Bit 4 reserved ++//Bit 2 output y/cb/cr saturation enable, only for post matrix (y saturate to 16-235, cb/cr saturate to 16-240) ++//Bit 1 input y/cb/cr saturation enable, only for post matrix (y saturate to 16-235, cb/cr saturate to 16-240) ++//Bit 0 post conversion matrix enable ++#define VPP2_MATRIX_CTRL (0x195f) ++#define P_VPP2_MATRIX_CTRL (volatile unsigned int *)((0x195f << 2) + 0xff900000) ++//Bit 28:16 coef00 ++//Bit 12:0 coef01 ++#define VPP2_MATRIX_COEF00_01 (0x1960) ++#define P_VPP2_MATRIX_COEF00_01 (volatile unsigned int *)((0x1960 << 2) + 0xff900000) ++//Bit 28:16 coef02 ++//Bit 12:0 coef10 ++#define VPP2_MATRIX_COEF02_10 (0x1961) ++#define P_VPP2_MATRIX_COEF02_10 (volatile unsigned int *)((0x1961 << 2) + 0xff900000) ++//Bit 28:16 coef11 ++//Bit 12:0 coef12 ++#define VPP2_MATRIX_COEF11_12 (0x1962) ++#define P_VPP2_MATRIX_COEF11_12 (volatile unsigned int *)((0x1962 << 2) + 0xff900000) ++//Bit 28:16 coef20 ++//Bit 12:0 coef21 ++#define VPP2_MATRIX_COEF20_21 (0x1963) ++#define P_VPP2_MATRIX_COEF20_21 (volatile unsigned int *)((0x1963 << 2) + 0xff900000) ++#define VPP2_MATRIX_COEF22 (0x1964) ++#define P_VPP2_MATRIX_COEF22 (volatile unsigned int *)((0x1964 << 2) + 0xff900000) ++//Bit 26:16 offset0 ++//Bit 10:0 offset1 ++#define VPP2_MATRIX_OFFSET0_1 (0x1965) ++#define P_VPP2_MATRIX_OFFSET0_1 (volatile unsigned int *)((0x1965 << 2) + 0xff900000) ++//Bit 10:0 offset2 ++#define VPP2_MATRIX_OFFSET2 (0x1966) ++#define P_VPP2_MATRIX_OFFSET2 (volatile unsigned int *)((0x1966 << 2) + 0xff900000) ++//Bit 26:16 pre_offset0 ++//Bit 10:0 pre_offset1 ++#define VPP2_MATRIX_PRE_OFFSET0_1 (0x1967) ++#define P_VPP2_MATRIX_PRE_OFFSET0_1 (volatile unsigned int *)((0x1967 << 2) + 0xff900000) ++//Bit 10:0 pre_offset2 ++#define VPP2_MATRIX_PRE_OFFSET2 (0x1968) ++#define P_VPP2_MATRIX_PRE_OFFSET2 (volatile unsigned int *)((0x1968 << 2) + 0xff900000) ++// dummy data used in the VPP postblend ++// Bit 23:16 Y ++// Bit 15:8 CB ++// Bit 7:0 CR ++#define VPP2_DUMMY_DATA1 (0x1969) ++#define P_VPP2_DUMMY_DATA1 (volatile unsigned int *)((0x1969 << 2) + 0xff900000) ++//Bit 31 gainoff module enable ++//Bit 26:16 gain0, 1.10 unsigned data ++//Bit 10:0 gain1, 1.10 unsigned dat ++#define VPP2_GAINOFF_CTRL0 (0x196a) ++#define P_VPP2_GAINOFF_CTRL0 (volatile unsigned int *)((0x196a << 2) + 0xff900000) ++//Bit 26:16 gain2, 1.10 unsigned data ++//Bit 10:0, offset0, signed data ++#define VPP2_GAINOFF_CTRL1 (0x196b) ++#define P_VPP2_GAINOFF_CTRL1 (volatile unsigned int *)((0x196b << 2) + 0xff900000) ++//Bit 26:16, offset1, signed data ++//Bit 10:0, offset2, signed data ++#define VPP2_GAINOFF_CTRL2 (0x196c) ++#define P_VPP2_GAINOFF_CTRL2 (volatile unsigned int *)((0x196c << 2) + 0xff900000) ++//Bit 26:16, pre_offset0, signed data ++//Bit 10:0, pre_offset1, signed data ++#define VPP2_GAINOFF_CTRL3 (0x196d) ++#define P_VPP2_GAINOFF_CTRL3 (volatile unsigned int *)((0x196d << 2) + 0xff900000) ++//Bit 10:0, pre_offset2, signed data ++#define VPP2_GAINOFF_CTRL4 (0x196e) ++#define P_VPP2_GAINOFF_CTRL4 (volatile unsigned int *)((0x196e << 2) + 0xff900000) ++//only two registers used in the color management, which are defined in the chroma_reg.h ++#define VPP2_CHROMA_ADDR_PORT (0x1970) ++#define P_VPP2_CHROMA_ADDR_PORT (volatile unsigned int *)((0x1970 << 2) + 0xff900000) ++#define VPP2_CHROMA_DATA_PORT (0x1971) ++#define P_VPP2_CHROMA_DATA_PORT (volatile unsigned int *)((0x1971 << 2) + 0xff900000) ++//`include "chroma_reg.h" //defined inside is the indirect addressed registers ++//(hsvsharp), (blue), gainoff, mat_vd1,mat_vd2, mat_post, prebld, postbld,(hsharp),sco_ff, vadj1, vadj2, ofifo, (chroma1), clk0(free_clk) vpp_reg ++//each item 2bits, for each 2bits, if bit 2*i+1 == 1, free clk, else if bit 2*i == 1 no clk, else auto gated clock ++//bit1 is not used, because I can not turn off vpp_reg clk because I can not turn on again ++//because the register itself canot be set again without clk ++//Bit 31:0 ++#define VPP2_GCLK_CTRL0 (0x1972) ++#define P_VPP2_GCLK_CTRL0 (volatile unsigned int *)((0x1972 << 2) + 0xff900000) ++//Chroma2_filter, Chroma2, (Ccoring), (blackext), dnlp ++//Bit 9:0 ++#define VPP2_GCLK_CTRL1 (0x1973) ++#define P_VPP2_GCLK_CTRL1 (volatile unsigned int *)((0x1973 << 2) + 0xff900000) ++//prehsc_clk, line_buf, prevsc, vsc, hsc_clk, clk0(free_clk) ++//Bit 11:0 ++#define VPP2_SC_GCLK_CTRL (0x1974) ++#define P_VPP2_SC_GCLK_CTRL (volatile unsigned int *)((0x1974 << 2) + 0xff900000) ++//Bit 17:9 VD1 alpha for preblend ++//Bit 8:0 VD1 alpha for postblend ++#define VPP2_MISC1 (0x1976) ++#define P_VPP2_MISC1 (volatile unsigned int *)((0x1976 << 2) + 0xff900000) ++//Bit 31:24 bottom of region03 output value ++//Bit 23:16 bottom of region02 output value ++//Bit 15:8 bottom of region01 output value ++//Bit 7:0 bottom of region00 output value ++#define VPP2_DNLP_CTRL_00 (0x1981) ++#define P_VPP2_DNLP_CTRL_00 (volatile unsigned int *)((0x1981 << 2) + 0xff900000) ++//Bit 31:24 bottom of region07 output value ++//Bit 23:16 bottom of region06 output value ++//Bit 15:8 bottom of region05 output value ++//Bit 7:0 bottom of region04 output value ++#define VPP2_DNLP_CTRL_01 (0x1982) ++#define P_VPP2_DNLP_CTRL_01 (volatile unsigned int *)((0x1982 << 2) + 0xff900000) ++//Bit 31:24 bottom of region11 output value ++//Bit 23:16 bottom of region10 output value ++//Bit 15:8 bottom of region09 output value ++//Bit 7:0 bottom of region08 output value ++#define VPP2_DNLP_CTRL_02 (0x1983) ++#define P_VPP2_DNLP_CTRL_02 (volatile unsigned int *)((0x1983 << 2) + 0xff900000) ++//Bit 31:24 bottom of region15 output value ++//Bit 23:16 bottom of region14 output value ++//Bit 15:8 bottom of region13 output value ++//Bit 7:0 bottom of region12 output value ++#define VPP2_DNLP_CTRL_03 (0x1984) ++#define P_VPP2_DNLP_CTRL_03 (volatile unsigned int *)((0x1984 << 2) + 0xff900000) ++//Bit 31:24 bottom of region19 output value ++//Bit 23:16 bottom of region18 output value ++//Bit 15:8 bottom of region17 output value ++//Bit 7:0 bottom of region16 output value ++#define VPP2_DNLP_CTRL_04 (0x1985) ++#define P_VPP2_DNLP_CTRL_04 (volatile unsigned int *)((0x1985 << 2) + 0xff900000) ++//Bit 31:24 bottom of region23 output value ++//Bit 23:16 bottom of region22 output value ++//Bit 15:8 bottom of region21 output value ++//Bit 7:0 bottom of region20 output value ++#define VPP2_DNLP_CTRL_05 (0x1986) ++#define P_VPP2_DNLP_CTRL_05 (volatile unsigned int *)((0x1986 << 2) + 0xff900000) ++//Bit 31:24 bottom of region27 output value ++//Bit 23:16 bottom of region26 output value ++//Bit 15:8 bottom of region25 output value ++//Bit 7:0 bottom of region24 output value ++#define VPP2_DNLP_CTRL_06 (0x1987) ++#define P_VPP2_DNLP_CTRL_06 (volatile unsigned int *)((0x1987 << 2) + 0xff900000) ++//Bit 31:24 bottom of region31 output value ++//Bit 23:16 bottom of region30 output value ++//Bit 15:8 bottom of region29 output value ++//Bit 7:0 bottom of region28 output value ++#define VPP2_DNLP_CTRL_07 (0x1988) ++#define P_VPP2_DNLP_CTRL_07 (volatile unsigned int *)((0x1988 << 2) + 0xff900000) ++//Bit 31:24 bottom of region35 output value ++//Bit 23:16 bottom of region34 output value ++//Bit 15:8 bottom of region33 output value ++//Bit 7:0 bottom of region32 output value ++#define VPP2_DNLP_CTRL_08 (0x1989) ++#define P_VPP2_DNLP_CTRL_08 (volatile unsigned int *)((0x1989 << 2) + 0xff900000) ++//Bit 31:24 bottom of region39 output value ++//Bit 23:16 bottom of region38 output value ++//Bit 15:8 bottom of region37 output value ++//Bit 7:0 bottom of region36 output value ++#define VPP2_DNLP_CTRL_09 (0x198a) ++#define P_VPP2_DNLP_CTRL_09 (volatile unsigned int *)((0x198a << 2) + 0xff900000) ++//Bit 31:24 bottom of region43 output value ++//Bit 23:16 bottom of region42 output value ++//Bit 15:8 bottom of region41 output value ++//Bit 7:0 bottom of region40 output value ++#define VPP2_DNLP_CTRL_10 (0x198b) ++#define P_VPP2_DNLP_CTRL_10 (volatile unsigned int *)((0x198b << 2) + 0xff900000) ++//Bit 31:24 bottom of region47 output value ++//Bit 23:16 bottom of region46 output value ++//Bit 15:8 bottom of region45 output value ++//Bit 7:0 bottom of region44 output value ++#define VPP2_DNLP_CTRL_11 (0x198c) ++#define P_VPP2_DNLP_CTRL_11 (volatile unsigned int *)((0x198c << 2) + 0xff900000) ++//Bit 31:24 bottom of region51 output value ++//Bit 23:16 bottom of region50 output value ++//Bit 15:8 bottom of region49 output value ++//Bit 7:0 bottom of region48 output value ++#define VPP2_DNLP_CTRL_12 (0x198d) ++#define P_VPP2_DNLP_CTRL_12 (volatile unsigned int *)((0x198d << 2) + 0xff900000) ++//Bit 31:24 bottom of region55 output value ++//Bit 23:16 bottom of region54 output value ++//Bit 15:8 bottom of region53 output value ++//Bit 7:0 bottom of region52 output value ++#define VPP2_DNLP_CTRL_13 (0x198e) ++#define P_VPP2_DNLP_CTRL_13 (volatile unsigned int *)((0x198e << 2) + 0xff900000) ++//Bit 31:24 bottom of region59 output value ++//Bit 23:16 bottom of region58 output value ++//Bit 15:8 bottom of region57 output value ++//Bit 7:0 bottom of region56 output value ++#define VPP2_DNLP_CTRL_14 (0x198f) ++#define P_VPP2_DNLP_CTRL_14 (volatile unsigned int *)((0x198f << 2) + 0xff900000) ++//Bit 31:24 bottom of region63 output value ++//Bit 23:16 bottom of region62 output value ++//Bit 15:8 bottom of region61 output value ++//Bit 7:0 bottom of region60 output value ++#define VPP2_DNLP_CTRL_15 (0x1990) ++#define P_VPP2_DNLP_CTRL_15 (volatile unsigned int *)((0x1990 << 2) + 0xff900000) ++//Bit 20 reserved ++//Bit 19 reserved ++//Bit 18 demo dynamic nonlinear luma processing enable ++//Bit 17 reserved ++//Bit 16 reserved ++//Bit 15:14, 2'b00: demo adjust on top, 2'b01: demo adjust on bottom, 2'b10: demo adjust on left, 2'b11: demo adjust on right ++//Bit 4 reserved ++//Bit 3 reserved ++//Bit 2 dynamic nonlinear luma processing enable ++//Bit 1 reserved ++//Bit 0 reserved ++#define VPP2_VE_ENABLE_CTRL (0x19a1) ++#define P_VPP2_VE_ENABLE_CTRL (volatile unsigned int *)((0x19a1 << 2) + 0xff900000) ++//Bit 12:0, demo left or top screen width ++#define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH (0x19a2) ++#define P_VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH (volatile unsigned int *)((0x19a2 << 2) + 0xff900000) ++#define VPP2_VE_DEMO_CENTER_BAR (0x19a3) ++#define P_VPP2_VE_DEMO_CENTER_BAR (volatile unsigned int *)((0x19a3 << 2) + 0xff900000) ++//28:16 ve_line_length ++//12:0 ve_pic_height ++#define VPP2_VE_H_V_SIZE (0x19a4) ++#define P_VPP2_VE_H_V_SIZE (volatile unsigned int *)((0x19a4 << 2) + 0xff900000) ++//Bit 10 reset bit, high active ++//Bit 9 0: measuring rising edge, 1: measuring falling edge ++//Bit 8 if true, accumulate the counter number, otherwise not ++//Bit 7:0 vsync_span, define how many vsync span need to measure ++#define VPP2_VDO_MEAS_CTRL (0x19a8) ++#define P_VPP2_VDO_MEAS_CTRL (volatile unsigned int *)((0x19a8 << 2) + 0xff900000) ++//Read only ++//19:16 ind_meas_count_n, every number of sync_span vsyncs, this counter add 1 ++//15:0, high bit portion of counter ++#define VPP2_VDO_MEAS_VS_COUNT_HI (0x19a9) ++#define P_VPP2_VDO_MEAS_VS_COUNT_HI (volatile unsigned int *)((0x19a9 << 2) + 0xff900000) ++//Read only ++//31:0, low bit portion of counter ++#define VPP2_VDO_MEAS_VS_COUNT_LO (0x19aa) ++#define P_VPP2_VDO_MEAS_VS_COUNT_LO (volatile unsigned int *)((0x19aa << 2) + 0xff900000) ++//vertical scaler phase step ++//Bit 27:0, 4.24 format ++#define VPP2_OSD_VSC_PHASE_STEP (0x19c0) ++#define P_VPP2_OSD_VSC_PHASE_STEP (volatile unsigned int *)((0x19c0 << 2) + 0xff900000) ++//Bit 31:16, botttom vertical scaler initial phase ++//Bit 15:0, top vertical scaler initial phase ++#define VPP2_OSD_VSC_INI_PHASE (0x19c1) ++#define P_VPP2_OSD_VSC_INI_PHASE (volatile unsigned int *)((0x19c1 << 2) + 0xff900000) ++//Bit 24 osd vertical Scaler enable ++//Bit 23 osd_prog_interlace 0: current field is progressive, 1: current field is interlace ++//Bit 22:21 osd_vsc_double_line_mode, bit1, double input width and half input height, bit0, change line buffer becomes 2 lines ++//Bit 20 osd_vsc_phase0_always_en ++//Bit 19 osd_vsc_nearest_en ++//Bit 17:16 osd_vsc_bot_rpt_l0_num ++//Bit 14:11 osd_vsc_bot_ini_rcv_num ++//Bit 9:8 osd_vsc_top_rpt_l0_num ++//Bit 6:3 osd_vsc_top_ini_rcv_num ++//Bit 2:0 osd_vsc_bank_length ++#define VPP2_OSD_VSC_CTRL0 (0x19c2) ++#define P_VPP2_OSD_VSC_CTRL0 (volatile unsigned int *)((0x19c2 << 2) + 0xff900000) ++//horizontal scaler phase step ++//Bit 27:0, 4.24 format ++#define VPP2_OSD_HSC_PHASE_STEP (0x19c3) ++#define P_VPP2_OSD_HSC_PHASE_STEP (volatile unsigned int *)((0x19c3 << 2) + 0xff900000) ++//Bit 31:16, horizontal scaler initial phase1 ++//Bit 15:0, horizontal scaler initial phase0 ++#define VPP2_OSD_HSC_INI_PHASE (0x19c4) ++#define P_VPP2_OSD_HSC_INI_PHASE (volatile unsigned int *)((0x19c4 << 2) + 0xff900000) ++//Bit 22 osd horizontal scaler enable ++//Bit 21 osd_hsc_double_pix_mode ++//Bit 20 osd_hsc_phase0_always_en ++//Bit 19 osd_hsc_nearest_en ++//Bit 17:16 osd_hsc_rpt_p0_num1 ++//Bit 14:11 osd_hsc_ini_rcv_num1 ++//Bit 9:8 osd_hsc_rpt_p0_num0 ++//Bit 6:3 osd_hsc_ini_rcv_num0 ++//Bit 2:0 osd_hsc_bank_length ++#define VPP2_OSD_HSC_CTRL0 (0x19c5) ++#define P_VPP2_OSD_HSC_CTRL0 (volatile unsigned int *)((0x19c5 << 2) + 0xff900000) ++//for 3D quincunx sub-sampling ++//bit 15:8 pattern, each patten 1 bit, from lsb -> msb ++//bit 6:4 pattern start ++//bit 2:0 pattern end ++#define VPP2_OSD_HSC_INI_PAT_CTRL (0x19c6) ++#define P_VPP2_OSD_HSC_INI_PAT_CTRL (volatile unsigned int *)((0x19c6 << 2) + 0xff900000) ++//bit 31:24, componet 0 ++//bit 23:16, component 1 ++//bit 15:8, component 2 ++//bit 7:0 component 3, alpha ++#define VPP2_OSD_SC_DUMMY_DATA (0x19c7) ++#define P_VPP2_OSD_SC_DUMMY_DATA (volatile unsigned int *)((0x19c7 << 2) + 0xff900000) ++//Bit 14 osc_sc_din_osd1_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha. ++//Bit 13 osc_sc_din_osd2_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha. ++//Bit 12 osc_sc_dout_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha. ++//Bit 12 osc_sc_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha. ++//Bit 11:4 default alpha for vd1 or vd2 if they are selected as the source ++//Bit 3 osd scaler path enable ++//Bit 1:0 osd_sc_sel, 00: select osd1 input, 01: select osd2 input, 10: select vd1 input, 11: select vd2 input after matrix ++#define VPP2_OSD_SC_CTRL0 (0x19c8) ++#define P_VPP2_OSD_SC_CTRL0 (volatile unsigned int *)((0x19c8 << 2) + 0xff900000) ++//Bit 28:16 OSD scaler input width minus 1 ++//Bit 12:0 OSD scaler input height minus 1 ++#define VPP2_OSD_SCI_WH_M1 (0x19c9) ++#define P_VPP2_OSD_SCI_WH_M1 (volatile unsigned int *)((0x19c9 << 2) + 0xff900000) ++//Bit 28:16 OSD scaler output horizontal start ++//Bit 12:0 OSD scaler output horizontal end ++#define VPP2_OSD_SCO_H_START_END (0x19ca) ++#define P_VPP2_OSD_SCO_H_START_END (volatile unsigned int *)((0x19ca << 2) + 0xff900000) ++//Bit 28:16 OSD scaler output vertical start ++//Bit 12:0 OSD scaler output vertical end ++#define VPP2_OSD_SCO_V_START_END (0x19cb) ++#define P_VPP2_OSD_SCO_V_START_END (volatile unsigned int *)((0x19cb << 2) + 0xff900000) ++//Because there are many coefficients used in the vertical filter and horizontal filters, ++//indirect access the coefficients of vertical filter and horizontal filter is used. ++//For vertical filter, there are 33x4 coefficients ++//For horizontal filter, there are 33x4 coefficients ++//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2) ++//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not ++//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef ++//Bit 8 type of index, 0: vertical coef, 1: horizontal coef ++//Bit 6:0 coef index ++#define VPP2_OSD_SCALE_COEF_IDX (0x19cc) ++#define P_VPP2_OSD_SCALE_COEF_IDX (volatile unsigned int *)((0x19cc << 2) + 0xff900000) ++//coefficients for vertical filter and horizontal filter ++#define VPP2_OSD_SCALE_COEF (0x19cd) ++#define P_VPP2_OSD_SCALE_COEF (volatile unsigned int *)((0x19cd << 2) + 0xff900000) ++//Bit 12:0 line number use to generate interrupt when line == this number ++#define VPP2_INT_LINE_NUM (0x19ce) ++#define P_VPP2_INT_LINE_NUM (volatile unsigned int *)((0x19ce << 2) + 0xff900000) ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: vpp2_regs.h ++// ++//`define VIU_VCBUS_BASE 8'h1a ++// ++// Reading file: vregs_clk2.h ++// ++//=========================================================================== ++// Video Interface Registers 0xa00 - 0xaff ++//=========================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: VIU_VCBUS_BASE = 0x1a ++// ----------------------------------------------- ++#define VIU_ADDR_START (0x1a00) ++#define P_VIU_ADDR_START (volatile unsigned int *)((0x1a00 << 2) + 0xff900000) ++#define VIU_ADDR_END (0x1aff) ++#define P_VIU_ADDR_END (volatile unsigned int *)((0x1aff << 2) + 0xff900000) ++//`define TRACE_REG 8'ff ++//------------------------------------------------------------------------------ ++// VIU top-level registers ++//------------------------------------------------------------------------------ ++// Bit 0 RW, osd1_reset ++// Bit 1 RW, osd2_reset ++// Bit 2 RW, vd1_reset ++// Bit 3 RW, vd1_fmt_reset ++// Bit 4 RW, vd2_reset ++// Bit 5 RW, vd2_fmt_reset ++// Bit 6 RW, di_dsr1to2_reset ++// Bit 7 RW, vpp_reset ++// Bit 8 RW, di_if1_reset ++// Bit 9 RW, di_if1_fmt_reset ++// Bit 10 RW, di_inp_reset ++// Bit 11 RW, di_inp_fmt_reset ++// Bit 12 RW, di_mem_reset ++// Bit 13 RW, di_mem_fmt_reset ++// Bit 14 RW, di_nr_wr_mif_reset ++// Bit 15 RW, dein_wr_mif_reset ++// Bit 16 RW, di_chan2_mif_reset ++// Bit 17 RW, di_mtn_wr_mif_reset ++// Bit 18 RW, di_mtn_rd_mif_reset ++// Bit 19 RW, di_mad_reset ++// Bit 20 RW, vdin0_reset ++// Bit 21 RW, vdin1_reset ++// Bit 22 RW, nrin_mux_reset ++// Bit 23 RW, vdin0_wr_reset ++// Bit 24 RW, vdin1_wr_reset ++// Bit 25 RW, reserved ++// Bit 26 RW, d2d3_reset ++// Bit 27 RW, di_cont_wr_mif_reset ++// Bit 28 RW, di_cont_rd_mif_reset ++#define VIU_SW_RESET (0x1a01) ++#define P_VIU_SW_RESET (volatile unsigned int *)((0x1a01 << 2) + 0xff900000) ++#define VIU_SW_RESET0 (0x1a02) ++#define P_VIU_SW_RESET0 (volatile unsigned int *)((0x1a02 << 2) + 0xff900000) ++// Bit 0 RW, software reset for mcvecrd_mif ++// Bit 1 RW, software reset for mcinfowr_mif ++// Bit 2 RW, software reset for mcinford_mif ++#define VIU_SECURE_REG (0x1a04) ++#define P_VIU_SECURE_REG (volatile unsigned int *)((0x1a04 << 2) + 0xff900000) ++// Bit 0 RW, dolby core1_tv secure w and r ++// Bit 1 RW, dolby core2 secure w and r ++// Bit 2 RW, dolby core3 secure w and r ++// Bit 3 RW, for osd1 secure read ++// Bit 4 RW, for osd2 secure read ++#define DOLBY_INT_STAT (0x1a05) ++#define P_DOLBY_INT_STAT (volatile unsigned int *)((0x1a05 << 2) + 0xff900000) ++// todo ++//bit 15:12 osdbld_gclk_ctrl 3:2 regclk ctrl 1:0 blending clk control ++//bit 8 if true, vsync interrup is generate only field == 0 ++//bit 7:0 fix_disable ++#define VIU_MISC_CTRL0 (0x1a06) ++#define P_VIU_MISC_CTRL0 (volatile unsigned int *)((0x1a06 << 2) + 0xff900000) ++#define VIU_MISC_CTRL1 (0x1a07) ++#define P_VIU_MISC_CTRL1 (volatile unsigned int *)((0x1a07 << 2) + 0xff900000) ++// Bit 15:14 mali_afbcd_gclk_ctrl mali_afbcd clock gate control[5:4] ++// Bit 12 osd1_afbcd_axi_mux 0 : use the osd mif as input; 1 : use afbcd as input ++// Bit 11:8 mali_afbcd_gclk_ctrl mali_afbcd clock gate control[3:0] ++// Bit 7:2 vd2_afbcd_gclk_ctrl vd2_afbcd clock gate control ++// Bit 1 vpp_vd2_din_sel 0: vpp vd2 sel the mif input; 1: vpp vd2 sel the dos afbcd ++// Bit 0 vd2_afbcd_out_sel 0: vd2_afbcd output to vpp; 1 : vd2_afbcd output to di inp ++#define D2D3_INTF_LENGTH (0x1a08) ++#define P_D2D3_INTF_LENGTH (volatile unsigned int *)((0x1a08 << 2) + 0xff900000) ++// Bit 31:30 vdin0 dout splitter, bit 0 turns on vdin0 to old path, bit 1 turns on vdin0 to d2d3_intf vdin0 input path ++// Bit 29:28 vdin1 dout splitter, bit 0 turns on vdin1 to old path, bit 1 turns on vdin1 to d2d3_intf vdin1 input path ++// Bit 27:26 NR write dout splitter, bit 0 turns on NR write to old path, bit 1 turns on NR WR to d2d3_intf NR WR input path ++// Bit 23 if true, turn on clk_d2d3_reg (register clock) ++// Bit 22 if true, turn on clk_d2d3 ++// Bit 21 reg_v1_go_line ++// Bit 20 reg_v1_go_field ++// Bit 19 reg_v0_go_field ++// Bit 18:16 v1_gofld_sel, 000: display go_field/go_line, 001: DI pre_frame_rst/go_line, 010: vdin0 go_field/go_line, ++//011: vdin1 go_field/go_line, otherwise: force go_field by reg_v1_go_field(bit20), force go_line by reg_v1_go_line(bit21) ++// Bit 15:13 v0_gofld_sel, 000: display go_field, 001: DI pre_frame_rst, 010: vdin0 go_field, 011: vdin1 go_field, otherwise: force go_field by ++// reg_v0_go_field(bit19) ++// Bit 12:6 hole_lines for d2d3 depth read interface ++// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 fomart output), 2'b10: scale output, otherwise nothing as v1 ++// Bit 3 use_vdin_eol, if true, use vdin eol as the v0_eol, otherwise using length to get the v0_eol ++// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 fomart output), 101: vpp scale output ++// ++#define D2D3_INTF_CTRL0 (0x1a09) ++#define P_D2D3_INTF_CTRL0 (volatile unsigned int *)((0x1a09 << 2) + 0xff900000) ++//------------------------------------------------------------------------------ ++// OSD1 registers ++//------------------------------------------------------------------------------ ++// Bit 31 Reserved ++// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics; ++// 0=use gated clock for low power. ++// Bit 29 R, test_rd_dsr ++// Bit 28 R, osd_done ++// Bit 27:24 R, osd_blk_mode ++// Bit 23:22 R, osd_blk_ptr ++// Bit 21 R, osd_enable ++// ++// Bit 20:12 RW, global_alpha ++// Bit 11 RW, test_rd_en ++// Bit 10: 9 Reserved for control signals ++// Bit 8: 5 RW, ctrl_mtch_y ++// Bit 4 RW, ctrl_422to444 ++// Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable; ++// Bit 1 to enable block 1, and so on. ++#define VIU_OSD1_CTRL_STAT (0x1a10) ++#define P_VIU_OSD1_CTRL_STAT (volatile unsigned int *)((0x1a10 << 2) + 0xff900000) ++// Bit 31:26 Reserved ++// Bit 25:16 R, fifo_count ++// Bit 15 RW, osd_dpath_sel 0-osd1 mif 1-vpu mali afbcd ++// Bit 14 RW, replaced_alpha_en ++// Bit 13: 6 RW, replaced_alpha ++// Bit 5: 4 RW, hold_fifo_lines[6:5] ++// Bit 3 RW, rgb2yuv_full_range ++// Bit 2 RW, alpha_9b_mode ++// Bit 1 RW, reserved ++// Bit 0 RW, color_expand_mode ++#define VIU_OSD1_CTRL_STAT2 (0x1a2d) ++#define P_VIU_OSD1_CTRL_STAT2 (volatile unsigned int *)((0x1a2d << 2) + 0xff900000) ++// Bit 31: 9 Reserved ++// Bit 8 RW, 0 = Write LUT, 1 = Read LUT ++// Bit 7: 0 RW, lut_addr ++#define VIU_OSD1_COLOR_ADDR (0x1a11) ++#define P_VIU_OSD1_COLOR_ADDR (volatile unsigned int *)((0x1a11 << 2) + 0xff900000) ++// Bit 31:24 RW, Y or R ++// Bit 23:16 RW, Cb or G ++// Bit 15: 8 RW, Cr or B ++// Bit 7: 0 RW, Alpha ++#define VIU_OSD1_COLOR (0x1a12) ++#define P_VIU_OSD1_COLOR (volatile unsigned int *)((0x1a12 << 2) + 0xff900000) ++// Bit 31:24 RW, Y or R ++// Bit 23:16 RW, Cb or G ++// Bit 15: 8 RW, Cr or B ++// Bit 7: 0 RW, Alpha ++#define VIU_OSD1_TCOLOR_AG0 (0x1a17) ++#define P_VIU_OSD1_TCOLOR_AG0 (volatile unsigned int *)((0x1a17 << 2) + 0xff900000) ++#define VIU_OSD1_TCOLOR_AG1 (0x1a18) ++#define P_VIU_OSD1_TCOLOR_AG1 (volatile unsigned int *)((0x1a18 << 2) + 0xff900000) ++#define VIU_OSD1_TCOLOR_AG2 (0x1a19) ++#define P_VIU_OSD1_TCOLOR_AG2 (volatile unsigned int *)((0x1a19 << 2) + 0xff900000) ++#define VIU_OSD1_TCOLOR_AG3 (0x1a1a) ++#define P_VIU_OSD1_TCOLOR_AG3 (volatile unsigned int *)((0x1a1a << 2) + 0xff900000) ++// Bit 31:30 Reserved ++// Bit 29 RW, y_rev: 0=normal read, 1=reverse read in Y direction ++// Bit 28 RW, x_rev: 0=normal read, 1=reverse read in X direction ++// Bit 27:24 Reserved ++// Bit 23:16 RW, tbl_addr ++// Bit 15 RW, little_endian: 0=big endian, 1=little endian ++// Bit 14 RW, rpt_y ++// Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous ++// pixel; 11=Interpolate with the average value ++// between previous and next pixel. ++// Bit 11: 8 RW, osd_blk_mode ++// Bit 7 RW, rgb_en ++// Bit 6 RW, tc_alpha_en ++// Bit 5: 2 RW, color_matrix ++// Bit 1 RW, interlace_en ++// Bit 0 RW, interlace_sel_odd ++#define VIU_OSD1_BLK0_CFG_W0 (0x1a1b) ++#define P_VIU_OSD1_BLK0_CFG_W0 (volatile unsigned int *)((0x1a1b << 2) + 0xff900000) ++#define VIU_OSD1_BLK1_CFG_W0 (0x1a1f) ++#define P_VIU_OSD1_BLK1_CFG_W0 (volatile unsigned int *)((0x1a1f << 2) + 0xff900000) ++#define VIU_OSD1_BLK2_CFG_W0 (0x1a23) ++#define P_VIU_OSD1_BLK2_CFG_W0 (volatile unsigned int *)((0x1a23 << 2) + 0xff900000) ++#define VIU_OSD1_BLK3_CFG_W0 (0x1a27) ++#define P_VIU_OSD1_BLK3_CFG_W0 (volatile unsigned int *)((0x1a27 << 2) + 0xff900000) ++// Bit 31:29 Reserved ++// Bit 28:16 RW, x_end ++// Bit 15:13 Reserved ++// Bit 12: 0 RW, x_start ++#define VIU_OSD1_BLK0_CFG_W1 (0x1a1c) ++#define P_VIU_OSD1_BLK0_CFG_W1 (volatile unsigned int *)((0x1a1c << 2) + 0xff900000) ++#define VIU_OSD1_BLK1_CFG_W1 (0x1a20) ++#define P_VIU_OSD1_BLK1_CFG_W1 (volatile unsigned int *)((0x1a20 << 2) + 0xff900000) ++#define VIU_OSD1_BLK2_CFG_W1 (0x1a24) ++#define P_VIU_OSD1_BLK2_CFG_W1 (volatile unsigned int *)((0x1a24 << 2) + 0xff900000) ++#define VIU_OSD1_BLK3_CFG_W1 (0x1a28) ++#define P_VIU_OSD1_BLK3_CFG_W1 (volatile unsigned int *)((0x1a28 << 2) + 0xff900000) ++// Bit 31:29 Reserved ++// Bit 28:16 RW, y_end ++// Bit 15:13 Reserved ++// Bit 12: 0 RW, y_start ++#define VIU_OSD1_BLK0_CFG_W2 (0x1a1d) ++#define P_VIU_OSD1_BLK0_CFG_W2 (volatile unsigned int *)((0x1a1d << 2) + 0xff900000) ++#define VIU_OSD1_BLK1_CFG_W2 (0x1a21) ++#define P_VIU_OSD1_BLK1_CFG_W2 (volatile unsigned int *)((0x1a21 << 2) + 0xff900000) ++#define VIU_OSD1_BLK2_CFG_W2 (0x1a25) ++#define P_VIU_OSD1_BLK2_CFG_W2 (volatile unsigned int *)((0x1a25 << 2) + 0xff900000) ++#define VIU_OSD1_BLK3_CFG_W2 (0x1a29) ++#define P_VIU_OSD1_BLK3_CFG_W2 (volatile unsigned int *)((0x1a29 << 2) + 0xff900000) ++// Bit 31:28 Reserved ++// Bit 27:16 RW, h_end ++// Bit 15:12 Reserved ++// Bit 11: 0 RW, h_start ++#define VIU_OSD1_BLK0_CFG_W3 (0x1a1e) ++#define P_VIU_OSD1_BLK0_CFG_W3 (volatile unsigned int *)((0x1a1e << 2) + 0xff900000) ++#define VIU_OSD1_BLK1_CFG_W3 (0x1a22) ++#define P_VIU_OSD1_BLK1_CFG_W3 (volatile unsigned int *)((0x1a22 << 2) + 0xff900000) ++#define VIU_OSD1_BLK2_CFG_W3 (0x1a26) ++#define P_VIU_OSD1_BLK2_CFG_W3 (volatile unsigned int *)((0x1a26 << 2) + 0xff900000) ++#define VIU_OSD1_BLK3_CFG_W3 (0x1a2a) ++#define P_VIU_OSD1_BLK3_CFG_W3 (volatile unsigned int *)((0x1a2a << 2) + 0xff900000) ++// Bit 31:28 Reserved ++// Bit 27:16 RW, v_end ++// Bit 15:12 Reserved ++// Bit 11: 0 RW, v_start ++#define VIU_OSD1_BLK0_CFG_W4 (0x1a13) ++#define P_VIU_OSD1_BLK0_CFG_W4 (volatile unsigned int *)((0x1a13 << 2) + 0xff900000) ++#define VIU_OSD1_BLK1_CFG_W4 (0x1a14) ++#define P_VIU_OSD1_BLK1_CFG_W4 (volatile unsigned int *)((0x1a14 << 2) + 0xff900000) ++#define VIU_OSD1_BLK2_CFG_W4 (0x1a15) ++#define P_VIU_OSD1_BLK2_CFG_W4 (volatile unsigned int *)((0x1a15 << 2) + 0xff900000) ++#define VIU_OSD1_BLK3_CFG_W4 (0x1a16) ++#define P_VIU_OSD1_BLK3_CFG_W4 (volatile unsigned int *)((0x1a16 << 2) + 0xff900000) ++// Bit 31 RW, burst_len_sel[2] of [2:0] ++// Bit 30 RW, byte_swap: In addition to endian control, further define ++// whether to swap upper and lower byte within a 16-bit mem word. ++// 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]} ++// Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word ++// Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif ++// Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved ++// Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT ++// Bit 19 R, fifo_overflow ++// Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8. ++// Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128. ++// Bit 9: 5 RW, hold_fifo_lines[4:0] ++// Bit 4 RW, clear_err: one pulse to clear fifo_overflow ++// Bit 3 RW, fifo_sync_rst ++// Bit 2: 1 RW, endian ++// Bit 0 RW, urgent ++#define VIU_OSD1_FIFO_CTRL_STAT (0x1a2b) ++#define P_VIU_OSD1_FIFO_CTRL_STAT (volatile unsigned int *)((0x1a2b << 2) + 0xff900000) ++// Bit 31:24 R, Y or R ++// Bit 23:16 R, Cb or G ++// Bit 15: 8 R, Cr or B ++// Bit 7: 0 R, Output Alpha[8:1] ++#define VIU_OSD1_TEST_RDDATA (0x1a2c) ++#define P_VIU_OSD1_TEST_RDDATA (volatile unsigned int *)((0x1a2c << 2) + 0xff900000) ++// Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate. ++// Bit 12: 0 RW, effective FIFO size when prot_en=1. ++#define VIU_OSD1_PROT_CTRL (0x1a2e) ++#define P_VIU_OSD1_PROT_CTRL (volatile unsigned int *)((0x1a2e << 2) + 0xff900000) ++//Bit 7, highlight_en ++//Bit 6 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix ++//Bit 5:4 probe_sel, 00: select matrix 0, 01: select matrix 1, otherwise select nothing ++//Bit 3:2, matrix coef idx selection, 00: select mat0, 01: select mat1, otherwise slect nothing ++//Bit 1 mat1 conversion matrix enable ++//Bit 0 mat0 conversion matrix enable ++#define VIU_OSD1_MATRIX_CTRL (0x1a90) ++#define P_VIU_OSD1_MATRIX_CTRL (volatile unsigned int *)((0x1a90 << 2) + 0xff900000) ++//Bit 28:16 coef00 ++//Bit 12:0 coef01 ++#define VIU_OSD1_MATRIX_COEF00_01 (0x1a91) ++#define P_VIU_OSD1_MATRIX_COEF00_01 (volatile unsigned int *)((0x1a91 << 2) + 0xff900000) ++//Bit 28:16 coef02 ++//Bit 12:0 coef10 ++#define VIU_OSD1_MATRIX_COEF02_10 (0x1a92) ++#define P_VIU_OSD1_MATRIX_COEF02_10 (volatile unsigned int *)((0x1a92 << 2) + 0xff900000) ++//Bit 28:16 coef11 ++//Bit 12:0 coef12 ++#define VIU_OSD1_MATRIX_COEF11_12 (0x1a93) ++#define P_VIU_OSD1_MATRIX_COEF11_12 (volatile unsigned int *)((0x1a93 << 2) + 0xff900000) ++//Bit 28:16 coef20 ++//Bit 12:0 coef21 ++#define VIU_OSD1_MATRIX_COEF20_21 (0x1a94) ++#define P_VIU_OSD1_MATRIX_COEF20_21 (volatile unsigned int *)((0x1a94 << 2) + 0xff900000) ++//Bit 31:30 mat_clmod ++//Bit 18:16 mat_convrs ++//Bit 12:0 mat_coef42 ++#define VIU_OSD1_MATRIX_COLMOD_COEF42 (0x1a95) ++#define P_VIU_OSD1_MATRIX_COLMOD_COEF42 (volatile unsigned int *)((0x1a95 << 2) + 0xff900000) ++//Bit 26:16 offset0 ++//Bit 10:0 offset1 ++#define VIU_OSD1_MATRIX_OFFSET0_1 (0x1a96) ++#define P_VIU_OSD1_MATRIX_OFFSET0_1 (volatile unsigned int *)((0x1a96 << 2) + 0xff900000) ++//Bit 10:0 offset2 ++#define VIU_OSD1_MATRIX_OFFSET2 (0x1a97) ++#define P_VIU_OSD1_MATRIX_OFFSET2 (volatile unsigned int *)((0x1a97 << 2) + 0xff900000) ++//Bit 26:16 pre_offset0 ++//Bit 10:0 pre_offset1 ++#define VIU_OSD1_MATRIX_PRE_OFFSET0_1 (0x1a98) ++#define P_VIU_OSD1_MATRIX_PRE_OFFSET0_1 (volatile unsigned int *)((0x1a98 << 2) + 0xff900000) ++//Bit 10:0 pre_offset2 ++#define VIU_OSD1_MATRIX_PRE_OFFSET2 (0x1a99) ++#define P_VIU_OSD1_MATRIX_PRE_OFFSET2 (volatile unsigned int *)((0x1a99 << 2) + 0xff900000) ++//Read only ++//Bit 29:20 component 0 ++//Bit 19:10 component 1 ++//Bit 9:0 component 2 ++#define VIU_OSD1_MATRIX_PROBE_COLOR (0x1a9a) ++#define P_VIU_OSD1_MATRIX_PROBE_COLOR (volatile unsigned int *)((0x1a9a << 2) + 0xff900000) ++//Bit 23:16 component 0 ++//Bit 15:8 component 1 ++//Bit 7:0 component 2 ++#define VIU_OSD1_MATRIX_HL_COLOR (0x1a9b) ++#define P_VIU_OSD1_MATRIX_HL_COLOR (volatile unsigned int *)((0x1a9b << 2) + 0xff900000) ++//28:16 probe x, postion ++//12:0 probe y, position ++#define VIU_OSD1_MATRIX_PROBE_POS (0x1a9c) ++#define P_VIU_OSD1_MATRIX_PROBE_POS (volatile unsigned int *)((0x1a9c << 2) + 0xff900000) ++//Bit 28:16 coef22 ++//Bit 12:0 coef30 ++#define VIU_OSD1_MATRIX_COEF22_30 (0x1a9d) ++#define P_VIU_OSD1_MATRIX_COEF22_30 (volatile unsigned int *)((0x1a9d << 2) + 0xff900000) ++//Bit 28:16 coef31 ++//Bit 12:0 coef32 ++#define VIU_OSD1_MATRIX_COEF31_32 (0x1a9e) ++#define P_VIU_OSD1_MATRIX_COEF31_32 (volatile unsigned int *)((0x1a9e << 2) + 0xff900000) ++//Bit 28:16 coef40 ++//Bit 12:0 coef41 ++#define VIU_OSD1_MATRIX_COEF40_41 (0x1a9f) ++#define P_VIU_OSD1_MATRIX_COEF40_41 (volatile unsigned int *)((0x1a9f << 2) + 0xff900000) ++//Bit 31:27 for all [31] for all eotf enable,[30] for matrix3x3 enable, [29:27] for eotf_ch0~3 ++//Bit 17:6 for clock gating ++//Bit 5:4 pscale_mode ch2 ++//Bit 3:2 pscale_mode ch1 ++//Bit 1:0 pscale_mode ch0 ++#define VIU_OSD1_EOTF_CTL (0x1ad4) ++#define P_VIU_OSD1_EOTF_CTL (volatile unsigned int *)((0x1ad4 << 2) + 0xff900000) ++//Bit 28:16 coef00 ++//Bit 12:0 coef01 ++#define VIU_OSD1_EOTF_COEF00_01 (0x1ad5) ++#define P_VIU_OSD1_EOTF_COEF00_01 (volatile unsigned int *)((0x1ad5 << 2) + 0xff900000) ++//Bit 28:16 coef02 ++//Bit 12:0 coef10 ++#define VIU_OSD1_EOTF_COEF02_10 (0x1ad6) ++#define P_VIU_OSD1_EOTF_COEF02_10 (volatile unsigned int *)((0x1ad6 << 2) + 0xff900000) ++//Bit 28:16 coef11 ++//Bit 12:0 coef12 ++#define VIU_OSD1_EOTF_COEF11_12 (0x1ad7) ++#define P_VIU_OSD1_EOTF_COEF11_12 (volatile unsigned int *)((0x1ad7 << 2) + 0xff900000) ++//Bit 28:16 coef20 ++//Bit 12:0 coef21 ++#define VIU_OSD1_EOTF_COEF20_21 (0x1ad8) ++#define P_VIU_OSD1_EOTF_COEF20_21 (volatile unsigned int *)((0x1ad8 << 2) + 0xff900000) ++//Bit 28:16 coef22 ++//Bit 2:0 coef_rs ++#define VIU_OSD1_EOTF_COEF22_RS (0x1ad9) ++#define P_VIU_OSD1_EOTF_COEF22_RS (volatile unsigned int *)((0x1ad9 << 2) + 0xff900000) ++#define VIU_OSD1_EOTF_LUT_ADDR_PORT (0x1ada) ++#define P_VIU_OSD1_EOTF_LUT_ADDR_PORT (volatile unsigned int *)((0x1ada << 2) + 0xff900000) ++#define VIU_OSD1_EOTF_LUT_DATA_PORT (0x1adb) ++#define P_VIU_OSD1_EOTF_LUT_DATA_PORT (volatile unsigned int *)((0x1adb << 2) + 0xff900000) ++//Bit 31:29 for OETF ch0~ch2 ++//Bit 21:12 for clock gating ++//Bit 11:8 for oetf_scl_ch2 ++//Bit 7:4 for oetf_scl_ch1 ++//Bit 3:0 for oetf_scl_ch0 ++#define VIU_OSD1_OETF_CTL (0x1adc) ++#define P_VIU_OSD1_OETF_CTL (volatile unsigned int *)((0x1adc << 2) + 0xff900000) ++#define VIU_OSD1_OETF_LUT_ADDR_PORT (0x1add) ++#define P_VIU_OSD1_OETF_LUT_ADDR_PORT (volatile unsigned int *)((0x1add << 2) + 0xff900000) ++#define VIU_OSD1_OETF_LUT_DATA_PORT (0x1ade) ++#define P_VIU_OSD1_OETF_LUT_DATA_PORT (volatile unsigned int *)((0x1ade << 2) + 0xff900000) ++#define VIU_OSD1_OETF_3X3_OFST_0 (0x1aa0) ++#define P_VIU_OSD1_OETF_3X3_OFST_0 (volatile unsigned int *)((0x1aa0 << 2) + 0xff900000) ++#define VIU_OSD1_OETF_3X3_OFST_1 (0x1aa1) ++#define P_VIU_OSD1_OETF_3X3_OFST_1 (volatile unsigned int *)((0x1aa1 << 2) + 0xff900000) ++//------------------------------------------------------------------------------ ++// OSD2 registers ++//------------------------------------------------------------------------------ ++// Bit 31 Reserved ++// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics; ++// 0=use gated clock for low power. ++// Bit 29 R, test_rd_dsr ++// Bit 28 R, osd_done ++// Bit 27:24 R, osd_blk_mode ++// Bit 23:22 R, osd_blk_ptr ++// Bit 21 R, osd_enable ++// ++// Bit 20:12 RW, global_alpha ++// Bit 11 RW, test_rd_en ++// Bit 10 RW, hl2_en ++// Bit 9 RW, hl1_en ++// Bit 8: 5 RW, ctrl_mtch_y ++// Bit 4 RW, ctrl_422to444 ++// Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable; ++// Bit 1 to enable block 1, and so on. ++#define VIU_OSD2_CTRL_STAT (0x1a30) ++#define P_VIU_OSD2_CTRL_STAT (volatile unsigned int *)((0x1a30 << 2) + 0xff900000) ++// Bit 31:26 Reserved ++// Bit 25:16 R, fifo_count ++// Bit 15 Reserved ++// Bit 14 RW, replaced_alpha_en ++// Bit 13: 6 RW, replaced_alpha ++// Bit 5: 4 RW, hold_fifo_lines[6:5] ++// Bit 3 RW, rgb2yuv_full_range ++// Bit 2 RW, alpha_9b_mode ++// Bit 1 RW, reserved ++// Bit 0 RW, color_expand_mode ++#define VIU_OSD2_CTRL_STAT2 (0x1a4d) ++#define P_VIU_OSD2_CTRL_STAT2 (volatile unsigned int *)((0x1a4d << 2) + 0xff900000) ++// Bit 31: 9 Reserved ++// Bit 8 RW, 0 = Write LUT, 1 = Read LUT ++// Bit 7: 0 RW, lut_addr ++#define VIU_OSD2_COLOR_ADDR (0x1a31) ++#define P_VIU_OSD2_COLOR_ADDR (volatile unsigned int *)((0x1a31 << 2) + 0xff900000) ++// Bit 31:24 RW, Y or R ++// Bit 23:16 RW, Cb or G ++// Bit 15: 8 RW, Cr or B ++// Bit 7: 0 RW, Alpha ++#define VIU_OSD2_COLOR (0x1a32) ++#define P_VIU_OSD2_COLOR (volatile unsigned int *)((0x1a32 << 2) + 0xff900000) ++// Bit 31:28 Reserved ++// Bit 27:16 RW, hl[1-2]_h/v_start ++// Bit 15:12 Reserved ++// Bit 11: 0 RW, hl[1-2]_h/v_end ++#define VIU_OSD2_HL1_H_START_END (0x1a33) ++#define P_VIU_OSD2_HL1_H_START_END (volatile unsigned int *)((0x1a33 << 2) + 0xff900000) ++#define VIU_OSD2_HL1_V_START_END (0x1a34) ++#define P_VIU_OSD2_HL1_V_START_END (volatile unsigned int *)((0x1a34 << 2) + 0xff900000) ++#define VIU_OSD2_HL2_H_START_END (0x1a35) ++#define P_VIU_OSD2_HL2_H_START_END (volatile unsigned int *)((0x1a35 << 2) + 0xff900000) ++#define VIU_OSD2_HL2_V_START_END (0x1a36) ++#define P_VIU_OSD2_HL2_V_START_END (volatile unsigned int *)((0x1a36 << 2) + 0xff900000) ++// Bit 31:24 RW, Y or R ++// Bit 23:16 RW, Cb or G ++// Bit 15: 8 RW, Cr or B ++// Bit 7: 0 RW, Alpha ++#define VIU_OSD2_TCOLOR_AG0 (0x1a37) ++#define P_VIU_OSD2_TCOLOR_AG0 (volatile unsigned int *)((0x1a37 << 2) + 0xff900000) ++#define VIU_OSD2_TCOLOR_AG1 (0x1a38) ++#define P_VIU_OSD2_TCOLOR_AG1 (volatile unsigned int *)((0x1a38 << 2) + 0xff900000) ++#define VIU_OSD2_TCOLOR_AG2 (0x1a39) ++#define P_VIU_OSD2_TCOLOR_AG2 (volatile unsigned int *)((0x1a39 << 2) + 0xff900000) ++#define VIU_OSD2_TCOLOR_AG3 (0x1a3a) ++#define P_VIU_OSD2_TCOLOR_AG3 (volatile unsigned int *)((0x1a3a << 2) + 0xff900000) ++// Bit 31:24 Reserved ++// Bit 23:16 RW, tbl_addr ++// Bit 15 RW, little_endian: 0=big endian, 1=little endian ++// Bit 14 RW, rpt_y ++// Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous ++// pixel; 11=Interpolate with the average value ++// between previous and next pixel. ++// Bit 11: 8 RW, osd_blk_mode ++// Bit 7 RW, rgb_en ++// Bit 6 RW, tc_alpha_en ++// Bit 5: 2 RW, color_matrix ++// Bit 1 RW, interlace_en ++// Bit 0 RW, interlace_sel_odd ++#define VIU_OSD2_BLK0_CFG_W0 (0x1a3b) ++#define P_VIU_OSD2_BLK0_CFG_W0 (volatile unsigned int *)((0x1a3b << 2) + 0xff900000) ++#define VIU_OSD2_BLK1_CFG_W0 (0x1a3f) ++#define P_VIU_OSD2_BLK1_CFG_W0 (volatile unsigned int *)((0x1a3f << 2) + 0xff900000) ++#define VIU_OSD2_BLK2_CFG_W0 (0x1a43) ++#define P_VIU_OSD2_BLK2_CFG_W0 (volatile unsigned int *)((0x1a43 << 2) + 0xff900000) ++#define VIU_OSD2_BLK3_CFG_W0 (0x1a47) ++#define P_VIU_OSD2_BLK3_CFG_W0 (volatile unsigned int *)((0x1a47 << 2) + 0xff900000) ++// Bit 31:29 Reserved ++// Bit 28:16 RW, x_end ++// Bit 15:13 Reserved ++// Bit 12: 0 RW, x_start ++#define VIU_OSD2_BLK0_CFG_W1 (0x1a3c) ++#define P_VIU_OSD2_BLK0_CFG_W1 (volatile unsigned int *)((0x1a3c << 2) + 0xff900000) ++#define VIU_OSD2_BLK1_CFG_W1 (0x1a40) ++#define P_VIU_OSD2_BLK1_CFG_W1 (volatile unsigned int *)((0x1a40 << 2) + 0xff900000) ++#define VIU_OSD2_BLK2_CFG_W1 (0x1a44) ++#define P_VIU_OSD2_BLK2_CFG_W1 (volatile unsigned int *)((0x1a44 << 2) + 0xff900000) ++#define VIU_OSD2_BLK3_CFG_W1 (0x1a48) ++#define P_VIU_OSD2_BLK3_CFG_W1 (volatile unsigned int *)((0x1a48 << 2) + 0xff900000) ++// Bit 31:29 Reserved ++// Bit 28:16 RW, y_end ++// Bit 15:13 Reserved ++// Bit 12: 0 RW, y_start ++#define VIU_OSD2_BLK0_CFG_W2 (0x1a3d) ++#define P_VIU_OSD2_BLK0_CFG_W2 (volatile unsigned int *)((0x1a3d << 2) + 0xff900000) ++#define VIU_OSD2_BLK1_CFG_W2 (0x1a41) ++#define P_VIU_OSD2_BLK1_CFG_W2 (volatile unsigned int *)((0x1a41 << 2) + 0xff900000) ++#define VIU_OSD2_BLK2_CFG_W2 (0x1a45) ++#define P_VIU_OSD2_BLK2_CFG_W2 (volatile unsigned int *)((0x1a45 << 2) + 0xff900000) ++#define VIU_OSD2_BLK3_CFG_W2 (0x1a49) ++#define P_VIU_OSD2_BLK3_CFG_W2 (volatile unsigned int *)((0x1a49 << 2) + 0xff900000) ++// Bit 31:28 Reserved ++// Bit 27:16 RW, h_end ++// Bit 15:12 Reserved ++// Bit 11: 0 RW, h_start ++#define VIU_OSD2_BLK0_CFG_W3 (0x1a3e) ++#define P_VIU_OSD2_BLK0_CFG_W3 (volatile unsigned int *)((0x1a3e << 2) + 0xff900000) ++#define VIU_OSD2_BLK1_CFG_W3 (0x1a42) ++#define P_VIU_OSD2_BLK1_CFG_W3 (volatile unsigned int *)((0x1a42 << 2) + 0xff900000) ++#define VIU_OSD2_BLK2_CFG_W3 (0x1a46) ++#define P_VIU_OSD2_BLK2_CFG_W3 (volatile unsigned int *)((0x1a46 << 2) + 0xff900000) ++#define VIU_OSD2_BLK3_CFG_W3 (0x1a4a) ++#define P_VIU_OSD2_BLK3_CFG_W3 (volatile unsigned int *)((0x1a4a << 2) + 0xff900000) ++// Bit 31:28 Reserved ++// Bit 27:16 RW, v_end ++// Bit 15:12 Reserved ++// Bit 11: 0 RW, v_start ++#define VIU_OSD2_BLK0_CFG_W4 (0x1a64) ++#define P_VIU_OSD2_BLK0_CFG_W4 (volatile unsigned int *)((0x1a64 << 2) + 0xff900000) ++#define VIU_OSD2_BLK1_CFG_W4 (0x1a65) ++#define P_VIU_OSD2_BLK1_CFG_W4 (volatile unsigned int *)((0x1a65 << 2) + 0xff900000) ++#define VIU_OSD2_BLK2_CFG_W4 (0x1a66) ++#define P_VIU_OSD2_BLK2_CFG_W4 (volatile unsigned int *)((0x1a66 << 2) + 0xff900000) ++#define VIU_OSD2_BLK3_CFG_W4 (0x1a67) ++#define P_VIU_OSD2_BLK3_CFG_W4 (volatile unsigned int *)((0x1a67 << 2) + 0xff900000) ++// Bit 31 RW, burst_len_sel[2] of [2:0] ++// Bit 30 RW, byte_swap: In addition to endian control, further define ++// whether to swap upper and lower byte within a 16-bit mem word. ++// 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]} ++// Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word ++// Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif ++// Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved ++// Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT ++// Bit 19 R, fifo_overflow ++// ++// Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8. ++// Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128. ++// Bit 9: 5 RW, hold_fifo_lines[4:0] ++// Bit 4 RW, clear_err: one pulse to clear fifo_overflow ++// Bit 3 RW, fifo_sync_rst ++// Bit 2: 1 RW, endian ++// Bit 0 RW, urgent ++#define VIU_OSD2_FIFO_CTRL_STAT (0x1a4b) ++#define P_VIU_OSD2_FIFO_CTRL_STAT (volatile unsigned int *)((0x1a4b << 2) + 0xff900000) ++// Bit 31:24 R, Y or R ++// Bit 23:16 R, Cb or G ++// Bit 15: 8 R, Cr or B ++// Bit 7: 0 R, Output Alpha[8:1] ++#define VIU_OSD2_TEST_RDDATA (0x1a4c) ++#define P_VIU_OSD2_TEST_RDDATA (volatile unsigned int *)((0x1a4c << 2) + 0xff900000) ++// Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate. ++// Bit 12: 0 RW, effective FIFO size when prot_en=1. ++#define VIU_OSD2_PROT_CTRL (0x1a4e) ++#define P_VIU_OSD2_PROT_CTRL (volatile unsigned int *)((0x1a4e << 2) + 0xff900000) ++//------------------------------------------------------------------------------ ++// VD1 path ++//------------------------------------------------------------------------------ ++#define VD1_IF0_GEN_REG (0x1a50) ++#define P_VD1_IF0_GEN_REG (volatile unsigned int *)((0x1a50 << 2) + 0xff900000) ++#define VD1_IF0_CANVAS0 (0x1a51) ++#define P_VD1_IF0_CANVAS0 (volatile unsigned int *)((0x1a51 << 2) + 0xff900000) ++#define VD1_IF0_CANVAS1 (0x1a52) ++#define P_VD1_IF0_CANVAS1 (volatile unsigned int *)((0x1a52 << 2) + 0xff900000) ++#define VD1_IF0_LUMA_X0 (0x1a53) ++#define P_VD1_IF0_LUMA_X0 (volatile unsigned int *)((0x1a53 << 2) + 0xff900000) ++#define VD1_IF0_LUMA_Y0 (0x1a54) ++#define P_VD1_IF0_LUMA_Y0 (volatile unsigned int *)((0x1a54 << 2) + 0xff900000) ++#define VD1_IF0_CHROMA_X0 (0x1a55) ++#define P_VD1_IF0_CHROMA_X0 (volatile unsigned int *)((0x1a55 << 2) + 0xff900000) ++#define VD1_IF0_CHROMA_Y0 (0x1a56) ++#define P_VD1_IF0_CHROMA_Y0 (volatile unsigned int *)((0x1a56 << 2) + 0xff900000) ++#define VD1_IF0_LUMA_X1 (0x1a57) ++#define P_VD1_IF0_LUMA_X1 (volatile unsigned int *)((0x1a57 << 2) + 0xff900000) ++#define VD1_IF0_LUMA_Y1 (0x1a58) ++#define P_VD1_IF0_LUMA_Y1 (volatile unsigned int *)((0x1a58 << 2) + 0xff900000) ++#define VD1_IF0_CHROMA_X1 (0x1a59) ++#define P_VD1_IF0_CHROMA_X1 (volatile unsigned int *)((0x1a59 << 2) + 0xff900000) ++#define VD1_IF0_CHROMA_Y1 (0x1a5a) ++#define P_VD1_IF0_CHROMA_Y1 (volatile unsigned int *)((0x1a5a << 2) + 0xff900000) ++#define VD1_IF0_RPT_LOOP (0x1a5b) ++#define P_VD1_IF0_RPT_LOOP (volatile unsigned int *)((0x1a5b << 2) + 0xff900000) ++#define VD1_IF0_LUMA0_RPT_PAT (0x1a5c) ++#define P_VD1_IF0_LUMA0_RPT_PAT (volatile unsigned int *)((0x1a5c << 2) + 0xff900000) ++#define VD1_IF0_CHROMA0_RPT_PAT (0x1a5d) ++#define P_VD1_IF0_CHROMA0_RPT_PAT (volatile unsigned int *)((0x1a5d << 2) + 0xff900000) ++#define VD1_IF0_LUMA1_RPT_PAT (0x1a5e) ++#define P_VD1_IF0_LUMA1_RPT_PAT (volatile unsigned int *)((0x1a5e << 2) + 0xff900000) ++#define VD1_IF0_CHROMA1_RPT_PAT (0x1a5f) ++#define P_VD1_IF0_CHROMA1_RPT_PAT (volatile unsigned int *)((0x1a5f << 2) + 0xff900000) ++#define VD1_IF0_LUMA_PSEL (0x1a60) ++#define P_VD1_IF0_LUMA_PSEL (volatile unsigned int *)((0x1a60 << 2) + 0xff900000) ++#define VD1_IF0_CHROMA_PSEL (0x1a61) ++#define P_VD1_IF0_CHROMA_PSEL (volatile unsigned int *)((0x1a61 << 2) + 0xff900000) ++#define VD1_IF0_DUMMY_PIXEL (0x1a62) ++#define P_VD1_IF0_DUMMY_PIXEL (volatile unsigned int *)((0x1a62 << 2) + 0xff900000) ++#define VD1_IF0_LUMA_FIFO_SIZE (0x1a63) ++#define P_VD1_IF0_LUMA_FIFO_SIZE (volatile unsigned int *)((0x1a63 << 2) + 0xff900000) ++#define VD1_IF0_RANGE_MAP_Y (0x1a6a) ++#define P_VD1_IF0_RANGE_MAP_Y (volatile unsigned int *)((0x1a6a << 2) + 0xff900000) ++#define VD1_IF0_RANGE_MAP_CB (0x1a6b) ++#define P_VD1_IF0_RANGE_MAP_CB (volatile unsigned int *)((0x1a6b << 2) + 0xff900000) ++#define VD1_IF0_RANGE_MAP_CR (0x1a6c) ++#define P_VD1_IF0_RANGE_MAP_CR (volatile unsigned int *)((0x1a6c << 2) + 0xff900000) ++#define VD1_IF0_GEN_REG2 (0x1a6d) ++#define P_VD1_IF0_GEN_REG2 (volatile unsigned int *)((0x1a6d << 2) + 0xff900000) ++#define VD1_IF0_PROT_CNTL (0x1a6e) ++#define P_VD1_IF0_PROT_CNTL (volatile unsigned int *)((0x1a6e << 2) + 0xff900000) ++#define VD1_IF0_URGENT_CTRL (0x1a6f) ++#define P_VD1_IF0_URGENT_CTRL (volatile unsigned int *)((0x1a6f << 2) + 0xff900000) ++//Bit 31 it true, disable clock, otherwise enable clock ++//Bit 30 soft rst bit ++//Bit 28 if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation ++//Bit 27:24 horizontal formatter initial phase ++//Bit 23 horizontal formatter repeat pixel 0 enable ++//Bit 22:21 horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1 ++//Bit 20 horizontal formatter enable ++//Bit 19 if true, always use phase0 while vertical formater, meaning always ++// repeat data, no interpolation ++//Bit 18 if true, disable vertical formatter chroma repeat last line ++//Bit 17 veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable ++//Bit 16 veritcal formatter repeat line 0 enable ++//Bit 15:12 vertical formatter skip line num at the beginning ++//Bit 11:8 vertical formatter initial phase ++//Bit 7:1 vertical formatter phase step (3.4) ++//Bit 0 vertical formatter enable ++#define VIU_VD1_FMT_CTRL (0x1a68) ++#define P_VIU_VD1_FMT_CTRL (volatile unsigned int *)((0x1a68 << 2) + 0xff900000) ++//Bit 27:16 horizontal formatter width ++//Bit 11:0 vertical formatter width ++#define VIU_VD1_FMT_W (0x1a69) ++#define P_VIU_VD1_FMT_W (volatile unsigned int *)((0x1a69 << 2) + 0xff900000) ++//------------------------------------------------------------------------------ ++// VD2 path ++//------------------------------------------------------------------------------ ++#define VD2_IF0_GEN_REG (0x1a70) ++#define P_VD2_IF0_GEN_REG (volatile unsigned int *)((0x1a70 << 2) + 0xff900000) ++#define VD2_IF0_CANVAS0 (0x1a71) ++#define P_VD2_IF0_CANVAS0 (volatile unsigned int *)((0x1a71 << 2) + 0xff900000) ++#define VD2_IF0_CANVAS1 (0x1a72) ++#define P_VD2_IF0_CANVAS1 (volatile unsigned int *)((0x1a72 << 2) + 0xff900000) ++#define VD2_IF0_LUMA_X0 (0x1a73) ++#define P_VD2_IF0_LUMA_X0 (volatile unsigned int *)((0x1a73 << 2) + 0xff900000) ++#define VD2_IF0_LUMA_Y0 (0x1a74) ++#define P_VD2_IF0_LUMA_Y0 (volatile unsigned int *)((0x1a74 << 2) + 0xff900000) ++#define VD2_IF0_CHROMA_X0 (0x1a75) ++#define P_VD2_IF0_CHROMA_X0 (volatile unsigned int *)((0x1a75 << 2) + 0xff900000) ++#define VD2_IF0_CHROMA_Y0 (0x1a76) ++#define P_VD2_IF0_CHROMA_Y0 (volatile unsigned int *)((0x1a76 << 2) + 0xff900000) ++#define VD2_IF0_LUMA_X1 (0x1a77) ++#define P_VD2_IF0_LUMA_X1 (volatile unsigned int *)((0x1a77 << 2) + 0xff900000) ++#define VD2_IF0_LUMA_Y1 (0x1a78) ++#define P_VD2_IF0_LUMA_Y1 (volatile unsigned int *)((0x1a78 << 2) + 0xff900000) ++#define VD2_IF0_CHROMA_X1 (0x1a79) ++#define P_VD2_IF0_CHROMA_X1 (volatile unsigned int *)((0x1a79 << 2) + 0xff900000) ++#define VD2_IF0_CHROMA_Y1 (0x1a7a) ++#define P_VD2_IF0_CHROMA_Y1 (volatile unsigned int *)((0x1a7a << 2) + 0xff900000) ++#define VD2_IF0_RPT_LOOP (0x1a7b) ++#define P_VD2_IF0_RPT_LOOP (volatile unsigned int *)((0x1a7b << 2) + 0xff900000) ++#define VD2_IF0_LUMA0_RPT_PAT (0x1a7c) ++#define P_VD2_IF0_LUMA0_RPT_PAT (volatile unsigned int *)((0x1a7c << 2) + 0xff900000) ++#define VD2_IF0_CHROMA0_RPT_PAT (0x1a7d) ++#define P_VD2_IF0_CHROMA0_RPT_PAT (volatile unsigned int *)((0x1a7d << 2) + 0xff900000) ++#define VD2_IF0_LUMA1_RPT_PAT (0x1a7e) ++#define P_VD2_IF0_LUMA1_RPT_PAT (volatile unsigned int *)((0x1a7e << 2) + 0xff900000) ++#define VD2_IF0_CHROMA1_RPT_PAT (0x1a7f) ++#define P_VD2_IF0_CHROMA1_RPT_PAT (volatile unsigned int *)((0x1a7f << 2) + 0xff900000) ++#define VD2_IF0_LUMA_PSEL (0x1a80) ++#define P_VD2_IF0_LUMA_PSEL (volatile unsigned int *)((0x1a80 << 2) + 0xff900000) ++#define VD2_IF0_CHROMA_PSEL (0x1a81) ++#define P_VD2_IF0_CHROMA_PSEL (volatile unsigned int *)((0x1a81 << 2) + 0xff900000) ++#define VD2_IF0_DUMMY_PIXEL (0x1a82) ++#define P_VD2_IF0_DUMMY_PIXEL (volatile unsigned int *)((0x1a82 << 2) + 0xff900000) ++#define VD2_IF0_LUMA_FIFO_SIZE (0x1a83) ++#define P_VD2_IF0_LUMA_FIFO_SIZE (volatile unsigned int *)((0x1a83 << 2) + 0xff900000) ++#define VD2_IF0_RANGE_MAP_Y (0x1a8a) ++#define P_VD2_IF0_RANGE_MAP_Y (volatile unsigned int *)((0x1a8a << 2) + 0xff900000) ++#define VD2_IF0_RANGE_MAP_CB (0x1a8b) ++#define P_VD2_IF0_RANGE_MAP_CB (volatile unsigned int *)((0x1a8b << 2) + 0xff900000) ++#define VD2_IF0_RANGE_MAP_CR (0x1a8c) ++#define P_VD2_IF0_RANGE_MAP_CR (volatile unsigned int *)((0x1a8c << 2) + 0xff900000) ++#define VD2_IF0_GEN_REG2 (0x1a8d) ++#define P_VD2_IF0_GEN_REG2 (volatile unsigned int *)((0x1a8d << 2) + 0xff900000) ++#define VD2_IF0_PROT_CNTL (0x1a8e) ++#define P_VD2_IF0_PROT_CNTL (volatile unsigned int *)((0x1a8e << 2) + 0xff900000) ++#define VD2_IF0_URGENT_CTRL (0x1a8f) ++#define P_VD2_IF0_URGENT_CTRL (volatile unsigned int *)((0x1a8f << 2) + 0xff900000) ++//Bit 31 it true, disable clock, otherwise enable clock ++//Bit 30 soft rst bit ++//Bit 28 if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation ++//Bit 27:24 horizontal formatter initial phase ++//Bit 23 horizontal formatter repeat pixel 0 enable ++//Bit 22:21 horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1 ++//Bit 20 horizontal formatter enable ++//Bit 17 veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable ++//Bit 16 veritcal formatter repeat line 0 enable ++//Bit 15:12 vertical formatter skip line num at the beginning ++//Bit 11:8 vertical formatter initial phase ++//Bit 7:1 vertical formatter phase step (3.4) ++//Bit 0 vertical formatter enable ++#define VIU_VD2_FMT_CTRL (0x1a88) ++#define P_VIU_VD2_FMT_CTRL (volatile unsigned int *)((0x1a88 << 2) + 0xff900000) ++//Bit 27:16 horizontal formatter width ++//Bit 11:0 vertical formatter width ++#define VIU_VD2_FMT_W (0x1a89) ++#define P_VIU_VD2_FMT_W (volatile unsigned int *)((0x1a89 << 2) + 0xff900000) ++// //todo add comment ++#define LDIM_STTS_GCLK_CTRL0 (0x1ac0) ++#define P_LDIM_STTS_GCLK_CTRL0 (volatile unsigned int *)((0x1ac0 << 2) + 0xff900000) ++#define LDIM_STTS_CTRL0 (0x1ac1) ++#define P_LDIM_STTS_CTRL0 (volatile unsigned int *)((0x1ac1 << 2) + 0xff900000) ++#define LDIM_STTS_WIDTHM1_HEIGHTM1 (0x1ac2) ++#define P_LDIM_STTS_WIDTHM1_HEIGHTM1 (volatile unsigned int *)((0x1ac2 << 2) + 0xff900000) ++#define LDIM_STTS_MATRIX_COEF00_01 (0x1ac3) ++#define P_LDIM_STTS_MATRIX_COEF00_01 (volatile unsigned int *)((0x1ac3 << 2) + 0xff900000) ++#define LDIM_STTS_MATRIX_COEF02_10 (0x1ac4) ++#define P_LDIM_STTS_MATRIX_COEF02_10 (volatile unsigned int *)((0x1ac4 << 2) + 0xff900000) ++#define LDIM_STTS_MATRIX_COEF11_12 (0x1ac5) ++#define P_LDIM_STTS_MATRIX_COEF11_12 (volatile unsigned int *)((0x1ac5 << 2) + 0xff900000) ++#define LDIM_STTS_MATRIX_COEF20_21 (0x1ac6) ++#define P_LDIM_STTS_MATRIX_COEF20_21 (volatile unsigned int *)((0x1ac6 << 2) + 0xff900000) ++#define LDIM_STTS_MATRIX_COEF22 (0x1ac7) ++#define P_LDIM_STTS_MATRIX_COEF22 (volatile unsigned int *)((0x1ac7 << 2) + 0xff900000) ++#define LDIM_STTS_MATRIX_OFFSET0_1 (0x1ac8) ++#define P_LDIM_STTS_MATRIX_OFFSET0_1 (volatile unsigned int *)((0x1ac8 << 2) + 0xff900000) ++#define LDIM_STTS_MATRIX_OFFSET2 (0x1ac9) ++#define P_LDIM_STTS_MATRIX_OFFSET2 (volatile unsigned int *)((0x1ac9 << 2) + 0xff900000) ++#define LDIM_STTS_MATRIX_PRE_OFFSET0_1 (0x1aca) ++#define P_LDIM_STTS_MATRIX_PRE_OFFSET0_1 (volatile unsigned int *)((0x1aca << 2) + 0xff900000) ++#define LDIM_STTS_MATRIX_PRE_OFFSET2 (0x1acb) ++#define P_LDIM_STTS_MATRIX_PRE_OFFSET2 (volatile unsigned int *)((0x1acb << 2) + 0xff900000) ++#define LDIM_STTS_MATRIX_HL_COLOR (0x1acc) ++#define P_LDIM_STTS_MATRIX_HL_COLOR (volatile unsigned int *)((0x1acc << 2) + 0xff900000) ++#define LDIM_STTS_MATRIX_PROBE_POS (0x1acd) ++#define P_LDIM_STTS_MATRIX_PROBE_POS (volatile unsigned int *)((0x1acd << 2) + 0xff900000) ++// ++// //read only ++#define LDIM_STTS_MATRIX_PROBE_COLOR (0x1ace) ++#define P_LDIM_STTS_MATRIX_PROBE_COLOR (volatile unsigned int *)((0x1ace << 2) + 0xff900000) ++// ++// //Bit 31, local dimming statistic enable ++// //Bit 29, 1: output region histogram 16bit 0:output region histogram 20bit ++// //Bit 28, eol enable ++// //Bit 27:25, vertical line overlap number for max finding ++// //Bit 24:22, horizontal pixel overlap number, 0: 17 pix, 1: 9 pix, 2: 5 pix, 3: 3 pix, 4: 0 pix ++// //Bit 20, 1,2,1 low pass filter enable before max/hist statistic ++// //Bit 19:16, region H/V position index, refer to VDIN_LDIM_STTS_HIST_SET_REGION ++// //Bit 15:14, 1: region read index auto increase per block read finished to VDIN_LDIM_STTS_HIST_READ_REGION ++// // 2: region read index auto increase per read finished to VDIN_LDIM_STTS_HIST_READ_REGION ++// // 0/3: disable read index self increase ++// //Bit 13:8, region read sub index, which mux the hist & max-finding result to cbus port, refer to LDIM_STTS_HIST_READ_REGION ++// //Bit 6:0, region read index ++#define LDIM_STTS_HIST_REGION_IDX (0x1ad0) ++#define P_LDIM_STTS_HIST_REGION_IDX (volatile unsigned int *)((0x1ad0 << 2) + 0xff900000) ++//Bit 28:0, if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h0: read/write hvstart0 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h1: read/write hend01 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h2: read/write vend01 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h3: read/write hend23 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h4: read/write vend23 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h5: read/write hend45 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h6: read/write vend45 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'd7: read/write hend67 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h8: read/write vend67 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h9: read/write hend89 ++// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'ha: read/write vend89 ++// //hvstart0, Bit 28:16 row0 vstart, Bit 12:0 col0 hstart ++// //hend01, Bit 28:16 col1 hend, Bit 12:0 col0 hend ++// //vend01, Bit 28:16 row1 vend, Bit 12:0 row0 vend ++// //hend23, Bit 28:16 col3 hend, Bit 12:0 col2 hend ++// //vend23, Bit 28:16 row3 vend, Bit 12:0 row2 vend ++// //hend45, Bit 28:16 col5 hend, Bit 12:0 col4 hend ++// //vend45, Bit 28:16 row5 vend, Bit 12:0 row4 vend ++// //hend67, Bit 28:16 col7 hend, Bit 12:0 col6 hend ++// //vend67, Bit 28:16 row7 vend, Bit 12:0 row6 vend ++// //hend89, Bit 28:16 col9 hend, Bit 12:0 col8 hend ++// //vend89, Bit 28:16 row9 vend, Bit 12:0 row8 vend ++#define LDIM_STTS_HIST_SET_REGION (0x1ad1) ++#define P_LDIM_STTS_HIST_SET_REGION (volatile unsigned int *)((0x1ad1 << 2) + 0xff900000) ++// ++// //if LDIM_STTS_HIST_REGION_IDX[29] == 0, that is output hist with 20bit data. ++// //if LDIM_STTS_HIST_REGION_IDX[21] == 0, that is output 16hist bins in comp 0. ++// //output sequence as rd_sub_idx from 0~47: {max_comp2, comp0_hist0}, {max_comp1, comp0_hist1}, {max_comp0, comp0_hist2}, ++// // comp0_hist3 ... comp2_hist16 ++// //if LDIM_STTS_HIST_REGION_IDX[29] == 1, that is output hist with 16bit data. ++// //if LDIM_STTS_HIST_REGION_IDX[21] == 0, that is output 16hist bins in comp 0. ++// //output sequence as rd_sub_idx from 0~47: {max_comp2, max_comp1, max_comp0}, comp0_hist0, comp0_hist1, comp0_hist2 ++// // comp0_hist3 ... comp2_hist16 ++// //if LDIM_STTS_HIST_REGION_IDX[29] == 0, that is output hist with 20bit data. ++// //if LDIM_STTS_HIST_REGION_IDX[21] == 1, that is output 32hist bins in comp 0. ++// //output sequence as rd_sub_idx from 0~47: {max_comp2, max_comp1, max_comp0}, comp0_hist0, comp0_hist1, comp0_hist2 ++// // comp0_hist3 ...comp0_hist31 ... comp1_hist16 ++// ++#define LDIM_STTS_HIST_READ_REGION (0x1ad2) ++#define P_LDIM_STTS_HIST_READ_REGION (volatile unsigned int *)((0x1ad2 << 2) + 0xff900000) ++#define LDIM_STTS_HIST_START_RD_REGION (0x1ad3) ++#define P_LDIM_STTS_HIST_START_RD_REGION (volatile unsigned int *)((0x1ad3 << 2) + 0xff900000) ++// //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di if1 chroma path ++// //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di if1 luma path ++// `define DI_IF1_URGENT_CTRL 8'ha3 ++// //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path ++// //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path ++// `define DI_INP_URGENT_CTRL 8'ha4 ++// //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di mem chroma path ++// //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di mem luma path ++// `define DI_MEM_URGENT_CTRL 8'ha5 ++// //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di chan2 chroma path ++// //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di chan2 luma path ++// `define DI_CHAN2_URGENT_CTRL 8'ha6 ++#define VD1_IF0_GEN_REG3 (0x1aa7) ++#define P_VD1_IF0_GEN_REG3 (volatile unsigned int *)((0x1aa7 << 2) + 0xff900000) ++//bit 31:1, reversed ++//bit 0, cntl_64bit_rev ++#define VD2_IF0_GEN_REG3 (0x1aa8) ++#define P_VD2_IF0_GEN_REG3 (volatile unsigned int *)((0x1aa8 << 2) + 0xff900000) ++//bit 31:1, reversed ++//bit 0, cntl_64bit_rev ++#define OSD_BLENDO_H_START_END (0x1aa9) ++#define P_OSD_BLENDO_H_START_END (volatile unsigned int *)((0x1aa9 << 2) + 0xff900000) ++//OSD blending output horizontal start and end ++//Bit 28:16 start ++//Bit 12:0 end ++#define OSD_BLENDO_V_START_END (0x1aaa) ++#define P_OSD_BLENDO_V_START_END (volatile unsigned int *)((0x1aaa << 2) + 0xff900000) ++//OSD blending output vertical start and end ++//Bit 28:16 start ++//Bit 12:0 end ++#define OSD_BLEND_GEN_CTRL0 (0x1aab) ++#define P_OSD_BLEND_GEN_CTRL0 (volatile unsigned int *)((0x1aab << 2) + 0xff900000) ++//Bit 31:23 const_out_alpha ++//Bit 22:14 const_op_alpha ++//Bit 13 if true, OSD2 foreground otherwise OSD1 foreground ++//Bit 12 OSD BLENDing enable ++//Bit 9:8 alpha_op_sel 00: output alpha use osd1_alpha, 01: use osd2_alpha, else use const_out_alpha ++//Bit 5:4 color_op_sel 00: use osd1_alpha, 01: use osd2_alpha, else use const_op_alpha ++//Bit 1 OSD2 enable ++//Bit 0 OSD1 enable ++#define OSD_BLEND_GEN_CTRL1 (0x1aac) ++#define P_OSD_BLEND_GEN_CTRL1 (volatile unsigned int *)((0x1aac << 2) + 0xff900000) ++//Bit 31 osd1_alpha_premult, if true, osd1 alpha is premultipiled ++//Bit 30 osd2_alpha_premult, if true, osd2 alpha is premultipiled ++//Bit 23:16 osd blending hold lines ++//Bit 13:0 osd blending h_size ++#define OSD_BLEND_DUMMY_DATA (0x1aad) ++#define P_OSD_BLEND_DUMMY_DATA (volatile unsigned int *)((0x1aad << 2) + 0xff900000) ++//Bit 29:20 Y/R ++//Bit 19:10 CB/G ++//Bit 9:0 Cr/B ++#define OSD_BLEND_CURRENT_XY (0x1aae) ++#define P_OSD_BLEND_CURRENT_XY (volatile unsigned int *)((0x1aae << 2) + 0xff900000) ++//Bit 28:16 current_x ++//Bit 12:0 current_y ++//Bit 7, highlight_en ++//Bit 6 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix ++//Bit 5:4 probe_sel, 00: select matrix 0, 01: select matrix 1, otherwise select nothing ++//Bit 3:2, matrix coef idx selection, 00: select mat0, 01: select mat1, otherwise slect nothing ++//Bit 1 mat1 conversion matrix enable ++//Bit 0 mat0 conversion matrix enable ++#define VIU_OSD2_MATRIX_CTRL (0x1ab0) ++#define P_VIU_OSD2_MATRIX_CTRL (volatile unsigned int *)((0x1ab0 << 2) + 0xff900000) ++//Bit 28:16 coef00 ++//Bit 12:0 coef01 ++#define VIU_OSD2_MATRIX_COEF00_01 (0x1ab1) ++#define P_VIU_OSD2_MATRIX_COEF00_01 (volatile unsigned int *)((0x1ab1 << 2) + 0xff900000) ++//Bit 28:16 coef02 ++//Bit 12:0 coef10 ++#define VIU_OSD2_MATRIX_COEF02_10 (0x1ab2) ++#define P_VIU_OSD2_MATRIX_COEF02_10 (volatile unsigned int *)((0x1ab2 << 2) + 0xff900000) ++//Bit 28:16 coef11 ++//Bit 12:0 coef12 ++#define VIU_OSD2_MATRIX_COEF11_12 (0x1ab3) ++#define P_VIU_OSD2_MATRIX_COEF11_12 (volatile unsigned int *)((0x1ab3 << 2) + 0xff900000) ++//Bit 28:16 coef20 ++//Bit 12:0 coef21 ++#define VIU_OSD2_MATRIX_COEF20_21 (0x1ab4) ++#define P_VIU_OSD2_MATRIX_COEF20_21 (volatile unsigned int *)((0x1ab4 << 2) + 0xff900000) ++#define VIU_OSD2_MATRIX_COEF22 (0x1ab5) ++#define P_VIU_OSD2_MATRIX_COEF22 (volatile unsigned int *)((0x1ab5 << 2) + 0xff900000) ++//Bit 26:16 offset0 ++//Bit 10:0 offset1 ++#define VIU_OSD2_MATRIX_OFFSET0_1 (0x1ab6) ++#define P_VIU_OSD2_MATRIX_OFFSET0_1 (volatile unsigned int *)((0x1ab6 << 2) + 0xff900000) ++//Bit 10:0 offset2 ++#define VIU_OSD2_MATRIX_OFFSET2 (0x1ab7) ++#define P_VIU_OSD2_MATRIX_OFFSET2 (volatile unsigned int *)((0x1ab7 << 2) + 0xff900000) ++//Bit 26:16 pre_offset0 ++//Bit 10:0 pre_offset1 ++#define VIU_OSD2_MATRIX_PRE_OFFSET0_1 (0x1ab8) ++#define P_VIU_OSD2_MATRIX_PRE_OFFSET0_1 (volatile unsigned int *)((0x1ab8 << 2) + 0xff900000) ++//Bit 10:0 pre_offset2 ++#define VIU_OSD2_MATRIX_PRE_OFFSET2 (0x1ab9) ++#define P_VIU_OSD2_MATRIX_PRE_OFFSET2 (volatile unsigned int *)((0x1ab9 << 2) + 0xff900000) ++//Read only ++//Bit 29:20 component 0 ++//Bit 19:10 component 1 ++//Bit 9:0 component 2 ++#define VIU_OSD2_MATRIX_PROBE_COLOR (0x1aba) ++#define P_VIU_OSD2_MATRIX_PROBE_COLOR (volatile unsigned int *)((0x1aba << 2) + 0xff900000) ++//Bit 23:16 component 0 ++//Bit 15:8 component 1 ++//Bit 7:0 component 2 ++#define VIU_OSD2_MATRIX_HL_COLOR (0x1abb) ++#define P_VIU_OSD2_MATRIX_HL_COLOR (volatile unsigned int *)((0x1abb << 2) + 0xff900000) ++//28:16 probe x, postion ++//12:0 probe y, position ++#define VIU_OSD2_MATRIX_PROBE_POS (0x1abc) ++#define P_VIU_OSD2_MATRIX_PROBE_POS (volatile unsigned int *)((0x1abc << 2) + 0xff900000) ++//the segment of afbc dec is 8'he0-8'hfe ++//`define AFBC_DEC_OFFSET 8'he0 ++// ++// Reading file: afbc_dec_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++////===============================//// ++//// reg ++////===============================//// ++#define AFBC_ENABLE (0x1ae0) ++#define P_AFBC_ENABLE (volatile unsigned int *)((0x1ae0 << 2) + 0xff900000) ++//Bit 31:1, reserved ++//Bit 8, dec_enable unsigned , default = 0 ++//Bit 7:1, reserved ++//Bit 0, frm_start unsigned , default = 0 ++#define AFBC_MODE (0x1ae1) ++#define P_AFBC_MODE (volatile unsigned int *)((0x1ae1 << 2) + 0xff900000) ++//Bit 31, soft_reset the use as go_field ++//Bit 30, reserved ++//Bit 29, ddr_sz_mode uns, default = 0 , 0: fixed block ddr size 1 : unfixed block ddr size; ++//Bit 28, blk_mem_mode uns, default = 0 , 0: fixed 16x128 size; 1 : fixed 12x128 size ++//Bit 27:26, rev_mode uns, default = 0 , reverse mode ++//Bit 25:24, mif_urgent uns, default = 3 , info mif and data mif urgent ++//Bit 22:16, hold_line_num ++//Bit 15:14, burst_len uns, default = 1, 0: burst1 1:burst2 2:burst4 ++//Bit 13:8, compbits_yuv uns, default = 0 , ++// bit 1:0,: y component bitwidth : 00-8bit 01-9bit 10-10bit ++// bit 3:2,: u component bitwidth : 00-8bit 01-9bit 10-10bit ++// bit 5:4,: v component bitwidth : 00-8bit 01-9bit 10-10bit ++//Bit 7:6, vert_skip_y uns, default = 0 , luma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2 ++//Bit 5:4, horz_skip_y uns, default = 0 , luma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2 ++//Bit 3:2, vert_skip_uv uns, default = 0 , chroma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2 ++//Bit 1:0, horz_skip_uv uns, default = 0 , chroma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2 ++#define AFBC_SIZE_IN (0x1ae2) ++#define P_AFBC_SIZE_IN (volatile unsigned int *)((0x1ae2 << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28:16 hsize_in uns, default = 1920 , pic horz size in unit: pixel ++//Bit 15:13, reserved ++//Bit 12:0, vsize_in uns, default = 1080 , pic vert size in unit: pixel ++#define AFBC_DEC_DEF_COLOR (0x1ae3) ++#define P_AFBC_DEC_DEF_COLOR (volatile unsigned int *)((0x1ae3 << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 29:20, def_color_y uns, default = 0, afbc dec y default setting value ++//Bit 19:10, def_color_u uns, default = 0, afbc dec u default setting value ++//Bit 9: 0, def_color_v uns, default = 0, afbc dec v default setting value ++#define AFBC_CONV_CTRL (0x1ae4) ++#define P_AFBC_CONV_CTRL (volatile unsigned int *)((0x1ae4 << 2) + 0xff900000) ++//Bit 31:12, reserved ++//Bit 11: 0, conv_lbuf_len uns, default = 256, unit=16 pixel need to set = 2^n ++#define AFBC_LBUF_DEPTH (0x1ae5) ++#define P_AFBC_LBUF_DEPTH (volatile unsigned int *)((0x1ae5 << 2) + 0xff900000) ++//Bit 31:28, reserved ++//Bit 27:16, dec_lbuf_depth uns, default = 128; // unit= 8 pixel ++//Bit 15:12, reserved ++//Bit 11:0, mif_lbuf_depth uns, default = 128; ++#define AFBC_HEAD_BADDR (0x1ae6) ++#define P_AFBC_HEAD_BADDR (volatile unsigned int *)((0x1ae6 << 2) + 0xff900000) ++//Bit 31:0, mif_info_baddr uns, default = 32'h0; ++#define AFBC_BODY_BADDR (0x1ae7) ++#define P_AFBC_BODY_BADDR (volatile unsigned int *)((0x1ae7 << 2) + 0xff900000) ++//Bit 31:0, mif_data_baddr uns, default = 32'h0001_0000; ++#define AFBC_SIZE_OUT (0x1ae8) ++#define P_AFBC_SIZE_OUT (volatile unsigned int *)((0x1ae8 << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28:16, hsize_out uns, default = 1920 ; // unit: 1 pixel ++//Bit 15:13, reserved ++//Bit 12:0, vsize_out uns, default = 1080 ; // unit: 1 pixel ++#define AFBC_OUT_YSCOPE (0x1ae9) ++#define P_AFBC_OUT_YSCOPE (volatile unsigned int *)((0x1ae9 << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28:16, out_vert_bgn uns, default = 0 ; // unit: 1 pixel ++//Bit 15:13, reserved ++//Bit 12:0, out_vert_end uns, default = 1079 ; // unit: 1 pixel ++#define AFBC_STAT (0x1aea) ++#define P_AFBC_STAT (volatile unsigned int *)((0x1aea << 2) + 0xff900000) ++//Bit 31:1, reserved ++//Bit 0, frm_end_stat uns, frame end status ++#define AFBC_VD_CFMT_CTRL (0x1aeb) ++#define P_AFBC_VD_CFMT_CTRL (volatile unsigned int *)((0x1aeb << 2) + 0xff900000) ++//Bit 31 it true, disable clock, otherwise enable clock ++//Bit 30 soft rst bit ++//Bit 28 if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation ++//Bit 27:24 horizontal formatter initial phase ++//Bit 23 horizontal formatter repeat pixel 0 enable ++//Bit 22:21 horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1 ++//Bit 20 horizontal formatter enable ++//Bit 19 if true, always use phase0 while vertical formater, meaning always ++// repeat data, no interpolation ++//Bit 18 if true, disable vertical formatter chroma repeat last line ++//Bit 17 veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable ++//Bit 16 veritcal formatter repeat line 0 enable ++//Bit 15:12 vertical formatter skip line num at the beginning ++//Bit 11:8 vertical formatter initial phase ++//Bit 7:1 vertical formatter phase step (3.4) ++//Bit 0 vertical formatter enable ++#define AFBC_VD_CFMT_W (0x1aec) ++#define P_AFBC_VD_CFMT_W (volatile unsigned int *)((0x1aec << 2) + 0xff900000) ++//Bit 27:16 horizontal formatter width ++//Bit 11:0 vertical formatter width ++#define AFBC_MIF_HOR_SCOPE (0x1aed) ++#define P_AFBC_MIF_HOR_SCOPE (volatile unsigned int *)((0x1aed << 2) + 0xff900000) ++//Bit 31:26, reserved ++//Bit 25:16, mif_blk_bgn_h uns, default = 0 ; // unit: 32 pixel/block hor ++//Bit 15:10, reserved ++//Bit 9: 0, mif_blk_end_h uns, default = 59 ; // unit: 32 pixel/block hor ++#define AFBC_MIF_VER_SCOPE (0x1aee) ++#define P_AFBC_MIF_VER_SCOPE (volatile unsigned int *)((0x1aee << 2) + 0xff900000) ++//Bit 31:28, reserved ++//Bit 27:16, mif_blk_bgn_v uns, default = 0 ; // unit: 32 pixel/block ver ++//Bit 15:12, reserved ++//Bit 11: 0, mif_blk_end_v uns, default = 269; // unit: 32 pixel/block ver ++#define AFBC_PIXEL_HOR_SCOPE (0x1aef) ++#define P_AFBC_PIXEL_HOR_SCOPE (volatile unsigned int *)((0x1aef << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28:16, dec_pixel_bgn_h uns, default = 0 ; // unit: pixel ++//Bit 15:13, reserved ++//Bit 12: 0, dec_pixel_end_h uns, default = 1919 ; // unit: pixel ++#define AFBC_PIXEL_VER_SCOPE (0x1af0) ++#define P_AFBC_PIXEL_VER_SCOPE (volatile unsigned int *)((0x1af0 << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28:16, dec_pixel_bgn_v uns, default = 0 ; // unit: pixel ++//Bit 15:13, reserved ++//Bit 12: 0, dec_pixel_end_v uns, default = 1079 ; // unit: pixel ++#define AFBC_VD_CFMT_H (0x1af1) ++#define P_AFBC_VD_CFMT_H (volatile unsigned int *)((0x1af1 << 2) + 0xff900000) ++//Bit 12:0 vertical formatter height ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: afbc_dec_regs.h ++// ++// ++// Closing file: vregs_clk2.h ++// ++//`define VENC_VCBUS_BASE 8'h1b ++// ++// Reading file: venc_regs.h ++// ++//=========================================================================== ++// Video Interface Registers 0xa00 - 0xbff ++//=========================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: VENC_VCBUS_BASE = 0x1b ++// ----------------------------------------------- ++// bit 15:8 -- vfifo2vd_vd_sel ++// bit 0 -- vfifo2vd_en ++#define ENCP_VFIFO2VD_CTL (0x1b58) ++#define P_ENCP_VFIFO2VD_CTL (volatile unsigned int *)((0x1b58 << 2) + 0xff900000) ++// bit 12:0 -- vfifo2vd_pixel_start ++#define ENCP_VFIFO2VD_PIXEL_START (0x1b59) ++#define P_ENCP_VFIFO2VD_PIXEL_START (volatile unsigned int *)((0x1b59 << 2) + 0xff900000) ++// bit 12:00 -- vfifo2vd_pixel_end ++#define ENCP_VFIFO2VD_PIXEL_END (0x1b5a) ++#define P_ENCP_VFIFO2VD_PIXEL_END (volatile unsigned int *)((0x1b5a << 2) + 0xff900000) ++// bit 10:0 -- vfifo2vd_line_top_start ++#define ENCP_VFIFO2VD_LINE_TOP_START (0x1b5b) ++#define P_ENCP_VFIFO2VD_LINE_TOP_START (volatile unsigned int *)((0x1b5b << 2) + 0xff900000) ++// bit 10:00 -- vfifo2vd_line_top_end ++#define ENCP_VFIFO2VD_LINE_TOP_END (0x1b5c) ++#define P_ENCP_VFIFO2VD_LINE_TOP_END (volatile unsigned int *)((0x1b5c << 2) + 0xff900000) ++// bit 10:00 -- vfifo2vd_line_bot_start ++#define ENCP_VFIFO2VD_LINE_BOT_START (0x1b5d) ++#define P_ENCP_VFIFO2VD_LINE_BOT_START (volatile unsigned int *)((0x1b5d << 2) + 0xff900000) ++// bit 10:00 -- vfifo2vd_line_bot_end ++#define ENCP_VFIFO2VD_LINE_BOT_END (0x1b5e) ++#define P_ENCP_VFIFO2VD_LINE_BOT_END (volatile unsigned int *)((0x1b5e << 2) + 0xff900000) ++// Route the hsync and vsync signals round the chip. There are three ++// sources and users of these signals: VIU, internal video encoder, and ++// the pins on the chip. Some muxing is still being done in the VIU. It ++// was not moved to the venc module so that the same exact VIU code could ++// be used both in Twister and Twister2000. ++// Bit 2: venc_sync_source (1=>pins, 0=>viu) ++// Bit 1: viu_sync_source (1=>pins, 0=>venc) ++// Bit 0: vpins_sync_source (1=>venc, 0=>viu) ++#define VENC_SYNC_ROUTE (0x1b60) ++#define P_VENC_SYNC_ROUTE (volatile unsigned int *)((0x1b60 << 2) + 0xff900000) ++#define VENC_VIDEO_EXSRC (0x1b61) ++#define P_VENC_VIDEO_EXSRC (volatile unsigned int *)((0x1b61 << 2) + 0xff900000) ++#define VENC_DVI_SETTING (0x1b62) ++#define P_VENC_DVI_SETTING (volatile unsigned int *)((0x1b62 << 2) + 0xff900000) ++#define VENC_C656_CTRL (0x1b63) ++#define P_VENC_C656_CTRL (volatile unsigned int *)((0x1b63 << 2) + 0xff900000) ++#define VENC_UPSAMPLE_CTRL0 (0x1b64) ++#define P_VENC_UPSAMPLE_CTRL0 (volatile unsigned int *)((0x1b64 << 2) + 0xff900000) ++#define VENC_UPSAMPLE_CTRL1 (0x1b65) ++#define P_VENC_UPSAMPLE_CTRL1 (volatile unsigned int *)((0x1b65 << 2) + 0xff900000) ++#define VENC_UPSAMPLE_CTRL2 (0x1b66) ++#define P_VENC_UPSAMPLE_CTRL2 (volatile unsigned int *)((0x1b66 << 2) + 0xff900000) ++// Invert control for tcon output ++// bit[15:14] -- vsync, hsync, ++// bit[13:0] -- oev3, oev2, cpv2, cph3, cph2, cph1, oeh, vcom, stv2, stv1, cpv1, oev1, sth1, sth2 ++#define TCON_INVERT_CTL (0x1b67) ++#define P_TCON_INVERT_CTL (volatile unsigned int *)((0x1b67 << 2) + 0xff900000) ++#define VENC_VIDEO_PROG_MODE (0x1b68) ++#define P_VENC_VIDEO_PROG_MODE (volatile unsigned int *)((0x1b68 << 2) + 0xff900000) ++//---- Venc pixel/line info ++#define VENC_ENCI_LINE (0x1b69) ++#define P_VENC_ENCI_LINE (volatile unsigned int *)((0x1b69 << 2) + 0xff900000) ++#define VENC_ENCI_PIXEL (0x1b6a) ++#define P_VENC_ENCI_PIXEL (volatile unsigned int *)((0x1b6a << 2) + 0xff900000) ++#define VENC_ENCP_LINE (0x1b6b) ++#define P_VENC_ENCP_LINE (volatile unsigned int *)((0x1b6b << 2) + 0xff900000) ++#define VENC_ENCP_PIXEL (0x1b6c) ++#define P_VENC_ENCP_PIXEL (volatile unsigned int *)((0x1b6c << 2) + 0xff900000) ++//---- Status ++#define VENC_STATA (0x1b6d) ++#define P_VENC_STATA (volatile unsigned int *)((0x1b6d << 2) + 0xff900000) ++//---- Interrupt setting ++#define VENC_INTCTRL (0x1b6e) ++#define P_VENC_INTCTRL (volatile unsigned int *)((0x1b6e << 2) + 0xff900000) ++#define VENC_INTFLAG (0x1b6f) ++#define P_VENC_INTFLAG (volatile unsigned int *)((0x1b6f << 2) + 0xff900000) ++//--------- Video test configuration ++#define VENC_VIDEO_TST_EN (0x1b70) ++#define P_VENC_VIDEO_TST_EN (volatile unsigned int *)((0x1b70 << 2) + 0xff900000) ++#define VENC_VIDEO_TST_MDSEL (0x1b71) ++#define P_VENC_VIDEO_TST_MDSEL (volatile unsigned int *)((0x1b71 << 2) + 0xff900000) ++#define VENC_VIDEO_TST_Y (0x1b72) ++#define P_VENC_VIDEO_TST_Y (volatile unsigned int *)((0x1b72 << 2) + 0xff900000) ++#define VENC_VIDEO_TST_CB (0x1b73) ++#define P_VENC_VIDEO_TST_CB (volatile unsigned int *)((0x1b73 << 2) + 0xff900000) ++#define VENC_VIDEO_TST_CR (0x1b74) ++#define P_VENC_VIDEO_TST_CR (volatile unsigned int *)((0x1b74 << 2) + 0xff900000) ++#define VENC_VIDEO_TST_CLRBAR_STRT (0x1b75) ++#define P_VENC_VIDEO_TST_CLRBAR_STRT (volatile unsigned int *)((0x1b75 << 2) + 0xff900000) ++#define VENC_VIDEO_TST_CLRBAR_WIDTH (0x1b76) ++#define P_VENC_VIDEO_TST_CLRBAR_WIDTH (volatile unsigned int *)((0x1b76 << 2) + 0xff900000) ++#define VENC_VIDEO_TST_VDCNT_STSET (0x1b77) ++#define P_VENC_VIDEO_TST_VDCNT_STSET (volatile unsigned int *)((0x1b77 << 2) + 0xff900000) ++//----- Video dac setting ++#define VENC_VDAC_DACSEL0 (0x1b78) ++#define P_VENC_VDAC_DACSEL0 (volatile unsigned int *)((0x1b78 << 2) + 0xff900000) ++#define VENC_VDAC_DACSEL1 (0x1b79) ++#define P_VENC_VDAC_DACSEL1 (volatile unsigned int *)((0x1b79 << 2) + 0xff900000) ++#define VENC_VDAC_DACSEL2 (0x1b7a) ++#define P_VENC_VDAC_DACSEL2 (volatile unsigned int *)((0x1b7a << 2) + 0xff900000) ++#define VENC_VDAC_DACSEL3 (0x1b7b) ++#define P_VENC_VDAC_DACSEL3 (volatile unsigned int *)((0x1b7b << 2) + 0xff900000) ++#define VENC_VDAC_DACSEL4 (0x1b7c) ++#define P_VENC_VDAC_DACSEL4 (volatile unsigned int *)((0x1b7c << 2) + 0xff900000) ++#define VENC_VDAC_DACSEL5 (0x1b7d) ++#define P_VENC_VDAC_DACSEL5 (volatile unsigned int *)((0x1b7d << 2) + 0xff900000) ++#define VENC_VDAC_SETTING (0x1b7e) ++#define P_VENC_VDAC_SETTING (volatile unsigned int *)((0x1b7e << 2) + 0xff900000) ++#define VENC_VDAC_TST_VAL (0x1b7f) ++#define P_VENC_VDAC_TST_VAL (volatile unsigned int *)((0x1b7f << 2) + 0xff900000) ++#define VENC_VDAC_DAC0_GAINCTRL (0x1bf0) ++#define P_VENC_VDAC_DAC0_GAINCTRL (volatile unsigned int *)((0x1bf0 << 2) + 0xff900000) ++#define VENC_VDAC_DAC0_OFFSET (0x1bf1) ++#define P_VENC_VDAC_DAC0_OFFSET (volatile unsigned int *)((0x1bf1 << 2) + 0xff900000) ++#define VENC_VDAC_DAC1_GAINCTRL (0x1bf2) ++#define P_VENC_VDAC_DAC1_GAINCTRL (volatile unsigned int *)((0x1bf2 << 2) + 0xff900000) ++#define VENC_VDAC_DAC1_OFFSET (0x1bf3) ++#define P_VENC_VDAC_DAC1_OFFSET (volatile unsigned int *)((0x1bf3 << 2) + 0xff900000) ++#define VENC_VDAC_DAC2_GAINCTRL (0x1bf4) ++#define P_VENC_VDAC_DAC2_GAINCTRL (volatile unsigned int *)((0x1bf4 << 2) + 0xff900000) ++#define VENC_VDAC_DAC2_OFFSET (0x1bf5) ++#define P_VENC_VDAC_DAC2_OFFSET (volatile unsigned int *)((0x1bf5 << 2) + 0xff900000) ++#define VENC_VDAC_DAC3_GAINCTRL (0x1bf6) ++#define P_VENC_VDAC_DAC3_GAINCTRL (volatile unsigned int *)((0x1bf6 << 2) + 0xff900000) ++#define VENC_VDAC_DAC3_OFFSET (0x1bf7) ++#define P_VENC_VDAC_DAC3_OFFSET (volatile unsigned int *)((0x1bf7 << 2) + 0xff900000) ++#define VENC_VDAC_DAC4_GAINCTRL (0x1bf8) ++#define P_VENC_VDAC_DAC4_GAINCTRL (volatile unsigned int *)((0x1bf8 << 2) + 0xff900000) ++#define VENC_VDAC_DAC4_OFFSET (0x1bf9) ++#define P_VENC_VDAC_DAC4_OFFSET (volatile unsigned int *)((0x1bf9 << 2) + 0xff900000) ++#define VENC_VDAC_DAC5_GAINCTRL (0x1bfa) ++#define P_VENC_VDAC_DAC5_GAINCTRL (volatile unsigned int *)((0x1bfa << 2) + 0xff900000) ++#define VENC_VDAC_DAC5_OFFSET (0x1bfb) ++#define P_VENC_VDAC_DAC5_OFFSET (volatile unsigned int *)((0x1bfb << 2) + 0xff900000) ++#define VENC_VDAC_FIFO_CTRL (0x1bfc) ++#define P_VENC_VDAC_FIFO_CTRL (volatile unsigned int *)((0x1bfc << 2) + 0xff900000) ++#define ENCL_TCON_INVERT_CTL (0x1bfd) ++#define P_ENCL_TCON_INVERT_CTL (volatile unsigned int *)((0x1bfd << 2) + 0xff900000) ++// ++// Closing file: venc_regs.h ++// ++// ++// Reading file: enc480p_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++//=========================================================================== ++// Video Encoder 480p Registers 0xb80 - 0xbef ++//=========================================================================== ++//-------- Video basic setting ++#define ENCP_VIDEO_EN (0x1b80) ++#define P_ENCP_VIDEO_EN (volatile unsigned int *)((0x1b80 << 2) + 0xff900000) ++#define ENCP_VIDEO_SYNC_MODE (0x1b81) ++#define P_ENCP_VIDEO_SYNC_MODE (volatile unsigned int *)((0x1b81 << 2) + 0xff900000) ++#define ENCP_MACV_EN (0x1b82) ++#define P_ENCP_MACV_EN (volatile unsigned int *)((0x1b82 << 2) + 0xff900000) ++#define ENCP_VIDEO_Y_SCL (0x1b83) ++#define P_ENCP_VIDEO_Y_SCL (volatile unsigned int *)((0x1b83 << 2) + 0xff900000) ++#define ENCP_VIDEO_PB_SCL (0x1b84) ++#define P_ENCP_VIDEO_PB_SCL (volatile unsigned int *)((0x1b84 << 2) + 0xff900000) ++#define ENCP_VIDEO_PR_SCL (0x1b85) ++#define P_ENCP_VIDEO_PR_SCL (volatile unsigned int *)((0x1b85 << 2) + 0xff900000) ++#define ENCP_VIDEO_SYNC_SCL (0x1b86) ++#define P_ENCP_VIDEO_SYNC_SCL (volatile unsigned int *)((0x1b86 << 2) + 0xff900000) ++#define ENCP_VIDEO_MACV_SCL (0x1b87) ++#define P_ENCP_VIDEO_MACV_SCL (volatile unsigned int *)((0x1b87 << 2) + 0xff900000) ++#define ENCP_VIDEO_Y_OFFST (0x1b88) ++#define P_ENCP_VIDEO_Y_OFFST (volatile unsigned int *)((0x1b88 << 2) + 0xff900000) ++#define ENCP_VIDEO_PB_OFFST (0x1b89) ++#define P_ENCP_VIDEO_PB_OFFST (volatile unsigned int *)((0x1b89 << 2) + 0xff900000) ++#define ENCP_VIDEO_PR_OFFST (0x1b8a) ++#define P_ENCP_VIDEO_PR_OFFST (volatile unsigned int *)((0x1b8a << 2) + 0xff900000) ++#define ENCP_VIDEO_SYNC_OFFST (0x1b8b) ++#define P_ENCP_VIDEO_SYNC_OFFST (volatile unsigned int *)((0x1b8b << 2) + 0xff900000) ++#define ENCP_VIDEO_MACV_OFFST (0x1b8c) ++#define P_ENCP_VIDEO_MACV_OFFST (volatile unsigned int *)((0x1b8c << 2) + 0xff900000) ++//----- Video mode ++#define ENCP_VIDEO_MODE (0x1b8d) ++#define P_ENCP_VIDEO_MODE (volatile unsigned int *)((0x1b8d << 2) + 0xff900000) ++#define ENCP_VIDEO_MODE_ADV (0x1b8e) ++#define P_ENCP_VIDEO_MODE_ADV (volatile unsigned int *)((0x1b8e << 2) + 0xff900000) ++//--------------- Debug pins ++#define ENCP_DBG_PX_RST (0x1b90) ++#define P_ENCP_DBG_PX_RST (volatile unsigned int *)((0x1b90 << 2) + 0xff900000) ++#define ENCP_DBG_LN_RST (0x1b91) ++#define P_ENCP_DBG_LN_RST (volatile unsigned int *)((0x1b91 << 2) + 0xff900000) ++#define ENCP_DBG_PX_INT (0x1b92) ++#define P_ENCP_DBG_PX_INT (volatile unsigned int *)((0x1b92 << 2) + 0xff900000) ++#define ENCP_DBG_LN_INT (0x1b93) ++#define P_ENCP_DBG_LN_INT (volatile unsigned int *)((0x1b93 << 2) + 0xff900000) ++//----------- Video Advanced setting ++#define ENCP_VIDEO_YFP1_HTIME (0x1b94) ++#define P_ENCP_VIDEO_YFP1_HTIME (volatile unsigned int *)((0x1b94 << 2) + 0xff900000) ++#define ENCP_VIDEO_YFP2_HTIME (0x1b95) ++#define P_ENCP_VIDEO_YFP2_HTIME (volatile unsigned int *)((0x1b95 << 2) + 0xff900000) ++#define ENCP_VIDEO_YC_DLY (0x1b96) ++#define P_ENCP_VIDEO_YC_DLY (volatile unsigned int *)((0x1b96 << 2) + 0xff900000) ++#define ENCP_VIDEO_MAX_PXCNT (0x1b97) ++#define P_ENCP_VIDEO_MAX_PXCNT (volatile unsigned int *)((0x1b97 << 2) + 0xff900000) ++#define ENCP_VIDEO_HSPULS_BEGIN (0x1b98) ++#define P_ENCP_VIDEO_HSPULS_BEGIN (volatile unsigned int *)((0x1b98 << 2) + 0xff900000) ++#define ENCP_VIDEO_HSPULS_END (0x1b99) ++#define P_ENCP_VIDEO_HSPULS_END (volatile unsigned int *)((0x1b99 << 2) + 0xff900000) ++#define ENCP_VIDEO_HSPULS_SWITCH (0x1b9a) ++#define P_ENCP_VIDEO_HSPULS_SWITCH (volatile unsigned int *)((0x1b9a << 2) + 0xff900000) ++#define ENCP_VIDEO_VSPULS_BEGIN (0x1b9b) ++#define P_ENCP_VIDEO_VSPULS_BEGIN (volatile unsigned int *)((0x1b9b << 2) + 0xff900000) ++#define ENCP_VIDEO_VSPULS_END (0x1b9c) ++#define P_ENCP_VIDEO_VSPULS_END (volatile unsigned int *)((0x1b9c << 2) + 0xff900000) ++#define ENCP_VIDEO_VSPULS_BLINE (0x1b9d) ++#define P_ENCP_VIDEO_VSPULS_BLINE (volatile unsigned int *)((0x1b9d << 2) + 0xff900000) ++#define ENCP_VIDEO_VSPULS_ELINE (0x1b9e) ++#define P_ENCP_VIDEO_VSPULS_ELINE (volatile unsigned int *)((0x1b9e << 2) + 0xff900000) ++#define ENCP_VIDEO_EQPULS_BEGIN (0x1b9f) ++#define P_ENCP_VIDEO_EQPULS_BEGIN (volatile unsigned int *)((0x1b9f << 2) + 0xff900000) ++#define ENCP_VIDEO_EQPULS_END (0x1ba0) ++#define P_ENCP_VIDEO_EQPULS_END (volatile unsigned int *)((0x1ba0 << 2) + 0xff900000) ++#define ENCP_VIDEO_EQPULS_BLINE (0x1ba1) ++#define P_ENCP_VIDEO_EQPULS_BLINE (volatile unsigned int *)((0x1ba1 << 2) + 0xff900000) ++#define ENCP_VIDEO_EQPULS_ELINE (0x1ba2) ++#define P_ENCP_VIDEO_EQPULS_ELINE (volatile unsigned int *)((0x1ba2 << 2) + 0xff900000) ++#define ENCP_VIDEO_HAVON_END (0x1ba3) ++#define P_ENCP_VIDEO_HAVON_END (volatile unsigned int *)((0x1ba3 << 2) + 0xff900000) ++#define ENCP_VIDEO_HAVON_BEGIN (0x1ba4) ++#define P_ENCP_VIDEO_HAVON_BEGIN (volatile unsigned int *)((0x1ba4 << 2) + 0xff900000) ++#define ENCP_VIDEO_VAVON_ELINE (0x1baf) ++#define P_ENCP_VIDEO_VAVON_ELINE (volatile unsigned int *)((0x1baf << 2) + 0xff900000) ++#define ENCP_VIDEO_VAVON_BLINE (0x1ba6) ++#define P_ENCP_VIDEO_VAVON_BLINE (volatile unsigned int *)((0x1ba6 << 2) + 0xff900000) ++#define ENCP_VIDEO_HSO_BEGIN (0x1ba7) ++#define P_ENCP_VIDEO_HSO_BEGIN (volatile unsigned int *)((0x1ba7 << 2) + 0xff900000) ++#define ENCP_VIDEO_HSO_END (0x1ba8) ++#define P_ENCP_VIDEO_HSO_END (volatile unsigned int *)((0x1ba8 << 2) + 0xff900000) ++#define ENCP_VIDEO_VSO_BEGIN (0x1ba9) ++#define P_ENCP_VIDEO_VSO_BEGIN (volatile unsigned int *)((0x1ba9 << 2) + 0xff900000) ++#define ENCP_VIDEO_VSO_END (0x1baa) ++#define P_ENCP_VIDEO_VSO_END (volatile unsigned int *)((0x1baa << 2) + 0xff900000) ++#define ENCP_VIDEO_VSO_BLINE (0x1bab) ++#define P_ENCP_VIDEO_VSO_BLINE (volatile unsigned int *)((0x1bab << 2) + 0xff900000) ++#define ENCP_VIDEO_VSO_ELINE (0x1bac) ++#define P_ENCP_VIDEO_VSO_ELINE (volatile unsigned int *)((0x1bac << 2) + 0xff900000) ++#define ENCP_VIDEO_SYNC_WAVE_CURVE (0x1bad) ++#define P_ENCP_VIDEO_SYNC_WAVE_CURVE (volatile unsigned int *)((0x1bad << 2) + 0xff900000) ++#define ENCP_VIDEO_MAX_LNCNT (0x1bae) ++#define P_ENCP_VIDEO_MAX_LNCNT (volatile unsigned int *)((0x1bae << 2) + 0xff900000) ++#define ENCP_VIDEO_SY_VAL (0x1bb0) ++#define P_ENCP_VIDEO_SY_VAL (volatile unsigned int *)((0x1bb0 << 2) + 0xff900000) ++#define ENCP_VIDEO_SY2_VAL (0x1bb1) ++#define P_ENCP_VIDEO_SY2_VAL (volatile unsigned int *)((0x1bb1 << 2) + 0xff900000) ++#define ENCP_VIDEO_BLANKY_VAL (0x1bb2) ++#define P_ENCP_VIDEO_BLANKY_VAL (volatile unsigned int *)((0x1bb2 << 2) + 0xff900000) ++#define ENCP_VIDEO_BLANKPB_VAL (0x1bb3) ++#define P_ENCP_VIDEO_BLANKPB_VAL (volatile unsigned int *)((0x1bb3 << 2) + 0xff900000) ++#define ENCP_VIDEO_BLANKPR_VAL (0x1bb4) ++#define P_ENCP_VIDEO_BLANKPR_VAL (volatile unsigned int *)((0x1bb4 << 2) + 0xff900000) ++#define ENCP_VIDEO_HOFFST (0x1bb5) ++#define P_ENCP_VIDEO_HOFFST (volatile unsigned int *)((0x1bb5 << 2) + 0xff900000) ++#define ENCP_VIDEO_VOFFST (0x1bb6) ++#define P_ENCP_VIDEO_VOFFST (volatile unsigned int *)((0x1bb6 << 2) + 0xff900000) ++#define ENCP_VIDEO_RGB_CTRL (0x1bb7) ++#define P_ENCP_VIDEO_RGB_CTRL (volatile unsigned int *)((0x1bb7 << 2) + 0xff900000) ++#define ENCP_VIDEO_FILT_CTRL (0x1bb8) ++#define P_ENCP_VIDEO_FILT_CTRL (volatile unsigned int *)((0x1bb8 << 2) + 0xff900000) ++#define ENCP_VIDEO_OFLD_VPEQ_OFST (0x1bb9) ++#define P_ENCP_VIDEO_OFLD_VPEQ_OFST (volatile unsigned int *)((0x1bb9 << 2) + 0xff900000) ++#define ENCP_VIDEO_OFLD_VOAV_OFST (0x1bba) ++#define P_ENCP_VIDEO_OFLD_VOAV_OFST (volatile unsigned int *)((0x1bba << 2) + 0xff900000) ++#define ENCP_VIDEO_MATRIX_CB (0x1bbb) ++#define P_ENCP_VIDEO_MATRIX_CB (volatile unsigned int *)((0x1bbb << 2) + 0xff900000) ++#define ENCP_VIDEO_MATRIX_CR (0x1bbc) ++#define P_ENCP_VIDEO_MATRIX_CR (volatile unsigned int *)((0x1bbc << 2) + 0xff900000) ++#define ENCP_VIDEO_RGBIN_CTRL (0x1bbd) ++#define P_ENCP_VIDEO_RGBIN_CTRL (volatile unsigned int *)((0x1bbd << 2) + 0xff900000) ++//------------------Macrovision advanced setting ++#define ENCP_MACV_BLANKY_VAL (0x1bc0) ++#define P_ENCP_MACV_BLANKY_VAL (volatile unsigned int *)((0x1bc0 << 2) + 0xff900000) ++#define ENCP_MACV_MAXY_VAL (0x1bc1) ++#define P_ENCP_MACV_MAXY_VAL (volatile unsigned int *)((0x1bc1 << 2) + 0xff900000) ++#define ENCP_MACV_1ST_PSSYNC_STRT (0x1bc2) ++#define P_ENCP_MACV_1ST_PSSYNC_STRT (volatile unsigned int *)((0x1bc2 << 2) + 0xff900000) ++#define ENCP_MACV_PSSYNC_STRT (0x1bc3) ++#define P_ENCP_MACV_PSSYNC_STRT (volatile unsigned int *)((0x1bc3 << 2) + 0xff900000) ++#define ENCP_MACV_AGC_STRT (0x1bc4) ++#define P_ENCP_MACV_AGC_STRT (volatile unsigned int *)((0x1bc4 << 2) + 0xff900000) ++#define ENCP_MACV_AGC_END (0x1bc5) ++#define P_ENCP_MACV_AGC_END (volatile unsigned int *)((0x1bc5 << 2) + 0xff900000) ++#define ENCP_MACV_WAVE_END (0x1bc6) ++#define P_ENCP_MACV_WAVE_END (volatile unsigned int *)((0x1bc6 << 2) + 0xff900000) ++#define ENCP_MACV_STRTLINE (0x1bc7) ++#define P_ENCP_MACV_STRTLINE (volatile unsigned int *)((0x1bc7 << 2) + 0xff900000) ++#define ENCP_MACV_ENDLINE (0x1bc8) ++#define P_ENCP_MACV_ENDLINE (volatile unsigned int *)((0x1bc8 << 2) + 0xff900000) ++#define ENCP_MACV_TS_CNT_MAX_L (0x1bc9) ++#define P_ENCP_MACV_TS_CNT_MAX_L (volatile unsigned int *)((0x1bc9 << 2) + 0xff900000) ++#define ENCP_MACV_TS_CNT_MAX_H (0x1bca) ++#define P_ENCP_MACV_TS_CNT_MAX_H (volatile unsigned int *)((0x1bca << 2) + 0xff900000) ++#define ENCP_MACV_TIME_DOWN (0x1bcb) ++#define P_ENCP_MACV_TIME_DOWN (volatile unsigned int *)((0x1bcb << 2) + 0xff900000) ++#define ENCP_MACV_TIME_LO (0x1bcc) ++#define P_ENCP_MACV_TIME_LO (volatile unsigned int *)((0x1bcc << 2) + 0xff900000) ++#define ENCP_MACV_TIME_UP (0x1bcd) ++#define P_ENCP_MACV_TIME_UP (volatile unsigned int *)((0x1bcd << 2) + 0xff900000) ++#define ENCP_MACV_TIME_RST (0x1bce) ++#define P_ENCP_MACV_TIME_RST (volatile unsigned int *)((0x1bce << 2) + 0xff900000) ++//---------------- VBI control ------------------- ++#define ENCP_VBI_CTRL (0x1bd0) ++#define P_ENCP_VBI_CTRL (volatile unsigned int *)((0x1bd0 << 2) + 0xff900000) ++#define ENCP_VBI_SETTING (0x1bd1) ++#define P_ENCP_VBI_SETTING (volatile unsigned int *)((0x1bd1 << 2) + 0xff900000) ++#define ENCP_VBI_BEGIN (0x1bd2) ++#define P_ENCP_VBI_BEGIN (volatile unsigned int *)((0x1bd2 << 2) + 0xff900000) ++#define ENCP_VBI_WIDTH (0x1bd3) ++#define P_ENCP_VBI_WIDTH (volatile unsigned int *)((0x1bd3 << 2) + 0xff900000) ++#define ENCP_VBI_HVAL (0x1bd4) ++#define P_ENCP_VBI_HVAL (volatile unsigned int *)((0x1bd4 << 2) + 0xff900000) ++#define ENCP_VBI_DATA0 (0x1bd5) ++#define P_ENCP_VBI_DATA0 (volatile unsigned int *)((0x1bd5 << 2) + 0xff900000) ++#define ENCP_VBI_DATA1 (0x1bd6) ++#define P_ENCP_VBI_DATA1 (volatile unsigned int *)((0x1bd6 << 2) + 0xff900000) ++//----------------C656 OUT Control------------- Grant ++#define C656_HS_ST (0x1be0) ++#define P_C656_HS_ST (volatile unsigned int *)((0x1be0 << 2) + 0xff900000) ++#define C656_HS_ED (0x1be1) ++#define P_C656_HS_ED (volatile unsigned int *)((0x1be1 << 2) + 0xff900000) ++#define C656_VS_LNST_E (0x1be2) ++#define P_C656_VS_LNST_E (volatile unsigned int *)((0x1be2 << 2) + 0xff900000) ++#define C656_VS_LNST_O (0x1be3) ++#define P_C656_VS_LNST_O (volatile unsigned int *)((0x1be3 << 2) + 0xff900000) ++#define C656_VS_LNED_E (0x1be4) ++#define P_C656_VS_LNED_E (volatile unsigned int *)((0x1be4 << 2) + 0xff900000) ++#define C656_VS_LNED_O (0x1be5) ++#define P_C656_VS_LNED_O (volatile unsigned int *)((0x1be5 << 2) + 0xff900000) ++#define C656_FS_LNST (0x1be6) ++#define P_C656_FS_LNST (volatile unsigned int *)((0x1be6 << 2) + 0xff900000) ++#define C656_FS_LNED (0x1be7) ++#define P_C656_FS_LNED (volatile unsigned int *)((0x1be7 << 2) + 0xff900000) ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: enc480p_regs.h ++// ++// ++// Reading file: enci_regs.h ++// ++//=========================================================================== ++// Video Interface Registers 0xb00 - 0xb57 ++//=========================================================================== ++#define ENCI_VIDEO_MODE (0x1b00) ++#define P_ENCI_VIDEO_MODE (volatile unsigned int *)((0x1b00 << 2) + 0xff900000) ++#define ENCI_VIDEO_MODE_ADV (0x1b01) ++#define P_ENCI_VIDEO_MODE_ADV (volatile unsigned int *)((0x1b01 << 2) + 0xff900000) ++#define ENCI_VIDEO_FSC_ADJ (0x1b02) ++#define P_ENCI_VIDEO_FSC_ADJ (volatile unsigned int *)((0x1b02 << 2) + 0xff900000) ++#define ENCI_VIDEO_BRIGHT (0x1b03) ++#define P_ENCI_VIDEO_BRIGHT (volatile unsigned int *)((0x1b03 << 2) + 0xff900000) ++#define ENCI_VIDEO_CONT (0x1b04) ++#define P_ENCI_VIDEO_CONT (volatile unsigned int *)((0x1b04 << 2) + 0xff900000) ++#define ENCI_VIDEO_SAT (0x1b05) ++#define P_ENCI_VIDEO_SAT (volatile unsigned int *)((0x1b05 << 2) + 0xff900000) ++#define ENCI_VIDEO_HUE (0x1b06) ++#define P_ENCI_VIDEO_HUE (volatile unsigned int *)((0x1b06 << 2) + 0xff900000) ++#define ENCI_VIDEO_SCH (0x1b07) ++#define P_ENCI_VIDEO_SCH (volatile unsigned int *)((0x1b07 << 2) + 0xff900000) ++#define ENCI_SYNC_MODE (0x1b08) ++#define P_ENCI_SYNC_MODE (volatile unsigned int *)((0x1b08 << 2) + 0xff900000) ++#define ENCI_SYNC_CTRL (0x1b09) ++#define P_ENCI_SYNC_CTRL (volatile unsigned int *)((0x1b09 << 2) + 0xff900000) ++#define ENCI_SYNC_HSO_BEGIN (0x1b0a) ++#define P_ENCI_SYNC_HSO_BEGIN (volatile unsigned int *)((0x1b0a << 2) + 0xff900000) ++#define ENCI_SYNC_HSO_END (0x1b0b) ++#define P_ENCI_SYNC_HSO_END (volatile unsigned int *)((0x1b0b << 2) + 0xff900000) ++#define ENCI_SYNC_VSO_EVN (0x1b0c) ++#define P_ENCI_SYNC_VSO_EVN (volatile unsigned int *)((0x1b0c << 2) + 0xff900000) ++#define ENCI_SYNC_VSO_ODD (0x1b0d) ++#define P_ENCI_SYNC_VSO_ODD (volatile unsigned int *)((0x1b0d << 2) + 0xff900000) ++#define ENCI_SYNC_VSO_EVNLN (0x1b0e) ++#define P_ENCI_SYNC_VSO_EVNLN (volatile unsigned int *)((0x1b0e << 2) + 0xff900000) ++#define ENCI_SYNC_VSO_ODDLN (0x1b0f) ++#define P_ENCI_SYNC_VSO_ODDLN (volatile unsigned int *)((0x1b0f << 2) + 0xff900000) ++#define ENCI_SYNC_HOFFST (0x1b10) ++#define P_ENCI_SYNC_HOFFST (volatile unsigned int *)((0x1b10 << 2) + 0xff900000) ++#define ENCI_SYNC_VOFFST (0x1b11) ++#define P_ENCI_SYNC_VOFFST (volatile unsigned int *)((0x1b11 << 2) + 0xff900000) ++#define ENCI_SYNC_ADJ (0x1b12) ++#define P_ENCI_SYNC_ADJ (volatile unsigned int *)((0x1b12 << 2) + 0xff900000) ++#define ENCI_RGB_SETTING (0x1b13) ++#define P_ENCI_RGB_SETTING (volatile unsigned int *)((0x1b13 << 2) + 0xff900000) ++//`define ENCI_CMPN_MATRIX_CB 8'h14 ++//`define ENCI_CMPN_MATRIX_CR 8'h15 ++#define ENCI_DE_H_BEGIN (0x1b16) ++#define P_ENCI_DE_H_BEGIN (volatile unsigned int *)((0x1b16 << 2) + 0xff900000) ++#define ENCI_DE_H_END (0x1b17) ++#define P_ENCI_DE_H_END (volatile unsigned int *)((0x1b17 << 2) + 0xff900000) ++#define ENCI_DE_V_BEGIN_EVEN (0x1b18) ++#define P_ENCI_DE_V_BEGIN_EVEN (volatile unsigned int *)((0x1b18 << 2) + 0xff900000) ++#define ENCI_DE_V_END_EVEN (0x1b19) ++#define P_ENCI_DE_V_END_EVEN (volatile unsigned int *)((0x1b19 << 2) + 0xff900000) ++#define ENCI_DE_V_BEGIN_ODD (0x1b1a) ++#define P_ENCI_DE_V_BEGIN_ODD (volatile unsigned int *)((0x1b1a << 2) + 0xff900000) ++#define ENCI_DE_V_END_ODD (0x1b1b) ++#define P_ENCI_DE_V_END_ODD (volatile unsigned int *)((0x1b1b << 2) + 0xff900000) ++#define ENCI_VBI_SETTING (0x1b20) ++#define P_ENCI_VBI_SETTING (volatile unsigned int *)((0x1b20 << 2) + 0xff900000) ++#define ENCI_VBI_CCDT_EVN (0x1b21) ++#define P_ENCI_VBI_CCDT_EVN (volatile unsigned int *)((0x1b21 << 2) + 0xff900000) ++#define ENCI_VBI_CCDT_ODD (0x1b22) ++#define P_ENCI_VBI_CCDT_ODD (volatile unsigned int *)((0x1b22 << 2) + 0xff900000) ++#define ENCI_VBI_CC525_LN (0x1b23) ++#define P_ENCI_VBI_CC525_LN (volatile unsigned int *)((0x1b23 << 2) + 0xff900000) ++#define ENCI_VBI_CC625_LN (0x1b24) ++#define P_ENCI_VBI_CC625_LN (volatile unsigned int *)((0x1b24 << 2) + 0xff900000) ++#define ENCI_VBI_WSSDT (0x1b25) ++#define P_ENCI_VBI_WSSDT (volatile unsigned int *)((0x1b25 << 2) + 0xff900000) ++#define ENCI_VBI_WSS_LN (0x1b26) ++#define P_ENCI_VBI_WSS_LN (volatile unsigned int *)((0x1b26 << 2) + 0xff900000) ++#define ENCI_VBI_CGMSDT_L (0x1b27) ++#define P_ENCI_VBI_CGMSDT_L (volatile unsigned int *)((0x1b27 << 2) + 0xff900000) ++#define ENCI_VBI_CGMSDT_H (0x1b28) ++#define P_ENCI_VBI_CGMSDT_H (volatile unsigned int *)((0x1b28 << 2) + 0xff900000) ++#define ENCI_VBI_CGMS_LN (0x1b29) ++#define P_ENCI_VBI_CGMS_LN (volatile unsigned int *)((0x1b29 << 2) + 0xff900000) ++#define ENCI_VBI_TTX_HTIME (0x1b2a) ++#define P_ENCI_VBI_TTX_HTIME (volatile unsigned int *)((0x1b2a << 2) + 0xff900000) ++#define ENCI_VBI_TTX_LN (0x1b2b) ++#define P_ENCI_VBI_TTX_LN (volatile unsigned int *)((0x1b2b << 2) + 0xff900000) ++#define ENCI_VBI_TTXDT0 (0x1b2c) ++#define P_ENCI_VBI_TTXDT0 (volatile unsigned int *)((0x1b2c << 2) + 0xff900000) ++#define ENCI_VBI_TTXDT1 (0x1b2d) ++#define P_ENCI_VBI_TTXDT1 (volatile unsigned int *)((0x1b2d << 2) + 0xff900000) ++#define ENCI_VBI_TTXDT2 (0x1b2e) ++#define P_ENCI_VBI_TTXDT2 (volatile unsigned int *)((0x1b2e << 2) + 0xff900000) ++#define ENCI_VBI_TTXDT3 (0x1b2f) ++#define P_ENCI_VBI_TTXDT3 (volatile unsigned int *)((0x1b2f << 2) + 0xff900000) ++#define ENCI_MACV_N0 (0x1b30) ++#define P_ENCI_MACV_N0 (volatile unsigned int *)((0x1b30 << 2) + 0xff900000) ++#define ENCI_MACV_N1 (0x1b31) ++#define P_ENCI_MACV_N1 (volatile unsigned int *)((0x1b31 << 2) + 0xff900000) ++#define ENCI_MACV_N2 (0x1b32) ++#define P_ENCI_MACV_N2 (volatile unsigned int *)((0x1b32 << 2) + 0xff900000) ++#define ENCI_MACV_N3 (0x1b33) ++#define P_ENCI_MACV_N3 (volatile unsigned int *)((0x1b33 << 2) + 0xff900000) ++#define ENCI_MACV_N4 (0x1b34) ++#define P_ENCI_MACV_N4 (volatile unsigned int *)((0x1b34 << 2) + 0xff900000) ++#define ENCI_MACV_N5 (0x1b35) ++#define P_ENCI_MACV_N5 (volatile unsigned int *)((0x1b35 << 2) + 0xff900000) ++#define ENCI_MACV_N6 (0x1b36) ++#define P_ENCI_MACV_N6 (volatile unsigned int *)((0x1b36 << 2) + 0xff900000) ++#define ENCI_MACV_N7 (0x1b37) ++#define P_ENCI_MACV_N7 (volatile unsigned int *)((0x1b37 << 2) + 0xff900000) ++#define ENCI_MACV_N8 (0x1b38) ++#define P_ENCI_MACV_N8 (volatile unsigned int *)((0x1b38 << 2) + 0xff900000) ++#define ENCI_MACV_N9 (0x1b39) ++#define P_ENCI_MACV_N9 (volatile unsigned int *)((0x1b39 << 2) + 0xff900000) ++#define ENCI_MACV_N10 (0x1b3a) ++#define P_ENCI_MACV_N10 (volatile unsigned int *)((0x1b3a << 2) + 0xff900000) ++#define ENCI_MACV_N11 (0x1b3b) ++#define P_ENCI_MACV_N11 (volatile unsigned int *)((0x1b3b << 2) + 0xff900000) ++#define ENCI_MACV_N12 (0x1b3c) ++#define P_ENCI_MACV_N12 (volatile unsigned int *)((0x1b3c << 2) + 0xff900000) ++#define ENCI_MACV_N13 (0x1b3d) ++#define P_ENCI_MACV_N13 (volatile unsigned int *)((0x1b3d << 2) + 0xff900000) ++#define ENCI_MACV_N14 (0x1b3e) ++#define P_ENCI_MACV_N14 (volatile unsigned int *)((0x1b3e << 2) + 0xff900000) ++#define ENCI_MACV_N15 (0x1b3f) ++#define P_ENCI_MACV_N15 (volatile unsigned int *)((0x1b3f << 2) + 0xff900000) ++#define ENCI_MACV_N16 (0x1b40) ++#define P_ENCI_MACV_N16 (volatile unsigned int *)((0x1b40 << 2) + 0xff900000) ++#define ENCI_MACV_N17 (0x1b41) ++#define P_ENCI_MACV_N17 (volatile unsigned int *)((0x1b41 << 2) + 0xff900000) ++#define ENCI_MACV_N18 (0x1b42) ++#define P_ENCI_MACV_N18 (volatile unsigned int *)((0x1b42 << 2) + 0xff900000) ++#define ENCI_MACV_N19 (0x1b43) ++#define P_ENCI_MACV_N19 (volatile unsigned int *)((0x1b43 << 2) + 0xff900000) ++#define ENCI_MACV_N20 (0x1b44) ++#define P_ENCI_MACV_N20 (volatile unsigned int *)((0x1b44 << 2) + 0xff900000) ++#define ENCI_MACV_N21 (0x1b45) ++#define P_ENCI_MACV_N21 (volatile unsigned int *)((0x1b45 << 2) + 0xff900000) ++#define ENCI_MACV_N22 (0x1b46) ++#define P_ENCI_MACV_N22 (volatile unsigned int *)((0x1b46 << 2) + 0xff900000) ++//`define ENCI_MACV_P_AGC 8'h47 ++#define ENCI_DBG_PX_RST (0x1b48) ++#define P_ENCI_DBG_PX_RST (volatile unsigned int *)((0x1b48 << 2) + 0xff900000) ++#define ENCI_DBG_FLDLN_RST (0x1b49) ++#define P_ENCI_DBG_FLDLN_RST (volatile unsigned int *)((0x1b49 << 2) + 0xff900000) ++#define ENCI_DBG_PX_INT (0x1b4a) ++#define P_ENCI_DBG_PX_INT (volatile unsigned int *)((0x1b4a << 2) + 0xff900000) ++#define ENCI_DBG_FLDLN_INT (0x1b4b) ++#define P_ENCI_DBG_FLDLN_INT (volatile unsigned int *)((0x1b4b << 2) + 0xff900000) ++#define ENCI_DBG_MAXPX (0x1b4c) ++#define P_ENCI_DBG_MAXPX (volatile unsigned int *)((0x1b4c << 2) + 0xff900000) ++#define ENCI_DBG_MAXLN (0x1b4d) ++#define P_ENCI_DBG_MAXLN (volatile unsigned int *)((0x1b4d << 2) + 0xff900000) ++#define ENCI_MACV_MAX_AMP (0x1b50) ++#define P_ENCI_MACV_MAX_AMP (volatile unsigned int *)((0x1b50 << 2) + 0xff900000) ++#define ENCI_MACV_PULSE_LO (0x1b51) ++#define P_ENCI_MACV_PULSE_LO (volatile unsigned int *)((0x1b51 << 2) + 0xff900000) ++#define ENCI_MACV_PULSE_HI (0x1b52) ++#define P_ENCI_MACV_PULSE_HI (volatile unsigned int *)((0x1b52 << 2) + 0xff900000) ++#define ENCI_MACV_BKP_MAX (0x1b53) ++#define P_ENCI_MACV_BKP_MAX (volatile unsigned int *)((0x1b53 << 2) + 0xff900000) ++#define ENCI_CFILT_CTRL (0x1b54) ++#define P_ENCI_CFILT_CTRL (volatile unsigned int *)((0x1b54 << 2) + 0xff900000) ++#define ENCI_CFILT7 (0x1b55) ++#define P_ENCI_CFILT7 (volatile unsigned int *)((0x1b55 << 2) + 0xff900000) ++#define ENCI_YC_DELAY (0x1b56) ++#define P_ENCI_YC_DELAY (volatile unsigned int *)((0x1b56 << 2) + 0xff900000) ++#define ENCI_VIDEO_EN (0x1b57) ++#define P_ENCI_VIDEO_EN (volatile unsigned int *)((0x1b57 << 2) + 0xff900000) ++// ++// Closing file: enci_regs.h ++// ++//`define VENC2_VCBUS_BASE 8'h1c ++// ++// Reading file: venc2_regs.h ++// ++//=========================================================================== ++// Venc Registers (Cont.) 0xc00 - 0xcff (VENC registers 0xc00 - 0xcef) ++//=========================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: VENC2_VCBUS_BASE = 0x1c ++// ----------------------------------------------- ++// Program video control signals from ENCI core to DVI/HDMI interface ++#define ENCI_DVI_HSO_BEGIN (0x1c00) ++#define P_ENCI_DVI_HSO_BEGIN (volatile unsigned int *)((0x1c00 << 2) + 0xff900000) ++#define ENCI_DVI_HSO_END (0x1c01) ++#define P_ENCI_DVI_HSO_END (volatile unsigned int *)((0x1c01 << 2) + 0xff900000) ++#define ENCI_DVI_VSO_BLINE_EVN (0x1c02) ++#define P_ENCI_DVI_VSO_BLINE_EVN (volatile unsigned int *)((0x1c02 << 2) + 0xff900000) ++#define ENCI_DVI_VSO_BLINE_ODD (0x1c03) ++#define P_ENCI_DVI_VSO_BLINE_ODD (volatile unsigned int *)((0x1c03 << 2) + 0xff900000) ++#define ENCI_DVI_VSO_ELINE_EVN (0x1c04) ++#define P_ENCI_DVI_VSO_ELINE_EVN (volatile unsigned int *)((0x1c04 << 2) + 0xff900000) ++#define ENCI_DVI_VSO_ELINE_ODD (0x1c05) ++#define P_ENCI_DVI_VSO_ELINE_ODD (volatile unsigned int *)((0x1c05 << 2) + 0xff900000) ++#define ENCI_DVI_VSO_BEGIN_EVN (0x1c06) ++#define P_ENCI_DVI_VSO_BEGIN_EVN (volatile unsigned int *)((0x1c06 << 2) + 0xff900000) ++#define ENCI_DVI_VSO_BEGIN_ODD (0x1c07) ++#define P_ENCI_DVI_VSO_BEGIN_ODD (volatile unsigned int *)((0x1c07 << 2) + 0xff900000) ++#define ENCI_DVI_VSO_END_EVN (0x1c08) ++#define P_ENCI_DVI_VSO_END_EVN (volatile unsigned int *)((0x1c08 << 2) + 0xff900000) ++#define ENCI_DVI_VSO_END_ODD (0x1c09) ++#define P_ENCI_DVI_VSO_END_ODD (volatile unsigned int *)((0x1c09 << 2) + 0xff900000) ++// Define cmpt and cvbs cb/cr delay after ENCI chroma filters ++// Bit 15:12 RW, enci_cb_cvbs_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved. ++// Bit 11: 8 RW, enci_cr_cvbs_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved. ++// Bit 7: 4 RW, enci_cb_cmpt_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved. ++// Bit 3: 0 RW, enci_cr_cmpt_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved. ++#define ENCI_CFILT_CTRL2 (0x1c0a) ++#define P_ENCI_CFILT_CTRL2 (volatile unsigned int *)((0x1c0a << 2) + 0xff900000) ++#define ENCI_DACSEL_0 (0x1c0b) ++#define P_ENCI_DACSEL_0 (volatile unsigned int *)((0x1c0b << 2) + 0xff900000) ++#define ENCI_DACSEL_1 (0x1c0c) ++#define P_ENCI_DACSEL_1 (volatile unsigned int *)((0x1c0c << 2) + 0xff900000) ++#define ENCP_DACSEL_0 (0x1c0d) ++#define P_ENCP_DACSEL_0 (volatile unsigned int *)((0x1c0d << 2) + 0xff900000) ++#define ENCP_DACSEL_1 (0x1c0e) ++#define P_ENCP_DACSEL_1 (volatile unsigned int *)((0x1c0e << 2) + 0xff900000) ++#define ENCP_MAX_LINE_SWITCH_POINT (0x1c0f) ++#define P_ENCP_MAX_LINE_SWITCH_POINT (volatile unsigned int *)((0x1c0f << 2) + 0xff900000) ++#define ENCI_TST_EN (0x1c10) ++#define P_ENCI_TST_EN (volatile unsigned int *)((0x1c10 << 2) + 0xff900000) ++#define ENCI_TST_MDSEL (0x1c11) ++#define P_ENCI_TST_MDSEL (volatile unsigned int *)((0x1c11 << 2) + 0xff900000) ++#define ENCI_TST_Y (0x1c12) ++#define P_ENCI_TST_Y (volatile unsigned int *)((0x1c12 << 2) + 0xff900000) ++#define ENCI_TST_CB (0x1c13) ++#define P_ENCI_TST_CB (volatile unsigned int *)((0x1c13 << 2) + 0xff900000) ++#define ENCI_TST_CR (0x1c14) ++#define P_ENCI_TST_CR (volatile unsigned int *)((0x1c14 << 2) + 0xff900000) ++#define ENCI_TST_CLRBAR_STRT (0x1c15) ++#define P_ENCI_TST_CLRBAR_STRT (volatile unsigned int *)((0x1c15 << 2) + 0xff900000) ++#define ENCI_TST_CLRBAR_WIDTH (0x1c16) ++#define P_ENCI_TST_CLRBAR_WIDTH (volatile unsigned int *)((0x1c16 << 2) + 0xff900000) ++#define ENCI_TST_VDCNT_STSET (0x1c17) ++#define P_ENCI_TST_VDCNT_STSET (volatile unsigned int *)((0x1c17 << 2) + 0xff900000) ++// bit 15:8 -- vfifo2vd_vd_sel ++// bit 7 -- vfifo2vd_drop ++// bit 6:1 -- vfifo2vd_delay ++// bit 0 -- vfifo2vd_en ++#define ENCI_VFIFO2VD_CTL (0x1c18) ++#define P_ENCI_VFIFO2VD_CTL (volatile unsigned int *)((0x1c18 << 2) + 0xff900000) ++// bit 12:0 -- vfifo2vd_pixel_start ++#define ENCI_VFIFO2VD_PIXEL_START (0x1c19) ++#define P_ENCI_VFIFO2VD_PIXEL_START (volatile unsigned int *)((0x1c19 << 2) + 0xff900000) ++// bit 12:00 -- vfifo2vd_pixel_end ++#define ENCI_VFIFO2VD_PIXEL_END (0x1c1a) ++#define P_ENCI_VFIFO2VD_PIXEL_END (volatile unsigned int *)((0x1c1a << 2) + 0xff900000) ++// bit 10:0 -- vfifo2vd_line_top_start ++#define ENCI_VFIFO2VD_LINE_TOP_START (0x1c1b) ++#define P_ENCI_VFIFO2VD_LINE_TOP_START (volatile unsigned int *)((0x1c1b << 2) + 0xff900000) ++// bit 10:00 -- vfifo2vd_line_top_end ++#define ENCI_VFIFO2VD_LINE_TOP_END (0x1c1c) ++#define P_ENCI_VFIFO2VD_LINE_TOP_END (volatile unsigned int *)((0x1c1c << 2) + 0xff900000) ++// bit 10:00 -- vfifo2vd_line_bot_start ++#define ENCI_VFIFO2VD_LINE_BOT_START (0x1c1d) ++#define P_ENCI_VFIFO2VD_LINE_BOT_START (volatile unsigned int *)((0x1c1d << 2) + 0xff900000) ++// bit 10:00 -- vfifo2vd_line_bot_end ++#define ENCI_VFIFO2VD_LINE_BOT_END (0x1c1e) ++#define P_ENCI_VFIFO2VD_LINE_BOT_END (volatile unsigned int *)((0x1c1e << 2) + 0xff900000) ++#define ENCI_VFIFO2VD_CTL2 (0x1c1f) ++#define P_ENCI_VFIFO2VD_CTL2 (volatile unsigned int *)((0x1c1f << 2) + 0xff900000) ++// bit 15:8 -- vfifo2vd_vd_sel ++// bit 7 -- vfifo2vd_drop ++// bit 6:1 -- vfifo2vd_delay ++// bit 0 -- vfifo2vd_en ++#define ENCT_VFIFO2VD_CTL (0x1c20) ++#define P_ENCT_VFIFO2VD_CTL (volatile unsigned int *)((0x1c20 << 2) + 0xff900000) ++// bit 12:0 -- vfifo2vd_pixel_start ++#define ENCT_VFIFO2VD_PIXEL_START (0x1c21) ++#define P_ENCT_VFIFO2VD_PIXEL_START (volatile unsigned int *)((0x1c21 << 2) + 0xff900000) ++// bit 12:00 -- vfifo2vd_pixel_end ++#define ENCT_VFIFO2VD_PIXEL_END (0x1c22) ++#define P_ENCT_VFIFO2VD_PIXEL_END (volatile unsigned int *)((0x1c22 << 2) + 0xff900000) ++// bit 10:0 -- vfifo2vd_line_top_start ++#define ENCT_VFIFO2VD_LINE_TOP_START (0x1c23) ++#define P_ENCT_VFIFO2VD_LINE_TOP_START (volatile unsigned int *)((0x1c23 << 2) + 0xff900000) ++// bit 10:00 -- vfifo2vd_line_top_end ++#define ENCT_VFIFO2VD_LINE_TOP_END (0x1c24) ++#define P_ENCT_VFIFO2VD_LINE_TOP_END (volatile unsigned int *)((0x1c24 << 2) + 0xff900000) ++// bit 10:00 -- vfifo2vd_line_bot_start ++#define ENCT_VFIFO2VD_LINE_BOT_START (0x1c25) ++#define P_ENCT_VFIFO2VD_LINE_BOT_START (volatile unsigned int *)((0x1c25 << 2) + 0xff900000) ++// bit 10:00 -- vfifo2vd_line_bot_end ++#define ENCT_VFIFO2VD_LINE_BOT_END (0x1c26) ++#define P_ENCT_VFIFO2VD_LINE_BOT_END (volatile unsigned int *)((0x1c26 << 2) + 0xff900000) ++#define ENCT_VFIFO2VD_CTL2 (0x1c27) ++#define P_ENCT_VFIFO2VD_CTL2 (volatile unsigned int *)((0x1c27 << 2) + 0xff900000) ++#define ENCT_TST_EN (0x1c28) ++#define P_ENCT_TST_EN (volatile unsigned int *)((0x1c28 << 2) + 0xff900000) ++#define ENCT_TST_MDSEL (0x1c29) ++#define P_ENCT_TST_MDSEL (volatile unsigned int *)((0x1c29 << 2) + 0xff900000) ++#define ENCT_TST_Y (0x1c2a) ++#define P_ENCT_TST_Y (volatile unsigned int *)((0x1c2a << 2) + 0xff900000) ++#define ENCT_TST_CB (0x1c2b) ++#define P_ENCT_TST_CB (volatile unsigned int *)((0x1c2b << 2) + 0xff900000) ++#define ENCT_TST_CR (0x1c2c) ++#define P_ENCT_TST_CR (volatile unsigned int *)((0x1c2c << 2) + 0xff900000) ++#define ENCT_TST_CLRBAR_STRT (0x1c2d) ++#define P_ENCT_TST_CLRBAR_STRT (volatile unsigned int *)((0x1c2d << 2) + 0xff900000) ++#define ENCT_TST_CLRBAR_WIDTH (0x1c2e) ++#define P_ENCT_TST_CLRBAR_WIDTH (volatile unsigned int *)((0x1c2e << 2) + 0xff900000) ++#define ENCT_TST_VDCNT_STSET (0x1c2f) ++#define P_ENCT_TST_VDCNT_STSET (volatile unsigned int *)((0x1c2f << 2) + 0xff900000) ++// Program video control signals from ENCP core to DVI/HDMI interface ++#define ENCP_DVI_HSO_BEGIN (0x1c30) ++#define P_ENCP_DVI_HSO_BEGIN (volatile unsigned int *)((0x1c30 << 2) + 0xff900000) ++#define ENCP_DVI_HSO_END (0x1c31) ++#define P_ENCP_DVI_HSO_END (volatile unsigned int *)((0x1c31 << 2) + 0xff900000) ++#define ENCP_DVI_VSO_BLINE_EVN (0x1c32) ++#define P_ENCP_DVI_VSO_BLINE_EVN (volatile unsigned int *)((0x1c32 << 2) + 0xff900000) ++#define ENCP_DVI_VSO_BLINE_ODD (0x1c33) ++#define P_ENCP_DVI_VSO_BLINE_ODD (volatile unsigned int *)((0x1c33 << 2) + 0xff900000) ++#define ENCP_DVI_VSO_ELINE_EVN (0x1c34) ++#define P_ENCP_DVI_VSO_ELINE_EVN (volatile unsigned int *)((0x1c34 << 2) + 0xff900000) ++#define ENCP_DVI_VSO_ELINE_ODD (0x1c35) ++#define P_ENCP_DVI_VSO_ELINE_ODD (volatile unsigned int *)((0x1c35 << 2) + 0xff900000) ++#define ENCP_DVI_VSO_BEGIN_EVN (0x1c36) ++#define P_ENCP_DVI_VSO_BEGIN_EVN (volatile unsigned int *)((0x1c36 << 2) + 0xff900000) ++#define ENCP_DVI_VSO_BEGIN_ODD (0x1c37) ++#define P_ENCP_DVI_VSO_BEGIN_ODD (volatile unsigned int *)((0x1c37 << 2) + 0xff900000) ++#define ENCP_DVI_VSO_END_EVN (0x1c38) ++#define P_ENCP_DVI_VSO_END_EVN (volatile unsigned int *)((0x1c38 << 2) + 0xff900000) ++#define ENCP_DVI_VSO_END_ODD (0x1c39) ++#define P_ENCP_DVI_VSO_END_ODD (volatile unsigned int *)((0x1c39 << 2) + 0xff900000) ++#define ENCP_DE_H_BEGIN (0x1c3a) ++#define P_ENCP_DE_H_BEGIN (volatile unsigned int *)((0x1c3a << 2) + 0xff900000) ++#define ENCP_DE_H_END (0x1c3b) ++#define P_ENCP_DE_H_END (volatile unsigned int *)((0x1c3b << 2) + 0xff900000) ++#define ENCP_DE_V_BEGIN_EVEN (0x1c3c) ++#define P_ENCP_DE_V_BEGIN_EVEN (volatile unsigned int *)((0x1c3c << 2) + 0xff900000) ++#define ENCP_DE_V_END_EVEN (0x1c3d) ++#define P_ENCP_DE_V_END_EVEN (volatile unsigned int *)((0x1c3d << 2) + 0xff900000) ++#define ENCP_DE_V_BEGIN_ODD (0x1c3e) ++#define P_ENCP_DE_V_BEGIN_ODD (volatile unsigned int *)((0x1c3e << 2) + 0xff900000) ++#define ENCP_DE_V_END_ODD (0x1c3f) ++#define P_ENCP_DE_V_END_ODD (volatile unsigned int *)((0x1c3f << 2) + 0xff900000) ++// Bit 15:11 - sync length ++// Bit 10:0 - sync start line ++#define ENCI_SYNC_LINE_LENGTH (0x1c40) ++#define P_ENCI_SYNC_LINE_LENGTH (volatile unsigned int *)((0x1c40 << 2) + 0xff900000) ++// Bit 15 - sync_pulse_enable ++// Bit 12:0 - sync start pixel ++#define ENCI_SYNC_PIXEL_EN (0x1c41) ++#define P_ENCI_SYNC_PIXEL_EN (volatile unsigned int *)((0x1c41 << 2) + 0xff900000) ++// Bit 15 - enci_sync_enable ++// Bit 14 - encp_sync_enable ++// Bit 13 - enct_sync_enable ++// Bit 12 - short_fussy_sync ++// Bit 11 - fussy_sync_enable ++// Bit 10:0 - sync target line ++#define ENCI_SYNC_TO_LINE_EN (0x1c42) ++#define P_ENCI_SYNC_TO_LINE_EN (volatile unsigned int *)((0x1c42 << 2) + 0xff900000) ++// Bit 12:0 - sync target pixel ++#define ENCI_SYNC_TO_PIXEL (0x1c43) ++#define P_ENCI_SYNC_TO_PIXEL (volatile unsigned int *)((0x1c43 << 2) + 0xff900000) ++// Bit 15:11 - sync length ++// Bit 10:0 - sync start line ++#define ENCP_SYNC_LINE_LENGTH (0x1c44) ++#define P_ENCP_SYNC_LINE_LENGTH (volatile unsigned int *)((0x1c44 << 2) + 0xff900000) ++// Bit 15 - sync_pulse_enable ++// Bit 12:0 - sync start pixel ++#define ENCP_SYNC_PIXEL_EN (0x1c45) ++#define P_ENCP_SYNC_PIXEL_EN (volatile unsigned int *)((0x1c45 << 2) + 0xff900000) ++// Bit 15 - enci_sync_enable ++// Bit 14 - encp_sync_enable ++// Bit 13 - enct_sync_enable ++// Bit 12 - short_fussy_sync ++// Bit 11 - fussy_sync_enable ++// Bit 10:0 - sync target line ++#define ENCP_SYNC_TO_LINE_EN (0x1c46) ++#define P_ENCP_SYNC_TO_LINE_EN (volatile unsigned int *)((0x1c46 << 2) + 0xff900000) ++// Bit 12:0 - sync target pixel ++#define ENCP_SYNC_TO_PIXEL (0x1c47) ++#define P_ENCP_SYNC_TO_PIXEL (volatile unsigned int *)((0x1c47 << 2) + 0xff900000) ++// Bit 15:11 - sync length ++// Bit 10:0 - sync start line ++#define ENCT_SYNC_LINE_LENGTH (0x1c48) ++#define P_ENCT_SYNC_LINE_LENGTH (volatile unsigned int *)((0x1c48 << 2) + 0xff900000) ++// Bit 15 - sync_pulse_enable ++// Bit 12:0 - sync start pixel ++#define ENCT_SYNC_PIXEL_EN (0x1c49) ++#define P_ENCT_SYNC_PIXEL_EN (volatile unsigned int *)((0x1c49 << 2) + 0xff900000) ++// Bit 15 - enci_sync_enable ++// Bit 14 - encp_sync_enable ++// Bit 13 - enct_sync_enable ++// Bit 12 - short_fussy_sync ++// Bit 11 - fussy_sync_enable ++// Bit 10:0 - sync target line ++#define ENCT_SYNC_TO_LINE_EN (0x1c4a) ++#define P_ENCT_SYNC_TO_LINE_EN (volatile unsigned int *)((0x1c4a << 2) + 0xff900000) ++// Bit 12:0 - sync target pixel ++#define ENCT_SYNC_TO_PIXEL (0x1c4b) ++#define P_ENCT_SYNC_TO_PIXEL (volatile unsigned int *)((0x1c4b << 2) + 0xff900000) ++// Bit 15:11 - sync length ++// Bit 10:0 - sync start line ++#define ENCL_SYNC_LINE_LENGTH (0x1c4c) ++#define P_ENCL_SYNC_LINE_LENGTH (volatile unsigned int *)((0x1c4c << 2) + 0xff900000) ++// Bit 15 - sync_pulse_enable ++// Bit 12:0 - sync start pixel ++#define ENCL_SYNC_PIXEL_EN (0x1c4d) ++#define P_ENCL_SYNC_PIXEL_EN (volatile unsigned int *)((0x1c4d << 2) + 0xff900000) ++// Bit 15 - enci_sync_enable ++// Bit 14 - encp_sync_enable ++// Bit 13 - enct_sync_enable ++// Bit 12 - short_fussy_sync ++// Bit 11 - fussy_sync_enable ++// Bit 10:0 - sync target line ++#define ENCL_SYNC_TO_LINE_EN (0x1c4e) ++#define P_ENCL_SYNC_TO_LINE_EN (volatile unsigned int *)((0x1c4e << 2) + 0xff900000) ++// Bit 12:0 - sync target pixel ++#define ENCL_SYNC_TO_PIXEL (0x1c4f) ++#define P_ENCL_SYNC_TO_PIXEL (volatile unsigned int *)((0x1c4f << 2) + 0xff900000) ++// bit 3 cfg_encp_lcd_scaler_bypass. 1=Do not scale LCD input data; ++// 0=Scale LCD input data to y [16*4,235*4], c [16*4,240*4]. ++// bit 2 cfg_encp_vadj_scaler_bypass. 1=Do not scale data to enc480p_vadj; ++// 0=Scale enc480p_vadj input data to y [16*4,235*4], c [16*4,240*4]. ++// bit 1 cfg_vfifo2vd_out_scaler_bypass. 1=Do not scale vfifo2vd's output vdata; ++// 0=Scale vfifo2vd's output vdata to y [16,235], c [16,240]. ++// bit 0 cfg_vfifo_din_full_range. 1=Data from viu fifo is full range [0,1023]; ++// 0=Data from viu fifo is y [16*4,235*4], c [16*4,240*4]. ++#define ENCP_VFIFO2VD_CTL2 (0x1c50) ++#define P_ENCP_VFIFO2VD_CTL2 (volatile unsigned int *)((0x1c50 << 2) + 0xff900000) ++// bit 15:1 Reserved. ++// bit 0 cfg_int_dvi_sel_rgb. Applicable for using on-chip hdmi tx module only. This bit controls correct bit-mapping from ++// Venc to hdmi_tx depending on whether YCbCr or RGB mode. ++// 1=Map data bit from Venc to hdmi_tx for RGB mode; ++// 0=Default. Map data bit from Venc to hdmi_tx for YCbCr mode. ++#define VENC_DVI_SETTING_MORE (0x1c51) ++#define P_VENC_DVI_SETTING_MORE (volatile unsigned int *)((0x1c51 << 2) + 0xff900000) ++#define VENC_VDAC_DAC4_FILT_CTRL0 (0x1c54) ++#define P_VENC_VDAC_DAC4_FILT_CTRL0 (volatile unsigned int *)((0x1c54 << 2) + 0xff900000) ++#define VENC_VDAC_DAC4_FILT_CTRL1 (0x1c55) ++#define P_VENC_VDAC_DAC4_FILT_CTRL1 (volatile unsigned int *)((0x1c55 << 2) + 0xff900000) ++#define VENC_VDAC_DAC5_FILT_CTRL0 (0x1c56) ++#define P_VENC_VDAC_DAC5_FILT_CTRL0 (volatile unsigned int *)((0x1c56 << 2) + 0xff900000) ++#define VENC_VDAC_DAC5_FILT_CTRL1 (0x1c57) ++#define P_VENC_VDAC_DAC5_FILT_CTRL1 (volatile unsigned int *)((0x1c57 << 2) + 0xff900000) ++//Bit 0 filter_en ++#define VENC_VDAC_DAC0_FILT_CTRL0 (0x1c58) ++#define P_VENC_VDAC_DAC0_FILT_CTRL0 (volatile unsigned int *)((0x1c58 << 2) + 0xff900000) ++//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6 ++//Bit 15:8, coef1, ++//Bit 7:0, coef0, ++#define VENC_VDAC_DAC0_FILT_CTRL1 (0x1c59) ++#define P_VENC_VDAC_DAC0_FILT_CTRL1 (volatile unsigned int *)((0x1c59 << 2) + 0xff900000) ++//Bit 0 filter_en ++#define VENC_VDAC_DAC1_FILT_CTRL0 (0x1c5a) ++#define P_VENC_VDAC_DAC1_FILT_CTRL0 (volatile unsigned int *)((0x1c5a << 2) + 0xff900000) ++//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6 ++//Bit 15:8, coef1, ++//Bit 7:0, coef0, ++#define VENC_VDAC_DAC1_FILT_CTRL1 (0x1c5b) ++#define P_VENC_VDAC_DAC1_FILT_CTRL1 (volatile unsigned int *)((0x1c5b << 2) + 0xff900000) ++//Bit 0 filter_en ++#define VENC_VDAC_DAC2_FILT_CTRL0 (0x1c5c) ++#define P_VENC_VDAC_DAC2_FILT_CTRL0 (volatile unsigned int *)((0x1c5c << 2) + 0xff900000) ++//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6 ++//Bit 15:8, coef1, ++//Bit 7:0, coef0, ++#define VENC_VDAC_DAC2_FILT_CTRL1 (0x1c5d) ++#define P_VENC_VDAC_DAC2_FILT_CTRL1 (volatile unsigned int *)((0x1c5d << 2) + 0xff900000) ++//Bit 0 filter_en ++#define VENC_VDAC_DAC3_FILT_CTRL0 (0x1c5e) ++#define P_VENC_VDAC_DAC3_FILT_CTRL0 (volatile unsigned int *)((0x1c5e << 2) + 0xff900000) ++//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6 ++//Bit 15:8, coef1, ++//Bit 7:0, coef0, ++#define VENC_VDAC_DAC3_FILT_CTRL1 (0x1c5f) ++#define P_VENC_VDAC_DAC3_FILT_CTRL1 (volatile unsigned int *)((0x1c5f << 2) + 0xff900000) ++//=========================================================================== ++// ENCT registers ++#define ENCT_VIDEO_EN (0x1c60) ++#define P_ENCT_VIDEO_EN (volatile unsigned int *)((0x1c60 << 2) + 0xff900000) ++#define ENCT_VIDEO_Y_SCL (0x1c61) ++#define P_ENCT_VIDEO_Y_SCL (volatile unsigned int *)((0x1c61 << 2) + 0xff900000) ++#define ENCT_VIDEO_PB_SCL (0x1c62) ++#define P_ENCT_VIDEO_PB_SCL (volatile unsigned int *)((0x1c62 << 2) + 0xff900000) ++#define ENCT_VIDEO_PR_SCL (0x1c63) ++#define P_ENCT_VIDEO_PR_SCL (volatile unsigned int *)((0x1c63 << 2) + 0xff900000) ++#define ENCT_VIDEO_Y_OFFST (0x1c64) ++#define P_ENCT_VIDEO_Y_OFFST (volatile unsigned int *)((0x1c64 << 2) + 0xff900000) ++#define ENCT_VIDEO_PB_OFFST (0x1c65) ++#define P_ENCT_VIDEO_PB_OFFST (volatile unsigned int *)((0x1c65 << 2) + 0xff900000) ++#define ENCT_VIDEO_PR_OFFST (0x1c66) ++#define P_ENCT_VIDEO_PR_OFFST (volatile unsigned int *)((0x1c66 << 2) + 0xff900000) ++//----- Video mode ++#define ENCT_VIDEO_MODE (0x1c67) ++#define P_ENCT_VIDEO_MODE (volatile unsigned int *)((0x1c67 << 2) + 0xff900000) ++#define ENCT_VIDEO_MODE_ADV (0x1c68) ++#define P_ENCT_VIDEO_MODE_ADV (volatile unsigned int *)((0x1c68 << 2) + 0xff900000) ++//--------------- Debug pins ++#define ENCT_DBG_PX_RST (0x1c69) ++#define P_ENCT_DBG_PX_RST (volatile unsigned int *)((0x1c69 << 2) + 0xff900000) ++#define ENCT_DBG_LN_RST (0x1c6a) ++#define P_ENCT_DBG_LN_RST (volatile unsigned int *)((0x1c6a << 2) + 0xff900000) ++#define ENCT_DBG_PX_INT (0x1c6b) ++#define P_ENCT_DBG_PX_INT (volatile unsigned int *)((0x1c6b << 2) + 0xff900000) ++#define ENCT_DBG_LN_INT (0x1c6c) ++#define P_ENCT_DBG_LN_INT (volatile unsigned int *)((0x1c6c << 2) + 0xff900000) ++//----------- Video Advanced setting ++#define ENCT_VIDEO_YFP1_HTIME (0x1c6d) ++#define P_ENCT_VIDEO_YFP1_HTIME (volatile unsigned int *)((0x1c6d << 2) + 0xff900000) ++#define ENCT_VIDEO_YFP2_HTIME (0x1c6e) ++#define P_ENCT_VIDEO_YFP2_HTIME (volatile unsigned int *)((0x1c6e << 2) + 0xff900000) ++#define ENCT_VIDEO_YC_DLY (0x1c6f) ++#define P_ENCT_VIDEO_YC_DLY (volatile unsigned int *)((0x1c6f << 2) + 0xff900000) ++#define ENCT_VIDEO_MAX_PXCNT (0x1c70) ++#define P_ENCT_VIDEO_MAX_PXCNT (volatile unsigned int *)((0x1c70 << 2) + 0xff900000) ++#define ENCT_VIDEO_HAVON_END (0x1c71) ++#define P_ENCT_VIDEO_HAVON_END (volatile unsigned int *)((0x1c71 << 2) + 0xff900000) ++#define ENCT_VIDEO_HAVON_BEGIN (0x1c72) ++#define P_ENCT_VIDEO_HAVON_BEGIN (volatile unsigned int *)((0x1c72 << 2) + 0xff900000) ++#define ENCT_VIDEO_VAVON_ELINE (0x1c73) ++#define P_ENCT_VIDEO_VAVON_ELINE (volatile unsigned int *)((0x1c73 << 2) + 0xff900000) ++#define ENCT_VIDEO_VAVON_BLINE (0x1c74) ++#define P_ENCT_VIDEO_VAVON_BLINE (volatile unsigned int *)((0x1c74 << 2) + 0xff900000) ++#define ENCT_VIDEO_HSO_BEGIN (0x1c75) ++#define P_ENCT_VIDEO_HSO_BEGIN (volatile unsigned int *)((0x1c75 << 2) + 0xff900000) ++#define ENCT_VIDEO_HSO_END (0x1c76) ++#define P_ENCT_VIDEO_HSO_END (volatile unsigned int *)((0x1c76 << 2) + 0xff900000) ++#define ENCT_VIDEO_VSO_BEGIN (0x1c77) ++#define P_ENCT_VIDEO_VSO_BEGIN (volatile unsigned int *)((0x1c77 << 2) + 0xff900000) ++#define ENCT_VIDEO_VSO_END (0x1c78) ++#define P_ENCT_VIDEO_VSO_END (volatile unsigned int *)((0x1c78 << 2) + 0xff900000) ++#define ENCT_VIDEO_VSO_BLINE (0x1c79) ++#define P_ENCT_VIDEO_VSO_BLINE (volatile unsigned int *)((0x1c79 << 2) + 0xff900000) ++#define ENCT_VIDEO_VSO_ELINE (0x1c7a) ++#define P_ENCT_VIDEO_VSO_ELINE (volatile unsigned int *)((0x1c7a << 2) + 0xff900000) ++#define ENCT_VIDEO_MAX_LNCNT (0x1c7b) ++#define P_ENCT_VIDEO_MAX_LNCNT (volatile unsigned int *)((0x1c7b << 2) + 0xff900000) ++#define ENCT_VIDEO_BLANKY_VAL (0x1c7c) ++#define P_ENCT_VIDEO_BLANKY_VAL (volatile unsigned int *)((0x1c7c << 2) + 0xff900000) ++#define ENCT_VIDEO_BLANKPB_VAL (0x1c7d) ++#define P_ENCT_VIDEO_BLANKPB_VAL (volatile unsigned int *)((0x1c7d << 2) + 0xff900000) ++#define ENCT_VIDEO_BLANKPR_VAL (0x1c7e) ++#define P_ENCT_VIDEO_BLANKPR_VAL (volatile unsigned int *)((0x1c7e << 2) + 0xff900000) ++#define ENCT_VIDEO_HOFFST (0x1c7f) ++#define P_ENCT_VIDEO_HOFFST (volatile unsigned int *)((0x1c7f << 2) + 0xff900000) ++#define ENCT_VIDEO_VOFFST (0x1c80) ++#define P_ENCT_VIDEO_VOFFST (volatile unsigned int *)((0x1c80 << 2) + 0xff900000) ++#define ENCT_VIDEO_RGB_CTRL (0x1c81) ++#define P_ENCT_VIDEO_RGB_CTRL (volatile unsigned int *)((0x1c81 << 2) + 0xff900000) ++#define ENCT_VIDEO_FILT_CTRL (0x1c82) ++#define P_ENCT_VIDEO_FILT_CTRL (volatile unsigned int *)((0x1c82 << 2) + 0xff900000) ++#define ENCT_VIDEO_OFLD_VPEQ_OFST (0x1c83) ++#define P_ENCT_VIDEO_OFLD_VPEQ_OFST (volatile unsigned int *)((0x1c83 << 2) + 0xff900000) ++#define ENCT_VIDEO_OFLD_VOAV_OFST (0x1c84) ++#define P_ENCT_VIDEO_OFLD_VOAV_OFST (volatile unsigned int *)((0x1c84 << 2) + 0xff900000) ++#define ENCT_VIDEO_MATRIX_CB (0x1c85) ++#define P_ENCT_VIDEO_MATRIX_CB (volatile unsigned int *)((0x1c85 << 2) + 0xff900000) ++#define ENCT_VIDEO_MATRIX_CR (0x1c86) ++#define P_ENCT_VIDEO_MATRIX_CR (volatile unsigned int *)((0x1c86 << 2) + 0xff900000) ++#define ENCT_VIDEO_RGBIN_CTRL (0x1c87) ++#define P_ENCT_VIDEO_RGBIN_CTRL (volatile unsigned int *)((0x1c87 << 2) + 0xff900000) ++#define ENCT_MAX_LINE_SWITCH_POINT (0x1c88) ++#define P_ENCT_MAX_LINE_SWITCH_POINT (volatile unsigned int *)((0x1c88 << 2) + 0xff900000) ++#define ENCT_DACSEL_0 (0x1c89) ++#define P_ENCT_DACSEL_0 (volatile unsigned int *)((0x1c89 << 2) + 0xff900000) ++#define ENCT_DACSEL_1 (0x1c8a) ++#define P_ENCT_DACSEL_1 (volatile unsigned int *)((0x1c8a << 2) + 0xff900000) ++//=========================================================================== ++// For ENCL ++//=========================================================================== ++// bit 15:8 -- vfifo2vd_vd_sel ++// bit 7 -- vfifo2vd_drop ++// bit 6:1 -- vfifo2vd_delay ++// bit 0 -- vfifo2vd_en ++#define ENCL_VFIFO2VD_CTL (0x1c90) ++#define P_ENCL_VFIFO2VD_CTL (volatile unsigned int *)((0x1c90 << 2) + 0xff900000) ++// bit 12:0 -- vfifo2vd_pixel_start ++#define ENCL_VFIFO2VD_PIXEL_START (0x1c91) ++#define P_ENCL_VFIFO2VD_PIXEL_START (volatile unsigned int *)((0x1c91 << 2) + 0xff900000) ++// bit 12:00 -- vfifo2vd_pixel_end ++#define ENCL_VFIFO2VD_PIXEL_END (0x1c92) ++#define P_ENCL_VFIFO2VD_PIXEL_END (volatile unsigned int *)((0x1c92 << 2) + 0xff900000) ++// bit 10:0 -- vfifo2vd_line_top_start ++#define ENCL_VFIFO2VD_LINE_TOP_START (0x1c93) ++#define P_ENCL_VFIFO2VD_LINE_TOP_START (volatile unsigned int *)((0x1c93 << 2) + 0xff900000) ++// bit 10:00 -- vfifo2vd_line_top_end ++#define ENCL_VFIFO2VD_LINE_TOP_END (0x1c94) ++#define P_ENCL_VFIFO2VD_LINE_TOP_END (volatile unsigned int *)((0x1c94 << 2) + 0xff900000) ++// bit 10:00 -- vfifo2vd_line_bot_start ++#define ENCL_VFIFO2VD_LINE_BOT_START (0x1c95) ++#define P_ENCL_VFIFO2VD_LINE_BOT_START (volatile unsigned int *)((0x1c95 << 2) + 0xff900000) ++// bit 10:00 -- vfifo2vd_line_bot_end ++#define ENCL_VFIFO2VD_LINE_BOT_END (0x1c96) ++#define P_ENCL_VFIFO2VD_LINE_BOT_END (volatile unsigned int *)((0x1c96 << 2) + 0xff900000) ++#define ENCL_VFIFO2VD_CTL2 (0x1c97) ++#define P_ENCL_VFIFO2VD_CTL2 (volatile unsigned int *)((0x1c97 << 2) + 0xff900000) ++#define ENCL_TST_EN (0x1c98) ++#define P_ENCL_TST_EN (volatile unsigned int *)((0x1c98 << 2) + 0xff900000) ++#define ENCL_TST_MDSEL (0x1c99) ++#define P_ENCL_TST_MDSEL (volatile unsigned int *)((0x1c99 << 2) + 0xff900000) ++#define ENCL_TST_Y (0x1c9a) ++#define P_ENCL_TST_Y (volatile unsigned int *)((0x1c9a << 2) + 0xff900000) ++#define ENCL_TST_CB (0x1c9b) ++#define P_ENCL_TST_CB (volatile unsigned int *)((0x1c9b << 2) + 0xff900000) ++#define ENCL_TST_CR (0x1c9c) ++#define P_ENCL_TST_CR (volatile unsigned int *)((0x1c9c << 2) + 0xff900000) ++#define ENCL_TST_CLRBAR_STRT (0x1c9d) ++#define P_ENCL_TST_CLRBAR_STRT (volatile unsigned int *)((0x1c9d << 2) + 0xff900000) ++#define ENCL_TST_CLRBAR_WIDTH (0x1c9e) ++#define P_ENCL_TST_CLRBAR_WIDTH (volatile unsigned int *)((0x1c9e << 2) + 0xff900000) ++#define ENCL_TST_VDCNT_STSET (0x1c9f) ++#define P_ENCL_TST_VDCNT_STSET (volatile unsigned int *)((0x1c9f << 2) + 0xff900000) ++//=========================================================================== ++// ENCL registers ++#define ENCL_VIDEO_EN (0x1ca0) ++#define P_ENCL_VIDEO_EN (volatile unsigned int *)((0x1ca0 << 2) + 0xff900000) ++#define ENCL_VIDEO_Y_SCL (0x1ca1) ++#define P_ENCL_VIDEO_Y_SCL (volatile unsigned int *)((0x1ca1 << 2) + 0xff900000) ++#define ENCL_VIDEO_PB_SCL (0x1ca2) ++#define P_ENCL_VIDEO_PB_SCL (volatile unsigned int *)((0x1ca2 << 2) + 0xff900000) ++#define ENCL_VIDEO_PR_SCL (0x1ca3) ++#define P_ENCL_VIDEO_PR_SCL (volatile unsigned int *)((0x1ca3 << 2) + 0xff900000) ++#define ENCL_VIDEO_Y_OFFST (0x1ca4) ++#define P_ENCL_VIDEO_Y_OFFST (volatile unsigned int *)((0x1ca4 << 2) + 0xff900000) ++#define ENCL_VIDEO_PB_OFFST (0x1ca5) ++#define P_ENCL_VIDEO_PB_OFFST (volatile unsigned int *)((0x1ca5 << 2) + 0xff900000) ++#define ENCL_VIDEO_PR_OFFST (0x1ca6) ++#define P_ENCL_VIDEO_PR_OFFST (volatile unsigned int *)((0x1ca6 << 2) + 0xff900000) ++//----- Video mode ++#define ENCL_VIDEO_MODE (0x1ca7) ++#define P_ENCL_VIDEO_MODE (volatile unsigned int *)((0x1ca7 << 2) + 0xff900000) ++#define ENCL_VIDEO_MODE_ADV (0x1ca8) ++#define P_ENCL_VIDEO_MODE_ADV (volatile unsigned int *)((0x1ca8 << 2) + 0xff900000) ++//--------------- Debug pins ++#define ENCL_DBG_PX_RST (0x1ca9) ++#define P_ENCL_DBG_PX_RST (volatile unsigned int *)((0x1ca9 << 2) + 0xff900000) ++#define ENCL_DBG_LN_RST (0x1caa) ++#define P_ENCL_DBG_LN_RST (volatile unsigned int *)((0x1caa << 2) + 0xff900000) ++#define ENCL_DBG_PX_INT (0x1cab) ++#define P_ENCL_DBG_PX_INT (volatile unsigned int *)((0x1cab << 2) + 0xff900000) ++#define ENCL_DBG_LN_INT (0x1cac) ++#define P_ENCL_DBG_LN_INT (volatile unsigned int *)((0x1cac << 2) + 0xff900000) ++//----------- Video Advanced setting ++#define ENCL_VIDEO_YFP1_HTIME (0x1cad) ++#define P_ENCL_VIDEO_YFP1_HTIME (volatile unsigned int *)((0x1cad << 2) + 0xff900000) ++#define ENCL_VIDEO_YFP2_HTIME (0x1cae) ++#define P_ENCL_VIDEO_YFP2_HTIME (volatile unsigned int *)((0x1cae << 2) + 0xff900000) ++#define ENCL_VIDEO_YC_DLY (0x1caf) ++#define P_ENCL_VIDEO_YC_DLY (volatile unsigned int *)((0x1caf << 2) + 0xff900000) ++#define ENCL_VIDEO_MAX_PXCNT (0x1cb0) ++#define P_ENCL_VIDEO_MAX_PXCNT (volatile unsigned int *)((0x1cb0 << 2) + 0xff900000) ++#define ENCL_VIDEO_HAVON_END (0x1cb1) ++#define P_ENCL_VIDEO_HAVON_END (volatile unsigned int *)((0x1cb1 << 2) + 0xff900000) ++#define ENCL_VIDEO_HAVON_BEGIN (0x1cb2) ++#define P_ENCL_VIDEO_HAVON_BEGIN (volatile unsigned int *)((0x1cb2 << 2) + 0xff900000) ++#define ENCL_VIDEO_VAVON_ELINE (0x1cb3) ++#define P_ENCL_VIDEO_VAVON_ELINE (volatile unsigned int *)((0x1cb3 << 2) + 0xff900000) ++#define ENCL_VIDEO_VAVON_BLINE (0x1cb4) ++#define P_ENCL_VIDEO_VAVON_BLINE (volatile unsigned int *)((0x1cb4 << 2) + 0xff900000) ++#define ENCL_VIDEO_HSO_BEGIN (0x1cb5) ++#define P_ENCL_VIDEO_HSO_BEGIN (volatile unsigned int *)((0x1cb5 << 2) + 0xff900000) ++#define ENCL_VIDEO_HSO_END (0x1cb6) ++#define P_ENCL_VIDEO_HSO_END (volatile unsigned int *)((0x1cb6 << 2) + 0xff900000) ++#define ENCL_VIDEO_VSO_BEGIN (0x1cb7) ++#define P_ENCL_VIDEO_VSO_BEGIN (volatile unsigned int *)((0x1cb7 << 2) + 0xff900000) ++#define ENCL_VIDEO_VSO_END (0x1cb8) ++#define P_ENCL_VIDEO_VSO_END (volatile unsigned int *)((0x1cb8 << 2) + 0xff900000) ++#define ENCL_VIDEO_VSO_BLINE (0x1cb9) ++#define P_ENCL_VIDEO_VSO_BLINE (volatile unsigned int *)((0x1cb9 << 2) + 0xff900000) ++#define ENCL_VIDEO_VSO_ELINE (0x1cba) ++#define P_ENCL_VIDEO_VSO_ELINE (volatile unsigned int *)((0x1cba << 2) + 0xff900000) ++#define ENCL_VIDEO_MAX_LNCNT (0x1cbb) ++#define P_ENCL_VIDEO_MAX_LNCNT (volatile unsigned int *)((0x1cbb << 2) + 0xff900000) ++#define ENCL_VIDEO_BLANKY_VAL (0x1cbc) ++#define P_ENCL_VIDEO_BLANKY_VAL (volatile unsigned int *)((0x1cbc << 2) + 0xff900000) ++#define ENCL_VIDEO_BLANKPB_VAL (0x1cbd) ++#define P_ENCL_VIDEO_BLANKPB_VAL (volatile unsigned int *)((0x1cbd << 2) + 0xff900000) ++#define ENCL_VIDEO_BLANKPR_VAL (0x1cbe) ++#define P_ENCL_VIDEO_BLANKPR_VAL (volatile unsigned int *)((0x1cbe << 2) + 0xff900000) ++#define ENCL_VIDEO_HOFFST (0x1cbf) ++#define P_ENCL_VIDEO_HOFFST (volatile unsigned int *)((0x1cbf << 2) + 0xff900000) ++#define ENCL_VIDEO_VOFFST (0x1cc0) ++#define P_ENCL_VIDEO_VOFFST (volatile unsigned int *)((0x1cc0 << 2) + 0xff900000) ++#define ENCL_VIDEO_RGB_CTRL (0x1cc1) ++#define P_ENCL_VIDEO_RGB_CTRL (volatile unsigned int *)((0x1cc1 << 2) + 0xff900000) ++#define ENCL_VIDEO_FILT_CTRL (0x1cc2) ++#define P_ENCL_VIDEO_FILT_CTRL (volatile unsigned int *)((0x1cc2 << 2) + 0xff900000) ++#define ENCL_VIDEO_OFLD_VPEQ_OFST (0x1cc3) ++#define P_ENCL_VIDEO_OFLD_VPEQ_OFST (volatile unsigned int *)((0x1cc3 << 2) + 0xff900000) ++#define ENCL_VIDEO_OFLD_VOAV_OFST (0x1cc4) ++#define P_ENCL_VIDEO_OFLD_VOAV_OFST (volatile unsigned int *)((0x1cc4 << 2) + 0xff900000) ++#define ENCL_VIDEO_MATRIX_CB (0x1cc5) ++#define P_ENCL_VIDEO_MATRIX_CB (volatile unsigned int *)((0x1cc5 << 2) + 0xff900000) ++#define ENCL_VIDEO_MATRIX_CR (0x1cc6) ++#define P_ENCL_VIDEO_MATRIX_CR (volatile unsigned int *)((0x1cc6 << 2) + 0xff900000) ++#define ENCL_VIDEO_RGBIN_CTRL (0x1cc7) ++#define P_ENCL_VIDEO_RGBIN_CTRL (volatile unsigned int *)((0x1cc7 << 2) + 0xff900000) ++#define ENCL_MAX_LINE_SWITCH_POINT (0x1cc8) ++#define P_ENCL_MAX_LINE_SWITCH_POINT (volatile unsigned int *)((0x1cc8 << 2) + 0xff900000) ++#define ENCL_DACSEL_0 (0x1cc9) ++#define P_ENCL_DACSEL_0 (volatile unsigned int *)((0x1cc9 << 2) + 0xff900000) ++#define ENCL_DACSEL_1 (0x1cca) ++#define P_ENCL_DACSEL_1 (volatile unsigned int *)((0x1cca << 2) + 0xff900000) ++// ++// Closing file: venc2_regs.h ++// ++//`define VPP_VCBUS_BASE 8'h1d ++// ++// Reading file: vpp_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++// ----------------------------------------------- ++// CBUS_BASE: VPP_VCBUS_BASE = 0x1d ++// ----------------------------------------------- ++//=========================================================================== ++// Video postprocesing Registers ++//=========================================================================== ++// dummy data used in the VPP preblend and scaler ++// Bit 23:16 Y ++// Bit 15:8 CB ++// Bit 7:0 CR ++#define VPP_DUMMY_DATA (0x1d00) ++#define P_VPP_DUMMY_DATA (volatile unsigned int *)((0x1d00 << 2) + 0xff900000) ++//input line length used in VPP ++#define VPP_LINE_IN_LENGTH (0x1d01) ++#define P_VPP_LINE_IN_LENGTH (volatile unsigned int *)((0x1d01 << 2) + 0xff900000) ++//input Picture height used in VPP ++#define VPP_PIC_IN_HEIGHT (0x1d02) ++#define P_VPP_PIC_IN_HEIGHT (volatile unsigned int *)((0x1d02 << 2) + 0xff900000) ++//Because there are many coefficients used in the vertical filter and horizontal filters, ++//indirect access the coefficients of vertical filter and horizontal filter is used. ++//For vertical filter, there are 33x4 coefficients ++//For horizontal filter, there are 33x4 coefficients ++//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2) ++//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not ++//Bit 13 if true, vertical separated coef enable ++//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef ++//Bit 8:7 type of index, 00: vertical coef, 01: vertical chroma coef: 10: horizontal coef, 11: resevered ++//Bit 6:0 coef index ++#define VPP_SCALE_COEF_IDX (0x1d03) ++#define P_VPP_SCALE_COEF_IDX (volatile unsigned int *)((0x1d03 << 2) + 0xff900000) ++//coefficients for vertical filter and horizontal filter ++#define VPP_SCALE_COEF (0x1d04) ++#define P_VPP_SCALE_COEF (volatile unsigned int *)((0x1d04 << 2) + 0xff900000) ++//these following registers are the absolute line address pointer for output divided screen ++//The output divided screen is shown in the following: ++// ++// -------------------------- <------ line zero ++// . ++// . ++// . region0 <---------- nonlinear region or nonscaling region ++// . ++// --------------------------- ++// --------------------------- <------ region1_startp ++// . ++// . region1 <---------- nonlinear region ++// . ++// . ++// --------------------------- ++// --------------------------- <------ region2_startp ++// . ++// . region2 <---------- linear region ++// . ++// . ++// --------------------------- ++// --------------------------- <------ region3_startp ++// . ++// . region3 <---------- nonlinear region ++// . ++// . ++// --------------------------- ++// --------------------------- <------ region4_startp ++// . ++// . region4 <---------- nonlinear region or nonoscaling region ++// . ++// . ++// --------------------------- <------ region4_endp ++//Bit 28:16 region1 startp ++//Bit 12:0 region2 startp ++#define VPP_VSC_REGION12_STARTP (0x1d05) ++#define P_VPP_VSC_REGION12_STARTP (volatile unsigned int *)((0x1d05 << 2) + 0xff900000) ++//Bit 28:16 region3 startp ++//Bit 12:0 region4 startp ++#define VPP_VSC_REGION34_STARTP (0x1d06) ++#define P_VPP_VSC_REGION34_STARTP (volatile unsigned int *)((0x1d06 << 2) + 0xff900000) ++#define VPP_VSC_REGION4_ENDP (0x1d07) ++#define P_VPP_VSC_REGION4_ENDP (volatile unsigned int *)((0x1d07 << 2) + 0xff900000) ++//vertical start phase step, (source/dest)*(2^24) ++//Bit 27:24 integer part ++//Bit 23:0 fraction part ++#define VPP_VSC_START_PHASE_STEP (0x1d08) ++#define P_VPP_VSC_START_PHASE_STEP (volatile unsigned int *)((0x1d08 << 2) + 0xff900000) ++//vertical scaler region0 phase slope, Bit24 signed bit ++#define VPP_VSC_REGION0_PHASE_SLOPE (0x1d09) ++#define P_VPP_VSC_REGION0_PHASE_SLOPE (volatile unsigned int *)((0x1d09 << 2) + 0xff900000) ++//vertical scaler region1 phase slope, Bit24 signed bit ++#define VPP_VSC_REGION1_PHASE_SLOPE (0x1d0a) ++#define P_VPP_VSC_REGION1_PHASE_SLOPE (volatile unsigned int *)((0x1d0a << 2) + 0xff900000) ++//vertical scaler region3 phase slope, Bit24 signed bit ++#define VPP_VSC_REGION3_PHASE_SLOPE (0x1d0b) ++#define P_VPP_VSC_REGION3_PHASE_SLOPE (volatile unsigned int *)((0x1d0b << 2) + 0xff900000) ++//vertical scaler region4 phase slope, Bit24 signed bit ++#define VPP_VSC_REGION4_PHASE_SLOPE (0x1d0c) ++#define P_VPP_VSC_REGION4_PHASE_SLOPE (volatile unsigned int *)((0x1d0c << 2) + 0xff900000) ++//Bit 18:17 double line mode, input/output line width of vscaler becomes 2X, ++// so only 2 line buffer in this case, use for 3D line by line interleave scaling ++// bit1 true, double the input width and half input height, bit0 true, change line buffer 2 lines instead of 4 lines ++//Bit 16 0: progressive output, 1: interlace output ++//Bit 15 vertical scaler output line0 in advance or not for bottom field ++//Bit 14:13 vertical scaler initial repeat line0 number for bottom field ++//Bit 11:8 vertical scaler initial receiving number for bottom field ++//Bit 7 vertical scaler output line0 in advance or not for top field ++//Bit 6:5 vertical scaler initial repeat line0 number for top field ++//Bit 3:0 vertical scaler initial receiving number for top field ++#define VPP_VSC_PHASE_CTRL (0x1d0d) ++#define P_VPP_VSC_PHASE_CTRL (volatile unsigned int *)((0x1d0d << 2) + 0xff900000) ++//Bit 31:16 vertical scaler field initial phase for bottom field ++//Bit 15:0 vertical scaler field initial phase for top field ++#define VPP_VSC_INI_PHASE (0x1d0e) ++#define P_VPP_VSC_INI_PHASE (volatile unsigned int *)((0x1d0e << 2) + 0xff900000) ++//Bit 28:16 region1 startp ++//Bit 12:0 region2 startp ++#define VPP_HSC_REGION12_STARTP (0x1d10) ++#define P_VPP_HSC_REGION12_STARTP (volatile unsigned int *)((0x1d10 << 2) + 0xff900000) ++//Bit 28:16 region3 startp ++//Bit 12:0 region4 startp ++#define VPP_HSC_REGION34_STARTP (0x1d11) ++#define P_VPP_HSC_REGION34_STARTP (volatile unsigned int *)((0x1d11 << 2) + 0xff900000) ++#define VPP_HSC_REGION4_ENDP (0x1d12) ++#define P_VPP_HSC_REGION4_ENDP (volatile unsigned int *)((0x1d12 << 2) + 0xff900000) ++//horizontal start phase step, (source/dest)*(2^24) ++//Bit 27:24 integer part ++//Bit 23:0 fraction part ++#define VPP_HSC_START_PHASE_STEP (0x1d13) ++#define P_VPP_HSC_START_PHASE_STEP (volatile unsigned int *)((0x1d13 << 2) + 0xff900000) ++//horizontal scaler region0 phase slope, Bit24 signed bit ++#define VPP_HSC_REGION0_PHASE_SLOPE (0x1d14) ++#define P_VPP_HSC_REGION0_PHASE_SLOPE (volatile unsigned int *)((0x1d14 << 2) + 0xff900000) ++//horizontal scaler region1 phase slope, Bit24 signed bit ++#define VPP_HSC_REGION1_PHASE_SLOPE (0x1d15) ++#define P_VPP_HSC_REGION1_PHASE_SLOPE (volatile unsigned int *)((0x1d15 << 2) + 0xff900000) ++//horizontal scaler region3 phase slope, Bit24 signed bit ++#define VPP_HSC_REGION3_PHASE_SLOPE (0x1d16) ++#define P_VPP_HSC_REGION3_PHASE_SLOPE (volatile unsigned int *)((0x1d16 << 2) + 0xff900000) ++//horizontal scaler region4 phase slope, Bit24 signed bit ++#define VPP_HSC_REGION4_PHASE_SLOPE (0x1d17) ++#define P_VPP_HSC_REGION4_PHASE_SLOPE (volatile unsigned int *)((0x1d17 << 2) + 0xff900000) ++//Bit 22:21 horizontal scaler initial repeat pixel0 number0 ++//Bit 19:16 horizontal scaler initial receiving number0 ++//Bit 15:0 horizontal scaler top field initial phase0 ++#define VPP_HSC_PHASE_CTRL (0x1d18) ++#define P_VPP_HSC_PHASE_CTRL (volatile unsigned int *)((0x1d18 << 2) + 0xff900000) ++// Bit 22 if true, divide VSC line length 2 as the HSC input length, othwise VSC length length is the same as the VSC line length, ++// just for special usage, more flexibility ++// Bit 21 if true, prevsc uses lin buffer, otherwise prevsc does not use line buffer, it should be same as prevsc_en ++// Bit 20 prehsc_en ++// Bit 19 prevsc_en ++// Bit 18 vsc_en ++// Bit 17 hsc_en ++// Bit 16 scale_top_en ++// Bit 15 video1 scale out enable ++// Bit 12 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for horizontal scaler ++// Bit 10:8 horizontal scaler bank length ++// Bit 5, vertical scaler phase field mode, if true, disable the opposite parity line output, more bandwith needed if output 1080i ++// Bit 4 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for vertical scaler ++// Bit 2:0 vertical scaler bank length ++#define VPP_SC_MISC (0x1d19) ++#define P_VPP_SC_MISC (volatile unsigned int *)((0x1d19 << 2) + 0xff900000) ++// preblend video1 horizontal start and end ++//Bit 28:16 start ++//Bit 12:0 end ++#define VPP_PREBLEND_VD1_H_START_END (0x1d1a) ++#define P_VPP_PREBLEND_VD1_H_START_END (volatile unsigned int *)((0x1d1a << 2) + 0xff900000) ++// preblend video1 vertical start and end ++//Bit 28:16 start ++//Bit 12:0 end ++#define VPP_PREBLEND_VD1_V_START_END (0x1d1b) ++#define P_VPP_PREBLEND_VD1_V_START_END (volatile unsigned int *)((0x1d1b << 2) + 0xff900000) ++// postblend video1 horizontal start and end ++//Bit 28:16 start ++//Bit 12:0 end ++#define VPP_POSTBLEND_VD1_H_START_END (0x1d1c) ++#define P_VPP_POSTBLEND_VD1_H_START_END (volatile unsigned int *)((0x1d1c << 2) + 0xff900000) ++// postblend video1 vertical start and end ++//Bit 28:16 start ++//Bit 12:0 end ++#define VPP_POSTBLEND_VD1_V_START_END (0x1d1d) ++#define P_VPP_POSTBLEND_VD1_V_START_END (volatile unsigned int *)((0x1d1d << 2) + 0xff900000) ++// preblend/postblend video2 horizontal start and end ++//Bit 28:16 start ++//Bit 12:0 end ++#define VPP_BLEND_VD2_H_START_END (0x1d1e) ++#define P_VPP_BLEND_VD2_H_START_END (volatile unsigned int *)((0x1d1e << 2) + 0xff900000) ++// preblend/postblend video2 vertical start and end ++//Bit 28:16 start ++//Bit 12:0 end ++#define VPP_BLEND_VD2_V_START_END (0x1d1f) ++#define P_VPP_BLEND_VD2_V_START_END (volatile unsigned int *)((0x1d1f << 2) + 0xff900000) ++// preblend horizontal size ++#define VPP_PREBLEND_H_SIZE (0x1d20) ++#define P_VPP_PREBLEND_H_SIZE (volatile unsigned int *)((0x1d20 << 2) + 0xff900000) ++// postblend horizontal size ++#define VPP_POSTBLEND_H_SIZE (0x1d21) ++#define P_VPP_POSTBLEND_H_SIZE (volatile unsigned int *)((0x1d21 << 2) + 0xff900000) ++//VPP hold lines ++//Bit 29:24 ++//Bit 21:16 ++//Bit 15:8 preblend hold lines ++//Bit 7:0 postblend hold lines ++#define VPP_HOLD_LINES (0x1d22) ++#define P_VPP_HOLD_LINES (volatile unsigned int *)((0x1d22 << 2) + 0xff900000) ++//Bit 26 if true, automatic change post blend output to one color if field ==1 ++//Bit 25 if true, change screen to one color value for preblender ++//Bit 24 if true, change screen to one color value for postblender ++// Bit 23:16 one color Y ++// Bit 15:8 one color Cb ++// Bit 7:0 one color Cr ++#define VPP_BLEND_ONECOLOR_CTRL (0x1d23) ++#define P_VPP_BLEND_ONECOLOR_CTRL (volatile unsigned int *)((0x1d23 << 2) + 0xff900000) ++//Read Only, VPP preblend current_x, current_y ++//Bit 28:16 current_x ++//Bit 12:0 current_y ++#define VPP_PREBLEND_CURRENT_XY (0x1d24) ++#define P_VPP_PREBLEND_CURRENT_XY (volatile unsigned int *)((0x1d24 << 2) + 0xff900000) ++//Read Only, VPP postblend current_x, current_y ++//Bit 28:16 current_x ++//Bit 12:0 current_y ++#define VPP_POSTBLEND_CURRENT_XY (0x1d25) ++#define P_VPP_POSTBLEND_CURRENT_XY (volatile unsigned int *)((0x1d25 << 2) + 0xff900000) ++// Bit 31 vd1_bgosd_exchange_en for preblend ++// Bit 30 vd1_bgosd_exchange_en for postblend ++// Bit 28 color management enable ++// Bit 27, if true, vd2 use viu2 output as the input, otherwise use normal vd2 from memory ++// Bit 26:18, vd2 alpha ++// Bit 17, osd2 enable for preblend ++// Bit 16, osd1 enable for preblend ++// Bit 15, vd2 enable for preblend ++// Bit 14, vd1 enable for preblend ++// Bit 13, osd2 enable for postblend ++// Bit 12, osd1 enable for postblend ++// Bit 11, vd2 enable for postblend ++// Bit 10, vd1 enable for postblend ++// Bit 9, if true, osd1 is alpha premultipiled ++// Bit 8, if true, osd2 is alpha premultipiled ++// Bit 7, postblend module enable ++// Bit 6, preblend module enable ++// Bit 5, if true, osd2 foreground compared with osd1 in preblend ++// Bit 4, if true, osd2 foreground compared with osd1 in postblend ++// Bit 3, ++// Bit 2, if true, disable resetting async fifo every vsync, otherwise every vsync ++// the aync fifo will be reseted. ++// Bit 1, ++// Bit 0 if true, the output result of VPP is saturated ++#define VPP_MISC (0x1d26) ++#define P_VPP_MISC (volatile unsigned int *)((0x1d26 << 2) + 0xff900000) ++//Bit 31:20 ofifo line length minus 1 ++//Bit 19 if true invert input vs ++//Bit 18 if true invert input hs ++//Bit 17 force top/bottom field, enable ++//Bit 16 force top/bottom field, 0: top, 1: bottom ++//Bit 15 force one go_field, one pluse, write only ++//Bit 14 force one go_line, one pluse, write only ++//Bit 12:0 ofifo size (actually only bit 10:1 is valid), always even number ++#define VPP_OFIFO_SIZE (0x1d27) ++#define P_VPP_OFIFO_SIZE (volatile unsigned int *)((0x1d27 << 2) + 0xff900000) ++//Read only ++//Bit 28:18 current scale out fifo counter ++//Bit 17:13 current afifo counter ++//Bit 12:0 current ofifo counter ++#define VPP_FIFO_STATUS (0x1d28) ++#define P_VPP_FIFO_STATUS (volatile unsigned int *)((0x1d28 << 2) + 0xff900000) ++// Bit 5 SMOKE3 postblend enable only when postblend vd2 is not enable ++// Bit 4 SMOKE3 preblend enable only when preblend vd2 is not enable ++// Bit 3 SMOKE2 postblend enable only when postblend osd2 is not enable ++// Bit 2 SMOKE2 preblend enable only when preblend osd2 is not enable ++// Bit 1 SMOKE1 postblend enable only when postblend osd1 is not enable ++// Bit 0 SMOKE1 preblend enable only when preblend osd1 is not enable ++#define VPP_SMOKE_CTRL (0x1d29) ++#define P_VPP_SMOKE_CTRL (volatile unsigned int *)((0x1d29 << 2) + 0xff900000) ++//smoke can be used only when that blending is disable and then be used as smoke function ++//smoke1 for OSD1 chanel ++//smoke2 for OSD2 chanel ++//smoke3 for VD2 chanel ++//31:24 Y ++//23:16 Cb ++//15:8 Cr ++//7:0 Alpha ++#define VPP_SMOKE1_VAL (0x1d2a) ++#define P_VPP_SMOKE1_VAL (volatile unsigned int *)((0x1d2a << 2) + 0xff900000) ++#define VPP_SMOKE2_VAL (0x1d2b) ++#define P_VPP_SMOKE2_VAL (volatile unsigned int *)((0x1d2b << 2) + 0xff900000) ++#define VPP_SMOKE3_VAL (0x1d2c) ++#define P_VPP_SMOKE3_VAL (volatile unsigned int *)((0x1d2c << 2) + 0xff900000) ++//Bit 28:16 start ++//Bit 12:0 end ++#define VPP_SMOKE1_H_START_END (0x1d2d) ++#define P_VPP_SMOKE1_H_START_END (volatile unsigned int *)((0x1d2d << 2) + 0xff900000) ++//Bit 28:16 start ++//Bit 12:0 end ++#define VPP_SMOKE1_V_START_END (0x1d2e) ++#define P_VPP_SMOKE1_V_START_END (volatile unsigned int *)((0x1d2e << 2) + 0xff900000) ++//Bit 28:16 start ++//Bit 12:0 end ++#define VPP_SMOKE2_H_START_END (0x1d2f) ++#define P_VPP_SMOKE2_H_START_END (volatile unsigned int *)((0x1d2f << 2) + 0xff900000) ++//Bit 28:16 start ++//Bit 12:0 end ++#define VPP_SMOKE2_V_START_END (0x1d30) ++#define P_VPP_SMOKE2_V_START_END (volatile unsigned int *)((0x1d30 << 2) + 0xff900000) ++//Bit 28:16 start ++//Bit 12:0 end ++#define VPP_SMOKE3_H_START_END (0x1d31) ++#define P_VPP_SMOKE3_H_START_END (volatile unsigned int *)((0x1d31 << 2) + 0xff900000) ++//Bit 28:16 start ++//Bit 12:0 end ++#define VPP_SMOKE3_V_START_END (0x1d32) ++#define P_VPP_SMOKE3_V_START_END (volatile unsigned int *)((0x1d32 << 2) + 0xff900000) ++//Bit 27:16 scale out fifo line length minus 1 ++//Bit 12:0 scale out fifo size (actually only bit 11:1 is valid, 11:1, max 1024), always even number ++#define VPP_SCO_FIFO_CTRL (0x1d33) ++#define P_VPP_SCO_FIFO_CTRL (volatile unsigned int *)((0x1d33 << 2) + 0xff900000) ++//for 3D quincunx sub-sampling and horizontal pixel by pixel 3D interleaving ++//Bit 27:24, prehsc_mode, bit 3:2, prehsc odd line interp mode, bit 1:0, prehsc even line interp mode, ++// each 2bit, 00: pix0+pix1/2, average, 01: pix1, 10: pix0 ++//Bit 23 horizontal scaler double pixel mode ++//Bit 22:21 horizontal scaler initial repeat pixel0 number1 ++//Bit 19:16 horizontal scaler initial receiving number1 ++//Bit 15:0 horizontal scaler top field initial phase1 ++#define VPP_HSC_PHASE_CTRL1 (0x1d34) ++#define P_VPP_HSC_PHASE_CTRL1 (volatile unsigned int *)((0x1d34 << 2) + 0xff900000) ++//for 3D quincunx sub-sampling ++//31:24 prehsc pattern, each patten 1 bit, from lsb -> msb ++//22:20 prehsc pattern start ++//18:16 prehsc pattern end ++//15:8 hsc pattern, each patten 1 bit, from lsb -> msb ++//6:4 hsc pattern start ++//2:0 hsc pattern end ++#define VPP_HSC_INI_PAT_CTRL (0x1d35) ++#define P_VPP_HSC_INI_PAT_CTRL (volatile unsigned int *)((0x1d35 << 2) + 0xff900000) ++//Bit 3 minus black level enable for vadj2 ++//Bit 2 Video adjustment enable for vadj2 ++//Bit 1 minus black level enable for vadj1 ++//Bit 0 Video adjustment enable for vadj1 ++#define VPP_VADJ_CTRL (0x1d40) ++#define P_VPP_VADJ_CTRL (volatile unsigned int *)((0x1d40 << 2) + 0xff900000) ++//Bit 16:8 brightness, signed value ++//Bit 7:0 contrast, unsigned value, contrast from 0 <= contrast <2 ++#define VPP_VADJ1_Y (0x1d41) ++#define P_VPP_VADJ1_Y (volatile unsigned int *)((0x1d41 << 2) + 0xff900000) ++//cb' = cb*ma + cr*mb ++//cr' = cb*mc + cr*md ++//all are bit 9:0, signed value, -2 < ma/mb/mc/md < 2 ++#define VPP_VADJ1_MA_MB (0x1d42) ++#define P_VPP_VADJ1_MA_MB (volatile unsigned int *)((0x1d42 << 2) + 0xff900000) ++#define VPP_VADJ1_MC_MD (0x1d43) ++#define P_VPP_VADJ1_MC_MD (volatile unsigned int *)((0x1d43 << 2) + 0xff900000) ++//Bit 16:8 brightness, signed value ++//Bit 7:0 contrast, unsigned value, contrast from 0 <= contrast <2 ++#define VPP_VADJ2_Y (0x1d44) ++#define P_VPP_VADJ2_Y (volatile unsigned int *)((0x1d44 << 2) + 0xff900000) ++//cb' = cb*ma + cr*mb ++//cr' = cb*mc + cr*md ++//all are bit 9:0, signed value, -2 < ma/mb/mc/md < 2 ++#define VPP_VADJ2_MA_MB (0x1d45) ++#define P_VPP_VADJ2_MA_MB (volatile unsigned int *)((0x1d45 << 2) + 0xff900000) ++#define VPP_VADJ2_MC_MD (0x1d46) ++#define P_VPP_VADJ2_MC_MD (volatile unsigned int *)((0x1d46 << 2) + 0xff900000) ++//Bit 2 horizontal chroma sharp/blur selection, 0:sharp, 1: blur ++//Bit 1 horizontal luma sharp/blur selection, 0:sharp, 1: blur ++//Bit 0 horizontal sharpness enable ++#define VPP_HSHARP_CTRL (0x1d50) ++#define P_VPP_HSHARP_CTRL (volatile unsigned int *)((0x1d50 << 2) + 0xff900000) ++//{1'b0,threhsold} < diff ++//Bit 26:16 luma threshold0 ++//Bit 10:0 luma threshold1 ++#define VPP_HSHARP_LUMA_THRESH01 (0x1d51) ++#define P_VPP_HSHARP_LUMA_THRESH01 (volatile unsigned int *)((0x1d51 << 2) + 0xff900000) ++// ++//Bit 26:16 luma threshold2 ++//Bit 10:0 luma threshold3 ++#define VPP_HSHARP_LUMA_THRESH23 (0x1d52) ++#define P_VPP_HSHARP_LUMA_THRESH23 (volatile unsigned int *)((0x1d52 << 2) + 0xff900000) ++//Bit 26:16 chroma threshold0 ++//Bit 10:0 chroma threshold1 ++#define VPP_HSHARP_CHROMA_THRESH01 (0x1d53) ++#define P_VPP_HSHARP_CHROMA_THRESH01 (volatile unsigned int *)((0x1d53 << 2) + 0xff900000) ++//Bit 26:16 chroma threshold2 ++//Bit 10:0 chroma threshold3 ++#define VPP_HSHARP_CHROMA_THRESH23 (0x1d54) ++#define P_VPP_HSHARP_CHROMA_THRESH23 (volatile unsigned int *)((0x1d54 << 2) + 0xff900000) ++//Bit 23:16 luma gain2 ++//Bit 15:8 luma gain1 ++//Bit 7:0 luma gain0 ++#define VPP_HSHARP_LUMA_GAIN (0x1d55) ++#define P_VPP_HSHARP_LUMA_GAIN (volatile unsigned int *)((0x1d55 << 2) + 0xff900000) ++// ++//Bit 23:16 chroma gain2 ++//Bit 15:8 chroma gain1 ++//Bit 7:0 chroma gain0 ++#define VPP_HSHARP_CHROMA_GAIN (0x1d56) ++#define P_VPP_HSHARP_CHROMA_GAIN (volatile unsigned int *)((0x1d56 << 2) + 0xff900000) ++//Read only ++//Bit 31, if it is true, it means this probe is valid in the last field/frame ++//Bit 29:20 component 0 ++//Bit 19:10 component 1 ++//Bit 9:0 component 2 ++#define VPP_MATRIX_PROBE_COLOR (0x1d5c) ++#define P_VPP_MATRIX_PROBE_COLOR (volatile unsigned int *)((0x1d5c << 2) + 0xff900000) ++#define VPP_MATRIX_PROBE_COLOR1 (0x1dd7) ++#define P_VPP_MATRIX_PROBE_COLOR1 (volatile unsigned int *)((0x1dd7 << 2) + 0xff900000) ++//Bit 23:16 component 0 ++//Bit 15:8 component 1 ++//Bit 7:0 component 2 ++#define VPP_MATRIX_HL_COLOR (0x1d5d) ++#define P_VPP_MATRIX_HL_COLOR (volatile unsigned int *)((0x1d5d << 2) + 0xff900000) ++//28:16 probe x, postion ++//12:0 probe y, position ++#define VPP_MATRIX_PROBE_POS (0x1d5e) ++#define P_VPP_MATRIX_PROBE_POS (volatile unsigned int *)((0x1d5e << 2) + 0xff900000) ++//Bit 16, highlight_en ++//Bit 15 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix ++//Bit 14:12 probe_sel, 000: select post matrix, 001: select vd1 matrix, 010: select vd2 matrix ++//Bit 9:8 matrix coef idx selection, 00: select post matrix, 01: select vd1 matrix, 10: select vd2 matrix ++//Bit 5 vd1 conversion matrix enable ++//Bit 4 vd2 conversion matrix enable ++//Bit 2 output y/cb/cr saturation enable, only for post matrix (y saturate to 16-235, cb/cr saturate to 16-240) ++//Bit 1 input y/cb/cr saturation enable, only for post matrix (y saturate to 16-235, cb/cr saturate to 16-240) ++//Bit 0 post conversion matrix enable ++#define VPP_MATRIX_CTRL (0x1d5f) ++#define P_VPP_MATRIX_CTRL (volatile unsigned int *)((0x1d5f << 2) + 0xff900000) ++//Bit 28:16 coef00 ++//Bit 12:0 coef01 ++#define VPP_MATRIX_COEF00_01 (0x1d60) ++#define P_VPP_MATRIX_COEF00_01 (volatile unsigned int *)((0x1d60 << 2) + 0xff900000) ++//Bit 28:16 coef02 ++//Bit 12:0 coef10 ++#define VPP_MATRIX_COEF02_10 (0x1d61) ++#define P_VPP_MATRIX_COEF02_10 (volatile unsigned int *)((0x1d61 << 2) + 0xff900000) ++//Bit 28:16 coef11 ++//Bit 12:0 coef12 ++#define VPP_MATRIX_COEF11_12 (0x1d62) ++#define P_VPP_MATRIX_COEF11_12 (volatile unsigned int *)((0x1d62 << 2) + 0xff900000) ++//Bit 28:16 coef20 ++//Bit 12:0 coef21 ++#define VPP_MATRIX_COEF20_21 (0x1d63) ++#define P_VPP_MATRIX_COEF20_21 (volatile unsigned int *)((0x1d63 << 2) + 0xff900000) ++#define VPP_MATRIX_COEF22 (0x1d64) ++#define P_VPP_MATRIX_COEF22 (volatile unsigned int *)((0x1d64 << 2) + 0xff900000) ++//Bit 26:16 offset0 ++//Bit 10:0 offset1 ++#define VPP_MATRIX_OFFSET0_1 (0x1d65) ++#define P_VPP_MATRIX_OFFSET0_1 (volatile unsigned int *)((0x1d65 << 2) + 0xff900000) ++//Bit 10:0 offset2 ++#define VPP_MATRIX_OFFSET2 (0x1d66) ++#define P_VPP_MATRIX_OFFSET2 (volatile unsigned int *)((0x1d66 << 2) + 0xff900000) ++//Bit 26:16 pre_offset0 ++//Bit 10:0 pre_offset1 ++#define VPP_MATRIX_PRE_OFFSET0_1 (0x1d67) ++#define P_VPP_MATRIX_PRE_OFFSET0_1 (volatile unsigned int *)((0x1d67 << 2) + 0xff900000) ++//Bit 10:0 pre_offset2 ++#define VPP_MATRIX_PRE_OFFSET2 (0x1d68) ++#define P_VPP_MATRIX_PRE_OFFSET2 (volatile unsigned int *)((0x1d68 << 2) + 0xff900000) ++// dummy data used in the VPP postblend ++// Bit 23:16 Y ++// Bit 15:8 CB ++// Bit 7:0 CR ++#define VPP_DUMMY_DATA1 (0x1d69) ++#define P_VPP_DUMMY_DATA1 (volatile unsigned int *)((0x1d69 << 2) + 0xff900000) ++//Bit 31 gainoff module enable ++//Bit 26:16 gain0, 1.10 unsigned data ++//Bit 10:0 gain1, 1.10 unsigned dat ++#define VPP_GAINOFF_CTRL0 (0x1d6a) ++#define P_VPP_GAINOFF_CTRL0 (volatile unsigned int *)((0x1d6a << 2) + 0xff900000) ++//Bit 26:16 gain2, 1.10 unsigned data ++//Bit 10:0, offset0, signed data ++#define VPP_GAINOFF_CTRL1 (0x1d6b) ++#define P_VPP_GAINOFF_CTRL1 (volatile unsigned int *)((0x1d6b << 2) + 0xff900000) ++//Bit 26:16, offset1, signed data ++//Bit 10:0, offset2, signed data ++#define VPP_GAINOFF_CTRL2 (0x1d6c) ++#define P_VPP_GAINOFF_CTRL2 (volatile unsigned int *)((0x1d6c << 2) + 0xff900000) ++//Bit 26:16, pre_offset0, signed data ++//Bit 10:0, pre_offset1, signed data ++#define VPP_GAINOFF_CTRL3 (0x1d6d) ++#define P_VPP_GAINOFF_CTRL3 (volatile unsigned int *)((0x1d6d << 2) + 0xff900000) ++//Bit 10:0, pre_offset2, signed data ++#define VPP_GAINOFF_CTRL4 (0x1d6e) ++#define P_VPP_GAINOFF_CTRL4 (volatile unsigned int *)((0x1d6e << 2) + 0xff900000) ++//only two registers used in the color management, which are defined in the chroma_reg.h ++//`define VPP_CHROMA_ADDR_PORT 8'h70 ++//`define VPP_CHROMA_DATA_PORT 8'h71 ++// ++// Reading file: chroma_reg.h ++// ++//********************************************************************************** ++//* Copyright (c) 2008, AMLOGIC Inc. ++//* All rights reserved ++//********************************************************************************** ++//* File : chroma_reg.v ++//* Author : Terrence Wang ++//* Date : Dec 2008 ++//* Description : ++//* ++//********************************************************************************** ++//* Modification History: ++//* Date Modified By Reason ++//********************************************************************************** ++// synopsys translate_off ++// synopsys translate_on ++#define VPP_CHROMA_ADDR_PORT (0x1d70) ++#define P_VPP_CHROMA_ADDR_PORT (volatile unsigned int *)((0x1d70 << 2) + 0xff900000) ++#define VPP_CHROMA_DATA_PORT (0x1d71) ++#define P_VPP_CHROMA_DATA_PORT (volatile unsigned int *)((0x1d71 << 2) + 0xff900000) ++//`define CHROMA_ADDR_PORT 8'h67 ++//`define CHROMA_DATA_PORT 8'h68 ++ ++// CHROMA_GAIN_REG_XX(00-07) ++// hue gain, sat gain function control ++// Bit 31 reg_sat_en enable sat adjustment in current region ++// Bit 27 reg_sat_increase sat adjustment increase or decrease ++// 1'b1: increase 1'b0: decrease ++// Bit 26:25 reg_sat_central_en sat adjustment with central biggest or one side biggest ++// 2'b01 central biggest 2'b00 one side biggest ++// Bit 24 reg_sat_shape when sat adjustment one side biggest, define left or right ++// 1'b1: left side biggest 1'b0 right side biggest ++// Bit 23:16 reg_sat_gain define the sat gain when sat adjustment ++// 0x00-0xff ++// Bit 15 reg_hue_en enable hue adjustment in current region ++// Bit 11 reg_hue_clockwise hue adjustment clockwise or anti-clockwise ++// 1'b1: clockwise 1'b0: anti-clockwise ++// Bit 10:9 reg_hue_central_en when hue adjustment, parabola curve or non-symmetry curve ++// 1'b1: parabola curve 1'b0: non-symmetry curve ++// Bit 8 reg_hue_shape when non-symmetry curve, define which side change more ++// 1'b1: right side change more 1'b0: left side change more ++// Bit 7:0 reg_hue_gain define the hue gain when hue adjustment ++// 0x00-0x80, note: should be no bigger than 0x80 ++ ++ #define CHROMA_GAIN_REG00 0x00 ++ ++ ++// HUE_HUE_RANGE_REG_XX(00-07) ++// hue range select ++// Bit 31:24 no use now ++// Bit 23:16 reg_hue_shift_range define the angle of target region ++// 0x00-0xff,(0x100 means 120 degree though it can not be set) ++// must be greater or equal than 8'd8 ++// Bit 15 reg_symmetry_en this is used for create one symmetry region ++// the symmetry region hue_shift_start = reg_hue_hue_shift_start + reg_hue_shift_range<<5 ++// the symmetry region hue_shift_range = reg_hue_shift_range ++// in symmetry region, all the sat and hue setting will be same with original region, ++// except reg_hue_shape, reg_sat_shape, reg_hue_clockwise will be reversed ++// Bit 14:0 reg_hue_hue_shift_start define the start angle of target region ++// 0x6000 means 360 degree ++// only region 0 and 1 can exceed 360 degrees. ++ ++ #define HUE_HUE_RANGE_REG00 0x01 ++ ++ ++// HUE_RANGE_INV_REG_XX ++// Calculation should be follow ++// HUE_RANGE_INV_REG0X[15:0] = ((1<<20)/HUE_HUE_RANGE_REG0X[23:16]+1)>>1 ++// HUE_RANGE_INV_REG_XX is to used to save divider ++ ++ #define HUE_RANGE_INV_REG00 0x02 ++ ++ ++ ++// for belowing each low, high, low_slope, high_slope group: ++// a_____________b ++// / \ a = low + 2^low_slope ++// / \ b = high - 2^high_slope ++// / \ low_slope <= 7; high_slope <= 7 ++// / \ b >= a ++// ______/_____________________\________ ++// low high ++// ++// ++// HUE_LUM_RANGE_REG_XX(00-07) ++// luma range selection for hue adjustment ++// Bit 31:24 reg_sat_lum_low define the low level of luma value for sat adjustment ++// 0x00-0xff ++// Bit 23:20 reg_hue_lum_high_slope define the slope area below high level of luma value for hue adjustment ++// 0x00-0x07 ++// Bit 19:16 reg_hue_lum_low_slope define the slope area above low level of luma value for hue adjustment ++// 0x00-0x07 ++// Bit 15:8 reg_hue_lum_high define the high level of luma value for hue adjustment ++// 0x00-0xff ++// Bit 7:0 reg_hue_lum_low define the low level of luma value for hue adjustment ++// 0x00-0xff ++ ++ #define HUE_LUM_RANGE_REG00 0x03 ++ ++// HUE_SAT_RANGE_REG_XX(00-07) ++// sat range selection for hue adjustment ++// Bit 31:24 reg_sat_lum_high define the high level of luma value for sat adjustment ++// 0x00-0xff ++// Bit 23:20 reg_hue_sat_high_slope define the slope area below high level of sat value for hue adjustment ++// 0x00-0x07 ++// Bit 19:16 reg_hue_sat_low_slope define the slope area above low level of sat value for hue adjustment ++// 0x00-0x07 ++// Bit 15:8 reg_hue_sat_high define the high level of sat value for hue adjustment ++// 0x00-0xff ++// Bit 7:0 reg_hue_sat_low define the low level of sat value for hue adjustment ++// 0x00-0xff ++ ++ #define HUE_SAT_RANGE_REG00 0x04 ++ ++// SAT_SAT_RANGE_REG_XX(00-07) ++// sat range selection for hue adjustment ++// Bit 31:28 reg_sat_lum_high_slope define the slope area below high level of luma value for sat adjustment ++// 0x00-0x07 ++// Bit 27:24 reg_sat_lum_low_slope define the slope area above low level of luma value for sat adjustment ++// 0x00-0x07 ++// Bit 23:20 reg_sat_sat_high_slope define the slope area below high level of sat value for sat adjustment ++// 0x00-0x07 ++// Bit 19:16 reg_sat_sat_low_slope define the slope area above low level of sat value for sat adjustment ++// 0x00-0x07 ++// Bit 15:8 reg_sat_sat_high define the high level of sat value for sat adjustment ++// 0x00-0xff ++// Bit 7:0 reg_sat_sat_low define the low level of sat value for sat adjustment ++// 0x00-0xff ++ ++ #define SAT_SAT_RANGE_REG00 0x05 ++ ++ ++ #define CHROMA_GAIN_REG01 0x06 ++ #define HUE_HUE_RANGE_REG01 0x07 ++ #define HUE_RANGE_INV_REG01 0x08 ++ #define HUE_LUM_RANGE_REG01 0x09 ++ #define HUE_SAT_RANGE_REG01 0x0a ++ #define SAT_SAT_RANGE_REG01 0x0b ++ ++ #define CHROMA_GAIN_REG02 0x0c ++ #define HUE_HUE_RANGE_REG02 0x0d ++ #define HUE_RANGE_INV_REG02 0x0e ++ #define HUE_LUM_RANGE_REG02 0x0f ++ #define HUE_SAT_RANGE_REG02 0x10 ++ #define SAT_SAT_RANGE_REG02 0x11 ++ ++ ++ #define CHROMA_GAIN_REG03 0x12 ++ #define HUE_HUE_RANGE_REG03 0x13 ++ #define HUE_RANGE_INV_REG03 0x14 ++ #define HUE_LUM_RANGE_REG03 0x15 ++ #define HUE_SAT_RANGE_REG03 0x16 ++ #define SAT_SAT_RANGE_REG03 0x17 ++ ++ #define CHROMA_GAIN_REG04 0x18 ++ #define HUE_HUE_RANGE_REG04 0x19 ++ #define HUE_RANGE_INV_REG04 0x1a ++ #define HUE_LUM_RANGE_REG04 0x1b ++ #define HUE_SAT_RANGE_REG04 0x1c ++ #define SAT_SAT_RANGE_REG04 0x1d ++ ++ #define CHROMA_GAIN_REG05 0x1e ++ #define HUE_HUE_RANGE_REG05 0x1f ++ #define HUE_RANGE_INV_REG05 0x20 ++ #define HUE_LUM_RANGE_REG05 0x21 ++ #define HUE_SAT_RANGE_REG05 0x22 ++ #define SAT_SAT_RANGE_REG05 0x23 ++ ++ #define CHROMA_GAIN_REG06 0x24 ++ #define HUE_HUE_RANGE_REG06 0x25 ++ #define HUE_RANGE_INV_REG06 0x26 ++ #define HUE_LUM_RANGE_REG06 0x27 ++ #define HUE_SAT_RANGE_REG06 0x28 ++ #define SAT_SAT_RANGE_REG06 0x29 ++ ++ #define CHROMA_GAIN_REG07 0x2a ++ #define HUE_HUE_RANGE_REG07 0x2b ++ #define HUE_RANGE_INV_REG07 0x2c ++ #define HUE_LUM_RANGE_REG07 0x2d ++ #define HUE_SAT_RANGE_REG07 0x2e ++ #define SAT_SAT_RANGE_REG07 0x2f ++ ++// REG_CHROMA_CONTROL ++// Bit 31 reg_chroma_en enable color manage function ++// 1'b1: enable 1'b0: bypass ++// Bit 6 sat_sel uv_max or u^2+v^2 selected as sat for reference ++// 1'b1: uv_max(default) 1'b0: u^2+v^2 ++// Bit 5 uv_adj_en final uv_adjust enable ++// 1'b1: enable 1'b0: bypass ++// Bit 2 hue_en rgb to hue enable ++// 1'b1: enable(default) 1'b0: bypass ++// Bit 1:0 csc_sel define input YUV with different color type ++// 2'b00: 601(16-235) 2'b01: 709(16-235) ++// 2'b10: 601(0-255) 2'b11: 709(0-255) ++ #define REG_CHROMA_CONTROL 0x30 // default 32h'80000024 ++ #define REG_DEMO_CENTER_BAR 0x31 // default 32h'0 ++ #define REG_DEMO_HLIGHT_MODE 0x32 // default 32h'0 ++ #define REG_DEMO_OWR_DATA 0x33 // default 32h'0 ++ ++ ++////===========================================//// ++//// CM2 ADDR ++////===========================================//// ++ ++ #define SAT_BYYB_NODE_REG0 0x200 // default 32'h0 ++//Bit 31:24, sat_byyb_node3 the 4th node ++//Bit 23:16, sat_byyb_node2 the 3th node ++//Bit 15: 8, sat_byyb_node1 signed, the 2th node about saturation ++//Bit 7: 0, sat_byyb_node0 signed, the 1th node about saturation ++//gain offset along y coordinate,the gain normalized to 128 as "1" ++ ++ #define SAT_BYYB_NODE_REG1 0x201 // default 32'h0 ++//Bit 31:24, sat_byyb_node7 the 8th node ++//Bit 23:16, sat_byyb_node6 the 7th node ++//Bit 15: 8, sat_byyb_node5 signed, the 6th node about saturation ++//Bit 7: 0, sat_byyb_node4 signed, the 5th node about saturation ++//gain offset along y coordinate,the gain normalized to 128 as "1" ++ ++ #define SAT_BYYB_NODE_REG2 0x202 // default 32'h0 ++//Bit 31: 8, reserved ++//Bit 7: 0, sat_byyb_node4 signed, the 5th node about saturation ++ ++ ++ #define SAT_SRC_NODE_REG 0x203 // default 32'h0 ++//Bit 31:28, reserved ++//Bit 27:16, sat_src_node1 ++//Bit 15:12, reserved ++//Bit 11: 0, sat_src_node0 usigned, threshold of input saturation for first and second piece ++ ++ #define CM_ENH_SFT_MODE_REG 0x204 // default 32'h0 ++//Bit 31: 9, reserved ++//Bit 8: 6, hue_lsft_mode hue offset adjustments scale ++//Bit 5: 4, luma_lsft_mode luma offset adjustments scale for reg_cm2_adj_luma_via_hue ++//Bit 3: 2, sat_byy_rsft_mode saturation gain adjustments scale for reg_cm2_adj_sat_via_y ++//Bit 1: 0, sat_byhs_rsft_mode saturation gain adjustments scale for reg_cm2_adj_sat_via_hs[:][:] 0:no scale up/down 1:dnscale by 2(-128,127)/2 ++ ++ #define FRM_SIZE_REG 0x205 // default 32'h0 ++//Bit 31:29, reserved ++//Bit 28:16, reg_frm_height the frame height size ++//Bit 15:13, reserved ++//Bit 12: 0, reg_frm_width the frame width size ++ ++ #define FITLER_CFG_REG 0x206 // default 32'h0 ++//Bit 31: 5, reserved ++//Bit 4: 4, inteleav_mod horizontal interleave filter(zero-padding) for 3D considerations 0:using non-zero padding lpf 1:using zero-padding lpf ++//Bit 3: 2, lpf_slt_uv apply cm on lp portion or original video pixels options ++//Bit 1: 0, lpf_slt_y apply cm on lp portion or original video pixels options ++ ++ #define CM_GLOBAL_GAIN_REG 0x207 // default 32'h0 ++//Bit 31:28, reserved ++//Bit 27:16, cm2_global_sat global saturation gain for general color adjustments(0~4095 <=> 0~8),512 normalized to "1" ++//Bit 15:12, reserved ++//Bit 11: 0, cm2_global_hue global hue offsets for general color adjustments(0~4095 <=> 0~360 degree) ++ ++ #define CM_ENH_CTL_REG 0x208 // default 32'h0 ++//Bit 31:7, reserved ++//Bit 6, hue_adj_en cm2 hue adjustments ++//Bit 5, sat_adj_en cm2 saturation adjustments ++//Bit 4, luma_adj_en enable siganl for cm2 luma adjustments ++//Bit 3, reserved ++//Bit 2, cm2_filt_en apply cm on lp portion enable ++//Bit 1, cm2_en cm2 enable siganl ++//Bit 0, cm1_en ++ ++ #define ROI_X_SCOPE_REG 0x209 // default 32'h0 ++//Bit 31:29, reserved ++//Bit 28:16, roi_x_end ending col index of the region of interest ++//Bit 15:13, reserved ++//Bit 12: 0, roi_x_beg start col index of the region of interest ++ ++ #define ROI_Y_SCOPE_REG 0x20a // default 32'h0 ++//Bit 31:29, reserved ++//Bit 28:16, roi_y_end ending row index of the region of interest ++//Bit 15:13, reserved ++//Bit 12: 0, roi_y_beg start row index of the region of interest ++ ++ #define POI_XY_DIR_REG 0x20b // default 32'h0 ++//Bit 31:29, reserved ++//Bit 28:16, poi_y_dir ending row index of the region of interest ++//Bit 15:13, reserved ++//Bit 12: 0, poi_x_dir start row index of the region of interest ++ ++ #define COI_Y_SCOPE_REG 0x20c // default 32'h0 ++//Bit 31:16, reserved ++//Bit 15: 8, coi_y_end ++//Bit 7: 0, coi_y_beg ++ ++ #define COI_H_SCOPE_REG 0x20d // default 32'h0 ++//Bit 31:28, reserved ++//Bit 27:16, coi_h_end ++//Bit 15:12, reserved ++//Bit 11: 0, coi_h_beg lower bound of hue value for color of interest ,12 bits precision ++ ++ #define COI_S_SCOPE_REG 0x20e // default 32'h0 ++//Bit 31:28, reserved ++//Bit 27:16, coi_s_end ++//Bit 15:12, reserved ++//Bit 11: 0, coi_s_beg lower bound of sat value for color of interest ,12 bits precision ++ #define IFO_MODE_REG 0x20f // default 32'h0 ++//Bit 31:8, reserved ++//Bit 7:6, ifo_mode3 ++//Bit 5:4, ifo_mode2 ++//Bit 3:2, ifo_mode1 ++//Bit 1:0, ifo_mode0 ++ #define POI_RPL_MODE_REG 0x210 // default 32'h0 ++//Bit 31:4, reserved ++//Bit 3:0, poi_rpl_mode enhance mode control of pixels inside and outside region of interest bit[3:2]control roi ++ #define DEMO_OWR_YHS_REG 0x211 // default 32'h0 ++//Bit 31: 0, demo_owr_yhs ++ ++ #define DEMO_POI_Y_REG 0x212 // default 32'h0 ++//Bit 31: 8, reserved ++//Bit 7: 0, luma_data_poi_r only get locked higher 8bits ++ #define DEMO_POI_H_REG 0x213 // default 32'h0 ++//Bit 31: 12, reserved ++//Bit 11: 0, hue_data_poi_r only get locked higher 12bits ++ #define DEMO_POI_S_REG 0x214 // default 32'h0 ++//Bit 31: 12, reserved ++//Bit 11: 0, sat_data_poi_r only get locked higher 12bits ++ //#define LUMA_BYH_LIMT_REG 0x215 // default 32'h0 ++ #define LUMA_ADJ_LIMT_REG 0x215 // default 32'h0 ++//Bit 31:24, reserved ++//Bit 23:16, luma_lmt_satslp slope to do the luma adjustment degrade ++//Bit 15:12, reserved ++//Bit 11:0, luma_lmt_satth threshold to saturation ++ #define SAT_ADJ_LIMT_REG 0x216 // default 32'h0 ++//Bit 31:24, reserved ++//Bit 23:16, sat_lmt_satslp slope to do the adjustment degrade ++//Bit 15:12, reserved ++//Bit 11:0, sat_lmt_satth threshold to saturation ++ #define HUE_ADJ_LIMT_REG 0x217 // default 32'h0 ++//Bit 31: 24, reserved ++//Bit 23: 16, hue_lmt_satslp slope to do the adjustment degrade ++//Bit 15: 12, reserved ++//Bit 11: 0, hue_lmt_satth threshold to saturation ++ #define UVHS_OFST_REG 0x218 // default 32'h0 ++//Bit 31: 24, hs2uv_v_ofst ++//Bit 23: 16, hs2uv_u_ofst ++//Bit 15: 8, uv2hs_v_ofst ++//Bit 7: 0, uv2hs_u_ofst ++ #define HUE_CFG_PARA_REG 0x219 // default 32'h0 ++//Bit 31: 17, reserved ++//Bit 16, hue_protect_en ++//Bit 15: 13, cm2_hue_byhs_mode ++//Bit 12, cm2_hue_div_mode ++//Bit 11: 0, cm2_before_hue_ofst ++ #define DEMO_SPLT_CFG_REG 0x21a // default 32'h0 ++//Bit 31: 22, reserved ++//Bit 21: 20, demo_split_mode ++//Bit 19: 16, demo_split_width slope to do the adjustment degrade ++//Bit 15: 13, reserved ++//Bit 12: 0, demo_split_post threshold to saturation ++ #define DEMO_SPLT_YHS_REG 0x21b // default 32'h0 ++//Bit 31: 0, demo_splt_yhs threshold to saturation ++ ++ #define XVYCC_YSCP_REG 0x21c // default 32'h0 ++//Bit 31: 28, reserved ++//Bit 27: 16, xvycc_y_max ++//Bit 15: 12, reserved ++//Bit 11: 0, xvycc_y_min ++ #define XVYCC_USCP_REG 0x21d // default 32'h0 ++//Bit 31: 28, reserved ++//Bit 27: 16, xvycc_u_max ++//Bit 15: 12, reserved ++//Bit 11: 0, xvycc_u_min ++ #define XVYCC_VSCP_REG 0x21e // default 32'h0 ++//Bit 31: 28, reserved ++//Bit 27: 16, xvycc_v_max ++//Bit 15: 12, reserved ++//Bit 11: 0, xvycc_v_min ++ ++////========= NODE 0 COEFFICIENT ==============//// ++ ++ #define REG_CM2_ENH_COEFF0_H00 0x100 // default 32'H0 ++//Bit 31: 24, reg_cm2_adj_sat_via_hs_2 ++//Bit 23: 16, reg_cm2_adj_sat_via_hs_1 ++//Bit 15: 8, reg_cm2_adj_sat_via_hs_0 ++//Bit 7: 0, reg_cm2_adj_luma_via_h ++ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx ++ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx ++ #define REG_CM2_ENH_COEFF1_H00 0x101 // default 32'H0 ++ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx ++ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx ++ #define REG_CM2_ENH_COEFF2_H00 0x102 // default 32'H0 ++ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx ++ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx ++ #define REG_CM2_ENH_COEFF3_H00 0x103 // default 32'H0 ++ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx ++ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx ++ #define REG_CM2_ENH_COEFF4_H00 0x104 // default 32'H0 ++ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx ++ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx ++ ++////========= NODE 1 COEFFICIENT ==============//// ++ ++ #define REG_CM2_ENH_COEFF0_H01 0x108 // default 32'H0 ++ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx ++ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx ++ #define REG_CM2_ENH_COEFF1_H01 0x109 // default 32'H0 ++ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx ++ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx ++ #define REG_CM2_ENH_COEFF2_H01 0x10a // default 32'H0 ++ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx ++ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx ++ #define REG_CM2_ENH_COEFF3_H01 0x10b // default 32'H0 ++ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx ++ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx ++ #define REG_CM2_ENH_COEFF4_H01 0x10c // default 32'H0 ++ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx ++ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx ++ ++////========= NODE 2 COEFFICIENT ==============//// ++ ++ #define REG_CM2_ENH_COEFF0_H02 0x110 // default 32'H0 ++ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx ++ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx ++ #define REG_CM2_ENH_COEFF1_H02 0x111 // default 32'H0 ++ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx ++ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx ++ #define REG_CM2_ENH_COEFF2_H02 0x112 // default 32'H0 ++ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx ++ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx ++ #define REG_CM2_ENH_COEFF3_H02 0x113 // default 32'H0 ++ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx ++ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx ++ #define REG_CM2_ENH_COEFF4_H02 0x114 // default 32'H0 ++ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx ++ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx ++ ++////========= NODE 3 COEFFICIENT ==============//// ++ ++ #define REG_CM2_ENH_COEFF0_H03 0x118 // default 32'H0 ++ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx ++ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx ++ #define REG_CM2_ENH_COEFF1_H03 0x119 // default 32'H0 ++ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx ++ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx ++ #define REG_CM2_ENH_COEFF2_H03 0x11a // default 32'H0 ++ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx ++ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx ++ #define REG_CM2_ENH_COEFF3_H03 0x11b // default 32'H0 ++ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx ++ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx ++ #define REG_CM2_ENH_COEFF4_H03 0x11c // default 32'H0 ++ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx ++ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx ++ ++////========= NODE 4 COEFFICIENT ==============//// ++ ++ #define REG_CM2_ENH_COEFF0_H04 0x120 // default 32'H0 ++ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx ++ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx ++ #define REG_CM2_ENH_COEFF1_H04 0x121 // default 32'H0 ++ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx ++ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx ++ #define REG_CM2_ENH_COEFF2_H04 0x122 // default 32'H0 ++ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx ++ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx ++ #define REG_CM2_ENH_COEFF3_H04 0x123 // default 32'H0 ++ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx ++ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx ++ #define REG_CM2_ENH_COEFF4_H04 0x124 // default 32'H0 ++ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx ++ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx ++ ++////========= NODE 5 COEFFICIENT ==============//// ++ ++ #define REG_CM2_ENH_COEFF0_H05 0x128 // default 32'H0 ++ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx ++ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx ++ #define REG_CM2_ENH_COEFF1_H05 0x129 // default 32'H0 ++ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx ++ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx ++ #define REG_CM2_ENH_COEFF2_H05 0x12a // default 32'H0 ++ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx ++ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx ++ #define REG_CM2_ENH_COEFF3_H05 0x12b // default 32'H0 ++ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx ++ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx ++ #define REG_CM2_ENH_COEFF4_H05 0x12c // default 32'H0 ++ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx ++ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx ++ ++////========= NODE 6 COEFFICIENT ==============//// ++ ++ #define REG_CM2_ENH_COEFF0_H06 0x130 // default 32'H0 ++ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx ++ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx ++ #define REG_CM2_ENH_COEFF1_H06 0x131 // default 32'H0 ++ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx ++ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx ++ #define REG_CM2_ENH_COEFF2_H06 0x132 // default 32'H0 ++ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx ++ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx ++ #define REG_CM2_ENH_COEFF3_H06 0x133 // default 32'H0 ++ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx ++ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx ++ #define REG_CM2_ENH_COEFF4_H06 0x134 // default 32'H0 ++ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx ++ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx ++ ++////========= NODE 7 COEFFICIENT ==============//// ++ ++ #define REG_CM2_ENH_COEFF0_H07 0x138 // default 32'H0 ++ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx ++ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx ++ #define REG_CM2_ENH_COEFF1_H07 0x139 // default 32'H0 ++ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx ++ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx ++ #define REG_CM2_ENH_COEFF2_H07 0x13a // default 32'H0 ++ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx ++ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx ++ #define REG_CM2_ENH_COEFF3_H07 0x13b // default 32'H0 ++ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx ++ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx ++ #define REG_CM2_ENH_COEFF4_H07 0x13c // default 32'H0 ++ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx ++ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx ++ ++////========= NODE 8 COEFFICIENT ==============//// ++ ++ #define REG_CM2_ENH_COEFF0_H08 0x140 // default 32'H0 ++ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx ++ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx ++ #define REG_CM2_ENH_COEFF1_H08 0x141 // default 32'H0 ++ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx ++ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx ++ #define REG_CM2_ENH_COEFF2_H08 0x142 // default 32'H0 ++ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx ++ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx ++ #define REG_CM2_ENH_COEFF3_H08 0x143 // default 32'H0 ++ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx ++ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx ++ #define REG_CM2_ENH_COEFF4_H08 0x144 // default 32'H0 ++ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx ++ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx ++ ++////========= NODE 9 COEFFICIENT ==============//// ++ ++ #define REG_CM2_ENH_COEFF0_H09 0x148 // default 32'H0 ++ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx ++ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx ++ #define REG_CM2_ENH_COEFF1_H09 0x149 // default 32'H0 ++ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx ++ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx ++ #define REG_CM2_ENH_COEFF2_H09 0x14a // default 32'H0 ++ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx ++ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx ++ #define REG_CM2_ENH_COEFF3_H09 0x14b // default 32'H0 ++ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx ++ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx ++ #define REG_CM2_ENH_COEFF4_H09 0x14c // default 32'H0 ++ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx ++ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx ++ ++////========= NODE 10 COEFFICIENT ==============//// ++ ++ #define REG_CM2_ENH_COEFF0_H10 0x150 // default 32'H0 ++ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx ++ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx ++ #define REG_CM2_ENH_COEFF1_H10 0x151 // default 32'H0 ++ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx ++ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx ++ #define REG_CM2_ENH_COEFF2_H10 0x152 // default 32'H0 ++ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx ++ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx ++ #define REG_CM2_ENH_COEFF3_H10 0x153 // default 32'H0 ++ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx ++ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx ++ #define REG_CM2_ENH_COEFF4_H10 0x154 // default 32'H0 ++ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx ++ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx ++ ++////========= NODE 11 COEFFICIENT ==============//// ++ ++ #define REG_CM2_ENH_COEFF0_H11 0x158 // default 32'H0 ++ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx ++ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx ++ #define REG_CM2_ENH_COEFF1_H11 0x159 // default 32'H0 ++ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx ++ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx ++ #define REG_CM2_ENH_COEFF2_H11 0x15a // default 32'H0 ++ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx ++ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx ++ #define REG_CM2_ENH_COEFF3_H11 0x15b // default 32'H0 ++ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx ++ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx ++ #define REG_CM2_ENH_COEFF4_H11 0x15c // default 32'H0 ++ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx ++ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx ++ ++////========= NODE 12 COEFFICIENT ==============//// ++ ++ #define REG_CM2_ENH_COEFF0_H12 0x160 // default 32'H0 ++ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx ++ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx ++ #define REG_CM2_ENH_COEFF1_H12 0x161 // default 32'H0 ++ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx ++ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx ++ #define REG_CM2_ENH_COEFF2_H12 0x162 // default 32'H0 ++ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx ++ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx ++ #define REG_CM2_ENH_COEFF3_H12 0x163 // default 32'H0 ++ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx ++ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx ++ #define REG_CM2_ENH_COEFF4_H12 0x164 // default 32'H0 ++ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx ++ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx ++ ++////========= NODE 13 COEFFICIENT ==============//// ++ ++ #define REG_CM2_ENH_COEFF0_H13 0x168 // default 32'H0 ++ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx ++ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx ++ #define REG_CM2_ENH_COEFF1_H13 0x169 // default 32'H0 ++ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx ++ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx ++ #define REG_CM2_ENH_COEFF2_H13 0x16a // default 32'H0 ++ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx ++ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx ++ #define REG_CM2_ENH_COEFF3_H13 0x16b // default 32'H0 ++ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx ++ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx ++ #define REG_CM2_ENH_COEFF4_H13 0x16c // default 32'H0 ++ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx ++ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx ++ ++ ++/* Constraints ++0) ++ there are 16 regions totally. 8 regions are for hue adjustment, 8 regions are for sat adjustment. ++ the hue range of the 16 regions can be set to overlap, but if overlap, the hue range(start and end) must be same. ++ the 8 regions for hue adjustment should not overlap. if corresponding reg_hue_en_00 - 07 == 1 ++ the 8 regions for hue adjustment are defined by: (example are for region 0) ++ a) hue: ++ start: reg_hue_hue_shift_start_00[14:0] ++ end: ++ if reg_symmetry_en_00 == 0 ++ reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<5) ++ if reg_symmetry_en_00 == 1 ++ reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<6) ++ b) sat: ++ start: reg_hue_sat_low_00 ++ end: reg_hue_sat_high_00 ++ ++ the 8 regions for sat adjustment should not overlap. if corresponding reg_sat_en_00 - 07 == 1 ++ the 8 regions for sat adjustment are defined by: (example are for region 0) ++ a) hue: same as that for hue adjustment. ++ start: reg_hue_hue_shift_start_00[14:0] ++ end: ++ if reg_symmetry_en_00 == 0 ++ reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<5) ++ if reg_symmetry_en_00 == 1 ++ reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<6) ++ b) sat: ++ start: reg_sat_sat_low_00 ++ end: reg_sat_sat_high_00 ++ ++1) ++ reg_hue_hue_shift_range_00[7:0]: ++ reg_hue_hue_shift_range_01[7:0]: ++ reg_hue_hue_shift_range_02[7:0]: ++ reg_hue_hue_shift_range_03[7:0]: ++ reg_hue_hue_shift_range_04[7:0]: ++ reg_hue_hue_shift_range_05[7:0]: ++ reg_hue_hue_shift_range_06[7:0]: ++ reg_hue_hue_shift_range_07[7:0]: ++ must be greater or equal than 8'd8, so as reg_hue_range_inv_regxx can be represented by 0.0000_0000_xxxx_xxxx_xxxx_xxxx ++ ++2) ++ all regions of 0-7 should meet below requirement. below is just an example for region 7. ++ (reg_hue_lum_high_07 - reg_hue_lum_low_07) >= ++ (1<= ++ (1<= ++ (1<= ++ (1< msb ++//bit 6:4 pattern start ++//bit 2:0 pattern end ++#define VPP_OSD_HSC_INI_PAT_CTRL (0x1dc6) ++#define P_VPP_OSD_HSC_INI_PAT_CTRL (volatile unsigned int *)((0x1dc6 << 2) + 0xff900000) ++//bit 31:24, componet 0 ++//bit 23:16, component 1 ++//bit 15:8, component 2 ++//bit 7:0 component 3, alpha ++#define VPP_OSD_SC_DUMMY_DATA (0x1dc7) ++#define P_VPP_OSD_SC_DUMMY_DATA (volatile unsigned int *)((0x1dc7 << 2) + 0xff900000) ++//Bit 14 osc_sc_din_osd1_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha. ++//Bit 13 osc_sc_din_osd2_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha. ++//Bit 12 osc_sc_dout_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha. ++//Bit 12 osc_sc_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha. ++//Bit 11:4 default alpha for vd1 or vd2 if they are selected as the source ++//Bit 3 osd scaler path enable ++//Bit 1:0 osd_sc_sel, 00: select osd1 input, 01: select osd2 input, 10: select vd1 input, 11: select vd2 input after matrix ++#define VPP_OSD_SC_CTRL0 (0x1dc8) ++#define P_VPP_OSD_SC_CTRL0 (volatile unsigned int *)((0x1dc8 << 2) + 0xff900000) ++//Bit 28:16 OSD scaler input width minus 1 ++//Bit 12:0 OSD scaler input height minus 1 ++#define VPP_OSD_SCI_WH_M1 (0x1dc9) ++#define P_VPP_OSD_SCI_WH_M1 (volatile unsigned int *)((0x1dc9 << 2) + 0xff900000) ++//Bit 28:16 OSD scaler output horizontal start ++//Bit 12:0 OSD scaler output horizontal end ++#define VPP_OSD_SCO_H_START_END (0x1dca) ++#define P_VPP_OSD_SCO_H_START_END (volatile unsigned int *)((0x1dca << 2) + 0xff900000) ++//Bit 28:16 OSD scaler output vertical start ++//Bit 12:0 OSD scaler output vertical end ++#define VPP_OSD_SCO_V_START_END (0x1dcb) ++#define P_VPP_OSD_SCO_V_START_END (volatile unsigned int *)((0x1dcb << 2) + 0xff900000) ++//Because there are many coefficients used in the vertical filter and horizontal filters, ++//indirect access the coefficients of vertical filter and horizontal filter is used. ++//For vertical filter, there are 33x4 coefficients ++//For horizontal filter, there are 33x4 coefficients ++//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2) ++//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not ++//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef ++//Bit 8 type of index, 0: vertical coef, 1: horizontal coef ++//Bit 6:0 coef index ++#define VPP_OSD_SCALE_COEF_IDX (0x1dcc) ++#define P_VPP_OSD_SCALE_COEF_IDX (volatile unsigned int *)((0x1dcc << 2) + 0xff900000) ++//coefficients for vertical filter and horizontal filter ++#define VPP_OSD_SCALE_COEF (0x1dcd) ++#define P_VPP_OSD_SCALE_COEF (volatile unsigned int *)((0x1dcd << 2) + 0xff900000) ++//Bit 12:0 line number use to generate interrupt when line == this number ++#define VPP_INT_LINE_NUM (0x1dce) ++#define P_VPP_INT_LINE_NUM (volatile unsigned int *)((0x1dce << 2) + 0xff900000) ++#define VPP_XVYCC_MISC (0x1dcf) ++#define P_VPP_XVYCC_MISC (volatile unsigned int *)((0x1dcf << 2) + 0xff900000) ++// new add lti/cti in 120924 ++//Bit 3: 0 //default== 0 reg_hlti_dn_flt_coe[0] ++//Bit 7: 4 //default== 0 reg_hlti_dn_flt_coe[1] ++//Bit 11: 8 //default== 0 reg_hlti_dn_flt_coe[2] ++//Bit 15:12 //default== 2 reg_hlti_dn_flt_coe[3] ++//Bit 19:16 //default== 4 reg_hlti_dn_flt_coe[4] ++//Bit 22:20 //default== 3 reg_hlti_dn_flt_nrm u3: 3~7 ++#define VPP_HLTI_DN_FLT (0x1dd0) ++#define P_VPP_HLTI_DN_FLT (volatile unsigned int *)((0x1dd0 << 2) + 0xff900000) ++//Bit 7: 0 //default== 8 reg_hlti_bst_gain u8, norm 16 as "1" ++//Bit 15: 8 //default== 20 reg_hlti_bst_core u8, norm 32 as "1" ++//Bit 23:16 //default== 32 reg_hlti_oob_gain u8, norm 32 as "1" ++//Bit 28:24 //default== 0 reg_hlti_oob_core u5 ++#define VPP_HLTI_GAIN (0x1dd1) ++#define P_VPP_HLTI_GAIN (volatile unsigned int *)((0x1dd1 << 2) + 0xff900000) ++//Bit 7: 0 //default== 2 reg_hlti_clp_ofst u8, ++//Bit 8 //default== 0 reg_hlti_clp_mode u1, ++//Bit 11: 9 //default== 1 reg_hlti_clp_wind u3, ++//Bit 14:12 //default== 1 reg_hlti_bst_fltr u3, ++//Bit 15 //default== 1 reg_hlti_enable u1, ++#define VPP_HLTI_PARA (0x1dd2) ++#define P_VPP_HLTI_PARA (volatile unsigned int *)((0x1dd2 << 2) + 0xff900000) ++//Bit 3: 0 //default== 0 reg_hcti_dn_flt_coe[0] ++//Bit 7: 4 //default== 0 reg_hcti_dn_flt_coe[1] ++//Bit 11: 8 //default== 1 reg_hcti_dn_flt_coe[2] ++//Bit 15:12 //default== 2 reg_hcti_dn_flt_coe[3] ++//Bit 19:16 //default== 2 reg_hcti_dn_flt_coe[4] ++//Bit 22:20 //default== 3 reg_hcti_dn_flt_nrm u3: 3~7 ++#define VPP_HCTI_DN_FLT (0x1dd3) ++#define P_VPP_HCTI_DN_FLT (volatile unsigned int *)((0x1dd3 << 2) + 0xff900000) ++//Bit 7: 0 //default== 48 reg_hcti_bst_gain u8, norm 16 as "1" ++//Bit15: 8 //default== 17 reg_hcti_bst_core u8, norm 32 as "1" ++//Bit23:16 //default== 16 reg_hcti_oob_gain u8, norm 32 as "1" ++//Bit28:24 //default== 0 reg_hcti_oob_core u5 ++#define VPP_HCTI_GAIN (0x1dd4) ++#define P_VPP_HCTI_GAIN (volatile unsigned int *)((0x1dd4 << 2) + 0xff900000) ++//Bit 7: 0 //default== 0 reg_hcti_clp_ofst u8, ++//Bit 8 //default== 1 reg_hcti_clp_mode u1, ++//Bit 11: 9 //default== 3 reg_hcti_clp_wind u3, ++//Bit 14:12 //default== 6 reg_hcti_bst_fltr u3, ++//Bit 15 //default== 1 reg_hcti_enable u1, ++#define VPP_HCTI_PARA (0x1dd5) ++#define P_VPP_HCTI_PARA (volatile unsigned int *)((0x1dd5 << 2) + 0xff900000) ++//Bit 7: 0 //default== 48 reg_vcti_bst_gain u8, normalize 16 as "1" ++//Bit 15: 8 //default== 10 reg_vcti_bst_core u8 ++//Bit 19:16 //default== 10 reg_vcti_clp_ofst u4 ++//Bit 20 //default== 1 reg_vcti_clp_wind u1, 0: wind 3, 1: wind5 ++#define VPP_VCTI_PARA (0x1dd6) ++#define P_VPP_VCTI_PARA (volatile unsigned int *)((0x1dd6 << 2) + 0xff900000) ++//`define VPP_MATRIX_PROBE_COLOR1 8'hd7 //defined before ++//Bit 31 //default== 0, urgent fifo hold enable ++//Bit 28:12 //default== 0, urgent fifo hold line threshold ++//Bit 15 //default== 0, urgent_ctrl_en ++//Bit 14 //default== 0, urgent_wr, if true for write buffer ++//Bit 13 //default== 0, out_inv_en ++//Bit 12 //default == 0, urgent_ini_value ++//Bit 11:6 //default == 0, up_th up threshold ++//Bit 5:0 //default == 0, dn_th dn threshold ++#define VPP_OFIFO_URG_CTRL (0x1dd8) ++#define P_VPP_OFIFO_URG_CTRL (volatile unsigned int *)((0x1dd8 << 2) + 0xff900000) ++#define VPP_CLIP_MISC0 (0x1dd9) ++#define P_VPP_CLIP_MISC0 (volatile unsigned int *)((0x1dd9 << 2) + 0xff900000) ++//Bit 29:20 // default == 1023, final clip r channel top ++//Bit 19:10 // default == 1023, final clip g channel top ++//Bit 9: 0 // default == 1023, final clip b channel top ++#define VPP_CLIP_MISC1 (0x1dda) ++#define P_VPP_CLIP_MISC1 (volatile unsigned int *)((0x1dda << 2) + 0xff900000) ++//Bit 29:20 // default == 0, final clip r channel bottom ++//Bit 19:10 // default == 0, final clip g channel bottom ++//Bit 9: 0 // default == 0, final clip b channel bottom ++#define VPP_MATRIX_COEF13_14 (0x1ddb) ++#define P_VPP_MATRIX_COEF13_14 (volatile unsigned int *)((0x1ddb << 2) + 0xff900000) ++//Bit 28:16 // default == 0, matrix coef13 ++//Bit 12:0 // default == 0, matrix coef14 ++#define VPP_MATRIX_COEF23_24 (0x1ddc) ++#define P_VPP_MATRIX_COEF23_24 (volatile unsigned int *)((0x1ddc << 2) + 0xff900000) ++//Bit 28:16 // default == 0, matrix coef23 ++//Bit 12:0 // default == 0, matrix coef24 ++#define VPP_MATRIX_COEF15_25 (0x1ddd) ++#define P_VPP_MATRIX_COEF15_25 (volatile unsigned int *)((0x1ddd << 2) + 0xff900000) ++//Bit 28:16 // default == 0, matrix coef15 ++//Bit 12:0 // default == 0, matrix coef25 ++#define VPP_MATRIX_CLIP (0x1dde) ++#define P_VPP_MATRIX_CLIP (volatile unsigned int *)((0x1dde << 2) + 0xff900000) ++//Bit 7:5 // default == 0, mat rs ++//Bit 4:3 // default == 0, mat clmod ++//Bit 2:0 // default == 0, mat clip enable ++#define VPP_XVYCC_MISC0 (0x1ddf) ++#define P_VPP_XVYCC_MISC0 (volatile unsigned int *)((0x1ddf << 2) + 0xff900000) ++//Bit 29:20 // default == 1023, xvycc clip r channel top ++//Bit 19:10 // default == 1023, xvycc clip g channel top ++//Bit 9: 0 // default == 1023, xvycc clip b channel top ++#define VPP_XVYCC_MISC1 (0x1de0) ++#define P_VPP_XVYCC_MISC1 (volatile unsigned int *)((0x1de0 << 2) + 0xff900000) ++//Bit 29:20 // default == 0, xvycc clip r channel bottom ++//Bit 19:10 // default == 0, xvycc clip g channel bottom ++//Bit 9: 0 // default == 0, xvycc clip b channel bottom ++#define VPP_VD1_CLIP_MISC0 (0x1de1) ++#define P_VPP_VD1_CLIP_MISC0 (volatile unsigned int *)((0x1de1 << 2) + 0xff900000) ++//Bit 29:20 // default == 1023, vd1 clip r channel top ++//Bit 19:10 // default == 1023, vd1 clip g channel top ++//Bit 9: 0 // default == 1023, vd1 clip b channel top ++#define VPP_VD1_CLIP_MISC1 (0x1de2) ++#define P_VPP_VD1_CLIP_MISC1 (volatile unsigned int *)((0x1de2 << 2) + 0xff900000) ++//Bit 29:20 // default == 0, vd1 clip r channel bottom ++//Bit 19:10 // default == 0, vd1 clip g channel bottom ++//Bit 9: 0 // default == 0, vd1 clip b channel bottom ++#define VPP_VD2_CLIP_MISC0 (0x1de3) ++#define P_VPP_VD2_CLIP_MISC0 (volatile unsigned int *)((0x1de3 << 2) + 0xff900000) ++//Bit 29:20 // default == 1023, vd2 clip r channel top ++//Bit 19:10 // default == 1023, vd2 clip g channel top ++//Bit 9: 0 // default == 1023, vd2 clip b channel top ++#define VPP_VD2_CLIP_MISC1 (0x1de4) ++#define P_VPP_VD2_CLIP_MISC1 (volatile unsigned int *)((0x1de4 << 2) + 0xff900000) ++//Bit 29:20 // default == 0, vd2 clip r channel bottom ++//Bit 19:10 // default == 0, vd2 clip g channel bottom ++//Bit 9: 0 // default == 0, vd2 clip b channel bottom ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: vpp_regs.h ++// ++//`define VIU2_VCBUS_BASE 8'h1e ++// ++// Reading file: v2regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++//=========================================================================== ++// Video Interface 2 Registers 0xe00 - 0xeff ++//=========================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: VIU2_VCBUS_BASE = 0x1e ++// ----------------------------------------------- ++#define VIU2_ADDR_START (0x1e00) ++#define P_VIU2_ADDR_START (volatile unsigned int *)((0x1e00 << 2) + 0xff900000) ++#define VIU2_ADDR_END (0x1eff) ++#define P_VIU2_ADDR_END (volatile unsigned int *)((0x1eff << 2) + 0xff900000) ++//------------------------------------------------------------------------------ ++// VIU2 top-level registers ++//------------------------------------------------------------------------------ ++// Bit 0 RW, osd1_reset ++// Bit 1 RW, osd2_reset ++// Bit 2 RW, vd1_reset ++// Bit 3 RW, vd1_fmt_reset ++// Bit 7 RW, vpp_reset ++#define VIU2_SW_RESET (0x1e01) ++#define P_VIU2_SW_RESET (volatile unsigned int *)((0x1e01 << 2) + 0xff900000) ++#define VIU2_SW_RESET0 (0x1e02) ++#define P_VIU2_SW_RESET0 (volatile unsigned int *)((0x1e02 << 2) + 0xff900000) ++// Bit 0 RW, software reset for mcvecrd_mif ++// Bit 1 RW, software reset for mcinfowr_mif ++// Bit 2 RW, software reset for mcinford_mif ++//bit 8 if true, vsync interrup is generate only field == 0 ++//bit 7:0 fix_disable ++#define VIU2_MISC_CTRL0 (0x1e06) ++#define P_VIU2_MISC_CTRL0 (volatile unsigned int *)((0x1e06 << 2) + 0xff900000) ++//------------------------------------------------------------------------------ ++// OSD1 registers ++//------------------------------------------------------------------------------ ++// Bit 31 Reserved ++// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics; ++// 0=use gated clock for low power. ++// Bit 29 R, test_rd_dsr ++// Bit 28 R, osd_done ++// Bit 27:24 R, osd_blk_mode ++// Bit 23:22 R, osd_blk_ptr ++// Bit 21 R, osd_enable ++// ++// Bit 20:12 RW, global_alpha ++// Bit 11 RW, test_rd_en ++// Bit 10: 9 Reserved for control signals ++// Bit 8: 5 RW, ctrl_mtch_y ++// Bit 4 RW, ctrl_422to444 ++// Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable; ++// Bit 1 to enable block 1, and so on. ++#define VIU2_OSD1_CTRL_STAT (0x1e10) ++#define P_VIU2_OSD1_CTRL_STAT (volatile unsigned int *)((0x1e10 << 2) + 0xff900000) ++// Bit 31:26 Reserved ++// Bit 25:16 R, fifo_count ++// Bit 15: 6 Reserved ++// Bit 5: 4 RW, hold_fifo_lines[6:5] ++// Bit 3 RW, rgb2yuv_full_range ++// Bit 2 RW, alpha_9b_mode ++// Bit 1 RW, reserved ++// Bit 0 RW, color_expand_mode ++#define VIU2_OSD1_CTRL_STAT2 (0x1e2d) ++#define P_VIU2_OSD1_CTRL_STAT2 (volatile unsigned int *)((0x1e2d << 2) + 0xff900000) ++// Bit 31: 9 Reserved ++// Bit 8 RW, 0 = Write LUT, 1 = Read LUT ++// Bit 7: 0 RW, lut_addr ++#define VIU2_OSD1_COLOR_ADDR (0x1e11) ++#define P_VIU2_OSD1_COLOR_ADDR (volatile unsigned int *)((0x1e11 << 2) + 0xff900000) ++// Bit 31:24 RW, Y or R ++// Bit 23:16 RW, Cb or G ++// Bit 15: 8 RW, Cr or B ++// Bit 7: 0 RW, Alpha ++#define VIU2_OSD1_COLOR (0x1e12) ++#define P_VIU2_OSD1_COLOR (volatile unsigned int *)((0x1e12 << 2) + 0xff900000) ++// Bit 31:24 RW, Y or R ++// Bit 23:16 RW, Cb or G ++// Bit 15: 8 RW, Cr or B ++// Bit 7: 0 RW, Alpha ++#define VIU2_OSD1_TCOLOR_AG0 (0x1e17) ++#define P_VIU2_OSD1_TCOLOR_AG0 (volatile unsigned int *)((0x1e17 << 2) + 0xff900000) ++#define VIU2_OSD1_TCOLOR_AG1 (0x1e18) ++#define P_VIU2_OSD1_TCOLOR_AG1 (volatile unsigned int *)((0x1e18 << 2) + 0xff900000) ++#define VIU2_OSD1_TCOLOR_AG2 (0x1e19) ++#define P_VIU2_OSD1_TCOLOR_AG2 (volatile unsigned int *)((0x1e19 << 2) + 0xff900000) ++#define VIU2_OSD1_TCOLOR_AG3 (0x1e1a) ++#define P_VIU2_OSD1_TCOLOR_AG3 (volatile unsigned int *)((0x1e1a << 2) + 0xff900000) ++// Bit 31:30 Reserved ++// Bit 29 RW, y_rev: 0=normal read, 1=reverse read in Y direction ++// Bit 28 RW, x_rev: 0=normal read, 1=reverse read in X direction ++// Bit 27:24 Reserved ++// Bit 23:16 RW, tbl_addr ++// Bit 15 RW, little_endian: 0=big endian, 1=little endian ++// Bit 14 RW, rpt_y ++// Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous ++// pixel; 11=Interpolate with the average value ++// between previous and next pixel. ++// Bit 11: 8 RW, osd_blk_mode ++// Bit 7 RW, rgb_en ++// Bit 6 RW, tc_alpha_en ++// Bit 5: 2 RW, color_matrix ++// Bit 1 RW, interlace_en ++// Bit 0 RW, interlace_sel_odd ++#define VIU2_OSD1_BLK0_CFG_W0 (0x1e1b) ++#define P_VIU2_OSD1_BLK0_CFG_W0 (volatile unsigned int *)((0x1e1b << 2) + 0xff900000) ++#define VIU2_OSD1_BLK1_CFG_W0 (0x1e1f) ++#define P_VIU2_OSD1_BLK1_CFG_W0 (volatile unsigned int *)((0x1e1f << 2) + 0xff900000) ++#define VIU2_OSD1_BLK2_CFG_W0 (0x1e23) ++#define P_VIU2_OSD1_BLK2_CFG_W0 (volatile unsigned int *)((0x1e23 << 2) + 0xff900000) ++#define VIU2_OSD1_BLK3_CFG_W0 (0x1e27) ++#define P_VIU2_OSD1_BLK3_CFG_W0 (volatile unsigned int *)((0x1e27 << 2) + 0xff900000) ++// Bit 31:29 Reserved ++// Bit 28:16 RW, x_end ++// Bit 15:13 Reserved ++// Bit 12: 0 RW, x_start ++#define VIU2_OSD1_BLK0_CFG_W1 (0x1e1c) ++#define P_VIU2_OSD1_BLK0_CFG_W1 (volatile unsigned int *)((0x1e1c << 2) + 0xff900000) ++#define VIU2_OSD1_BLK1_CFG_W1 (0x1e20) ++#define P_VIU2_OSD1_BLK1_CFG_W1 (volatile unsigned int *)((0x1e20 << 2) + 0xff900000) ++#define VIU2_OSD1_BLK2_CFG_W1 (0x1e24) ++#define P_VIU2_OSD1_BLK2_CFG_W1 (volatile unsigned int *)((0x1e24 << 2) + 0xff900000) ++#define VIU2_OSD1_BLK3_CFG_W1 (0x1e28) ++#define P_VIU2_OSD1_BLK3_CFG_W1 (volatile unsigned int *)((0x1e28 << 2) + 0xff900000) ++// Bit 31:29 Reserved ++// Bit 28:16 RW, y_end ++// Bit 15:13 Reserved ++// Bit 12: 0 RW, y_start ++#define VIU2_OSD1_BLK0_CFG_W2 (0x1e1d) ++#define P_VIU2_OSD1_BLK0_CFG_W2 (volatile unsigned int *)((0x1e1d << 2) + 0xff900000) ++#define VIU2_OSD1_BLK1_CFG_W2 (0x1e21) ++#define P_VIU2_OSD1_BLK1_CFG_W2 (volatile unsigned int *)((0x1e21 << 2) + 0xff900000) ++#define VIU2_OSD1_BLK2_CFG_W2 (0x1e25) ++#define P_VIU2_OSD1_BLK2_CFG_W2 (volatile unsigned int *)((0x1e25 << 2) + 0xff900000) ++#define VIU2_OSD1_BLK3_CFG_W2 (0x1e29) ++#define P_VIU2_OSD1_BLK3_CFG_W2 (volatile unsigned int *)((0x1e29 << 2) + 0xff900000) ++// Bit 31:28 Reserved ++// Bit 27:16 RW, h_end ++// Bit 15:12 Reserved ++// Bit 11: 0 RW, h_start ++#define VIU2_OSD1_BLK0_CFG_W3 (0x1e1e) ++#define P_VIU2_OSD1_BLK0_CFG_W3 (volatile unsigned int *)((0x1e1e << 2) + 0xff900000) ++#define VIU2_OSD1_BLK1_CFG_W3 (0x1e22) ++#define P_VIU2_OSD1_BLK1_CFG_W3 (volatile unsigned int *)((0x1e22 << 2) + 0xff900000) ++#define VIU2_OSD1_BLK2_CFG_W3 (0x1e26) ++#define P_VIU2_OSD1_BLK2_CFG_W3 (volatile unsigned int *)((0x1e26 << 2) + 0xff900000) ++#define VIU2_OSD1_BLK3_CFG_W3 (0x1e2a) ++#define P_VIU2_OSD1_BLK3_CFG_W3 (volatile unsigned int *)((0x1e2a << 2) + 0xff900000) ++// Bit 31:28 Reserved ++// Bit 27:16 RW, v_end ++// Bit 15:12 Reserved ++// Bit 11: 0 RW, v_start ++#define VIU2_OSD1_BLK0_CFG_W4 (0x1e13) ++#define P_VIU2_OSD1_BLK0_CFG_W4 (volatile unsigned int *)((0x1e13 << 2) + 0xff900000) ++#define VIU2_OSD1_BLK1_CFG_W4 (0x1e14) ++#define P_VIU2_OSD1_BLK1_CFG_W4 (volatile unsigned int *)((0x1e14 << 2) + 0xff900000) ++#define VIU2_OSD1_BLK2_CFG_W4 (0x1e15) ++#define P_VIU2_OSD1_BLK2_CFG_W4 (volatile unsigned int *)((0x1e15 << 2) + 0xff900000) ++#define VIU2_OSD1_BLK3_CFG_W4 (0x1e16) ++#define P_VIU2_OSD1_BLK3_CFG_W4 (volatile unsigned int *)((0x1e16 << 2) + 0xff900000) ++// Bit 31 RW, burst_len_sel[2] of [2:0] ++// Bit 30 RW, byte_swap: In addition to endian control, further define ++// whether to swap upper and lower byte within a 16-bit mem word. ++// 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]} ++// Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word ++// Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif ++// Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved ++// Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT ++// Bit 19 R, fifo_overflow ++// ++// Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8. ++// Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128. ++// Bit 9: 5 RW, hold_fifo_lines[4:0] ++// Bit 4 RW, clear_err: one pulse to clear fifo_overflow ++// Bit 3 RW, fifo_sync_rst ++// Bit 2: 1 RW, endian ++// Bit 0 RW, urgent ++#define VIU2_OSD1_FIFO_CTRL_STAT (0x1e2b) ++#define P_VIU2_OSD1_FIFO_CTRL_STAT (volatile unsigned int *)((0x1e2b << 2) + 0xff900000) ++// Bit 31:24 R, Y or R ++// Bit 23:16 R, Cb or G ++// Bit 15: 8 R, Cr or B ++// Bit 7: 0 R, Output Alpha[8:1] ++#define VIU2_OSD1_TEST_RDDATA (0x1e2c) ++#define P_VIU2_OSD1_TEST_RDDATA (volatile unsigned int *)((0x1e2c << 2) + 0xff900000) ++// Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate. ++// Bit 12: 0 RW, effective FIFO size when prot_en=1. ++#define VIU2_OSD1_PROT_CTRL (0x1e2e) ++#define P_VIU2_OSD1_PROT_CTRL (volatile unsigned int *)((0x1e2e << 2) + 0xff900000) ++//------------------------------------------------------------------------------ ++// OSD2 registers ++//------------------------------------------------------------------------------ ++// Bit 31 Reserved ++// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics; ++// 0=use gated clock for low power. ++// Bit 29 R, test_rd_dsr ++// Bit 28 R, osd_done ++// Bit 27:24 R, osd_blk_mode ++// Bit 23:22 R, osd_blk_ptr ++// Bit 21 R, osd_enable ++// ++// Bit 20:12 RW, global_alpha ++// Bit 11 RW, test_rd_en ++// Bit 10 RW, hl2_en ++// Bit 9 RW, hl1_en ++// Bit 8: 5 RW, ctrl_mtch_y ++// Bit 4 RW, ctrl_422to444 ++// Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable; ++// Bit 1 to enable block 1, and so on. ++#define VIU2_OSD2_CTRL_STAT (0x1e30) ++#define P_VIU2_OSD2_CTRL_STAT (volatile unsigned int *)((0x1e30 << 2) + 0xff900000) ++// Bit 31:26 Reserved ++// Bit 25:16 R, fifo_count ++// Bit 15: 6 Reserved ++// Bit 5: 4 RW, hold_fifo_lines[6:5] ++// Bit 3 RW, rgb2yuv_full_range ++// Bit 2 RW, alpha_9b_mode ++// Bit 1 RW, reserved ++// Bit 0 RW, color_expand_mode ++#define VIU2_OSD2_CTRL_STAT2 (0x1e4d) ++#define P_VIU2_OSD2_CTRL_STAT2 (volatile unsigned int *)((0x1e4d << 2) + 0xff900000) ++// Bit 31: 9 Reserved ++// Bit 8 RW, 0 = Write LUT, 1 = Read LUT ++// Bit 7: 0 RW, lut_addr ++#define VIU2_OSD2_COLOR_ADDR (0x1e31) ++#define P_VIU2_OSD2_COLOR_ADDR (volatile unsigned int *)((0x1e31 << 2) + 0xff900000) ++// Bit 31:24 RW, Y or R ++// Bit 23:16 RW, Cb or G ++// Bit 15: 8 RW, Cr or B ++// Bit 7: 0 RW, Alpha ++#define VIU2_OSD2_COLOR (0x1e32) ++#define P_VIU2_OSD2_COLOR (volatile unsigned int *)((0x1e32 << 2) + 0xff900000) ++// Bit 31:28 Reserved ++// Bit 27:16 RW, hl[1-2]_h/v_start ++// Bit 15:12 Reserved ++// Bit 11: 0 RW, hl[1-2]_h/v_end ++#define VIU2_OSD2_HL1_H_START_END (0x1e33) ++#define P_VIU2_OSD2_HL1_H_START_END (volatile unsigned int *)((0x1e33 << 2) + 0xff900000) ++#define VIU2_OSD2_HL1_V_START_END (0x1e34) ++#define P_VIU2_OSD2_HL1_V_START_END (volatile unsigned int *)((0x1e34 << 2) + 0xff900000) ++#define VIU2_OSD2_HL2_H_START_END (0x1e35) ++#define P_VIU2_OSD2_HL2_H_START_END (volatile unsigned int *)((0x1e35 << 2) + 0xff900000) ++#define VIU2_OSD2_HL2_V_START_END (0x1e36) ++#define P_VIU2_OSD2_HL2_V_START_END (volatile unsigned int *)((0x1e36 << 2) + 0xff900000) ++// Bit 31:24 RW, Y or R ++// Bit 23:16 RW, Cb or G ++// Bit 15: 8 RW, Cr or B ++// Bit 7: 0 RW, Alpha ++#define VIU2_OSD2_TCOLOR_AG0 (0x1e37) ++#define P_VIU2_OSD2_TCOLOR_AG0 (volatile unsigned int *)((0x1e37 << 2) + 0xff900000) ++#define VIU2_OSD2_TCOLOR_AG1 (0x1e38) ++#define P_VIU2_OSD2_TCOLOR_AG1 (volatile unsigned int *)((0x1e38 << 2) + 0xff900000) ++#define VIU2_OSD2_TCOLOR_AG2 (0x1e39) ++#define P_VIU2_OSD2_TCOLOR_AG2 (volatile unsigned int *)((0x1e39 << 2) + 0xff900000) ++#define VIU2_OSD2_TCOLOR_AG3 (0x1e3a) ++#define P_VIU2_OSD2_TCOLOR_AG3 (volatile unsigned int *)((0x1e3a << 2) + 0xff900000) ++// Bit 31:24 Reserved ++// Bit 23:16 RW, tbl_addr ++// Bit 15 RW, little_endian: 0=big endian, 1=little endian ++// Bit 14 RW, rpt_y ++// Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous ++// pixel; 11=Interpolate with the average value ++// between previous and next pixel. ++// Bit 11: 8 RW, osd_blk_mode ++// Bit 7 RW, rgb_en ++// Bit 6 RW, tc_alpha_en ++// Bit 5: 2 RW, color_matrix ++// Bit 1 RW, interlace_en ++// Bit 0 RW, interlace_sel_odd ++#define VIU2_OSD2_BLK0_CFG_W0 (0x1e3b) ++#define P_VIU2_OSD2_BLK0_CFG_W0 (volatile unsigned int *)((0x1e3b << 2) + 0xff900000) ++#define VIU2_OSD2_BLK1_CFG_W0 (0x1e3f) ++#define P_VIU2_OSD2_BLK1_CFG_W0 (volatile unsigned int *)((0x1e3f << 2) + 0xff900000) ++#define VIU2_OSD2_BLK2_CFG_W0 (0x1e43) ++#define P_VIU2_OSD2_BLK2_CFG_W0 (volatile unsigned int *)((0x1e43 << 2) + 0xff900000) ++#define VIU2_OSD2_BLK3_CFG_W0 (0x1e47) ++#define P_VIU2_OSD2_BLK3_CFG_W0 (volatile unsigned int *)((0x1e47 << 2) + 0xff900000) ++// Bit 31:29 Reserved ++// Bit 28:16 RW, x_end ++// Bit 15:13 Reserved ++// Bit 12: 0 RW, x_start ++#define VIU2_OSD2_BLK0_CFG_W1 (0x1e3c) ++#define P_VIU2_OSD2_BLK0_CFG_W1 (volatile unsigned int *)((0x1e3c << 2) + 0xff900000) ++#define VIU2_OSD2_BLK1_CFG_W1 (0x1e40) ++#define P_VIU2_OSD2_BLK1_CFG_W1 (volatile unsigned int *)((0x1e40 << 2) + 0xff900000) ++#define VIU2_OSD2_BLK2_CFG_W1 (0x1e44) ++#define P_VIU2_OSD2_BLK2_CFG_W1 (volatile unsigned int *)((0x1e44 << 2) + 0xff900000) ++#define VIU2_OSD2_BLK3_CFG_W1 (0x1e48) ++#define P_VIU2_OSD2_BLK3_CFG_W1 (volatile unsigned int *)((0x1e48 << 2) + 0xff900000) ++// Bit 31:29 Reserved ++// Bit 28:16 RW, y_end ++// Bit 15:13 Reserved ++// Bit 12: 0 RW, y_start ++#define VIU2_OSD2_BLK0_CFG_W2 (0x1e3d) ++#define P_VIU2_OSD2_BLK0_CFG_W2 (volatile unsigned int *)((0x1e3d << 2) + 0xff900000) ++#define VIU2_OSD2_BLK1_CFG_W2 (0x1e41) ++#define P_VIU2_OSD2_BLK1_CFG_W2 (volatile unsigned int *)((0x1e41 << 2) + 0xff900000) ++#define VIU2_OSD2_BLK2_CFG_W2 (0x1e45) ++#define P_VIU2_OSD2_BLK2_CFG_W2 (volatile unsigned int *)((0x1e45 << 2) + 0xff900000) ++#define VIU2_OSD2_BLK3_CFG_W2 (0x1e49) ++#define P_VIU2_OSD2_BLK3_CFG_W2 (volatile unsigned int *)((0x1e49 << 2) + 0xff900000) ++// Bit 31:28 Reserved ++// Bit 27:16 RW, h_end ++// Bit 15:12 Reserved ++// Bit 11: 0 RW, h_start ++#define VIU2_OSD2_BLK0_CFG_W3 (0x1e3e) ++#define P_VIU2_OSD2_BLK0_CFG_W3 (volatile unsigned int *)((0x1e3e << 2) + 0xff900000) ++#define VIU2_OSD2_BLK1_CFG_W3 (0x1e42) ++#define P_VIU2_OSD2_BLK1_CFG_W3 (volatile unsigned int *)((0x1e42 << 2) + 0xff900000) ++#define VIU2_OSD2_BLK2_CFG_W3 (0x1e46) ++#define P_VIU2_OSD2_BLK2_CFG_W3 (volatile unsigned int *)((0x1e46 << 2) + 0xff900000) ++#define VIU2_OSD2_BLK3_CFG_W3 (0x1e4a) ++#define P_VIU2_OSD2_BLK3_CFG_W3 (volatile unsigned int *)((0x1e4a << 2) + 0xff900000) ++// Bit 31:28 Reserved ++// Bit 27:16 RW, v_end ++// Bit 15:12 Reserved ++// Bit 11: 0 RW, v_start ++#define VIU2_OSD2_BLK0_CFG_W4 (0x1e64) ++#define P_VIU2_OSD2_BLK0_CFG_W4 (volatile unsigned int *)((0x1e64 << 2) + 0xff900000) ++#define VIU2_OSD2_BLK1_CFG_W4 (0x1e65) ++#define P_VIU2_OSD2_BLK1_CFG_W4 (volatile unsigned int *)((0x1e65 << 2) + 0xff900000) ++#define VIU2_OSD2_BLK2_CFG_W4 (0x1e66) ++#define P_VIU2_OSD2_BLK2_CFG_W4 (volatile unsigned int *)((0x1e66 << 2) + 0xff900000) ++#define VIU2_OSD2_BLK3_CFG_W4 (0x1e67) ++#define P_VIU2_OSD2_BLK3_CFG_W4 (volatile unsigned int *)((0x1e67 << 2) + 0xff900000) ++// Bit 31 RW, burst_len_sel[2] of [2:0] ++// Bit 30 RW, byte_swap: In addition to endian control, further define ++// whether to swap upper and lower byte within a 16-bit mem word. ++// 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]} ++// Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word ++// Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif ++// Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved ++// Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT ++// Bit 19 R, fifo_overflow ++// Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8. ++// Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128. ++// Bit 9: 5 RW, hold_fifo_lines[4:0] ++// Bit 4 RW, clear_err: one pulse to clear fifo_overflow ++// Bit 3 RW, fifo_sync_rst ++// Bit 2: 1 RW, endian ++// Bit 0 RW, urgent ++#define VIU2_OSD2_FIFO_CTRL_STAT (0x1e4b) ++#define P_VIU2_OSD2_FIFO_CTRL_STAT (volatile unsigned int *)((0x1e4b << 2) + 0xff900000) ++// Bit 31:24 R, Y or R ++// Bit 23:16 R, Cb or G ++// Bit 15: 8 R, Cr or B ++// Bit 7: 0 R, Output Alpha[8:1] ++#define VIU2_OSD2_TEST_RDDATA (0x1e4c) ++#define P_VIU2_OSD2_TEST_RDDATA (volatile unsigned int *)((0x1e4c << 2) + 0xff900000) ++// Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate. ++// Bit 12: 0 RW, effective FIFO size when prot_en=1. ++#define VIU2_OSD2_PROT_CTRL (0x1e4e) ++#define P_VIU2_OSD2_PROT_CTRL (volatile unsigned int *)((0x1e4e << 2) + 0xff900000) ++//------------------------------------------------------------------------------ ++// VD1 path ++//------------------------------------------------------------------------------ ++#define VIU2_VD1_IF0_GEN_REG (0x1e50) ++#define P_VIU2_VD1_IF0_GEN_REG (volatile unsigned int *)((0x1e50 << 2) + 0xff900000) ++#define VIU2_VD1_IF0_CANVAS0 (0x1e51) ++#define P_VIU2_VD1_IF0_CANVAS0 (volatile unsigned int *)((0x1e51 << 2) + 0xff900000) ++#define VIU2_VD1_IF0_CANVAS1 (0x1e52) ++#define P_VIU2_VD1_IF0_CANVAS1 (volatile unsigned int *)((0x1e52 << 2) + 0xff900000) ++#define VIU2_VD1_IF0_LUMA_X0 (0x1e53) ++#define P_VIU2_VD1_IF0_LUMA_X0 (volatile unsigned int *)((0x1e53 << 2) + 0xff900000) ++#define VIU2_VD1_IF0_LUMA_Y0 (0x1e54) ++#define P_VIU2_VD1_IF0_LUMA_Y0 (volatile unsigned int *)((0x1e54 << 2) + 0xff900000) ++#define VIU2_VD1_IF0_CHROMA_X0 (0x1e55) ++#define P_VIU2_VD1_IF0_CHROMA_X0 (volatile unsigned int *)((0x1e55 << 2) + 0xff900000) ++#define VIU2_VD1_IF0_CHROMA_Y0 (0x1e56) ++#define P_VIU2_VD1_IF0_CHROMA_Y0 (volatile unsigned int *)((0x1e56 << 2) + 0xff900000) ++#define VIU2_VD1_IF0_LUMA_X1 (0x1e57) ++#define P_VIU2_VD1_IF0_LUMA_X1 (volatile unsigned int *)((0x1e57 << 2) + 0xff900000) ++#define VIU2_VD1_IF0_LUMA_Y1 (0x1e58) ++#define P_VIU2_VD1_IF0_LUMA_Y1 (volatile unsigned int *)((0x1e58 << 2) + 0xff900000) ++#define VIU2_VD1_IF0_CHROMA_X1 (0x1e59) ++#define P_VIU2_VD1_IF0_CHROMA_X1 (volatile unsigned int *)((0x1e59 << 2) + 0xff900000) ++#define VIU2_VD1_IF0_CHROMA_Y1 (0x1e5a) ++#define P_VIU2_VD1_IF0_CHROMA_Y1 (volatile unsigned int *)((0x1e5a << 2) + 0xff900000) ++#define VIU2_VD1_IF0_RPT_LOOP (0x1e5b) ++#define P_VIU2_VD1_IF0_RPT_LOOP (volatile unsigned int *)((0x1e5b << 2) + 0xff900000) ++#define VIU2_VD1_IF0_LUMA0_RPT_PAT (0x1e5c) ++#define P_VIU2_VD1_IF0_LUMA0_RPT_PAT (volatile unsigned int *)((0x1e5c << 2) + 0xff900000) ++#define VIU2_VD1_IF0_CHROMA0_RPT_PAT (0x1e5d) ++#define P_VIU2_VD1_IF0_CHROMA0_RPT_PAT (volatile unsigned int *)((0x1e5d << 2) + 0xff900000) ++#define VIU2_VD1_IF0_LUMA1_RPT_PAT (0x1e5e) ++#define P_VIU2_VD1_IF0_LUMA1_RPT_PAT (volatile unsigned int *)((0x1e5e << 2) + 0xff900000) ++#define VIU2_VD1_IF0_CHROMA1_RPT_PAT (0x1e5f) ++#define P_VIU2_VD1_IF0_CHROMA1_RPT_PAT (volatile unsigned int *)((0x1e5f << 2) + 0xff900000) ++#define VIU2_VD1_IF0_LUMA_PSEL (0x1e60) ++#define P_VIU2_VD1_IF0_LUMA_PSEL (volatile unsigned int *)((0x1e60 << 2) + 0xff900000) ++#define VIU2_VD1_IF0_CHROMA_PSEL (0x1e61) ++#define P_VIU2_VD1_IF0_CHROMA_PSEL (volatile unsigned int *)((0x1e61 << 2) + 0xff900000) ++#define VIU2_VD1_IF0_DUMMY_PIXEL (0x1e62) ++#define P_VIU2_VD1_IF0_DUMMY_PIXEL (volatile unsigned int *)((0x1e62 << 2) + 0xff900000) ++#define VIU2_VD1_IF0_LUMA_FIFO_SIZE (0x1e63) ++#define P_VIU2_VD1_IF0_LUMA_FIFO_SIZE (volatile unsigned int *)((0x1e63 << 2) + 0xff900000) ++#define VIU2_VD1_IF0_RANGE_MAP_Y (0x1e6a) ++#define P_VIU2_VD1_IF0_RANGE_MAP_Y (volatile unsigned int *)((0x1e6a << 2) + 0xff900000) ++#define VIU2_VD1_IF0_RANGE_MAP_CB (0x1e6b) ++#define P_VIU2_VD1_IF0_RANGE_MAP_CB (volatile unsigned int *)((0x1e6b << 2) + 0xff900000) ++#define VIU2_VD1_IF0_RANGE_MAP_CR (0x1e6c) ++#define P_VIU2_VD1_IF0_RANGE_MAP_CR (volatile unsigned int *)((0x1e6c << 2) + 0xff900000) ++#define VIU2_VD1_IF0_GEN_REG2 (0x1e6d) ++#define P_VIU2_VD1_IF0_GEN_REG2 (volatile unsigned int *)((0x1e6d << 2) + 0xff900000) ++#define VIU2_VD1_IF0_PROT_CNTL (0x1e6e) ++#define P_VIU2_VD1_IF0_PROT_CNTL (volatile unsigned int *)((0x1e6e << 2) + 0xff900000) ++#define VIU2_VD1_IF0_URGENT_CTRL (0x1e6f) ++#define P_VIU2_VD1_IF0_URGENT_CTRL (volatile unsigned int *)((0x1e6f << 2) + 0xff900000) ++//Bit 31 it true, disable clock, otherwise enable clock ++//Bit 30 soft rst bit ++//Bit 28 if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation ++//Bit 27:24 horizontal formatter initial phase ++//Bit 23 horizontal formatter repeat pixel 0 enable ++//Bit 22:21 horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1 ++//Bit 20 horizontal formatter enable ++//Bit 19 if true, always use phase0 while vertical formater, meaning always ++// repeat data, no interpolation ++//Bit 18 if true, disable vertical formatter chroma repeat last line ++//Bit 17 veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable ++//Bit 16 veritcal formatter repeat line 0 enable ++//Bit 15:12 vertical formatter skip line num at the beginning ++//Bit 11:8 vertical formatter initial phase ++//Bit 7:1 vertical formatter phase step (3.4) ++//Bit 0 vertical formatter enable ++#define VIU2_VD1_FMT_CTRL (0x1e68) ++#define P_VIU2_VD1_FMT_CTRL (volatile unsigned int *)((0x1e68 << 2) + 0xff900000) ++//Bit 27:16 horizontal formatter width ++//Bit 11:0 vertical formatter width ++#define VIU2_VD1_FMT_W (0x1e69) ++#define P_VIU2_VD1_FMT_W (volatile unsigned int *)((0x1e69 << 2) + 0xff900000) ++#define VIU2_VD1_IF0_GEN_REG3 (0x1e70) ++#define P_VIU2_VD1_IF0_GEN_REG3 (volatile unsigned int *)((0x1e70 << 2) + 0xff900000) ++//bit 31:1, reversed ++//bit 0, cntl_64bit_rev ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: v2regs.h ++// ++//`define VIUB_VCBUS_BASE 8'h20 ++// ++// Reading file: vregs_clk1.h ++// ++//=========================================================================== ++// Video Interface Registers 0xa00 - 0xaff ++//=========================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: VIUB_VCBUS_BASE = 0x20 ++// ----------------------------------------------- ++#define VIUB_ADDR_START (0x2000) ++#define P_VIUB_ADDR_START (volatile unsigned int *)((0x2000 << 2) + 0xff900000) ++#define VIUB_ADDR_END (0x20ff) ++#define P_VIUB_ADDR_END (volatile unsigned int *)((0x20ff << 2) + 0xff900000) ++//`define TRACE_REG 8'ff ++//------------------------------------------------------------------------------ ++// VIU top-level registers ++//------------------------------------------------------------------------------ ++// Bit 0 RW, osd1_reset ++// Bit 1 RW, osd2_reset ++// Bit 2 RW, vd1_reset ++// Bit 3 RW, vd1_fmt_reset ++// Bit 4 RW, vd2_reset ++// Bit 5 RW, vd2_fmt_reset ++// Bit 6 RW, di_dsr1to2_reset ++// Bit 7 RW, vpp_reset ++// Bit 8 RW, di_if1_reset ++// Bit 9 RW, di_if1_fmt_reset ++// Bit 10 RW, di_inp_reset ++// Bit 11 RW, di_inp_fmt_reset ++// Bit 12 RW, di_mem_reset ++// Bit 13 RW, di_mem_fmt_reset ++// Bit 14 RW, di_nr_wr_mif_reset ++// Bit 15 RW, dein_wr_mif_reset ++// Bit 16 RW, di_chan2_mif_reset ++// Bit 17 RW, di_mtn_wr_mif_reset ++// Bit 18 RW, di_mtn_rd_mif_reset ++// Bit 19 RW, di_mad_reset ++// Bit 20 RW, vdin0_reset ++// Bit 21 RW, vdin1_reset ++// Bit 22 RW, nrin_mux_reset ++// Bit 23 RW, vdin0_wr_reset ++// Bit 24 RW, vdin1_wr_reset ++// Bit 25 RW, reserved ++// Bit 26 RW, d2d3_reset ++// Bit 27 RW, di_cont_wr_mif_reset ++// Bit 28 RW, di_cont_rd_mif_reset ++#define VIUB_SW_RESET (0x2001) ++#define P_VIUB_SW_RESET (volatile unsigned int *)((0x2001 << 2) + 0xff900000) ++#define VIUB_SW_RESET0 (0x2002) ++#define P_VIUB_SW_RESET0 (volatile unsigned int *)((0x2002 << 2) + 0xff900000) ++// Bit 0 RW, software reset for mcvecrd_mif ++// Bit 1 RW, software reset for mcinfowr_mif ++// Bit 2 RW, software reset for mcinford_mif ++//bit 8 if true, vsync interrup is generate only field == 0 ++//bit 7:0 fix_disable ++#define VIUB_MISC_CTRL0 (0x2006) ++#define P_VIUB_MISC_CTRL0 (volatile unsigned int *)((0x2006 << 2) + 0xff900000) ++#define VIUB_GCLK_CTRL0 (0x2007) ++#define P_VIUB_GCLK_CTRL0 (volatile unsigned int *)((0x2007 << 2) + 0xff900000) ++//// gclk_ctrl0_gl[ 0] : def=1 di_top_wrap clk enable ++//// ++//// gclk_ctrl0_gl[ 8] : def=0 mad pre clock enable, from mad clock ++//// gclk_ctrl0_gl[ 9] : def=0 mad post clock enable, from mad clock ++//// gclk_ctrl0_gl[10] : def=0 div clock enable, di slow clock including di&mcdi ++//// gclk_ctrl0_gl[11] : def=0 mcdi clock enable, from div clock ++//// gclk_ctrl0_gl[12] : def=0 di post clock enable, from div clock ++//// gclk_ctrl0_gl[13] : def=0 reserved ++//// gclk_ctrl0_gl[14] : def=1 di_no_clk_gate, for old di ++//// gclk_ctrl0_gl[15] : def=0 di_gate_all, for old di ++#define VIUB_GCLK_CTRL1 (0x2008) ++#define P_VIUB_GCLK_CTRL1 (volatile unsigned int *)((0x2008 << 2) + 0xff900000) ++//// gclk_ctrl1_gl[ 1: 0] : def=2'b00 mif-sub-arb clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl1_gl[ 3: 2] : def=2'b00 if1 rdmif clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl1_gl[ 5: 4] : def=2'b00 if2 rdmif clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl1_gl[ 7: 6] : def=2'b00 de wrmif clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl1_gl[ 9: 8] : def=2'b00 mtnrd post mif clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl1_gl[11:10] : def=2'b00 mcdi post mif clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl1_gl[17:16] : def=2'b00 inp rdmif clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl1_gl[19:18] : def=2'b00 mem rdmif clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl1_gl[21:20] : def=2'b00 chan rdmif clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl1_gl[23:22] : def=2'b00 nr wrmif clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl1_gl[25:24] : def=2'b00 mtn mif clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl1_gl[27:26] : def=2'b00 mcdi pre mif clock gate ctrl [1]: clock valid, [0]: clock close ++//// ++#define VIUB_GCLK_CTRL2 (0x2009) ++#define P_VIUB_GCLK_CTRL2 (volatile unsigned int *)((0x2009 << 2) + 0xff900000) ++//// gclk_ctrl_pre[ 1: 0] : def=2'b00 nr clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl_pre[ 3: 2] : def=2'b00 pd clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl_pre[ 5: 4] : def=2'b00 mtn det clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl_pre[ 7: 6] : def=2'b00 debanding clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl_pre[ 9: 8] : def=2'b00 dnr clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl_pre[11:10] : def=2'b00 nr&dnr blend clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl_pre[13:12] : def=2'b00 mcdi clock gate ctrl [1]: clock valid, [0]: clock close ++#define VIUB_GCLK_CTRL3 (0x200a) ++#define P_VIUB_GCLK_CTRL3 (volatile unsigned int *)((0x200a << 2) + 0xff900000) ++//// gclk_ctrl_post[ 1: 0] : def=2'b00 di blend clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl_post[ 3: 2] : def=2'b00 ei clock gate ctrl [1]: clock valid, [0]: clock close ++//// gclk_ctrl_post[ 5: 4] : def=2'b00 ei_0 clock gate ctrl [1]: clock valid, [0]: clock close ++#define DI_IF2_GEN_REG (0x2010) ++#define P_DI_IF2_GEN_REG (volatile unsigned int *)((0x2010 << 2) + 0xff900000) ++#define DI_IF2_CANVAS0 (0x2011) ++#define P_DI_IF2_CANVAS0 (volatile unsigned int *)((0x2011 << 2) + 0xff900000) ++#define DI_IF2_LUMA_X0 (0x2012) ++#define P_DI_IF2_LUMA_X0 (volatile unsigned int *)((0x2012 << 2) + 0xff900000) ++#define DI_IF2_LUMA_Y0 (0x2013) ++#define P_DI_IF2_LUMA_Y0 (volatile unsigned int *)((0x2013 << 2) + 0xff900000) ++#define DI_IF2_CHROMA_X0 (0x2014) ++#define P_DI_IF2_CHROMA_X0 (volatile unsigned int *)((0x2014 << 2) + 0xff900000) ++#define DI_IF2_CHROMA_Y0 (0x2015) ++#define P_DI_IF2_CHROMA_Y0 (volatile unsigned int *)((0x2015 << 2) + 0xff900000) ++#define DI_IF2_RPT_LOOP (0x2016) ++#define P_DI_IF2_RPT_LOOP (volatile unsigned int *)((0x2016 << 2) + 0xff900000) ++#define DI_IF2_LUMA0_RPT_PAT (0x2017) ++#define P_DI_IF2_LUMA0_RPT_PAT (volatile unsigned int *)((0x2017 << 2) + 0xff900000) ++#define DI_IF2_CHROMA0_RPT_PAT (0x2018) ++#define P_DI_IF2_CHROMA0_RPT_PAT (volatile unsigned int *)((0x2018 << 2) + 0xff900000) ++#define DI_IF2_DUMMY_PIXEL (0x2019) ++#define P_DI_IF2_DUMMY_PIXEL (volatile unsigned int *)((0x2019 << 2) + 0xff900000) ++#define DI_IF2_LUMA_FIFO_SIZE (0x201a) ++#define P_DI_IF2_LUMA_FIFO_SIZE (volatile unsigned int *)((0x201a << 2) + 0xff900000) ++#define DI_IF2_RANGE_MAP_Y (0x201b) ++#define P_DI_IF2_RANGE_MAP_Y (volatile unsigned int *)((0x201b << 2) + 0xff900000) ++#define DI_IF2_RANGE_MAP_CB (0x201c) ++#define P_DI_IF2_RANGE_MAP_CB (volatile unsigned int *)((0x201c << 2) + 0xff900000) ++#define DI_IF2_RANGE_MAP_CR (0x201d) ++#define P_DI_IF2_RANGE_MAP_CR (volatile unsigned int *)((0x201d << 2) + 0xff900000) ++#define DI_IF2_GEN_REG2 (0x201e) ++#define P_DI_IF2_GEN_REG2 (volatile unsigned int *)((0x201e << 2) + 0xff900000) ++#define DI_IF2_FMT_CTRL (0x201f) ++#define P_DI_IF2_FMT_CTRL (volatile unsigned int *)((0x201f << 2) + 0xff900000) ++#define DI_IF2_FMT_W (0x2020) ++#define P_DI_IF2_FMT_W (volatile unsigned int *)((0x2020 << 2) + 0xff900000) ++#define DI_IF2_URGENT_CTRL (0x2021) ++#define P_DI_IF2_URGENT_CTRL (volatile unsigned int *)((0x2021 << 2) + 0xff900000) ++//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path ++//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path ++#define DI_IF2_GEN_REG3 (0x2022) ++#define P_DI_IF2_GEN_REG3 (volatile unsigned int *)((0x2022 << 2) + 0xff900000) ++//bit 31:1, reversed ++//bit 0, cntl_64bit_rev ++#define DI_IF1_URGENT_CTRL (0x20a3) ++#define P_DI_IF1_URGENT_CTRL (volatile unsigned int *)((0x20a3 << 2) + 0xff900000) ++//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path ++//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path ++#define DI_INP_URGENT_CTRL (0x20a4) ++#define P_DI_INP_URGENT_CTRL (volatile unsigned int *)((0x20a4 << 2) + 0xff900000) ++//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di mem chroma path ++//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di mem luma path ++#define DI_MEM_URGENT_CTRL (0x20a5) ++#define P_DI_MEM_URGENT_CTRL (volatile unsigned int *)((0x20a5 << 2) + 0xff900000) ++//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di chan2 chroma path ++//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di chan2 luma path ++#define DI_CHAN2_URGENT_CTRL (0x20a6) ++#define P_DI_CHAN2_URGENT_CTRL (volatile unsigned int *)((0x20a6 << 2) + 0xff900000) ++#define DI_IF1_GEN_REG3 (0x20a7) ++#define P_DI_IF1_GEN_REG3 (volatile unsigned int *)((0x20a7 << 2) + 0xff900000) ++//bit 31:1, reversed ++//bit 0, cntl_64bit_rev ++#define DI_INP_GEN_REG3 (0x20a8) ++#define P_DI_INP_GEN_REG3 (volatile unsigned int *)((0x20a8 << 2) + 0xff900000) ++//bit 31:1, reversed ++//bit 0, cntl_64bit_rev ++#define DI_MEM_GEN_REG3 (0x20a9) ++#define P_DI_MEM_GEN_REG3 (volatile unsigned int *)((0x20a9 << 2) + 0xff900000) ++//bit 31:1, reversed ++//bit 0, cntl_64bit_rev ++#define DI_CHAN2_GEN_REG3 (0x20aa) ++#define P_DI_CHAN2_GEN_REG3 (volatile unsigned int *)((0x20aa << 2) + 0xff900000) ++//bit 31:1, reversed ++//bit 0, cntl_64bit_rev ++// ++// Closing file: vregs_clk1.h ++// ++//====================================================================== ++// vpu register. ++//====================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: VPU_VCBUS_BASE = 0x27 ++// ----------------------------------------------- ++#define VPU_OSD1_MMC_CTRL (0x2701) ++#define P_VPU_OSD1_MMC_CTRL (volatile unsigned int *)((0x2701 << 2) + 0xff900000) ++#define VPU_OSD2_MMC_CTRL (0x2702) ++#define P_VPU_OSD2_MMC_CTRL (volatile unsigned int *)((0x2702 << 2) + 0xff900000) ++#define VPU_VD1_MMC_CTRL (0x2703) ++#define P_VPU_VD1_MMC_CTRL (volatile unsigned int *)((0x2703 << 2) + 0xff900000) ++#define VPU_VD2_MMC_CTRL (0x2704) ++#define P_VPU_VD2_MMC_CTRL (volatile unsigned int *)((0x2704 << 2) + 0xff900000) ++#define VPU_DI_IF1_MMC_CTRL (0x2705) ++#define P_VPU_DI_IF1_MMC_CTRL (volatile unsigned int *)((0x2705 << 2) + 0xff900000) ++#define VPU_DI_MEM_MMC_CTRL (0x2706) ++#define P_VPU_DI_MEM_MMC_CTRL (volatile unsigned int *)((0x2706 << 2) + 0xff900000) ++#define VPU_DI_INP_MMC_CTRL (0x2707) ++#define P_VPU_DI_INP_MMC_CTRL (volatile unsigned int *)((0x2707 << 2) + 0xff900000) ++#define VPU_DI_MTNRD_MMC_CTRL (0x2708) ++#define P_VPU_DI_MTNRD_MMC_CTRL (volatile unsigned int *)((0x2708 << 2) + 0xff900000) ++#define VPU_DI_CHAN2_MMC_CTRL (0x2709) ++#define P_VPU_DI_CHAN2_MMC_CTRL (volatile unsigned int *)((0x2709 << 2) + 0xff900000) ++#define VPU_DI_MTNWR_MMC_CTRL (0x270a) ++#define P_VPU_DI_MTNWR_MMC_CTRL (volatile unsigned int *)((0x270a << 2) + 0xff900000) ++#define VPU_DI_NRWR_MMC_CTRL (0x270b) ++#define P_VPU_DI_NRWR_MMC_CTRL (volatile unsigned int *)((0x270b << 2) + 0xff900000) ++#define VPU_DI_DIWR_MMC_CTRL (0x270c) ++#define P_VPU_DI_DIWR_MMC_CTRL (volatile unsigned int *)((0x270c << 2) + 0xff900000) ++#define VPU_VDIN0_MMC_CTRL (0x270d) ++#define P_VPU_VDIN0_MMC_CTRL (volatile unsigned int *)((0x270d << 2) + 0xff900000) ++#define VPU_VDIN1_MMC_CTRL (0x270e) ++#define P_VPU_VDIN1_MMC_CTRL (volatile unsigned int *)((0x270e << 2) + 0xff900000) ++#define VPU_BT656_MMC_CTRL (0x270f) ++#define P_VPU_BT656_MMC_CTRL (volatile unsigned int *)((0x270f << 2) + 0xff900000) ++#define VPU_TVD3D_MMC_CTRL (0x2710) ++#define P_VPU_TVD3D_MMC_CTRL (volatile unsigned int *)((0x2710 << 2) + 0xff900000) ++#define VPU_TVDVBI_MMC_CTRL (0x2711) ++#define P_VPU_TVDVBI_MMC_CTRL (volatile unsigned int *)((0x2711 << 2) + 0xff900000) ++//Read only ++//`define VPU_TVDVBI_VSLATCH_ADDR 8'h12 ++//Read only ++//`define VPU_TVDVBI_WRRSP_ADDR 8'h13 ++#define VPU_VDIN_PRE_ARB_CTRL (0x2714) ++#define P_VPU_VDIN_PRE_ARB_CTRL (volatile unsigned int *)((0x2714 << 2) + 0xff900000) ++#define VPU_VDISP_PRE_ARB_CTRL (0x2715) ++#define P_VPU_VDISP_PRE_ARB_CTRL (volatile unsigned int *)((0x2715 << 2) + 0xff900000) ++#define VPU_VPUARB2_PRE_ARB_CTRL (0x2716) ++#define P_VPU_VPUARB2_PRE_ARB_CTRL (volatile unsigned int *)((0x2716 << 2) + 0xff900000) ++#define VPU_OSD3_MMC_CTRL (0x2717) ++#define P_VPU_OSD3_MMC_CTRL (volatile unsigned int *)((0x2717 << 2) + 0xff900000) ++#define VPU_OSD4_MMC_CTRL (0x2718) ++#define P_VPU_OSD4_MMC_CTRL (volatile unsigned int *)((0x2718 << 2) + 0xff900000) ++#define VPU_VD3_MMC_CTRL (0x2719) ++#define P_VPU_VD3_MMC_CTRL (volatile unsigned int *)((0x2719 << 2) + 0xff900000) ++// [31:11] Reserved. ++// [10: 8] cntl_viu_vdin_sel_data. Select VIU to VDIN data path, must clear it first before changing the path selection: ++// 3'b000=Disable VIU to VDIN path; ++// 3'b001=Enable VIU of ENC_I domain to VDIN; ++// 3'b010=Enable VIU of ENC_P domain to VDIN; ++// 3'b100=Enable VIU of ENC_T domain to VDIN; ++// [ 6: 4] cntl_viu_vdin_sel_clk. Select which clock to VDIN path, must clear it first before changing the clock: ++// 3'b000=Disable VIU to VDIN clock; ++// 3'b001=Select encI clock to VDIN; ++// 3'b010=Select encP clock to VDIN; ++// 3'b100=Select encT clock to VDIN; ++// [ 3: 2] cntl_viu2_sel_venc. Select which one of the encI/P/T that VIU2 connects to: ++// 0=No connection, 1=ENCI, 2=ENCP, 3=ENCT. ++// [ 1: 0] cntl_viu1_sel_venc. Select which one of the encI/P/T that VIU1 connects to: ++// 0=No connection, 1=ENCI, 2=ENCP, 3=ENCT. ++#define VPU_VIU_VENC_MUX_CTRL (0x271a) ++#define P_VPU_VIU_VENC_MUX_CTRL (volatile unsigned int *)((0x271a << 2) + 0xff900000) ++// [15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2. ++// [11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1. ++// [ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format: ++// 0=output CrYCb(BRG); ++// 1=output YCbCr(RGB); ++// 2=output YCrCb(RBG); ++// 3=output CbCrY(GBR); ++// 4=output CbYCr(GRB); ++// 5=output CrCbY(BGR); ++// 6,7=Rsrv. ++// [ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI). ++// [ 3] inv_vsync. 1=Invert Vsync polarity. ++// [ 2] inv_hsync. 1=Invert Hsync polarity. ++// [ 1: 0] src_sel. 0=Disable output to HDMI; 1=Select VENC_I output to HDMI; 2=Select VENC_P output. ++#define VPU_HDMI_SETTING (0x271b) ++#define P_VPU_HDMI_SETTING (volatile unsigned int *)((0x271b << 2) + 0xff900000) ++#define ENCI_INFO_READ (0x271c) ++#define P_ENCI_INFO_READ (volatile unsigned int *)((0x271c << 2) + 0xff900000) ++#define ENCP_INFO_READ (0x271d) ++#define P_ENCP_INFO_READ (volatile unsigned int *)((0x271d << 2) + 0xff900000) ++#define ENCT_INFO_READ (0x271e) ++#define P_ENCT_INFO_READ (volatile unsigned int *)((0x271e << 2) + 0xff900000) ++#define ENCL_INFO_READ (0x271f) ++#define P_ENCL_INFO_READ (volatile unsigned int *)((0x271f << 2) + 0xff900000) ++// Bit 0 RW, viu_rst_n ++// Bit 1 RW, vdin_mmc_arb_rst_n ++// Bit 2 RW, vdisp_mmc_arb_rst_n ++// Bit 3 RW, vpuarb2_mmc_arb_rst_n ++#define VPU_SW_RESET (0x2720) ++#define P_VPU_SW_RESET (volatile unsigned int *)((0x2720 << 2) + 0xff900000) ++//Bit 30 d2d3_depr_req_sel, 0:vdisp_pre_arb, 1: vpuarb2_pre_arb ++//Bit 27:22 d2d3_depr_brst_num ++//Bit 21:16 d2d3_depr_id ++//Bit 14 d2d3_depw_req_sel, 0: vdin_pre_arb, 1: vdisp_pre_arb ++//Bit 11:6 d2d3_depw_brst_num ++//Bit 5:0 d2d3_depw_id ++#define VPU_D2D3_MMC_CTRL (0x2721) ++#define P_VPU_D2D3_MMC_CTRL (volatile unsigned int *)((0x2721 << 2) + 0xff900000) ++//Bit 30 mtn_contrd_req_pre, 0:disp1_arb, 1: vdin_pre_arb ++//Bit 27:22 mtn_contrd_brst_num ++//Bit 21:16 mtn_contrd_id ++//Bit 14 mtn_contwr_req_pre, 0: vdisp1_arb, 1: vdin_pre_arb ++//Bit 11:6 mtn_contwr_brst_num ++//Bit 5:0 mtn_contwr_id ++#define VPU_CONT_MMC_CTRL (0x2722) ++#define P_VPU_CONT_MMC_CTRL (volatile unsigned int *)((0x2722 << 2) + 0xff900000) ++// Bit 6 RW, gclk_mpeg_vpu_misc ++// Bit 5 RW, gclk_mpeg_venc_l_top ++// Bit 4 RW, gclk_mpeg_vencl_int ++// Bit 3 RW, gclk_mpeg_vencp_int ++// Bit 2 RW, gclk_mpeg_vi2_top ++// Bit 1 RW, gclk_mpeg_vi_top ++// Bit 0 RW, gclk_mpeg_venc_p_top ++#define VPU_CLK_GATE (0x2723) ++#define P_VPU_CLK_GATE (volatile unsigned int *)((0x2723 << 2) + 0xff900000) ++//Bit 12 RW, rdma_pre ++//Bit 11: 6 RW, rdma_num ++//Bit 5: 0 RW, rdma_id ++#define VPU_RDMA_MMC_CTRL (0x2724) ++#define P_VPU_RDMA_MMC_CTRL (volatile unsigned int *)((0x2724 << 2) + 0xff900000) ++#define VPU_MEM_PD_REG0 (0x2725) ++#define P_VPU_MEM_PD_REG0 (volatile unsigned int *)((0x2725 << 2) + 0xff900000) ++#define VPU_MEM_PD_REG1 (0x2726) ++#define P_VPU_MEM_PD_REG1 (volatile unsigned int *)((0x2726 << 2) + 0xff900000) ++// [ 31] hdmi_data_ovr_en: 1=Enable overriding data input to HDMI TX with hdmi_data_ovr[29:0]. 0=No override. Default 0. ++// [ 30] Reserved. Default 0 ++// [29: 0] hdmi_data_ovr. Default 0. ++#define VPU_HDMI_DATA_OVR (0x2727) ++#define P_VPU_HDMI_DATA_OVR (volatile unsigned int *)((0x2727 << 2) + 0xff900000) ++//Bit 15 RW, prot1_sel_osd4 ++//Bit 14 RW, prot1_sel_osd3 ++//Bit 13 RW, prot1_sel_osd2 ++//Bit 12 RW, prot1_sel_osd1 ++//Bit 11: 6 RW, prot1_brst_num ++//Bit 5: 0 RW, prot1_id ++#define VPU_PROT1_MMC_CTRL (0x2728) ++#define P_VPU_PROT1_MMC_CTRL (volatile unsigned int *)((0x2728 << 2) + 0xff900000) ++//Bit 14 RW, prot2_sel_vd3 ++//Bit 13 RW, prot2_sel_vd2 ++//Bit 12 RW, prot2_sel_vd1 ++//Bit 11: 6 RW, prot2_brst_num ++//Bit 5: 0 RW, prot2_id ++#define VPU_PROT2_MMC_CTRL (0x2729) ++#define P_VPU_PROT2_MMC_CTRL (volatile unsigned int *)((0x2729 << 2) + 0xff900000) ++//Bit 14 RW, prot3_sel_vd3 ++//Bit 13 RW, prot3_sel_vd2 ++//Bit 12 RW, prot3_sel_vd1 ++//Bit 11: 6 RW, prot3_brst_num ++//Bit 5: 0 RW, prot3_id ++#define VPU_PROT3_MMC_CTRL (0x272a) ++#define P_VPU_PROT3_MMC_CTRL (volatile unsigned int *)((0x272a << 2) + 0xff900000) ++//Bit 29:24 RW, s3_brst_num ++//Bit 21:16 RW, s2_brst_num ++//Bit 13: 8 RW, s1_brst_num ++//Bit 5: 0 RW, s0_brst_num ++#define VPU_ARB4_V1_MMC_CTRL (0x272b) ++#define P_VPU_ARB4_V1_MMC_CTRL (volatile unsigned int *)((0x272b << 2) + 0xff900000) ++//Bit 29:24 RW, s3_brst_num ++//Bit 21:16 RW, s2_brst_num ++//Bit 13: 8 RW, s1_brst_num ++//Bit 5: 0 RW, s0_brst_num ++#define VPU_ARB4_V2_MMC_CTRL (0x272c) ++#define P_VPU_ARB4_V2_MMC_CTRL (volatile unsigned int *)((0x272c << 2) + 0xff900000) ++//Bit 27:22 RW, mcvecwr_num ++//Bit 21:16 RW, mcvecwr_id ++//Bit 11:6 RW, mcvecrd_num ++//Bit 5:0 RW, mcvecrd_id ++#define VPU_MCVEC_MMC_CTRL (0x272d) ++#define P_VPU_MCVEC_MMC_CTRL (volatile unsigned int *)((0x272d << 2) + 0xff900000) ++//Bit 27:22 RW, mcinfwr_num ++//Bit 21:16 RW, mcinfwr_id ++//Bit 11:6 RW, mcinfrd_num ++//Bit 5:0 RW, mcinfrd_id ++#define VPU_MCINF_MMC_CTRL (0x272e) ++#define P_VPU_MCINF_MMC_CTRL (volatile unsigned int *)((0x272e << 2) + 0xff900000) ++//Bit 31 reg_vpu_pwm_inv, 1: invert the pwm signal, active low ++//Bit 30:29 reg_vpu_pwm_src_sel, 00: encl, enct, encp ++//Bit 28:16 reg_vpu_pwm_v_end0 ++//Bit 12:0 reg_vpu_pwm_v_start0 ++#define VPU_VPU_PWM_V0 (0x2730) ++#define P_VPU_VPU_PWM_V0 (volatile unsigned int *)((0x2730 << 2) + 0xff900000) ++//Bit 28:16 reg_vpu_pwm_v_end1 ++//Bit 12:0 reg_vpu_pwm_v_start1 ++#define VPU_VPU_PWM_V1 (0x2731) ++#define P_VPU_VPU_PWM_V1 (volatile unsigned int *)((0x2731 << 2) + 0xff900000) ++//Bit 28:16 reg_vpu_pwm_v_end2 ++//Bit 12:0 reg_vpu_pwm_v_start2 ++#define VPU_VPU_PWM_V2 (0x2732) ++#define P_VPU_VPU_PWM_V2 (volatile unsigned int *)((0x2732 << 2) + 0xff900000) ++//Bit 28:16 reg_vpu_pwm_v_end3 ++//Bit 12:0 reg_vpu_pwm_v_start3 ++#define VPU_VPU_PWM_V3 (0x2733) ++#define P_VPU_VPU_PWM_V3 (volatile unsigned int *)((0x2733 << 2) + 0xff900000) ++//Bit 28:16 reg_vpu_pwm_h_end0 ++//Bit 12:0 reg_vpu_pwm_h_start0 ++#define VPU_VPU_PWM_H0 (0x2734) ++#define P_VPU_VPU_PWM_H0 (volatile unsigned int *)((0x2734 << 2) + 0xff900000) ++//Bit 28:16 reg_vpu_pwm_h_end1 ++//Bit 12:0 reg_vpu_pwm_h_start1 ++#define VPU_VPU_PWM_H1 (0x2735) ++#define P_VPU_VPU_PWM_H1 (volatile unsigned int *)((0x2735 << 2) + 0xff900000) ++//Bit 28:16 reg_vpu_pwm_h_end2 ++//Bit 12:0 reg_vpu_pwm_h_start2 ++#define VPU_VPU_PWM_H2 (0x2736) ++#define P_VPU_VPU_PWM_H2 (volatile unsigned int *)((0x2736 << 2) + 0xff900000) ++//Bit 28:16 reg_vpu_pwm_h_end3 ++//Bit 12:0 reg_vpu_pwm_h_start3 ++#define VPU_VPU_PWM_H3 (0x2737) ++#define P_VPU_VPU_PWM_H3 (volatile unsigned int *)((0x2737 << 2) + 0xff900000) ++//Bit 18 reg_vpu_3d_go_high_fld_pol: 0: go high at field 0, 1: go high at field 1 ++//Bit 17 reg_vpu_3d_sync_setting_vsync_latch ++//Bit 16 reg_vpu_3d_sync_enable ++//Bit 14:8 reg_vpu_3d_sync_v_end ++//Bit 6:0 reg_vpu_3d_sync_v_start ++#define VPU_VPU_3D_SYNC1 (0x2738) ++#define P_VPU_VPU_3D_SYNC1 (volatile unsigned int *)((0x2738 << 2) + 0xff900000) ++//Bit 28:16 reg_vpu_3d_sync_h_end ++//Bit 12:0 reg_vpu_3d_sync_h_start ++#define VPU_VPU_3D_SYNC2 (0x2739) ++#define P_VPU_VPU_3D_SYNC2 (volatile unsigned int *)((0x2739 << 2) + 0xff900000) ++//Bit 4 csi2_pre, 1: using vpu pre arbiter0, 0: using vpu pre arbiter2 ++//Bit 2:1 isp_in_sel, 01: select bt656, 10: select Mipi CSI2, otherwise select nothing ++//Bit 0, if true, force vencl clk enable, otherwise, it might auto turn off by mipi DSI ++#define VPU_MISC_CTRL (0x2740) ++#define P_VPU_MISC_CTRL (volatile unsigned int *)((0x2740 << 2) + 0xff900000) ++#define VPU_ISP_GCLK_CTRL0 (0x2741) ++#define P_VPU_ISP_GCLK_CTRL0 (volatile unsigned int *)((0x2741 << 2) + 0xff900000) ++#define VPU_ISP_GCLK_CTRL1 (0x2742) ++#define P_VPU_ISP_GCLK_CTRL1 (volatile unsigned int *)((0x2742 << 2) + 0xff900000) ++#define VPU_HDMI_FMT_CTRL (0x2743) ++#define P_VPU_HDMI_FMT_CTRL (volatile unsigned int *)((0x2743 << 2) + 0xff900000) ++#define VPU_VDIN_ASYNC_HOLD_CTRL (0x2744) ++#define P_VPU_VDIN_ASYNC_HOLD_CTRL (volatile unsigned int *)((0x2744 << 2) + 0xff900000) ++#define VPU_VDISP_ASYNC_HOLD_CTRL (0x2745) ++#define P_VPU_VDISP_ASYNC_HOLD_CTRL (volatile unsigned int *)((0x2745 << 2) + 0xff900000) ++#define VPU_VPUARB2_ASYNC_HOLD_CTRL (0x2746) ++#define P_VPU_VPUARB2_ASYNC_HOLD_CTRL (volatile unsigned int *)((0x2746 << 2) + 0xff900000) ++// arb0_rd_urg_ctrl_o <= vpp_off_urg_ctrl & vpu_arb_urg_ctrl[0] | ++// rdma_ddr_req_busy_sync_d1 & vpu_arb_urg_ctrl[1] ++// ; ++// ++// arb1_rd_urg_ctrl_o <= vpp_off_urg_ctrl & vpu_arb_urg_ctrl[2] | ++// rdma_ddr_req_busy_sync_d1 & vpu_arb_urg_ctrl[3] ++// ; ++// ++// arb2_rd_urg_ctrl_o <= vpp_off_urg_ctrl & vpu_arb_urg_ctrl[4] | ++// rdma_ddr_req_busy_sync_d1 & vpu_arb_urg_ctrl[5] ++// ; ++// ++// arb0_wr_urg_ctrl_o <= vdin0_lff_urg_ctrl_sync_d1 & vpu_arb_urg_ctrl[6] | ++// vdin1_lff_urg_ctrl_sync_d1 & vpu_arb_urg_ctrl[7] ++// ; ++// ++// arb1_wr_urg_ctrl_o <= vdin0_lff_urg_ctrl_sync_d1 & vpu_arb_urg_ctrl[8] | ++// vdin1_lff_urg_ctrl_sync_d1 & vpu_arb_urg_ctrl[9] ++// ++#define VPU_ARB_URG_CTRL (0x2747) ++#define P_VPU_ARB_URG_CTRL (volatile unsigned int *)((0x2747 << 2) + 0xff900000) ++#define VPU_SECURE_DUMMY (0x2748) ++#define P_VPU_SECURE_DUMMY (volatile unsigned int *)((0x2748 << 2) + 0xff900000) ++#define VPU_VENCL_DITH_EN (0x2749) ++#define P_VPU_VENCL_DITH_EN (volatile unsigned int *)((0x2749 << 2) + 0xff900000) ++// todo : ++#define VPU_422TO444_RST (0x274a) ++#define P_VPU_422TO444_RST (volatile unsigned int *)((0x274a << 2) + 0xff900000) ++// todo : ++#define VPU_422TO444_CTRL0 (0x274b) ++#define P_VPU_422TO444_CTRL0 (volatile unsigned int *)((0x274b << 2) + 0xff900000) ++// todo : ++#define VPU_422TO444_CTRL1 (0x274c) ++#define P_VPU_422TO444_CTRL1 (volatile unsigned int *)((0x274c << 2) + 0xff900000) ++// todo : ++// Picture Rotate (PROT) module 1 (for OSD) registers: ++#define VPU_PROT1_CLK_GATE (0x2750) ++#define P_VPU_PROT1_CLK_GATE (volatile unsigned int *)((0x2750 << 2) + 0xff900000) ++#define VPU_PROT1_GEN_CNTL (0x2751) ++#define P_VPU_PROT1_GEN_CNTL (volatile unsigned int *)((0x2751 << 2) + 0xff900000) ++#define VPU_PROT1_X_START_END (0x2752) ++#define P_VPU_PROT1_X_START_END (volatile unsigned int *)((0x2752 << 2) + 0xff900000) ++#define VPU_PROT1_Y_START_END (0x2753) ++#define P_VPU_PROT1_Y_START_END (volatile unsigned int *)((0x2753 << 2) + 0xff900000) ++#define VPU_PROT1_Y_LEN_STEP (0x2754) ++#define P_VPU_PROT1_Y_LEN_STEP (volatile unsigned int *)((0x2754 << 2) + 0xff900000) ++#define VPU_PROT1_RPT_LOOP (0x2755) ++#define P_VPU_PROT1_RPT_LOOP (volatile unsigned int *)((0x2755 << 2) + 0xff900000) ++#define VPU_PROT1_RPT_PAT (0x2756) ++#define P_VPU_PROT1_RPT_PAT (volatile unsigned int *)((0x2756 << 2) + 0xff900000) ++#define VPU_PROT1_DDR (0x2757) ++#define P_VPU_PROT1_DDR (volatile unsigned int *)((0x2757 << 2) + 0xff900000) ++#define VPU_PROT1_RBUF_ROOM (0x2758) ++#define P_VPU_PROT1_RBUF_ROOM (volatile unsigned int *)((0x2758 << 2) + 0xff900000) ++#define VPU_PROT1_STAT_0 (0x2759) ++#define P_VPU_PROT1_STAT_0 (volatile unsigned int *)((0x2759 << 2) + 0xff900000) ++#define VPU_PROT1_STAT_1 (0x275a) ++#define P_VPU_PROT1_STAT_1 (volatile unsigned int *)((0x275a << 2) + 0xff900000) ++#define VPU_PROT1_STAT_2 (0x275b) ++#define P_VPU_PROT1_STAT_2 (volatile unsigned int *)((0x275b << 2) + 0xff900000) ++#define VPU_PROT1_REQ_ONOFF (0x275c) ++#define P_VPU_PROT1_REQ_ONOFF (volatile unsigned int *)((0x275c << 2) + 0xff900000) ++// Picture Rotate (PROT) module 2 (for VD) registers: ++#define VPU_PROT2_CLK_GATE (0x2760) ++#define P_VPU_PROT2_CLK_GATE (volatile unsigned int *)((0x2760 << 2) + 0xff900000) ++#define VPU_PROT2_GEN_CNTL (0x2761) ++#define P_VPU_PROT2_GEN_CNTL (volatile unsigned int *)((0x2761 << 2) + 0xff900000) ++#define VPU_PROT2_X_START_END (0x2762) ++#define P_VPU_PROT2_X_START_END (volatile unsigned int *)((0x2762 << 2) + 0xff900000) ++#define VPU_PROT2_Y_START_END (0x2763) ++#define P_VPU_PROT2_Y_START_END (volatile unsigned int *)((0x2763 << 2) + 0xff900000) ++#define VPU_PROT2_Y_LEN_STEP (0x2764) ++#define P_VPU_PROT2_Y_LEN_STEP (volatile unsigned int *)((0x2764 << 2) + 0xff900000) ++#define VPU_PROT2_RPT_LOOP (0x2765) ++#define P_VPU_PROT2_RPT_LOOP (volatile unsigned int *)((0x2765 << 2) + 0xff900000) ++#define VPU_PROT2_RPT_PAT (0x2766) ++#define P_VPU_PROT2_RPT_PAT (volatile unsigned int *)((0x2766 << 2) + 0xff900000) ++#define VPU_PROT2_DDR (0x2767) ++#define P_VPU_PROT2_DDR (volatile unsigned int *)((0x2767 << 2) + 0xff900000) ++#define VPU_PROT2_RBUF_ROOM (0x2768) ++#define P_VPU_PROT2_RBUF_ROOM (volatile unsigned int *)((0x2768 << 2) + 0xff900000) ++#define VPU_PROT2_STAT_0 (0x2769) ++#define P_VPU_PROT2_STAT_0 (volatile unsigned int *)((0x2769 << 2) + 0xff900000) ++#define VPU_PROT2_STAT_1 (0x276a) ++#define P_VPU_PROT2_STAT_1 (volatile unsigned int *)((0x276a << 2) + 0xff900000) ++#define VPU_PROT2_STAT_2 (0x276b) ++#define P_VPU_PROT2_STAT_2 (volatile unsigned int *)((0x276b << 2) + 0xff900000) ++#define VPU_PROT2_REQ_ONOFF (0x276c) ++#define P_VPU_PROT2_REQ_ONOFF (volatile unsigned int *)((0x276c << 2) + 0xff900000) ++// Picture Rotate (PROT) module 3 (for VD) registers: ++#define VPU_PROT3_CLK_GATE (0x2770) ++#define P_VPU_PROT3_CLK_GATE (volatile unsigned int *)((0x2770 << 2) + 0xff900000) ++#define VPU_PROT3_GEN_CNTL (0x2771) ++#define P_VPU_PROT3_GEN_CNTL (volatile unsigned int *)((0x2771 << 2) + 0xff900000) ++#define VPU_PROT3_X_START_END (0x2772) ++#define P_VPU_PROT3_X_START_END (volatile unsigned int *)((0x2772 << 2) + 0xff900000) ++#define VPU_PROT3_Y_START_END (0x2773) ++#define P_VPU_PROT3_Y_START_END (volatile unsigned int *)((0x2773 << 2) + 0xff900000) ++#define VPU_PROT3_Y_LEN_STEP (0x2774) ++#define P_VPU_PROT3_Y_LEN_STEP (volatile unsigned int *)((0x2774 << 2) + 0xff900000) ++#define VPU_PROT3_RPT_LOOP (0x2775) ++#define P_VPU_PROT3_RPT_LOOP (volatile unsigned int *)((0x2775 << 2) + 0xff900000) ++#define VPU_PROT3_RPT_PAT (0x2776) ++#define P_VPU_PROT3_RPT_PAT (volatile unsigned int *)((0x2776 << 2) + 0xff900000) ++#define VPU_PROT3_DDR (0x2777) ++#define P_VPU_PROT3_DDR (volatile unsigned int *)((0x2777 << 2) + 0xff900000) ++#define VPU_PROT3_RBUF_ROOM (0x2778) ++#define P_VPU_PROT3_RBUF_ROOM (volatile unsigned int *)((0x2778 << 2) + 0xff900000) ++#define VPU_PROT3_STAT_0 (0x2779) ++#define P_VPU_PROT3_STAT_0 (volatile unsigned int *)((0x2779 << 2) + 0xff900000) ++#define VPU_PROT3_STAT_1 (0x277a) ++#define P_VPU_PROT3_STAT_1 (volatile unsigned int *)((0x277a << 2) + 0xff900000) ++#define VPU_PROT3_STAT_2 (0x277b) ++#define P_VPU_PROT3_STAT_2 (volatile unsigned int *)((0x277b << 2) + 0xff900000) ++#define VPU_PROT3_REQ_ONOFF (0x277c) ++#define P_VPU_PROT3_REQ_ONOFF (volatile unsigned int *)((0x277c << 2) + 0xff900000) ++//Bit 20 reg_viu2vdin_sw_reset: software reset ++//Bit 19:18 reg_viu2vdin_dn_ratio: down-scale ratio; 0: no scale; 1: 1/2; 2:1/4; 3: reserved ++//Bit 17:16 reg_viu2vdin_flt_mode: filter mode; 0: no filter; 1:[0 2 2 0]/4; 2:[1 1 1 1]/4; 3:[1 3 3 1]/8 ++//Bit 15:14 reversed ++//Bit 13:0 reg_viu2vdin_hsize: source horizontal size ++#define VPU_VIU2VDIN_HDN_CTRL (0x2780) ++#define P_VPU_VIU2VDIN_HDN_CTRL (volatile unsigned int *)((0x2780 << 2) + 0xff900000) ++#define VPU_VIU_ASYNC_MASK (0x2781) ++#define P_VPU_VIU_ASYNC_MASK (volatile unsigned int *)((0x2781 << 2) + 0xff900000) ++#define VDIN_MISC_CTRL (0x2782) ++#define P_VDIN_MISC_CTRL (volatile unsigned int *)((0x2782 << 2) + 0xff900000) ++// vpu arbtration : ++// the segment is 8'h90-8'hc8 ++// ++// Reading file: vpu_arb_axi_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++////===============================//// ++//// reg ++////===============================//// ++#define VPU_RDARB_MODE_L1C1 (0x2790) ++#define P_VPU_RDARB_MODE_L1C1 (volatile unsigned int *)((0x2790 << 2) + 0xff900000) ++//Bit 31:22, reserved ++//Bit 21:16, rdarb_sel uns, default = 0 , ++// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1 ++// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1 ++// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1 ++// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1 ++// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1 ++// rdarb_sel[5]==0 slave dc5 connect master port0 rdarb_sel[5]==1 slave dc5 connect master port1 ++//Bit 15:10, reserved ++//Bit 9:8, rdarb_arb_mode uns, default = 0 , ++// rdarb_arb_mode[0] master port0 arb way, ++// rdarb_arb_mode[1] master port1 arb way, ++//Bit 7:4, reserved ++//Bit 3:0, rdarb_gate_clk_ctrl uns, default = 0 , ++// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control ++// rdarb_gate_clk_ctrl[3:2] master port1 clk gate control ++#define VPU_RDARB_REQEN_SLV_L1C1 (0x2791) ++#define P_VPU_RDARB_REQEN_SLV_L1C1 (volatile unsigned int *)((0x2791 << 2) + 0xff900000) ++//Bit 31:12, reserved ++//Bit 11:0, rdarb_dc_req_en unsigned , default = 12'hfff ++// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable, ++// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable, ++// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable, ++// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable, ++// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable, ++// rdarb_dc_req_en[5]: the slv5 req to mst port0 enable, ++// rdarb_dc_req_en[6]: the slv0 req to mst port1 enable, ++// rdarb_dc_req_en[7]: the slv1 req to mst port1 enable, ++// rdarb_dc_req_en[8]: the slv2 req to mst port1 enable, ++// rdarb_dc_req_en[9]: the slv3 req to mst port1 enable, ++// rdarb_dc_req_en[10]: the slv4 req to mst port1 enable, ++// rdarb_dc_req_en[11]: the slv5 req to mst port1 enable, ++#define VPU_RDARB_WEIGH0_SLV_L1C1 (0x2792) ++#define P_VPU_RDARB_WEIGH0_SLV_L1C1 (volatile unsigned int *)((0x2792 << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:0, rddc_weigh_sxn unsigned , default = 0 ++// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number ++// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number ++// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number ++// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number ++// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number ++#define VPU_RDARB_WEIGH1_SLV_L1C1 (0x2793) ++#define P_VPU_RDARB_WEIGH1_SLV_L1C1 (volatile unsigned int *)((0x2793 << 2) + 0xff900000) ++//Bit 31:6, reserved ++//Bit 5:0, rddc_weigh_sxn unsigned , default = 0 ++// rddc_weigh_sxn[5*6+:6]: the slv5 req weigh number ++#define VPU_WRARB_MODE_L1C1 (0x2794) ++#define P_VPU_WRARB_MODE_L1C1 (volatile unsigned int *)((0x2794 << 2) + 0xff900000) ++//Bit 31:22, reserved ++//Bit 21:16, wrarb_sel uns, default = 0 , ++// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1 ++// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1 ++// wrarb_sel[2]==0 slave dc2 connect master port0 wrarb_sel[2]==1 slave dc2 connect master port1 ++// wrarb_sel[3]==0 slave dc3 connect master port0 wrarb_sel[3]==1 slave dc3 connect master port1 ++// wrarb_sel[4]==0 slave dc4 connect master port0 wrarb_sel[4]==1 slave dc4 connect master port1 ++// wrarb_sel[5]==0 slave dc5 connect master port0 wrarb_sel[5]==1 slave dc5 connect master port1 ++//Bit 15:10, reserved ++//Bit 9:8, wrarb_arb_mode uns, default = 0 , ++// wrarb_arb_mode[0] master port0 arb way, ++// wrarb_arb_mode[1] master port1 arb way, ++//Bit 7:4, reserved ++//Bit 3:0, wrarb_gate_clk_ctrl uns, default = 0 , ++// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control ++// wrarb_gate_clk_ctrl[3:2] master port1 clk gate control ++#define VPU_WRARB_REQEN_SLV_L1C1 (0x2795) ++#define P_VPU_WRARB_REQEN_SLV_L1C1 (volatile unsigned int *)((0x2795 << 2) + 0xff900000) ++//Bit 31:12, reserved ++//Bit 11:0, wrarb_dc_req_en unsigned , default = 0 ++// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable, ++// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable, ++// wrarb_dc_req_en[2]: the slv2 req to mst port0 enable, ++// wrarb_dc_req_en[3]: the slv3 req to mst port0 enable, ++// wrarb_dc_req_en[4]: the slv4 req to mst port0 enable, ++// wrarb_dc_req_en[5]: the slv5 req to mst port0 enable, ++// wrarb_dc_req_en[0]: the slv0 req to mst port1 enable, ++// wrarb_dc_req_en[1]: the slv1 req to mst port1 enable, ++// wrarb_dc_req_en[2]: the slv2 req to mst port1 enable, ++// wrarb_dc_req_en[3]: the slv3 req to mst port1 enable, ++// wrarb_dc_req_en[4]: the slv4 req to mst port1 enable, ++// wrarb_dc_req_en[5]: the slv5 req to mst port1 enable, ++#define VPU_WRARB_WEIGH0_SLV_L1C1 (0x2796) ++#define P_VPU_WRARB_WEIGH0_SLV_L1C1 (volatile unsigned int *)((0x2796 << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:0, wrdc_weigh_sxn unsigned , default = 0 ++// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number ++// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number ++// wrdc_weigh_sxn[2*6+:6]: the slv2 req weigh number ++// wrdc_weigh_sxn[3*6+:6]: the slv3 req weigh number ++// wrdc_weigh_sxn[4*6+:6]: the slv4 req weigh number ++#define VPU_WRARB_WEIGH1_SLV_L1C1 (0x2797) ++#define P_VPU_WRARB_WEIGH1_SLV_L1C1 (volatile unsigned int *)((0x2797 << 2) + 0xff900000) ++//Bit 31:6, reserved ++//Bit 5:0, wrdc_weigh_sxn unsigned , default = 0 ++// wrdc_weigh_sxn[5*6+:6]: the slv5 req weigh number ++#define VPU_RDWR_ARB_STATUS_L1C1 (0x2798) ++#define P_VPU_RDWR_ARB_STATUS_L1C1 (volatile unsigned int *)((0x2798 << 2) + 0xff900000) ++//Bit 31:4, reserved ++//Bit 3:2, wrarb_arb_busy unsigned , default = 0 ++//Bit 1:0, rdarb_arb_busy unsigned , default = 0 ++#define VPU_RDARB_MODE_L1C2 (0x2799) ++#define P_VPU_RDARB_MODE_L1C2 (volatile unsigned int *)((0x2799 << 2) + 0xff900000) ++//Bit 31:21, reserved ++//Bit 20:16, rdarb_sel uns, default = 0 , ++// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1 ++// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1 ++// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1 ++// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1 ++// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1 ++//Bit 15:10, reserved ++//Bit 9:8, rdarb_arb_mode uns, default = 0 , ++// rdarb_arb_mode[0] master port0 arb way, ++// rdarb_arb_mode[1] master port1 arb way, ++//Bit 7:4, reserved ++//Bit 3:0, rdarb_gate_clk_ctrl uns, default = 0 , ++// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control ++// rdarb_gate_clk_ctrl[3:2] master port0 clk gate control ++#define VPU_RDARB_REQEN_SLV_L1C2 (0x279a) ++#define P_VPU_RDARB_REQEN_SLV_L1C2 (volatile unsigned int *)((0x279a << 2) + 0xff900000) ++//Bit 31:10, reserved ++//Bit 9:0, rdarb_dc_req_en unsigned , default = 0 ++// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable, ++// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable, ++// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable, ++// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable, ++// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable, ++// rdarb_dc_req_en[5]: the slv0 req to mst port1 enable, ++// rdarb_dc_req_en[6]: the slv1 req to mst port1 enable, ++// rdarb_dc_req_en[7]: the slv2 req to mst port1 enable, ++// rdarb_dc_req_en[8]: the slv3 req to mst port1 enable, ++// rdarb_dc_req_en[9]: the slv4 req to mst port1 enable, ++#define VPU_RDARB_WEIGH0_SLV_L1C2 (0x279b) ++#define P_VPU_RDARB_WEIGH0_SLV_L1C2 (volatile unsigned int *)((0x279b << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:0, rddc_weigh_sxn unsigned , default = 0 ++// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number ++// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number ++// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number ++// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number ++// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number ++#define VPU_RDWR_ARB_STATUS_L1C2 (0x279c) ++#define P_VPU_RDWR_ARB_STATUS_L1C2 (volatile unsigned int *)((0x279c << 2) + 0xff900000) ++//Bit 31:3, reserved ++//Bit 2, wrarb_arb_busy unsigned , default = 0 ++//Bit 1:0, rdarb_arb_busy unsigned , default = 0 ++#define VPU_RDARB_MODE_L2C1 (0x279d) ++#define P_VPU_RDARB_MODE_L2C1 (volatile unsigned int *)((0x279d << 2) + 0xff900000) ++//Bit 31:28, reserved ++//Bit 27:16, rdarb_sel uns, default = 0 , ++// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1 ++// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1 ++// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1 ++// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1 ++// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1 ++// rdarb_sel[5]==0 slave dc5 connect master port0 rdarb_sel[5]==1 slave dc5 connect master port1 ++//Bit 15:11, reserved ++//Bit 10:8, rdarb_arb_mode uns, default = 0 , ++// rdarb_arb_mode[0] master port0 arb way, ++// rdarb_arb_mode[1] master port1 arb way, ++//Bit 7:6, reserved ++//Bit 5:0, rdarb_gate_clk_ctrl uns, default = 0 , ++// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control ++// rdarb_gate_clk_ctrl[3:2] master port1 clk gate control ++// rdarb_gate_clk_ctrl[5:4] master port2 clk gate control ++#define VPU_RDARB_REQEN_SLV_L2C1 (0x279e) ++#define P_VPU_RDARB_REQEN_SLV_L2C1 (volatile unsigned int *)((0x279e << 2) + 0xff900000) ++//Bit 31:18, reserved ++//Bit 17:0, rdarb_dc_req_en unsigned , default = 0 ++// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable, ++// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable, ++// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable, ++// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable, ++// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable, ++// rdarb_dc_req_en[5]: the slv5 req to mst port0 enable, ++// rdarb_dc_req_en[0]: the slv0 req to mst port1 enable, ++// rdarb_dc_req_en[1]: the slv1 req to mst port1 enable, ++// rdarb_dc_req_en[2]: the slv2 req to mst port1 enable, ++// rdarb_dc_req_en[3]: the slv3 req to mst port1 enable, ++// rdarb_dc_req_en[4]: the slv4 req to mst port1 enable, ++// rdarb_dc_req_en[5]: the slv5 req to mst port1 enable, ++#define VPU_RDARB_WEIGH0_SLV_L2C1 (0x279f) ++#define P_VPU_RDARB_WEIGH0_SLV_L2C1 (volatile unsigned int *)((0x279f << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:0, rddc_weigh_sxn unsigned , default = 0 ++// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number ++// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number ++// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number ++// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number ++// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number ++#define VPU_RDARB_WEIGH1_SLV_L2C1 (0x27a0) ++#define P_VPU_RDARB_WEIGH1_SLV_L2C1 (volatile unsigned int *)((0x27a0 << 2) + 0xff900000) ++//Bit 31:6, reserved ++//Bit 5:0, rddc_weigh_sxn unsigned , default = 0 ++// rddc_weigh_sxn[5*6+:6]: the slv5 req weigh number ++#define VPU_RDWR_ARB_STATUS_L2C1 (0x27a1) ++#define P_VPU_RDWR_ARB_STATUS_L2C1 (volatile unsigned int *)((0x27a1 << 2) + 0xff900000) ++//Bit 31:4, reserved ++//Bit 3:2, wrarb_arb_busy unsigned , default = 0 ++//Bit 1:0, rdarb_arb_busy unsigned , default = 0 ++#define VPU_WRARB_MODE_L2C1 (0x27a2) ++#define P_VPU_WRARB_MODE_L2C1 (volatile unsigned int *)((0x27a2 << 2) + 0xff900000) ++//Bit 31:20, reserved ++//Bit 19:16, wrarb_sel uns, default = 0 , ++// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1 ++// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1 ++// wrarb_sel[2]==0 slave dc2 connect master port0 wrarb_sel[2]==1 slave dc2 connect master port1 ++// wrarb_sel[3]==0 slave dc3 connect master port0 wrarb_sel[3]==1 slave dc3 connect master port1 ++//Bit 15:10, reserved ++//Bit 9:8, wrarb_arb_mode uns, default = 0 , ++// wrarb_arb_mode[0] master port0 arb way, ++// wrarb_arb_mode[1] master port1 arb way, ++//Bit 7:4, reserved ++//Bit 3:0, wrarb_gate_clk_ctrl uns, default = 0 , ++// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control ++// wrarb_gate_clk_ctrl[3:2] master port0 clk gate control ++#define VPU_WRARB_REQEN_SLV_L2C1 (0x27a3) ++#define P_VPU_WRARB_REQEN_SLV_L2C1 (volatile unsigned int *)((0x27a3 << 2) + 0xff900000) ++//Bit 31:8, reserved ++//Bit 7:0, wrarb_dc_req_en unsigned , default = 0 ++// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable, ++// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable, ++// wrarb_dc_req_en[2]: the slv2 req to mst port0 enable, ++// wrarb_dc_req_en[3]: the slv3 req to mst port0 enable, ++// wrarb_dc_req_en[0]: the slv0 req to mst port1 enable, ++// wrarb_dc_req_en[1]: the slv1 req to mst port1 enable, ++// wrarb_dc_req_en[2]: the slv2 req to mst port1 enable, ++// wrarb_dc_req_en[3]: the slv3 req to mst port1 enable, ++#define VPU_WRARB_WEIGH0_SLV_L2C1 (0x27a4) ++#define P_VPU_WRARB_WEIGH0_SLV_L2C1 (volatile unsigned int *)((0x27a4 << 2) + 0xff900000) ++//Bit 31:24, reserved ++//Bit 23:0, wrdc_weigh_sxn unsigned , default = 0 ++// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number ++// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number ++// wrdc_weigh_sxn[2*6+:6]: the slv2 req weigh number ++// wrdc_weigh_sxn[3*6+:6]: the slv3 req weigh number ++#define VPU_ASYNC_RD_MODE0 (0x27a5) ++#define P_VPU_ASYNC_RD_MODE0 (volatile unsigned int *)((0x27a5 << 2) + 0xff900000) ++//Bit 31:19, reserved ++//Bit 18, req_en unsigned , default = 0 async enable ++//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control ++//Bit 15:12, auto_arugt_weight unsigned , default = 4 ++//Bit 11, reserved ++//Bit 10:9, arugt_sel unsigned , default = 0 ++// 00 : use auto fifo arugt generate the output arugt. ++// 01 : use the register bit control ++// 00 : use the input arguent ++//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit ++//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold ++//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold ++#define VPU_ASYNC_RD_MODE1 (0x27a6) ++#define P_VPU_ASYNC_RD_MODE1 (volatile unsigned int *)((0x27a6 << 2) + 0xff900000) ++//Bit 31:19, reserved ++//Bit 18, req_en unsigned , default = 0 async enable ++//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control ++//Bit 15:12, auto_arugt_weight unsigned , default = 4 ++//Bit 11, reserved ++//Bit 10:9, arugt_sel unsigned , default = 0 ++// 00 : use auto fifo arugt generate the output arugt. ++// 01 : use the register bit control ++// 00 : use the input arguent ++//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit ++//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold ++//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold ++#define VPU_ASYNC_RD_MODE2 (0x27a7) ++#define P_VPU_ASYNC_RD_MODE2 (volatile unsigned int *)((0x27a7 << 2) + 0xff900000) ++//Bit 31:19, reserved ++//Bit 18, req_en unsigned , default = 0 async enable ++//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control ++//Bit 15:12, auto_arugt_weight unsigned , default = 4 ++//Bit 11, reserved ++//Bit 10:9, arugt_sel unsigned , default = 0 ++// 00 : use auto fifo arugt generate the output arugt. ++// 01 : use the register bit control ++// 00 : use the input arguent ++//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit ++//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold ++//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold ++#define VPU_ASYNC_RD_MODE3 (0x27a8) ++#define P_VPU_ASYNC_RD_MODE3 (volatile unsigned int *)((0x27a8 << 2) + 0xff900000) ++//Bit 31:19, reserved ++//Bit 18, req_en unsigned , default = 0 async enable ++//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control ++//Bit 15:12, auto_arugt_weight unsigned , default = 4 ++//Bit 11, reserved ++//Bit 10:9, arugt_sel unsigned , default = 0 ++// 00 : use auto fifo arugt generate the output arugt. ++// 01 : use the register bit control ++// 00 : use the input arguent ++//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit ++//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold ++//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold ++#define VPU_ASYNC_RD_MODE4 (0x27a9) ++#define P_VPU_ASYNC_RD_MODE4 (volatile unsigned int *)((0x27a9 << 2) + 0xff900000) ++//Bit 31:19, reserved ++//Bit 18, req_en unsigned , default = 0 async enable ++//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control ++//Bit 15:12, auto_arugt_weight unsigned , default = 4 ++//Bit 11, reserved ++//Bit 10:9, arugt_sel unsigned , default = 0 ++// 00 : use auto fifo arugt generate the output arugt. ++// 01 : use the register bit control ++// 00 : use the input arguent ++//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit ++//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold ++//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold ++#define VPU_ASYNC_WR_MODE0 (0x27aa) ++#define P_VPU_ASYNC_WR_MODE0 (volatile unsigned int *)((0x27aa << 2) + 0xff900000) ++//Bit 31:19, reserved ++//Bit 18, req_en unsigned , default = 0 async enable ++//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control ++//Bit 15:12, auto_arugt_weight unsigned , default = 4 ++//Bit 11, reserved ++//Bit 10:9, arugt_sel unsigned , default = 0 ++// 00 : use auto fifo arugt generate the output arugt. ++// 01 : use the register bit control ++// 00 : use the input arguent ++//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit ++//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold ++//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold ++#define VPU_ASYNC_WR_MODE1 (0x27ab) ++#define P_VPU_ASYNC_WR_MODE1 (volatile unsigned int *)((0x27ab << 2) + 0xff900000) ++//Bit 31:19, reserved ++//Bit 18, req_en unsigned , default = 0 async enable ++//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control ++//Bit 15:12, auto_arugt_weight unsigned , default = 4 ++//Bit 11, reserved ++//Bit 10:9, arugt_sel unsigned , default = 0 ++// 00 : use auto fifo arugt generate the output arugt. ++// 01 : use the register bit control ++// 00 : use the input arguent ++//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit ++//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold ++//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold ++#define VPU_ASYNC_WR_MODE2 (0x27ac) ++#define P_VPU_ASYNC_WR_MODE2 (volatile unsigned int *)((0x27ac << 2) + 0xff900000) ++//Bit 31:19, reserved ++//Bit 18, req_en unsigned , default = 0 async enable ++//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control ++//Bit 15:12, auto_arugt_weight unsigned , default = 4 ++//Bit 11, reserved ++//Bit 10:9, arugt_sel unsigned , default = 0 ++// 00 : use auto fifo arugt generate the output arugt. ++// 01 : use the register bit control ++// 00 : use the input arguent ++//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit ++//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold ++//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold ++#define VPU_ASYNC_STAT (0x27ad) ++#define P_VPU_ASYNC_STAT (volatile unsigned int *)((0x27ad << 2) + 0xff900000) ++//Bit 31:19, reserved ++//Bit 18, axiwr2_chan_idle unsigned , RO, axi write channel2 idle state ++//Bit 17, axiwr1_chan_idle unsigned , RO, axi write channel1 idle state ++//Bit 16, axiwr0_chan_idle unsigned , RO, axi write channel0 idle state ++//Bit 15:5, reserved ++//Bit 4, axird4_chan_idle unsigned , RO, axi read channel4 idle state ++//Bit 3, axird3_chan_idle unsigned , RO, axi read channel3 idle state ++//Bit 2, axird2_chan_idle unsigned , RO, axi read channel2 idle state ++//Bit 1, axird1_chan_idle unsigned , RO, axi read channel1 idle state ++//Bit 0, axird0_chan_idle unsigned , RO, axi read channel0 idle state ++#define VPU_WRARB_MODE_L1C2 (0x27ae) ++#define P_VPU_WRARB_MODE_L1C2 (volatile unsigned int *)((0x27ae << 2) + 0xff900000) ++//Bit 31:18, reserved ++//Bit 17:16, wrarb_sel uns, default = 0 , ++// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1 ++// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1 ++//Bit 15:9, reserved ++//Bit 8, wrarb_arb_mode uns, default = 0 , ++// wrarb_arb_mode[0] master port0 arb way, ++//Bit 7:2, reserved ++//Bit 1:0, wrarb_gate_clk_ctrl uns, default = 0 , ++// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control ++#define VPU_WRARB_REQEN_SLV_L1C2 (0x27af) ++#define P_VPU_WRARB_REQEN_SLV_L1C2 (volatile unsigned int *)((0x27af << 2) + 0xff900000) ++//Bit 31:2, reserved ++//Bit 1:0, wrarb_dc_req_en unsigned , default = 0 ++// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable, ++// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable, ++#define VPU_WRARB_WEIGH0_SLV_L1C2 (0x27b0) ++#define P_VPU_WRARB_WEIGH0_SLV_L1C2 (volatile unsigned int *)((0x27b0 << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:0, wrdc_weigh_sxn unsigned , default = 0 ++// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number ++// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number ++// wrdc_weigh_sxn[2*6+:6]: the slv1 req weigh number ++// wrdc_weigh_sxn[3*6+:6]: the slv1 req weigh number ++// wrdc_weigh_sxn[4*6+:6]: the slv1 req weigh number ++#define VPU_WRARB_WEIGH1_SLV_L1C2 (0x27b1) ++#define P_VPU_WRARB_WEIGH1_SLV_L1C2 (volatile unsigned int *)((0x27b1 << 2) + 0xff900000) ++//Bit 31:18, reserved ++//Bit 17:0, wrdc_weigh_sxn unsigned , default = 0 ++// wrdc_weigh_sxn[5*6+:6]: the slv0 req weigh number ++// wrdc_weigh_sxn[6*6+:6]: the slv1 req weigh number ++// wrdc_weigh_sxn[7*6+:6]: the slv1 req weigh number ++#define VPU_RDARB_WEIGH1_SLV_L1C2 (0x27b2) ++#define P_VPU_RDARB_WEIGH1_SLV_L1C2 (volatile unsigned int *)((0x27b2 << 2) + 0xff900000) ++//Bit 31:18, reserved ++//Bit 17:0, rddc_weigh_sxn unsigned , default = 0 ++// rddc_weigh_sxn[5*6+:6]: the slv0 req weigh number ++// rddc_weigh_sxn[6*6+:6]: the slv1 req weigh number ++// rddc_weigh_sxn[7*6+:6]: the slv2 req weigh number ++#define VPU_ARB_DBG_CTRL_L1C1 (0x27b3) ++#define P_VPU_ARB_DBG_CTRL_L1C1 (volatile unsigned int *)((0x27b3 << 2) + 0xff900000) ++#define VPU_ARB_DBG_STAT_L1C1 (0x27b4) ++#define P_VPU_ARB_DBG_STAT_L1C1 (volatile unsigned int *)((0x27b4 << 2) + 0xff900000) ++#define VPU_ARB_DBG_CTRL_L1C2 (0x27b5) ++#define P_VPU_ARB_DBG_CTRL_L1C2 (volatile unsigned int *)((0x27b5 << 2) + 0xff900000) ++#define VPU_ARB_DBG_STAT_L1C2 (0x27b6) ++#define P_VPU_ARB_DBG_STAT_L1C2 (volatile unsigned int *)((0x27b6 << 2) + 0xff900000) ++#define VPU_ARB_DBG_CTRL_L2C1 (0x27b7) ++#define P_VPU_ARB_DBG_CTRL_L2C1 (volatile unsigned int *)((0x27b7 << 2) + 0xff900000) ++#define VPU_ARB_DBG_STAT_L2C1 (0x27b8) ++#define P_VPU_ARB_DBG_STAT_L2C1 (volatile unsigned int *)((0x27b8 << 2) + 0xff900000) ++#define VPU_ARB_PATH_CTRL (0x27b9) ++#define P_VPU_ARB_PATH_CTRL (volatile unsigned int *)((0x27b9 << 2) + 0xff900000) ++#define VPU_ARB_PATH_MAP00 (0x27ba) ++#define P_VPU_ARB_PATH_MAP00 (volatile unsigned int *)((0x27ba << 2) + 0xff900000) ++#define VPU_ARB_PATH_MAP01 (0x27bb) ++#define P_VPU_ARB_PATH_MAP01 (volatile unsigned int *)((0x27bb << 2) + 0xff900000) ++#define VPU_ARB_PATH_MAP02 (0x27bc) ++#define P_VPU_ARB_PATH_MAP02 (volatile unsigned int *)((0x27bc << 2) + 0xff900000) ++#define VPU_ARB_PATH_MAP03 (0x27bd) ++#define P_VPU_ARB_PATH_MAP03 (volatile unsigned int *)((0x27bd << 2) + 0xff900000) ++#define VPU_ARB_PATH_MAP10 (0x27be) ++#define P_VPU_ARB_PATH_MAP10 (volatile unsigned int *)((0x27be << 2) + 0xff900000) ++#define VPU_ARB_PATH_MAP11 (0x27bf) ++#define P_VPU_ARB_PATH_MAP11 (volatile unsigned int *)((0x27bf << 2) + 0xff900000) ++#define VPU_ARB_PATH_MAP12 (0x27c0) ++#define P_VPU_ARB_PATH_MAP12 (volatile unsigned int *)((0x27c0 << 2) + 0xff900000) ++#define VPU_ARB_PATH_MAP13 (0x27c1) ++#define P_VPU_ARB_PATH_MAP13 (volatile unsigned int *)((0x27c1 << 2) + 0xff900000) ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: vpu_arb_axi_regs.h ++// ++// the segment is 8'he0-8'hef ++#define VPU_VENCL_DITH_CTRL (0x27e0) ++#define P_VPU_VENCL_DITH_CTRL (volatile unsigned int *)((0x27e0 << 2) + 0xff900000) ++#define VPU_VENCL_DITH_LUT_1 (0x27e1) ++#define P_VPU_VENCL_DITH_LUT_1 (volatile unsigned int *)((0x27e1 << 2) + 0xff900000) ++#define VPU_VENCL_DITH_LUT_2 (0x27e2) ++#define P_VPU_VENCL_DITH_LUT_2 (volatile unsigned int *)((0x27e2 << 2) + 0xff900000) ++#define VPU_VENCL_DITH_LUT_3 (0x27e3) ++#define P_VPU_VENCL_DITH_LUT_3 (volatile unsigned int *)((0x27e3 << 2) + 0xff900000) ++#define VPU_VENCL_DITH_LUT_4 (0x27e4) ++#define P_VPU_VENCL_DITH_LUT_4 (volatile unsigned int *)((0x27e4 << 2) + 0xff900000) ++#define VPU_VENCL_DITH_LUT_5 (0x27e5) ++#define P_VPU_VENCL_DITH_LUT_5 (volatile unsigned int *)((0x27e5 << 2) + 0xff900000) ++#define VPU_VENCL_DITH_LUT_6 (0x27e6) ++#define P_VPU_VENCL_DITH_LUT_6 (volatile unsigned int *)((0x27e6 << 2) + 0xff900000) ++#define VPU_VENCL_DITH_LUT_7 (0x27e7) ++#define P_VPU_VENCL_DITH_LUT_7 (volatile unsigned int *)((0x27e7 << 2) + 0xff900000) ++#define VPU_VENCL_DITH_LUT_8 (0x27e8) ++#define P_VPU_VENCL_DITH_LUT_8 (volatile unsigned int *)((0x27e8 << 2) + 0xff900000) ++#define VPU_VENCL_DITH_LUT_9 (0x27e9) ++#define P_VPU_VENCL_DITH_LUT_9 (volatile unsigned int *)((0x27e9 << 2) + 0xff900000) ++#define VPU_VENCL_DITH_LUT_10 (0x27ea) ++#define P_VPU_VENCL_DITH_LUT_10 (volatile unsigned int *)((0x27ea << 2) + 0xff900000) ++#define VPU_VENCL_DITH_LUT_11 (0x27eb) ++#define P_VPU_VENCL_DITH_LUT_11 (volatile unsigned int *)((0x27eb << 2) + 0xff900000) ++#define VPU_VENCL_DITH_LUT_12 (0x27ec) ++#define P_VPU_VENCL_DITH_LUT_12 (volatile unsigned int *)((0x27ec << 2) + 0xff900000) ++//new added 4x4 dither ++// the segment is 8'hf0 ++#define VPU_HDMI_DITH_01_04 (0x27f0) ++#define P_VPU_HDMI_DITH_01_04 (volatile unsigned int *)((0x27f0 << 2) + 0xff900000) ++#define VPU_HDMI_DITH_01_15 (0x27f1) ++#define P_VPU_HDMI_DITH_01_15 (volatile unsigned int *)((0x27f1 << 2) + 0xff900000) ++#define VPU_HDMI_DITH_01_26 (0x27f2) ++#define P_VPU_HDMI_DITH_01_26 (volatile unsigned int *)((0x27f2 << 2) + 0xff900000) ++#define VPU_HDMI_DITH_01_37 (0x27f3) ++#define P_VPU_HDMI_DITH_01_37 (volatile unsigned int *)((0x27f3 << 2) + 0xff900000) ++#define VPU_HDMI_DITH_10_04 (0x27f4) ++#define P_VPU_HDMI_DITH_10_04 (volatile unsigned int *)((0x27f4 << 2) + 0xff900000) ++#define VPU_HDMI_DITH_10_15 (0x27f5) ++#define P_VPU_HDMI_DITH_10_15 (volatile unsigned int *)((0x27f5 << 2) + 0xff900000) ++#define VPU_HDMI_DITH_10_26 (0x27f6) ++#define P_VPU_HDMI_DITH_10_26 (volatile unsigned int *)((0x27f6 << 2) + 0xff900000) ++#define VPU_HDMI_DITH_10_37 (0x27f7) ++#define P_VPU_HDMI_DITH_10_37 (volatile unsigned int *)((0x27f7 << 2) + 0xff900000) ++#define VPU_HDMI_DITH_11_04 (0x27f8) ++#define P_VPU_HDMI_DITH_11_04 (volatile unsigned int *)((0x27f8 << 2) + 0xff900000) ++#define VPU_HDMI_DITH_11_15 (0x27f9) ++#define P_VPU_HDMI_DITH_11_15 (volatile unsigned int *)((0x27f9 << 2) + 0xff900000) ++#define VPU_HDMI_DITH_11_26 (0x27fa) ++#define P_VPU_HDMI_DITH_11_26 (volatile unsigned int *)((0x27fa << 2) + 0xff900000) ++#define VPU_HDMI_DITH_11_37 (0x27fb) ++#define P_VPU_HDMI_DITH_11_37 (volatile unsigned int *)((0x27fb << 2) + 0xff900000) ++#define VPU_HDMI_DITH_CNTL (0x27fc) ++#define P_VPU_HDMI_DITH_CNTL (volatile unsigned int *)((0x27fc << 2) + 0xff900000) ++//======================================================================== ++// MIPI CSI2 Controller Adaptor (16'h2a00 - 16'h2aff) ++// ++//======================================================================== ++//`define CSI2_VCBUS_BASE 8'h2a ++//`include "csi2_regs.h" ++//====================================================================== ++// D2D3 registers ++//====================================================================== ++//`define D2D3_VCBUS_BASE 8'h2b ++// ++// Reading file: d2d3_regs.h ++// ++//=========================================================================== ++// D2D3 Registers 0x - 0x ++//=========================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: D2D3_VCBUS_BASE = 0x2b ++// ----------------------------------------------- ++//------------------------------------------------------------------------------ ++// D2D3 top-level registers ++//------------------------------------------------------------------------------ ++// Bit 31 RW, rd_lock_en, 1 to allow update some read-only registers based on filed ++// Bit 30 RW, sw_rst_nobuf, 1 to reset the whole d2d3 unit ++// Bit 29:28 RW, clk_auto_dis, [29] DBR clock disable ++// [28] DPG clock disable ++// Bit 27:16 RW, clk_ctrl, [27:26] gated clock control for register unit ++// [25:24] gated clock control for DBR unit ++// [23:22] gated clock control for LBDG unit ++// [21:20] gated clock control for MBDG unit ++// [19:18] gated clock control for CBDG unit ++// [17:16] gated clock control for DBLD unit and SCD81 unit ++// Bit 15:12 Reserved ++// Bit 11 RW, lo_chroma_sign, 0: negate the u/v component of DBR left channel video output, 1: bypass ++// Bit 10 RW, ro_chroma_sign, 0: negate the u/v component of DBR right channel video output, 1: bypass ++// Bit 9 RW, vi0_chroma_sign, 0: negate the u/v component of DPG video input, 1: bypass ++// Bit 8 RW, vi1_chroma_sign, 0: negate the u/v component of DBR video input, 1: bypass ++// Bit 7:5 Reserved ++// Bit 4 RW, lg_en, Enable the LBDG unit and LBDG clock ++// Bit 3 RW, mg_en, Enable the MBDG unit and MBDG clock ++// Bit 2 RW, cg_en, Enable the CBDG unit and CBDG clock ++// Bit 1 RW, dbr_en, Enable the DBR unit and DBR clock ++// Bit 0 RW, dpg_en, Enable the DPG unit and clock except sub-unit CBDG, MBDG and LBDG ++#define D2D3_GLB_CTRL (0x2b00) ++#define P_D2D3_GLB_CTRL (volatile unsigned int *)((0x2b00 << 2) + 0xff900000) ++// Indicate the input picture size in DPG unit ++// Bit 31:16 RW, szx_vi_m1, The horizontal size minus 1 ++// Bit 15:0 RW, szy_vi_m1, The vertical size minus 1 ++#define D2D3_DPG_INPIC_SIZE (0x2b01) ++#define P_D2D3_DPG_INPIC_SIZE (volatile unsigned int *)((0x2b01 << 2) + 0xff900000) ++// Indicate the output picture size in DBR unit ++// Bit 31:16 RW, szx_vo_m1, The horizontal size minus 1 ++// Bit 15:0 RW, szy_vo_m1, The vertical size minus 1 ++#define D2D3_DBR_OUTPIC_SIZE (0x2b02) ++#define P_D2D3_DBR_OUTPIC_SIZE (volatile unsigned int *)((0x2b02 << 2) + 0xff900000) ++// Indicate the rectangular window to generate the "depth" in DPG unit ++// Bit 31:16 RW, dg_win_x_start, Horizontal start position, count from 0 ++// Bit 15:0 RW, dg_win_x_end, Horizontal end position, count from 0 ++#define D2D3_DGEN_WIN_HOR (0x2b03) ++#define P_D2D3_DGEN_WIN_HOR (volatile unsigned int *)((0x2b03 << 2) + 0xff900000) ++// Indicate the rectangular window to generate the "depth" in DPG unit ++// Bit 31:16 RW, dg_win_y_start, Vertical start position, count from 0 ++// Bit 15:0 RW, dg_win_y_end, Vertical end position, count from 0 ++#define D2D3_DGEN_WIN_VER (0x2b04) ++#define P_D2D3_DGEN_WIN_VER (volatile unsigned int *)((0x2b04 << 2) + 0xff900000) ++//------------------------------------------------------------------------------ ++// CBDG SCU18 SCD81 SCD81_PRE registers ++// cg: color based depth generate module ++// scu18: scale up module ++// scd81: scale down module ++// scd81_pre: scd81 pre-scale-down module ++//------------------------------------------------------------------------------ ++// Indicate parameters of pre-scale-down unit ++// Bit 31:16 RW, scd81_hphs_step, horizontal step ++// Bit 15:0 RW, scd81_hphs_ini, horizontal initial phase ++#define D2D3_PRE_SCD_H (0x2b05) ++#define P_D2D3_PRE_SCD_H (volatile unsigned int *)((0x2b05 << 2) + 0xff900000) ++// Bit 31:16 RW, scu18_iniph, initial phase in SCU18, ++// [23:16] indicate the horizontal phase offset from the first data of every line ++// [31:24] indicate the vertical phase offset from the first line of every frame ++// Bit 15:12 Reserved ++// Bit 11 RW, scd81_predrop_en, 1 to enable scd81 pre-scale-down function ++// Bit 10:9 RW, cg_csc_sel, Color Space Conversion(CSC) matrix mode selector in CBDG ++// 0: BT.601 (16-235/240) ++// 1: BT.709 (16-235/240) ++// 2: BT.601 (0-255) ++// 3: BT.709 (0-255) ++// Bit 8 RW, scu18_rep_en, 1 to double each line of the SCU18 output ++// Bit 7:4 RW, scu18_factor, up-scale factor in SCU18 on DBR input depth data ++// [7:6] for vertical, 0->1:1, 1->1:2, 2->1:4, 3->1:8 ++// [5:4] for horizontal, 0->1:1, 1->1:2, 2->1:4, 3->1:8 ++// Bit 3:0 RW, scd81_factor, down-scale factor in SCD81 on DPG source video ++// [3:2] for vertical, 0->1:1, 1->2:1, 2->4:1, 3->8:1 ++// [1:0] for horizontal, 0->1:1, 1->2:1, 2->4:1, 3->8:1 ++#define D2D3_SCALER_CTRL (0x2b06) ++#define P_D2D3_SCALER_CTRL (volatile unsigned int *)((0x2b06 << 2) + 0xff900000) ++// Bit 31:24 RW, cg_rpg_dth, the down |r-g| threshold for sky detect ++// Bit 23:16 RW, cg_rpg_uth, the up |r-g| threshold for sky detect ++// Bit 15:8 RW, cg_lum_dth, the down Y threshold for sky detect ++// Bit 7:0 RW, cg_lum_uth, the up Y threshold for sky detect ++#define D2D3_CG_THRESHOLD_1 (0x2b07) ++#define P_D2D3_CG_THRESHOLD_1 (volatile unsigned int *)((0x2b07 << 2) + 0xff900000) ++// Bit 31:24 RW, cg_rpb_dth, the down |r-b| threshold for sky detect ++// Bit 23:16 RW, cg_rpb_uth, the up |r-b| threshold for sky detect ++// Bit 15:8 RW, cg_bpg_dth, the down |b-g| threshold for sky detect ++// Bit 7:0 RW, cg_bpg_uth, the up |b-g| threshold for sky detect ++#define D2D3_CG_THRESHOLD_2 (0x2b08) ++#define P_D2D3_CG_THRESHOLD_2 (volatile unsigned int *)((0x2b08 << 2) + 0xff900000) ++// Bit 31:24 RW, cg_vp_rel_k, parameter to calculate vanish point reliability ++// Bit 23:16 RW, cg_vp_y_thr, the max limitation to calculate the vanish-point's vertical position ++// Bit 15:8 RW, cg_meet_dval, signed depth value in the sky-bitmap ++// Bit 7:0 RW, cg_unmt_dval, signed depth value not in the sky-bitmap ++#define D2D3_CG_PARAM_1 (0x2b09) ++#define P_D2D3_CG_PARAM_1 (volatile unsigned int *)((0x2b09 << 2) + 0xff900000) ++// Bit 31:16 RW, cg_vpos_thr, Maximal vertical limitation for sky-bit map when cg_vpos_en=1 and cg_vpos_adpt_en=0 ++// Bit 15:8 Reserved ++// Bit 7 RW, cg_vpos_en, 1 to enable the max vertical limitation for sky-bitmap ++// Bit 6 RW, cg_vpos_adpt_en, 1 to enable the adaptive max vertical limitation for sky-bitmap. ++// It is only valid when cg_vpos_en=1. ++// The max vertical limitation is the previous field's vanish-point (vertical position) if cg_vpos_adpt_en=1. ++// Bit 5:4 RW, cg_lpf_bypass, bypass of low pass filter ++// [5]:Vertical bypass, 1: bypass the vertical LPF on the CBDG depth ++// [4]:Horizontal bypass, 1: bypass the horizontal LPF on the CBDG depth ++// Bit 3:0 RW, cg_vp_rel_s, parameter to calculate vanish point reliability ++#define D2D3_CG_PARAM_2 (0x2b0a) ++#define P_D2D3_CG_PARAM_2 (volatile unsigned int *)((0x2b0a << 2) + 0xff900000) ++// Indicate parameters of pre-scale-down unit ++// Bit 31:16 RW, scd81_vphs_step, vertical step ++// Bit 15:0 RW, scd81_vphs_ini, vertical initial phase ++#define D2D3_PRE_SCD_V (0x2b0b) ++#define P_D2D3_PRE_SCD_V (volatile unsigned int *)((0x2b0b << 2) + 0xff900000) ++//------------------------------------------------------------------------------ ++// D2P registers ++// d2p: depth to parallax transform module ++//------------------------------------------------------------------------------ ++// Bit 31:24 RW, d2p_brdwid, Horizontal boundary width for parallax, the parallax value would be forced to 0 in boundary, ++// the d2p_brdwid should not 0 when D2P_WRAP is enabled ++// Bit 23:22 Reserved ++// Bit 21:20 RW, d2p_lomode, line output mode, ++// 0:whole line is left or right; 1:whole line is left or right; ++// 2:left/right pixel interleaved; 3:left/right half-line interleaved ++// Bit 19 RW, d2p_neg, 1 to exchange the left and right parallax value ++// Bit 18 Reserved ++// Bit 17 RW, d2p_wrap_en, 1 to enable D2P_WRAP unit ++// Bit 16 RW, d2p_lar, Indicate the first output for left or right, 0: left; 1: right ++// Bit 15 RW, d2p_lr_switch, enable left/right flag filed switch automatically, only valid when parallax output mode is field interleaved ++// Bit 14 RW, d2p_1dtolr, enable to generate 2 parallax data (left and right) from one depth ++// Bit 13:12 RW, d2p_out_mode, Parallax output mode ++// 0:left/right pixel interleaved; 1:line or half line interleaved; 2:field interleaved ++// Bit 11:8 RW, d2p_smode, Shift mode, ++// 0: no shift; 1: enable left shift; ++// 2: enable right shift; 3: both left and right shift are enabled ++// Bit 7:0 RW, d2p_offset, depth offset, signed, ++#define D2D3_D2P_PARAM_1 (0x2b0c) ++#define P_D2D3_D2P_PARAM_1 (volatile unsigned int *)((0x2b0c << 2) + 0xff900000) ++// Bit 31:24 RW, d2p_pg0, positive parallax gain when Parallax value < pt ++// Bit 23:16 RW, d2p_pg1, positive parallax gain when Parallax value >= pt ++// Bit 15:8 RW, d2p_pt, unsigned value used to separate the positive parallax range ++// Bit 7:0 RW, d2p_plimit, The limitation for positive parallax ++#define D2D3_D2P_PARAM_2 (0x2b0d) ++#define P_D2D3_D2P_PARAM_2 (volatile unsigned int *)((0x2b0d << 2) + 0xff900000) ++// Bit 31:24 RW, d2p_ng0, negative parallax gain when Parallax value > -nt ++// Bit 23:16 RW, d2p_ng1, negative parallax gain when Parallax value <= -nt ++// Bit 15:8 RW, d2p_nt, unsigned value used to separate the negative parallax range ++// Bit 7:0 RW, d2p_nlimit, The limitation for negative parallax ++#define D2D3_D2P_PARAM_3 (0x2b0e) ++#define P_D2D3_D2P_PARAM_3 (volatile unsigned int *)((0x2b0e << 2) + 0xff900000) ++// Indicate step parameters of SCU18 unit ++// Bit 31:17 Reserved ++// Bit 16 RW, scu18_step_en, step set enable in SCU18 ++// Bit 15:8 RW, scu18_hphs_step, horizontal step in SCU18 ++// Bit 7:0 RW, scu18_vphs_step, vertical step in SCU18 ++#define D2D3_SCU18_STEP (0x2b0f) ++#define P_D2D3_SCU18_STEP (volatile unsigned int *)((0x2b0f << 2) + 0xff900000) ++//------------------------------------------------------------------------------ ++// LBDG and DBLD registers ++// lg: luma based depth generate module ++// db: depth blending module ++//------------------------------------------------------------------------------ ++// Bit 31:22 Reserved ++// Bit 21:20 RW, db_lpf_bpcoeff, [21]:Vertical factor of low pass filter, ++// 1: Vfactor = 0/0/64/0/0, 0: Vfactor = {db_vf_a,db_vf_b,db_vf_c,db_vf_b,db_vf_a}, see D2D3_CTRL_15 ++// [20]:Horizontal factor of low pass filter, ++// 1: Hfactor = 0/0/64/0/0, 0: Hfactor = {db_hf_a,db_hf_b,db_hf_c,db_hf_b,db_hf_a}, see D2D3_CTRL_14 ++// Bit 19:18 RW, lg_lpf_bpcoeff, [19]:Vertical factor of low pass filter, 1: Vfactor = 0/64/0, 0: Vfactor = 20/24/20 ++// [18]:Horizontal factor of low pass filter, 1: Hfactor = 0/64/0, 0: Hfactor = 16/32/16 ++// Bit 17:16 RW, cg_lpf_bpcoeff, [17]:Vertical factor of low pass filter, 1: Vfactor = 0/64/0, 0: Vfactor = 20/24/20 ++// [16]:Horizontal factor of low pass filter, 1: Hfactor = 0/64/0, 0: Hfactor = 16/32/16 ++// Bit 15:10 Reserved ++// Bit 9:8 RW, db_lpf_bypass, [9] 1 to bypass the vertical LPF on the DBLD depth ++// [8] 1 to bypass the horizontal LPF on the DBLD depth ++// Bit 7:6 RW, lg_lpf_bypass, [7] 1 to bypass the vertical LPF on the LBDG depth ++// [6] 1 to bypass the horizontal LPF on the LBDG depth ++// Bit 5:0 RW, lg_kc, gain of CPL(v-u+256-y) to calculate the depth in LBDG ++#define D2D3_DPF_LPF_CTRL (0x2b10) ++#define P_D2D3_DPF_LPF_CTRL (volatile unsigned int *)((0x2b10 << 2) + 0xff900000) ++//------------------------------------------------------------------------------ ++// DBLD registers ++// db: depth blending module ++//------------------------------------------------------------------------------ ++// Bit 31:24 RW, db_g2_cg, gain of CBDG depth in DBLD ++// Bit 23:16 RW, db_o2_cg, offset of CBDG depth in DBLD ++// Bit 15:8 RW, db_g1_cg, gain of CBDG depth using for summary in DBLD ++// Bit 7:0 RW, db_o1_cg, offset of CBDG depth using for summary in DBLD ++#define D2D3_DBLD_CG_PARAM (0x2b11) ++#define P_D2D3_DBLD_CG_PARAM (volatile unsigned int *)((0x2b11 << 2) + 0xff900000) ++// Bit 31:24 RW, db_g2_mg, gain of MBDG depth in DBLD ++// Bit 23:16 RW, db_o2_mg, offset of MBDG depth in DBLD ++// Bit 15:8 RW, db_g1_mg, gain of MBDG depth using for summary in DBLD ++// Bit 7:0 RW, db_o1_mg, offset of MBDG depth using for summary in DBLD ++#define D2D3_DBLD_MG_PARAM (0x2b12) ++#define P_D2D3_DBLD_MG_PARAM (volatile unsigned int *)((0x2b12 << 2) + 0xff900000) ++// Bit 31:24 RW, db_g2_lg, gain of LBDG depth in DBLD ++// Bit 23:16 RW, db_o2_lg, offset of LBDG depth in DBLD ++// Bit 15:8 RW, db_g1_lg, gain of LBDG depth using for summary in DBLD ++// Bit 7:0 RW, db_o1_lg, offset of LBDG depth using for summary in DBLD ++#define D2D3_DBLD_LG_PARAM (0x2b13) ++#define P_D2D3_DBLD_LG_PARAM (volatile unsigned int *)((0x2b13 << 2) + 0xff900000) ++// Bit 31:24 RW, db_factor, unsigned gain of difference in DBLD ++// Bit 23:16 RW, db_hf_a, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign ++// Bit 15:8 RW, db_hf_b, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign ++// Bit 7:0 RW, db_hf_c, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign ++#define D2D3_DBLD_LPF_HCOEFF (0x2b14) ++#define P_D2D3_DBLD_LPF_HCOEFF (volatile unsigned int *)((0x2b14 << 2) + 0xff900000) ++// Bit 31:24 RW, db_owin_fill, signed depth value outside the rectangular window defined in register DGEN_WIN_HOR and DGEN_WIN_VER ++// Bit 23:16 RW, db_vf_a, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign ++// Bit 15:8 RW, db_vf_b, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign ++// Bit 7:0 RW, db_vf_c, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign ++#define D2D3_DBLD_LPF_VCOEFF (0x2b15) ++#define P_D2D3_DBLD_LPF_VCOEFF (volatile unsigned int *)((0x2b15 << 2) + 0xff900000) ++// Bit 31:28 RW, hist_depth_idx, ++// Bit 27:26 Reserved ++// Bit 25 RW, mbdg_dep_neg, 1 to negate the output data of MBDG ++// Bit 24 RW, lbdg_dep_neg, 1 to negate the output data of LBDG ++// Bit 23:16 RW, db_f1_ctrl, MUX1 selector ++// [1:0] MUX1 path1 selector, 0:summary, 1:CBDG, 2:MBDG, 3:LBDG ++// [3:2] MUX1 path2 selector, 0:summary, 1:CBDG, 2:MBDG, 3:LBDG ++// [6:4] MUX1 out1 selector, 1:CBDG, 2:MBDG, 3:LBDG, 4:summary, 5:MUX1out0, others:summary ++// [7] MUX1OUT0 selector, 0:MIN (MUX1PATH1,MUX1Path2), 1:MAX (MUX1Path1,MUX1Path2) ++// Bit 15:8 RW, db_f2_ctrl, MUX2 selector ++// [1:0] MUX2 path1 selector, 0:MUX1OUT1, 1:CBDG, 2:MBDG, 3:LBDG ++// [3:2] MUX2 path2 selector, 0:MUX1OUT1, 1:CBDG, 2:MBDG, 3:LBDG ++// [6:4] MUX2 out1 selector, 1:CBDG, 2:MBDG, 3:LBDG, 4:summary, 5:MUX2out0, others:MUX2out0 ++// [7] MUX2OUT0 selector, 0:MIN (MUX2PATH1,MUX2Path2), 1:MAX (MUX2Path1,MUX2Path2) ++// Bit 7:4 RW, db_fifo0_sel, the source input of FIFO0 ++// 0: no use; 1:from CBDG; 2:from MBDG; 3:from LBDG others:reserved ++// Bit 3:0 RW, db_fifo1_sel, the source input of FIFO1 ++// 0: no use; 1:from CBDG; 2:from MBDG; 3:from LBDG 4: from FIFO0; others:reserved ++#define D2D3_DBLD_PATH_CTRL (0x2b16) ++#define P_D2D3_DBLD_PATH_CTRL (volatile unsigned int *)((0x2b16 << 2) + 0xff900000) ++// Indicate the input picture size in SCU18 unit ++// Bit 31:16 RW, szy_scui, The vertical size ++// Bit 15:0 RW, szx_scui, The horizontal size ++#define D2D3_SCU18_INPIC_SIZE (0x2b17) ++#define P_D2D3_SCU18_INPIC_SIZE (volatile unsigned int *)((0x2b17 << 2) + 0xff900000) ++//------------------------------------------------------------------------------ ++// MBDG registers ++// mg: model based depth generate module ++//------------------------------------------------------------------------------ ++// Bit 31:18 Reserved ++// Bit 17 RW, mg_vp_en, mdg vanish point enable, not used ++// Bit 16 RW, mg_sw_en, 1 to use the software forced parameter for the point D, U and C in MBDG ++// Bit 15:8 RW, mg_owin_fill, Signed depth value outside the rectangular window defined in register DGEN_WIN_HOR and DGEN_WIN_VER ++// Bit 7 RW, mg_iir_en, 1 to enable the 2-taps IIR filter in MBDG ++// Bit 6:0 RW, mg_iir, [6]: 1 to bypass the 2-taps IIR filter in MBDG ++// [5:0]:Unsigned coefficient of the 2-taps IIR filter in MBDG ++// [6]:bypass, 1:bypass, 0:not bypass ++#define D2D3_MBDG_CTRL (0x2b18) ++#define P_D2D3_MBDG_CTRL (volatile unsigned int *)((0x2b18 << 2) + 0xff900000) ++// Bit 31:28 RW, mg_dtl_pxl_left, Max pixel number (1<< mg_dtl_pxl_left) using in the left window for activities in MBDG ++// Bit 27:24 RW, mg_dtl_pxl_right, Max pixel number (1<< mg_dtl_pxl_right) using in the right window for activities in MBDG ++// Bit 23:16 RW, mg_cx_sw, Depth of point C in horizontal curve in MBDG for software forced ++// Bit 15:8 RW, mg_ux_sw, Depth of point U in horizontal curve in MBDG for software forced ++// Bit 7:0 RW, mg_dx_sw, Depth of point D in horizontal curve in MBDG for software forced ++#define D2D3_MBDG_PARAM_0 (0x2b19) ++#define P_D2D3_MBDG_PARAM_0 (volatile unsigned int *)((0x2b19 << 2) + 0xff900000) ++// Bit 31:28 RW, mg_dtl_pxl_up, Max pixel number (1<< mg_dtl_pxl_up) using in the top window for activities in MBDG ++// Bit 27:24 RW, mg_dtl_pxl_dn, Max pixel number (1<< mg_dtl_pxl_dn) using in the bottom window for activities in MBDG ++// Bit 23:16 RW, mg_cy_sw, Depth of point C in vertical curve in MBDG for software forced ++// Bit 15:8 RW, mg_uy_sw, Depth of point U in vertical curve in MBDG for software forced ++// Bit 7:0 RW, mg_dy_sw, Depth of point D in vertical curve in MBDG for software forced ++#define D2D3_MBDG_PARAM_1 (0x2b1a) ++#define P_D2D3_MBDG_PARAM_1 (volatile unsigned int *)((0x2b1a << 2) + 0xff900000) ++// Bit 31:24 RW, mg_dtl_ln_up, Line number in the top window for activities in MBDG ++// Bit 23:16 RW, mg_dtl_ln_dn, Line number in the bottom window for activities in MBDG ++// Bit 15:8 RW, mg_dtl_ln_left, Column number in the left window for activities in MBDG ++// Bit 7:0 RW, mg_dtl_ln_right,Column number in the right window for activities in MBDG ++#define D2D3_MBDG_PARAM_2 (0x2b1b) ++#define P_D2D3_MBDG_PARAM_2 (volatile unsigned int *)((0x2b1b << 2) + 0xff900000) ++// Bit 31:24 RW, mg_y_max, Software initial depth of point D and U in vertical curve ++// Bit 23:16 RW, mg_y_min, Software initial depth of point C in vertical curve ++// Bit 15:8 RW, mg_x_max, Software initial depth of point D and U in horizontal curve ++// Bit 7:0 RW, mg_x_min, Software initial depth of point C in horizontal curve ++#define D2D3_MBDG_PARAM_3 (0x2b1c) ++#define P_D2D3_MBDG_PARAM_3 (volatile unsigned int *)((0x2b1c << 2) + 0xff900000) ++// Bit 31:27 Reserved ++// Bit 26 RW, mg_y_adapt_en, 1 to enable the adaptive mode for point U/D in vertical curve calculation ++// Bit 25 RW, mg_xmm_adapt_en, 1 to enable the XMM adaptive mode for point U/D in horizontal curve calculation ++// Bit 24 RW, mg_x_adapt_en, 1 to enable the adaptive mode for point U/D in horizontal curve calculation ++// Bit 23:20 RW, mg_ytrans_1, Shifter controller in vertical curve calculation, if mg_xtrans_1<0, right shift abs(mg_xtrans_1) bits, others left shift abs(mg_xtrans_1) bits ++// Bit 19:16 RW, mg_xtrans_1, Shifter controller in horizontal curve calculation, if mg_xtrans_1<0, right shift abs(mg_xtrans_1) bits, others left shift abs(mg_xtrans_1) bits ++// Bit 15:8 RW, mg_yk_0, The based activities value of the ACT for vertical curve ++// Bit 7:0 RW, mg_xk_0, The based activities value of the ACT for horizontal curve ++#define D2D3_MBDG_PARAM_4 (0x2b1d) ++#define P_D2D3_MBDG_PARAM_4 (volatile unsigned int *)((0x2b1d << 2) + 0xff900000) ++// Bit 31:24 RW, mg_ysu3, Quantized value 3 in vertical curve adaptive calculation ++// Bit 23:16 RW, mg_ysu2, Quantized value 2 in vertical curve adaptive calculation ++// Bit 15:8 RW, mg_ysu1, Quantized value 1 in vertical curve adaptive calculation ++// Bit 7:0 RW, mg_ysu0, Quantized value 0 in vertical curve adaptive calculation ++#define D2D3_MBDG_PARAM_5 (0x2b1e) ++#define P_D2D3_MBDG_PARAM_5 (volatile unsigned int *)((0x2b1e << 2) + 0xff900000) ++// Bit 31:24 RW, mg_xsu3, Quantized value 3 in horizontal curve adaptive calculation ++// Bit 23:16 RW, mg_xsu2, Quantized value 2 in horizontal curve adaptive calculation ++// Bit 15:8 RW, mg_xsu1, Quantized value 1 in horizontal curve adaptive calculation ++// Bit 7:0 RW, mg_xsu0, Quantized value 0 in horizontal curve adaptive calculation ++#define D2D3_MBDG_PARAM_6 (0x2b1f) ++#define P_D2D3_MBDG_PARAM_6 (volatile unsigned int *)((0x2b1f << 2) + 0xff900000) ++// Bit 31:16 Reserved ++// Bit 15:8 RW, mg_xsu4, Quantized value 4 in horizontal curve adaptive calculation ++// Bit 7:0 RW, mg_ysu4, Quantized value 4 in vertical curve adaptive calculation ++#define D2D3_MBDG_PARAM_7 (0x2b20) ++#define P_D2D3_MBDG_PARAM_7 (volatile unsigned int *)((0x2b20 << 2) + 0xff900000) ++// Bit 31:28 RW, dbg_hscnt_sel see DBG_STATUS_2 ++// Bit 27:25 Reserved ++// Bit 24 RW, dbg_dbr_en, 1 to enable debug mode in DBR ++// Bit 23:16 RW, dbg_force_data, Forced data in debug mode ++// Bit 15:12 RW, dbg_bld_ctrl, debug controller for DBLD ++// [12]:enable; [13]: 0 for passive mode, 0 for handshake mode ++// [15:14]: 0 for constant mode, 1 for step1 mode ++// Bit 11:8 RW, dbg_mg_ctrl, debug controller for MBDG ++// [8]:enable; [9]: 0 for passive mode, 0 for handshake mode ++// [11:10]: 0 for constant mode, 1 for step1 mode ++// Bit 7:4 RW, dbg_cg_ctrl, debug controller for CBDG ++// [4]:enable; [5]: 0 for passive mode, 0 for handshake mode ++// [7:6]: 0 for constant mode, 1 for step1 mode ++// Bit 3:0 RW, dbg_lg_ctrl, debug controller for LBDG ++// [0]:enable; [1]: 0 for passive mode, 0 for handshake mode ++// [3:2]: 0 for constant mode, 1 for step1 mode ++#define D2D3_DBG_CTRL (0x2b23) ++#define P_D2D3_DBG_CTRL (volatile unsigned int *)((0x2b23 << 2) + 0xff900000) ++//------------------------------------------------------------------------------ ++// DWMIF registers ++//------------------------------------------------------------------------------ ++// Bit 31:18 Reserved ++// Bit 17 RW, dw_x_rev 0: Normal write data from left to right in horizontal ++// 1: Reversed write data from left to right in horizontal ++// Bit 16 RW, dw_y_rev 0: Normal write data from top to bottom in horizontal ++// 1: Reversed write data from bottom to top in horizontal ++// Bit 15 RW, dw_done_clr 1 to clear register depw_done (DWMIF_STATUS) ++// Bit 14 RW, dw_little_endian, 0: data is ordered in big-endian, 1: little endian ++// Bit 13:12 RW, dw_pic_struct, 0:read every line, 1:reserved, 2:read even line, 3:read odd line ++// Bit 11 RW, dw_urgent, urgent index ++// Bit 10 RW, dw_clr_wrrsp, 1:clear the write fifo counter ++// Bit 9 RW, dw_canvas_wr, canvas write initialization again ++// Bit 8 RW, dw_req_en, 1 to enable write request ++// Bit 7:0 RW, dw_canvas_index,Canvas index for the MSB of memory address for memory write ++#define D2D3_DWMIF_CTRL (0x2b24) ++#define P_D2D3_DWMIF_CTRL (volatile unsigned int *)((0x2b24 << 2) + 0xff900000) ++// Bit 31 Reserved ++// Bit 30:16 RW, dw_end_x, Horizontal end position for memory write, count by BYTE ++// Bit 15 Reserved ++// Bit 14:0 RW, dw_start_x, Horizontal start position for memory write, count by BYTE ++#define D2D3_DWMIF_HPOS (0x2b25) ++#define P_D2D3_DWMIF_HPOS (volatile unsigned int *)((0x2b25 << 2) + 0xff900000) ++// Bit 31:29 Reserved ++// Bit 28:16 RW, dw_end_y, Vertical end position for memory write, count by BYTE ++// Bit 15:13 Reserved ++// Bit 12:0 RW, dw_start_y, Vertical start position for memory write, count by BYTE ++#define D2D3_DWMIF_VPOS (0x2b26) ++#define P_D2D3_DWMIF_VPOS (volatile unsigned int *)((0x2b26 << 2) + 0xff900000) ++// Bit 31:28 Reserved ++// Bit 27:16 RW, dw_vsizem1, Vertical size for memory write, equal the size minus 1 ++// Bit 15:12 Reserved ++// Bit 11:0 RW, dw_hsizem1, Horizontal size for memory write, equal the size minus 1 ++#define D2D3_DWMIF_SIZE (0x2b27) ++#define P_D2D3_DWMIF_SIZE (volatile unsigned int *)((0x2b27 << 2) + 0xff900000) ++//------------------------------------------------------------------------------ ++// DRMIF registers ++//------------------------------------------------------------------------------ ++// Bit 31:18 Reserved ++// Bit 17 RW, dr_y_rev, 0: Normal Read data from top to bottom in horizontal ++// 1: Reversed read data from bottom to top in horizontal ++// Bit 16 RW, dr_x_rev, 0: Normal Read data from left to right in horizontal ++// 1: Reversed read data from right to left in horizontal ++// Bit 15 RW, dr_clr_fifo_error, 1 to clear the overflow flag of the sticky FIFO ++// Bit 14 RW, dr_little_endian, 0: data is ordered in big-endian; 1: little-endian ++// Bit 13:12 RW, dr_pic_struct, 0: progressive; 1: Reserved; ++// 2: interlaced, even line; 3: interlaced, odd line ++// Bit 11 RW, dr_urgent, urgent index, no use in this system ++// Bit 10:9 RW, dr_burst_size, Burst read length for each request; 0=24,1=32,2=48,3=64 ++// Bit 8 RW, dr_req_en, 1 to enable read request ++// Bit 7:0 RW, dr_canvas_index, Canvas index for the MSB of memory address for memory read ++#define D2D3_DRMIF_CTRL (0x2b28) ++#define P_D2D3_DRMIF_CTRL (volatile unsigned int *)((0x2b28 << 2) + 0xff900000) ++// Bit 31 Reserved ++// Bit 30:16 RW, dr_end_x, Horizontal end position for memory read, count by BYTE ++// Bit 15 Reserved ++// Bit 14:0 RW, dr_start_x, Horizontal start position for memory read, count by BYTE ++#define D2D3_DRMIF_HPOS (0x2b29) ++#define P_D2D3_DRMIF_HPOS (volatile unsigned int *)((0x2b29 << 2) + 0xff900000) ++// Bit 31:29 Reserved ++// Bit 28:16 RW, dr_end_y, Vertical end position for memory read, count by BYTE ++// Bit 15:13 Reserved ++// Bit 12:0 RW, dr_start_y, Vertical start position for memory read, count by BYTE ++#define D2D3_DRMIF_VPOS (0x2b2a) ++#define P_D2D3_DRMIF_VPOS (volatile unsigned int *)((0x2b2a << 2) + 0xff900000) ++//------------------------------------------------------------------------------ ++// PDR registers ++// ddd: parallax based render ++//------------------------------------------------------------------------------ ++// Bit 31:8 Reserved ++// Bit 7 RW, ddd_brdlpf_en, 1 to enable the smooth filter on the depth around the boundary ++// Bit 6 RW, ddd_extn_black, 1 to enable the function to fill black colour when interpolated pixels is outside the picture in DBR ++// Bit 5 RW, ddd_wrap_en, Reserved ++// Bit 4 RW, ddd_hhalf, 1 to indicate the left/right line length is a half of original line. ++// Bit 3:2 RW, ddd_out_mode, Reserved ++// Bit 1:0 RW, ddd_lomode, wrap & pbr interleave mode: ++// 2'b0x: whole line is left or right; ++// 2'b10: d2p_lar=1(D2P_PARAM_1), rlrlrlrl inteleave in one line, ++// d2p_lar=0(D2P_PARAM_1), lrlrlrlr inteleave in one line, ++// 2'b11: d2p_lar=1(D2P_PARAM_1), rrrrr?lllll, half line is right, another half is left, ++// d2p_lar=0(D2P_PARAM_1), lllll?rrrrr, half line is left, another half is right, ++#define D2D3_DBR_DDD_CTRL (0x2b2c) ++#define P_D2D3_DBR_DDD_CTRL (volatile unsigned int *)((0x2b2c << 2) + 0xff900000) ++// Bit 31:0 RW, ddd_dbg_ctrl, no use ++#define D2D3_DBR_DDD_DBG (0x2b2d) ++#define P_D2D3_DBR_DDD_DBG (volatile unsigned int *)((0x2b2d << 2) + 0xff900000) ++//------------------------------------------------------------------------------ ++// LRDMX registers ++//------------------------------------------------------------------------------ ++// Bit 31:9 Reserved ++// Bit 8 RW, lr_merge, 1: all the left/right input go to the left channel output ++// Bit 7:6 RW, lrd_ff0_sel, FF0 source selector ++// 0:from left input; 1:from right input; 2:from FF0; 3:no used ++// Bit 5:4 RW, lrd_ff1_sel, FF1 source selector ++// 0:from left input; 1:from right input; 2:from FF0; 3:no used ++// Bit 3:2 RW, lrd_lout_sel, left channel DEMUX ++// 00: ff0 01:ff1 10: left input 11:right input ++// Bit 1:0 RW, lrd_rout_sel, right channel DEMUX ++// 00: ff1 01:ff0 10: left input 11:right input ++#define D2D3_DBR_LRDMX_CTRL (0x2b2f) ++#define P_D2D3_DBR_LRDMX_CTRL (volatile unsigned int *)((0x2b2f << 2) + 0xff900000) ++//------------------------------------------------------------------------------ ++// Read Only registers ++//------------------------------------------------------------------------------ ++// Bit 31:24 RO, ro_cg_vprel, vanish point's reliability in CBDG ++// Bit 23:12 RO, ro_cg_vpx, vanish point's X-Axis in CBDG ++// Bit 11:0 RO, ro_cg_vpy, vanish point's Y-Axis in CBDG ++#define D2D3_CBDG_STATUS_1 (0x2b30) ++#define P_D2D3_CBDG_STATUS_1 (volatile unsigned int *)((0x2b30 << 2) + 0xff900000) ++// Bit 31:24 RO, ro_mg_cx[7:0], X-Axis of point C in horizontal curve in MBDG ++// Bit 23:16 RO, ro_mg_ux, Depth value of point U in horizontal curve in MBDG ++// Bit 15:8 RO, ro_mg_dx, Depth value of point D in horizontal curve in MBDG ++// Bit 7:0 RO, ro_mg_minx, Depth value of point C in horizontal curve in MBDG ++#define D2D3_MBDG_STATUS_1 (0x2b31) ++#define P_D2D3_MBDG_STATUS_1 (volatile unsigned int *)((0x2b31 << 2) + 0xff900000) ++// Bit 31:24 RO, ro_mg_cy[7:0], X-Axis of point C in vertical curve in MBDG ++// Bit 23:16 RO, ro_mg_uy, Depth value of point U in vertical curve in MBDG ++// Bit 15:8 RO, ro_mg_dy, Depth value of point D in vertical curve in MBDG ++// Bit 7:0 RO, ro_mg_miny, Depth value of point C in vertical curve in MBDG ++#define D2D3_MBDG_STATUS_2 (0x2b32) ++#define P_D2D3_MBDG_STATUS_2 (volatile unsigned int *)((0x2b32 << 2) + 0xff900000) ++// Bit 31 RO, ro_wrap_status, 1 indicate the D2P_WRAP is busy to perform the initialization ++// Bit 30:8 Reserved ++// Bit 7:4 RO, ro_mg_cy[11:8], X-Axis of point C in vertical curve in MBDG ++// Bit 3:0 RO, ro_mg_cx[11:8], X-Axis of point C in horizontal curve in MBDG ++#define D2D3_MBDG_STATUS_3 (0x2b33) ++#define P_D2D3_MBDG_STATUS_3 (volatile unsigned int *)((0x2b33 << 2) + 0xff900000) ++// Bit 31:21 Reserved ++// Bit 20:0 RO, ro_mg_sum_u, ACT(top): activities of the top part ++#define D2D3_MBDG_STATUS_4 (0x2b34) ++#define P_D2D3_MBDG_STATUS_4 (volatile unsigned int *)((0x2b34 << 2) + 0xff900000) ++// Bit 31:21 Reserved ++// Bit 20:0 RO, ro_mg_sum_d, ACT(bottom): activities of the bottom part ++#define D2D3_MBDG_STATUS_5 (0x2b35) ++#define P_D2D3_MBDG_STATUS_5 (volatile unsigned int *)((0x2b35 << 2) + 0xff900000) ++// Bit 31:21 Reserved ++// Bit 20:0 RO, ro_mg_sum_l, ACT(left): activities of the left part ++#define D2D3_MBDG_STATUS_6 (0x2b36) ++#define P_D2D3_MBDG_STATUS_6 (volatile unsigned int *)((0x2b36 << 2) + 0xff900000) ++// Bit 31:21 Reserved ++// Bit 20:0 RO, ro_mg_sum_r, ACT(right): activities of the right part ++#define D2D3_MBDG_STATUS_7 (0x2b37) ++#define P_D2D3_MBDG_STATUS_7 (volatile unsigned int *)((0x2b37 << 2) + 0xff900000) ++// Bit 31:0 dbg_handshake_ro0, handshake signal for debug, internal srdy and rrdy ++#define D2D3_DBG_STATUS_1 (0x2b38) ++#define P_D2D3_DBG_STATUS_1 (volatile unsigned int *)((0x2b38 << 2) + 0xff900000) ++// Bit 31:0 dbg_hscnt, dbg_hscnt_sel == 4'h0, output lg hscnt ++// dbg_hscnt_sel == 4'h1, output cg hscnt ++// dbg_hscnt_sel == 4'h2, output mg hscnt ++// dbg_hscnt_sel == 4'h3, output bld hscnt ++// dbg_hscnt_sel == other value, output 32'h0 ++#define D2D3_DBG_STATUS_2 (0x2b39) ++#define P_D2D3_DBG_STATUS_2 (volatile unsigned int *)((0x2b39 << 2) + 0xff900000) ++// Bit 31:0 RO, drmif_status, drmif module internal status ++#define D2D3_DRMIF_STATUS (0x2b3a) ++#define P_D2D3_DRMIF_STATUS (volatile unsigned int *)((0x2b3a << 2) + 0xff900000) ++// Bit 31:2 RO, Reserved ++// Bit 1:0 RO, d2d3_status0, [1]: depw_done, one field depth write to ddr has done ++// [0]: dwmif_pending_ddr_wrrsp, 1 to indicate write response from ddr ++#define D2D3_DWMIF_STATUS (0x2b3b) ++#define P_D2D3_DWMIF_STATUS (volatile unsigned int *)((0x2b3b << 2) + 0xff900000) ++// Bit 31:24 Reserved ++// Bit 23:0 RO, ro_meet_sum, register sumxy_sum_dbg in CBDG ++#define D2D3_CBDG_STATUS_2 (0x2b3c) ++#define P_D2D3_CBDG_STATUS_2 (volatile unsigned int *)((0x2b3c << 2) + 0xff900000) ++// Bit 31:20 Reserved ++// Bit 19:0 RO, ro_hist_depth, ++#define D2D3_DBLD_STATUS (0x2b3d) ++#define P_D2D3_DBLD_STATUS (volatile unsigned int *)((0x2b3d << 2) + 0xff900000) ++// Bit 31:0 Reserved ++#define D2D3_RESEV_STATUS1 (0x2b3e) ++#define P_D2D3_RESEV_STATUS1 (volatile unsigned int *)((0x2b3e << 2) + 0xff900000) ++// Bit 31:0 Reserved ++#define D2D3_RESEV_STATUS2 (0x2b3f) ++#define P_D2D3_RESEV_STATUS2 (volatile unsigned int *)((0x2b3f << 2) + 0xff900000) ++// ++// Closing file: d2d3_regs.h ++// ++//======================================================================== ++// MIPI DSI Host Controller (16'h2c00 - 16'h2cff) ++// ++//======================================================================== ++//`define DSI_VCBUS_BASE 8'h2c ++//`include "dsi_regs.h" ++//======================================================================== ++// ISP register (16'h2d00 - 16'h2dff) ++//======================================================================== ++//`define ISP_VCBUS_BASE 8'h2d ++//`include "isp_reg.h" ++//`define MADB_VCBUS_BASE 8'h2d ++// ++// Reading file: dnr_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++// ----------------------------------------------- ++// CBUS_BASE: MADB_VCBUS_BASE = 0x2d ++// ----------------------------------------------- ++#define DNR_CTRL (0x2d00) ++#define P_DNR_CTRL (volatile unsigned int *)((0x2d00 << 2) + 0xff900000) ++//Bit 31:17, reserved ++//Bit 16, reg_dnr_en , dnr enable . unsigned , default = 1 ++//Bit 15, reg_dnr_db_vdbstep , vdb step, 0: 4, 1: 8 . unsigned , default = 1 ++//Bit 14, reg_dnr_db_vdbprten , vdb protectoin enable . unsigned , default = 1 ++//Bit 13, reg_dnr_gbs_difen , enable dif (between LR and LL/RR) condition for gbs stat.. unsigned , default = 0 ++//Bit 12, reg_dnr_luma_en , enable ycbcr2luma module . unsigned , default = 1 ++//Bit 11:10, reg_dnr_db_mod , deblocking mode, 0: disable, 1: horizontal deblocking, 2: vertical deblocking, 3: horizontal & vertical deblocking. unsigned , default = 3 ++//Bit 9, reg_dnr_db_chrmen , enable chroma deblocking . unsigned , default = 1 ++//Bit 8, reg_dnr_hvdif_mod , 0: calc. difs by original Y, 1: by new luma. unsigned , default = 1 ++//Bit 7, reserved ++//Bit 6: 4, reg_dnr_demo_lften , b0: Y b1:U b2:V . unsigned , default = 7 ++//Bit 3, reserved ++//Bit 2: 0, reg_dnr_demo_rgten , b0: Y b1:U b2:V . unsigned , default = 7 ++#define DNR_HVSIZE (0x2d01) ++#define P_DNR_HVSIZE (volatile unsigned int *)((0x2d01 << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28:16, reg_dnr_hsize , hsize . unsigned , default = 0 ++//Bit 15:13, reserved ++//Bit 12: 0, reg_dnr_vsize , vsize . unsigned , default = 0 ++#define DNR_DBLK_BLANK_NUM (0x2d02) ++#define P_DNR_DBLK_BLANK_NUM (volatile unsigned int *)((0x2d02 << 2) + 0xff900000) ++//Bit 31:16, reserved ++//Bit 15: 8, reg_dblk_hblank_num , deblock hor blank num . unsigned , default = 16 ++//Bit 7: 0, reg_dblk_vblank_num , deblock ver blank num . unsigned , default = 45 ++#define DNR_BLK_OFFST (0x2d03) ++#define P_DNR_BLK_OFFST (volatile unsigned int *)((0x2d03 << 2) + 0xff900000) ++//Bit 31: 7, reserved ++//Bit 6: 4, reg_dnr_hbofst , horizontal block offset may provide by software calc.. unsigned , default = 0 ++//Bit 3, reserved ++//Bit 2: 0, reg_dnr_vbofst , vertical block offset may provide by software calc.. unsigned , default = 0 ++#define DNR_GBS (0x2d04) ++#define P_DNR_GBS (volatile unsigned int *)((0x2d04 << 2) + 0xff900000) ++//Bit 31: 2, reserved ++//Bit 1: 0, reg_dnr_gbs , global block strength may update by software calc.. unsigned , default = 0 ++#define DNR_HBOFFST_STAT (0x2d05) ++#define P_DNR_HBOFFST_STAT (volatile unsigned int *)((0x2d05 << 2) + 0xff900000) ++//Bit 31:24, reg_dnr_hbof_difthd , dif threshold (>=) between LR and LL/RR. unsigned , default = 2 ++//Bit 23:16, reg_dnr_hbof_edgethd , edge threshold (<=) for LR . unsigned , default = 32 ++//Bit 15: 8, reg_dnr_hbof_flatthd , flat threshold (>=) for LR . unsigned , default = 0 ++//Bit 7, reserved ++//Bit 6: 4, reg_dnr_hbof_delta , delta for weighted bin accumulator. unsigned , default = 1 ++//Bit 3, reserved ++//Bit 2: 0, reg_dnr_hbof_statmod , statistic mode for horizontal block offset, 0: count flags for 8-bin, 1: count LRs for 8-bin, 2: count difs for 8-bin, 3: count weighted flags for 8-bin, 4: count flags for first 32-bin, 5: count LRs for first 32-bin, 6 or 7: count difs for first 32-bin. unsigned , default = 2 ++#define DNR_VBOFFST_STAT (0x2d06) ++#define P_DNR_VBOFFST_STAT (volatile unsigned int *)((0x2d06 << 2) + 0xff900000) ++//Bit 31:24, reg_dnr_vbof_difthd , dif threshold (>=) between Up and Dw. unsigned , default = 1 ++//Bit 23:16, reg_dnr_vbof_edgethd , edge threshold (<=) for Up/Dw. unsigned , default = 16 ++//Bit 15: 8, reg_dnr_vbof_flatthd , flat threshold (>=) for Up/Dw. unsigned , default = 0 ++//Bit 7, reserved ++//Bit 6: 4, reg_dnr_vbof_delta , delta for weighted bin accumulator. unsigned , default = 1 ++//Bit 3, reserved ++//Bit 2: 0, reg_dnr_vbof_statmod , statistic mode for vertical block offset, 0: count flags for 8-bin, 1: count Ups for 8-bin, 2: count difs for 8-bin, 3: count weighted flags for 8-bin, 4: count flags for first 32-bin, 5: count Ups for first 32-bin, 6 or 7: count difs for first 32-bin. unsigned , default = 2 ++#define DNR_GBS_STAT (0x2d07) ++#define P_DNR_GBS_STAT (volatile unsigned int *)((0x2d07 << 2) + 0xff900000) ++//Bit 31:24, reg_dnr_gbs_edgethd , edge threshold (<=) for LR . unsigned , default = 32 ++//Bit 23:16, reg_dnr_gbs_flatthd , flat threshold (>=) for LR . unsigned , default = 0 ++//Bit 15: 8, reg_dnr_gbs_varthd , variation threshold (<=) for Lvar/Rvar. unsigned , default = 16 ++//Bit 7: 0, reg_dnr_gbs_difthd , dif threshold (>=) between LR and LL/RR. unsigned , default = 2 ++#define DNR_STAT_X_START_END (0x2d08) ++#define P_DNR_STAT_X_START_END (volatile unsigned int *)((0x2d08 << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:16, reg_dnr_stat_xst . unsigned , default = 24 ++//Bit 15:14, reserved ++//Bit 13: 0, reg_dnr_stat_xed . unsigned , default = HSIZE - 25 ++#define DNR_STAT_Y_START_END (0x2d09) ++#define P_DNR_STAT_Y_START_END (volatile unsigned int *)((0x2d09 << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:16, reg_dnr_stat_yst . unsigned , default = 24 ++//Bit 15:14, reserved ++//Bit 13: 0, reg_dnr_stat_yed . unsigned , default = VSIZE - 25 ++#define DNR_LUMA (0x2d0a) ++#define P_DNR_LUMA (volatile unsigned int *)((0x2d0a << 2) + 0xff900000) ++//Bit 31:27, reserved ++//Bit 26:24, reg_dnr_luma_sqrtshft , left shift for fast squart of chroma, [0, 4]. unsigned , default = 2 ++//Bit 23:21, reserved ++//Bit 20:16, reg_dnr_luma_sqrtoffst , offset for fast squart of chroma. signed , default = 0 ++//Bit 15, reserved ++//Bit 14:12, reg_dnr_luma_wcmod , theta related to warm/cool segment line, 0: 0, 1: 45, 2: 90, 3: 135, 4: 180, 5: 225, 6: 270, 7: 315. . unsigned , default = 3 ++//Bit 11: 8, reg_dnr_luma_cshft , shift for calc. delta part, 0~8, . unsigned , default = 8 ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_dnr_luma_cgain , final gain for delta part, 32 normalized to "1". unsigned , default = 4 ++#define DNR_DB_YEDGE_THD (0x2d0b) ++#define P_DNR_DB_YEDGE_THD (volatile unsigned int *)((0x2d0b << 2) + 0xff900000) ++//Bit 31:24, reg_dnr_db_yedgethd0 , edge threshold0 for luma . unsigned , default = 12 ++//Bit 23:16, reg_dnr_db_yedgethd1 , edge threshold1 for luma . unsigned , default = 15 ++//Bit 15: 8, reg_dnr_db_yedgethd2 , edge threshold2 for luma . unsigned , default = 18 ++//Bit 7: 0, reg_dnr_db_yedgethd3 , edge threshold3 for luma . unsigned , default = 25 ++#define DNR_DB_CEDGE_THD (0x2d0c) ++#define P_DNR_DB_CEDGE_THD (volatile unsigned int *)((0x2d0c << 2) + 0xff900000) ++//Bit 31:24, reg_dnr_db_cedgethd0 , edge threshold0 for chroma . unsigned , default = 12 ++//Bit 23:16, reg_dnr_db_cedgethd1 , edge threshold1 for chroma . unsigned , default = 15 ++//Bit 15: 8, reg_dnr_db_cedgethd2 , edge threshold2 for chroma . unsigned , default = 18 ++//Bit 7: 0, reg_dnr_db_cedgethd3 , edge threshold3 for chroma . unsigned , default = 25 ++#define DNR_DB_HGAP (0x2d0d) ++#define P_DNR_DB_HGAP (volatile unsigned int *)((0x2d0d << 2) + 0xff900000) ++//Bit 31:24, reserved ++//Bit 23:16, reg_dnr_db_hgapthd , horizontal gap thd (<=) for very sure blockiness . unsigned , default = 8 ++//Bit 15: 8, reg_dnr_db_hgapdifthd , dif thd between hgap and lft/rgt hdifs. unsigned , default = 1 ++//Bit 7: 1, reserved ++//Bit 0, reg_dnr_db_hgapmod , horizontal gap calc. mode, 0: just use current col x, 1: find max between (x-1, x, x+1) . unsigned , default = 0 ++#define DNR_DB_HBS (0x2d0e) ++#define P_DNR_DB_HBS (volatile unsigned int *)((0x2d0e << 2) + 0xff900000) ++//Bit 31: 6, reserved ++//Bit 5: 4, reg_dnr_db_hbsup , horizontal bs up value . unsigned , default = 1 ++//Bit 3: 2, reg_dnr_db_hbsmax , max value of hbs for global control. unsigned , default = 3 ++//Bit 1: 0, reg_dnr_db_hgbsthd , gbs thd (>=) for hbs calc. . unsigned , default = 1 ++#define DNR_DB_HACT (0x2d0f) ++#define P_DNR_DB_HACT (volatile unsigned int *)((0x2d0f << 2) + 0xff900000) ++//Bit 31:16, reserved ++//Bit 15: 8, reg_dnr_db_hactthd0 , thd0 of hact, for block classification. unsigned , default = 10 ++//Bit 7: 0, reg_dnr_db_hactthd1 , thd1 of hact, for block classification. unsigned , default = 32 ++#define DNR_DB_YHDELTA_GAIN (0x2d10) ++#define P_DNR_DB_YHDELTA_GAIN (volatile unsigned int *)((0x2d10 << 2) + 0xff900000) ++//Bit 31:27, reserved ++//Bit 26:24, reg_dnr_db_yhdeltagain1 , (p1-q1) gain for Y's delta calc. when bs=1, normalized 8 as "1" . unsigned , default = 2 ++//Bit 23, reserved ++//Bit 22:20, reg_dnr_db_yhdeltagain2 , (p1-q1) gain for Y's delta calc. when bs=2, normalized 8 as "1" . unsigned , default = 0 ++//Bit 19, reserved ++//Bit 18:16, reg_dnr_db_yhdeltagain3 , (p1-q1) gain for Y's delta calc. when bs=3, normalized 8 as "1" . unsigned , default = 0 ++//Bit 15, reserved ++//Bit 14: 8, reg_dnr_db_yhdeltaadjoffst , offset for adjust Y's hdelta (-64, 63). signed , default = 0 ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_dnr_db_yhdeltaadjgain , gain for adjust Y's hdelta, normalized 32 as "1" . unsigned , default = 32 ++#define DNR_DB_YHDELTA2_GAIN (0x2d11) ++#define P_DNR_DB_YHDELTA2_GAIN (volatile unsigned int *)((0x2d11 << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:24, reg_dnr_db_yhdelta2gain2 , gain for bs=2's adjust Y's hdelta2, normalized 64 as "1" . unsigned , default = 8 ++//Bit 23:21, reserved ++//Bit 20:16, reg_dnr_db_yhdelta2offst2 , offset for bs=2's adjust Y's hdelta2 (-16, 15). signed , default = 0 ++//Bit 15:14, reserved ++//Bit 13: 8, reg_dnr_db_yhdelta2gain3 , gain for bs=3's adjust Y's hdelta2, normalized 64 as "1" . unsigned , default = 4 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_dnr_db_yhdelta2offst3 , offset for bs=3's adjust Y's hdelta2 (-16, 15). signed , default = 0 ++#define DNR_DB_CHDELTA_GAIN (0x2d12) ++#define P_DNR_DB_CHDELTA_GAIN (volatile unsigned int *)((0x2d12 << 2) + 0xff900000) ++//Bit 31:27, reserved ++//Bit 26:24, reg_dnr_db_chdeltagain1 , (p1-q1) gain for UV's delta calc. when bs=1, normalized 8 as "1". unsigned , default = 2 ++//Bit 23, reserved ++//Bit 22:20, reg_dnr_db_chdeltagain2 , (p1-q1) gain for UV's delta calc. when bs=2, normalized 8 as "1". unsigned , default = 0 ++//Bit 19, reserved ++//Bit 18:16, reg_dnr_db_chdeltagain3 , (p1-q1) gain for UV's delta calc. when bs=3, normalized 8 as "1". unsigned , default = 0 ++//Bit 15, reserved ++//Bit 14: 8, reg_dnr_db_chdeltaadjoffst , offset for adjust UV's hdelta (-64, 63). signed , default = 0 ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_dnr_db_chdeltaadjgain , gain for adjust UV's hdelta, normalized 32 as "1". unsigned , default = 32 ++#define DNR_DB_CHDELTA2_GAIN (0x2d13) ++#define P_DNR_DB_CHDELTA2_GAIN (volatile unsigned int *)((0x2d13 << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:24, reg_dnr_db_chdelta2gain2 , gain for bs=2's adjust UV's hdelta2, normalized 64 as "1" . unsigned , default = 8 ++//Bit 23:21, reserved ++//Bit 20:16, reg_dnr_db_chdelta2offst2 , offset for bs=2's adjust UV's hdelta2 (-16, 15). signed , default = 0 ++//Bit 15:14, reserved ++//Bit 13: 8, reg_dnr_db_chdelta2gain3 , gain for bs=2's adjust UV's hdelta2, normalized 64 as "1" . unsigned , default = 4 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_dnr_db_chdelta2offst3 , offset for bs=2's adjust UV's hdelta2 (-16, 15). signed , default = 0 ++#define DNR_DB_YC_VEDGE_THD (0x2d14) ++#define P_DNR_DB_YC_VEDGE_THD (volatile unsigned int *)((0x2d14 << 2) + 0xff900000) ++//Bit 31:16, reserved ++//Bit 15: 8, reg_dnr_db_yvedgethd , special Y's edge thd for vdb. unsigned , default = 12 ++//Bit 7: 0, reg_dnr_db_cvedgethd , special UV's edge thd for vdb. unsigned , default = 12 ++#define DNR_DB_VBS_MISC (0x2d15) ++#define P_DNR_DB_VBS_MISC (volatile unsigned int *)((0x2d15 << 2) + 0xff900000) ++//Bit 31:24, reg_dnr_db_vgapthd , vertical gap thd (<=) for very sure blockiness . unsigned , default = 8 ++//Bit 23:16, reg_dnr_db_vactthd , thd of vact, for block classification . unsigned , default = 10 ++//Bit 15: 8, reg_dnr_db_vgapdifthd , dif thd between vgap and vact. unsigned , default = 4 ++//Bit 7: 4, reserved ++//Bit 3: 2, reg_dnr_db_vbsmax , max value of vbs for global control. unsigned , default = 2 ++//Bit 1: 0, reg_dnr_db_vgbsthd , gbs thd (>=) for vbs calc. . unsigned , default = 1 ++#define DNR_DB_YVDELTA_GAIN (0x2d16) ++#define P_DNR_DB_YVDELTA_GAIN (volatile unsigned int *)((0x2d16 << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:24, reg_dnr_db_yvdeltaadjgain , gain for adjust Y's vdelta, normalized 32 as "1". unsigned , default = 32 ++//Bit 23, reserved ++//Bit 22:16, reg_dnr_db_yvdeltaadjoffst , offset for adjust Y's vdelta (-64, 63). signed , default = 0 ++//Bit 15:14, reserved ++//Bit 13: 8, reg_dnr_db_yvdelta2gain , gain for adjust Y's vdelta2, normalized 64 as "1". unsigned , default = 8 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_dnr_db_yvdelta2offst , offset for adjust Y's vdelta2 (-16, 15). signed , default = 0 ++#define DNR_DB_CVDELTA_GAIN (0x2d17) ++#define P_DNR_DB_CVDELTA_GAIN (volatile unsigned int *)((0x2d17 << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:24, reg_dnr_db_cvdeltaadjgain , gain for adjust UV's vdelta, normalized 32 as "1". unsigned , default = 32 ++//Bit 23, reserved ++//Bit 22:16, reg_dnr_db_cvdeltaadjoffst , offset for adjust UV's vdelta (-64, 63). signed , default = 0 ++//Bit 15:14, reserved ++//Bit 13: 8, reg_dnr_db_cvdelta2gain , gain for adjust UV's vdelta2, normalized 64 as "1". unsigned , default = 8 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_dnr_db_cvdelta2offst , offset for adjust UV's vdelta2 (-16, 15). signed , default = 0 ++#define DNR_RO_GBS_STAT_LR (0x2d18) ++#define P_DNR_RO_GBS_STAT_LR (volatile unsigned int *)((0x2d18 << 2) + 0xff900000) ++//Bit 31: 0, ro_gbs_stat_lr . unsigned , default = 0 ++#define DNR_RO_GBS_STAT_LL (0x2d19) ++#define P_DNR_RO_GBS_STAT_LL (volatile unsigned int *)((0x2d19 << 2) + 0xff900000) ++//Bit 31: 0, ro_gbs_stat_ll . unsigned , default = 0 ++#define DNR_RO_GBS_STAT_RR (0x2d1a) ++#define P_DNR_RO_GBS_STAT_RR (volatile unsigned int *)((0x2d1a << 2) + 0xff900000) ++//Bit 31: 0, ro_gbs_stat_rr . unsigned , default = 0 ++#define DNR_RO_GBS_STAT_DIF (0x2d1b) ++#define P_DNR_RO_GBS_STAT_DIF (volatile unsigned int *)((0x2d1b << 2) + 0xff900000) ++//Bit 31: 0, ro_gbs_stat_dif . unsigned , default = 0 ++#define DNR_RO_GBS_STAT_CNT (0x2d1c) ++#define P_DNR_RO_GBS_STAT_CNT (volatile unsigned int *)((0x2d1c << 2) + 0xff900000) ++//Bit 31: 0, ro_gbs_stat_cnt . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_0 (0x2d1d) ++#define P_DNR_RO_HBOF_STAT_CNT_0 (volatile unsigned int *)((0x2d1d << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt0 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_1 (0x2d1e) ++#define P_DNR_RO_HBOF_STAT_CNT_1 (volatile unsigned int *)((0x2d1e << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt1 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_2 (0x2d1f) ++#define P_DNR_RO_HBOF_STAT_CNT_2 (volatile unsigned int *)((0x2d1f << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt2 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_3 (0x2d20) ++#define P_DNR_RO_HBOF_STAT_CNT_3 (volatile unsigned int *)((0x2d20 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt3 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_4 (0x2d21) ++#define P_DNR_RO_HBOF_STAT_CNT_4 (volatile unsigned int *)((0x2d21 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt4 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_5 (0x2d22) ++#define P_DNR_RO_HBOF_STAT_CNT_5 (volatile unsigned int *)((0x2d22 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt5 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_6 (0x2d23) ++#define P_DNR_RO_HBOF_STAT_CNT_6 (volatile unsigned int *)((0x2d23 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt6 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_7 (0x2d24) ++#define P_DNR_RO_HBOF_STAT_CNT_7 (volatile unsigned int *)((0x2d24 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt7 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_8 (0x2d25) ++#define P_DNR_RO_HBOF_STAT_CNT_8 (volatile unsigned int *)((0x2d25 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt8 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_9 (0x2d26) ++#define P_DNR_RO_HBOF_STAT_CNT_9 (volatile unsigned int *)((0x2d26 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt9 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_10 (0x2d27) ++#define P_DNR_RO_HBOF_STAT_CNT_10 (volatile unsigned int *)((0x2d27 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt10 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_11 (0x2d28) ++#define P_DNR_RO_HBOF_STAT_CNT_11 (volatile unsigned int *)((0x2d28 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt11 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_12 (0x2d29) ++#define P_DNR_RO_HBOF_STAT_CNT_12 (volatile unsigned int *)((0x2d29 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt12 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_13 (0x2d2a) ++#define P_DNR_RO_HBOF_STAT_CNT_13 (volatile unsigned int *)((0x2d2a << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt13 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_14 (0x2d2b) ++#define P_DNR_RO_HBOF_STAT_CNT_14 (volatile unsigned int *)((0x2d2b << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt14 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_15 (0x2d2c) ++#define P_DNR_RO_HBOF_STAT_CNT_15 (volatile unsigned int *)((0x2d2c << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt15 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_16 (0x2d2d) ++#define P_DNR_RO_HBOF_STAT_CNT_16 (volatile unsigned int *)((0x2d2d << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt16 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_17 (0x2d2e) ++#define P_DNR_RO_HBOF_STAT_CNT_17 (volatile unsigned int *)((0x2d2e << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt17 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_18 (0x2d2f) ++#define P_DNR_RO_HBOF_STAT_CNT_18 (volatile unsigned int *)((0x2d2f << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt18 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_19 (0x2d30) ++#define P_DNR_RO_HBOF_STAT_CNT_19 (volatile unsigned int *)((0x2d30 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt19 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_20 (0x2d31) ++#define P_DNR_RO_HBOF_STAT_CNT_20 (volatile unsigned int *)((0x2d31 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt20 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_21 (0x2d32) ++#define P_DNR_RO_HBOF_STAT_CNT_21 (volatile unsigned int *)((0x2d32 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt21 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_22 (0x2d33) ++#define P_DNR_RO_HBOF_STAT_CNT_22 (volatile unsigned int *)((0x2d33 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt22 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_23 (0x2d34) ++#define P_DNR_RO_HBOF_STAT_CNT_23 (volatile unsigned int *)((0x2d34 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt23 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_24 (0x2d35) ++#define P_DNR_RO_HBOF_STAT_CNT_24 (volatile unsigned int *)((0x2d35 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt24 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_25 (0x2d36) ++#define P_DNR_RO_HBOF_STAT_CNT_25 (volatile unsigned int *)((0x2d36 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt25 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_26 (0x2d37) ++#define P_DNR_RO_HBOF_STAT_CNT_26 (volatile unsigned int *)((0x2d37 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt26 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_27 (0x2d38) ++#define P_DNR_RO_HBOF_STAT_CNT_27 (volatile unsigned int *)((0x2d38 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt27 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_28 (0x2d39) ++#define P_DNR_RO_HBOF_STAT_CNT_28 (volatile unsigned int *)((0x2d39 << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt28 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_29 (0x2d3a) ++#define P_DNR_RO_HBOF_STAT_CNT_29 (volatile unsigned int *)((0x2d3a << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt29 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_30 (0x2d3b) ++#define P_DNR_RO_HBOF_STAT_CNT_30 (volatile unsigned int *)((0x2d3b << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt30 . unsigned , default = 0 ++#define DNR_RO_HBOF_STAT_CNT_31 (0x2d3c) ++#define P_DNR_RO_HBOF_STAT_CNT_31 (volatile unsigned int *)((0x2d3c << 2) + 0xff900000) ++//Bit 31: 0, ro_hbof_stat_cnt31 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_0 (0x2d3d) ++#define P_DNR_RO_VBOF_STAT_CNT_0 (volatile unsigned int *)((0x2d3d << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt0 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_1 (0x2d3e) ++#define P_DNR_RO_VBOF_STAT_CNT_1 (volatile unsigned int *)((0x2d3e << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt1 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_2 (0x2d3f) ++#define P_DNR_RO_VBOF_STAT_CNT_2 (volatile unsigned int *)((0x2d3f << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt2 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_3 (0x2d40) ++#define P_DNR_RO_VBOF_STAT_CNT_3 (volatile unsigned int *)((0x2d40 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt3 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_4 (0x2d41) ++#define P_DNR_RO_VBOF_STAT_CNT_4 (volatile unsigned int *)((0x2d41 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt4 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_5 (0x2d42) ++#define P_DNR_RO_VBOF_STAT_CNT_5 (volatile unsigned int *)((0x2d42 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt5 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_6 (0x2d43) ++#define P_DNR_RO_VBOF_STAT_CNT_6 (volatile unsigned int *)((0x2d43 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt6 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_7 (0x2d44) ++#define P_DNR_RO_VBOF_STAT_CNT_7 (volatile unsigned int *)((0x2d44 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt7 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_8 (0x2d45) ++#define P_DNR_RO_VBOF_STAT_CNT_8 (volatile unsigned int *)((0x2d45 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt8 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_9 (0x2d46) ++#define P_DNR_RO_VBOF_STAT_CNT_9 (volatile unsigned int *)((0x2d46 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt9 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_10 (0x2d47) ++#define P_DNR_RO_VBOF_STAT_CNT_10 (volatile unsigned int *)((0x2d47 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt10 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_11 (0x2d48) ++#define P_DNR_RO_VBOF_STAT_CNT_11 (volatile unsigned int *)((0x2d48 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt11 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_12 (0x2d49) ++#define P_DNR_RO_VBOF_STAT_CNT_12 (volatile unsigned int *)((0x2d49 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt12 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_13 (0x2d4a) ++#define P_DNR_RO_VBOF_STAT_CNT_13 (volatile unsigned int *)((0x2d4a << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt13 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_14 (0x2d4b) ++#define P_DNR_RO_VBOF_STAT_CNT_14 (volatile unsigned int *)((0x2d4b << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt14 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_15 (0x2d4c) ++#define P_DNR_RO_VBOF_STAT_CNT_15 (volatile unsigned int *)((0x2d4c << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt15 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_16 (0x2d4d) ++#define P_DNR_RO_VBOF_STAT_CNT_16 (volatile unsigned int *)((0x2d4d << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt16 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_17 (0x2d4e) ++#define P_DNR_RO_VBOF_STAT_CNT_17 (volatile unsigned int *)((0x2d4e << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt17 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_18 (0x2d4f) ++#define P_DNR_RO_VBOF_STAT_CNT_18 (volatile unsigned int *)((0x2d4f << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt18 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_19 (0x2d50) ++#define P_DNR_RO_VBOF_STAT_CNT_19 (volatile unsigned int *)((0x2d50 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt19 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_20 (0x2d51) ++#define P_DNR_RO_VBOF_STAT_CNT_20 (volatile unsigned int *)((0x2d51 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt20 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_21 (0x2d52) ++#define P_DNR_RO_VBOF_STAT_CNT_21 (volatile unsigned int *)((0x2d52 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt21 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_22 (0x2d53) ++#define P_DNR_RO_VBOF_STAT_CNT_22 (volatile unsigned int *)((0x2d53 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt22 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_23 (0x2d54) ++#define P_DNR_RO_VBOF_STAT_CNT_23 (volatile unsigned int *)((0x2d54 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt23 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_24 (0x2d55) ++#define P_DNR_RO_VBOF_STAT_CNT_24 (volatile unsigned int *)((0x2d55 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt24 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_25 (0x2d56) ++#define P_DNR_RO_VBOF_STAT_CNT_25 (volatile unsigned int *)((0x2d56 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt25 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_26 (0x2d57) ++#define P_DNR_RO_VBOF_STAT_CNT_26 (volatile unsigned int *)((0x2d57 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt26 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_27 (0x2d58) ++#define P_DNR_RO_VBOF_STAT_CNT_27 (volatile unsigned int *)((0x2d58 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt27 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_28 (0x2d59) ++#define P_DNR_RO_VBOF_STAT_CNT_28 (volatile unsigned int *)((0x2d59 << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt28 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_29 (0x2d5a) ++#define P_DNR_RO_VBOF_STAT_CNT_29 (volatile unsigned int *)((0x2d5a << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt29 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_30 (0x2d5b) ++#define P_DNR_RO_VBOF_STAT_CNT_30 (volatile unsigned int *)((0x2d5b << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt30 . unsigned , default = 0 ++#define DNR_RO_VBOF_STAT_CNT_31 (0x2d5c) ++#define P_DNR_RO_VBOF_STAT_CNT_31 (volatile unsigned int *)((0x2d5c << 2) + 0xff900000) ++//Bit 31: 0, ro_vbof_stat_cnt31 . unsigned , default = 0 ++#define DNR_DM_CTRL (0x2d60) ++#define P_DNR_DM_CTRL (volatile unsigned int *)((0x2d60 << 2) + 0xff900000) ++//Bit 31:13, reserved ++//Bit 12, reg_dnr_dm_fedgeflg_en , enable edge flag calc. of each frame. unsigned , default = 1 ++//Bit 11, reg_dnr_dm_fedgeflg_cl , clear frame edge flag if needed. unsigned , default = 1 ++//Bit 10, reg_dnr_dm_fedgeflg_df , user defined edge when reg_dnr_dm_fedgeflg_en=0, default = 1 ++//Bit 9, reg_dnr_dm_en , enable demosquito function . unsigned , default = 1 ++//Bit 8, reg_dnr_dm_chrmen , enable chrome processing for demosquito. unsigned , default = 1 ++//Bit 7: 6, reg_dnr_dm_level , demosquito level . unsigned , default = 3 ++//Bit 5: 4, reg_dnr_dm_leveldw0 , level down when gbs is small. unsigned , default = 1 ++//Bit 3: 2, reg_dnr_dm_leveldw1 , level down for no edge/flat blocks. unsigned , default = 1 ++//Bit 1: 0, reg_dnr_dm_gbsthd , small/large threshold for gbs (<=). unsigned , default = 0 ++#define DNR_DM_NR_BLND (0x2d61) ++#define P_DNR_DM_NR_BLND (volatile unsigned int *)((0x2d61 << 2) + 0xff900000) ++//Bit 31:25, reserved ++//Bit 24, reg_dnr_dm_defalpen , enable user define alpha for dm & nr blend. unsigned , default = 0 ++//Bit 23:16, reg_dnr_dm_defalp , user define alpha for dm & nr blend if enable. unsigned , default = 0 ++//Bit 15:14, reserved ++//Bit 13: 8, reg_dnr_dm_alpgain , gain for nr/dm alpha, normalized 32 as "1". unsigned , default = 32 ++//Bit 7: 0, reg_dnr_dm_alpoffst , (-128, 127), offset for nr/dm alpha. signed , default = 0 ++#define DNR_DM_RNG_THD (0x2d62) ++#define P_DNR_DM_RNG_THD (volatile unsigned int *)((0x2d62 << 2) + 0xff900000) ++//Bit 31:24, reserved ++//Bit 23:16, reg_dnr_dm_rngminthd . unsigned , default = 2 ++//Bit 15: 8, reg_dnr_dm_rngmaxthd . unsigned , default = 64 ++//Bit 7: 0, reg_dnr_dm_rngdifthd . unsigned , default = 4 ++#define DNR_DM_RNG_GAIN_OFST (0x2d63) ++#define P_DNR_DM_RNG_GAIN_OFST (volatile unsigned int *)((0x2d63 << 2) + 0xff900000) ++//Bit 31:14, reserved ++//Bit 13: 8, reg_dnr_dm_rnggain , normalized 16 as "1" . unsigned , default = 16 ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_dnr_dm_rngofst . unsigned , default = 0 ++#define DNR_DM_DIR_MISC (0x2d64) ++#define P_DNR_DM_DIR_MISC (volatile unsigned int *)((0x2d64 << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29, reg_dnr_dm_diralpen . unsigned , default = 1 ++//Bit 28:24, reg_dnr_dm_diralpgain . unsigned , default = 0 ++//Bit 23:22, reserved ++//Bit 21:16, reg_dnr_dm_diralpofst . unsigned , default = 0 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_dnr_dm_diralpmin . unsigned , default = 0 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_dnr_dm_diralpmax . unsigned , default = 31 ++#define DNR_DM_COR_DIF (0x2d65) ++#define P_DNR_DM_COR_DIF (volatile unsigned int *)((0x2d65 << 2) + 0xff900000) ++//Bit 31: 4, reserved ++//Bit 3: 1, reg_dnr_dm_cordifshft . unsigned , default = 3 ++//Bit 0, reg_dnr_dm_cordifmod , 0:use max dir dif as cordif, 1: use max3x3 - min3x3 as cordif. unsigned , default = 1 ++#define DNR_DM_FLT_THD (0x2d66) ++#define P_DNR_DM_FLT_THD (volatile unsigned int *)((0x2d66 << 2) + 0xff900000) ++//Bit 31:24, reg_dnr_dm_fltthd00 , block flat threshold0 for block average difference when gbs is small, for flat block detection. unsigned , default = 4 ++//Bit 23:16, reg_dnr_dm_fltthd01 , block flat threshold1 for block average difference when gbs is small, for flat block detection. unsigned , default = 6 ++//Bit 15: 8, reg_dnr_dm_fltthd10 , block flat threshold0 for block average difference when gbs is large, for flat block detection. unsigned , default = 9 ++//Bit 7: 0, reg_dnr_dm_fltthd11 , block flat threshold1 for block average difference when gbs is large, for flat block detection. unsigned , default = 12 ++#define DNR_DM_VAR_THD (0x2d67) ++#define P_DNR_DM_VAR_THD (volatile unsigned int *)((0x2d67 << 2) + 0xff900000) ++//Bit 31:24, reg_dnr_dm_varthd00 , block variance threshold0 (>=) when gbs is small, for flat block detection. unsigned , default = 2 ++//Bit 23:16, reg_dnr_dm_varthd01 , block variance threshold1 (<=) when gbs is small, for flat block detection. unsigned , default = 15 ++//Bit 15: 8, reg_dnr_dm_varthd10 , block variance threshold0 (>=) when gbs is large, for flat block detection. unsigned , default = 3 ++//Bit 7: 0, reg_dnr_dm_varthd11 , block variance threshold1 (<=) when gbs is large, for flat block detection. unsigned , default = 24 ++#define DNR_DM_EDGE_DIF_THD (0x2d68) ++#define P_DNR_DM_EDGE_DIF_THD (volatile unsigned int *)((0x2d68 << 2) + 0xff900000) ++//Bit 31:24, reg_dnr_dm_edgethd0 , block edge threshold (<=) when gbs is small, for flat block detection. unsigned , default = 32 ++//Bit 23:16, reg_dnr_dm_edgethd1 , block edge threshold (<=) when gbs is large, for flat block detection. unsigned , default = 48 ++//Bit 15: 8, reg_dnr_dm_difthd0 , block dif threshold (<=) when gbs is small, for flat block detection. unsigned , default = 48 ++//Bit 7: 0, reg_dnr_dm_difthd1 , block dif threshold (<=) when gbs is large, for flat block detection. unsigned , default = 64 ++#define DNR_DM_AVG_THD (0x2d69) ++#define P_DNR_DM_AVG_THD (volatile unsigned int *)((0x2d69 << 2) + 0xff900000) ++//Bit 31:16, reserved ++//Bit 15: 8, reg_dnr_dm_avgthd0 , block average threshold (>=), for flat block detection. unsigned , default = 160 ++//Bit 7: 0, reg_dnr_dm_avgthd1 , block average threshold (<=), for flat block detection. unsigned , default = 128 ++#define DNR_DM_AVG_VAR_DIF_THD (0x2d6a) ++#define P_DNR_DM_AVG_VAR_DIF_THD (volatile unsigned int *)((0x2d6a << 2) + 0xff900000) ++//Bit 31:16, reserved ++//Bit 15: 8, reg_dnr_dm_avgdifthd , block average dif threshold (<) between cur and up block, for flat block detection. unsigned , default = 12 ++//Bit 7: 0, reg_dnr_dm_vardifthd , block variance dif threshold (>=) between cur and up block, for flat block detection. unsigned , default = 1 ++#define DNR_DM_VAR_EDGE_DIF_THD2 (0x2d6b) ++#define P_DNR_DM_VAR_EDGE_DIF_THD2 (volatile unsigned int *)((0x2d6b << 2) + 0xff900000) ++//Bit 31:24, reserved ++//Bit 23:16, reg_dnr_dm_varthd2 , block variance threshold (>=), for edge block detection. unsigned , default = 24 ++//Bit 15: 8, reg_dnr_dm_edgethd2 , block edge threshold (>=), for edge block detection. unsigned , default = 40 ++//Bit 7: 0, reg_dnr_dm_difthd2 , block dif threshold (>=), for edge block detection. unsigned , default = 80 ++#define DNR_DM_DIF_FLT_MISC (0x2d6c) ++#define P_DNR_DM_DIF_FLT_MISC (volatile unsigned int *)((0x2d6c << 2) + 0xff900000) ++//Bit 31:28, reg_dnr_dm_ldifoob , pre-defined large dif when pixel out of blocks. unsigned , default = 0 ++//Bit 27:24, reg_dnr_dm_bdifoob , pre-defined block dif when pixel out of blocks;. unsigned , default = 0 ++//Bit 23:16, reg_dnr_dm_fltalp , pre-defined alpha for dm and nr blending, when block is flat with mos.. unsigned , default = 200 ++//Bit 15:12, reserved ++//Bit 11: 8, reg_dnr_dm_fltminbdif , pre-defined min block dif for dm filter, when block is flat with mos.. unsigned , default = 12 ++//Bit 7, reserved ++//Bit 6: 2, reg_dnr_dm_difnormgain , gain for pixel dif normalization for dm filter, normalized 16 as "1". unsigned , default = 16 ++//Bit 1, reg_dnr_dm_difnormen , enable pixel dif normalization for dm filter. unsigned , default = 1 ++//Bit 0, reg_dnr_dm_difupden , enable block dif update using max of left, cur, right difs. unsigned , default = 0 ++#define DNR_DM_SDIF_LUT0_2 (0x2d6d) ++#define P_DNR_DM_SDIF_LUT0_2 (volatile unsigned int *)((0x2d6d << 2) + 0xff900000) ++//Bit 31:21, reserved ++//Bit 20:16, reg_dnr_dm_sdiflut0 , normally 0-16 . unsigned , default = 16 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_dnr_dm_sdiflut1 , normally 0-16 . unsigned , default = 14 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_dnr_dm_sdiflut2 , normally 0-16 . unsigned , default = 13 ++#define DNR_DM_SDIF_LUT3_5 (0x2d6e) ++#define P_DNR_DM_SDIF_LUT3_5 (volatile unsigned int *)((0x2d6e << 2) + 0xff900000) ++//Bit 31:21, reserved ++//Bit 20:16, reg_dnr_dm_sdiflut3 , normally 0-16 . unsigned , default = 10 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_dnr_dm_sdiflut4 , normally 0-16 . unsigned , default = 7 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_dnr_dm_sdiflut5 , normally 0-16 . unsigned , default = 5 ++#define DNR_DM_SDIF_LUT6_8 (0x2d6f) ++#define P_DNR_DM_SDIF_LUT6_8 (volatile unsigned int *)((0x2d6f << 2) + 0xff900000) ++//Bit 31:21, reserved ++//Bit 20:16, reg_dnr_dm_sdiflut6 , normally 0-16 . unsigned , default = 3 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_dnr_dm_sdiflut7 , normally 0-16 . unsigned , default = 1 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_dnr_dm_sdiflut8 , normally 0-16 . unsigned , default = 0 ++#define DNR_DM_LDIF_LUT0_2 (0x2d70) ++#define P_DNR_DM_LDIF_LUT0_2 (volatile unsigned int *)((0x2d70 << 2) + 0xff900000) ++//Bit 31:21, reserved ++//Bit 20:16, reg_dnr_dm_ldiflut0 , normally 0-16 . unsigned , default = 0 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_dnr_dm_ldiflut1 , normally 0-16 . unsigned , default = 4 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_dnr_dm_ldiflut2 , normally 0-16 . unsigned , default = 12 ++#define DNR_DM_LDIF_LUT3_5 (0x2d71) ++#define P_DNR_DM_LDIF_LUT3_5 (volatile unsigned int *)((0x2d71 << 2) + 0xff900000) ++//Bit 31:21, reserved ++//Bit 20:16, reg_dnr_dm_ldiflut3 , normally 0-16 . unsigned , default = 14 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_dnr_dm_ldiflut4 , normally 0-16 . unsigned , default = 15 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_dnr_dm_ldiflut5 , normally 0-16 . unsigned , default = 16 ++#define DNR_DM_LDIF_LUT6_8 (0x2d72) ++#define P_DNR_DM_LDIF_LUT6_8 (volatile unsigned int *)((0x2d72 << 2) + 0xff900000) ++//Bit 31:21, reserved ++//Bit 20:16, reg_dnr_dm_ldiflut6 , normally 0-16 . unsigned , default = 16 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_dnr_dm_ldiflut7 , normally 0-16 . unsigned , default = 16 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_dnr_dm_ldiflut8 , normally 0-16 . unsigned , default = 16 ++#define DNR_DM_DIF2NORM_LUT0_2 (0x2d73) ++#define P_DNR_DM_DIF2NORM_LUT0_2 (volatile unsigned int *)((0x2d73 << 2) + 0xff900000) ++//Bit 31:21, reserved ++//Bit 20:16, reg_dnr_dm_dif2normlut0 , normally 0-16 . unsigned , default = 16 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_dnr_dm_dif2normlut1 , normally 0-16 . unsigned , default = 5 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_dnr_dm_dif2normlut2 , normally 0-16 . unsigned , default = 3 ++#define DNR_DM_DIF2NORM_LUT3_5 (0x2d74) ++#define P_DNR_DM_DIF2NORM_LUT3_5 (volatile unsigned int *)((0x2d74 << 2) + 0xff900000) ++//Bit 31:21, reserved ++//Bit 20:16, reg_dnr_dm_dif2normlut3 , normally 0-16 . unsigned , default = 2 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_dnr_dm_dif2normlut4 , normally 0-16 . unsigned , default = 2 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_dnr_dm_dif2normlut5 , normally 0-16 . unsigned , default = 1 ++#define DNR_DM_DIF2NORM_LUT6_8 (0x2d75) ++#define P_DNR_DM_DIF2NORM_LUT6_8 (volatile unsigned int *)((0x2d75 << 2) + 0xff900000) ++//Bit 31:21, reserved ++//Bit 20:16, reg_dnr_dm_dif2normlut6 , normally 0-16 . unsigned , default = 1 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_dnr_dm_dif2normlut7 , normally 0-16 . unsigned , default = 1 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_dnr_dm_dif2normlut8 , normally 0-16 . unsigned , default = 1 ++#define DNR_DM_GMS_THD (0x2d76) ++#define P_DNR_DM_GMS_THD (volatile unsigned int *)((0x2d76 << 2) + 0xff900000) ++//Bit 31:16, reserved ++//Bit 15: 8, reg_gms_stat_thd0 . unsigned , default = 0 ++//Bit 7: 0, reg_gms_stat_thd1 . unsigned , default = 128 ++#define DNR_RO_DM_GMS_STAT_CNT (0x2d77) ++#define P_DNR_RO_DM_GMS_STAT_CNT (volatile unsigned int *)((0x2d77 << 2) + 0xff900000) ++//Bit 31: 0, ro_dm_gms_stat_cnt . unsigned , default = 0 ++#define DNR_RO_DM_GMS_STAT_MS (0x2d78) ++#define P_DNR_RO_DM_GMS_STAT_MS (volatile unsigned int *)((0x2d78 << 2) + 0xff900000) ++//Bit 31: 0, ro_dm_gms_stat_ms . unsigned , default = 0 ++// 0x80-0x90 ++// ++// Reading file: decomb_regs.h ++// ++#define DECOMB_DET_VERT_CON0 (0x2d80) ++#define P_DECOMB_DET_VERT_CON0 (volatile unsigned int *)((0x2d80 << 2) + 0xff900000) ++//Bit 31:24 reg_di_dcmb_det_vcon_thd0 default = 60 // u8 ++//Bit 23:16 reg_di_dcmb_det_vcon_thd1 default = 80 // u8 ++//Bit 15: 8 reg_di_dcmb_det_valp_lmt0 default = 63 // u8 ++//Bit 7: 0 reg_di_dcmb_det_valp_lmt1 default = 4 // u8 ++#define DECOMB_DET_VERT_CON1 (0x2d81) ++#define P_DECOMB_DET_VERT_CON1 (volatile unsigned int *)((0x2d81 << 2) + 0xff900000) ++//Bit 23:16 reg_di_dcmb_det_valp_lmt2 default = 0 // u8 ++//Bit 15: 8 reg_di_dcmb_det_vrate0 default = 32 // u8 ++//Bit 7: 0 reg_di_dcmb_det_vrate1 default = 4 // u8 ++#define DECOMB_DET_EDGE_CON0 (0x2d82) ++#define P_DECOMB_DET_EDGE_CON0 (volatile unsigned int *)((0x2d82 << 2) + 0xff900000) ++//Bit 31:24 reg_di_dcmb_det_econ_thd0 default = 60 // u8 ++//Bit 23:16 reg_di_dcmb_det_econ_thd1 default = 80 // u8 ++//Bit 15: 8 reg_di_dcmb_det_ealp_lmt0 default = 63 // u8 ++//Bit 7: 0 reg_di_dcmb_det_ealp_lmt1 default = 4 // u8 ++#define DECOMB_DET_EDGE_CON1 (0x2d83) ++#define P_DECOMB_DET_EDGE_CON1 (volatile unsigned int *)((0x2d83 << 2) + 0xff900000) ++//Bit 23:16 reg_di_dcmb_det_ealp_lmt2 default = 0 // u8 ++//Bit 15: 8 reg_di_dcmb_det_erate0 default = 32 // u8 ++//Bit 7: 0 reg_di_dcmb_det_erate1 default = 4 // u8 ++#define DECOMB_PARA (0x2d84) ++#define P_DECOMB_PARA (volatile unsigned int *)((0x2d84 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:28 reg_di_dcmb_cmb_lpf default = 1 // u2, 0:no lpf, 1:[1 2 1], 2,3: [1 2 2 2 1] ++//Bit 27:26 reg_di_dcmb_vedge_chk default = 0 // u2, vertical edge check, 0: no check, 1: vrt!=0, 2: vrt==3 ++//Bit 25:24 reg_di_dcmb_nedge_chk default = 0 // u2, no idea edge check, 0, no check, 1, check ++//Bit 23:20 reg_di_dcmb_edge_min default = 0 // u4, min edge for edge cmb ++//Bit 19:16 reg_di_dcmb_edge_max default = 15 // u4, min edge for edge cmb ++//Bit 15:8 reg_di_dcmb_bld_alp default = 255 // u8, user defined alpha for di & decmb blend ++//Bit 7:0 reg_di_dcmb_bld_alp_beta default = 40 // u8, beta for mtn & cmb blend, for bld alpha calc. ++#define DECOMB_BLND_CON0 (0x2d85) ++#define P_DECOMB_BLND_CON0 (volatile unsigned int *)((0x2d85 << 2) + 0xff900000) ++//Bit 31:24 reg_di_dcmb_bld_con_thd0 default = 100 // u8 ++//Bit 23:16 reg_di_dcmb_bld_con_thd1 default = 120 // u8 ++//Bit 15: 8 reg_di_dcmb_bld_alp_lmt0 default = 0 // u8 ++//Bit 7: 0 reg_di_dcmb_bld_alp_lmt1 default = 128 // u8 ++#define DECOMB_BLND_CON1 (0x2d86) ++#define P_DECOMB_BLND_CON1 (volatile unsigned int *)((0x2d86 << 2) + 0xff900000) ++//Bit 23:16 reg_di_dcmb_bld_alp_lmt2 default = 255 // u8 ++//Bit 15: 8 reg_di_dcmb_bld_rate0 default = 32 // u8 ++//Bit 7: 0 reg_di_dcmb_bld_rate1 default = 32 // u8 ++#define DECOMB_YC_THRD (0x2d87) ++#define P_DECOMB_YC_THRD (volatile unsigned int *)((0x2d87 << 2) + 0xff900000) ++//Bit 31:16 reserved ++//Bit 15: 8 reg_di_dcmb_ythd default = 2 // u8, default = 2 ++//Bit 7: 0 reg_di_dcmb_cthd default = 2 // u8, default = 2 ++#define DECOMB_MTN_GAIN_OFST (0x2d88) ++#define P_DECOMB_MTN_GAIN_OFST (volatile unsigned int *)((0x2d88 << 2) + 0xff900000) ++//Bit 31:22 reserved ++//Bit 21:16 reg_di_dcmb_mtn_alp_gain default = 16 // u6, 16 is normalized to '1' ++//Bit 15:9 reserved ++//Bit 8:0 reg_di_dcmb_mtn_alp_ofst default = 0 // s9, [-256, 255] ++#define DECOMB_CMB_SEL_GAIN_OFST (0x2d89) ++#define P_DECOMB_CMB_SEL_GAIN_OFST (volatile unsigned int *)((0x2d89 << 2) + 0xff900000) ++//Bit 31:22 reserved ++//Bit 21:16 reg_di_dcmb_cmb_sel_gain default = 48 // u6, 16 is normalized to '1' ++//Bit 15:9 reserved ++//Bit 8:0 reg_di_dcmb_cmb_sel_ofst default = 0 // s9, [-256, 255] ++#define DECOMB_WIND00 (0x2d8a) ++#define P_DECOMB_WIND00 (volatile unsigned int *)((0x2d8a << 2) + 0xff900000) ++//Bit 31:29 reserved ++//Bit 28:16 reg_di_dcmb_wnd00 default = 0 // u13, x0 for window 0, software control ++//Bit 15:13 reserved ++//Bit 12:0 reg_di_dcmb_wnd01 default = 719 // u13, x1 for window 0, HSIZE-1, software control ++#define DECOMB_WIND01 (0x2d8b) ++#define P_DECOMB_WIND01 (volatile unsigned int *)((0x2d8b << 2) + 0xff900000) ++//Bit 31:29 reserved ++//Bit 28:16 reg_di_dcmb_wnd02 default = 0 // u13, y0 for window 0, software control ++//Bit 15:13 reserved ++//Bit 12:0 reg_di_dcmb_wnd03 default = 39 // u13, y1 for window 0, software control ++#define DECOMB_WIND10 (0x2d8c) ++#define P_DECOMB_WIND10 (volatile unsigned int *)((0x2d8c << 2) + 0xff900000) ++//Bit 31:29 reserved ++//Bit 28:16 reg_di_dcmb_wnd10 default = 0 // u13, x0 for window 1, software control ++//Bit 15:13 reserved ++//Bit 12:0 reg_di_dcmb_wnd11 default = 719 // u13, x1 for window 1, HSIZE-1, software control ++#define DECOMB_WIND11 (0x2d8d) ++#define P_DECOMB_WIND11 (volatile unsigned int *)((0x2d8d << 2) + 0xff900000) ++//Bit 31:29 reserved ++//Bit 28:16 reg_di_dcmb_wnd12 default = 40 // u13, y0 for window 1, software control ++//Bit 15:13 reserved ++//Bit 12:0 reg_di_dcmb_wnd13 default = 239 // u13, y1 for window 1, VSIZE-1-40, software control ++#define DECOMB_MODE (0x2d8e) ++#define P_DECOMB_MODE (volatile unsigned int *)((0x2d8e << 2) + 0xff900000) ++//Bit 31:16 reserved ++//Bit 15 reg_di_dcmb_is_cmb_bef default = 1 // u1, 1: decide is_cmb before cmbing refine, 0: decide is_cmb after cmbing refine ++//Bit 14 reg_di_dcmb_en0 default = 1 // u1, enable decmobing for wind0 ++//Bit 13 reg_di_dcmb_en1 default = 1 // u1, enable decmobing for wind1 ++//Bit 12 reg_di_dcmb_en2 default = 1 // u1, enable decmobing for wind2 ++//Bit 11:10 reg_di_dcmb_lpf_mod0 default = 2 // u2, get combing free pixels of wind0 by: 0, vertical lpf, 1, edge lpf, 2,3, ei data ++//Bit 9:8 reg_di_dcmb_lpf_mod1 default = 2 // u2, get combing free pixels of wind1 by: 0, vertical lpf, 1, edge lpf, 2,3, ei data ++//Bit 7:6 reg_di_dcmb_lpf_mod2 default = 0 // u2, get combing free pixels of wind2 by: 0, vertical lpf, 1, edge lpf, 2,3, ei data ++//Bit 5 reg_di_dcmb_cmb_sel0 default = 1 // u1, wind0 decmb based on: 0, vert cmb, 1, edge cmb ++//Bit 4 reg_di_dcmb_cmb_sel1 default = 1 // u1, wind1 decmb based on: 0, vert cmb, 1, edge cmb ++//Bit 3 reg_di_dcmb_cmb_sel2 default = 0 // u1, wind2 decmb based on: 0, vert cmb, 1, edge cmb ++//Bit 2 reg_di_dcmb_alp_mod0 default = 1 // u1, wind0 decmb alpha based on: 0, user-defined, 1, motion adaptive ++//Bit 1 reg_di_dcmb_alp_mod1 default = 1 // u1, wind1 decmb alpha based on: 0, user-defined, 1, motion adaptive ++//Bit 0 reg_di_dcmb_alp_mod2 default = 1 // u1, wind2 decmb alpha based on: 0, user-defined, 1, motion adaptive ++#define DECOMB_FRM_SIZE (0x2d8f) ++#define P_DECOMB_FRM_SIZE (volatile unsigned int *)((0x2d8f << 2) + 0xff900000) ++//Bit 31:29 reserved ++//Bit 28:16 hsize_in default = 1920 // u13, pic horz size in unit: pixel ++//Bit 15:13 reserved ++//Bit 12:0 vsize_in default = 1080 // u13, pic vert size in unit: pixel ++#define DECOMB_HV_BLANK (0x2d90) ++#define P_DECOMB_HV_BLANK (volatile unsigned int *)((0x2d90 << 2) + 0xff900000) ++//Bit 31:16 reserved ++//Bit 15:8 hblank_num default = 20 // u8, hor blank time ++//Bit 7:0 vblank_num default = 50 // u8, ver blank time ++// ++// Closing file: decomb_regs.h ++// ++// 0x98-0xa3 ++// ++// Reading file: nr2_det_polar_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++#define NR2_POLAR3_MODE (0x2d98) ++#define P_NR2_POLAR3_MODE (volatile unsigned int *)((0x2d98 << 2) + 0xff900000) ++//Bit 31:20 reserved ++//Bit 19:18 reg_polar3_f02lpf_mod0 // unsigned , default = 3 low pass filter mode for field 0 and field2 before polar3 detection; 0 for no lpf, 1: [1 2 1]/4 vert lpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 no hlpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 [1 2 1]/4 hlpf ++//Bit 17:16 reg_polar3_f02lpf_mod1 // unsigned , default = 3 low pass filter mode for field 0 and field2 before polar3 detection; 0 for no lpf, 1: [1 2 1]/4 vert lpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 no hlpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 [1 2 1]/4 hlpf ++//Bit 15: 8 reg_polar3_dif02_thrd0 // unsigned , default = 5 threshold of dif for polar3 detection except for 32 detection, only do polar3 detection on obvious motion, [0] for luma, 1[1] for chroma ++//Bit 7: 0 reg_polar3_dif02_thrd1 // unsigned , default = 5 threshold of dif for polar3 detection except for 32 detection, only do polar3 detection on obvious motion, [0] for luma, 1[1] for chroma ++#define NR2_POLAR3_THRD (0x2d99) ++#define P_NR2_POLAR3_THRD (volatile unsigned int *)((0x2d99 << 2) + 0xff900000) ++//Bit 31:24 reg_polar3_txtf02_thrd0 // unsigned , default = 30 threshold to vertical f0f2 texture, if texture larger than this threshold, will not do the polar3 decision. ++//Bit 23:16 reg_polar3_txtf02_thrd1 // unsigned , default = 30 threshold to vertical f0f2 texture, if texture larger than this threshold, will not do the polar3 decision. ++//Bit 15: 8 reg_polar3_txtf1_thrd0 // unsigned , default = 20 threshold to vertical f1 texture, if texture larger than this threshold, will not do the polar3 decision. ++//Bit 7: 0 reg_polar3_txtf1_thrd1 // unsigned , default = 20 threshold to vertical f1 texture, if texture larger than this threshold, will not do the polar3 decision. ++#define NR2_POLAR3_PARA0 (0x2d9a) ++#define P_NR2_POLAR3_PARA0 (volatile unsigned int *)((0x2d9a << 2) + 0xff900000) ++//Bit 31:28 reg_polar3_rate00 // unsigned , default = 6 delt = rate*dif02/32, e.g. f2((f0+f2)/2 + delt), then polar3_p1++; ++//Bit 19:16 reg_polar3_rate11 // unsigned , default = 8 delt = rate*dif02/32, e.g. f2-ofst1((f0+f2)/2 + delt), then polar3_p1++; ++//Bit 15:12 reg_polar3_rate20 // unsigned , default = 2 delt = rate*dif02/32, e.g. f2((f0 + delt+ ofset2), then polar3_p2++; ++//Bit 11: 8 reg_polar3_rate21 // unsigned , default = 2 delt = rate*dif02/32, e.g. f2((f0 + delt+ ofset2), then polar3_p2++; ++//Bit 7: 1 reserved ++//Bit 0 reg_polar3_ro_reset // unsigned , default = 0 reset signal of the polar3 read only registers ++#define NR2_POLAR3_PARA1 (0x2d9b) ++#define P_NR2_POLAR3_PARA1 (volatile unsigned int *)((0x2d9b << 2) + 0xff900000) ++//Bit 31:24 reg_polar3_rate30 // unsigned , default = 48 delt = rate*dif02/32, e.g. f2((f0 + delt+ofst3), then polar3_32++; ++//Bit 23:16 reg_polar3_rate31 // unsigned , default = 48 delt = rate*dif02/32, e.g. f2((f0 + delt+ofst3), then polar3_32++; ++//Bit 15:12 reg_polar3_ofst30 // signed , default = 2 delt = rate*dif02/32, e.g. f2((f0 + delt+ofst3), then polar3_32++; ++//Bit 11: 8 reg_polar3_ofst31 // signed , default = 2 delt = rate*dif02/32, e.g. f2((f0 + delt+ofst3), then polar3_32++; ++//Bit 7: 4 reg_polar3_ofst20 // signed , default = 2 delt = rate*dif02/32, e.g. f2((f0 + delt+ ofset2), then polar3_p2++; ++//Bit 3: 0 reg_polar3_ofst21 // signed , default = 2 delt = rate*dif02/32, e.g. f2((f0 + delt+ ofset2), then polar3_p2++; ++#define NR2_POLAR3_CTRL (0x2d9c) ++#define P_NR2_POLAR3_CTRL (volatile unsigned int *)((0x2d9c << 2) + 0xff900000) ++//Bit 31:24 reg_polar3_ofst10 // signed , default = 1 ++//Bit 23:16 reg_polar3_ofst11 // signed , default = 1 ++//Bit 15: 8 reg_polar3_h_mute // unsigned , default = 10 horizontal pixels to mute for left right sides for polar3 detection; ++//Bit 7: 0 reg_polar3_v_mute // unsigned , default = 10 vertical pixels to mute for top and bottom sides for polar3 detection; ++#define NR2_RO_POLAR3_NUMOFPIX (0x2d9d) ++#define P_NR2_RO_POLAR3_NUMOFPIX (volatile unsigned int *)((0x2d9d << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23: 0 ro_polar3_numofpix // unsigned , default = 0 number of pixels detected as polar3 ++#define NR2_RO_POLAR3_SMOOTHMV (0x2d9e) ++#define P_NR2_RO_POLAR3_SMOOTHMV (volatile unsigned int *)((0x2d9e << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23: 0 ro_polar3_smoothmv // unsigned , default = 0 number of pixels with smooth mv, F(t) is close between avg of f(t-1) and f(t+1); ++#define NR2_RO_POLAR3_M1 (0x2d9f) ++#define P_NR2_RO_POLAR3_M1 (volatile unsigned int *)((0x2d9f << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23: 0 ro_polar3_m1 // unsigned , default = 0 number of pixels with F(t) is close to f(t-1) instead of f(t+1), but in between [f(t-1), f(t+1)]; ++#define NR2_RO_POLAR3_P1 (0x2da0) ++#define P_NR2_RO_POLAR3_P1 (volatile unsigned int *)((0x2da0 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23: 0 ro_polar3_p1 // unsigned , default = 0 number of pixels with F(t) is close to f(t+1) instead of f(t-1), but in between [f(t-1), f(t+1)]; ++#define NR2_RO_POLAR3_M2 (0x2da1) ++#define P_NR2_RO_POLAR3_M2 (volatile unsigned int *)((0x2da1 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23: 0 ro_polar3_m2 // unsigned , default = 0 number of pixels with F(t) is close to f(t-1) instead of f(t+1), but out side of (f(t-1), f(t+1)); ++#define NR2_RO_POLAR3_P2 (0x2da2) ++#define P_NR2_RO_POLAR3_P2 (volatile unsigned int *)((0x2da2 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23: 0 ro_polar3_p2 // unsigned , default = 0 number of pixels with F(t) is close to f(t+1) instead of f(t-1), but out side of (f(t-1), f(t+1)); ++#define NR2_RO_POLAR3_32 (0x2da3) ++#define P_NR2_RO_POLAR3_32 (volatile unsigned int *)((0x2da3 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23: 0 ro_polar3_32 // unsigned , default = 0 number of pixels with F(t) far from [f(t-1),f(t+1)] and f(t-1) is close to f(t+1); ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: nr2_det_polar_regs.h ++// ++// 0xa4-0xf7 / 0xff ++// ++// Reading file: nr4_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++//========== nr4_drt_regs register begin ==========// ++#define NR4_DRT_CTRL (0x2da4) ++#define P_NR4_DRT_CTRL (volatile unsigned int *)((0x2da4 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_ydrt_3line_ssd_gain // unsigned , default = 16 gain to max ssd normalized 16 as '1' ++//Bit 23:16 reg_nr4_ydrt_5line_ssd_gain // unsigned , default = 16 gain to max ssd normalized 16 as '1' ++//Bit 15 reserved ++//Bit 14:13 reg_nr4_drt_yhsad_mode // unsigned , default = 1 mode for luma horiztonal sad calc., 0: no vertical lpf, 1: vertical [1 2 1], 2 or 3: vertical [ 1 2 2 2 1] if 5 lines ++//Bit 12:11 reg_nr4_drt_chsad_mode // unsigned , default = 1 mode for chroma horiztonal sad calc., 0: no vertical lpf, 1: vertical [1 2 1], 2 or 3: vertical [ 1 2 2 2 1] if 5 lines ++//Bit 10 reg_nr4_drt_yhsad_hlpf // unsigned , default = 1 hlpf for luma hsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf ++//Bit 9 reg_nr4_drt_yvsad_hlpf // unsigned , default = 1 hlpf for luma vsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf ++//Bit 8 reg_nr4_drt_ydsad_hlpf // unsigned , default = 1 hlpf for luma dsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf ++//Bit 7 reg_nr4_drt_chsad_hlpf // unsigned , default = 1 hlpf for chrome hsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf ++//Bit 6 reg_nr4_drt_cvsad_hlpf // unsigned , default = 1 hlpf for chroma vsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf ++//Bit 5 reg_nr4_drt_cdsad_hlpf // unsigned , default = 1 hlpf for chroma dsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf ++//Bit 4 reg_nr4_ydrt_dif_mode // unsigned , default = 1 0:y_dif, 1: y_dif + (u_dif + v_dif)/2 ++//Bit 3: 2 reg_nr4_cdrt_dif_mode // unsigned , default = 2 0:(u_dif + v_dif), 1: y_dif/4 + (u_dif + v_dif)*3/4, 2:y_dif/2 + (u_dif + v_dif)/2, 3: y_dif (not recommended) ++//Bit 1: 0 reserved ++#define NR4_DRT_YSAD_GAIN (0x2da5) ++#define P_NR4_DRT_YSAD_GAIN (volatile unsigned int *)((0x2da5 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_ysad_hrz_gain // unsigned , default = 16 gain for horizontal sad, 16 normalized to "1" ++//Bit 23:16 reg_nr4_ysad_diag_gain // unsigned , default = 20 gain for diagonal sad, 16 normalized to "1" ++//Bit 15: 8 reg_nr4_ysad_vrt_gain // unsigned , default = 16 gain for vertical sad, 16 normalized to "1" ++//Bit 7: 6 reserved ++//Bit 5: 0 reg_nr4_drt_ysad_core_rate // unsigned , default = 6 rate of coring for sad(theta) - sad(theta+pi/2)*rate/64 ++#define NR4_DRT_CSAD_GAIN (0x2da6) ++#define P_NR4_DRT_CSAD_GAIN (volatile unsigned int *)((0x2da6 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_csad_hrz_gain // unsigned , default = 16 gain for horizontal sad, 16 normalized to "1" ++//Bit 23:16 reg_nr4_csad_diag_gain // unsigned , default = 20 gain for diagonal sad, 16 normalized to "1" ++//Bit 15: 8 reg_nr4_csad_vrt_gain // unsigned , default = 16 gain for vertical sad, 16 normalized to "1" ++//Bit 7: 6 reserved ++//Bit 5: 0 reg_nr4_drt_csad_core_rate // unsigned , default = 6 rate of coring for sad(theta) - sad(theta+pi/2)*rate/64 ++#define NR4_DRT_SAD_ALP_CORE (0x2da7) ++#define P_NR4_DRT_SAD_ALP_CORE (volatile unsigned int *)((0x2da7 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:20 reg_nr4_ydrt_alp_core_rate // unsigned , default = 0 luma ratio to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 0/32 ++//Bit 19:16 reg_nr4_cdrt_alp_core_rate // unsigned , default = 0 chroma ratio to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 0/32 ++//Bit 15:14 reserved ++//Bit 13: 8 reg_nr4_ydrt_alp_core_ofst // unsigned , default = 10 luma offset to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 10 ++//Bit 7: 6 reserved ++//Bit 5: 0 reg_nr4_cdrt_alp_core_ofst // unsigned , default = 10 chroma offset to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 10 ++#define NR4_DRT_ALP_MINMAX (0x2da8) ++#define P_NR4_DRT_ALP_MINMAX (volatile unsigned int *)((0x2da8 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:24 reg_nr4_ydrt_alp_min // unsigned , default = 0 luma min value of alpha, dft = 0 ++//Bit 23:22 reserved ++//Bit 21:16 reg_nr4_ydrt_alp_max // unsigned , default = 63 luma max value of alpha, dft = 63 ++//Bit 15:14 reserved ++//Bit 13: 8 reg_nr4_cdrt_alp_min // unsigned , default = 0 chroma min value of alpha, dft = 0 ++//Bit 7: 6 reserved ++//Bit 5: 0 reg_nr4_cdrt_alp_max // unsigned , default = 63 chroma max value of alpha, dft = 63 ++//========== nr4_drt_regs register end ==========// ++//========== nr4_snr_regs register begin ==========// ++#define NR4_SNR_CTRL_REG (0x2da9) ++#define P_NR4_SNR_CTRL_REG (volatile unsigned int *)((0x2da9 << 2) + 0xff900000) ++//Bit 31:13 reserved ++//Bit 12 reg_nr4_bet2_sel // unsigned , default = 1 ++//Bit 11: 9 reg_nr4_snr2_sel_mode // unsigned , default = 0 0: no filter, 1: adpgau, adp_drt_lpf blend; 2: adpgau, drt4_lpf blend; 3: adp_drt_lpf method, 4: drt4_lpf method, 5: adp_drt_ //original image blend, 6: drt4_lpf, original image blend, 7: adpgau method; dft=1 ++//Bit 8 reg_nr4_snr2_gaulpf_mode // unsigned , default = 1 0: 3*5 or 5*5 gaussian lpf; 1: 3*3 (window size) gaussian lpf; dft=1 ++//Bit 7: 6 reg_nr4_snr2_alpha0_sad_mode // unsigned , default = 3 0: max_sad*max_ssd; 1: max_sad*max_sad; 2: adp_max_sad*max_ssd; 3: adp_max_sad*adp_max_sad dft=3 ++//Bit 5: 4 reg_nr4_snr2_alpha1_sad_mode // unsigned , default = 2 0: max_sad; 1: cross_max_sad; 2 or 3: adp_sad dft=2 ++//Bit 3: 2 reserved ++//Bit 1: 0 reg_nr4_snr2_adp_drtlpf_mode // unsigned , default = 3 0: adp_drtlpf [2 1 1]/4, 1: adp_drtlpf [4 2 1 1]/8; 2: adp_drtlpf [2 2 2 1 1]/8; 3: adp_drtlpf [7 7 7 6 5]/32; dft=3; ++#define NR4_SNR_ALPHA0_MAX_MIN (0x2daa) ++#define P_NR4_SNR_ALPHA0_MAX_MIN (volatile unsigned int *)((0x2daa << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:23 reg_nr4_snr2_alp0_ymin // unsigned , default = 127 normalized to 128 as '1' ++//Bit 22:16 reg_nr4_snr2_alp0_ymax // unsigned , default = 127 normalized to 128 as '1' ++//Bit 15:14 reserved ++//Bit 13: 7 reg_nr4_snr2_alp0_cmin // unsigned , default = 127 normalized to 128 as '1' ++//Bit 6: 0 reg_nr4_snr2_alp0_cmax // unsigned , default = 127 normalized to 128 as '1' ++#define NR4_ALP0C_ERR2CURV_LIMIT0 (0x2dab) ++#define P_NR4_ALP0C_ERR2CURV_LIMIT0 (volatile unsigned int *)((0x2dab << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_snr2_alp0_minerr_cpar0 // unsigned , default = 0 threshold0 of curve to map mierr to alp0 for chroma channel, this will be set value of flat region mierr that no need blur. ++//Bit 23:16 reg_nr4_snr2_alp0_minerr_cpar1 // unsigned , default = 25 threshold1 of curve to map mierr to alp0 for chroma channel,this will be set value of texture region mierr that can not blur. ++//Bit 15: 8 reg_nr4_snr2_alp0_minerr_cpar5 // unsigned , default = 40 rate0 (for mierrth1) of curve to map mierr to alp0 for chroma channel. the larger of the value, the deep of the slope. 0~255. ++#define NR4_ALP0C_ERR2CURV_LIMIT1 (0x2dac) ++#define P_NR4_ALP0C_ERR2CURV_LIMIT1 (volatile unsigned int *)((0x2dac << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:16 reg_nr4_snr2_alp0_minerr_cpar2 // unsigned , default = 127 level limit(for mierrth1) of curve to map mierr to alp0 for chroma channel, that we can do for texture region. 0~255. ++#define NR4_ALP0Y_ERR2CURV_LIMIT0 (0x2dad) ++#define P_NR4_ALP0Y_ERR2CURV_LIMIT0 (volatile unsigned int *)((0x2dad << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_snr2_alp0_minerr_ypar0 // unsigned , default = 0 threshold0 of curve to map mierr to alp0 for luma channel, this will be set value of flat region mierr that no need blur. 0~255. ++//Bit 23:16 reg_nr4_snr2_alp0_minerr_ypar1 // unsigned , default = 25 threshold1 of curve to map mierr to alp0 for luma channel,this will be set value of texture region mierr that can not blur. ++//Bit 15: 8 reg_nr4_snr2_alp0_minerr_ypar5 // unsigned , default = 40 rate0 (for mierrth1) of curve to map mierr to alp0 for luma channel. the larger of the value, the deep of the slope. 0~255. ++#define NR4_ALP0Y_ERR2CURV_LIMIT1 (0x2dae) ++#define P_NR4_ALP0Y_ERR2CURV_LIMIT1 (volatile unsigned int *)((0x2dae << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:16 reg_nr4_snr2_alp0_minerr_ypar2 // unsigned , default = 127 level limit(for mierrth1) of curve to map mierr to alp0 for luma channel, alp0 that we can do for texture region. 0~255. ++#define NR4_SNR_ALPA1_RATE_AND_OFST (0x2daf) ++#define P_NR4_SNR_ALPA1_RATE_AND_OFST (volatile unsigned int *)((0x2daf << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:18 reg_nr4_snr2_alp1_ycore_rate // unsigned , default = 0 normalized 64 as "1" ++//Bit 17:12 reg_nr4_snr2_alp1_ccore_rate // unsigned , default = 0 normalized 64 as "1" ++//Bit 11: 6 reg_nr4_snr2_alp1_ycore_ofst // signed , default = 3 normalized 64 as "1" ++//Bit 5: 0 reg_nr4_snr2_alp1_ccore_ofst // signed , default = 3 normalized 64 as "1" ++#define NR4_SNR_ALPHA1_MAX_MIN (0x2db0) ++#define P_NR4_SNR_ALPHA1_MAX_MIN (volatile unsigned int *)((0x2db0 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:18 reg_nr4_snr2_alp1_ymin // unsigned , default = 0 normalized to 64 as '1' ++//Bit 17:12 reg_nr4_snr2_alp1_ymax // unsigned , default = 63 normalized to 64 as '1' ++//Bit 11: 6 reg_nr4_snr2_alp1_cmin // unsigned , default = 0 normalized to 64 as '1' ++//Bit 5: 0 reg_nr4_snr2_alp1_cmax // unsigned , default = 63 normalized to 64 as '1' ++#define NR4_ALP1C_ERR2CURV_LIMIT0 (0x2db1) ++#define P_NR4_ALP1C_ERR2CURV_LIMIT0 (volatile unsigned int *)((0x2db1 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_snr2_alp1_minerr_cpar0 // unsigned , default = 0 annel, this will be set value of flat region mierr that no need directional NR. 0~255. ++//Bit 23:16 reg_nr4_snr2_alp1_minerr_cpar1 // unsigned , default = 24 hannel,this will be set value of texture region mierr that can not do directional NR. 0~255. ++//Bit 15: 8 reg_nr4_snr2_alp1_minerr_cpar5 // unsigned , default = 0 a/chroma channel. the larger of the value, the deep of the slope. ++//Bit 7: 0 reg_nr4_snr2_alp1_minerr_cpar6 // unsigned , default = 20 a/chroma channel. the larger of the value, the deep of the slope. 0~255 ++#define NR4_ALP1C_ERR2CURV_LIMIT1 (0x2db2) ++#define P_NR4_ALP1C_ERR2CURV_LIMIT1 (volatile unsigned int *)((0x2db2 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:16 reg_nr4_snr2_alp1_minerr_cpar2 // unsigned , default = 0 will be set to alp1 that we can do for flat region. 0~255. ++//Bit 15: 8 reg_nr4_snr2_alp1_minerr_cpar3 // unsigned , default = 16 this will be set to alp1 that we can do for misc region. 0~255. ++//Bit 7: 0 reg_nr4_snr2_alp1_minerr_cpar4 // unsigned , default = 63 will be set to alp1 that we can do for texture region. 0~255.255 before ++#define NR4_ALP1Y_ERR2CURV_LIMIT0 (0x2db3) ++#define P_NR4_ALP1Y_ERR2CURV_LIMIT0 (volatile unsigned int *)((0x2db3 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_snr2_alp1_minerr_ypar0 // unsigned , default = 0 thra/chroma channel, this will be set value of flat region mierr that no need directional NR. 0~255. ++//Bit 23:16 reg_nr4_snr2_alp1_minerr_ypar1 // unsigned , default = 24 thra/chroma channel,this will be set value of texture region mierr that can not do directional NR. 0~255. ++//Bit 15: 8 reg_nr4_snr2_alp1_minerr_ypar5 // unsigned , default = 0 ratlp1 for luma/chroma channel. the larger of the value, the deep of the slope. ++//Bit 7: 0 reg_nr4_snr2_alp1_minerr_ypar6 // unsigned , default = 20 ratlp1 for luma/chroma channel. the larger of the value, the deep of the slope. 0~255 ++#define NR4_ALP1Y_ERR2CURV_LIMIT1 (0x2db4) ++#define P_NR4_ALP1Y_ERR2CURV_LIMIT1 (volatile unsigned int *)((0x2db4 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:16 reg_nr4_snr2_alp1_minerr_ypar2 // unsigned , default = 0 lev to alp1 for luma/chroma channel, this will be set to alp1 that we can do for flat region. 0~255. ++//Bit 15: 8 reg_nr4_snr2_alp1_minerr_ypar3 // unsigned , default = 16 levierr to alp1 for luma/chroma channel, this will be set to alp1 that we can do for misc region. 0~255. ++//Bit 7: 0 reg_nr4_snr2_alp1_minerr_ypar4 // unsigned , default = 63 lev to alp1 for luma/chroma channel, this will be set to alp1 that we can do for texture region. 0~255.255 before ++//========== nr4_snr_regs register end ==========// ++//========== nr4_tnr_regs register begin ==========// ++#define NR4_MTN_CTRL (0x2db5) ++#define P_NR4_MTN_CTRL (volatile unsigned int *)((0x2db5 << 2) + 0xff900000) ++//Bit 31: 2 reserved ++//Bit 1 reg_nr4_mtn_ref_en // unsigned , default = 1 enable motion refinement, dft = 1 ++//Bit 0 reg_nr4_mtn_ref_bet_sel // unsigned , default = 0 beta selection mode for motion refinement, 0: beta1, 1: beta2, dft = 0 ++#define NR4_MTN_REF_PAR0 (0x2db6) ++#define P_NR4_MTN_REF_PAR0 (volatile unsigned int *)((0x2db6 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_mtn_ref_par0 // unsigned , default = 24 par0 for beta to gain, dft = ++//Bit 23:16 reg_nr4_mtn_ref_par1 // unsigned , default = 60 par1 for beta to gain, dft = ++//Bit 15: 8 reg_nr4_mtn_ref_par2 // unsigned , default = 4 par2 for beta to gain, dft = ++//Bit 7: 0 reg_nr4_mtn_ref_par3 // unsigned , default = 32 par3 for beta to gain, dft = ++#define NR4_MTN_REF_PAR1 (0x2db7) ++#define P_NR4_MTN_REF_PAR1 (volatile unsigned int *)((0x2db7 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:16 reg_nr4_mtn_ref_par4 // unsigned , default = 128 par4 for beta to gain, dft = ++//Bit 15: 8 reg_nr4_mtn_ref_par5 // unsigned , default = 40 par5 for beta to gain, dft = ++//Bit 7: 0 reg_nr4_mtn_ref_par6 // unsigned , default = 20 par6 for beta to gain, dft = ++//========== nr4_tnr_regs register end ==========// ++//========== nr4_mcnr_regs register begin ==========// ++#define NR4_MCNR_LUMA_ENH_CTRL (0x2db8) ++#define P_NR4_MCNR_LUMA_ENH_CTRL (volatile unsigned int *)((0x2db8 << 2) + 0xff900000) ++//Bit 31: 4 reserved ++//Bit 3 reg_nr4_luma_plus_en // unsigned , default = 1 enable luma enhancement, dft = 1 ++//Bit 2 reg_nr4_luma_plus_wt_mode // unsigned , default = 1 luma weight calc mode, 0:sqrt(1+x^2), 1: 1+abs(x), dft = 0 ++//Bit 1: 0 reg_nr4_luma_plus_orient_mode // unsigned , default = 1 0: only use previous orient for pre and cur luma plus, 1: 0: only use current orient for pre and cur luma plus ++#define NR4_MCNR_LUMA_STAT_LIMTX (0x2db9) ++#define P_NR4_MCNR_LUMA_STAT_LIMTX (volatile unsigned int *)((0x2db9 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:16 reg_nr4_luma_plus_xst // unsigned , default = 8 start for luma plus statistic, dft = 8 ++//Bit 15:14 reserved ++//Bit 13: 0 reg_nr4_luma_plus_xed // unsigned , default = 711 end for luma plus statistic, dft = HSIZE-8-1; ++#define NR4_MCNR_LUMA_STAT_LIMTY (0x2dba) ++#define P_NR4_MCNR_LUMA_STAT_LIMTY (volatile unsigned int *)((0x2dba << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:16 reg_nr4_luma_plus_yst // unsigned , default = 8 start for luma plus statistic, dft = 8 ++//Bit 15:14 reserved ++//Bit 13: 0 reg_nr4_luma_plus_yed // unsigned , default = 231 end for luma plus statistic, dft = VSIZE-8-1 ++#define NR4_MCNR_LUMA_DIF_CALC (0x2dbb) ++#define P_NR4_MCNR_LUMA_DIF_CALC (volatile unsigned int *)((0x2dbb << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:24 reg_nr4_luma_plus_ugain // unsigned , default = 8 U's gain for luma enhancement, 16 normalized as '1' ++//Bit 23:22 reserved ++//Bit 21:16 reg_nr4_luma_plus_vgain // unsigned , default = 8 V's gain for luma enhancement, 16 normalized as '1' ++//Bit 15: 8 reg_nr4_luma_plus_ycor_thd // unsigned , default = 2 Y coring threshold for difference calc., dft = 0 ++//Bit 7: 0 reg_nr4_luma_plus_ccor_thd // unsigned , default = 0 C coring threshold for difference calc., dft = 0 ++#define NR4_MCNR_LUMAPRE_CAL_PRAM (0x2dbc) ++#define P_NR4_MCNR_LUMAPRE_CAL_PRAM (volatile unsigned int *)((0x2dbc << 2) + 0xff900000) ++//Bit 31:26 reserved ++//Bit 25:24 reg_nr4_pre_u_orient // signed , default = 0 orientation of previous U, initial to 0, and will be updated by software ++//Bit 23:18 reserved ++//Bit 17:16 reg_nr4_pre_v_orient // signed , default = 0 orientation of previous V, initial to 0, and will be updated by software ++//Bit 15: 8 reg_nr4_pre_u_mean // unsigned , default = 0 mean of previous U, initial to 0, and will be updated by software ++//Bit 7: 0 reg_nr4_pre_v_mean // unsigned , default = 0 mean of previousV, initial to 0, and will be updated by software ++#define NR4_MCNR_LUMACUR_CAL_PRAM (0x2dbd) ++#define P_NR4_MCNR_LUMACUR_CAL_PRAM (volatile unsigned int *)((0x2dbd << 2) + 0xff900000) ++//Bit 31:26 reserved ++//Bit 25:24 reg_nr4_cur_u_orient // signed , default = 0 orientation of current U, initial to 0, and will be updated by software ++//Bit 23:18 reserved ++//Bit 17:16 reg_nr4_cur_v_orient // signed , default = 0 orientation of current V, initial to 0, and will be updated by software ++//Bit 15: 8 reg_nr4_cur_u_mean // unsigned , default = 0 mean of current U, initial to 0, and will be updated by software ++//Bit 7: 0 reg_nr4_cur_v_mean // unsigned , default = 0 mean of current, initial to 0, and will be updated by software ++#define NR4_MCNR_MV_CTRL_REG (0x2dbe) ++#define P_NR4_MCNR_MV_CTRL_REG (volatile unsigned int *)((0x2dbe << 2) + 0xff900000) ++//Bit 31:14 reserved ++//Bit 13:12 reg_nr4_sad_bitw // unsigned , default = 2 sad bit width (8 + x) before clip to u8, dft = 1 ++//Bit 11: 4 reg_nr4_glb_gain // unsigned , default = 64 global gain calc. by software, 64 is normalized as '1' ++//Bit 3: 0 reg_nr4_mv_err_rsft // unsigned , default = 8 right shift for mv err calc., dft = 9 ++#define NR4_MCNR_MV_GAIN0 (0x2dbf) ++#define P_NR4_MCNR_MV_GAIN0 (volatile unsigned int *)((0x2dbf << 2) + 0xff900000) ++//Bit 31:28 reg_nr4_lftmvx_gain // unsigned , default = 1 left mvx gain for err calc., dft = 1 ++//Bit 27:24 reg_nr4_lftmvy_gain // unsigned , default = 1 left mvy gain for err calc., dft = 1 ++//Bit 23:20 reg_nr4_zmvx_gain // unsigned , default = 5 zero mvx gain for err calc., dft = 2 ++//Bit 19:16 reg_nr4_zmvy_gain // unsigned , default = 5 zero mvy gain for err calc., dft = 4 ++//Bit 15:12 reg_nr4_lmvx0_gain // unsigned , default = 2 line mvx0 gain for err calc., dft = 1 ++//Bit 11: 8 reg_nr4_lmvx1_gain // unsigned , default = 2 line mvx1 gain for err calc., dft = 1 ++//Bit 7: 4 reg_nr4_lmvy0_gain // unsigned , default = 2 line mvy0 gain for err calc., dft = 1 ++//Bit 3: 0 reg_nr4_lmvy1_gain // unsigned , default = 2 line mvy1 gain for err calc., dft = 1 ++#define NR4_MCNR_LMV_PARM (0x2dc0) ++#define P_NR4_MCNR_LMV_PARM (volatile unsigned int *)((0x2dc0 << 2) + 0xff900000) ++//Bit 31:28 reg_nr4_lmv_rt0 // unsigned , default = 3 ratio of max lmv ++//Bit 27:24 reg_nr4_lmv_rt1 // unsigned , default = 3 ratio of second max lmv ++//Bit 23:22 reserved ++//Bit 21:16 reg_nr4_lmv_num_lmt0 // unsigned , default = 16 lmv0 least/limit number of (total number - zero_bin) ++//Bit 15:14 reserved ++//Bit 13: 8 reg_nr4_lmv_num_lmt1 // unsigned , default = 8 lmv1 least/limit number of (total number - zero_bin - max0) ++//Bit 7: 2 reserved ++//Bit 1: 0 reg_nr4_max_sad_rng // unsigned , default = 1 search range of max2 sad in small region, dft = 1 ++#define NR4_MCNR_ALP0_REG (0x2dc1) ++#define P_NR4_MCNR_ALP0_REG (volatile unsigned int *)((0x2dc1 << 2) + 0xff900000) ++//Bit 31:26 reserved ++//Bit 25 reg_nr4_alp0_fail_chk // unsigned , default = 1 enable check for alp0 fail status ++//Bit 24 reg_nr4_bet0_coef_ref_en // unsigned , default = 1 bet1 refinement by coef_blt ++//Bit 23:16 reg_nr4_alp0_posad_gain // unsigned , default = 255 the sad (norm) gain for pixel pointed by MV; ++//Bit 15:10 reserved ++//Bit 9: 8 reg_nr4_alp0_norm_mode // unsigned , default = 0 alp0 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3 ++//Bit 7: 6 reserved ++//Bit 5: 0 reg_nr4_alp0_norm_gain // unsigned , default = 16 alp0 gain for sad norm, '32' as '1', dft = 1 ++#define NR4_MCNR_ALP1_AND_BET0_REG (0x2dc2) ++#define P_NR4_MCNR_ALP1_AND_BET0_REG (volatile unsigned int *)((0x2dc2 << 2) + 0xff900000) ++//Bit 31:26 reserved ++//Bit 25:24 reg_nr4_alp1_norm_mode // unsigned , default = 3 alp1 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3 ++//Bit 23:22 reserved ++//Bit 21:16 reg_nr4_alp1_norm_gain // unsigned , default = 3 alp1 gain for sad norm, '32' as '1', dft = 1 ++//Bit 15:10 reserved ++//Bit 9: 8 reg_nr4_bet0_norm_mode // unsigned , default = 3 bet0 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3 ++//Bit 7: 6 reserved ++//Bit 5: 0 reg_nr4_bet0_norm_gain // unsigned , default = 8 bet0 gain for sad norm, '32' as '1', dft = 1 ++#define NR4_MCNR_BET1_AND_BET2_REG (0x2dc3) ++#define P_NR4_MCNR_BET1_AND_BET2_REG (volatile unsigned int *)((0x2dc3 << 2) + 0xff900000) ++//Bit 31:26 reserved ++//Bit 25:24 reg_nr4_bet1_norm_mode // unsigned , default = 3 bet1 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3 ++//Bit 23:22 reserved ++//Bit 21:16 reg_nr4_bet1_norm_gain // unsigned , default = 8 bet1 gain for sad norm, '32' as '1', dft = 1 ++//Bit 15:10 reserved ++//Bit 9: 8 reg_nr4_bet2_norm_mode // unsigned , default = 0 bet2 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3 ++//Bit 7: 6 reserved ++//Bit 5: 0 reg_nr4_bet2_norm_gain // unsigned , default = 16 bet2 gain for sad norm, '32' as '1', dft = 1 ++#define NR4_MCNR_AC_DC_CRTL (0x2dc4) ++#define P_NR4_MCNR_AC_DC_CRTL (volatile unsigned int *)((0x2dc4 << 2) + 0xff900000) ++//Bit 31:16 reserved ++//Bit 15:12 reserved ++//Bit 11 reg_nr4_dc_mode // unsigned , default = 1 mode for dc selection,0: Y_lpf, 1: Y_lpf + (U_Lpf+V_lpf)/2, ++//Bit 10 reg_nr4_ac_mode // unsigned , default = 1 mode for ac selection, 0: Y_abs_dif, 1: Y_abs_dif + (U_abs_dif + V_abs_dif)/2 ++//Bit 9 reg_nr4_dc_sel // unsigned , default = 0 selection mode for dc value, 0: 3x5, 1: 5x5, dft = 1 ++//Bit 8 reg_nr4_ac_sel // unsigned , default = 0 selection mode for ac value, 0: 3x5, 1: 5x5, dft = 1 ++//Bit 7 reserved ++//Bit 6: 4 reg_nr4_dc_shft // unsigned , default = 2 right shift for dc value, dft = 2 ++//Bit 3 reserved ++//Bit 2: 0 reg_nr4_ac_shft // unsigned , default = 0 right shift for ac value, dft = 2 ++#define NR4_MCNR_CM_CTRL0 (0x2dc5) ++#define P_NR4_MCNR_CM_CTRL0 (volatile unsigned int *)((0x2dc5 << 2) + 0xff900000) ++//Bit 31:29 reserved ++//Bit 28 reg_nr4_cm_skin_prc_bet0 // unsigned , default = 0 enable skin tone processing for mcnr bet0 calc., dft = 1 ++//Bit 27:26 reg_nr4_cm_chrm_sel // unsigned , default = 1 chrome selection for color match, 0: 1x1, 1: 3X3LPF, 2: 3x5LPF, 3: 5x5LPF for 5lines, 3x5LPF for 3lines, dft = 3 ++//Bit 25:24 reg_nr4_cm_luma_sel // unsigned , default = 1 luma selection for color match, 0: 1x1, 1: 3X3LPF, 2: 3x5LPF, 3: 5x5LPF for 5lines, 3x5LPF for 3lines, dft = 3 ++//Bit 23:21 reg_nr4_cm_skin_rshft_bet0 // unsigned , default = 3 right shift for bet0's skin color gains, dft = 3 ++//Bit 20 reg_nr4_cm_var_sel // unsigned , default = 1 variation selection for color match, 0: 3x5, 1: 5x5 for 5lines, 3x5 for 3lines, dft = 1 ++//Bit 19 reg_nr4_cm_green_prc_bet0 // unsigned , default = 1 enable green processing for mcnr bet0 calc., dft = 1 ++//Bit 18:16 reg_nr4_cm_green_rshft_bet0 // unsigned , default = 4 right shift for bet0's green color gains, dft = 4 ++//Bit 15:14 reg_nr4_preflt_mod // unsigned , default = 2 pre filter mode in mcnr, 0: mv pointed pixel, 1: bilater filter ++//Bit 13:12 reg_nr4_alp1_mode // unsigned , default = 1 mode for alpha1's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad ++//Bit 11:10 reserved ++//Bit 9: 8 reg_nr4_bet0_mode // unsigned , default = 0 mode for bet0's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad, else: (co sad) - (min sad) ++//Bit 7: 6 reserved ++//Bit 5: 4 reg_nr4_bet1_mode // unsigned , default = 2 mode for bet1's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad, else: (co sad) - (min sad) ++//Bit 3: 2 reserved ++//Bit 1: 0 reg_nr4_bet2_mode // unsigned , default = 1 mode for bet2's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad, else: (co sad) - (min sad) ++#define NR4_MCNR_CM_PRAM (0x2dc6) ++#define P_NR4_MCNR_CM_PRAM (volatile unsigned int *)((0x2dc6 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29 reg_nr4_cm_blue_prc_alp0 // unsigned , default = 1 enable blue processing for mcnr alpha0 calc., dft = 1 ++//Bit 28 reg_nr4_cm_blue_prc_alp1 // unsigned , default = 1 enable blue processing for mcnr alpha1 calc., dft = 1 ++//Bit 27 reg_nr4_cm_skin_prc_alp0 // unsigned , default = 1 enable skin tone processing for mcnr alpha0 calc., dft = 1 ++//Bit 26 reg_nr4_cm_green_prc_alp0 // unsigned , default = 1 enable green processing for mcnr alpha0 clac., dft = 1 ++//Bit 25 reg_nr4_cm_skin_prc_alp1 // unsigned , default = 1 enable skin tone processing for mcnr alpha0 calc., dft = 1 ++//Bit 24 reg_nr4_cm_green_prc_alp1 // unsigned , default = 1 enable green processing for mcnr alpha1 clac., dft = 1 ++//Bit 23:20 reg_nr4_cm_blue_hue_st // unsigned , default = 13 hue start of blue, dft = ++//Bit 19:16 reg_nr4_cm_blue_hue_ed // unsigned , default = 15 hue end of blue, dft = ++//Bit 15:12 reg_nr4_cm_green_hue_st // unsigned , default = 7 hue start of green, dft = ++//Bit 11: 8 reg_nr4_cm_green_hue_ed // unsigned , default = 10 hue end of green, dft = ++//Bit 7: 4 reg_nr4_cm_skin_hue_st // unsigned , default = 5 hue start of skin, dft = ++//Bit 3: 0 reg_nr4_cm_skin_hue_ed // unsigned , default = 6 hue end of skin, dft = ++#define NR4_MCNR_CM_RSHFT_ALP0 (0x2dc7) ++#define P_NR4_MCNR_CM_RSHFT_ALP0 (volatile unsigned int *)((0x2dc7 << 2) + 0xff900000) ++//Bit 31:28 reserved ++//Bit 27:25 reg_nr4_cm_blue_rshft_bet0 // unsigned , default = 5 right shift for bet0's blue color gains, dft = 5 ++//Bit 24 reg_nr4_cm_blue_prc_bet0 // unsigned , default = 1 enable blue processing for mcnr bet0 calc., dft = 1 ++//Bit 23 reserved ++//Bit 22:20 reg_nr4_cm_blue_rshft_alp0 // unsigned , default = 5 right shift for alpha0/1's blue color gains, dft = 5 ++//Bit 19 reserved ++//Bit 18:16 reg_nr4_cm_blue_rshft_alp1 // unsigned , default = 5 right shift for alpha0/1's blue color gains, dft = 5 ++//Bit 15 reserved ++//Bit 14:12 reg_nr4_cm_green_rshft_alp0 // unsigned , default = 4 right shift for alpha0/1's green color gains, dft = 4 ++//Bit 11 reserved ++//Bit 10: 8 reg_nr4_cm_green_rshft_alp1 // unsigned , default = 4 right shift for alpha0/1's green color gains, dft = 4 ++//Bit 7 reserved ++//Bit 6: 4 reg_nr4_cm_skin_rshft_alp0 // unsigned , default = 3 right shift for alpha0/1's skin color gains, dft = 3 ++//Bit 3 reserved ++//Bit 2: 0 reg_nr4_cm_skin_rshft_alp1 // unsigned , default = 3 right shift for alpha0/1's skin color gains, dft = 3 ++#define NR4_MCNR_BLUE_CENT (0x2dc8) ++#define P_NR4_MCNR_BLUE_CENT (volatile unsigned int *)((0x2dc8 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:16 reg_nr4_cm_blue_centx // unsigned , default = 157 x coordinate of center of blue, dft = ++//Bit 15: 8 reserved ++//Bit 7: 0 reg_nr4_cm_blue_centy // unsigned , default = 110 y coordinate of center of blue, dft = ++#define NR4_MCNR_BLUE_GAIN_PAR0 (0x2dc9) ++#define P_NR4_MCNR_BLUE_GAIN_PAR0 (volatile unsigned int *)((0x2dc9 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_cm_blue_gain_par0 // unsigned , default = 32 par0 for blue gain, dft = ++//Bit 23:16 reg_nr4_cm_blue_gain_par1 // unsigned , default = 255 par1 for blue gain, dft = ++//Bit 15: 8 reg_nr4_cm_blue_gain_par2 // unsigned , default = 4 par2 for blue gain, dft = ++//Bit 7: 0 reg_nr4_cm_blue_gain_par3 // unsigned , default = 32 par3 for blue gain, dft = ++#define NR4_MCNR_BLUE_GAIN_PAR1 (0x2dca) ++#define P_NR4_MCNR_BLUE_GAIN_PAR1 (volatile unsigned int *)((0x2dca << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:16 reg_nr4_cm_blue_gain_par4 // unsigned , default = 32 par4 for blue gain, dft = ++//Bit 15: 8 reg_nr4_cm_blue_gain_par5 // unsigned , default = 32 par5 for blue gain, dft = ++//Bit 7: 0 reg_nr4_cm_blue_gain_par6 // unsigned , default = 0 par6 for blue gain, dft = ++#define NR4_MCNR_CM_BLUE_CLIP0 (0x2dcb) ++#define P_NR4_MCNR_CM_BLUE_CLIP0 (volatile unsigned int *)((0x2dcb << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:16 reg_nr4_cm_blue_luma_min // unsigned , default = 40 luma min for blue color matching, dft = ++//Bit 15: 8 reserved ++//Bit 7: 0 reg_nr4_cm_blue_luma_max // unsigned , default = 180 luma max for blue color matching, dft = ++#define NR4_MCNR_CM_BLUE_CLIP1 (0x2dcc) ++#define P_NR4_MCNR_CM_BLUE_CLIP1 (volatile unsigned int *)((0x2dcc << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_cm_blue_sat_min // unsigned , default = 5 saturation min for blue color matching, dft = ++//Bit 23:16 reg_nr4_cm_blue_sat_max // unsigned , default = 255 saturation max for blue color matching, dft = ++//Bit 15: 8 reg_nr4_cm_blue_var_min // unsigned , default = 0 variation min for blue color matching, dft = ++//Bit 7: 0 reg_nr4_cm_blue_var_max // unsigned , default = 12 variation max for blue color matching, dft = ++#define NR4_MCNR_GREEN_CENT (0x2dcd) ++#define P_NR4_MCNR_GREEN_CENT (volatile unsigned int *)((0x2dcd << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:16 reg_nr4_cm_green_centx // unsigned , default = 114 x coordinate of center of green, dft = ++//Bit 15: 8 reserved ++//Bit 7: 0 reg_nr4_cm_green_centy // unsigned , default = 126 y coordinate of center of green, dft = ++#define NR4_MCNR_GREEN_GAIN_PAR0 (0x2dce) ++#define P_NR4_MCNR_GREEN_GAIN_PAR0 (volatile unsigned int *)((0x2dce << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_cm_green_gain_par0 // unsigned , default = 16 par0 for green gain, dft = ++//Bit 23:16 reg_nr4_cm_green_gain_par1 // unsigned , default = 255 par1 for green gain, dft = ++//Bit 15: 8 reg_nr4_cm_green_gain_par2 // unsigned , default = 255 par2 for green gain, dft = ++//Bit 7: 0 reg_nr4_cm_green_gain_par3 // unsigned , default = 16 par3 for green gain, dft = ++#define NR4_MCNR_GREEN_GAIN_PAR1 (0x2dcf) ++#define P_NR4_MCNR_GREEN_GAIN_PAR1 (volatile unsigned int *)((0x2dcf << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:16 reg_nr4_cm_green_gain_par4 // unsigned , default = 16 par4 for green gain, dft = ++//Bit 15: 8 reg_nr4_cm_green_gain_par5 // unsigned , default = 128 par5 for green gain, dft = ++//Bit 7: 0 reg_nr4_cm_green_gain_par6 // unsigned , default = 0 par6 for green gain, dft = ++#define NR4_MCNR_GREEN_CLIP0 (0x2dd0) ++#define P_NR4_MCNR_GREEN_CLIP0 (volatile unsigned int *)((0x2dd0 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:16 reg_nr4_cm_green_luma_min // unsigned , default = 40 luma min for green color matching, dft = ++//Bit 15: 8 reserved ++//Bit 7: 0 reg_nr4_cm_green_luma_max // unsigned , default = 160 luma max for green color matching, dft = ++#define NR4_MCNR_GREEN_CLIP2 (0x2dd1) ++#define P_NR4_MCNR_GREEN_CLIP2 (volatile unsigned int *)((0x2dd1 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_cm_green_sat_min // unsigned , default = 4 saturation min for green color matching, dft = ++//Bit 23:16 reg_nr4_cm_green_sat_max // unsigned , default = 255 saturation max for green color matching, dft = ++//Bit 15: 8 reg_nr4_cm_green_var_min // unsigned , default = 0 variation min for green color matching, dft = ++//Bit 7: 0 reg_nr4_cm_green_var_max // unsigned , default = 12 variation max for green color matching, dft = ++#define NR4_MCNR_SKIN_CENT (0x2dd2) ++#define P_NR4_MCNR_SKIN_CENT (volatile unsigned int *)((0x2dd2 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:16 reg_nr4_cm_skin_centx // unsigned , default = 112 x coordinate of center of skin tone, dft = ++//Bit 15: 8 reserved ++//Bit 7: 0 reg_nr4_cm_skin_centy // unsigned , default = 149 y coordinate of center of skin tone, dft = ++#define NR4_MCNR_SKIN_GAIN_PAR0 (0x2dd3) ++#define P_NR4_MCNR_SKIN_GAIN_PAR0 (volatile unsigned int *)((0x2dd3 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_cm_skin_gain_par0 // unsigned , default = 20 par0 for skin gain, dft = ++//Bit 23:16 reg_nr4_cm_skin_gain_par1 // unsigned , default = 255 par1 for skin gain, dft = ++//Bit 15: 8 reg_nr4_cm_skin_gain_par2 // unsigned , default = 255 par2 for skin gain, dft = ++//Bit 7: 0 reg_nr4_cm_skin_gain_par3 // unsigned , default = 8 par3 for skin gain, dft = ++#define NR4_MCNR_SKIN_GAIN_PAR1 (0x2dd4) ++#define P_NR4_MCNR_SKIN_GAIN_PAR1 (volatile unsigned int *)((0x2dd4 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:16 reg_nr4_cm_skin_gain_par4 // unsigned , default = 8 par4 for skin gain, dft = ++//Bit 15: 8 reg_nr4_cm_skin_gain_par5 // unsigned , default = 128 par5 for skin gain, dft = ++//Bit 7: 0 reg_nr4_cm_skin_gain_par6 // unsigned , default = 0 par6 for skin gain, dft = ++#define NR4_MCNR_SKIN_CLIP0 (0x2dd5) ++#define P_NR4_MCNR_SKIN_CLIP0 (volatile unsigned int *)((0x2dd5 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:16 reg_nr4_cm_skin_luma_min // unsigned , default = 40 luma min for skin color matching, dft = ++//Bit 15: 8 reserved ++//Bit 7: 0 reg_nr4_cm_skin_luma_max // unsigned , default = 180 luma max for skin color matching, dft = ++#define NR4_MCNR_SKIN_CLIP1 (0x2dd6) ++#define P_NR4_MCNR_SKIN_CLIP1 (volatile unsigned int *)((0x2dd6 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_cm_skin_sat_min // unsigned , default = 5 saturation min for skin color matching, dft = ++//Bit 23:16 reg_nr4_cm_skin_sat_max // unsigned , default = 255 saturation max for skin color matching, dft = ++//Bit 15: 8 reg_nr4_cm_skin_var_min // unsigned , default = 0 variation min for skin color matching, dft = ++//Bit 7: 0 reg_nr4_cm_skin_var_max // unsigned , default = 12 variation max for skin color matching, dft = ++#define NR4_MCNR_ALP1_GLB_CTRL (0x2dd7) ++#define P_NR4_MCNR_ALP1_GLB_CTRL (volatile unsigned int *)((0x2dd7 << 2) + 0xff900000) ++//Bit 31 reg_nr4_alp1_glb_gain_en // unsigned , default = 0 alp1 adjust by global gain, dft = 1 ++//Bit 30:28 reg_nr4_alp1_glb_gain_lsft // unsigned , default = 6 alp1 left shift before combine with global gain ++//Bit 27 reg_nr4_bet0_glb_gain_en // unsigned , default = 1 bet0 adjust by global gain, dft = 1 ++//Bit 26:24 reg_nr4_bet0_glb_gain_lsft // unsigned , default = 6 bet1 left shift before combine with global gain ++//Bit 23 reg_nr4_bet1_glb_gain_en // unsigned , default = 0 bet1 adjust by global gain, dft = 0 ++//Bit 22:20 reg_nr4_bet1_glb_gain_lsft // unsigned , default = 6 bet1 left shift before combine with global gain ++//Bit 19 reg_nr4_bet2_glb_gain_en // unsigned , default = 1 bet2 adjust by global gain, dft = 1 ++//Bit 18:16 reg_nr4_bet2_glb_gain_lsft // unsigned , default = 6 bet2 left shift before combine with global gain ++//Bit 15 reg_nr4_alp1_ac_en // unsigned , default = 1 alp1 adjust by ac, dft = 1 ++//Bit 14:12 reg_nr4_alp1_ac_lsft // unsigned , default = 5 alp1 left shift before combine with ac ++//Bit 11 reg_nr4_bet0_ac_en // unsigned , default = 0 bet0 adjust by ac, dft = 1 ++//Bit 10: 8 reg_nr4_bet0_ac_lsft // unsigned , default = 5 bet0 left shift before combine with ac ++//Bit 7 reg_nr4_bet1_ac_en // unsigned , default = 0 bet1 adjust by ac, dft = 1 ++//Bit 6: 4 reg_nr4_bet1_ac_lsft // unsigned , default = 5 bet1 left shift before combine with ac ++//Bit 3 reg_nr4_bet2_ac_en // unsigned , default = 0 bet2 adjust by ac, dft = 1 ++//Bit 2: 0 reg_nr4_bet2_ac_lsft // unsigned , default = 5 bet2 left shift before combine with ac ++#define NR4_MCNR_DC2NORM_LUT0 (0x2dd8) ++#define P_NR4_MCNR_DC2NORM_LUT0 (volatile unsigned int *)((0x2dd8 << 2) + 0xff900000) ++//Bit 31:29 reserved ++//Bit 28:24 reg_nr4_dc2norm_lut0 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft = ++//Bit 23:21 reserved ++//Bit 20:16 reg_nr4_dc2norm_lut1 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft = ++//Bit 15:13 reserved ++//Bit 12: 8 reg_nr4_dc2norm_lut2 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft = ++//Bit 7: 5 reserved ++//Bit 4: 0 reg_nr4_dc2norm_lut3 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft = ++#define NR4_MCNR_DC2NORM_LUT1 (0x2dd9) ++#define P_NR4_MCNR_DC2NORM_LUT1 (volatile unsigned int *)((0x2dd9 << 2) + 0xff900000) ++//Bit 31:29 reserved ++//Bit 28:24 reg_nr4_dc2norm_lut4 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft = ++//Bit 23:21 reserved ++//Bit 20:16 reg_nr4_dc2norm_lut5 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft = ++//Bit 15:13 reserved ++//Bit 12: 8 reg_nr4_dc2norm_lut6 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft = ++//Bit 7: 5 reserved ++//Bit 4: 0 reg_nr4_dc2norm_lut7 // unsigned , default = 12 normal 0~16, dc to norm for alpha adjust, dft = ++#define NR4_MCNR_DC2NORM_LUT2 (0x2dda) ++#define P_NR4_MCNR_DC2NORM_LUT2 (volatile unsigned int *)((0x2dda << 2) + 0xff900000) ++//Bit 31: 5 reserved ++//Bit 4: 0 reg_nr4_dc2norm_lut8 // unsigned , default = 8 normal 0~16, dc to norm for alpha adjust, dft = ++#define NR4_MCNR_AC2NORM_LUT0 (0x2ddb) ++#define P_NR4_MCNR_AC2NORM_LUT0 (volatile unsigned int *)((0x2ddb << 2) + 0xff900000) ++//Bit 31:29 reserved ++//Bit 28:24 reg_nr4_ac2norm_lut0 // unsigned , default = 2 normal 0~16, ac to norm for alpha adjust, dft = ++//Bit 23:21 reserved ++//Bit 20:16 reg_nr4_ac2norm_lut1 // unsigned , default = 16 normal 0~16, ac to norm for alpha adjust, dft = ++//Bit 15:13 reserved ++//Bit 12: 8 reg_nr4_ac2norm_lut2 // unsigned , default = 16 normal 0~16, ac to norm for alpha adjust, dft = ++//Bit 7: 5 reserved ++//Bit 4: 0 reg_nr4_ac2norm_lut3 // unsigned , default = 12 normal 0~16, ac to norm for alpha adjust, dft = ++#define NR4_MCNR_AC2NORM_LUT1 (0x2ddc) ++#define P_NR4_MCNR_AC2NORM_LUT1 (volatile unsigned int *)((0x2ddc << 2) + 0xff900000) ++//Bit 31:29 reserved ++//Bit 28:24 reg_nr4_ac2norm_lut4 // unsigned , default = 4 normal 0~16, ac to norm for alpha adjust, dft = ++//Bit 23:21 reserved ++//Bit 20:16 reg_nr4_ac2norm_lut5 // unsigned , default = 2 normal 0~16, ac to norm for alpha adjust, dft = ++//Bit 15:13 reserved ++//Bit 12: 8 reg_nr4_ac2norm_lut6 // unsigned , default = 1 normal 0~16, ac to norm for alpha adjust, dft = ++//Bit 7: 5 reserved ++//Bit 4: 0 reg_nr4_ac2norm_lut7 // unsigned , default = 1 normal 0~16, ac to norm for alpha adjust, dft = ++#define NR4_MCNR_AC2NORM_LUT2 (0x2ddd) ++#define P_NR4_MCNR_AC2NORM_LUT2 (volatile unsigned int *)((0x2ddd << 2) + 0xff900000) ++//Bit 31: 5 reserved ++//Bit 4: 0 reg_nr4_ac2norm_lut8 // unsigned , default = 1 normal 0~16, ac to norm for alpha adjust, dft = ++#define NR4_MCNR_SAD2ALP0_LUT0 (0x2dde) ++#define P_NR4_MCNR_SAD2ALP0_LUT0 (volatile unsigned int *)((0x2dde << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2alp0_lut0 // unsigned , default = 255 sad to alpha0 for temporal pixel value, dft = 255 ++//Bit 23:16 reg_nr4_sad2alp0_lut1 // unsigned , default = 252 sad to alpha0 for temporal pixel value, dft = 252 ++//Bit 15: 8 reg_nr4_sad2alp0_lut2 // unsigned , default = 249 sad to alpha0 for temporal pixel value, dft = 249 ++//Bit 7: 0 reg_nr4_sad2alp0_lut3 // unsigned , default = 235 sad to alpha0 for temporal pixel value, dft = 70 ++#define NR4_MCNR_SAD2ALP0_LUT1 (0x2ddf) ++#define P_NR4_MCNR_SAD2ALP0_LUT1 (volatile unsigned int *)((0x2ddf << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2alp0_lut4 // unsigned , default = 185 sad to alpha0 for temporal pixel value, dft = 12 ++//Bit 23:16 reg_nr4_sad2alp0_lut5 // unsigned , default = 70 sad to alpha0 for temporal pixel value, dft = 1 ++//Bit 15: 8 reg_nr4_sad2alp0_lut6 // unsigned , default = 14 sad to alpha0 for temporal pixel value, dft = 0 ++//Bit 7: 0 reg_nr4_sad2alp0_lut7 // unsigned , default = 1 sad to alpha0 for temporal pixel value, dft = 0 ++#define NR4_MCNR_SAD2ALP0_LUT2 (0x2de0) ++#define P_NR4_MCNR_SAD2ALP0_LUT2 (volatile unsigned int *)((0x2de0 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2alp0_lut8 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0 ++//Bit 23:16 reg_nr4_sad2alp0_lut9 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0 ++//Bit 15: 8 reg_nr4_sad2alp0_lut10 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0 ++//Bit 7: 0 reg_nr4_sad2alp0_lut11 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0 ++#define NR4_MCNR_SAD2ALP0_LUT3 (0x2de1) ++#define P_NR4_MCNR_SAD2ALP0_LUT3 (volatile unsigned int *)((0x2de1 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2alp0_lut12 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0 ++//Bit 23:16 reg_nr4_sad2alp0_lut13 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0 ++//Bit 15: 8 reg_nr4_sad2alp0_lut14 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0 ++//Bit 7: 0 reg_nr4_sad2alp0_lut15 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0 ++#define NR4_MCNR_SAD2ALP1_LUT0 (0x2de2) ++#define P_NR4_MCNR_SAD2ALP1_LUT0 (volatile unsigned int *)((0x2de2 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2alp1_lut0 // unsigned , default = 192 sad to alpha1 for temporal blending, dft = 128 ++//Bit 23:16 reg_nr4_sad2alp1_lut1 // unsigned , default = 160 sad to alpha1 for temporal blending, dft = 128 ++//Bit 15: 8 reg_nr4_sad2alp1_lut2 // unsigned , default = 128 sad to alpha1 for temporal blending, dft = 128 ++//Bit 7: 0 reg_nr4_sad2alp1_lut3 // unsigned , default = 96 sad to alpha1 for temporal blending, dft = 64 ++#define NR4_MCNR_SAD2ALP1_LUT1 (0x2de3) ++#define P_NR4_MCNR_SAD2ALP1_LUT1 (volatile unsigned int *)((0x2de3 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2alp1_lut4 // unsigned , default = 64 sad to alpha1 for temporal blending, dft = 64 ++//Bit 23:16 reg_nr4_sad2alp1_lut5 // unsigned , default = 32 sad to alpha1 for temporal blending, dft = 128 ++//Bit 15: 8 reg_nr4_sad2alp1_lut6 // unsigned , default = 16 sad to alpha1 for temporal blending, dft = 255 ++//Bit 7: 0 reg_nr4_sad2alp1_lut7 // unsigned , default = 8 sad to alpha1 for temporal blending, dft = 255 ++#define NR4_MCNR_SAD2ALP1_LUT2 (0x2de4) ++#define P_NR4_MCNR_SAD2ALP1_LUT2 (volatile unsigned int *)((0x2de4 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2alp1_lut8 // unsigned , default = 4 sad to alpha1 for temporal blending, dft = 255 ++//Bit 23:16 reg_nr4_sad2alp1_lut9 // unsigned , default = 0 sad to alpha1 for temporal blending, dft = 255 ++//Bit 15: 8 reg_nr4_sad2alp1_lut10 // unsigned , default = 16 sad to alpha1 for temporal blending, dft = 255 ++//Bit 7: 0 reg_nr4_sad2alp1_lut11 // unsigned , default = 64 sad to alpha1 for temporal blending, dft = 255 ++#define NR4_MCNR_SAD2ALP1_LUT3 (0x2de5) ++#define P_NR4_MCNR_SAD2ALP1_LUT3 (volatile unsigned int *)((0x2de5 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2alp1_lut12 // unsigned , default = 96 sad to alpha1 for temporal blending, dft = 255 ++//Bit 23:16 reg_nr4_sad2alp1_lut13 // unsigned , default = 224 sad to alpha1 for temporal blending, dft = 255 ++//Bit 15: 8 reg_nr4_sad2alp1_lut14 // unsigned , default = 255 sad to alpha1 for temporal blending, dft = 255 ++//Bit 7: 0 reg_nr4_sad2alp1_lut15 // unsigned , default = 255 sad to alpha1 for temporal blending, dft = 255 ++#define NR4_MCNR_SAD2BET0_LUT0 (0x2de6) ++#define P_NR4_MCNR_SAD2BET0_LUT0 (volatile unsigned int *)((0x2de6 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2bet0_lut0 // unsigned , default = 0 sad to beta0 for tnr and mcnr blending, dft = 0 ++//Bit 23:16 reg_nr4_sad2bet0_lut1 // unsigned , default = 2 sad to beta0 for tnr and mcnr blending, dft = 2 ++//Bit 15: 8 reg_nr4_sad2bet0_lut2 // unsigned , default = 4 sad to beta0 for tnr and mcnr blending, dft = 4 ++//Bit 7: 0 reg_nr4_sad2bet0_lut3 // unsigned , default = 8 sad to beta0 for tnr and mcnr blending, dft = 8 ++#define NR4_MCNR_SAD2BET0_LUT1 (0x2de7) ++#define P_NR4_MCNR_SAD2BET0_LUT1 (volatile unsigned int *)((0x2de7 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2bet0_lut4 // unsigned , default = 16 sad to beta0 for tnr and mcnr blending, dft = 16 ++//Bit 23:16 reg_nr4_sad2bet0_lut5 // unsigned , default = 32 sad to beta0 for tnr and mcnr blending, dft = 32 ++//Bit 15: 8 reg_nr4_sad2bet0_lut6 // unsigned , default = 48 sad to beta0 for tnr and mcnr blending, dft = 48 ++//Bit 7: 0 reg_nr4_sad2bet0_lut7 // unsigned , default = 64 sad to beta0 for tnr and mcnr blending, dft = 64 ++#define NR4_MCNR_SAD2BET0_LUT2 (0x2de8) ++#define P_NR4_MCNR_SAD2BET0_LUT2 (volatile unsigned int *)((0x2de8 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2bet0_lut8 // unsigned , default = 80 sad to beta0 for tnr and mcnr blending, dft = 80 ++//Bit 23:16 reg_nr4_sad2bet0_lut9 // unsigned , default = 96 sad to beta0 for tnr and mcnr blending, dft = 96 ++//Bit 15: 8 reg_nr4_sad2bet0_lut10 // unsigned , default = 112 sad to beta0 for tnr and mcnr blending, dft = 112 ++//Bit 7: 0 reg_nr4_sad2bet0_lut11 // unsigned , default = 128 sad to beta0 for tnr and mcnr blending, dft = 128 ++#define NR4_MCNR_SAD2BET0_LUT3 (0x2de9) ++#define P_NR4_MCNR_SAD2BET0_LUT3 (volatile unsigned int *)((0x2de9 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2bet0_lut12 // unsigned , default = 196 sad to beta0 for tnr and mcnr blending, dft = 160 ++//Bit 23:16 reg_nr4_sad2bet0_lut13 // unsigned , default = 224 sad to beta0 for tnr and mcnr blending, dft = 192 ++//Bit 15: 8 reg_nr4_sad2bet0_lut14 // unsigned , default = 255 sad to beta0 for tnr and mcnr blending, dft = 224 ++//Bit 7: 0 reg_nr4_sad2bet0_lut15 // unsigned , default = 255 sad to beta0 for tnr and mcnr blending, dft = 255 ++#define NR4_MCNR_SAD2BET1_LUT0 (0x2dea) ++#define P_NR4_MCNR_SAD2BET1_LUT0 (volatile unsigned int *)((0x2dea << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2bet1_lut0 // unsigned , default = 0 sad to beta1 for deghost blending, dft = 0 ++//Bit 23:16 reg_nr4_sad2bet1_lut1 // unsigned , default = 2 sad to beta1 for deghost blending, dft = 2 ++//Bit 15: 8 reg_nr4_sad2bet1_lut2 // unsigned , default = 4 sad to beta1 for deghost blending, dft = 4 ++//Bit 7: 0 reg_nr4_sad2bet1_lut3 // unsigned , default = 8 sad to beta1 for deghost blending, dft = 8 ++#define NR4_MCNR_SAD2BET1_LUT1 (0x2deb) ++#define P_NR4_MCNR_SAD2BET1_LUT1 (volatile unsigned int *)((0x2deb << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2bet1_lut4 // unsigned , default = 16 sad to beta1 for deghost blending, dft = 16 ++//Bit 23:16 reg_nr4_sad2bet1_lut5 // unsigned , default = 32 sad to beta1 for deghost blending, dft = 32 ++//Bit 15: 8 reg_nr4_sad2bet1_lut6 // unsigned , default = 48 sad to beta1 for deghost blending, dft = 48 ++//Bit 7: 0 reg_nr4_sad2bet1_lut7 // unsigned , default = 64 sad to beta1 for deghost blending, dft = 64 ++#define NR4_MCNR_SAD2BET1_LUT2 (0x2dec) ++#define P_NR4_MCNR_SAD2BET1_LUT2 (volatile unsigned int *)((0x2dec << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2bet1_lut8 // unsigned , default = 80 sad to beta1 for deghost blending, dft = 80 ++//Bit 23:16 reg_nr4_sad2bet1_lut9 // unsigned , default = 96 sad to beta1 for deghost blending, dft = 96 ++//Bit 15: 8 reg_nr4_sad2bet1_lut10 // unsigned , default = 112 sad to beta1 for deghost blending, dft = 112 ++//Bit 7: 0 reg_nr4_sad2bet1_lut11 // unsigned , default = 128 sad to beta1 for deghost blending, dft = 128 ++#define NR4_MCNR_SAD2BET1_LUT3 (0x2ded) ++#define P_NR4_MCNR_SAD2BET1_LUT3 (volatile unsigned int *)((0x2ded << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2bet1_lut12 // unsigned , default = 160 sad to beta1 for deghost blending, dft = 160 ++//Bit 23:16 reg_nr4_sad2bet1_lut13 // unsigned , default = 192 sad to beta1 for deghost blending, dft = 192 ++//Bit 15: 8 reg_nr4_sad2bet1_lut14 // unsigned , default = 224 sad to beta1 for deghost blending, dft = 224 ++//Bit 7: 0 reg_nr4_sad2bet1_lut15 // unsigned , default = 255 sad to beta1 for deghost blending, dft = 255 ++#define NR4_MCNR_SAD2BET2_LUT0 (0x2dee) ++#define P_NR4_MCNR_SAD2BET2_LUT0 (volatile unsigned int *)((0x2dee << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2bet2_lut0 // unsigned , default = 0 sad to beta2 for snr and mcnr blending, dft = 0 ++//Bit 23:16 reg_nr4_sad2bet2_lut1 // unsigned , default = 1 sad to beta2 for snr and mcnr blending, dft = 2 ++//Bit 15: 8 reg_nr4_sad2bet2_lut2 // unsigned , default = 2 sad to beta2 for snr and mcnr blending, dft = 4 ++//Bit 7: 0 reg_nr4_sad2bet2_lut3 // unsigned , default = 4 sad to beta2 for snr and mcnr blending, dft = 8 ++#define NR4_MCNR_SAD2BET2_LUT1 (0x2def) ++#define P_NR4_MCNR_SAD2BET2_LUT1 (volatile unsigned int *)((0x2def << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2bet2_lut4 // unsigned , default = 8 sad to beta2 for snr and mcnr blending, dft = 16 ++//Bit 23:16 reg_nr4_sad2bet2_lut5 // unsigned , default = 16 sad to beta2 for snr and mcnr blending, dft = 32 ++//Bit 15: 8 reg_nr4_sad2bet2_lut6 // unsigned , default = 32 sad to beta2 for snr and mcnr blending, dft = 48 ++//Bit 7: 0 reg_nr4_sad2bet2_lut7 // unsigned , default = 48 sad to beta2 for snr and mcnr blending, dft = 64 ++#define NR4_MCNR_SAD2BET2_LUT2 (0x2df0) ++#define P_NR4_MCNR_SAD2BET2_LUT2 (volatile unsigned int *)((0x2df0 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2bet2_lut8 // unsigned , default = 64 sad to beta2 for snr and mcnr blending, dft = 80 ++//Bit 23:16 reg_nr4_sad2bet2_lut9 // unsigned , default = 80 sad to beta2 for snr and mcnr blending, dft = 96 ++//Bit 15: 8 reg_nr4_sad2bet2_lut10 // unsigned , default = 96 sad to beta2 for snr and mcnr blending, dft = 112 ++//Bit 7: 0 reg_nr4_sad2bet2_lut11 // unsigned , default = 112 sad to beta2 for snr and mcnr blending, dft = 128 ++#define NR4_MCNR_SAD2BET2_LUT3 (0x2df1) ++#define P_NR4_MCNR_SAD2BET2_LUT3 (volatile unsigned int *)((0x2df1 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_sad2bet2_lut12 // unsigned , default = 128 sad to beta2 for snr and mcnr blending, dft = 160 ++//Bit 23:16 reg_nr4_sad2bet2_lut13 // unsigned , default = 160 sad to beta2 for snr and mcnr blending, dft = 192 ++//Bit 15: 8 reg_nr4_sad2bet2_lut14 // unsigned , default = 224 sad to beta2 for snr and mcnr blending, dft = 224 ++//Bit 7: 0 reg_nr4_sad2bet2_lut15 // unsigned , default = 255 sad to beta2 for snr and mcnr blending, dft = 255 ++#define NR4_MCNR_RO_U_SUM (0x2df2) ++#define P_NR4_MCNR_RO_U_SUM (volatile unsigned int *)((0x2df2 << 2) + 0xff900000) ++//Bit 31: 0 ro_nr4_u_sum // unsigned , default = 0 sum of U of current field/frame ++#define NR4_MCNR_RO_V_SUM (0x2df3) ++#define P_NR4_MCNR_RO_V_SUM (volatile unsigned int *)((0x2df3 << 2) + 0xff900000) ++//Bit 31: 0 ro_nr4_v_sum // unsigned , default = 0 sum of V of current field/frame ++#define NR4_MCNR_RO_GRDU_SUM (0x2df4) ++#define P_NR4_MCNR_RO_GRDU_SUM (volatile unsigned int *)((0x2df4 << 2) + 0xff900000) ++//Bit 31: 0 ro_nr4_grdu_sum // unsigned , default = 0 sum of gradient U of current field/frame ++#define NR4_MCNR_RO_GRDV_SUM (0x2df5) ++#define P_NR4_MCNR_RO_GRDV_SUM (volatile unsigned int *)((0x2df5 << 2) + 0xff900000) ++//Bit 31: 0 ro_nr4_grdv_sum // unsigned , default = 0 sum of gradient V of current field/frame ++#define NR4_TOP_CTRL (0x2dff) ++#define P_NR4_TOP_CTRL (volatile unsigned int *)((0x2dff << 2) + 0xff900000) ++//Bit 31:20 reg_gclk_ctrl // unsigned , default = 0 ++//Bit 19 reserved ++//Bit 18 reg_nr4_mcnr_en // unsigned , default = 1 ncnr enable or bypass, dft = 1 ++//Bit 17 reg_nr2_en // unsigned , default = 1 nr2 enable, dft = 1 ++//Bit 16 reg_nr4_en // unsigned , default = 1 nr4 enable, dft = 1 ++//Bit 15 reg_nr2_proc_en // unsigned , default = 1 ++//Bit 14 reg_det3d_en // unsigned , default = 1 ++//Bit 13 di_polar_en // unsigned , default = 1 do does not have in C ++//Bit 12 reg_cfr_enable // unsigned , default = 0 0-disable; 1:enable ++//Bit 11: 9 reg_3dnr_enable_l // unsigned , default = 7 b0: Y b1:U b2:V ++//Bit 8: 6 reg_3dnr_enable_r // unsigned , default = 7 b0: Y b1:U b2:V ++//Bit 5 reg_nr4_lnbuf_ctrl // unsigned , default = 1 line buf ctrl for nr4: 0, 3lines, 1, 5lines, dft = 1 ++//Bit 4 reg_nr4_snr2_en // unsigned , default = 0 snr2 enable, 0: use old snr, 1: use new snr2, dft = 1 ++//Bit 3 reg_nr4_scene_change_en // unsigned , default = 1 enable scene change proc. dft = 1 ++//Bit 2 nr2_sw_en // unsigned , default = 1 do does not have in C ++//Bit 1 reserved ++//Bit 0 reg_nr4_scene_change_flg // unsigned , default = 0 flags for scene change, dft = 0 ++//========== nr4_mcnr_regs register end ==========// ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: nr4_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: dnr_regs.h ++// ++//======================================================================== ++// VI_HIST_SPL register (16'h2e00 - 16'h2eff) ++//======================================================================== ++//`define VI_HIST_SPL_VCBUS_BASE 8'h2e ++// ++// Reading file: vi_hist_spl_reg.h ++// ++// synopsys translate_off ++// synopsys translate_on ++// ---------------------------- ++// VI_HIST_SPL 0x2e ++// ---------------------------- ++// ----------------------------------------------- ++// CBUS_BASE: VI_HIST_SPL_VCBUS_BASE = 0x2e ++// ----------------------------------------------- ++//BIT 14: 34bin only, 0&255 and other 32bins ++//Bit 13:11 hist_din_sel, 00: from vdin0 dout, 1: from vdin1, 2: from nr dout, 3: di output, 4: vpp output, 5: vd1_din, 6: vd2_din, 7:osd1_dout ++//Bit 10:8 hist_din_comp_mux, mux of [29:22], [19:12], [9:2] for hist detect ++//Bit 7:5 hist_dnlp_low the real pixels in each bins got by VI_DNLP_HISTXX should multiple with 2^(dnlp_low+3) ++//Bit 3:2 hist_din_sel the source used for hist statistics. 00: from matrix0 dout, 01: from vsc_dout, 10: from matrix1 dout, 11: form matrix1 din ++//Bit 1 hist_win_en 1'b0: hist used for full picture; 1'b1: hist used for pixels within hist window ++//Bit 0 hist_spl_en 1'b0: disable hist readback; 1'b1: enable hist readback ++#define VI_HIST_CTRL (0x2e00) ++#define P_VI_HIST_CTRL (volatile unsigned int *)((0x2e00 << 2) + 0xff900000) ++//Bit 28:16 hist_hstart horizontal start value to define hist window ++//Bit 12:0 hist_hend horizontal end value to define hist window ++#define VI_HIST_H_START_END (0x2e01) ++#define P_VI_HIST_H_START_END (volatile unsigned int *)((0x2e01 << 2) + 0xff900000) ++//Bit 28:16 hist_vstart vertical start value to define hist window ++//Bit 12:0 hist_vend vertical end value to define hist window ++#define VI_HIST_V_START_END (0x2e02) ++#define P_VI_HIST_V_START_END (volatile unsigned int *)((0x2e02 << 2) + 0xff900000) ++//Bit 15:8 hist_max maximum value ++//Bit 7:0 hist_min minimum value ++//read only ++#define VI_HIST_MAX_MIN (0x2e03) ++#define P_VI_HIST_MAX_MIN (volatile unsigned int *)((0x2e03 << 2) + 0xff900000) ++//Bit 31:0 hist_spl_rd ++//counts for the total luma value ++//read only ++#define VI_HIST_SPL_VAL (0x2e04) ++#define P_VI_HIST_SPL_VAL (volatile unsigned int *)((0x2e04 << 2) + 0xff900000) ++//Bit 21:0 hist_spl_pixel_count ++//counts for the total calculated pixels ++//read only ++#define VI_HIST_SPL_PIX_CNT (0x2e05) ++#define P_VI_HIST_SPL_PIX_CNT (volatile unsigned int *)((0x2e05 << 2) + 0xff900000) ++//Bit 31:0 hist_chroma_sum ++//counts for the total chroma value ++//read only ++#define VI_HIST_CHROMA_SUM (0x2e06) ++#define P_VI_HIST_CHROMA_SUM (volatile unsigned int *)((0x2e06 << 2) + 0xff900000) ++//Bit 31:16 higher hist bin ++//Bit 15:0 lower hist bin ++//0-255 are splited to 64 bins evenly, and VI_DNLP_HISTXX ++//are the statistic number of pixels that within each bin. ++//VI_DNLP_HIST00[15:0] counts for the first bin ++//VI_DNLP_HIST00[31:16] counts for the second bin ++//VI_DNLP_HIST01[15:0] counts for the third bin ++//VI_DNLP_HIST01[31:16] counts for the fourth bin ++//etc... ++//read only ++#define VI_DNLP_HIST00 (0x2e07) ++#define P_VI_DNLP_HIST00 (volatile unsigned int *)((0x2e07 << 2) + 0xff900000) ++#define VI_DNLP_HIST01 (0x2e08) ++#define P_VI_DNLP_HIST01 (volatile unsigned int *)((0x2e08 << 2) + 0xff900000) ++#define VI_DNLP_HIST02 (0x2e09) ++#define P_VI_DNLP_HIST02 (volatile unsigned int *)((0x2e09 << 2) + 0xff900000) ++#define VI_DNLP_HIST03 (0x2e0a) ++#define P_VI_DNLP_HIST03 (volatile unsigned int *)((0x2e0a << 2) + 0xff900000) ++#define VI_DNLP_HIST04 (0x2e0b) ++#define P_VI_DNLP_HIST04 (volatile unsigned int *)((0x2e0b << 2) + 0xff900000) ++#define VI_DNLP_HIST05 (0x2e0c) ++#define P_VI_DNLP_HIST05 (volatile unsigned int *)((0x2e0c << 2) + 0xff900000) ++#define VI_DNLP_HIST06 (0x2e0d) ++#define P_VI_DNLP_HIST06 (volatile unsigned int *)((0x2e0d << 2) + 0xff900000) ++#define VI_DNLP_HIST07 (0x2e0e) ++#define P_VI_DNLP_HIST07 (volatile unsigned int *)((0x2e0e << 2) + 0xff900000) ++#define VI_DNLP_HIST08 (0x2e0f) ++#define P_VI_DNLP_HIST08 (volatile unsigned int *)((0x2e0f << 2) + 0xff900000) ++#define VI_DNLP_HIST09 (0x2e10) ++#define P_VI_DNLP_HIST09 (volatile unsigned int *)((0x2e10 << 2) + 0xff900000) ++#define VI_DNLP_HIST10 (0x2e11) ++#define P_VI_DNLP_HIST10 (volatile unsigned int *)((0x2e11 << 2) + 0xff900000) ++#define VI_DNLP_HIST11 (0x2e12) ++#define P_VI_DNLP_HIST11 (volatile unsigned int *)((0x2e12 << 2) + 0xff900000) ++#define VI_DNLP_HIST12 (0x2e13) ++#define P_VI_DNLP_HIST12 (volatile unsigned int *)((0x2e13 << 2) + 0xff900000) ++#define VI_DNLP_HIST13 (0x2e14) ++#define P_VI_DNLP_HIST13 (volatile unsigned int *)((0x2e14 << 2) + 0xff900000) ++#define VI_DNLP_HIST14 (0x2e15) ++#define P_VI_DNLP_HIST14 (volatile unsigned int *)((0x2e15 << 2) + 0xff900000) ++#define VI_DNLP_HIST15 (0x2e16) ++#define P_VI_DNLP_HIST15 (volatile unsigned int *)((0x2e16 << 2) + 0xff900000) ++#define VI_DNLP_HIST16 (0x2e17) ++#define P_VI_DNLP_HIST16 (volatile unsigned int *)((0x2e17 << 2) + 0xff900000) ++#define VI_DNLP_HIST17 (0x2e18) ++#define P_VI_DNLP_HIST17 (volatile unsigned int *)((0x2e18 << 2) + 0xff900000) ++#define VI_DNLP_HIST18 (0x2e19) ++#define P_VI_DNLP_HIST18 (volatile unsigned int *)((0x2e19 << 2) + 0xff900000) ++#define VI_DNLP_HIST19 (0x2e1a) ++#define P_VI_DNLP_HIST19 (volatile unsigned int *)((0x2e1a << 2) + 0xff900000) ++#define VI_DNLP_HIST20 (0x2e1b) ++#define P_VI_DNLP_HIST20 (volatile unsigned int *)((0x2e1b << 2) + 0xff900000) ++#define VI_DNLP_HIST21 (0x2e1c) ++#define P_VI_DNLP_HIST21 (volatile unsigned int *)((0x2e1c << 2) + 0xff900000) ++#define VI_DNLP_HIST22 (0x2e1d) ++#define P_VI_DNLP_HIST22 (volatile unsigned int *)((0x2e1d << 2) + 0xff900000) ++#define VI_DNLP_HIST23 (0x2e1e) ++#define P_VI_DNLP_HIST23 (volatile unsigned int *)((0x2e1e << 2) + 0xff900000) ++#define VI_DNLP_HIST24 (0x2e1f) ++#define P_VI_DNLP_HIST24 (volatile unsigned int *)((0x2e1f << 2) + 0xff900000) ++#define VI_DNLP_HIST25 (0x2e20) ++#define P_VI_DNLP_HIST25 (volatile unsigned int *)((0x2e20 << 2) + 0xff900000) ++#define VI_DNLP_HIST26 (0x2e21) ++#define P_VI_DNLP_HIST26 (volatile unsigned int *)((0x2e21 << 2) + 0xff900000) ++#define VI_DNLP_HIST27 (0x2e22) ++#define P_VI_DNLP_HIST27 (volatile unsigned int *)((0x2e22 << 2) + 0xff900000) ++#define VI_DNLP_HIST28 (0x2e23) ++#define P_VI_DNLP_HIST28 (volatile unsigned int *)((0x2e23 << 2) + 0xff900000) ++#define VI_DNLP_HIST29 (0x2e24) ++#define P_VI_DNLP_HIST29 (volatile unsigned int *)((0x2e24 << 2) + 0xff900000) ++#define VI_DNLP_HIST30 (0x2e25) ++#define P_VI_DNLP_HIST30 (volatile unsigned int *)((0x2e25 << 2) + 0xff900000) ++#define VI_DNLP_HIST31 (0x2e26) ++#define P_VI_DNLP_HIST31 (volatile unsigned int *)((0x2e26 << 2) + 0xff900000) ++#define VI_DNLP_HIST32 (0x2e27) ++#define P_VI_DNLP_HIST32 (volatile unsigned int *)((0x2e27 << 2) + 0xff900000) ++//Bit 28:16 hist_pic_height active input data window height ++//Bit 12:0 hist_pic_width active input data window width ++#define VI_HIST_PIC_SIZE (0x2e28) ++#define P_VI_HIST_PIC_SIZE (volatile unsigned int *)((0x2e28 << 2) + 0xff900000) ++//Bit 15:8 hist_pix_white_value: >= this value will be white pixel ++//Bit 7:0 hist_pix_black_value: <= this value will be black pixel ++#define VI_HIST_BLACK_WHITE_VALUE (0x2e29) ++#define P_VI_HIST_BLACK_WHITE_VALUE (volatile unsigned int *)((0x2e29 << 2) + 0xff900000) ++#define VI_HIST_GCLK_CTRL (0x2e2a) ++#define P_VI_HIST_GCLK_CTRL (volatile unsigned int *)((0x2e2a << 2) + 0xff900000) ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: vi_hist_spl_reg.h ++// ++//`define MCDI_VCBUS_BASE 8'h2f ++// ++// Reading file: mcdi_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++// ----------------------------------------------- ++// CBUS_BASE: MCDI_VCBUS_BASE = 0x2f ++// ----------------------------------------------- ++////=================================================================//// ++//// memc di core 0 ++////=================================================================//// ++#define MCDI_HV_SIZEIN (0x2f00) ++#define P_MCDI_HV_SIZEIN (volatile unsigned int *)((0x2f00 << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28:16, reg_mcdi_hsize image horizontal size (number of cols) default=1024 ++//Bit 15:13, reserved ++//Bit 12: 0, reg_mcdi_vsize image vertical size (number of rows) default=1024 ++#define MCDI_HV_BLKSIZEIN (0x2f01) ++#define P_MCDI_HV_BLKSIZEIN (volatile unsigned int *)((0x2f01 << 2) + 0xff900000) ++//Bit 31, reg_mcdi_vrev default = 0 ++//Bit 30, reg_mcdi_hrev default = 0 ++//Bit 29:28, reserved ++//Bit 27:16, reg_mcdi_blkhsize image horizontal blk size (number of cols) default=1024 ++//Bit 15:13, reserved ++//Bit 11: 0, reg_mcdi_blkvsize image vertical blk size (number of rows) default=1024 ++#define MCDI_BLKTOTAL (0x2f02) ++#define P_MCDI_BLKTOTAL (volatile unsigned int *)((0x2f02 << 2) + 0xff900000) ++//Bit 31:24, reserved ++//Bit 23: 0, reg_mcdi_blktotal ++#define MCDI_MOTINEN (0x2f03) ++#define P_MCDI_MOTINEN (volatile unsigned int *)((0x2f03 << 2) + 0xff900000) ++//Bit 31: 2, reserved ++//Bit 1, reg_mcdi_motionrefen. enable motion refinement of MA, default = 1 ++//Bit 0, reg_mcdi_motionparadoxen. enable motion paradox detection, default = 1 ++#define MCDI_CTRL_MODE (0x2f04) ++#define P_MCDI_CTRL_MODE (volatile unsigned int *)((0x2f04 << 2) + 0xff900000) ++//Bit 31:28, reserved ++//Bit 27:26, reg_mcdi_lmvlocken 0:disable, 1: use max Lmv, 2: use no-zero Lmv, lmv lock enable mode, default = 2 ++//Bit 25, reg_mcdi_reldetrptchken ++// 0: unable; 1: enable, enable repeat pattern check (not repeat mv detection) in rel det part, default = 1 ++//Bit 24, reg_mcdi_reldetgmvpd22chken ++// 0: unable; 1: enable, enable pull-down 22 mode check in gmv lock mode for rel det, default = 1 ++//Bit 23, reg_mcdi_pd22chken ++// 0: unable; 1: enable, enable pull-down 22 mode check (lock) function, default = 1 ++//Bit 22, reg_mcdi_reldetlpfen ++// 0: unable; 1: enable, enable det value lpf, default = 1 ++//Bit 21, reg_mcdi_reldetlmvpd22chken ++// 0: unable; 1: enable, enable pull-down 22 mode check in lmv lock mode for rel det, default = 1 ++//Bit 20, reg_mcdi_reldetlmvdifchken ++// 0: unable; 1: enable, enable lmv dif check in lmv lock mode for rel det, default = 1 ++//Bit 19, reg_mcdi_reldetgmvdifchken ++// 0: unable; 1: enable, enable lmv dif check in lmv lock mode for rel det, default = 1 ++//Bit 18, reg_mcdi_reldetpd22chken ++// 0: unable; 1: enable, enable pull-down 22 mode check for rel det refinement, default = 1 ++//Bit 17, reg_mcdi_reldetfrqchken ++// 0: unable; 1: enable, enable mv frequency check in rel det, default = 1 ++//Bit 16, reg_mcdi_qmeen ++// 0: unable; 1: enable, enable quarter motion estimation, defautl = 1 ++//Bit 15, reg_mcdi_refrptmven ++// 0: unable; 1: enable, use repeat mv in refinement, default = 1 ++//Bit 14, reg_mcdi_refgmven ++// 0: unable; 1: enable, use gmv in refinement, default = 1 ++//Bit 13, reg_mcdi_reflmven ++// 0: unable; 1: enable, use lmvs in refinement, default = 1 ++//Bit 12, reg_mcdi_refnmven ++// 0: unable; 1: enable, use neighoring mvs in refinement, default = 1 ++//Bit 11, reserved ++//Bit 10, reg_mcdi_referrfrqchken ++// 0: unable; 1: enable, enable mv frquency check while finding min err in ref, default = 1 ++//Bit 9, reg_mcdi_refen ++// 0: unable; 1: enable, enable mv refinement, default = 1 ++//Bit 8, reg_mcdi_horlineen ++// 0: unable; 1: enable,enable horizontal lines detection by sad map, default = 1 ++//Bit 7, reg_mcdi_highvertfrqdeten ++// 0: unable; 1: enable, enable high vertical frequency pattern detection, default = 1 ++//Bit 6, reg_mcdi_gmvlocken ++// 0: unable; 1: enable, enable gmv lock mode, default = 1 ++//Bit 5, reg_mcdi_rptmven ++// 0: unable; 1: enable, enable repeat pattern detection, default = 1 ++//Bit 4, reg_mcdi_gmven ++// 0: unable; 1: enable, enable global motion estimation, default = 1 ++//Bit 3, reg_mcdi_lmven ++// 0: unable; 1: enable, enable line mv estimation for hme, default = 1 ++//Bit 2, reg_mcdi_chkedgeen ++// 0: unable; 1: enable, enable check edge function, default = 1 ++//Bit 1, reg_mcdi_txtdeten ++// 0: unable; 1: enable, enable texture detection, default = 1 ++//Bit 0, reg_mcdi_memcen ++// 0: unable; 1: enable, enable of memc di, default = 1 ++#define MCDI_UNI_MVDST (0x2f05) ++#define P_MCDI_UNI_MVDST (volatile unsigned int *)((0x2f05 << 2) + 0xff900000) ++//Bit 31:20, reserved ++//Bit 19:17, reg_mcdi_unimvdstabsseg0 segment0 for uni-mv abs, default = 1 ++//Bit 16:12, reg_mcdi_unimvdstabsseg1 segment1 for uni-mv abs, default = 15 ++//Bit 11: 8, reg_mcdi_unimvdstabsdifgain0 2/2, gain0 of uni-mv abs dif for segment0, normalized 2 to '1', default = 2 ++//Bit 7: 5, reg_mcdi_unimvdstabsdifgain1 2/2, gain1 of uni-mv abs dif for segment1, normalized 2 to '1', default = 2 ++//Bit 4: 2, reg_mcdi_unimvdstabsdifgain2 2/2, gain2 of uni-mv abs dif beyond segment1, normalized 2 to '1', default = 2 ++//Bit 1: 0, reg_mcdi_unimvdstsgnshft shift for neighboring distance of uni-mv, default = 0 ++#define MCDI_BI_MVDST (0x2f06) ++#define P_MCDI_BI_MVDST (volatile unsigned int *)((0x2f06 << 2) + 0xff900000) ++//Bit 31:20, reserved ++//Bit 19:17, reg_mcdi_bimvdstabsseg0 segment0 for bi-mv abs, default = 1 ++//Bit 16:12, reg_mcdi_bimvdstabsseg1 segment1 for bi-mv abs, default = 9 ++//Bit 11: 8, reg_mcdi_bimvdstabsdifgain0 6/2, gain0 of bi-mv abs dif for segment0, normalized 2 to '1', default = 6 ++//Bit 7: 5, reg_mcdi_bimvdstabsdifgain1 3/2, gain1 of bi-mvabs dif for segment1, normalized 2 to '1', default = 3 ++//Bit 4: 2, reg_mcdi_bimvdstabsdifgain2 2/2, gain2 of bi-mvabs dif beyond segment1, normalized 2 to '1', default = 2 ++//Bit 1: 0, reg_mcdi_bimvdstsgnshft shift for neighboring distance of bi-mv, default = 0 ++#define MCDI_SAD_GAIN (0x2f07) ++#define P_MCDI_SAD_GAIN (volatile unsigned int *)((0x2f07 << 2) + 0xff900000) ++//Bit 31:19, reserved ++//Bit 18:17, reg_mcdi_unisadcorepxlgain uni-sad core pixels gain, default = 3 ++//Bit 16, reg_mcdi_unisadcorepxlnormen enable uni-sad core pixels normalization, default = 0 ++//Bit 15:11, reserved ++//Bit 10: 9, reg_mcdi_bisadcorepxlgain bi-sad core pixels gain, default = 3 ++//Bit 8, reg_mcdi_bisadcorepxlnormen enable bi-sad core pixels normalization, default = 1 ++//Bit 7: 3, reserved ++//Bit 2: 1, reg_mcdi_biqsadcorepxlgain bi-qsad core pixels gain, default = 3 ++//Bit 0, reg_mcdi_biqsadcorepxlnormen enable bi-qsad core pixels normalization, default = 1 ++#define MCDI_TXT_THD (0x2f08) ++#define P_MCDI_TXT_THD (volatile unsigned int *)((0x2f08 << 2) + 0xff900000) ++//Bit 31:24, reserved ++//Bit 23:16, reg_mcdi_txtminmaxdifthd, min max dif threshold (>=) for texture detection, default = 24 ++//Bit 15: 8, reg_mcdi_txtmeandifthd, mean dif threshold (<) for texture detection, default = 9 ++//Bit 7: 3, reserved ++//Bit 2: 0, reg_mcdi_txtdetthd, texture detecting threshold, 0~4, default = 2 ++#define MCDI_FLT_MODESEL (0x2f09) ++#define P_MCDI_FLT_MODESEL (volatile unsigned int *)((0x2f09 << 2) + 0xff900000) ++//Bit 31 reserved ++//Bit 30:28, reg_mcdi_flthorlineselmode mode for horizontal line detecting flat calculation, default = 1, same as below ++//Bit 27 reserved ++//Bit 26:24, reg_mcdi_fltgmvselmode mode for gmv flat calculation, default = 4, same as below ++//Bit 23, reserved ++//Bit 22:20, reg_mcdi_fltsadselmode mode for sad flat calculation, default = 2, same as below ++//Bit 19, reserved ++//Bit 18:16, reg_mcdi_fltbadwselmode mode for badw flat calculation, default = 3, same as below ++//Bit 15, reserved ++//Bit 14:12, reg_mcdi_fltrptmvselmode mode for repeat mv flat calculation, default = 4, same as below ++//Bit 11, reserved ++//Bit 10: 8, reg_mcdi_fltbadrelselmode mode for bad rel flat calculation, default = 4, same as below ++//Bit 7, reserved ++//Bit 6: 4, reg_mcdi_fltcolcfdselmode mode for col cfd flat calculation, default = 2, same as below ++//Bit 3, reserved ++//Bit 2: 0, reg_mcdi_fltpd22chkselmode mode for pd22 check flat calculation, default = 2, # 0:cur dif h, 1: cur dif v, 2: pre dif h, 3: pre dif v, 4: cur flt, 5: pre flt, 6: cur+pre, 7: max all(cur,pre) ++#define MCDI_CHK_EDGE_THD (0x2f0a) ++#define P_MCDI_CHK_EDGE_THD (volatile unsigned int *)((0x2f0a << 2) + 0xff900000) ++//Bit 23:28, reserved. ++//Bit 27:24, reg_mcdi_chkedgedifsadthd. thd (<=) for sad dif check, 0~8, default = 1 ++//Bit 23:16, reserved. ++//Bit 15:12, reg_mcdi_chkedgemaxedgethd. max drt of edge, default = 15 ++//Bit 11: 8, reg_mcdi_chkedgeminedgethd. min drt of edge, default = 2 ++//Bit 7, reserved. ++//Bit 6: 0, reg_mcdi_chkedgevdifthd. thd for vertical dif in check edge, default = 14 ++#define MCDI_CHK_EDGE_GAIN_OFFST (0x2f0b) ++#define P_MCDI_CHK_EDGE_GAIN_OFFST (volatile unsigned int *)((0x2f0b << 2) + 0xff900000) ++//Bit 31:24, reserved. ++//Bit 23:20, reg_mcdi_chkedgedifthd1. thd1 for edge dif check (<=), default = 4 ++//Bit 19:16, reg_mcdi_chkedgedifthd0. thd0 for edge dif check (>=), default = 15 ++//Bit :15, reserved. ++//Bit 14:10, reg_mcdi_chkedgechklen. total check length for edge check, 1~24 (>0), default = 24 ++//Bit 9: 8, reg_mcdi_chkedgeedgesel. final edge select mode, 0: original start edge, 1: lpf start edge, 2: orignal start+end edge, 3: lpf start+end edge, default = 1 ++//Bit 7: 3, reg_mcdi_chkedgesaddstgain. distance gain for sad calc while getting edges, default = 4 ++//Bit 2, reg_mcdi_chkedgechkmode. edge used in check mode, 0: original edge, 1: lpf edge, defautl = 1 ++//Bit 1, reg_mcdi_chkedgestartedge. edge mode for start edge, 0: original edge, 1: lpf edge, defautl = 0 ++//Bit 0, reg_mcdi_chkedgeedgelpf. edge lpf mode, 0:[0,2,4,2,0], 1:[1,2,2,2,1], default = 0 ++#define MCDI_LMV_RT (0x2f0c) ++#define P_MCDI_LMV_RT (volatile unsigned int *)((0x2f0c << 2) + 0xff900000) ++//BIt 31:15, reserved ++//Bit 14:12, reg_mcdi_lmvvalidmode valid mode for lmv calc., 100b: use char det, 010b: use flt, 001b: use hori flg ++//Bit 11:10, reg_mcdi_lmvgainmvmode four modes of mv selection for lmv weight calucluation, default = 1 ++// 0: cur(x-3), lst(x-1,x,x+1); 1: cur(x-4,x-3), lst(x,x+1); 2: cur(x-5,x-4,x-3), lst(x-1,x,x+1,x+2,x+3); 3: cur(x-6,x-5,x-4,x-3), lst(x-1,x,x+1,x+2); ++//Bit 9, reg_mcdi_lmvinitmode initial lmvs at first row of input field, 0: intial value = 0; 1: inital = 32 (invalid), default = 0 ++//Bit 8, reserved ++//Bit 7: 4, reg_mcdi_lmvrt0 ratio of max mv, default = 5 ++//Bit 3: 0, reg_mcdi_lmvrt1 ratio of second max mv, default = 5 ++#define MCDI_LMV_GAINTHD (0x2f0d) ++#define P_MCDI_LMV_GAINTHD (volatile unsigned int *)((0x2f0d << 2) + 0xff900000) ++//Bit 31:24, reg_mcdi_lmvvxmaxgain max gain of lmv weight, default = 96 ++//Bit 23, reserved ++//Bit 22:20, reg_mcdi_lmvdifthd0 dif threshold 0 (<) for small lmv, default = 1 ++//Bit 19:17, reg_mcdi_lmvdifthd1 dif threshold 1 (<) for median lmv, default = 2 ++//Bit 16:14, reg_mcdi_lmvdifthd2 dif threshold 2 (<) for large lmv, default = 3 ++//Bit 13: 8, reg_mcdi_lmvnumlmt least/limit number of (total number - max0), default = 20 ++//Bit 7: 0, reg_mcdi_lmvfltthd flt cnt thd (<) for lmv, default = 9 ++#define MCDI_RPTMV_THD0 (0x2f0e) ++#define P_MCDI_RPTMV_THD0 (volatile unsigned int *)((0x2f0e << 2) + 0xff900000) ++//Bit 31:25, reg_mcdi_rptmvslpthd2 slope thd (>=) between i and i+3/i-3 (i+4/i-4), default = 64 ++//Bit 24:20, reg_mcdi_rptmvslpthd1 slope thd (>=) between i and i+2/i-2, default = 4 ++//Bit 19:10, reg_mcdi_rptmvampthd2 amplitude thd (>=) between max and min, when count cycles, default = 300 ++//Bit 9: 0, reg_mcdi_rptmvampthd1 amplitude thd (>=) between average of max and min, default = 400 ++#define MCDI_RPTMV_THD1 (0x2f0f) ++#define P_MCDI_RPTMV_THD1 (volatile unsigned int *)((0x2f0f << 2) + 0xff900000) ++//Bit 31:28, reserved ++//Bit 27:25, reg_mcdi_rptmvcyccntthd thd (>=) of total cycles count, default = 2 ++//Bit 24:21, reg_mcdi_rptmvcycdifthd dif thd (<) of cycles length, default = 3 ++//Bit 20:18, reg_mcdi_rptmvcycvldthd thd (>) of valid cycles number, default = 1 ++//Bit 17:15, reg_mcdi_rptmvhalfcycminthd min length thd (>=) of half cycle, default = 2 ++//Bit 14:11, reg_mcdi_rptmvhalfcycdifthd neighboring half cycle length dif thd (<), default = 5 ++//Bit 10: 8, reg_mcdi_rptmvminmaxcntthd least number of valid max and min, default = 2 ++//Bit 7: 5, reg_mcdi_rptmvcycminthd min length thd (>=) of cycles, default = 2 ++//Bit 4: 0, reg_mcdi_rptmvcycmaxthd max length thd (<) of cycles, default = 17 ++#define MCDI_RPTMV_THD2 (0x2f10) ++#define P_MCDI_RPTMV_THD2 (volatile unsigned int *)((0x2f10 << 2) + 0xff900000) ++//Bit 31:24, reserved ++//Bit 23:16, reg_mcdi_rptmvhdifthd0 higher hdif thd (>=) (vertical edge) for rpt detection, default = 8 ++//Bit 15: 8, reg_mcdi_rptmvhdifthd1 hdif thd (>=) (slope edge) for rpt detection, default = 4 ++//Bit 7: 0, reg_mcdi_rptmvvdifthd vdif thd (>=) (slope edge) for rpt detection, default = 1 ++#define MCDI_RPTMV_SAD (0x2f11) ++#define P_MCDI_RPTMV_SAD (volatile unsigned int *)((0x2f11 << 2) + 0xff900000) ++//Bit 31:26, reserved ++//Bit 25:16, reg_mcdi_rptmvsaddifthdgain 7x3x(16/16), gain for sad dif thd in rpt mv detection, 0~672, normalized 16 as '1', default = 336 ++//Bit 15:10, reserved ++//Bit 9: 0, reg_mcdi_rptmvsaddifthdoffst offset for sad dif thd in rpt mv detection, -512~511, default = 16 ++#define MCDI_RPTMV_FLG (0x2f12) ++#define P_MCDI_RPTMV_FLG (volatile unsigned int *)((0x2f12 << 2) + 0xff900000) ++//Bit 31:18, reserved ++//Bit 17:16, reg_mcdi_rptmvmode select mode of mvs for repeat motion estimation, 0: hmv, 1: qmv/2, 2 or 3: qmv/4, default = 2 ++//Bit 15: 8, reg_mcdi_rptmvflgcntthd thd (>=) of min count number for rptmv of whole field, for rptmv estimation, default = 64 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_rptmvflgcntrt 4/32, ratio for repeat mv flag count, normalized 32 as '1', set 31 to 32, ++#define MCDI_RPTMV_GAIN (0x2f13) ++#define P_MCDI_RPTMV_GAIN (volatile unsigned int *)((0x2f13 << 2) + 0xff900000) ++//Bit 31:24, reg_mcdi_rptmvlftgain up repeat mv gain for hme, default = 96 ++//Bit 23:16, reg_mcdi_rptmvuplftgain up left repeat mv gain for hme, default = 32 ++//Bit 15: 8, reg_mcdi_rptmvupgain up repeat mv gain for hme, default = 64 ++//Bit 7: 0, reg_mcdi_rptmvuprightgain up right repeat mv gain for hme, default = 32 ++#define MCDI_GMV_RT (0x2f14) ++#define P_MCDI_GMV_RT (volatile unsigned int *)((0x2f14 << 2) + 0xff900000) ++//Bit 31, reserved ++//Bit 30:24, reg_mcdi_gmvmtnrt0 ratio 0 for motion senario, set 127 to 128, normalized 128 as '1', default =32 ++//Bit 23, reserved ++//Bit 22:16, reg_mcdi_gmvmtnrt1 ratio 1 for motion senario, set 127 to 128, normalized 128 as '1', default = 56 ++//Bit 15, reserved ++//Bit 14: 8, reg_mcdi_gmvstlrt0 ratio 0 for still senario, set 127 to 128, normalized 128 as '1', default = 56 ++//Bit 7, reserved ++//Bit 6: 0, reg_mcdi_gmvstlrt1 ratio 1 for still senario, set 127 to 128, normalized 128 as '1', default = 80 ++#define MCDI_GMV_GAIN (0x2f15) ++#define P_MCDI_GMV_GAIN (volatile unsigned int *)((0x2f15 << 2) + 0xff900000) ++//Bit 31:25, reg_mcdi_gmvzeromvlockrt0 ratio 0 for locking zero mv, set 127 to 128, normalized 128 as '1', default = 100 ++//Bit 24:18, reg_mcdi_gmvzeromvlockrt1 ratio 1 for locking zero mv, set 127 to 128, normalized 128 as '1', default = 112 ++//Bit 17:16, reg_mcdi_gmvvalidmode valid mode for gmv calc., 10b: use flt, 01b: use hori flg, default = 3 ++//Bit 15: 8, reg_mcdi_gmvvxgain gmv's vx gain when gmv locked for hme, default = 0 ++//Bit 7: 0, reg_mcdi_gmvfltthd flat thd (<) for gmv calc. default = 3 ++#define MCDI_HOR_SADOFST (0x2f16) ++#define P_MCDI_HOR_SADOFST (volatile unsigned int *)((0x2f16 << 2) + 0xff900000) ++//Bit 31:25, reserved ++//Bit 24:16, reg_mcdi_horsaddifthdgain 21*1/8, gain/divisor for sad dif threshold in hor line detection, normalized 8 as '1', default = 21 ++//Bit 15: 8, reg_mcdi_horsaddifthdoffst offset for sad dif threshold in hor line detection, -128~127, default = 0 ++//Bit 7: 0, reg_mcdi_horvdifthd threshold (>=) of vertical dif of next block for horizontal line detection, default = 24 ++#define MCDI_REF_MV_NUM (0x2f17) ++#define P_MCDI_REF_MV_NUM (volatile unsigned int *)((0x2f17 << 2) + 0xff900000) ++//Bit 31: 2, reserved ++//Bit 1: 0, reg_mcdi_refmcmode. motion compensated mode used in refinement, 0: pre, 1: next, 2: (pre+next)/2, default = 0 ++#define MCDI_REF_BADW_THD_GAIN (0x2f18) ++#define P_MCDI_REF_BADW_THD_GAIN (volatile unsigned int *)((0x2f18 << 2) + 0xff900000) ++//Bit 31:28, reserved ++//Bit 27:24, reg_mcdi_refbadwcnt2gain. gain for badwv count num==3, default = 6 ++//Bit 23:20, reg_mcdi_refbadwcnt1gain. gain for badwv count num==2, default = 3 ++//Bit 19:16, reg_mcdi_refbadwcnt0gain. gain for badwv count num==1, default = 1 ++//Bit 15:12, reg_mcdi_refbadwthd3. threshold 3 for detect badweave with largest average luma, default = 4 ++//Bit 11: 8, reg_mcdi_refbadwthd2. threshold 2 for detect badweave with third smallest average luma, default = 3 ++//Bit 7: 4, reg_mcdi_refbadwthd1. threshold 1 for detect badweave with second smallest average luma, default = 2 ++//Bit 3: 0, reg_mcdi_refbadwthd0. threshold 0 for detect badweave with smallest average luma, default = 1 ++#define MCDI_REF_BADW_SUM_GAIN (0x2f19) ++#define P_MCDI_REF_BADW_SUM_GAIN (volatile unsigned int *)((0x2f19 << 2) + 0xff900000) ++//Bit 31:13, reserved ++//Bit 12: 8, reg_mcdi_refbadwsumgain0. sum gain for r channel, 0~16, default = 8 ++//Bit 7: 5, reserved ++//Bit 4, reg_mcdi_refbadwcalcmode. mode for badw calculation, 0:sum, 1:max, default = 0 ++//Bit 3: 0, reserved ++#define MCDI_REF_BS_THD_GAIN (0x2f1a) ++#define P_MCDI_REF_BS_THD_GAIN (volatile unsigned int *)((0x2f1a << 2) + 0xff900000) ++//Bit 31:28, reg_mcdi_refbsudgain1. up & down block stregth gain1, normalized to 8 as '1', default = 2 ++//Bit 27:24, reg_mcdi_refbsudgain0. up & down block stregth gain0, normalized to 8 as '1', default = 4 ++//Bit 23:19, reserved ++//Bit 18:16, reg_mcdi_refbslftgain. left block strength gain, default = 0 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_mcdi_refbsthd1. threshold 1 for detect block stregth in refinment, default = 16 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_refbsthd0. threshold 0 for detect block stregth in refinment, default = 8 ++#define MCDI_REF_ERR_GAIN0 (0x2f1b) ++#define P_MCDI_REF_ERR_GAIN0 (volatile unsigned int *)((0x2f1b << 2) + 0xff900000) ++//Bit 31, reserved ++//Bit 30:24, reg_mcdi_referrnbrdstgain. neighoring mv distances gain for err calc. in ref, normalized to 8 as '1', default = 48 ++//Bit 23:20, reserved ++//Bit 19:16, reg_mcdi_referrbsgain. bs gain for err calc. in ref, normalized to 8 as '1', default = 4 ++//Bit 15, reserved ++//Bit 14: 8, reg_mcdi_referrbadwgain. badw gain for err calc. in ref, normalized to 8 as '1', default = 64 ++//Bit 7: 4, reserved ++//Bit 3: 0, reg_mcdi_referrsadgain. sad gain for err calc. in ref, normalized to 8 as '1', default = 4 ++#define MCDI_REF_ERR_GAIN1 (0x2f1c) ++#define P_MCDI_REF_ERR_GAIN1 (volatile unsigned int *)((0x2f1c << 2) + 0xff900000) ++//Bit 31:20, reserved ++//Bit 19:16, reg_mcdi_referrchkedgegain. check edge gain for err calc. in ref, normalized to 8 as '1', default = 4 ++//Bit 15:12, reserved ++//Bit 11: 8, reg_mcdi_referrlmvgain. (locked) lmv gain for err calc. in ref, normalized to 8 as '1', default = 0 ++//Bit 7: 4, reserved ++//Bit 3: 0, reg_mcdi_referrgmvgain. (locked) gmv gain for err calc. in ref, normalized to 8 as '1', default = 0 ++#define MCDI_REF_ERR_FRQ_CHK (0x2f1d) ++#define P_MCDI_REF_ERR_FRQ_CHK (volatile unsigned int *)((0x2f1d << 2) + 0xff900000) ++//Bit 31:28, reserved ++//Bit 27:24, reg_mcdi_referrfrqgain. gain for mv frquency, normalized to 4 as '1', default = 10 ++//Bit 23:21, reserved ++//Bit 20:16, reg_mcdi_referrfrqmax. max gain for mv frquency check, default = 31 ++//Bit 15, reserved ++//Bit 14:12, reg_mcdi_ref_errfrqmvdifthd2. mv dif threshold 2 (<) for mv frquency check, default = 3 ++//Bit 11, reserved ++//Bit 10: 8, reg_mcdi_ref_errfrqmvdifthd1. mv dif threshold 1 (<) for mv frquency check, default = 2 ++//Bit 7, reserved ++//Bit 6: 4, reg_mcdi_ref_errfrqmvdifthd0. mv dif threshold 0 (<) for mv frquency check, default = 1 ++//Bit 3: 0, reserved ++#define MCDI_QME_LPF_MSK (0x2f1e) ++#define P_MCDI_QME_LPF_MSK (volatile unsigned int *)((0x2f1e << 2) + 0xff900000) ++//Bit 31:28, reserved ++//Bit 27:24, reg_mcdi_qmechkedgelpfmsk0. lpf mask0 for chk edge in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7 ++//Bit 23:20, reserved ++//Bit 19:16, reg_mcdi_qmebslpfmsk0. lpf mask0 for bs in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7 ++//Bit 15:12, reserved ++//Bit 11: 8, reg_mcdi_qmebadwlpfmsk0. lpf mask0 for badw in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7 ++//Bit 7: 4, reserved ++//Bit 3: 0, reg_mcdi_qmesadlpfmsk0. lpf mask0 for sad in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7 ++#define MCDI_REL_DIF_THD_02 (0x2f1f) ++#define P_MCDI_REL_DIF_THD_02 (volatile unsigned int *)((0x2f1f << 2) + 0xff900000) ++//Bit 31:24, reserved. ++//Bit 23:16, reg_mcdi_reldifthd2. thd (<) for (hdif+vdif), default = 9 ++//Bit 15: 8, reg_mcdi_reldifthd1. thd (<) for (vdif), default = 5 ++//Bit 7: 0, reg_mcdi_reldifthd0. thd (>=) for (hdif-vdif), default = 48 ++#define MCDI_REL_DIF_THD_34 (0x2f20) ++#define P_MCDI_REL_DIF_THD_34 (volatile unsigned int *)((0x2f20 << 2) + 0xff900000) ++//Bit 31:16, reserved. ++//Bit 15: 8, reg_mcdi_reldifthd4. thd (<) for (hdif), default = 255 ++//Bit 7: 0, reg_mcdi_reldifthd3. thd (>=) for (vdif-hdif), default = 48 ++#define MCDI_REL_BADW_GAIN_OFFST_01 (0x2f21) ++#define P_MCDI_REL_BADW_GAIN_OFFST_01 (volatile unsigned int *)((0x2f21 << 2) + 0xff900000) ++//Bit 31:24, reg_mcdi_relbadwoffst1. offset for badw adj, for flat block, -128~127, default = 0 ++//Bit 23:16, reg_mcdi_relbadwgain1. gain for badw adj, for flat block, default = 128 ++//Bit 15: 8, reg_mcdi_relbadwoffst0. offset for badw adj, for vertical block, -128~127, default = 0 ++//Bit 7: 0, reg_mcdi_relbadwgain0. gain for badw adj, for vertical block, default = 160 ++#define MCDI_REL_BADW_GAIN_OFFST_23 (0x2f22) ++#define P_MCDI_REL_BADW_GAIN_OFFST_23 (volatile unsigned int *)((0x2f22 << 2) + 0xff900000) ++//Bit 31:24, reg_mcdi_relbadwoffst3. offset for badw adj, for other block, -128~127, default = 0 ++//Bit 23:16, reg_mcdi_relbadwgain3. gain for badw adj, for other block, default = 48 ++//Bit 15: 8, reg_mcdi_relbadwoffst2. offset for badw adj, for horizontal block, -128~127, default = 0 ++//Bit 7: 0, reg_mcdi_relbadwgain2. gain for badw adj, for horizontal block, default = 48 ++#define MCDI_REL_BADW_THD_GAIN_OFFST (0x2f23) ++#define P_MCDI_REL_BADW_THD_GAIN_OFFST (volatile unsigned int *)((0x2f23 << 2) + 0xff900000) ++//Bit 31:23, reserved. ++//Bit 22:16, reg_mcdi_relbadwoffst. offset for badw thd adj, -64~63, default = 0 ++//Bit 15: 8, reserved. ++//Bit 7: 0, reg_mcdi_relbadwthdgain. gain0 for badw thd adj, normalized to 16 as '1', default = 16 ++#define MCDI_REL_BADW_THD_MIN_MAX (0x2f24) ++#define P_MCDI_REL_BADW_THD_MIN_MAX (volatile unsigned int *)((0x2f24 << 2) + 0xff900000) ++//Bit 31:18, reserved. ++//Bit 17: 8, reg_mcdi_relbadwthdmax. max for badw thd adj, default = 256 ++//Bit 7: 0, reg_mcdi_relbadwthdmin. min for badw thd adj, default = 16 ++#define MCDI_REL_SAD_GAIN_OFFST_01 (0x2f25) ++#define P_MCDI_REL_SAD_GAIN_OFFST_01 (volatile unsigned int *)((0x2f25 << 2) + 0xff900000) ++//Bit 31:24, reg_mcdi_relsadoffst1. offset for sad adj, for flat block, -128~127, default = 0 ++//Bit 23:20, reserved. ++//Bit 19:16, reg_mcdi_relsadgain1. gain for sad adj, for flat block, normalized to 8 as '1', default = 8 ++//Bit 15: 8, reg_mcdi_relsadoffst0. offset for sad adj, for vertical block, -128~127, default = 0 ++//Bit 7: 4, reserved. ++//Bit 3: 0, reg_mcdi_relsadgain0. gain for sad adj, for vertical block, normalized to 8 as '1', default = 6 ++#define MCDI_REL_SAD_GAIN_OFFST_23 (0x2f26) ++#define P_MCDI_REL_SAD_GAIN_OFFST_23 (volatile unsigned int *)((0x2f26 << 2) + 0xff900000) ++//Bit 31:24, reg_mcdi_relsadoffst3. offset for sad adj, for other block, -128~127, default = 0 ++//Bit 23:20, reserved. ++//Bit 19:16, reg_mcdi_relsadgain3. gain for sad adj, for other block, normalized to 8 as '1', default = 8 ++//Bit 15: 8, reg_mcdi_relsadoffst2. offset for sad adj, for horizontal block, -128~127, default = 0 ++//Bit 7: 4, reserved. ++//Bit 3: 0, reg_mcdi_relsadgain2. gain for sad adj, for horizontal block, normalized to 8 as '1', default = 12 ++#define MCDI_REL_SAD_THD_GAIN_OFFST (0x2f27) ++#define P_MCDI_REL_SAD_THD_GAIN_OFFST (volatile unsigned int *)((0x2f27 << 2) + 0xff900000) ++//Bit 31:24, reserved. ++//Bit 23:16, reg_mcdi_relsadoffst. offset for sad thd adj, -128~127, default = 0 ++//Bit 15:10, reserved. ++//Bit 9: 0, reg_mcdi_relsadthdgain. gain for sad thd adj, 21*2/16, normalized to 16 as '1', default = 42 ++#define MCDI_REL_SAD_THD_MIN_MAX (0x2f28) ++#define P_MCDI_REL_SAD_THD_MIN_MAX (volatile unsigned int *)((0x2f28 << 2) + 0xff900000) ++//Bit 31:27, reserved. ++//Bit 26:16, reg_mcdi_relsadthdmax. max for sad thd adj, 21*32, default = 672 ++//Bit 15: 9, reserved. ++//Bit 8: 0, reg_mcdi_relsadthdmin. min for sad thd adj, 21*2, default = 42 ++#define MCDI_REL_DET_GAIN_00 (0x2f29) ++#define P_MCDI_REL_DET_GAIN_00 (volatile unsigned int *)((0x2f29 << 2) + 0xff900000) ++//Bit 31:21, reserved. ++//Bit 20:16, reg_mcdi_reldetbsgain0. gain0 (gmv locked) for bs, for det. calc. normalized to 16 as '1', default = 8 ++//Bit 15:14, reserved. ++//Bit 13: 8, reg_mcdi_reldetbadwgain0. gain0 (gmv locked) for badw, for det. calc. normalized to 16 as '1', default = 12 ++//Bit 7: 5, reserved. ++//Bit 4: 0, reg_mcdi_reldetsadgain0. gain0 (gmv locked) for qsad, for det. calc. normalized to 16 as '1', default = 8 ++#define MCDI_REL_DET_GAIN_01 (0x2f2a) ++#define P_MCDI_REL_DET_GAIN_01 (volatile unsigned int *)((0x2f2a << 2) + 0xff900000) ++//Bit 31:14, reserved. ++//Bit 12: 8, reg_mcdi_reldetchkedgegain0. gain0 (gmv locked) for chk_edge, for det. calc. normalized to 16 as '1', default = 2 ++//Bit 7, reserved. ++//Bit 6: 0, reg_mcdi_reldetnbrdstgain0. gain0 (gmv locked) for neighoring dist, for det. calc. normalized to 16 as '1', default = 24 ++#define MCDI_REL_DET_GAIN_10 (0x2f2b) ++#define P_MCDI_REL_DET_GAIN_10 (volatile unsigned int *)((0x2f2b << 2) + 0xff900000) ++//Bit 31:21, reserved. ++//Bit 20:16, reg_mcdi_reldetbsgain1. gain1 (lmv locked) for bs, for det. calc. normalized to 16 as '1', default = 0 ++//Bit 15:14, reserved. ++//Bit 13: 8, reg_mcdi_reldetbadwgain1. gain1 (lmv locked) for badw, for det. calc. normalized to 16 as '1', default = 8 ++//Bit 7: 5, reserved. ++//Bit 4: 0, reg_mcdi_reldetsadgain1. gain1 (lmv locked) for qsad, for det. calc. normalized to 16 as '1', default = 8 ++#define MCDI_REL_DET_GAIN_11 (0x2f2c) ++#define P_MCDI_REL_DET_GAIN_11 (volatile unsigned int *)((0x2f2c << 2) + 0xff900000) ++//Bit 31:14, reserved. ++//Bit 12: 8, reg_mcdi_reldetchkedgegain1. gain1 (lmv locked) for chk_edge, for det. calc. normalized to 16 as '1', default = 0 ++//Bit 7, reserved. ++//Bit 6: 0, reg_mcdi_reldetnbrdstgain1. gain1 (lmv locked) for neighoring dist, for det. calc. normalized to 16 as '1', default = 24 ++#define MCDI_REL_DET_GAIN_20 (0x2f2d) ++#define P_MCDI_REL_DET_GAIN_20 (volatile unsigned int *)((0x2f2d << 2) + 0xff900000) ++//Bit 31:21, reserved. ++//Bit 20:16, reg_mcdi_reldetbsgain2. gain2 (no locked) for bs, for det. calc. normalized to 16 as '1', default = 12 ++//Bit 15:14, reserved. ++//Bit 13: 8, reg_mcdi_reldetbadwgain2. gain2 (no locked) for badw, for det. calc. normalized to 16 as '1', default = 32 ++//Bit 7: 5, reserved. ++//Bit 4: 0, reg_mcdi_reldetsadgain2. gain2 (no locked) for qsad, for det. calc. normalized to 16 as '1', default = 16 ++#define MCDI_REL_DET_GAIN_21 (0x2f2e) ++#define P_MCDI_REL_DET_GAIN_21 (volatile unsigned int *)((0x2f2e << 2) + 0xff900000) ++//Bit 31:26, reserved ++//Bit 25:16, reg_mcdi_reldetoffst. offset for rel calculation, for det. calc. -512~511, default = 0 ++//Bit 15:14, reserved. ++//Bit 12: 8, reg_mcdi_reldetchkedgegain2. gain2 (no locked) for chk_edge, for det. calc. normalized to 16 as '1', default = 10 ++//Bit 7, reserved. ++//Bit 6: 0, reg_mcdi_reldetnbrdstgain2. gain2 (no locked) for neighoring dist, for det. calc. normalized to 16 as '1', default = 32 ++#define MCDI_REL_DET_GMV_DIF_CHK (0x2f2f) ++#define P_MCDI_REL_DET_GMV_DIF_CHK (volatile unsigned int *)((0x2f2f << 2) + 0xff900000) ++//Bit 31:24, reserved. ++//Bit 23:16, reg_mcdi_reldetgmvfltthd. flat thd (>=) for gmv lock decision, default = 0 ++//Bit 15, reserved. ++//Bit 14:12, reg_mcdi_reldetgmvdifthd. dif thd (>=) for current mv different from gmv for gmv dif check, actually used in Lmv lock check, default = 3 ++//Bit 11, reserved. ++//Bit 10: 8, reg_mcdi_reldetgmvdifmin. min mv dif for gmv dif check, default = 1, note: dif between reg_mcdi_rel_det_gmv_dif_max and reg_mcdi_rel_det_gmv_dif_min should be; 0,1,3,7, not work for others ++//Bit 7: 4, reg_mcdi_reldetgmvdifmax. max mv dif for gmv dif check, default = 4 ++//Bit 3: 1, reserved ++//Bit 0, reg_mcdi_reldetgmvdifmvmode. mv mode used for gmv dif check, 0: use refmv, 1: use qmv, default = 0 ++#define MCDI_REL_DET_LMV_DIF_CHK (0x2f30) ++#define P_MCDI_REL_DET_LMV_DIF_CHK (volatile unsigned int *)((0x2f30 << 2) + 0xff900000) ++//Bit 31:24, reserved. ++//Bit 23:16, reg_mcdi_reldetlmvfltthd. flat thd (>=) for lmv lock decision, default = 12 ++//Bit 15:14, reserved. ++//Bit 13:12, reg_mcdi_reldetlmvlockchkmode. lmv lock check mode, 0:cur Lmv, 1: cur & (last | next), 2: last & cur & next Lmv, default = 1 ++//Bit 11, reserved. ++//Bit 10: 8, reg_mcdi_reldetlmvdifmin. min mv dif for lmv dif check, default = 1, note: dif between reg_mcdi_rel_det_lmv_dif_max and reg_mcdi_rel_det_lmv_dif_min should be; 0,1,3,7, not work for others ++//Bit 7: 4, reg_mcdi_reldetlmvdifmax. max mv dif for lmv dif check, default = 4 ++//Bit 3: 1, reserved ++//Bit 0, reg_mcdi_reldetlmvdifmvmode. mv mode used for lmv dif check, 0: use refmv, 1: use qmv, default = 0 ++#define MCDI_REL_DET_FRQ_CHK (0x2f31) ++#define P_MCDI_REL_DET_FRQ_CHK (volatile unsigned int *)((0x2f31 << 2) + 0xff900000) ++//Bit 31:12, reserved. ++//Bit 11: 8, reg_mcdi_reldetfrqgain. gain for frequency check, normalized to 4 as '1', default = 10 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_reldetfrqmax. max value for frequency check, default = 31 ++#define MCDI_REL_DET_PD22_CHK (0x2f32) ++#define P_MCDI_REL_DET_PD22_CHK (volatile unsigned int *)((0x2f32 << 2) + 0xff900000) ++//Bit 31:18, reserved. ++//Bit 17: 8, reg_mcdi_reldetpd22chkoffst. offset for pd22 check happened, default = 512 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_reldetpd22chkgain. gain for pd22 check happened, normalized to 8 as '1', default = 12 ++#define MCDI_REL_DET_RPT_CHK_ROW (0x2f33) ++#define P_MCDI_REL_DET_RPT_CHK_ROW (volatile unsigned int *)((0x2f33 << 2) + 0xff900000) ++//Bit 31:27, reserved ++//Bit 26:16, reg_mcdi_reldetrptchkendrow. end row (<) number for repeat check, default = 2047 ++//Bit 15:11, reserved ++//Bit 10: 0, reg_mcdi_reldetrptchkstartrow. start row (>=) number for repeat check, default = 0 ++#define MCDI_REL_DET_RPT_CHK_GAIN_QMV (0x2f34) ++#define P_MCDI_REL_DET_RPT_CHK_GAIN_QMV (volatile unsigned int *)((0x2f34 << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:24, reg_mcdi_reldetrptchkqmvmax. max thd (<) of abs qmv for repeat check, default = 15, note that quarter mv's range is -63~63 ++//Bit 23:22, reserved ++//Bit 21:16, reg_mcdi_reldetrptchkqmvmin. min thd (>=) of abs qmv for repeat check, default = 10, note that quarter mv's range is -63~63 ++//Bit 15, reserved/ ++//Bit 14: 4, reg_mcdi_reldetrptchkoffst. offset for repeat check, default = 512 ++//Bit 3: 0, reg_mcdi_reldetrptchkgain. gain for repeat check, normalized to 8 as '1', default = 4 ++#define MCDI_REL_DET_RPT_CHK_THD_0 (0x2f35) ++#define P_MCDI_REL_DET_RPT_CHK_THD_0 (volatile unsigned int *)((0x2f35 << 2) + 0xff900000) ++//Bit 31:24, reserved ++//Bit 23:16, reg_mcdi_reldetrptchkzerosadthd. zero sad thd (<) for repeat check, default = 255 ++//Bit 15:14, reserved. ++//Bit 13: 8, reg_mcdi_reldetrptchkzerobadwthd. zero badw thd (>=) for repeat check, default = 16 ++//Bit 7: 4, reserved ++//Bit 3: 0, reg_mcdi_reldetrptchkfrqdifthd. frequency dif thd (<) for repeat check, 0~10, default = 5 ++#define MCDI_REL_DET_RPT_CHK_THD_1 (0x2f36) ++#define P_MCDI_REL_DET_RPT_CHK_THD_1 (volatile unsigned int *)((0x2f36 << 2) + 0xff900000) ++//Bit 31:16, reserved ++//Bit 15: 8, reg_mcdi_reldetrptchkvdifthd. vertical dif thd (<) for repeat check, default = 16 ++//Bit 7: 0, reg_mcdi_reldetrptchkhdifthd. horizontal dif thd (>=) for repeat check, default = 16 ++#define MCDI_REL_DET_LPF_DIF_THD (0x2f37) ++#define P_MCDI_REL_DET_LPF_DIF_THD (volatile unsigned int *)((0x2f37 << 2) + 0xff900000) ++//Bit 31:24, reg_mcdi_reldetlpfdifthd3. hdif thd (<) for lpf selection of horizontal block, default = 9 ++//Bit 23:16, reg_mcdi_reldetlpfdifthd2. vdif-hdif thd (>=) for lpf selection of horizontal block, default = 48 ++//Bit 15: 8, reg_mcdi_reldetlpfdifthd1. vdif thd (<) for lpf selection of vertical block, default = 9 ++//Bit 7: 0, reg_mcdi_reldetlpfdifthd0. hdif-vdif thd (>=) for lpf selection of vertical block, default = 48 ++#define MCDI_REL_DET_LPF_MSK_00_03 (0x2f38) ++#define P_MCDI_REL_DET_LPF_MSK_00_03 (volatile unsigned int *)((0x2f38 << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28:24, reg_mcdi_reldetlpfmsk03. det lpf mask03 for gmv/lmv locked mode, 0~16, default = 1 ++//Bit 23:21, reserved ++//Bit 20:16, reg_mcdi_reldetlpfmsk02. det lpf mask02 for gmv/lmv locked mode, 0~16, default = 1 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_mcdi_reldetlpfmsk01. det lpf mask01 for gmv/lmv locked mode, 0~16, default = 5 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_reldetlpfmsk00. det lpf mask00 for gmv/lmv locked mode, 0~16, default = 8 ++#define MCDI_REL_DET_LPF_MSK_04_12 (0x2f39) ++#define P_MCDI_REL_DET_LPF_MSK_04_12 (volatile unsigned int *)((0x2f39 << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28:24, reg_mcdi_reldetlpfmsk12. det lpf mask12 for vertical blocks, 0~16, default = 0 ++//Bit 23:21, reserved ++//Bit 20:16, reg_mcdi_reldetlpfmsk11. det lpf mask11 for vertical blocks, 0~16, default = 0 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_mcdi_reldetlpfmsk10. det lpf mask10 for vertical blocks, 0~16, default = 16 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_reldetlpfmsk04. det lpf mask04 for gmv/lmv locked mode, 0~16, default = 1 ++#define MCDI_REL_DET_LPF_MSK_13_21 (0x2f3a) ++#define P_MCDI_REL_DET_LPF_MSK_13_21 (volatile unsigned int *)((0x2f3a << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28:24, reg_mcdi_reldetlpfmsk21. det lpf mask21 for horizontal blocks, 0~16, default = 6 ++//Bit 23:21, reserved ++//Bit 20:16, reg_mcdi_reldetlpfmsk20. det lpf mask20 for horizontal blocks, 0~16, default = 8 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_mcdi_reldetlpfmsk14. det lpf mask14 for vertical blocks, 0~16, default = 0 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_reldetlpfmsk13. det lpf mask13 for vertical blocks, 0~16, default = 0 ++#define MCDI_REL_DET_LPF_MSK_22_30 (0x2f3b) ++#define P_MCDI_REL_DET_LPF_MSK_22_30 (volatile unsigned int *)((0x2f3b << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28:24, reg_mcdi_reldetlpfmsk30. det lpf mask30 for other blocks, 0~16, default = 16 ++//Bit 23:21, reserved ++//Bit 20:16, reg_mcdi_reldetlpfmsk24. det lpf mask24 for horizontal blocks, 0~16, default = 1 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_mcdi_reldetlpfmsk23. det lpf mask23 for horizontal blocks, 0~16, default = 0 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_reldetlpfmsk22. det lpf mask22 for horizontal blocks, 0~16, default = 1 ++#define MCDI_REL_DET_LPF_MSK_31_34 (0x2f3c) ++#define P_MCDI_REL_DET_LPF_MSK_31_34 (volatile unsigned int *)((0x2f3c << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28:24, reg_mcdi_reldetlpfmsk34. det lpf mask34 for other blocks, 0~16, default = 0 ++//Bit 23:21, reserved ++//Bit 20:16, reg_mcdi_reldetlpfmsk33. det lpf mask33 for other blocks, 0~16, default = 0 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_mcdi_reldetlpfmsk32. det lpf mask32 for other blocks, 0~16, default = 0 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_reldetlpfmsk31. det lpf mask31 for other blocks, 0~16, default = 0 ++//Note: there are four group lpf masks from addr 37~3b, each group sum equal to 16. ++#define MCDI_REL_DET_MIN (0x2f3d) ++#define P_MCDI_REL_DET_MIN (volatile unsigned int *)((0x2f3d << 2) + 0xff900000) ++//Bit 31: 7, reserved ++//Bit 6: 0, reg_mcdi_reldetmin. min of detected value, default = 16 ++#define MCDI_REL_DET_LUT_0_3 (0x2f3e) ++#define P_MCDI_REL_DET_LUT_0_3 (volatile unsigned int *)((0x2f3e << 2) + 0xff900000) ++//Bit 31:24, reg_mcdi_reldetmaplut3. default = 8 ++//Bit 23:16, reg_mcdi_reldetmaplut2. default = 4 ++//Bit 15: 8, reg_mcdi_reldetmaplut1. default = 2 ++//Bit 7: 0, reg_mcdi_reldetmaplut0. default = 0 ++#define MCDI_REL_DET_LUT_4_7 (0x2f3f) ++#define P_MCDI_REL_DET_LUT_4_7 (volatile unsigned int *)((0x2f3f << 2) + 0xff900000) ++//Bit 31:24, reg_mcdi_reldetmaplut7. default = 64 ++//Bit 23:16, reg_mcdi_reldetmaplut6. default = 48 ++//Bit 15: 8, reg_mcdi_reldetmaplut5. default = 32 ++//Bit 7: 0, reg_mcdi_reldetmaplut4. default = 16 ++#define MCDI_REL_DET_LUT_8_11 (0x2f40) ++#define P_MCDI_REL_DET_LUT_8_11 (volatile unsigned int *)((0x2f40 << 2) + 0xff900000) ++//Bit 31:24, reg_mcdi_reldetmaplut11. default = 160 ++//Bit 23:16, reg_mcdi_reldetmaplut10. default = 128 ++//Bit 15: 8, reg_mcdi_reldetmaplut9. default = 96 ++//Bit 7: 0, reg_mcdi_reldetmaplut8. default = 80 ++#define MCDI_REL_DET_LUT_12_15 (0x2f41) ++#define P_MCDI_REL_DET_LUT_12_15 (volatile unsigned int *)((0x2f41 << 2) + 0xff900000) ++//Bit 31:24, reg_mcdi_reldetmaplut15. default = 255 ++//Bit 23:16, reg_mcdi_reldetmaplut14. default = 240 ++//Bit 15: 8, reg_mcdi_reldetmaplut13. default = 224 ++//Bit 7: 0, reg_mcdi_reldetmaplut12. default = 192 ++#define MCDI_REL_DET_COL_CFD_THD (0x2f42) ++#define P_MCDI_REL_DET_COL_CFD_THD (volatile unsigned int *)((0x2f42 << 2) + 0xff900000) ++//Bit 31:24, reg_mcdi_reldetcolcfdfltthd. thd for flat smaller than (<) of column cofidence, default = 5 ++//Bit 23:16, reg_mcdi_reldetcolcfdthd1. thd for rel larger than (>=) in rel calc. mode col confidence without gmv locking, default = 160 ++//Bit 15: 8, reg_mcdi_reldetcolcfdthd0. thd for rel larger than (>=) in rel calc. mode col confidence when gmv locked, default = 100 ++//Bit 7: 2, reg_mcdi_reldetcolcfdbadwthd. thd for badw larger than (>=) in qbadw calc. mode of column cofidence, default = 16 ++//Bit 1, reserved ++//Bit 0, reg_mcdi_reldetcolcfdcalcmode. calc. mode for column cofidence, 0: use rel, 1: use qbadw, default = 0 ++#define MCDI_REL_DET_COL_CFD_AVG_LUMA (0x2f43) ++#define P_MCDI_REL_DET_COL_CFD_AVG_LUMA (volatile unsigned int *)((0x2f43 << 2) + 0xff900000) ++//Bit 31:24, reg_mcdi_reldetcolcfdavgmin1. avg luma min1 (>=) for column cofidence, valid between 16~235, default = 235 ++//Bit 23:16, reg_mcdi_reldetcolcfdavgmax1. avg luma max1 (<) for column cofidence, valid between 16~235, default = 235 ++//Bit 15: 8, reg_mcdi_reldetcolcfdavgmin0. avg luma min0 (>=) for column cofidence, valid between 16~235, default = 16 ++//Bit 7: 0, reg_mcdi_reldetcolcfdavgmax0. avg luma max0 (<) for column cofidence, valid between 16~235, default = 21 ++#define MCDI_REL_DET_BAD_THD_0 (0x2f44) ++#define P_MCDI_REL_DET_BAD_THD_0 (volatile unsigned int *)((0x2f44 << 2) + 0xff900000) ++//Bit 31:16, reserved ++//Bit 15: 8, reg_mcdi_reldetbadsadthd. thd (>=) for bad sad, default = 120 (480/4) ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_mcdi_reldetbadbadwthd. thd (>=) for bad badw, 0~42, default = 12 ++#define MCDI_REL_DET_BAD_THD_1 (0x2f45) ++#define P_MCDI_REL_DET_BAD_THD_1 (volatile unsigned int *)((0x2f45 << 2) + 0xff900000) ++//Bit 31:24, reserved ++//Bit 23:16, reg_mcdi_reldetbadrelfltthd. thd (>=) of flat for bad rel detection, default = 4 ++//Bit 15: 8, reg_mcdi_reldetbadrelthd1. thd (>=) for bad rel without gmv/lmv locked, default = 160 ++//Bit 7: 0, reg_mcdi_reldetbadrelthd0. thd (>=) for bad rel with gmv/lmv locked, default = 120 ++#define MCDI_PD22_CHK_THD (0x2f46) ++#define P_MCDI_PD22_CHK_THD (volatile unsigned int *)((0x2f46 << 2) + 0xff900000) ++//Bit 31:25, reserved ++//Bit 24:16, reg_mcdi_pd22chksaddifthd. sad dif thd (>=) for (pd22chksad - qsad) for pd22 check, default = 64 ++//Bit 15:14, reserved ++//Bit 13: 8, reg_mcdi_pd22chkqmvthd. thd (>=) of abs qmv for pd22 check, default = 2 ++//Bit 7: 0, reg_mcdi_pd22chkfltthd. thd (>=) of flat for pd22 check, default = 4 ++#define MCDI_PD22_CHK_GAIN_OFFST_0 (0x2f47) ++#define P_MCDI_PD22_CHK_GAIN_OFFST_0 (volatile unsigned int *)((0x2f47 << 2) + 0xff900000) ++//Bit 31:24, reg_mcdi_pd22chkedgeoffst0. offset0 of pd22chkedge from right film22 phase, -128~127, default = 0 ++//Bit 23:21, reserved ++//Bit 20:16, reg_mcdi_pd22chkedgegain0. gain0 of pd22chkedge from right film22 phase, normalized to 16 as '1', default = 16 ++//Bit 15:12, reserved ++//Bit 11: 8, reg_mcdi_pd22chkbadwoffst0. offset0 of pd22chkbadw from right film22 phase, -8~7, default = 0 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_pd22chkbadwgain0. gain0 of pd22chkbadw from right film22 phase, normalized to 16 as '1', default = 8 ++#define MCDI_PD22_CHK_GAIN_OFFST_1 (0x2f48) ++#define P_MCDI_PD22_CHK_GAIN_OFFST_1 (volatile unsigned int *)((0x2f48 << 2) + 0xff900000) ++//Bit 31:24, reg_mcdi_pd22chkedgeoffst1. offset1 of pd22chkedge from right film22 phase, -128~127, default = 0 ++//Bit 23:21, reserved ++//Bit 20:16, reg_mcdi_pd22chkedgegain1. gain1 of pd22chkedge from right film22 phase, normalized to 16 as '1', default = 16 ++//Bit 15:12, reserved ++//Bit 11: 8, reg_mcdi_pd22chkbadwoffst1. offset1 of pd22chkbadw from right film22 phase, -8~7, default = 0 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_pd22chkbadwgain1. gain1 of pd22chkbadw from right film22 phase, normalized to 16 as '1', default = 12 ++#define MCDI_LMV_LOCK_CNT_THD_GAIN (0x2f49) ++#define P_MCDI_LMV_LOCK_CNT_THD_GAIN (volatile unsigned int *)((0x2f49 << 2) + 0xff900000) ++//Bit 31:20, reserved ++//Bit 19:16, reg_mcdi_lmvlockcntmax. max lmv lock count number, default = 6 ++//Bit 15:12, reg_mcdi_lmvlockcntoffst. offset for lmv lock count, -8~7, default = 0 ++//Bit 11: 8, reg_mcdi_lmvlockcntgain. gain for lmv lock count, normalized 8 as '1', 15 is set to 16, default = 8 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_lmvlockcntthd. lmv count thd (>=) before be locked, 1~31, default = 4 ++#define MCDI_LMV_LOCK_ABS_DIF_THD (0x2f4a) ++#define P_MCDI_LMV_LOCK_ABS_DIF_THD (volatile unsigned int *)((0x2f4a << 2) + 0xff900000) ++//Bit 31:27, reserved ++//Bit 26:24, reg_mcdi_lmvlockdifthd2. lmv dif thd for third part, before locked, default = 1 ++//Bit 23, reserved ++//Bit 22:20, reg_mcdi_lmvlockdifthd1. lmv dif thd for second part, before locked, default = 1 ++//Bit 19, reserved ++//Bit 18:16, reg_mcdi_lmvlockdifthd0. lmv dif thd for first part, before locked, default = 1 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_mcdi_lmvlockabsmax. max abs (<) of lmv to be locked, default = 24 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_lmvlockabsmin. min abs (>=) of lmv to be locked, default = 1 ++#define MCDI_LMV_LOCK_ROW (0x2f4b) ++#define P_MCDI_LMV_LOCK_ROW (volatile unsigned int *)((0x2f4b << 2) + 0xff900000) ++//Bit 31:27, reserved ++//Bit 26:16, reg_mcdi_lmvlockendrow. end row (<) for lmv lock, default = 2047 ++//Bit 15:11, reserved ++//Bit 10: 0, reg_mcdi_lmvlockstartrow. start row (>=) for lmv lock, default = 0 ++#define MCDI_LMV_LOCK_RT_MODE (0x2f4c) ++#define P_MCDI_LMV_LOCK_RT_MODE (volatile unsigned int *)((0x2f4c << 2) + 0xff900000) ++//Bit 31:27, reserved ++//Bit 26:24, reg_mcdi_lmvlockextmode. extend lines for lmv lock check, check how many lines for lmv locking, default = 2 ++//Bit 23:16, reg_mcdi_lmvlockfltcntrt. ratio of flt cnt for lock check, normalized 256 as '1', 255 is set to 256, default = 32 ++//Bit 15: 8, reg_mcdi_lmvlocklmvcntrt1. ratio when use non-zero lmv for lock check, normalized 256 as '1', 255 is set to 256, default = 48 ++//Bit 7: 0, reg_mcdi_lmvlocklmvcntrt0. ratio when use max lmv for lock check, normalized 256 as '1', 255 is set to 256, default = 106 ++#define MCDI_GMV_LOCK_CNT_THD_GAIN (0x2f4d) ++#define P_MCDI_GMV_LOCK_CNT_THD_GAIN (volatile unsigned int *)((0x2f4d << 2) + 0xff900000) ++//Bit 31:20, reserved ++//Bit 19:16, reg_mcdi_gmvlockcntmax. max gmv lock count number, default = 6 ++//Bit 15:12, reg_mcdi_gmvlockcntoffst. offset for gmv lock count, -8~7, default = 0 ++//Bit 11: 8, reg_mcdi_gmvlockcntgain. gain for gmv lock count, normalized 8 as '1', 15 is set to 16, default = 8 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_gmvlockcntthd. gmv count thd (>=) before be locked, 1~31, default = 4 ++#define MCDI_GMV_LOCK_ABS_DIF_THD (0x2f4e) ++#define P_MCDI_GMV_LOCK_ABS_DIF_THD (volatile unsigned int *)((0x2f4e << 2) + 0xff900000) ++//Bit 31:27, reserved ++//Bit 26:24, reg_mcdi_gmvlockdifthd2. gmv dif thd for third part, before locked, default = 3 ++//Bit 23, reserved ++//Bit 22:20, reg_mcdi_gmvlockdifthd1. gmv dif thd for second part, before locked, default = 2 ++//Bit 19, reserved ++//Bit 18:16, reg_mcdi_gmvlockdifthd0. gmv dif thd for first part, before locked, default = 1 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_mcdi_gmvlockabsmax. max abs of gmv to be locked, default = 15 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_gmvlockabsmin. min abs of gmv to be locked, default = 1 ++#define MCDI_HIGH_VERT_FRQ_DIF_THD (0x2f4f) ++#define P_MCDI_HIGH_VERT_FRQ_DIF_THD (volatile unsigned int *)((0x2f4f << 2) + 0xff900000) ++//Bit 31: 0, reg_mcdi_highvertfrqfldavgdifthd. high_vert_frq field average luma dif thd (>=), 3*Blk_Width*Blk_Height, set by software, default = 103680 ++#define MCDI_HIGH_VERT_FRQ_DIF_DIF_THD (0x2f50) ++#define P_MCDI_HIGH_VERT_FRQ_DIF_DIF_THD (volatile unsigned int *)((0x2f50 << 2) + 0xff900000) ++//Bit 31: 0, reg_mcdi_highvertfrqfldavgdifdifthd. high_vert_frq field average luma dif's dif thd (<), 3*Blk_Width*Blk_Height, set by software, default = 103680 ++#define MCDI_HIGH_VERT_FRQ_RT_GAIN (0x2f51) ++#define P_MCDI_HIGH_VERT_FRQ_RT_GAIN (volatile unsigned int *)((0x2f51 << 2) + 0xff900000) ++//Bit 31:20, reserved ++//Bit 19:16, reg_mcdi_highvertfrqcntthd. high_vert_frq count thd (>=) before locked, 1~31, default = 4 ++//Bit 15: 8, reg_mcdi_highvertfrqbadsadrt. ratio for high_vert_frq bad sad count, normalized 256 as '1', 255 is set to 256, default = 24 ++//Bit 7: 0, reg_mcdi_highvertfrqbadbadwrt. ratio for high_vert_frq badw count, normalized 256 as '1', 255 is set to 256, default = 130 ++#define MCDI_MOTION_PARADOX_THD (0x2f52) ++#define P_MCDI_MOTION_PARADOX_THD (volatile unsigned int *)((0x2f52 << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28:24, reg_mcdi_motionparadoxcntthd. motion paradox count thd (>=) before locked, 1~31, default = 4 ++//Bit 23:22, reserved ++//Bit 21:16, reg_mcdi_motionparadoxgmvthd. abs gmv thd (<) of motion paradox, 0~32, note that 32 means invalid gmv, be careful, default = 32 ++//Bit 15: 0, reserved ++#define MCDI_MOTION_PARADOX_RT (0x2f53) ++#define P_MCDI_MOTION_PARADOX_RT (volatile unsigned int *)((0x2f53 << 2) + 0xff900000) ++//Bit 31:24, reserved ++//Bit 23:16, reg_mcdi_motionparadoxbadsadrt. ratio for field bad sad count of motion paradox, normalized 256 as '1', 255 is set to 256, default = 24 ++//Bit 15: 8, reg_mcdi_motionparadoxbadrelrt. ratio for field bad reliabilty count of motion paradox, normalized 256 as '1', 255 is set to 256, default = 120 ++//Bit 7: 0, reg_mcdi_motionparadoxmtnrt. ratio for field motion count of motion paradox, normalized 256 as '1', 255 is set to 256, default = 218 ++#define MCDI_MOTION_REF_THD (0x2f54) ++#define P_MCDI_MOTION_REF_THD (volatile unsigned int *)((0x2f54 << 2) + 0xff900000) ++//Bit 31:24, reserved ++//Bit 23:20, reg_mcdi_motionrefoffst. motion ref additive offset, default = 15 ++//Bit 19:16, reg_mcdi_motionrefgain. motion ref gain, normalized 8 as '1', default = 8 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_mcdi_motionrefrptmvthd. abs thd (>=) of rpt mv (0~31, 32 means invalid) for motion ref, default = 1 ++//Bit 7: 2, reg_mcdi_motionrefqmvthd. min thd (>=) of abs qmv for motion ref, note that quarter mv's range is -63~63, default = 2 ++//Bit 1: 0, reg_mcdi_motionreflpfmode. Mv and (8 x repeat flg) 's lpf mode of motion refinement, 0: no lpf, 1: [1 2 1], 2: [1 2 2 2 1], default = 1 ++#define MCDI_REL_COL_REF_RT (0x2f55) ++#define P_MCDI_REL_COL_REF_RT (volatile unsigned int *)((0x2f55 << 2) + 0xff900000) ++//Bit 31: 8, reserved ++//Bit 7: 0, reg_mcdi_relcolrefrt. ratio for column cofidence level against column number, for refinement, default = 135 ++#define MCDI_PD22_CHK_THD_RT (0x2f56) ++#define P_MCDI_PD22_CHK_THD_RT (volatile unsigned int *)((0x2f56 << 2) + 0xff900000) ++//Bit 31:27, reserved ++//Bit 26:16, reg_mcdi_pd22chkfltcntrt. ratio for flat count of field pulldown 22 check, normalized 2048 as '1', 2047 is set to 2048, default = 1 ++//Bit 15: 8, reg_mcdi_pd22chkcntrt. ratio of pulldown 22 check count, normalized 256 as '1', 255 is set to 256, default = 100 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_pd22chkcntthd. thd (>=) for pd22 count before locked, 1~31, default = 4 ++#define MCDI_CHAR_DET_DIF_THD (0x2f57) ++#define P_MCDI_CHAR_DET_DIF_THD (volatile unsigned int *)((0x2f57 << 2) + 0xff900000) ++//Bit 31:24, reserved ++//Bit 23:16, reg_mcdi_chardetminmaxdifthd. thd (>=) for dif between min and max value, default = 64 ++//Bit 15: 8, reg_mcdi_chardetmaxdifthd. thd (<) for dif between max value, default = 17 ++//Bit 7: 0, reg_mcdi_chardetmindifthd. thd (<) for dif between min value, default = 17 ++#define MCDI_CHAR_DET_CNT_THD (0x2f58) ++#define P_MCDI_CHAR_DET_CNT_THD (volatile unsigned int *)((0x2f58 << 2) + 0xff900000) ++//Bit 31:21, reserved ++//Bit 20:16, reg_mcdi_chardettotcntthd. thd (>=) for total count, 0~21, default = 18 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_mcdi_chardetmaxcntthd. thd (>=) for max count, 0~21, default = 1 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_chardetmincntthd. thd (>=) for min count, 0~21, default = 1 ++//new add ++#define MCDI_PD_22_CHK_WND0_X (0x2f59) ++#define P_MCDI_PD_22_CHK_WND0_X (volatile unsigned int *)((0x2f59 << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28:16, reg_mcdi_pd22chkwnd0_x1 u13, x1 for window 0, HSIZE-1, software control, default = 719 ++//Bit 15:13, reserved ++//Bit 12: 0, reg_mcdi_pd22chkwnd0_x0 u13, x0 for window 0, software control, default = 0 ++#define MCDI_PD_22_CHK_WND0_Y (0x2f5a) ++#define P_MCDI_PD_22_CHK_WND0_Y (volatile unsigned int *)((0x2f5a << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28:16, reg_mcdi_pd22chkwnd0_y1 u13, y1 for window 0 software control, default = 39 ++//Bit 15:13, reserved ++//Bit 12: 0, reg_mcdi_pd22chkwnd0_y0 u13, y0 for window 0, software control, default = 0 ++#define MCDI_PD_22_CHK_WND1_X (0x2f5b) ++#define P_MCDI_PD_22_CHK_WND1_X (volatile unsigned int *)((0x2f5b << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28:16, reg_mcdi_pd22chkwnd1_x1 u13, x1 for window 1, HSIZE-1, software control, default = 719 ++//Bit 15:13, reserved ++//Bit 12: 0, reg_mcdi_pd22chkwnd1_x0 u13, x0 for window 1, software control, default = 0 ++#define MCDI_PD_22_CHK_WND1_Y (0x2f5c) ++#define P_MCDI_PD_22_CHK_WND1_Y (volatile unsigned int *)((0x2f5c << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28:16, reg_mcdi_pd22chkwnd1_y1 u13, y1 for window 1 software control, default = 199 ++//Bit 15:13, reserved ++//Bit 12: 0, reg_mcdi_pd22chkwnd1_y0 u13, y0 for window 1, software control, default = 40 ++#define MCDI_PD_22_CHK_FRC_LMV (0x2f5d) ++#define P_MCDI_PD_22_CHK_FRC_LMV (volatile unsigned int *)((0x2f5d << 2) + 0xff900000) ++//Bit 31:11, reserved ++//Bit 10, reg_mcdi_pd22chklmvchk2 u1, lmv lock check while force vof for each windows, default = 1 ++//Bit 9, reg_mcdi_pd22chklmvchk1 u1, lmv lock check while force vof for each windows, default = 0 ++//Bit 8, reg_mcdi_pd22chklmvchk0 u1, lmv lock check while force vof for each windows, default = 0 ++//Bit 7, reserved ++//Bit 6, reg_mcdi_pd22chkfrcpd2 u1, force pd flags for each windows, default = 0 ++//Bit 5, reg_mcdi_pd22chkfrcpd1 u1, force pd flags for each windows, default = 0 ++//Bit 4, reg_mcdi_pd22chkfrcpd0 u1, force pd flags for each windows, default = 0 ++//Bit 3, reserved ++//Bit 2, reg_mcdi_pd22chkfrcvof2 u1, force vof flags for each windows, default = 1 ++//Bit 1, reg_mcdi_pd22chkfrcvof1 u1, force vof flags for each windows, default = 0 ++//Bit 0, reg_mcdi_pd22chkfrcvof0 u1, force vof flags for each windows, default = 0 ++#define MCDI_PD_22_CHK_FLG_CNT (0x2f5e) ++#define P_MCDI_PD_22_CHK_FLG_CNT (volatile unsigned int *)((0x2f5e << 2) + 0xff900000) ++//Bit 31:27, reserved. ++//Bit 26, reg_mcdi_pd22chkflg2. pull down 22 flag of prevoius one field. initial = 0 ++//Bit 25, reg_mcdi_pd22chkflg1. pull down 22 flag of prevoius one field. initial = 0 ++//Bit 24, reg_mcdi_pd22chkflg. pull down 22 flag of prevoius one field. initial = 0 ++//Bit 23:16, reg_mcdi_pd22chkcnt2. pull down 22 count till prevoius one field. initial = 0 ++//Bit 15: 8, reg_mcdi_pd22chkcnt1. pull down 22 count till prevoius one field. initial = 0 ++//Bit 7: 0, reg_mcdi_pd22chkcnt. pull down 22 count till prevoius one field. initial = 0 ++#define MCDI_RO_FLD_PD_22_PRE_CNT1 (0x2fca) ++#define P_MCDI_RO_FLD_PD_22_PRE_CNT1 (volatile unsigned int *)((0x2fca << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_fldpd22precnt1. prevoius pd22 check count of whole pre one field (block based). initial = 0 ++#define MCDI_RO_FLD_PD_22_FOR_CNT1 (0x2fcb) ++#define P_MCDI_RO_FLD_PD_22_FOR_CNT1 (volatile unsigned int *)((0x2fcb << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_fldpd22forcnt1. forward pd22 check count of whole pre one field (block based). initial = 0 ++#define MCDI_RO_FLD_PD_22_FLT_CNT1 (0x2fcc) ++#define P_MCDI_RO_FLD_PD_22_FLT_CNT1 (volatile unsigned int *)((0x2fcc << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_fldpd22fltcnt1. flat count (for pd22 check) of whole pre one field (block based). initial = 0 ++#define MCDI_RO_FLD_PD_22_PRE_CNT2 (0x2fcd) ++#define P_MCDI_RO_FLD_PD_22_PRE_CNT2 (volatile unsigned int *)((0x2fcd << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_fldpd22precnt2. prevoius pd22 check count of whole pre one field (block based). initial = 0 ++#define MCDI_RO_FLD_PD_22_FOR_CNT2 (0x2fce) ++#define P_MCDI_RO_FLD_PD_22_FOR_CNT2 (volatile unsigned int *)((0x2fce << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_fldpd22forcnt2. forward pd22 check count of whole pre one field (block based). initial = 0 ++#define MCDI_RO_FLD_PD_22_FLT_CNT2 (0x2fcf) ++#define P_MCDI_RO_FLD_PD_22_FLT_CNT2 (volatile unsigned int *)((0x2fcf << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_fldpd22fltcnt2. flat count (for pd22 check) of whole pre one field (block based). initial = 0 ++#define MCDI_FIELD_MV (0x2f60) ++#define P_MCDI_FIELD_MV (volatile unsigned int *)((0x2f60 << 2) + 0xff900000) ++//Bit 31:24, reg_mcdi_pd22chkcnt ++//Bit 23:16, reg_mcdi_fieldgmvcnt ++//Bit 15, reg_mcdi_pd22chkflg ++//Bit 14, reg_mcdi_fieldgmvlock ++//Bit 13: 8, reg_mcdi_fieldrptmv. last field rpt mv ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_mcdi_fieldgmv. last field gmv ++#define MCDI_FIELD_HVF_PRDX_CNT (0x2f61) ++#define P_MCDI_FIELD_HVF_PRDX_CNT (volatile unsigned int *)((0x2f61 << 2) + 0xff900000) ++//Bit 31:24, reg_mcdi_motionparadoxcnt. ++//Bit 23:17, reserved ++//Bit 16, reg_mcdi_motionparadoxflg. ++//Bit 15: 8, reg_mcdi_highvertfrqcnt. ++//Bit 7: 4, reserved ++//Bit 3: 2, reg_mcdi_highvertfrqphase. ++//Bit 1, reserved ++//Bit 0, reg_mcdi_highvertfrqflg. ++#define MCDI_FIELD_LUMA_AVG_SUM_0 (0x2f62) ++#define P_MCDI_FIELD_LUMA_AVG_SUM_0 (volatile unsigned int *)((0x2f62 << 2) + 0xff900000) ++//Bit 31: 0, reg_mcdi_fld_luma_avg_sum0. ++#define MCDI_FIELD_LUMA_AVG_SUM_1 (0x2f63) ++#define P_MCDI_FIELD_LUMA_AVG_SUM_1 (volatile unsigned int *)((0x2f63 << 2) + 0xff900000) ++//Bit 31: 0, reg_mcdi_fld_luma_avg_sum1. ++#define MCDI_YCBCR_BLEND_CRTL (0x2f64) ++#define P_MCDI_YCBCR_BLEND_CRTL (volatile unsigned int *)((0x2f64 << 2) + 0xff900000) ++//Bit 31:16, reserved ++//Bit 15: 8, reg_mcdi_ycbcrblendgain. ycbcr blending gain for cbcr in ycbcr. default = 0 ++//Bit 7: 2, reserved. ++//Bit 1: 0, reg_mcdi_ycbcrblendmode. 0:y+cmb(cb,cr), 1:med(r,g,b), 2:max(r,g,b), default = 2 ++#define MCDI_MCVECWR_CANVAS_SIZE (0x2f65) ++#define P_MCDI_MCVECWR_CANVAS_SIZE (volatile unsigned int *)((0x2f65 << 2) + 0xff900000) ++#define MCDI_MCVECRD_CANVAS_SIZE (0x2f66) ++#define P_MCDI_MCVECRD_CANVAS_SIZE (volatile unsigned int *)((0x2f66 << 2) + 0xff900000) ++#define MCDI_MCINFOWR_CANVAS_SIZE (0x2f67) ++#define P_MCDI_MCINFOWR_CANVAS_SIZE (volatile unsigned int *)((0x2f67 << 2) + 0xff900000) ++#define MCDI_MCINFORD_CANVAS_SIZE (0x2f68) ++#define P_MCDI_MCINFORD_CANVAS_SIZE (volatile unsigned int *)((0x2f68 << 2) + 0xff900000) ++#define MCDI_MCVECWR_X (0x2f92) ++#define P_MCDI_MCVECWR_X (volatile unsigned int *)((0x2f92 << 2) + 0xff900000) ++#define MCDI_MCVECWR_Y (0x2f93) ++#define P_MCDI_MCVECWR_Y (volatile unsigned int *)((0x2f93 << 2) + 0xff900000) ++#define MCDI_MCVECWR_CTRL (0x2f94) ++#define P_MCDI_MCVECWR_CTRL (volatile unsigned int *)((0x2f94 << 2) + 0xff900000) ++#define MCDI_MCVECRD_X (0x2f95) ++#define P_MCDI_MCVECRD_X (volatile unsigned int *)((0x2f95 << 2) + 0xff900000) ++#define MCDI_MCVECRD_Y (0x2f96) ++#define P_MCDI_MCVECRD_Y (volatile unsigned int *)((0x2f96 << 2) + 0xff900000) ++#define MCDI_MCVECRD_CTRL (0x2f97) ++#define P_MCDI_MCVECRD_CTRL (volatile unsigned int *)((0x2f97 << 2) + 0xff900000) ++#define MCDI_MCINFOWR_X (0x2f98) ++#define P_MCDI_MCINFOWR_X (volatile unsigned int *)((0x2f98 << 2) + 0xff900000) ++#define MCDI_MCINFOWR_Y (0x2f99) ++#define P_MCDI_MCINFOWR_Y (volatile unsigned int *)((0x2f99 << 2) + 0xff900000) ++#define MCDI_MCINFOWR_CTRL (0x2f9a) ++#define P_MCDI_MCINFOWR_CTRL (volatile unsigned int *)((0x2f9a << 2) + 0xff900000) ++#define MCDI_MCINFORD_X (0x2f9b) ++#define P_MCDI_MCINFORD_X (volatile unsigned int *)((0x2f9b << 2) + 0xff900000) ++#define MCDI_MCINFORD_Y (0x2f9c) ++#define P_MCDI_MCINFORD_Y (volatile unsigned int *)((0x2f9c << 2) + 0xff900000) ++#define MCDI_MCINFORD_CTRL (0x2f9d) ++#define P_MCDI_MCINFORD_CTRL (volatile unsigned int *)((0x2f9d << 2) + 0xff900000) ++// ================================================================== MC registers ======================================================================================================== ++#define MCDI_MC_CRTL (0x2f70) ++#define P_MCDI_MC_CRTL (volatile unsigned int *)((0x2f70 << 2) + 0xff900000) ++//Bit 31: 9, reserved ++//Bit 8, reg_mcdi_mcpreflg. flag to use previous field for MC, 0:forward field, 1: previous field, default = 1 ++//Bit 7, reg_mcdi_mcrelrefbycolcfden. enable rel refinement by column cofidence in mc blending, default = 1 ++//Bit 6: 5, reg_mcdi_mclpfen. enable mc pixles/rel lpf, 0:disable, 1: lpf rel, 2: lpf mc pxls, 3: lpf both rel and mc pxls, default = 0 ++//Bit 4: 2, reg_mcdi_mcdebugmode. enable mc debug mode, 0:disable, 1: split left/right, 2: split top/bottom, 3: debug mv, 4: debug rel, default = 0 ++//Bit 1: 0, reg_mcdi_mcen. mcdi enable mode, 0:disable, 1: blend with ma, 2: full mc, default = 1 ++#define MCDI_MC_LPF_MSK_0 (0x2f71) ++#define P_MCDI_MC_LPF_MSK_0 (volatile unsigned int *)((0x2f71 << 2) + 0xff900000) ++//Bit 31:21, reserved ++//Bit 20:16, reg_mcdi_mclpfmsk02. mc lpf coef. 2 for pixel 0 of current block, normalized 16 as '1', default = 0 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_mcdi_mclpfmsk01. mc lpf coef. 1 for pixel 0 of current block, normalized 16 as '1', default = 9 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_mclpfmsk00. mc lpf coef. 0 for pixel 0 of current block, normalized 16 as '1', default = 7 ++#define MCDI_MC_LPF_MSK_1 (0x2f72) ++#define P_MCDI_MC_LPF_MSK_1 (volatile unsigned int *)((0x2f72 << 2) + 0xff900000) ++//Bit 31:21, reserved ++//Bit 20:16, reg_mcdi_mclpfmsk12. mc lpf coef. 2 for pixel 1 of current block, 0~16, normalized 16 as '1', default = 0 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_mcdi_mclpfmsk11. mc lpf coef. 1 for pixel 1 of current block, 0~16, normalized 16 as '1', default = 11 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_mclpfmsk10. mc lpf coef. 0 for pixel 1 of current block, 0~16, normalized 16 as '1', default = 5 ++#define MCDI_MC_LPF_MSK_2 (0x2f73) ++#define P_MCDI_MC_LPF_MSK_2 (volatile unsigned int *)((0x2f73 << 2) + 0xff900000) ++//Bit 31:21, reserved ++//Bit 20:16, reg_mcdi_mclpfmsk22. mc lpf coef. 2 for pixel 2 of current block, 0~16, normalized 16 as '1', default = 1 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_mcdi_mclpfmsk21. mc lpf coef. 1 for pixel 2 of current block, 0~16, normalized 16 as '1', default = 14 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_mclpfmsk20. mc lpf coef. 0 for pixel 2 of current block, 0~16, normalized 16 as '1', default = 1 ++#define MCDI_MC_LPF_MSK_3 (0x2f74) ++#define P_MCDI_MC_LPF_MSK_3 (volatile unsigned int *)((0x2f74 << 2) + 0xff900000) ++//Bit 31:21, reserved ++//Bit 20:16, reg_mcdi_mclpfmsk32. mc lpf coef. 2 for pixel 3 of current block, 0~16, normalized 16 as '1', default = 5 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_mcdi_mclpfmsk31. mc lpf coef. 1 for pixel 3 of current block, 0~16, normalized 16 as '1', default = 11 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_mclpfmsk30. mc lpf coef. 0 for pixel 3 of current block, 0~16, normalized 16 as '1', default = 0 ++#define MCDI_MC_LPF_MSK_4 (0x2f75) ++#define P_MCDI_MC_LPF_MSK_4 (volatile unsigned int *)((0x2f75 << 2) + 0xff900000) ++//Bit 31:21, reserved ++//Bit 20:16, reg_mcdi_mclpfmsk42. mc lpf coef. 2 for pixel 4 of current block, 0~16, normalized 16 as '1', default = 7 ++//Bit 15:13, reserved ++//Bit 12: 8, reg_mcdi_mclpfmsk41. mc lpf coef. 1 for pixel 4 of current block, 0~16, normalized 16 as '1', default = 9 ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_mcdi_mclpfmsk40. mc lpf coef. 0 for pixel 4 of current block, 0~16, normalized 16 as '1', default = 0 ++#define MCDI_MC_REL_GAIN_OFFST_0 (0x2f76) ++#define P_MCDI_MC_REL_GAIN_OFFST_0 (volatile unsigned int *)((0x2f76 << 2) + 0xff900000) ++//Bit 31:26, reserved ++//Bit 25, reg_mcdi_mcmotionparadoxflg. flag of motion paradox, initial with 0 and read from software, default = 0 ++//Bit 24, reg_mcdi_mchighvertfrqflg. flag of high vert frq, initial with 0 and read from software, default = 0 ++//Bit 23:16, reg_mcdi_mcmotionparadoxoffst. offset (rel + offset) for rel (MC blending coef.) refinement if motion paradox detected before MC blending before MC blending, default = 128 ++//Bit 15:12, reserved ++//Bit 11: 8, reg_mcdi_mcmotionparadoxgain. gain for rel (MC blending coef.) refinement if motion paradox detected before MC blending, normalized 8 as '1', set 15 to 16, default = 8 ++//Bit 7: 4, reg_mcdi_mchighvertfrqoffst. minus offset (alpha - offset) for motion (MA blending coef.) refinement if high vertical frequency detected before MA blending, default = 15 ++//Bit 3: 0, reg_mcdi_mchighvertfrqgain. gain for motion (MA blending coef.) refinement if high vertical frequency detected before MA blending, normalized 8 as '1', set 15 to 16, default = 8 ++#define MCDI_MC_REL_GAIN_OFFST_1 (0x2f77) ++#define P_MCDI_MC_REL_GAIN_OFFST_1 (volatile unsigned int *)((0x2f77 << 2) + 0xff900000) ++//Bit 31:24, reg_mcdi_mcoutofboundrayoffst. offset (rel + offset) for rel (MC blending coef.) refinement if MC pointed out of boundray before MC blending before MC blending, default = 255 ++//Bit 23:20, reserved ++//Bit 19:16, reg_mcdi_mcoutofboundraygain. gain for rel (MC blending coef.) refinement if MC pointed out of boundray before MC blending, normalized 8 as '1', set 15 to 16, default = 8 ++//Bit 15: 8, reg_mcdi_mcrelrefbycolcfdoffst. offset (rel + offset) for rel (MC blending coef.) refinement if motion paradox detected before MC blending before MC blending, default = 255 ++//Bit 7: 4, reserved. ++//Bit 3: 0, reg_mcdi_mcrelrefbycolcfdgain. gain for rel (MC blending coef.) refinement if column cofidence failed before MC blending, normalized 8 as '1', set 15 to 16, default = 8 ++#define MCDI_MC_COL_CFD_0 (0x2f78) ++#define P_MCDI_MC_COL_CFD_0 (volatile unsigned int *)((0x2f78 << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_0. column cofidence value 0 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_1 (0x2f79) ++#define P_MCDI_MC_COL_CFD_1 (volatile unsigned int *)((0x2f79 << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_1. column cofidence value 1 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_2 (0x2f7a) ++#define P_MCDI_MC_COL_CFD_2 (volatile unsigned int *)((0x2f7a << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_2. column cofidence value 2 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_3 (0x2f7b) ++#define P_MCDI_MC_COL_CFD_3 (volatile unsigned int *)((0x2f7b << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_3. column cofidence value 3 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_4 (0x2f7c) ++#define P_MCDI_MC_COL_CFD_4 (volatile unsigned int *)((0x2f7c << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_4. column cofidence value 4 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_5 (0x2f7d) ++#define P_MCDI_MC_COL_CFD_5 (volatile unsigned int *)((0x2f7d << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_5. column cofidence value 5 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_6 (0x2f7e) ++#define P_MCDI_MC_COL_CFD_6 (volatile unsigned int *)((0x2f7e << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_6. column cofidence value 6 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_7 (0x2f7f) ++#define P_MCDI_MC_COL_CFD_7 (volatile unsigned int *)((0x2f7f << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_7. column cofidence value 7 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_8 (0x2f80) ++#define P_MCDI_MC_COL_CFD_8 (volatile unsigned int *)((0x2f80 << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_8. column cofidence value 8 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_9 (0x2f81) ++#define P_MCDI_MC_COL_CFD_9 (volatile unsigned int *)((0x2f81 << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_9. column cofidence value 9 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_10 (0x2f82) ++#define P_MCDI_MC_COL_CFD_10 (volatile unsigned int *)((0x2f82 << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_10. column cofidence value 10 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_11 (0x2f83) ++#define P_MCDI_MC_COL_CFD_11 (volatile unsigned int *)((0x2f83 << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_11. column cofidence value 11 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_12 (0x2f84) ++#define P_MCDI_MC_COL_CFD_12 (volatile unsigned int *)((0x2f84 << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_12. column cofidence value 12 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_13 (0x2f85) ++#define P_MCDI_MC_COL_CFD_13 (volatile unsigned int *)((0x2f85 << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_13. column cofidence value 13 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_14 (0x2f86) ++#define P_MCDI_MC_COL_CFD_14 (volatile unsigned int *)((0x2f86 << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_14. column cofidence value 14 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_15 (0x2f87) ++#define P_MCDI_MC_COL_CFD_15 (volatile unsigned int *)((0x2f87 << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_15. column cofidence value 15 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_16 (0x2f88) ++#define P_MCDI_MC_COL_CFD_16 (volatile unsigned int *)((0x2f88 << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_16. column cofidence value 16 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_17 (0x2f89) ++#define P_MCDI_MC_COL_CFD_17 (volatile unsigned int *)((0x2f89 << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_17. column cofidence value 17 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_18 (0x2f8a) ++#define P_MCDI_MC_COL_CFD_18 (volatile unsigned int *)((0x2f8a << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_18. column cofidence value 18 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_19 (0x2f8b) ++#define P_MCDI_MC_COL_CFD_19 (volatile unsigned int *)((0x2f8b << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_19. column cofidence value 19 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_20 (0x2f8c) ++#define P_MCDI_MC_COL_CFD_20 (volatile unsigned int *)((0x2f8c << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_20. column cofidence value 20 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_21 (0x2f8d) ++#define P_MCDI_MC_COL_CFD_21 (volatile unsigned int *)((0x2f8d << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_21. column cofidence value 21 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_22 (0x2f8e) ++#define P_MCDI_MC_COL_CFD_22 (volatile unsigned int *)((0x2f8e << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_22. column cofidence value 22 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_23 (0x2f8f) ++#define P_MCDI_MC_COL_CFD_23 (volatile unsigned int *)((0x2f8f << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_23. column cofidence value 23 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_24 (0x2f90) ++#define P_MCDI_MC_COL_CFD_24 (volatile unsigned int *)((0x2f90 << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_24. column cofidence value 24 read from software. initial = 0 ++#define MCDI_MC_COL_CFD_25 (0x2f91) ++#define P_MCDI_MC_COL_CFD_25 (volatile unsigned int *)((0x2f91 << 2) + 0xff900000) ++//Bit 31: 0, mcdi_mc_col_cfd_25. column cofidence value 25 read from software. initial = 0 ++// ===================================================================================== PRE RO Registers ========================================================================================== ++#define MCDI_RO_FLD_LUMA_AVG_SUM (0x2fa0) ++#define P_MCDI_RO_FLD_LUMA_AVG_SUM (volatile unsigned int *)((0x2fa0 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_fldlumaavgsum. block's luma avg sum of current filed (block based). initial = 0 ++#define MCDI_RO_GMV_VLD_CNT (0x2fa1) ++#define P_MCDI_RO_GMV_VLD_CNT (volatile unsigned int *)((0x2fa1 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_gmvvldcnt. valid gmv's count of pre one filed (block based). initial = 0 ++#define MCDI_RO_RPT_FLG_CNT (0x2fa2) ++#define P_MCDI_RO_RPT_FLG_CNT (volatile unsigned int *)((0x2fa2 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_rptflgcnt. repeat mv's count of pre one filed (block based). initial = 0 ++#define MCDI_RO_FLD_BAD_SAD_CNT (0x2fa3) ++#define P_MCDI_RO_FLD_BAD_SAD_CNT (volatile unsigned int *)((0x2fa3 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_fldbadsadcnt. bad sad count of whole pre one field (block based). initial = 0 ++#define MCDI_RO_FLD_BAD_BADW_CNT (0x2fa4) ++#define P_MCDI_RO_FLD_BAD_BADW_CNT (volatile unsigned int *)((0x2fa4 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_fldbadbadwcnt. bad badw count of whole pre one field (block based). initial = 0 ++#define MCDI_RO_FLD_BAD_REL_CNT (0x2fa5) ++#define P_MCDI_RO_FLD_BAD_REL_CNT (volatile unsigned int *)((0x2fa5 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_fldbadrelcnt. bad rel count of whole pre one field (block based). initial = 0 ++#define MCDI_RO_FLD_MTN_CNT (0x2fa6) ++#define P_MCDI_RO_FLD_MTN_CNT (volatile unsigned int *)((0x2fa6 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_fldmtncnt. motion count of whole pre one field (pixel based). initial = 0 ++#define MCDI_RO_FLD_VLD_CNT (0x2fa7) ++#define P_MCDI_RO_FLD_VLD_CNT (volatile unsigned int *)((0x2fa7 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_fldvldcnt. valid motion count of whole pre one field (pixel based). initial = 0 ++#define MCDI_RO_FLD_PD_22_PRE_CNT (0x2fa8) ++#define P_MCDI_RO_FLD_PD_22_PRE_CNT (volatile unsigned int *)((0x2fa8 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_fldpd22precnt. prevoius pd22 check count of whole pre one field (block based). initial = 0 ++#define MCDI_RO_FLD_PD_22_FOR_CNT (0x2fa9) ++#define P_MCDI_RO_FLD_PD_22_FOR_CNT (volatile unsigned int *)((0x2fa9 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_fldpd22forcnt. forward pd22 check count of whole pre one field (block based). initial = 0 ++#define MCDI_RO_FLD_PD_22_FLT_CNT (0x2faa) ++#define P_MCDI_RO_FLD_PD_22_FLT_CNT (volatile unsigned int *)((0x2faa << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_fldpd22fltcnt. flat count (for pd22 check) of whole pre one field (block based). initial = 0 ++#define MCDI_RO_HIGH_VERT_FRQ_FLG (0x2fab) ++#define P_MCDI_RO_HIGH_VERT_FRQ_FLG (volatile unsigned int *)((0x2fab << 2) + 0xff900000) ++//Bit 31:16, reserved. ++//Bit 15: 8, ro_mcdi_highvertfrqcnt. high vertical frequency count till prevoius one field. initial = 0 ++//Bit 7: 3, reserved. ++//Bit 2: 1, ro_mcdi_highvertfrqphase. high vertical frequency phase of prevoius one field. initial = 2 ++//Bit 0, ro_mcdi_highvertfrqflg. high vertical frequency flag of prevoius one field. initial = 0 ++#define MCDI_RO_GMV_LOCK_FLG (0x2fac) ++#define P_MCDI_RO_GMV_LOCK_FLG (volatile unsigned int *)((0x2fac << 2) + 0xff900000) ++//Bit 31:16, reserved. ++//Bit 15: 8, ro_mcdi_gmvlckcnt. global mv lock count till prevoius one field. initial = 0 ++//Bit 7: 2, ro_mcdi_gmv. global mv of prevoius one field. -31~31, initial = 32 (invalid value) ++//Bit 1, ro_mcdi_zerogmvlckflg. zero global mv lock flag of prevoius one field. initial = 0 ++//Bit 0, ro_mcdi_gmvlckflg. global mv lock flag of prevoius one field. initial = 0 ++#define MCDI_RO_RPT_MV (0x2fad) ++#define P_MCDI_RO_RPT_MV (volatile unsigned int *)((0x2fad << 2) + 0xff900000) ++//Bit 5: 0, ro_mcdi_rptmv. repeate mv of prevoius one field. -31~31, initial = 32 (invalid value) ++#define MCDI_RO_MOTION_PARADOX_FLG (0x2fae) ++#define P_MCDI_RO_MOTION_PARADOX_FLG (volatile unsigned int *)((0x2fae << 2) + 0xff900000) ++//Bit 31:16, reserved. ++//Bit 15: 8, ro_mcdi_motionparadoxcnt. motion paradox count till prevoius one field. initial = 0 ++//Bit 7: 1, reserved. ++//Bit 0, ro_mcdi_motionparadoxflg. motion paradox flag of prevoius one field. initial = 0 ++#define MCDI_RO_PD_22_FLG (0x2faf) ++#define P_MCDI_RO_PD_22_FLG (volatile unsigned int *)((0x2faf << 2) + 0xff900000) ++//Bit 31:27, reserved. ++//Bit 26, ro_mcdi_pd22flg2. pull down 22 flag of prevoius one field. initial = 0 ++//Bit 25, ro_mcdi_pd22flg1. pull down 22 flag of prevoius one field. initial = 0 ++//Bit 24, ro_mcdi_pd22flg. pull down 22 flag of prevoius one field. initial = 0 ++//Bit 23:16, ro_mcdi_pd22cnt2. pull down 22 count till prevoius one field. initial = 0 ++//Bit 15: 8, ro_mcdi_pd22cnt1. pull down 22 count till prevoius one field. initial = 0 ++//Bit 7: 0, ro_mcdi_pd22cnt. pull down 22 count till prevoius one field. initial = 0 ++#define MCDI_RO_COL_CFD_0 (0x2fb0) ++#define P_MCDI_RO_COL_CFD_0 (volatile unsigned int *)((0x2fb0 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_0. column cofidence value 0. initial = 0 ++#define MCDI_RO_COL_CFD_1 (0x2fb1) ++#define P_MCDI_RO_COL_CFD_1 (volatile unsigned int *)((0x2fb1 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_1. column cofidence value 1. initial = 0 ++#define MCDI_RO_COL_CFD_2 (0x2fb2) ++#define P_MCDI_RO_COL_CFD_2 (volatile unsigned int *)((0x2fb2 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_2. column cofidence value 2. initial = 0 ++#define MCDI_RO_COL_CFD_3 (0x2fb3) ++#define P_MCDI_RO_COL_CFD_3 (volatile unsigned int *)((0x2fb3 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_3. column cofidence value 3. initial = 0 ++#define MCDI_RO_COL_CFD_4 (0x2fb4) ++#define P_MCDI_RO_COL_CFD_4 (volatile unsigned int *)((0x2fb4 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_4. column cofidence value 4. initial = 0 ++#define MCDI_RO_COL_CFD_5 (0x2fb5) ++#define P_MCDI_RO_COL_CFD_5 (volatile unsigned int *)((0x2fb5 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_5. column cofidence value 5. initial = 0 ++#define MCDI_RO_COL_CFD_6 (0x2fb6) ++#define P_MCDI_RO_COL_CFD_6 (volatile unsigned int *)((0x2fb6 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_6. column cofidence value 6. initial = 0 ++#define MCDI_RO_COL_CFD_7 (0x2fb7) ++#define P_MCDI_RO_COL_CFD_7 (volatile unsigned int *)((0x2fb7 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_7. column cofidence value 7. initial = 0 ++#define MCDI_RO_COL_CFD_8 (0x2fb8) ++#define P_MCDI_RO_COL_CFD_8 (volatile unsigned int *)((0x2fb8 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_8. column cofidence value 8. initial = 0 ++#define MCDI_RO_COL_CFD_9 (0x2fb9) ++#define P_MCDI_RO_COL_CFD_9 (volatile unsigned int *)((0x2fb9 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_9. column cofidence value 9. initial = 0 ++#define MCDI_RO_COL_CFD_10 (0x2fba) ++#define P_MCDI_RO_COL_CFD_10 (volatile unsigned int *)((0x2fba << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_10. column cofidence value 10. initial = 0 ++#define MCDI_RO_COL_CFD_11 (0x2fbb) ++#define P_MCDI_RO_COL_CFD_11 (volatile unsigned int *)((0x2fbb << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_11. column cofidence value 11. initial = 0 ++#define MCDI_RO_COL_CFD_12 (0x2fbc) ++#define P_MCDI_RO_COL_CFD_12 (volatile unsigned int *)((0x2fbc << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_12. column cofidence value 12. initial = 0 ++#define MCDI_RO_COL_CFD_13 (0x2fbd) ++#define P_MCDI_RO_COL_CFD_13 (volatile unsigned int *)((0x2fbd << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_13. column cofidence value 13. initial = 0 ++#define MCDI_RO_COL_CFD_14 (0x2fbe) ++#define P_MCDI_RO_COL_CFD_14 (volatile unsigned int *)((0x2fbe << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_14. column cofidence value 14. initial = 0 ++#define MCDI_RO_COL_CFD_15 (0x2fbf) ++#define P_MCDI_RO_COL_CFD_15 (volatile unsigned int *)((0x2fbf << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_15. column cofidence value 15. initial = 0 ++#define MCDI_RO_COL_CFD_16 (0x2fc0) ++#define P_MCDI_RO_COL_CFD_16 (volatile unsigned int *)((0x2fc0 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_16. column cofidence value 16. initial = 0 ++#define MCDI_RO_COL_CFD_17 (0x2fc1) ++#define P_MCDI_RO_COL_CFD_17 (volatile unsigned int *)((0x2fc1 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_17. column cofidence value 17. initial = 0 ++#define MCDI_RO_COL_CFD_18 (0x2fc2) ++#define P_MCDI_RO_COL_CFD_18 (volatile unsigned int *)((0x2fc2 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_18. column cofidence value 18. initial = 0 ++#define MCDI_RO_COL_CFD_19 (0x2fc3) ++#define P_MCDI_RO_COL_CFD_19 (volatile unsigned int *)((0x2fc3 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_19. column cofidence value 19. initial = 0 ++#define MCDI_RO_COL_CFD_20 (0x2fc4) ++#define P_MCDI_RO_COL_CFD_20 (volatile unsigned int *)((0x2fc4 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_20. column cofidence value 20. initial = 0 ++#define MCDI_RO_COL_CFD_21 (0x2fc5) ++#define P_MCDI_RO_COL_CFD_21 (volatile unsigned int *)((0x2fc5 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_21. column cofidence value 21. initial = 0 ++#define MCDI_RO_COL_CFD_22 (0x2fc6) ++#define P_MCDI_RO_COL_CFD_22 (volatile unsigned int *)((0x2fc6 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_22. column cofidence value 22. initial = 0 ++#define MCDI_RO_COL_CFD_23 (0x2fc7) ++#define P_MCDI_RO_COL_CFD_23 (volatile unsigned int *)((0x2fc7 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_23. column cofidence value 23. initial = 0 ++#define MCDI_RO_COL_CFD_24 (0x2fc8) ++#define P_MCDI_RO_COL_CFD_24 (volatile unsigned int *)((0x2fc8 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_24. column cofidence value 24. initial = 0 ++#define MCDI_RO_COL_CFD_25 (0x2fc9) ++#define P_MCDI_RO_COL_CFD_25 (volatile unsigned int *)((0x2fc9 << 2) + 0xff900000) ++//Bit 31: 0, ro_mcdi_col_cfd_25. column cofidence value 25. initial = 0 ++// add space 8'hd0-8'hef ++// ++// Reading file: dipd_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++// using 8'he0-8'hef ++#define DIPD_COMB_CTRL0 (0x2fd0) ++#define P_DIPD_COMB_CTRL0 (volatile unsigned int *)((0x2fd0 << 2) + 0xff900000) ++//Bit 31:0, reg_pd_comb_ctrl0 ++#define DIPD_COMB_CTRL1 (0x2fd1) ++#define P_DIPD_COMB_CTRL1 (volatile unsigned int *)((0x2fd1 << 2) + 0xff900000) ++//Bit 31:0, reg_pd_comb_ctrl1 ++#define DIPD_COMB_CTRL2 (0x2fd2) ++#define P_DIPD_COMB_CTRL2 (volatile unsigned int *)((0x2fd2 << 2) + 0xff900000) ++//Bit 31:0, reg_pd_comb_ctrl2 ++#define DIPD_COMB_CTRL3 (0x2fd3) ++#define P_DIPD_COMB_CTRL3 (volatile unsigned int *)((0x2fd3 << 2) + 0xff900000) ++//Bit 31:0, reg_pd_comb_ctrl3 ++#define DIPD_COMB_CTRL4 (0x2fd4) ++#define P_DIPD_COMB_CTRL4 (volatile unsigned int *)((0x2fd4 << 2) + 0xff900000) ++//Bit 31:0, reg_pd_comb_ctrl4 ++#define DIPD_COMB_CTRL5 (0x2fd5) ++#define P_DIPD_COMB_CTRL5 (volatile unsigned int *)((0x2fd5 << 2) + 0xff900000) ++//Bit 31:0, reg_pd_comb_ctrl5 ++#define DIPD_RO_COMB_0 (0x2fd6) ++#define P_DIPD_RO_COMB_0 (volatile unsigned int *)((0x2fd6 << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_0 ++#define DIPD_RO_COMB_1 (0x2fd7) ++#define P_DIPD_RO_COMB_1 (volatile unsigned int *)((0x2fd7 << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_1 ++#define DIPD_RO_COMB_2 (0x2fd8) ++#define P_DIPD_RO_COMB_2 (volatile unsigned int *)((0x2fd8 << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_2 ++#define DIPD_RO_COMB_3 (0x2fd9) ++#define P_DIPD_RO_COMB_3 (volatile unsigned int *)((0x2fd9 << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_3 ++#define DIPD_RO_COMB_4 (0x2fda) ++#define P_DIPD_RO_COMB_4 (volatile unsigned int *)((0x2fda << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_4 ++#define DIPD_RO_COMB_5 (0x2fdb) ++#define P_DIPD_RO_COMB_5 (volatile unsigned int *)((0x2fdb << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_5 ++#define DIPD_RO_COMB_6 (0x2fdc) ++#define P_DIPD_RO_COMB_6 (volatile unsigned int *)((0x2fdc << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_6 ++#define DIPD_RO_COMB_7 (0x2fdd) ++#define P_DIPD_RO_COMB_7 (volatile unsigned int *)((0x2fdd << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_7 ++#define DIPD_RO_COMB_8 (0x2fde) ++#define P_DIPD_RO_COMB_8 (volatile unsigned int *)((0x2fde << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_8 ++#define DIPD_RO_COMB_9 (0x2fdf) ++#define P_DIPD_RO_COMB_9 (volatile unsigned int *)((0x2fdf << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_9 ++#define DIPD_RO_COMB_10 (0x2fe0) ++#define P_DIPD_RO_COMB_10 (volatile unsigned int *)((0x2fe0 << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_10 ++#define DIPD_RO_COMB_11 (0x2fe1) ++#define P_DIPD_RO_COMB_11 (volatile unsigned int *)((0x2fe1 << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_11 ++#define DIPD_RO_COMB_12 (0x2fe2) ++#define P_DIPD_RO_COMB_12 (volatile unsigned int *)((0x2fe2 << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_12 ++#define DIPD_RO_COMB_13 (0x2fe3) ++#define P_DIPD_RO_COMB_13 (volatile unsigned int *)((0x2fe3 << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_13 ++#define DIPD_RO_COMB_14 (0x2fe4) ++#define P_DIPD_RO_COMB_14 (volatile unsigned int *)((0x2fe4 << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_14 ++#define DIPD_RO_COMB_15 (0x2fe5) ++#define P_DIPD_RO_COMB_15 (volatile unsigned int *)((0x2fe5 << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_15 ++#define DIPD_RO_COMB_16 (0x2fe6) ++#define P_DIPD_RO_COMB_16 (volatile unsigned int *)((0x2fe6 << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_16 ++#define DIPD_RO_COMB_17 (0x2fe7) ++#define P_DIPD_RO_COMB_17 (volatile unsigned int *)((0x2fe7 << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_17 ++#define DIPD_RO_COMB_18 (0x2fe8) ++#define P_DIPD_RO_COMB_18 (volatile unsigned int *)((0x2fe8 << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_18 ++#define DIPD_RO_COMB_19 (0x2fe9) ++#define P_DIPD_RO_COMB_19 (volatile unsigned int *)((0x2fe9 << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_19 ++#define DIPD_RO_COMB_20 (0x2fea) ++#define P_DIPD_RO_COMB_20 (volatile unsigned int *)((0x2fea << 2) + 0xff900000) ++//Bit 31:0, ro_pd_comb_20 ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: dipd_regs.h ++// ++// addr space 8'hf0-8'hff ++// ++// Reading file: nr3_tnr_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++#define NR3_MODE (0x2ff0) ++#define P_NR3_MODE (volatile unsigned int *)((0x2ff0 << 2) + 0xff900000) ++//Bit 31: 6 reserved ++//Bit 5 reg_nr3_vtxt_mode // unsigned , default = 0 0: avg; 1:MAX ++//Bit 4 reg_3dnr_nr3_cbyy_ignor_coop // unsigned , default = 0 ignore coop condition for cbyy motion decision ++//Bit 3 reg_3dnr_nr3_ybyc_ignor_cnoop // unsigned , default = 0 ignore cnoop condition for ybyc motion decision ++//Bit 2: 0 reg_3dnr_nr3_suremot_txt_mode // unsigned , default = 3 0: cur, 1:p2; 2: (cur+p2)/2; 3/up: min(cur,p2) ++#define NR3_COOP_PARA (0x2ff1) ++#define P_NR3_COOP_PARA (volatile unsigned int *)((0x2ff1 << 2) + 0xff900000) ++//Bit 31:22 reserved ++//Bit 21:20 reg_3dnr_nr3_coop_mode // unsigned , default = 2 0 original pixel 1: [1 2 1]/4 lpf; 2: [1 2 2 2 1]/8; 3: 3x3 lpf ++//Bit 19:16 reg_3dnr_nr3_coop_ratio // unsigned , default = 8 cur and p2 color oop decision ratio: (avg1<(dif1*ratio/8 + ofst)); ++//Bit 15: 8 reg_3dnr_nr3_coop_ofset // signed , default = -1 cur and p2 color oop decision ofst: (avg1<(dif1*ratio/8 + ofst)); ++//Bit 7: 0 reg_3dnr_nr3_coop_sat_thrd // unsigned , default = 0 cur and p2 color oop decision min(sat0,sat1) threshold; ++#define NR3_CNOOP_GAIN (0x2ff2) ++#define P_NR3_CNOOP_GAIN (volatile unsigned int *)((0x2ff2 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:20 reg_3dnr_nr3_cnoop_ratio0 // unsigned , default = 8 cur and p2 color noop decision ratio0: (avg1<(MAX(sat0,sat2)*ratio0/8 + ofst0)); ++//Bit 19:16 reg_3dnr_nr3_cnoop_ratio1 // unsigned , default = 8 cur and p2 color noop decision ratio1: (dif1<(MIN(sat0,sat2)*ratio1/8 + ofst1)); ++//Bit 15: 8 reg_3dnr_nr3_cnoop_ofset0 // signed , default = 25 cur and p2 color noop decision ofset0: (avg1<(MAX(sat0,sat2)*ratio0/8 + ofst0)); ++//Bit 7: 0 reg_3dnr_nr3_cnoop_ofset1 // signed , default = 0 cur and p2 color noop decision ofset1: (dif1<(MIN(sat0,sat2)*ratio1/8 + ofst1)); ++#define NR3_YMOT_PARA (0x2ff3) ++#define P_NR3_YMOT_PARA (volatile unsigned int *)((0x2ff3 << 2) + 0xff900000) ++//Bit 31:20 reserved ++//Bit 19 reg_3dnr_nr3_ymot_only_en // unsigned , default = 1 enable signal for ignor chroma motion: (ytxt &coop) ++//Bit 18 reg_3dnr_nr3_ymot_only_cmtmode // unsigned , default = 1 0: cmot=ymot; 1: cmot = MIN(ymot, cmot) ++//Bit 17:16 reg_3dnr_nr3_ymot_only_txtmode // unsigned , default = 0 0, min(txt0,txt2); 1, max(txt0,txt2);2, (txt0+txt2)/2; 3: sat(txt0, txt2) ++//Bit 15: 8 reg_3dnr_nr3_ymot_only_txtthrd // unsigned , default = 10 threshold to luma texture to decide use ymot only ++//Bit 7: 0 reg_3dnr_nr3_ymot_only_motthrd // unsigned , default = 30 threshold to luma motion to decide use ymot only ++#define NR3_CMOT_PARA (0x2ff4) ++#define P_NR3_CMOT_PARA (volatile unsigned int *)((0x2ff4 << 2) + 0xff900000) ++//Bit 31:20 reserved ++//Bit 19 reg_3dnr_nr3_cmot_only_en // unsigned , default = 1 enable signal for ignor luma motion: (ctxt &cnoop) ++//Bit 18 reg_3dnr_nr3_cmot_only_ymtmode // unsigned , default = 0 0: ymot=cmot+ymot/4; 1: ymot = MIN(ymot, cmot) ++//Bit 17:16 reg_3dnr_nr3_cmot_only_txtmode // unsigned , default = 0 0, min(txt0,txt2); 1, max(txt0,txt2);2, (txt0+txt2)/2; 3: sat(txt0, txt2) ++//Bit 15: 8 reg_3dnr_nr3_cmot_only_txtthrd // unsigned , default = 20 threshold to chroma texture to decide use cmot only ++//Bit 7: 0 reg_3dnr_nr3_cmot_only_motthrd // unsigned , default = 15 threshold to chroma motion to decide use cmot only ++#define NR3_SUREMOT_YGAIN (0x2ff5) ++#define P_NR3_SUREMOT_YGAIN (volatile unsigned int *)((0x2ff5 << 2) + 0xff900000) ++//Bit 31:24 reg_3dnr_nr3_suremot_dec_yrate // unsigned , default = 16 (norm 16)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset ++//Bit 23:16 reg_3dnr_nr3_suremot_dec_yofst // unsigned , default = 12 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset ++//Bit 15: 8 reg_3dnr_nr3_suremot_frc_ygain // unsigned , default = 64 (norm 8)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset ++//Bit 7: 0 reg_3dnr_nr3_suremot_frc_yofst // unsigned , default = 20 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset ++#define NR3_SUREMOT_CGAIN (0x2ff6) ++#define P_NR3_SUREMOT_CGAIN (volatile unsigned int *)((0x2ff6 << 2) + 0xff900000) ++//Bit 31:24 reg_3dnr_nr3_suremot_dec_crate // unsigned , default = 34 (norm 16)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset ++//Bit 23:16 reg_3dnr_nr3_suremot_dec_cofst // unsigned , default = 38 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset ++//Bit 15: 8 reg_3dnr_nr3_suremot_frc_cgain // unsigned , default = 64 (norm 8)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset ++//Bit 7: 0 reg_3dnr_nr3_suremot_frc_cofst // unsigned , default = 20 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: nr3_tnr_regs.h ++// ++#define LBUF_TOP_CTRL (0x2fff) ++#define P_LBUF_TOP_CTRL (volatile unsigned int *)((0x2fff << 2) + 0xff900000) ++//bit 23:22 mode_444c422 ++//bit 21:20 mode_422c444 ++//bit 17 lbuf_fmt444_mode ++//bit 16 lbuf_line5_mode ++//bit 12:0 pre_lbuf_size ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: mcdi_regs.h ++// ++// VPU_VLOCK register (16'h3000 - 16'h30ff) ++//======================================================================== ++//`define VPU_VLOCK_VCBUS_BASE 8'h30 ++// ++// Reading file: vpu_vlock_reg.h ++// ++// synopsys translate_off ++// synopsys translate_on ++// ---------------------------- ++// VPU_VLOCK 0x30 ++// ---------------------------- ++// ----------------------------------------------- ++// CBUS_BASE: VPU_VLOCK_VCBUS_BASE = 0x30 ++// ----------------------------------------------- ++#define VPU_VLOCK_CTRL (0x3000) ++#define P_VPU_VLOCK_CTRL (volatile unsigned int *)((0x3000 << 2) + 0xff900000) ++#define VPU_VLOCK_MISC_CTRL (0x3001) ++#define P_VPU_VLOCK_MISC_CTRL (volatile unsigned int *)((0x3001 << 2) + 0xff900000) ++#define VPU_VLOCK_LOOP0_ACCUM_LMT (0x3002) ++#define P_VPU_VLOCK_LOOP0_ACCUM_LMT (volatile unsigned int *)((0x3002 << 2) + 0xff900000) ++#define VPU_VLOCK_LOOP0_CTRL0 (0x3003) ++#define P_VPU_VLOCK_LOOP0_CTRL0 (volatile unsigned int *)((0x3003 << 2) + 0xff900000) ++#define VPU_VLOCK_LOOP1_CTRL0 (0x3004) ++#define P_VPU_VLOCK_LOOP1_CTRL0 (volatile unsigned int *)((0x3004 << 2) + 0xff900000) ++#define VPU_VLOCK_LOOP1_IMISSYNC_MAX (0x3005) ++#define P_VPU_VLOCK_LOOP1_IMISSYNC_MAX (volatile unsigned int *)((0x3005 << 2) + 0xff900000) ++#define VPU_VLOCK_LOOP1_IMISSYNC_MIN (0x3006) ++#define P_VPU_VLOCK_LOOP1_IMISSYNC_MIN (volatile unsigned int *)((0x3006 << 2) + 0xff900000) ++#define VPU_VLOCK_OVWRITE_ACCUM0 (0x3007) ++#define P_VPU_VLOCK_OVWRITE_ACCUM0 (volatile unsigned int *)((0x3007 << 2) + 0xff900000) ++#define VPU_VLOCK_OVWRITE_ACCUM1 (0x3008) ++#define P_VPU_VLOCK_OVWRITE_ACCUM1 (volatile unsigned int *)((0x3008 << 2) + 0xff900000) ++#define VPU_VLOCK_OUTPUT0_CAPT_LMT (0x3009) ++#define P_VPU_VLOCK_OUTPUT0_CAPT_LMT (volatile unsigned int *)((0x3009 << 2) + 0xff900000) ++#define VPU_VLOCK_OUTPUT0_PLL_LMT (0x300a) ++#define P_VPU_VLOCK_OUTPUT0_PLL_LMT (volatile unsigned int *)((0x300a << 2) + 0xff900000) ++#define VPU_VLOCK_OUTPUT1_CAPT_LMT (0x300b) ++#define P_VPU_VLOCK_OUTPUT1_CAPT_LMT (volatile unsigned int *)((0x300b << 2) + 0xff900000) ++#define VPU_VLOCK_OUTPUT1_PLL_LMT (0x300c) ++#define P_VPU_VLOCK_OUTPUT1_PLL_LMT (volatile unsigned int *)((0x300c << 2) + 0xff900000) ++#define VPU_VLOCK_LOOP1_PHSDIF_TGT (0x300d) ++#define P_VPU_VLOCK_LOOP1_PHSDIF_TGT (volatile unsigned int *)((0x300d << 2) + 0xff900000) ++#define VPU_VLOCK_RO_LOOP0_ACCUM (0x300e) ++#define P_VPU_VLOCK_RO_LOOP0_ACCUM (volatile unsigned int *)((0x300e << 2) + 0xff900000) ++#define VPU_VLOCK_RO_LOOP1_ACCUM (0x300f) ++#define P_VPU_VLOCK_RO_LOOP1_ACCUM (volatile unsigned int *)((0x300f << 2) + 0xff900000) ++#define VPU_VLOCK_OROW_OCOL_MAX (0x3010) ++#define P_VPU_VLOCK_OROW_OCOL_MAX (volatile unsigned int *)((0x3010 << 2) + 0xff900000) ++#define VPU_VLOCK_RO_VS_I_DIST (0x3011) ++#define P_VPU_VLOCK_RO_VS_I_DIST (volatile unsigned int *)((0x3011 << 2) + 0xff900000) ++#define VPU_VLOCK_RO_VS_O_DIST (0x3012) ++#define P_VPU_VLOCK_RO_VS_O_DIST (volatile unsigned int *)((0x3012 << 2) + 0xff900000) ++#define VPU_VLOCK_RO_LINE_PIX_ADJ (0x3013) ++#define P_VPU_VLOCK_RO_LINE_PIX_ADJ (volatile unsigned int *)((0x3013 << 2) + 0xff900000) ++#define VPU_VLOCK_RO_OUTPUT_00_01 (0x3014) ++#define P_VPU_VLOCK_RO_OUTPUT_00_01 (volatile unsigned int *)((0x3014 << 2) + 0xff900000) ++#define VPU_VLOCK_RO_OUTPUT_10_11 (0x3015) ++#define P_VPU_VLOCK_RO_OUTPUT_10_11 (volatile unsigned int *)((0x3015 << 2) + 0xff900000) ++#define VPU_VLOCK_MX4096 (0x3016) ++#define P_VPU_VLOCK_MX4096 (volatile unsigned int *)((0x3016 << 2) + 0xff900000) ++#define VPU_VLOCK_STBDET_WIN0_WIN1 (0x3017) ++#define P_VPU_VLOCK_STBDET_WIN0_WIN1 (volatile unsigned int *)((0x3017 << 2) + 0xff900000) ++#define VPU_VLOCK_STBDET_CLP (0x3018) ++#define P_VPU_VLOCK_STBDET_CLP (volatile unsigned int *)((0x3018 << 2) + 0xff900000) ++#define VPU_VLOCK_STBDET_ABS_WIN0 (0x3019) ++#define P_VPU_VLOCK_STBDET_ABS_WIN0 (volatile unsigned int *)((0x3019 << 2) + 0xff900000) ++#define VPU_VLOCK_STBDET_ABS_WIN1 (0x301a) ++#define P_VPU_VLOCK_STBDET_ABS_WIN1 (volatile unsigned int *)((0x301a << 2) + 0xff900000) ++#define VPU_VLOCK_STBDET_SGN_WIN0 (0x301b) ++#define P_VPU_VLOCK_STBDET_SGN_WIN0 (volatile unsigned int *)((0x301b << 2) + 0xff900000) ++#define VPU_VLOCK_STBDET_SGN_WIN1 (0x301c) ++#define P_VPU_VLOCK_STBDET_SGN_WIN1 (volatile unsigned int *)((0x301c << 2) + 0xff900000) ++#define VPU_VLOCK_ADJ_EN_SYNC_CTRL (0x301d) ++#define P_VPU_VLOCK_ADJ_EN_SYNC_CTRL (volatile unsigned int *)((0x301d << 2) + 0xff900000) ++#define VPU_VLOCK_GCLK_EN (0x301e) ++#define P_VPU_VLOCK_GCLK_EN (volatile unsigned int *)((0x301e << 2) + 0xff900000) ++#define VPU_VLOCK_LOOP1_ACCUM_LMT (0x301f) ++#define P_VPU_VLOCK_LOOP1_ACCUM_LMT (volatile unsigned int *)((0x301f << 2) + 0xff900000) ++#define VPU_VLOCK_RO_M_INT_FRAC (0x3020) ++#define P_VPU_VLOCK_RO_M_INT_FRAC (volatile unsigned int *)((0x3020 << 2) + 0xff900000) ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: vpu_vlock_reg.h ++// ++//`define VPPB_VCBUS_BASE 8'h31 ++// ++// Reading file: srscl_reg.h ++// ++// synopsys translate_off ++// synopsys translate_on ++// ----------------------------------------------- ++// CBUS_BASE: VPPB_VCBUS_BASE = 0x31 ++// ----------------------------------------------- ++////=================================================================//// ++//// vkeystone ++////=================================================================//// ++// 8'h00-8'h17 ++// ++// Reading file: vkstone_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++#define VKS_CTRL (0x3100) ++#define P_VKS_CTRL (volatile unsigned int *)((0x3100 << 2) + 0xff900000) ++//Bit 31 reg_vks_en // unsigned , default = 1 enable signal of the vks function ++//Bit 30 reg_vks_scl_mode0 // unsigned , default = 1 : b0 mode of vks ofset mode, 0: offset= offset; 1: offset= offset*step= ofset/scale; ++//Bit 29 reg_vks_scl_mode1 // unsigned , default = 1 : b0 mode of vks ofset mode, 0: offset= offset; 1: offset= offset*step= ofset/scale; ++//Bit 28 reg_vks_fill_mode // unsigned , default = 1 mode of out-of-boundary fill, 0 extension, 1: fill with the fill_value ++//Bit 27:26 reg_vks_row_inp_mode // unsigned , default = 1 , interpolation mode from 16pieces ofset/step to each line ofset and step; 0: linear interpolation; 1: cubic interpolation (using ccoef) ++//Bit 25 reg_vks_border_ext_mode0 // unsigned , default = 0 , extend mode of the border data of luma and chroma, 0: copy the most border one; 1: extropolate the border one ++//Bit 24 reg_vks_border_ext_mode1 // unsigned , default = 0 , extend mode of the border data of luma and chroma, 0: copy the most border one; 1: extropolate the border one ++//Bit 23 reg_vks_obuf_mode0 // unsigned , default = 1 , mode of output buffer left/right side. 0: no precalculate active pixels during output fill region; 1: precaclc active pixels during output fill regions ++//Bit 22 reg_vks_obuf_mode1 // unsigned , default = 1 , mode of output buffer left/right side. 0: no precalculate active pixels during output fill region; 1: precaclc active pixels during output fill regions ++//Bit 21:20 reg_vks_obuf_mrgn0 // unsigned , default = 3 , margin pixels for left right most active pixel to the fill pixels to avoid jump ++//Bit 19:18 reg_vks_obuf_mrgn1 // unsigned , default = 3 , margin pixels for left right most active pixel to the fill pixels to avoid jump ++//Bit 17:16 reg_vks_phs_qmode // unsigned , default = 2 , interpolation mode of the phase, 0: floor to 1/64 phase; 1: round to 1/64 phase; 2/3 linear intp ++//Bit 15: 0 reg_vks_row_scl // unsigned , default = 11651 , scale of row to make it fit to the 16 pieces, scl = (2^23)/RowMax ++#define VKS_OUT_WIN_SIZE (0x3101) ++#define P_VKS_OUT_WIN_SIZE (volatile unsigned int *)((0x3101 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:16 reg_vks_ocolmax // unsigned , default = 1280 output outer window col number, decided by the projector ++//Bit 15:14 reserved ++//Bit 13: 0 reg_vks_orowmax // unsigned , default = 720 output outer window row number, decided by the projector ++#define VKS_PRELPF_YCOEF0 (0x3102) ++#define P_VKS_PRELPF_YCOEF0 (volatile unsigned int *)((0x3102 << 2) + 0xff900000) ++//Bit 31:24 reg_vks_prelpf_ycoef0 // signed , default = -128 coef of horizontal luma prelpf for Keystone, normalized 128 as '1' ++//Bit 23:16 reg_vks_prelpf_ycoef1 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1' ++//Bit 15: 8 reg_vks_prelpf_ycoef2 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1' ++//Bit 7: 0 reg_vks_prelpf_ycoef3 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1' ++#define VKS_PRELPF_YCOEF1 (0x3103) ++#define P_VKS_PRELPF_YCOEF1 (volatile unsigned int *)((0x3103 << 2) + 0xff900000) ++//Bit 31:16 reserved ++//Bit 15: 8 reg_vks_prelpf_ycoef4 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1' ++//Bit 7: 0 reg_vks_prelpf_ycoef5 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1' ++#define VKS_PRELPF_CCOEF0 (0x3104) ++#define P_VKS_PRELPF_CCOEF0 (volatile unsigned int *)((0x3104 << 2) + 0xff900000) ++//Bit 31:24 reg_vks_prelpf_ccoef0 // signed , default = -128 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1' ++//Bit 23:16 reg_vks_prelpf_ccoef1 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1' ++//Bit 15: 8 reg_vks_prelpf_ccoef2 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1' ++//Bit 7: 0 reg_vks_prelpf_ccoef3 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1' ++#define VKS_PRELPF_CCOEF1 (0x3105) ++#define P_VKS_PRELPF_CCOEF1 (volatile unsigned int *)((0x3105 << 2) + 0xff900000) ++//Bit 31:16 reserved ++//Bit 15: 8 reg_vks_prelpf_ccoef4 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1' ++//Bit 7: 0 reg_vks_prelpf_ccoef5 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1' ++#define VKS_FILL_VAL (0x3106) ++#define P_VKS_FILL_VAL (volatile unsigned int *)((0x3106 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:16 reg_vks_fill_value0 // unsigned , default = 0 , border fill color define. yuv: [0 128 128]; rgb:[0 0 0] ++//Bit 15: 8 reg_vks_fill_value1 // unsigned , default = 128 , border fill color define. yuv: [0 128 128]; rgb:[0 0 0] ++//Bit 7: 0 reg_vks_fill_value2 // unsigned , default = 128 , border fill color define. yuv: [0 128 128]; rgb:[0 0 0] ++#define VKS_IWIN_HSIZE (0x3107) ++#define P_VKS_IWIN_HSIZE (volatile unsigned int *)((0x3107 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:16 reg_vks_iwinx0 // unsigned , default = 160 , input start-col and end-col; ++//Bit 15:14 reserved ++//Bit 13: 0 reg_vks_iwinx1 // unsigned , default = 1279 , input start-col and end-col; ++#define VKS_IWIN_VSIZE (0x3108) ++#define P_VKS_IWIN_VSIZE (volatile unsigned int *)((0x3108 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:16 reg_vks_iwiny0 // unsigned , default = 0 , input start-row and end-row; ++//Bit 15:14 reserved ++//Bit 13: 0 reg_vks_iwiny1 // unsigned , default = 719 , input start-row and end-row; ++#define VKS_TOP_MISC (0x3109) ++#define P_VKS_TOP_MISC (volatile unsigned int *)((0x3109 << 2) + 0xff900000) ++//Bit 31:19 reserved ++//Bit 18 reg_flt_en // unsigned , default = 1 ++//Bit 17 reg_frm_rst // unsigned , default = 0 ++//Bit 16 reg_ctrl_sync // unsigned , default = 0 ++//Bit 15: 8 blank_num // unsigned , default = 4 ++//Bit 7: 0 flt_blank_num // unsigned , default = 9 ++#define VKS_START_CTRL (0x310a) ++#define P_VKS_START_CTRL (volatile unsigned int *)((0x310a << 2) + 0xff900000) ++//Bit 31:17 reserved ++//Bit 16 reg_vks_en_mode // unsigned , default = 0 ++//Bit 15: 0 reg_hold_phnum // unsigned , default = 5 ++#define VKS_LBUF_SIZE (0x310b) ++#define P_VKS_LBUF_SIZE (volatile unsigned int *)((0x310b << 2) + 0xff900000) ++//Bit 31:12 reserved ++//Bit 11: 0 reg_lbuf_depth // unsigned , default = 1024 ++#define VKS_PARA_ADDR_PORT (0x310e) ++#define P_VKS_PARA_ADDR_PORT (volatile unsigned int *)((0x310e << 2) + 0xff900000) ++#define VKS_PARA_DATA_PORT (0x310f) ++#define P_VKS_PARA_DATA_PORT (volatile unsigned int *)((0x310f << 2) + 0xff900000) ++ ++ #define VKS_SCL_OFSET00 0x9 // ++//Bit 31:20 reserved ++//Bit 19: 0 reg_vks_scl_ofset0 // unsigned , default = 118534 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase ++ #define VKS_SCL_OFSET01 0xa // ++//Bit 31:20 reserved ++//Bit 19: 0 reg_vks_scl_ofset1 // unsigned , default = 111450 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase ++ #define VKS_SCL_OFSET02 0xb // ++//Bit 31:20 reserved ++//Bit 19: 0 reg_vks_scl_ofset2 // unsigned , default = 104366 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase ++ #define VKS_SCL_OFSET03 0xc // ++//Bit 31:20 reserved ++//Bit 19: 0 reg_vks_scl_ofset3 // unsigned , default = 97283 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase ++ #define VKS_SCL_OFSET04 0xd // ++//Bit 31:20 reserved ++//Bit 19: 0 reg_vks_scl_ofset4 // unsigned , default = 90199 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase ++ #define VKS_SCL_OFSET05 0xe // ++//Bit 31:20 reserved ++//Bit 19: 0 reg_vks_scl_ofset5 // unsigned , default = 83115 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase ++ #define VKS_SCL_OFSET06 0xf // ++//Bit 31:20 reserved ++//Bit 19: 0 reg_vks_scl_ofset6 // unsigned , default = 76031 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase ++ #define VKS_SCL_OFSET07 0x10 // ++//Bit 31:20 reserved ++//Bit 19: 0 reg_vks_scl_ofset7 // unsigned , default = 68947 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase ++ #define VKS_SCL_OFSET08 0x11 // ++//Bit 31:20 reserved ++//Bit 19: 0 reg_vks_scl_ofset8 // unsigned , default = 61864 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase ++ #define VKS_SCL_OFSET09 0x12 // ++//Bit 31:20 reserved ++//Bit 19: 0 reg_vks_scl_ofset9 // unsigned , default = 54780 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase ++ #define VKS_SCL_OFSET10 0x13 // ++//Bit 31:20 reserved ++//Bit 19: 0 reg_vks_scl_ofset10 // unsigned , default = 47696 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase ++ #define VKS_SCL_OFSET11 0x14 // ++//Bit 31:20 reserved ++//Bit 19: 0 reg_vks_scl_ofset11 // unsigned , default = 40612 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase ++ #define VKS_SCL_OFSET12 0x15 // ++//Bit 31:20 reserved ++//Bit 19: 0 reg_vks_scl_ofset12 // unsigned , default = 33528 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase ++ #define VKS_SCL_OFSET13 0x16 // ++//Bit 31:20 reserved ++//Bit 19: 0 reg_vks_scl_ofset13 // unsigned , default = 26444 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase ++ #define VKS_SCL_OFSET14 0x17 // ++//Bit 31:20 reserved ++//Bit 19: 0 reg_vks_scl_ofset14 // unsigned , default = 19361 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase ++ #define VKS_SCL_OFSET15 0x18 // ++//Bit 31:20 reserved ++//Bit 19: 0 reg_vks_scl_ofset15 // unsigned , default = 12277 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase ++ #define VKS_SCL_OFSET16 0x19 // ++//Bit 31:20 reserved ++//Bit 19: 0 reg_vks_scl_ofset16 // unsigned , default = 5193 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase ++ #define VKS_SCL_STEP00 0x1a // ++//Bit 31:24 reserved ++//Bit 23: 0 reg_vks_scl_step0 // unsigned , default = 331378 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step ++ #define VKS_SCL_STEP01 0x1b // ++//Bit 31:24 reserved ++//Bit 23: 0 reg_vks_scl_step1 // unsigned , default = 383191 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step ++ #define VKS_SCL_STEP02 0x1c // ++//Bit 31:24 reserved ++//Bit 23: 0 reg_vks_scl_step2 // unsigned , default = 435004 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step ++ #define VKS_SCL_STEP03 0x1d // ++//Bit 31:24 reserved ++//Bit 23: 0 reg_vks_scl_step3 // unsigned , default = 486818 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step ++ #define VKS_SCL_STEP04 0x1e // ++//Bit 31:24 reserved ++//Bit 23: 0 reg_vks_scl_step4 // unsigned , default = 538631 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step ++ #define VKS_SCL_STEP05 0x1f // ++//Bit 31:24 reserved ++//Bit 23: 0 reg_vks_scl_step5 // unsigned , default = 590444 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step ++ #define VKS_SCL_STEP06 0x20 // ++//Bit 31:24 reserved ++//Bit 23: 0 reg_vks_scl_step6 // unsigned , default = 642257 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step ++ #define VKS_SCL_STEP07 0x21 // ++//Bit 31:24 reserved ++//Bit 23: 0 reg_vks_scl_step7 // unsigned , default = 694070 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step ++ #define VKS_SCL_STEP08 0x22 // ++//Bit 31:24 reserved ++//Bit 23: 0 reg_vks_scl_step8 // unsigned , default = 745884 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step ++ #define VKS_SCL_STEP09 0x23 // ++//Bit 31:24 reserved ++//Bit 23: 0 reg_vks_scl_step9 // unsigned , default = 797697 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step ++ #define VKS_SCL_STEP10 0x24 // ++//Bit 31:24 reserved ++//Bit 23: 0 reg_vks_scl_step10 // unsigned , default = 849510 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step ++ #define VKS_SCL_STEP11 0x25 // ++//Bit 31:24 reserved ++//Bit 23: 0 reg_vks_scl_step11 // unsigned , default = 901323 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step ++ #define VKS_SCL_STEP12 0x26 // ++//Bit 31:24 reserved ++//Bit 23: 0 reg_vks_scl_step12 // unsigned , default = 953136 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step ++ #define VKS_SCL_STEP13 0x27 // ++//Bit 31:24 reserved ++//Bit 23: 0 reg_vks_scl_step13 // unsigned , default = 1004949 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step ++ #define VKS_SCL_STEP14 0x28 // ++//Bit 31:24 reserved ++//Bit 23: 0 reg_vks_scl_step14 // unsigned , default = 1056763 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step ++ #define VKS_SCL_STEP15 0x29 // ++//Bit 31:24 reserved ++//Bit 23: 0 reg_vks_scl_step15 // unsigned , default = 1108576 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step ++ #define VKS_SCL_STEP16 0x2a // ++//Bit 31:24 reserved ++//Bit 23: 0 reg_vks_scl_step16 // unsigned , default = 1160389 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step ++ #define VKS_PPS_YCOEF00 0x2b // ++//Bit 31:24 reg_vks_ycoef0 // signed , default = 0 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef1 // signed , default = 128 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef2 // signed , default = 0 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef3 // signed , default = 0 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF01 0x2c // ++//Bit 31:24 reg_vks_ycoef4 // signed , default = 0 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef5 // signed , default = 127 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef6 // signed , default = 1 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef7 // signed , default = 0 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF02 0x2d // ++//Bit 31:24 reg_vks_ycoef8 // signed , default = -1 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef9 // signed , default = 127 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef10 // signed , default = 2 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef11 // signed , default = 0 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF03 0x2e // ++//Bit 31:24 reg_vks_ycoef12 // signed , default = -2 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef13 // signed , default = 127 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef14 // signed , default = 3 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef15 // signed , default = 0 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF04 0x2f // ++//Bit 31:24 reg_vks_ycoef16 // signed , default = -3 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef17 // signed , default = 126 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef18 // signed , default = 5 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef19 // signed , default = 0 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF05 0x30 // ++//Bit 31:24 reg_vks_ycoef20 // signed , default = -4 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef21 // signed , default = 126 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef22 // signed , default = 6 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef23 // signed , default = 0 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF06 0x31 // ++//Bit 31:24 reg_vks_ycoef24 // signed , default = -5 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef25 // signed , default = 125 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef26 // signed , default = 8 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef27 // signed , default = 0 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF07 0x32 // ++//Bit 31:24 reg_vks_ycoef28 // signed , default = -5 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef29 // signed , default = 124 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef30 // signed , default = 9 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef31 // signed , default = 0 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF08 0x33 // ++//Bit 31:24 reg_vks_ycoef32 // signed , default = -6 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef33 // signed , default = 123 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef34 // signed , default = 11 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef35 // signed , default = 0 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF09 0x34 // ++//Bit 31:24 reg_vks_ycoef36 // signed , default = -6 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef37 // signed , default = 122 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef38 // signed , default = 13 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef39 // signed , default = -1 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF10 0x35 // ++//Bit 31:24 reg_vks_ycoef40 // signed , default = -7 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef41 // signed , default = 121 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef42 // signed , default = 15 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef43 // signed , default = -1 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF11 0x36 // ++//Bit 31:24 reg_vks_ycoef44 // signed , default = -7 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef45 // signed , default = 119 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef46 // signed , default = 17 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef47 // signed , default = -1 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF12 0x37 // ++//Bit 31:24 reg_vks_ycoef48 // signed , default = -8 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef49 // signed , default = 118 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef50 // signed , default = 19 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef51 // signed , default = -1 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF13 0x38 // ++//Bit 31:24 reg_vks_ycoef52 // signed , default = -8 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef53 // signed , default = 116 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef54 // signed , default = 22 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef55 // signed , default = -2 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF14 0x39 // ++//Bit 31:24 reg_vks_ycoef56 // signed , default = -8 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef57 // signed , default = 114 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef58 // signed , default = 24 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef59 // signed , default = -2 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF15 0x3a // ++//Bit 31:24 reg_vks_ycoef60 // signed , default = -8 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef61 // signed , default = 112 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef62 // signed , default = 26 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef63 // signed , default = -2 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF16 0x3b // ++//Bit 31:24 reg_vks_ycoef64 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef65 // signed , default = 111 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef66 // signed , default = 29 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef67 // signed , default = -3 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF17 0x3c // ++//Bit 31:24 reg_vks_ycoef68 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef69 // signed , default = 109 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef70 // signed , default = 31 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef71 // signed , default = -3 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF18 0x3d // ++//Bit 31:24 reg_vks_ycoef72 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef73 // signed , default = 107 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef74 // signed , default = 33 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef75 // signed , default = -3 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF19 0x3e // ++//Bit 31:24 reg_vks_ycoef76 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef77 // signed , default = 104 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef78 // signed , default = 36 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef79 // signed , default = -3 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF20 0x3f // ++//Bit 31:24 reg_vks_ycoef80 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef81 // signed , default = 102 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef82 // signed , default = 39 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef83 // signed , default = -4 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF21 0x40 // ++//Bit 31:24 reg_vks_ycoef84 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef85 // signed , default = 100 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef86 // signed , default = 41 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef87 // signed , default = -4 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF22 0x41 // ++//Bit 31:24 reg_vks_ycoef88 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef89 // signed , default = 97 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef90 // signed , default = 44 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef91 // signed , default = -4 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF23 0x42 // ++//Bit 31:24 reg_vks_ycoef92 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef93 // signed , default = 95 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef94 // signed , default = 47 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef95 // signed , default = -5 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF24 0x43 // ++//Bit 31:24 reg_vks_ycoef96 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef97 // signed , default = 93 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef98 // signed , default = 49 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef99 // signed , default = -5 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF25 0x44 // ++//Bit 31:24 reg_vks_ycoef100 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef101 // signed , default = 90 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef102 // signed , default = 52 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef103 // signed , default = -5 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF26 0x45 // ++//Bit 31:24 reg_vks_ycoef104 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef105 // signed , default = 88 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef106 // signed , default = 55 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef107 // signed , default = -6 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF27 0x46 // ++//Bit 31:24 reg_vks_ycoef108 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef109 // signed , default = 85 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef110 // signed , default = 58 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef111 // signed , default = -6 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF28 0x47 // ++//Bit 31:24 reg_vks_ycoef112 // signed , default = -8 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef113 // signed , default = 82 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef114 // signed , default = 60 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef115 // signed , default = -6 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF29 0x48 // ++//Bit 31:24 reg_vks_ycoef116 // signed , default = -8 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef117 // signed , default = 80 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef118 // signed , default = 63 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef119 // signed , default = -7 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF30 0x49 // ++//Bit 31:24 reg_vks_ycoef120 // signed , default = -8 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef121 // signed , default = 77 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef122 // signed , default = 66 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef123 // signed , default = -7 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF31 0x4a // ++//Bit 31:24 reg_vks_ycoef124 // signed , default = -8 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef125 // signed , default = 74 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef126 // signed , default = 69 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef127 // signed , default = -7 poly-phase scalar coefs ++ #define VKS_PPS_YCOEF32 0x4b // ++//Bit 31:24 reg_vks_ycoef128 // signed , default = -8 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ycoef129 // signed , default = 72 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ycoef130 // signed , default = 72 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ycoef131 // signed , default = -8 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF00 0x4c // ++//Bit 31:24 reg_vks_ccoef0 // signed , default = 0 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef1 // signed , default = 128 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef2 // signed , default = 0 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef3 // signed , default = 0 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF01 0x4d // ++//Bit 31:24 reg_vks_ccoef4 // signed , default = 0 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef5 // signed , default = 127 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef6 // signed , default = 1 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef7 // signed , default = 0 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF02 0x4e // ++//Bit 31:24 reg_vks_ccoef8 // signed , default = -1 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef9 // signed , default = 127 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef10 // signed , default = 2 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef11 // signed , default = 0 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF03 0x4f // ++//Bit 31:24 reg_vks_ccoef12 // signed , default = -2 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef13 // signed , default = 127 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef14 // signed , default = 3 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef15 // signed , default = 0 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF04 0x50 // ++//Bit 31:24 reg_vks_ccoef16 // signed , default = -3 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef17 // signed , default = 126 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef18 // signed , default = 5 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef19 // signed , default = 0 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF05 0x51 // ++//Bit 31:24 reg_vks_ccoef20 // signed , default = -4 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef21 // signed , default = 126 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef22 // signed , default = 6 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef23 // signed , default = 0 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF06 0x52 // ++//Bit 31:24 reg_vks_ccoef24 // signed , default = -5 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef25 // signed , default = 125 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef26 // signed , default = 8 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef27 // signed , default = 0 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF07 0x53 // ++//Bit 31:24 reg_vks_ccoef28 // signed , default = -5 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef29 // signed , default = 124 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef30 // signed , default = 9 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef31 // signed , default = 0 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF08 0x54 // ++//Bit 31:24 reg_vks_ccoef32 // signed , default = -6 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef33 // signed , default = 123 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef34 // signed , default = 11 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef35 // signed , default = 0 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF09 0x55 // ++//Bit 31:24 reg_vks_ccoef36 // signed , default = -6 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef37 // signed , default = 122 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef38 // signed , default = 13 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef39 // signed , default = -1 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF10 0x56 // ++//Bit 31:24 reg_vks_ccoef40 // signed , default = -7 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef41 // signed , default = 121 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef42 // signed , default = 15 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef43 // signed , default = -1 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF11 0x57 // ++//Bit 31:24 reg_vks_ccoef44 // signed , default = -7 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef45 // signed , default = 119 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef46 // signed , default = 17 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef47 // signed , default = -1 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF12 0x58 // ++//Bit 31:24 reg_vks_ccoef48 // signed , default = -8 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef49 // signed , default = 118 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef50 // signed , default = 19 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef51 // signed , default = -1 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF13 0x59 // ++//Bit 31:24 reg_vks_ccoef52 // signed , default = -8 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef53 // signed , default = 116 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef54 // signed , default = 22 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef55 // signed , default = -2 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF14 0x5a // ++//Bit 31:24 reg_vks_ccoef56 // signed , default = -8 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef57 // signed , default = 114 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef58 // signed , default = 24 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef59 // signed , default = -2 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF15 0x5b // ++//Bit 31:24 reg_vks_ccoef60 // signed , default = -8 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef61 // signed , default = 112 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef62 // signed , default = 26 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef63 // signed , default = -2 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF16 0x5c // ++//Bit 31:24 reg_vks_ccoef64 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef65 // signed , default = 111 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef66 // signed , default = 29 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef67 // signed , default = -3 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF17 0x5d // ++//Bit 31:24 reg_vks_ccoef68 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef69 // signed , default = 109 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef70 // signed , default = 31 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef71 // signed , default = -3 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF18 0x5e // ++//Bit 31:24 reg_vks_ccoef72 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef73 // signed , default = 107 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef74 // signed , default = 33 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef75 // signed , default = -3 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF19 0x5f // ++//Bit 31:24 reg_vks_ccoef76 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef77 // signed , default = 104 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef78 // signed , default = 36 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef79 // signed , default = -3 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF20 0x60 // ++//Bit 31:24 reg_vks_ccoef80 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef81 // signed , default = 102 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef82 // signed , default = 39 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef83 // signed , default = -4 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF21 0x61 // ++//Bit 31:24 reg_vks_ccoef84 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef85 // signed , default = 100 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef86 // signed , default = 41 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef87 // signed , default = -4 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF22 0x62 // ++//Bit 31:24 reg_vks_ccoef88 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef89 // signed , default = 97 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef90 // signed , default = 44 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef91 // signed , default = -4 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF23 0x63 // ++//Bit 31:24 reg_vks_ccoef92 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef93 // signed , default = 95 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef94 // signed , default = 47 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef95 // signed , default = -5 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF24 0x64 // ++//Bit 31:24 reg_vks_ccoef96 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef97 // signed , default = 93 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef98 // signed , default = 49 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef99 // signed , default = -5 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF25 0x65 // ++//Bit 31:24 reg_vks_ccoef100 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef101 // signed , default = 90 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef102 // signed , default = 52 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef103 // signed , default = -5 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF26 0x66 // ++//Bit 31:24 reg_vks_ccoef104 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef105 // signed , default = 88 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef106 // signed , default = 55 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef107 // signed , default = -6 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF27 0x67 // ++//Bit 31:24 reg_vks_ccoef108 // signed , default = -9 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef109 // signed , default = 85 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef110 // signed , default = 58 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef111 // signed , default = -6 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF28 0x68 // ++//Bit 31:24 reg_vks_ccoef112 // signed , default = -8 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef113 // signed , default = 82 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef114 // signed , default = 60 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef115 // signed , default = -6 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF29 0x69 // ++//Bit 31:24 reg_vks_ccoef116 // signed , default = -8 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef117 // signed , default = 80 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef118 // signed , default = 63 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef119 // signed , default = -7 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF30 0x6a // ++//Bit 31:24 reg_vks_ccoef120 // signed , default = -8 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef121 // signed , default = 77 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef122 // signed , default = 66 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef123 // signed , default = -7 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF31 0x6b // ++//Bit 31:24 reg_vks_ccoef124 // signed , default = -8 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef125 // signed , default = 74 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef126 // signed , default = 69 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef127 // signed , default = -7 poly-phase scalar coefs ++ #define VKS_PPS_CCOEF32 0x6c // ++//Bit 31:24 reg_vks_ccoef128 // signed , default = -8 poly-phase scalar coefs ++//Bit 23:16 reg_vks_ccoef129 // signed , default = 72 poly-phase scalar coefs ++//Bit 15: 8 reg_vks_ccoef130 // signed , default = 72 poly-phase scalar coefs ++//Bit 7: 0 reg_vks_ccoef131 // signed , default = -8 poly-phase scalar coefs ++ ++ ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: vkstone_regs.h ++// ++////=================================================================//// ++//// vpp dither ++////=================================================================//// ++// 8'h20-8'h3f ++// ++// Reading file: vpp_dither_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++#define VPP_VE_DITHER_CTRL (0x3120) ++#define P_VPP_VE_DITHER_CTRL (volatile unsigned int *)((0x3120 << 2) + 0xff900000) ++#define VPP_VE_DITHER_LUT_1 (0x3121) ++#define P_VPP_VE_DITHER_LUT_1 (volatile unsigned int *)((0x3121 << 2) + 0xff900000) ++#define VPP_VE_DITHER_LUT_2 (0x3122) ++#define P_VPP_VE_DITHER_LUT_2 (volatile unsigned int *)((0x3122 << 2) + 0xff900000) ++#define VPP_VE_DITHER_LUT_3 (0x3123) ++#define P_VPP_VE_DITHER_LUT_3 (volatile unsigned int *)((0x3123 << 2) + 0xff900000) ++#define VPP_VE_DITHER_LUT_4 (0x3124) ++#define P_VPP_VE_DITHER_LUT_4 (volatile unsigned int *)((0x3124 << 2) + 0xff900000) ++#define VPP_VE_DITHER_LUT_5 (0x3125) ++#define P_VPP_VE_DITHER_LUT_5 (volatile unsigned int *)((0x3125 << 2) + 0xff900000) ++#define VPP_VE_DITHER_LUT_6 (0x3126) ++#define P_VPP_VE_DITHER_LUT_6 (volatile unsigned int *)((0x3126 << 2) + 0xff900000) ++#define VPP_VE_DITHER_LUT_7 (0x3127) ++#define P_VPP_VE_DITHER_LUT_7 (volatile unsigned int *)((0x3127 << 2) + 0xff900000) ++#define VPP_VE_DITHER_LUT_8 (0x3128) ++#define P_VPP_VE_DITHER_LUT_8 (volatile unsigned int *)((0x3128 << 2) + 0xff900000) ++#define VPP_VE_DITHER_LUT_9 (0x3129) ++#define P_VPP_VE_DITHER_LUT_9 (volatile unsigned int *)((0x3129 << 2) + 0xff900000) ++#define VPP_VE_DITHER_LUT_10 (0x312a) ++#define P_VPP_VE_DITHER_LUT_10 (volatile unsigned int *)((0x312a << 2) + 0xff900000) ++#define VPP_VE_DITHER_LUT_11 (0x312b) ++#define P_VPP_VE_DITHER_LUT_11 (volatile unsigned int *)((0x312b << 2) + 0xff900000) ++#define VPP_VE_DITHER_LUT_12 (0x312c) ++#define P_VPP_VE_DITHER_LUT_12 (volatile unsigned int *)((0x312c << 2) + 0xff900000) ++#define VPP_OSDSC_DITHER_CTRL (0x3130) ++#define P_VPP_OSDSC_DITHER_CTRL (volatile unsigned int *)((0x3130 << 2) + 0xff900000) ++#define VPP_OSDSC_DITHER_LUT_1 (0x3131) ++#define P_VPP_OSDSC_DITHER_LUT_1 (volatile unsigned int *)((0x3131 << 2) + 0xff900000) ++#define VPP_OSDSC_DITHER_LUT_2 (0x3132) ++#define P_VPP_OSDSC_DITHER_LUT_2 (volatile unsigned int *)((0x3132 << 2) + 0xff900000) ++#define VPP_OSDSC_DITHER_LUT_3 (0x3133) ++#define P_VPP_OSDSC_DITHER_LUT_3 (volatile unsigned int *)((0x3133 << 2) + 0xff900000) ++#define VPP_OSDSC_DITHER_LUT_4 (0x3134) ++#define P_VPP_OSDSC_DITHER_LUT_4 (volatile unsigned int *)((0x3134 << 2) + 0xff900000) ++#define VPP_OSDSC_DITHER_LUT_5 (0x3135) ++#define P_VPP_OSDSC_DITHER_LUT_5 (volatile unsigned int *)((0x3135 << 2) + 0xff900000) ++#define VPP_OSDSC_DITHER_LUT_6 (0x3136) ++#define P_VPP_OSDSC_DITHER_LUT_6 (volatile unsigned int *)((0x3136 << 2) + 0xff900000) ++#define VPP_OSDSC_DITHER_LUT_7 (0x3137) ++#define P_VPP_OSDSC_DITHER_LUT_7 (volatile unsigned int *)((0x3137 << 2) + 0xff900000) ++#define VPP_OSDSC_DITHER_LUT_8 (0x3138) ++#define P_VPP_OSDSC_DITHER_LUT_8 (volatile unsigned int *)((0x3138 << 2) + 0xff900000) ++#define VPP_OSDSC_DITHER_LUT_9 (0x3139) ++#define P_VPP_OSDSC_DITHER_LUT_9 (volatile unsigned int *)((0x3139 << 2) + 0xff900000) ++#define VPP_OSDSC_DITHER_LUT_10 (0x313a) ++#define P_VPP_OSDSC_DITHER_LUT_10 (volatile unsigned int *)((0x313a << 2) + 0xff900000) ++#define VPP_OSDSC_DITHER_LUT_11 (0x313b) ++#define P_VPP_OSDSC_DITHER_LUT_11 (volatile unsigned int *)((0x313b << 2) + 0xff900000) ++#define VPP_OSDSC_DITHER_LUT_12 (0x313c) ++#define P_VPP_OSDSC_DITHER_LUT_12 (volatile unsigned int *)((0x313c << 2) + 0xff900000) ++#define VPP_OSDSC_DITHER_LUT_13 (0x313d) ++#define P_VPP_OSDSC_DITHER_LUT_13 (volatile unsigned int *)((0x313d << 2) + 0xff900000) ++#define VPP_OSDSC_DITHER_LUT_14 (0x313e) ++#define P_VPP_OSDSC_DITHER_LUT_14 (volatile unsigned int *)((0x313e << 2) + 0xff900000) ++#define VPP_OSDSC_DITHER_LUT_15 (0x313f) ++#define P_VPP_OSDSC_DITHER_LUT_15 (volatile unsigned int *)((0x313f << 2) + 0xff900000) ++ ++ ++/* osd super scale */ ++#define OSDSR_HV_SIZEIN VPP_OSDSC_DITHER_CTRL ++#define OSDSR_CTRL_MODE VPP_OSDSC_DITHER_LUT_1 ++#define OSDSR_ABIC_HCOEF VPP_OSDSC_DITHER_LUT_2 ++#define OSDSR_YBIC_HCOEF VPP_OSDSC_DITHER_LUT_3 ++#define OSDSR_CBIC_HCOEF VPP_OSDSC_DITHER_LUT_4 ++#define OSDSR_ABIC_VCOEF VPP_OSDSC_DITHER_LUT_5 ++#define OSDSR_YBIC_VCOEF VPP_OSDSC_DITHER_LUT_6 ++#define OSDSR_CBIC_VCOEF VPP_OSDSC_DITHER_LUT_7 ++#define OSDSR_VAR_PARA VPP_OSDSC_DITHER_LUT_8 ++#define OSDSR_CONST_PARA VPP_OSDSC_DITHER_LUT_9 ++#define OSDSR_RKE_EXTWIN VPP_OSDSC_DITHER_LUT_10 ++#define OSDSR_UK_GRAD2DDIAG_TH_RATE VPP_OSDSC_DITHER_LUT_11 ++#define OSDSR_UK_GRAD2DDIAG_LIMIT VPP_OSDSC_DITHER_LUT_12 ++#define OSDSR_UK_GRAD2DADJA_TH_RATE VPP_OSDSC_DITHER_LUT_13 ++#define OSDSR_UK_GRAD2DADJA_LIMIT VPP_OSDSC_DITHER_LUT_14 ++#define OSDSR_UK_BST_GAIN VPP_OSDSC_DITHER_LUT_15 ++ ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: vpp_dither_regs.h ++// ++// 8'h40-8'h4f ++// ++// Reading file: osdsc_deband_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++#define OSD_DB_FLT_CTRL (0x3140) ++#define P_OSD_DB_FLT_CTRL (volatile unsigned int *)((0x3140 << 2) + 0xff900000) ++//Bit 31:27 reserved ++//Bit 26 reg_nrdeband_reset1 // unsigned , default = 1 , 0 : no reload chrm seed 1: reload chrm seed ++//Bit 25 reg_nrdeband_reset0 // unsigned , default = 1 , 0 : no reload luma seed 1: reload luma seed ++//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 , 0 : yuv 1: RGB ++//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below ++//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below ++//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y; ++//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m]) ++//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6 ++//Bit 16 reserved ++//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6 ++//Bit 12 reserved ++//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6 ++//Bit 8 reserved ++//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 , debanding random hp portion xor, [0] for luma ++//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 , debanding random hp portion xor, [1] for chroma ++//Bit 5 reg_nrdeband_en1 // unsigned , default = 0 , debanding registers, for luma ++//Bit 4 reg_nrdeband_en0 // unsigned , default = 0 , debanding registers, for chroma ++//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7 ++//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7 ++#define OSD_DB_FLT_CTRL1 (0x3141) ++#define P_OSD_DB_FLT_CTRL1 (volatile unsigned int *)((0x3141 << 2) + 0xff900000) ++//Bit 31:18 reserved ++//Bit 17:16 reg_nrdeband_noise_rs // unsigned , default = 2 ++//Bit 15:12 reg_nrdeband_randgain // unsigned , default = 8 ++//Bit 11 reserved ++//Bit 10: 8 reg_nrdeband_bandrand5 // unsigned , default = 6 ++//Bit 7 reserved ++//Bit 6: 4 reg_nrdeband_bandrand4 // unsigned , default = 6 ++//Bit 3 reserved ++//Bit 2: 0 reg_nrdeband_bandrand3 // unsigned , default = 6 ++#define OSD_DB_FLT_LUMA_THRD (0x3142) ++#define P_OSD_DB_FLT_LUMA_THRD (volatile unsigned int *)((0x3142 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:24 reg_nrdeband_luma_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf ++//Bit 23:22 reserved ++//Bit 21:16 reg_nrdeband_luma_th2 // unsigned , default = 28 , elseif th1) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 20 ++#define PK_CON_2CIRHPGAIN_LIMIT (0x3206) ++#define P_PK_CON_2CIRHPGAIN_LIMIT (volatile unsigned int *)((0x3206 << 2) + 0xff900000) ++//Bit 31:24, reg_pk_cirhpcon2gain2 : level limit(for hpconth1) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 5 ++//Bit 7: 0, reserved ++#define PK_CON_2CIRBPGAIN_TH_RATE (0x3207) ++#define P_PK_CON_2CIRBPGAIN_TH_RATE (volatile unsigned int *)((0x3207 << 2) + 0xff900000) ++//Bit 31:24, reg_pk_cirbpcon2gain0 : threshold0 of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 20 ++//Bit 23:16, reg_pk_cirbpcon2gain1 : threshold1 of curve to map bpcon to bpgain for circle bp filter (all 8 direction same).. unsigned , default = 50 ++//Bit 15: 8, reg_pk_cirbpcon2gain5 : rate0 (for bpconth1) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 25 ++#define PK_CON_2CIRBPGAIN_LIMIT (0x3208) ++#define P_PK_CON_2CIRBPGAIN_LIMIT (volatile unsigned int *)((0x3208 << 2) + 0xff900000) ++//Bit 31:24, reg_pk_cirbpcon2gain2 : level limit(for bpconth1) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 5 ++//Bit 7: 0, reserved ++#define PK_CON_2DRTHPGAIN_TH_RATE (0x3209) ++#define P_PK_CON_2DRTHPGAIN_TH_RATE (volatile unsigned int *)((0x3209 << 2) + 0xff900000) ++//Bit 31:24, reg_pk_drthpcon2gain0 : threshold0 of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 25 ++//Bit 23:16, reg_pk_drthpcon2gain1 : threshold1 of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 60 ++//Bit 15: 8, reg_pk_drthpcon2gain5 : rate0 (for hpconth1) of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 20 ++#define PK_CON_2DRTHPGAIN_LIMIT (0x320a) ++#define P_PK_CON_2DRTHPGAIN_LIMIT (volatile unsigned int *)((0x320a << 2) + 0xff900000) ++//Bit 31:24, reg_pk_drthpcon2gain2 : level limit(for hpconth1) of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 5 ++//Bit 7: 0, reserved ++#define PK_CON_2DRTBPGAIN_TH_RATE (0x320b) ++#define P_PK_CON_2DRTBPGAIN_TH_RATE (volatile unsigned int *)((0x320b << 2) + 0xff900000) ++//Bit 31:24, reg_pk_drtbpcon2gain0 : threshold0 of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 20 ++//Bit 23:16, reg_pk_drtbpcon2gain1 : threshold1 of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 50 ++//Bit 15: 8, reg_pk_drtbpcon2gain5 : rate0 (for bpconth1) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 25 ++#define PK_CON_2DRTBPGAIN_LIMIT (0x320c) ++#define P_PK_CON_2DRTBPGAIN_LIMIT (volatile unsigned int *)((0x320c << 2) + 0xff900000) ++//Bit 31:24, reg_pk_drtbpcon2gain2 : level limit(for bpconth1) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 5 ++//Bit 7: 0, reserved ++#define PK_CIRFB_LPF_MODE (0x320d) ++#define P_PK_CIRFB_LPF_MODE (volatile unsigned int *)((0x320d << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:28, reg_cirhp_horz_mode : no horz filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1 ++//Bit 27:26, reserved ++//Bit 25:24, reg_cirhp_vert_mode : no vert filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1 ++//Bit 23:22, reserved ++//Bit 21:20, reg_cirhp_diag_mode : filter on HP; 1: [1 2 1]/4; . unsigned , default = 1 ++//Bit 19:14, reserved ++//Bit 13:12, reg_cirbp_horz_mode : no horz filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1 ++//Bit 11:10, reserved ++//Bit 9: 8, reg_cirbp_vert_mode : no vert filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1 ++//Bit 7: 6, reserved ++//Bit 5: 4, reg_cirbp_diag_mode : filter on BP; 1: [1 2 1]/4; . unsigned , default = 1 ++//Bit 3: 0, reserved ++#define PK_DRTFB_LPF_MODE (0x320e) ++#define P_PK_DRTFB_LPF_MODE (volatile unsigned int *)((0x320e << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:28, reg_drthp_horz_mode : no horz filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1 ++//Bit 27:26, reserved ++//Bit 25:24, reg_drthp_vert_mode : no vert filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1 ++//Bit 23:22, reserved ++//Bit 21:20, reg_drthp_diag_mode : filter on HP; 1: [1 2 1]/4; 1 . unsigned , default = 1 ++//Bit 19:14, reserved ++//Bit 13:12, reg_drtbp_horz_mode : no horz filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1 ++//Bit 11:10, reserved ++//Bit 9: 8, reg_drtbp_vert_mode : no vert filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1 ++//Bit 7: 6, reserved ++//Bit 5: 4, reg_drtbp_diag_mode : filter on BP; 1: [1 2 1]/4; 1 . unsigned , default = 1 ++//Bit 3: 0, reserved ++#define PK_CIRFB_HP_CORING (0x320f) ++#define P_PK_CIRFB_HP_CORING (volatile unsigned int *)((0x320f << 2) + 0xff900000) ++//Bit 31:22, reserved ++//Bit 21:16, reg_cirhp_horz_core : coring of HP for Horz . unsigned , default = 0 ++//Bit 15:14, reserved ++//Bit 13: 8, reg_cirhp_vert_core : coring of HP for Vert . unsigned , default = 0 ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_cirhp_diag_core : coring of HP for Diag . unsigned , default = 0 ++#define PK_CIRFB_BP_CORING (0x3210) ++#define P_PK_CIRFB_BP_CORING (volatile unsigned int *)((0x3210 << 2) + 0xff900000) ++//Bit 31:22, reserved ++//Bit 21:16, reg_cirbp_horz_core : coring of HP for Horz . unsigned , default = 1 ++//Bit 15:14, reserved ++//Bit 13: 8, reg_cirbp_vert_core : coring of HP for Vert . unsigned , default = 1 ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_cirbp_diag_core : coring of HP for Diag . unsigned , default = 1 ++#define PK_DRTFB_HP_CORING (0x3211) ++#define P_PK_DRTFB_HP_CORING (volatile unsigned int *)((0x3211 << 2) + 0xff900000) ++//Bit 31:22, reserved ++//Bit 21:16, reg_drthp_horz_core : coring of HP for Horz . unsigned , default = 1 ++//Bit 15:14, reserved ++//Bit 13: 8, reg_drthp_vert_core : coring of HP for Vert . unsigned , default = 1 ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_drthp_diag_core : coring of HP for Diag . unsigned , default = 1 ++#define PK_DRTFB_BP_CORING (0x3212) ++#define P_PK_DRTFB_BP_CORING (volatile unsigned int *)((0x3212 << 2) + 0xff900000) ++//Bit 31:22, reserved ++//Bit 21:16, reg_drtbp_horz_core : coring of HP for Horz . unsigned , default = 1 ++//Bit 15:14, reserved ++//Bit 13: 8, reg_drtbp_vert_core : coring of HP for Vert . unsigned , default = 1 ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_drtbp_diag_core : coring of HP for Diag . unsigned , default = 1 ++#define PK_CIRFB_BLEND_GAIN (0x3213) ++#define P_PK_CIRFB_BLEND_GAIN (volatile unsigned int *)((0x3213 << 2) + 0xff900000) ++//Bit 31:28, reg_hp_cir_hgain : normalized 8 as '1' . unsigned , default = 8 ++//Bit 27:24, reg_hp_cir_vgain : normalized 8 as '1' . unsigned , default = 8 ++//Bit 23:20, reg_hp_cir_dgain : normalized 8 as '1' . unsigned , default = 8 ++//Bit 19:16, reserved ++//Bit 15:12, reg_bp_cir_hgain : normalized 8 as '1' . unsigned , default = 8 ++//Bit 11: 8, reg_bp_cir_vgain : normalized 8 as '1' . unsigned , default = 8 ++//Bit 7: 4, reg_bp_cir_dgain : normalized 8 as '1' . unsigned , default = 8 ++//Bit 3: 0, reserved ++#define NR_ALPY_SSD_GAIN_OFST (0x3214) ++#define P_NR_ALPY_SSD_GAIN_OFST (volatile unsigned int *)((0x3214 << 2) + 0xff900000) ++//Bit 31:16, reserved ++//Bit 15: 8, reg_nr_alp0_ssd_gain : gain to max ssd normalized 16 as '1' . unsigned , default = 16 ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_nr_alp0_ssd_ofst : offset to ssd before dividing to min_err . signed , default = -2 ++#define NR_ALP0Y_ERR2CURV_TH_RATE (0x3215) ++#define P_NR_ALP0Y_ERR2CURV_TH_RATE (volatile unsigned int *)((0x3215 << 2) + 0xff900000) ++//Bit 31:24, reg_nr_alp0_minerr_ypar0 : threshold0 of curve to map mierr to alp0 for luma channel, this will be set value of flat region mierr that no need blur. 0~255.. unsigned , default = 10 ++//Bit 23:16, reg_nr_alp0_minerr_ypar1 : threshold1 of curve to map mierr to alp0 for luma channel,this will be set value of texture region mierr that can not blur.. unsigned , default = 25 ++//Bit 15: 8, reg_nr_alp0_minerr_ypar5 : rate0 (for mierrth1) of curve to map mierr to alp0 for luma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 64 ++#define NR_ALP0Y_ERR2CURV_LIMIT (0x3216) ++#define P_NR_ALP0Y_ERR2CURV_LIMIT (volatile unsigned int *)((0x3216 << 2) + 0xff900000) ++//Bit 31:24, reg_nr_alp0_minerr_ypar2 : level limit(for mierrth1) of curve to map mierr to alp0 for luma channel, this will be set to alp0 that we can do for texture region. 0~255.. unsigned , default = 63 ++//Bit 7: 0, reserved ++#define NR_ALP0C_ERR2CURV_TH_RATE (0x3217) ++#define P_NR_ALP0C_ERR2CURV_TH_RATE (volatile unsigned int *)((0x3217 << 2) + 0xff900000) ++//Bit 31:24, reg_nr_alp0_minerr_cpar0 : threshold0 of curve to map mierr to alp0 for chroma channel, this will be set value of flat region mierr that no need blur.. unsigned , default = 10 ++//Bit 23:16, reg_nr_alp0_minerr_cpar1 : threshold1 of curve to map mierr to alp0 for chroma channel,this will be set value of texture region mierr that can not blur.. unsigned , default = 25 ++//Bit 15: 8, reg_nr_alp0_minerr_cpar5 : rate0 (for mierrth1) of curve to map mierr to alp0 for chroma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 64 ++#define NR_ALP0C_ERR2CURV_LIMIT (0x3218) ++#define P_NR_ALP0C_ERR2CURV_LIMIT (volatile unsigned int *)((0x3218 << 2) + 0xff900000) ++//Bit 31:24, reg_nr_alp0_minerr_cpar2 : level limit(for mierrth1) of curve to map mierr to alp0 for chroma channel, this will be set to alp0 that we can do for texture region. 0~255.. unsigned , default = 63 ++//Bit 7: 0, reserved ++#define NR_ALP0_MIN_MAX (0x3219) ++#define P_NR_ALP0_MIN_MAX (volatile unsigned int *)((0x3219 << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:24, reg_nr_alp0_ymin : normalized to 64 as '1' . unsigned , default = 0 ++//Bit 23:22, reserved ++//Bit 21:16, reg_nr_alp0_ymax : normalized to 64 as '1' . unsigned , default = 63 ++//Bit 15:14, reserved ++//Bit 13: 8, reg_nr_alp0_cmin : normalized to 64 as '1' . unsigned , default = 0 ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_nr_alp0_cmax : normalized to 64 as '1' . unsigned , default = 63 ++#define NR_ALP1_MIERR_CORING (0x321a) ++#define P_NR_ALP1_MIERR_CORING (volatile unsigned int *)((0x321a << 2) + 0xff900000) ++//Bit 31:17, reserved ++//Bit 16, reg_nr_alp1_maxerr_mode : 0 max err; 1: xerr . unsigned , default = 0 ++//Bit 15:14, reserved ++//Bit 13: 8, reg_nr_alp1_core_rate : normalized 64 as "1" . unsigned , default = 0 ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_nr_alp1_core_ofst : normalized 64 as "1" . signed , default = 3 ++#define NR_ALP1_ERR2CURV_TH_RATE (0x321b) ++#define P_NR_ALP1_ERR2CURV_TH_RATE (volatile unsigned int *)((0x321b << 2) + 0xff900000) ++//Bit 31:24, reg_nr_alp1_minerr_par0 : threshold0 of curve to map mierr to alp1 for luma/chroma channel, this will be set value of flat region mierr that no need directional NR. 0~255.. unsigned , default = 0 ++//Bit 23:16, reg_nr_alp1_minerr_par1 : threshold1 of curve to map mierr to alp1 for luma/chroma channel,this will be set value of texture region mierr that can not do directional NR. 0~255.. unsigned , default = 24 ++//Bit 15: 8, reg_nr_alp1_minerr_par5 : rate0 (for mierrth1) of curve to map mierr to alp1 for luma/chroma channel. the larger of the value, the deep of the slope. 0~255. unsigned , default = 20 ++#define NR_ALP1_ERR2CURV_LIMIT (0x321c) ++#define P_NR_ALP1_ERR2CURV_LIMIT (volatile unsigned int *)((0x321c << 2) + 0xff900000) ++//Bit 31:24, reg_nr_alp1_minerr_par2 : level limit(for mierrth1) of curve to map mierr to alp1 for luma/chroma channel, this will be set to alp1 that we can do for texture region. 0~255.255 before. unsigned , default = 63 ++//Bit 7: 0, reserved ++#define NR_ALP1_MIN_MAX (0x321d) ++#define P_NR_ALP1_MIN_MAX (volatile unsigned int *)((0x321d << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:24, reg_nr_alp1_ymin : normalized to 64 as '1' . unsigned , default = 0 ++//Bit 23:22, reserved ++//Bit 21:16, reg_nr_alp1_ymax : normalized to 64 as '1' . unsigned , default = 63 ++//Bit 15:14, reserved ++//Bit 13: 8, reg_nr_alp1_cmin : normalized to 64 as '1' . unsigned , default = 0 ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_nr_alp1_cmax : normalized to 64 as '1' . unsigned , default = 63 ++#define PK_ALP2_MIERR_CORING (0x321e) ++#define P_PK_ALP2_MIERR_CORING (volatile unsigned int *)((0x321e << 2) + 0xff900000) ++//Bit 31:17, reserved ++//Bit 16, reg_pk_alp2_maxerr_mode : 0 max err; 1: xerr . unsigned , default = 1 ++//Bit 15:14, reserved ++//Bit 13: 8, reg_pk_alp2_core_rate : normalized 64 as "1" . unsigned , default = 0 ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_pk_alp2_core_ofst : normalized 64 as "1" . signed , default = 1 ++#define PK_ALP2_ERR2CURV_TH_RATE (0x321f) ++#define P_PK_ALP2_ERR2CURV_TH_RATE (volatile unsigned int *)((0x321f << 2) + 0xff900000) ++//Bit 31:24, reg_pk_alp2_minerr_par0 : threshold0 of curve to map mierr to alp2 for luma channel, this will be set value of flat region mierr that no need peaking.. unsigned , default = 0 ++//Bit 23:16, reg_pk_alp2_minerr_par1 : threshold1 of curve to map mierr to alp2 for luma channel,this will be set value of texture region mierr that can not do peaking. 0~255.. unsigned , default = 24 ++//Bit 15: 8, reg_pk_alp2_minerr_par5 : rate0 (for mierrth1) of curve to map mierr to alp2 for luma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 20 ++#define PK_ALP2_ERR2CURV_LIMIT (0x3220) ++#define P_PK_ALP2_ERR2CURV_LIMIT (volatile unsigned int *)((0x3220 << 2) + 0xff900000) ++//Bit 31:24, reg_pk_alp2_minerr_par2 : level limit(for mierrth1) of curve to map mierr to alp2 for luma channel, this will be set to alp2 that we can do for texture region. 0~255. default = 32;. unsigned , default = 32 ++//Bit 7: 0, reserved ++#define PK_ALP2_MIN_MAX (0x3221) ++#define P_PK_ALP2_MIN_MAX (volatile unsigned int *)((0x3221 << 2) + 0xff900000) ++//Bit 31:14, reserved ++//Bit 13: 8, reg_pk_alp2_min : normalized to 64 as '1' . unsigned , default = 0 ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_pk_alp2_max : normalized to 64 as '1' . unsigned , default = 63 ++#define PK_FINALGAIN_HP_BP (0x3222) ++#define P_PK_FINALGAIN_HP_BP (volatile unsigned int *)((0x3222 << 2) + 0xff900000) ++//Bit 31:18, reserved ++//Bit 17:16, reg_final_gain_rs : s2: right shift bits for the gain normalization, 0 normal to 32 as 1; 1 normalize to 64 as 1; -2 normalized to 8 as 1; -1 normalize 16 as 1. default = 0 ++//Bit 15: 8, reg_hp_final_gain : gain to highpass boost result (including directional/circle blending), normalized 32 as '1', 0~255. 1.25 * 32. unsigned , default = 40 ++//Bit 7: 0, reg_bp_final_gain : gain to bandpass boost result (including directional/circle blending), normalized 32 as '1', 0~255. 1.25 * 32. unsigned , default = 30 ++#define PK_OS_HORZ_CORE_GAIN (0x3223) ++#define P_PK_OS_HORZ_CORE_GAIN (volatile unsigned int *)((0x3223 << 2) + 0xff900000) ++//Bit 31:24, reg_pk_os_hsidecore : side coring (not to current pixel) to adaptive overshoot margin in horizontal direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 8 ++//Bit 23:16, reg_pk_os_hsidegain : side gain (not to current pixel) to adaptive overshoot margin in horizontal direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20 ++//Bit 15: 8, reg_pk_os_hmidcore : midd coring (to current pixel) to adaptive overshoot margin in horizontal direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 2 ++//Bit 7: 0, reg_pk_os_hmidgain : midd gain (to current pixel) to adaptive overshoot margin in horizontal direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20 ++#define PK_OS_VERT_CORE_GAIN (0x3224) ++#define P_PK_OS_VERT_CORE_GAIN (volatile unsigned int *)((0x3224 << 2) + 0xff900000) ++//Bit 31:24, reg_pk_os_vsidecore : side coring (not to current pixel) to adaptive overshoot margin in vertical direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 8 ++//Bit 23:16, reg_pk_os_vsidegain : side gain (not to current pixel) to adaptive overshoot margin in vertical direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20 ++//Bit 15: 8, reg_pk_os_vmidcore : midd coring (to current pixel) to adaptive overshoot margin in vertical direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 2 ++//Bit 7: 0, reg_pk_os_vmidgain : midd gain (to current pixel) to adaptive overshoot margin in vertical direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20 ++#define PK_OS_ADPT_MISC (0x3225) ++#define P_PK_OS_ADPT_MISC (volatile unsigned int *)((0x3225 << 2) + 0xff900000) ++//Bit 31:24, reg_pk_os_minerr_core : coring to minerr for adaptive overshoot margin. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 40 ++//Bit 23:16, reg_pk_os_minerr_gain : gain to minerr based adaptive overshoot margin. normalized to 64 as '1'. 0~255;. unsigned , default = 6 ++//Bit 15: 8, reg_pk_os_adpt_max : maximum limit adaptive overshoot margin (4x). 0~255; . unsigned , default = 200 ++//Bit 7: 0, reg_pk_os_adpt_min : minimun limit adaptive overshoot margin (1x). 0~255; . unsigned , default = 20 ++#define PK_OS_STATIC (0x3226) ++#define P_PK_OS_STATIC (volatile unsigned int *)((0x3226 << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:28, reg_pk_osh_mode : 0~3: (2x+1) window in H direction . unsigned , default = 2 ++//Bit 27:26, reserved ++//Bit 25:24, reg_pk_osv_mode : 0~3: (2x+1) window in V direction . unsigned , default = 2 ++//Bit 23:22, reserved ++//Bit 21:12, reg_pk_os_down : static negative overshoot margin. 0~1023; . unsigned , default = 200 ++//Bit 11:10, reserved ++//Bit 9: 0, reg_pk_os_up : static positive overshoot margin. 0~1023; . unsigned , default = 200 ++#define PK_NR_ENABLE (0x3227) ++#define P_PK_NR_ENABLE (volatile unsigned int *)((0x3227 << 2) + 0xff900000) ++//Bit 31: 4, reserved ++//Bit 3: 2, reg_3d_mode , 0: no 3D; 1: L/R; 2: T/B; 3: horizontal interleaved, dft = 0 //. unsigned , default = 0 ++//Bit 1, reg_pk_en . unsigned , default = 1 ++//Bit 0, reg_nr_en . unsigned , default = 1 ++#define PK_DRT_SAD_MISC (0x3228) ++#define P_PK_DRT_SAD_MISC (volatile unsigned int *)((0x3228 << 2) + 0xff900000) ++//Bit 31:24, reg_pk_sad_ver_gain : gain to sad[4], 16 normalized to "1"; . unsigned , default = 32 ++//Bit 23:16, reg_pk_sad_hor_gain : gain to sad[0], 16 normalized to "1"; . unsigned , default = 24 ++//Bit 15:12, reserved ++//Bit 11 reserved ++//Bit 10: 9, reg_pk_bias_diag : bias towards diag . unsigned , default = 0 ++//Bit 8, reserved ++//Bit 7: 5, reserved ++//Bit 4: 0, reg_pk_drt_force : force direction of drt peaking filter, h2b: 0:hp drt force, 1: bp drt force; 2: bp+hp drt force, 3: no force;. unsigned , default = 24 ++#define NR_TI_DNLP_BLEND (0x3229) ++#define P_NR_TI_DNLP_BLEND (volatile unsigned int *)((0x3229 << 2) + 0xff900000) ++//Bit 31:11, reserved ++//Bit 10: 8, reg_dnlp_input_mode : dnlp input options. 0: org_y; 1: gau_y; 2: gauadp_y; 3: edgadplpf_y; 4: nr_y;5: lti_y; 6: pk_y (before os);7: pk_y (after os). unsigned , default = 4 ++//Bit 7: 4, reserved ++//Bit 3: 2, reg_nr_cti_blend_mode : blend mode of nr and lti result: 0: nr; 1:cti; 2: (nr+cti)/2; 3:cti + dlt_nr . unsigned , default = 1 ++//Bit 1: 0, reg_nr_lti_blend_mode : blend mode of nr and lti result: 0: nr; 1:lti; 2: (nr+lti)/2; 3:lti + dlt_nr . unsigned , default = 2 ++//////////////////////////////////////////////////////////////////////////////// ++// new ti regsters from here ++//////////////////////////////////////////////////////////////////////////////// ++#define LTI_DIR_CORE_ALPHA (0x322a) ++#define P_LTI_DIR_CORE_ALPHA (volatile unsigned int *)((0x322a << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:24, reg_adp_lti_dir_alp_core_ofst : ofst to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=10. unsigned , default = 10 ++//Bit 23:20, reserved ++//Bit 19:16, reg_adp_lti_dir_alp_core_rate : ofset to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=0/32. unsigned , default = 0 ++//Bit 15:14, reserved ++//Bit 13: 8, reg_adp_lti_dir_alpmin : min value of alpha, alpha = (min_err+x +ofst)/max_err*64; dft=10 . unsigned , default = 0 ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_adp_lti_dir_alpmax : max value of alpha, alpha = (min_err+x +ofst)/max_err*64; dft=63 . unsigned , default = 63 ++#define CTI_DIR_ALPHA (0x322b) ++#define P_CTI_DIR_ALPHA (volatile unsigned int *)((0x322b << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:24, reg_adp_cti_dir_alp_core_ofst : ofst to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=10. unsigned , default = 5 ++//Bit 23:20, reserved ++//Bit 19:16, reg_adp_cti_dir_alp_core_rate : ofset to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=0/32. unsigned , default = 0 ++//Bit 15:14, reserved ++//Bit 13: 8, reg_adp_cti_dir_alpmin : min value of alpha, alpha = (min_err +x+ofst)/max_err*64; dft=10 . unsigned , default = 0 ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_adp_cti_dir_alpmax : max value of alpha, alpha = (min_err +x+ofst)/max_err*64; dft=63 . unsigned , default = 63 ++#define LTI_CTI_DF_GAIN (0x322c) ++#define P_LTI_CTI_DF_GAIN (volatile unsigned int *)((0x322c << 2) + 0xff900000) ++//Bit 31:30, reserved ++//Bit 29:24, reg_adp_lti_hdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12 ++//Bit 23:22, reserved ++//Bit 21:16, reg_adp_lti_vdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12 ++//Bit 15:14, reserved ++//Bit 13: 8, reg_adp_cti_hdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12 ++//Bit 7: 6, reserved ++//Bit 5: 0, reg_adp_cti_vdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12 ++#define LTI_CTI_DIR_AC_DBG (0x322d) ++#define P_LTI_CTI_DIR_AC_DBG (volatile unsigned int *)((0x322d << 2) + 0xff900000) ++//Bit 31, reserved ++//Bit 30, reg_adp_lti_dir_lpf : 0: no lpf; 1: [1 2 2 2 1]/8 lpf . unsigned , default = 1 ++//Bit 29, reserved ++//Bit 28, reg_adp_lti_dir_difmode : 0: y_dif; 1: y_dif + (u_dif+v_dif)/2; . unsigned , default = 1 ++//Bit 27, reserved ++//Bit 26, reg_adp_cti_dir_lpf : 0: no lpf; 1: [1 2 2 2 1]/8 lpf dft=1 . unsigned , default = 1 ++//Bit 25:24, reg_adp_cti_dir_difmode : 0: (u_dif+v_dif); 1: y_dif/2 + (u_dif+v_dif)*3/4; 2: y_dif + (u_dif+v_dif)/2; 3: y_dif*2 (not recomended). unsigned , default = 2 ++//Bit 23:22, reg_adp_hvlti_dcblend_mode : 0: hlti_dc; 1:vlti_dc; 2: avg 3; blend on alpha . unsigned , default = 3 ++//Bit 21:20, reg_adp_hvcti_dcblend_mode : 0: hcti_dc; 1:vcti_dc; 2: avg 3; blend on alpha . unsigned , default = 2 ++//Bit 19:18, reg_adp_hvlti_acblend_mode : hlti_ac; 1:vlti_ac; 2: add 3;:adaptive to alpha . unsigned , default = 3 ++//Bit 17:16, reg_adp_hvcti_acblend_mode : hcti_ac; 1:vcti_ac; 2: add 3;: adaptive to alpha . unsigned , default = 2 ++//Bit 15, reserved ++//Bit 14:12, reg_adp_hlti_debug , for hlti debug, default = 0 . unsigned , default = 0 ++//Bit 11, reserved ++//Bit 10: 8, reg_adp_vlti_debug , for vlti debug, default = 0 . unsigned , default = 0 ++//Bit 7, reserved ++//Bit 6: 4, reg_adp_hcti_debug , for hcti debug, default = 0 . unsigned , default = 0 ++//Bit 3, reserved ++//Bit 2: 0, reg_adp_vcti_debug , for vcti debug, default = 0 . unsigned , default = 0 ++#define HCTI_FLT_CLP_DC (0x322e) ++#define P_HCTI_FLT_CLP_DC (volatile unsigned int *)((0x322e << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28, reg_adp_hcti_en , 0: no cti, 1: new cti, default = 1 . unsigned , default = 1 ++//Bit 27:26, reg_adp_hcti_vdn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 ++//Bit 25:24, reg_adp_hcti_hdn_flt , 0: no lpf; 1:[0, 0, 0, 4, 8, 4, 0, 0, 0], 2:[0, 0, 2, 4, 4, 4, 2, 0, 0], 3: [1, 2, 2, 2, 2, 2, 2, 2, 1], default = 2. unsigned , default = 2 ++//Bit 23:22, reg_adp_hcti_ddn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 ++//Bit 21:20, reg_adp_hcti_lpf0_flt , 0:no filter; 1:sigma=0.75, 2: sigma = 1.0, 3: sigma = 1.5, default = 1 . unsigned , default = 1 ++//Bit 19:18, reg_adp_hcti_lpf1_flt , 0:no filter; 1:sigma= 2.0, 2: sigma = 3.0, 3: sigma = 4.0, default = 1 . unsigned , default = 1 ++//Bit 17:16, reg_adp_hcti_lpf2_flt , 0:no filter; 1:sigma=5.0, 2: sigma = 9.0, 3: sigma = 13.0, default = 1 . unsigned , default = 1 ++//Bit 15:12, reg_adp_hcti_hard_clp_win , window size, 0~8, default = 5 . unsigned , default = 5 ++//Bit 11: 8, reg_adp_hcti_hard_win_min , window size, 0~8, default = 3 . unsigned , default = 3 ++//Bit 7: 5, reserved ++//Bit 4, reg_adp_hcti_clp_mode , 0: hard clip, 1: adaptive clip, default = 1 . unsigned , default = 1 ++//Bit 3, reserved ++//Bit 2: 0, reg_adp_hcti_dc_mode , 0:dn, 1:lpf0, 2:lpf1, 3:lpf2, 4: lpf3: 5: vdn result; 6/7:org, default = 0 . unsigned , default = 0 ++#define HCTI_BST_GAIN (0x322f) ++#define P_HCTI_BST_GAIN (volatile unsigned int *)((0x322f << 2) + 0xff900000) ++//Bit 31:24, reg_adp_hcti_bst_gain0 : gain of the bandpass 0 (lpf1-lpf2)- LBP, default = 80 . unsigned , default = 80 ++//Bit 23:16, reg_adp_hcti_bst_gain1 : gain of the bandpass 1 (lpf0-lpf1)- BP, default = 96 . unsigned , default = 96 ++//Bit 15: 8, reg_adp_hcti_bst_gain2 : gain of the bandpass 2 (hdn-lpf0)- HP, default = 64 . unsigned , default = 64 ++//Bit 7: 0, reg_adp_hcti_bst_gain3 : gain of the unsharp band (yuvin-hdn) - US, default = 16 . unsigned , default = 16 ++#define HCTI_BST_CORE (0x3230) ++#define P_HCTI_BST_CORE (volatile unsigned int *)((0x3230 << 2) + 0xff900000) ++//Bit 31:24, reg_adp_hcti_bst_core0 : core of the bandpass 0 (lpf1-lpf2)- LBP, default = 5 . unsigned , default = 5 ++//Bit 23:16, reg_adp_hcti_bst_core1 : core of the bandpass 1 (lpf0-lpf1)- BP, default = 5 . unsigned , default = 5 ++//Bit 15: 8, reg_adp_hcti_bst_core2 : core of the bandpass 2 (hdn-lpf0)- HP, default = 5 . unsigned , default = 5 ++//Bit 7: 0, reg_adp_hcti_bst_core3 : core of the unsharp band (yuvin-hdn) - US, default = 3 . unsigned , default = 5 ++#define HCTI_CON_2_GAIN_0 (0x3231) ++#define P_HCTI_CON_2_GAIN_0 (volatile unsigned int *)((0x3231 << 2) + 0xff900000) ++//Bit 31:29, reg_adp_hcti_con_mode : con mode 0:[0, 0,-1, 1, 0, 0, 0]+[0, 0, 0, 1,-1, 0, 0], 1: [0, 0,-1, 0, 1, 0, 0], 2: [0,-1, 0, 0, 0, 1, 0], 3:[-1, 0, 0, 0, 0, 0, 1], 4: .... default = 1. unsigned , default = 1 ++//Bit 28:26, reg_adp_hcti_dx_mode : dx mode 0: [-1 1 0]; 1~7: [-1 (2x+1)"0" 1], default = 2 . unsigned , default = 2 ++//Bit 25:24, reg_adp_hcti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0 ++//Bit 23:16, reg_adp_hcti_con_2_gain0 , default = 25 . unsigned , default = 25 ++//Bit 15: 8, reg_adp_hcti_con_2_gain1 , default = 60 . unsigned , default = 60 ++//Bit 7: 0, reg_adp_hcti_con_2_gain2 0;, default = 5 . unsigned , default = 5 ++#define HCTI_CON_2_GAIN_1 (0x3232) ++#define P_HCTI_CON_2_GAIN_1 (volatile unsigned int *)((0x3232 << 2) + 0xff900000) ++//Bit 31:24, reg_adp_hcti_con_2_gain3 96;, default = 96 . unsigned , default = 96 ++//Bit 23:16, reg_adp_hcti_con_2_gain4 5;, default = 5 . unsigned , default = 5 ++//Bit 15: 8, reg_adp_hcti_con_2_gain5 80;, default = 80 . unsigned , default = 80 ++//Bit 7: 0, reg_adp_hcti_con_2_gain6 20;, default = 20 . unsigned , default = 20 ++#define HCTI_OS_MARGIN (0x3233) ++#define P_HCTI_OS_MARGIN (volatile unsigned int *)((0x3233 << 2) + 0xff900000) ++//Bit 31: 8, reserved ++//Bit 7: 0, reg_adp_hcti_os_margin : margin for hcti overshoot, default = 0 . unsigned , default = 0 ++#define HLTI_FLT_CLP_DC (0x3234) ++#define P_HLTI_FLT_CLP_DC (volatile unsigned int *)((0x3234 << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28, reg_adp_hlti_en , 0: no cti, 1: new cti, default = 1 . unsigned , default = 1 ++//Bit 27:26, reg_adp_hlti_vdn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 ++//Bit 25:24, reg_adp_hlti_hdn_flt , 0: no lpf; 1:[0, 0, 0, 4, 8, 4, 0, 0, 0], 2:[0, 0, 2, 4, 4, 4, 2, 0, 0], 3: [1, 2, 2, 2, 2, 2, 2, 2, 1], default = 1. unsigned , default = 1 ++//Bit 23:22, reg_adp_hlti_ddn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 1 . unsigned , default = 1 ++//Bit 21:20, reg_adp_hlti_lpf0_flt , 0:no filter; 1:sigma=0.75, 2: sigma = 1.0, 3: sigma = 1.5, default = 1 . unsigned , default = 1 ++//Bit 19:18, reg_adp_hlti_lpf1_flt , 0:no filter; 1:sigma= 2.0, 2: sigma = 3.0, 3: sigma = 4.0, default = 1 . unsigned , default = 1 ++//Bit 17:16, reg_adp_hlti_lpf2_flt , 0:no filter; 1:sigma=5.0, 2: sigma = 9.0, 3: sigma = 13.0, default = 1 . unsigned , default = 1 ++//Bit 15:12, reg_adp_hlti_hard_clp_win , window size, 0~8, default = 2 . unsigned , default = 2 ++//Bit 11: 8, reg_adp_hlti_hard_win_min , window size, 0~8, default = 1 . unsigned , default = 1 ++//Bit 7: 5, reserved ++//Bit 4, reg_adp_hlti_clp_mode , 0: hard clip, 1: adaptive clip, default = 0 . unsigned , default = 0 ++//Bit 3, reserved ++//Bit 2: 0, reg_adp_hlti_dc_mode , 0:dn, 1:lpf0, 2:lpf1, 3:lpf2, 4: lpf3: 5: vdn result; 6/7:org, default = 4 . unsigned , default = 4 ++#define HLTI_BST_GAIN (0x3235) ++#define P_HLTI_BST_GAIN (volatile unsigned int *)((0x3235 << 2) + 0xff900000) ++//Bit 31:24, reg_adp_hlti_bst_gain0 : gain of the bandpass 0 (lpf1-lpf2)- LBP, default = 32 . unsigned , default = 32 ++//Bit 23:16, reg_adp_hlti_bst_gain1 : gain of the bandpass 1 (lpf0-lpf1)- BP, default = 32 . unsigned , default = 32 ++//Bit 15: 8, reg_adp_hlti_bst_gain2 : gain of the bandpass 2 (hdn-lpf0)- HP, default = 28 . unsigned , default = 28 ++//Bit 7: 0, reg_adp_hlti_bst_gain3 : gain of the unsharp band (yuvin-hdn) - US, default = 12 . unsigned , default = 12 ++#define HLTI_BST_CORE (0x3236) ++#define P_HLTI_BST_CORE (volatile unsigned int *)((0x3236 << 2) + 0xff900000) ++//Bit 31:24, reg_adp_hlti_bst_core0 : core of the bandpass 0 (lpf1-lpf2)- LBP, default = 5 . unsigned , default = 5 ++//Bit 23:16, reg_adp_hlti_bst_core1 : core of the bandpass 1 (lpf0-lpf1)- BP, default = 5 . unsigned , default = 5 ++//Bit 15: 8, reg_adp_hlti_bst_core2 : core of the bandpass 2 (hdn-lpf0)- HP, default = 5 . unsigned , default = 5 ++//Bit 7: 0, reg_adp_hlti_bst_core3 : core of the unsharp band (yuvin-hdn) - US, default = 3 . unsigned , default = 3 ++#define HLTI_CON_2_GAIN_0 (0x3237) ++#define P_HLTI_CON_2_GAIN_0 (volatile unsigned int *)((0x3237 << 2) + 0xff900000) ++//Bit 31:29, reg_adp_hlti_con_mode : con mode 0:[0, 0,-1, 1, 0, 0, 0]+[0, 0, 0, 1,-1, 0, 0], 1: [0, 0,-1, 0, 1, 0, 0], 2: [0,-1, 0, 0, 0, 1, 0], 3:[-1, 0, 0, 0, 0, 0, 1], 4: ....., default = 1. unsigned , default = 1 ++//Bit 28:26, reg_adp_hlti_dx_mode : dx mode 0: [-1 1 0]; 1~7: [-1 (2x+1)"0" 1], default = 1 . unsigned , default = 1 ++//Bit 25:24, reg_adp_hlti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0 ++//Bit 23:16, reg_adp_hlti_con_2_gain0 25;, default = 25 . unsigned , default = 25 ++//Bit 15: 8, reg_adp_hlti_con_2_gain1 60;, default = 60 . unsigned , default = 60 ++//Bit 7: 0, reg_adp_hlti_con_2_gain2 0;, default = 5 . unsigned , default = 5 ++#define HLTI_CON_2_GAIN_1 (0x3238) ++#define P_HLTI_CON_2_GAIN_1 (volatile unsigned int *)((0x3238 << 2) + 0xff900000) ++//Bit 31:24, reg_adp_hlti_con_2_gain3 96;, default = 96 . unsigned , default = 96 ++//Bit 23:16, reg_adp_hlti_con_2_gain4 5;, default = 95 . unsigned , default = 95 ++//Bit 15: 8, reg_adp_hlti_con_2_gain5 80;, default = 80 . unsigned , default = 80 ++//Bit 7: 0, reg_adp_hlti_con_2_gain6 20;, default = 20 . unsigned , default = 20 ++#define HLTI_OS_MARGIN (0x3239) ++#define P_HLTI_OS_MARGIN (volatile unsigned int *)((0x3239 << 2) + 0xff900000) ++//Bit 31: 8, reserved ++//Bit 7: 0, reg_adp_hlti_os_margin : margin for hlti overshoot, default = 0 . unsigned , default = 0 ++#define VLTI_FLT_CON_CLP (0x323a) ++#define P_VLTI_FLT_CON_CLP (volatile unsigned int *)((0x323a << 2) + 0xff900000) ++//Bit 31:15, reserved ++//Bit 14, reg_adp_vlti_en : enable bit of vlti, default = 1 . unsigned , default = 1 ++//Bit 13:12, reg_adp_vlti_hxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 ++//Bit 11:10, reg_adp_vlti_dxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 ++//Bit 9: 8, reg_adp_vlti_han_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 ++//Bit 7: 6, reg_adp_vlti_dan_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 ++//Bit 5: 4, reg_adp_vlti_dx_mode : 0:[-1 1] 1:[-1 0 -1]; 2/3: [-1 0 0 0 -1], default = 1 . unsigned , default = 1 ++//Bit 3, reserved ++//Bit 2, reg_adp_vlti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0 ++//Bit 1, reserved ++//Bit 0, reg_adp_vlti_hard_clp_win : window size; 0: 1x3 window; 1: 1x5 window, default = 0 . unsigned , default = 0 ++#define VLTI_BST_GAIN (0x323b) ++#define P_VLTI_BST_GAIN (volatile unsigned int *)((0x323b << 2) + 0xff900000) ++//Bit 31:24, reserved ++//Bit 23:16, reg_adp_vlti_bst_gain0 : gain to boost filter [-1 2 -1];, default = 32 . unsigned , default = 32 ++//Bit 15: 8, reg_adp_vlti_bst_gain1 : gain to boost filter [-1 0 2 0 -1];, default = 32 . unsigned , default = 32 ++//Bit 7: 0, reg_adp_vlti_bst_gain2 : gain to boost filter usf, default = 32 . unsigned , default = 32 ++#define VLTI_BST_CORE (0x323c) ++#define P_VLTI_BST_CORE (volatile unsigned int *)((0x323c << 2) + 0xff900000) ++//Bit 31:24, reserved ++//Bit 23:16, reg_adp_vlti_bst_core0 : coring to boost filter [-1 2 -1];, default = 5 . unsigned , default = 5 ++//Bit 15: 8, reg_adp_vlti_bst_core1 : coring to boost filter [-1 0 2 0 -1];, default = 5 . unsigned , default = 5 ++//Bit 7: 0, reg_adp_vlti_bst_core2 : coring to boost filter usf, default = 3 . unsigned , default = 3 ++#define VLTI_CON_2_GAIN_0 (0x323d) ++#define P_VLTI_CON_2_GAIN_0 (volatile unsigned int *)((0x323d << 2) + 0xff900000) ++//Bit 31:24, reg_adp_vlti_con_2_gain0 25;, default = 25 . unsigned , default = 25 ++//Bit 23:16, reg_adp_vlti_con_2_gain1 60;, default = 60 . unsigned , default = 60 ++//Bit 15: 8, reg_adp_vlti_con_2_gain2 0;, default = 5 . unsigned , default = 5 ++//Bit 7: 0, reg_adp_vlti_con_2_gain3 96;, default = 96 . unsigned , default = 96 ++#define VLTI_CON_2_GAIN_1 (0x323e) ++#define P_VLTI_CON_2_GAIN_1 (volatile unsigned int *)((0x323e << 2) + 0xff900000) ++//Bit 31:24, reg_adp_vlti_con_2_gain4 5;, default = 95 . unsigned , default = 95 ++//Bit 23:16, reg_adp_vlti_con_2_gain5 80;, default = 80 . unsigned , default = 80 ++//Bit 15: 8, reg_adp_vlti_con_2_gain6 20;, default = 20 . unsigned , default = 20 ++//Bit 7: 0, reg_adp_vlti_os_margin : margin for vlti overshoot, default = 0 . unsigned , default = 0 ++#define VCTI_FLT_CON_CLP (0x323f) ++#define P_VCTI_FLT_CON_CLP (volatile unsigned int *)((0x323f << 2) + 0xff900000) ++//Bit 31:15, reserved ++//Bit 14, reg_adp_vcti_en : enable bit of vlti, default = 1 . unsigned , default = 1 ++//Bit 13:12, reg_adp_vcti_hxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 ++//Bit 11:10, reg_adp_vcti_dxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 ++//Bit 9: 8, reg_adp_vcti_han_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 ++//Bit 7: 6, reg_adp_vcti_dan_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 ++//Bit 5: 4, reg_adp_vcti_dx_mode : 0:[-1 1] 1:[-1 0 -1]; 2/3: [-1 0 0 0 -1], default = 1 . unsigned , default = 1 ++//Bit 3, reserved ++//Bit 2, reg_adp_vcti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0 ++//Bit 1, reserved ++//Bit 0, reg_adp_vcti_hard_clp_win : window size; 0: 1x3 window; 1: 1x5 window, default = 0 . unsigned , default = 0 ++#define VCTI_BST_GAIN (0x3240) ++#define P_VCTI_BST_GAIN (volatile unsigned int *)((0x3240 << 2) + 0xff900000) ++//Bit 31:24, reserved ++//Bit 23:16, reg_adp_vcti_bst_gain0 : gain to boost filter [-1 2 -1];, default = 16 . unsigned , default = 16 ++//Bit 15: 8, reg_adp_vcti_bst_gain1 : gain to boost filter [-1 0 2 0 -1];, default = 16 . unsigned , default = 16 ++//Bit 7: 0, reg_adp_vcti_bst_gain2 : gain to boost filter usf, default = 16 . unsigned , default = 16 ++#define VCTI_BST_CORE (0x3241) ++#define P_VCTI_BST_CORE (volatile unsigned int *)((0x3241 << 2) + 0xff900000) ++//Bit 31:24, reserved ++//Bit 23:16, reg_adp_vcti_bst_core0 : coring to boost filter [-1 2 -1];, default = 5 . unsigned , default = 5 ++//Bit 15: 8, reg_adp_vcti_bst_core1 : coring to boost filter [-1 0 2 0 -1];, default = 5 . unsigned , default = 5 ++//Bit 7: 0, reg_adp_vcti_bst_core2 : coring to boost filter usf, default = 3 . unsigned , default = 3 ++#define VCTI_CON_2_GAIN_0 (0x3242) ++#define P_VCTI_CON_2_GAIN_0 (volatile unsigned int *)((0x3242 << 2) + 0xff900000) ++//Bit 31:24, reg_adp_vcti_con_2_gain0 25;, default = 25 . unsigned , default = 25 ++//Bit 23:16, reg_adp_vcti_con_2_gain1 60;, default = 60 . unsigned , default = 60 ++//Bit 15: 8, reg_adp_vcti_con_2_gain2 0;, default = 5 . unsigned , default = 5 ++//Bit 7: 0, reg_adp_vcti_con_2_gain3 96;, default = 96 . unsigned , default = 96 ++#define VCTI_CON_2_GAIN_1 (0x3243) ++#define P_VCTI_CON_2_GAIN_1 (volatile unsigned int *)((0x3243 << 2) + 0xff900000) ++//Bit 31:24, reg_adp_vcti_con_2_gain4 5;, default = 95 . unsigned , default = 95 ++//Bit 23:16, reg_adp_vcti_con_2_gain5 80;, default = 80 . unsigned , default = 80 ++//Bit 15: 8, reg_adp_vcti_con_2_gain6 20;, default = 20 . unsigned , default = 20 ++//Bit 7: 0, reg_adp_vcti_os_margin : margin for vcti overshoot, default = 0 . unsigned , default = 0 ++#define SHARP_3DLIMIT (0x3244) ++#define P_SHARP_3DLIMIT (volatile unsigned int *)((0x3244 << 2) + 0xff900000) ++//Bit 31:29, reserved ++//Bit 28:16, reg_3d_mid_width ,width of left part of 3d input, dft = half size of input width default = 0 . unsigned , default = 960 ++//Bit 15:13, reserved ++//Bit 12: 0, reg_3d_mid_height ,height of left part of 3d input, dft = half size of input height default = 0 . unsigned , default = 540 ++#define DNLP_EN (0x3245) ++#define P_DNLP_EN (volatile unsigned int *)((0x3245 << 2) + 0xff900000) ++//Bit 31: 1, reserved ++//Bit 0, reg_dnlp_en . unsigned , default = 1 ++#define DNLP_00 (0x3246) ++#define P_DNLP_00 (volatile unsigned int *)((0x3246 << 2) + 0xff900000) ++//Bit 31: 0, reg_dnlp_ygrid0 : dnlp00 . unsigned , default = 32'h08060402 ++#define DNLP_01 (0x3247) ++#define P_DNLP_01 (volatile unsigned int *)((0x3247 << 2) + 0xff900000) ++//Bit 31: 0, reg_dnlp_ygrid1 : dnlp01 . unsigned , default = 32'h100e0c0a ++#define DNLP_02 (0x3248) ++#define P_DNLP_02 (volatile unsigned int *)((0x3248 << 2) + 0xff900000) ++//Bit 31: 0, reg_dnlp_ygrid2 : dnlp02 . unsigned , default = 32'h1a171412 ++#define DNLP_03 (0x3249) ++#define P_DNLP_03 (volatile unsigned int *)((0x3249 << 2) + 0xff900000) ++//Bit 31: 0, reg_dnlp_ygrid3 : dnlp03 . unsigned , default = 32'h2824201d ++#define DNLP_04 (0x324a) ++#define P_DNLP_04 (volatile unsigned int *)((0x324a << 2) + 0xff900000) ++//Bit 31: 0, reg_dnlp_ygrid4 : dnlp04 . unsigned , default = 32'h3834302c ++#define DNLP_05 (0x324b) ++#define P_DNLP_05 (volatile unsigned int *)((0x324b << 2) + 0xff900000) ++//Bit 31: 0, reg_dnlp_ygrid5 : dnlp05 . unsigned , default = 32'h4b45403c ++#define DNLP_06 (0x324c) ++#define P_DNLP_06 (volatile unsigned int *)((0x324c << 2) + 0xff900000) ++//Bit 31: 0, reg_dnlp_ygrid6 : dnlp06 . unsigned , default = 32'h605b5550 ++#define DNLP_07 (0x324d) ++#define P_DNLP_07 (volatile unsigned int *)((0x324d << 2) + 0xff900000) ++//Bit 31: 0, reg_dnlp_ygrid7 : dnlp07 . unsigned , default = 32'h80787068 ++#define DNLP_08 (0x324e) ++#define P_DNLP_08 (volatile unsigned int *)((0x324e << 2) + 0xff900000) ++//Bit 31: 0, reg_dnlp_ygrid8 : dnlp08 . unsigned , default = 32'ha0989088 ++#define DNLP_09 (0x324f) ++#define P_DNLP_09 (volatile unsigned int *)((0x324f << 2) + 0xff900000) ++//Bit 31: 0, reg_dnlp_ygrid9 : dnlp09 . unsigned , default = 32'hb8b2aca6 ++#define DNLP_10 (0x3250) ++#define P_DNLP_10 (volatile unsigned int *)((0x3250 << 2) + 0xff900000) ++//Bit 31: 0, reg_dnlp_ygrid10 : dnlp10 . unsigned , default = 32'hc8c4c0bc ++#define DNLP_11 (0x3251) ++#define P_DNLP_11 (volatile unsigned int *)((0x3251 << 2) + 0xff900000) ++//Bit 31: 0, reg_dnlp_ygrid11 : dnlp11 . unsigned , default = 32'hd4d2cecb ++#define DNLP_12 (0x3252) ++#define P_DNLP_12 (volatile unsigned int *)((0x3252 << 2) + 0xff900000) ++//Bit 31: 0, reg_dnlp_ygrid12 : dnlp12 . unsigned , default = 32'hdad8d7d6 ++#define DNLP_13 (0x3253) ++#define P_DNLP_13 (volatile unsigned int *)((0x3253 << 2) + 0xff900000) ++//Bit 31: 0, reg_dnlp_ygrid13 : dnlp13 . unsigned , default = 32'he2e0dedc ++#define DNLP_14 (0x3254) ++#define P_DNLP_14 (volatile unsigned int *)((0x3254 << 2) + 0xff900000) ++//Bit 31: 0, reg_dnlp_ygrid14 : dnlp14 . unsigned , default = 32'hf0ece8e4 ++#define DNLP_15 (0x3255) ++#define P_DNLP_15 (volatile unsigned int *)((0x3255 << 2) + 0xff900000) ++//Bit 31: 0, reg_dnlp_ygrid15 : dnlp15 . unsigned , default = 32'hfffcf8f4 ++#define DEMO_CRTL (0x3256) ++#define P_DEMO_CRTL (volatile unsigned int *)((0x3256 << 2) + 0xff900000) ++//Bit 31:19, reserved ++//Bit 18:17, demo_disp_position . unsigned , default = 2 ++//Bit 16, demo_hsvsharp_enable . unsigned , default = 0 ++//Bit 15:13, reserved ++//Bit 12: 0, demo_left_top_screen_width : . unsigned , default = 360 ++#define SHARP_SR2_CTRL (0x3257) ++#define P_SHARP_SR2_CTRL (volatile unsigned int *)((0x3257 << 2) + 0xff900000) ++//Bit 31:22, reserved ++//Bit 21:16, reg_sr2_pk_la_err_dis_rate : . unsigned , low angle and high angle error should not be no less than nearby_error*rate/64; default = 24 ++//Bit 15:8, reg_sr2_pk_sad_diag_gain : . unsigned , gain to sad[2] and sad[6], 16 normalized to "1"; default = 16 ++//Bit 7, reg_sr2_vert_outphs : . unsigned , default = 0 ++//Bit 6, reg_sr2_horz_outphs : . unsigned , default = 0 ++//Bit 5, reg_sr2_vert_ratio : . unsigned , default = 0 ++//Bit 4, reg_sr2_hori_ratio : . unsigned , default = 0 ++//Bit 3, reg_sr2_bic_norm : . unsigned , default = 1 ++//Bit 2, reg_sr2_enable : . unsigned , default = 0 ++//Bit 1, reg_sr2_sharp_prc_lr_hbic : . unsigned , default = 0 ++//Bit 0, reg_sr2_sharp_prc_lr : lti/cti/nr/peaking processing using LR grid, 0: on HR grid; 1:on LR grid, horizontally no upscale, but using simple bic . unsigned , default = 0 ++#define SHARP_SR2_YBIC_HCOEF0 (0x3258) ++#define P_SHARP_SR2_YBIC_HCOEF0 (volatile unsigned int *)((0x3258 << 2) + 0xff900000) ++//Bit 31:24, reg_sr2_y_bic_hcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel Filter will be normalized to 128 as 鈥?鈥? default=0 ++//Bit 23:16, reg_sr2_y_bic_hcoef02 the same as above; default=0 ++//Bit 15: 8, reg_sr2_y_bic_hcoef01 the same as above; default=64 ++//Bit 7: 0, reg_sr2_y_bic_hcoef00 the same as above; default=0 ++#define SHARP_SR2_YBIC_HCOEF1 (0x3259) ++#define P_SHARP_SR2_YBIC_HCOEF1 (volatile unsigned int *)((0x3259 << 2) + 0xff900000) ++//Bit 31:24, reg_sr2_y_bic_hcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channel,Filter will be normalized to 128 as 鈥?鈥? default=-4 ++//Bit 23:16, reg_sr2_y_bic_hcoef12 the same as above; default=36 ++//Bit 15: 8, reg_sr2_y_bic_hcoef11 the same as above; default=36 ++//Bit 7: 0, reg_sr2_y_bic_hcoef10 the same as above; default=-4 ++#define SHARP_SR2_CBIC_HCOEF0 (0x325a) ++#define P_SHARP_SR2_CBIC_HCOEF0 (volatile unsigned int *)((0x325a << 2) + 0xff900000) ++//Bit 31:24, reg_sr2_c_bic_hcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel ,Filter will be normalized to 128 as 鈥?鈥? default=0 ++//Bit 23:16, reg_sr2_c_bic_hcoef02 the same as above; default=21 ++//Bit 15: 8, reg_sr2_c_bic_hcoef01 the same as above; default=22 ++//Bit 7: 0, reg_sr2_c_bic_hcoef00 the same as above; default=21 ++#define SHARP_SR2_CBIC_HCOEF1 (0x325b) ++#define P_SHARP_SR2_CBIC_HCOEF1 (volatile unsigned int *)((0x325b << 2) + 0xff900000) ++//Bit 31:24, reg_sr2_c_bic_hcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channel,Filter will be normalized to 128 as 鈥?鈥? default=-4 ++//Bit 23:16, reg_sr2_c_bic_hcoef12 the same as above; default=36 ++//Bit 15: 8, reg_sr2_c_bic_hcoef11 the same as above; default=36 ++//Bit 7: 0, reg_sr2_c_bic_hcoef10 the same as above; default=-4 ++#define SHARP_SR2_YBIC_VCOEF0 (0x325c) ++#define P_SHARP_SR2_YBIC_VCOEF0 (volatile unsigned int *)((0x325c << 2) + 0xff900000) ++//Bit 31:24, reg_sr2_y_bic_vcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel, Filter will be normalized to 128 as 鈥?鈥? default=0 ++//Bit 23:16, reg_sr2_y_bic_vcoef02 the same as above; default=0 ++//Bit 15: 8, reg_sr2_y_bic_vcoef01 the same as above; default=64 ++//Bit 7: 0, reg_sr2_y_bic_vcoef00 the same as above; default=0 ++#define SHARP_SR2_YBIC_VCOEF1 (0x325d) ++#define P_SHARP_SR2_YBIC_VCOEF1 (volatile unsigned int *)((0x325d << 2) + 0xff900000) ++//Bit 31:24, reg_sr2_y_bic_vcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channe, lFilter will be normalized to 128 as 鈥?鈥? default=-4 ++//Bit 23:16, reg_sr2_y_bic_vcoef12 the same as above; default=36 ++//Bit 15: 8, reg_sr2_y_bic_vcoef11 the same as above; default=36 ++//Bit 7: 0, reg_sr2_y_bic_vcoef10 the same as above; default=-4 ++#define SHARP_SR2_CBIC_VCOEF0 (0x325e) ++#define P_SHARP_SR2_CBIC_VCOEF0 (volatile unsigned int *)((0x325e << 2) + 0xff900000) ++//Bit 31:24, reg_sr2_c_bic_vcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel, Filter will be normalized to 128 as 鈥?鈥? default=0 ++//Bit 23:16, reg_sr2_c_bic_vcoef02 the same as above; default=21 ++//Bit 15: 8, reg_sr2_c_bic_vcoef01 the same as above; default=22 ++//Bit 7: 0, reg_sr2_c_bic_vcoef00 the same as above; default=21 ++#define SHARP_SR2_CBIC_VCOEF1 (0x325f) ++#define P_SHARP_SR2_CBIC_VCOEF1 (volatile unsigned int *)((0x325f << 2) + 0xff900000) ++//Bit 31:24, reg_sr2_c_bic_vcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channel,Filter will be normalized to 128 as 鈥?鈥? default=-4 ++//Bit 23:16, reg_sr2_c_bic_vcoef12 the same as above; default=36 ++//Bit 15: 8, reg_sr2_c_bic_vcoef11 the same as above; default=36 ++//Bit 7: 0, reg_sr2_c_bic_vcoef10 the same as above; default=-4 ++#define SHARP_SR2_MISC (0x3260) ++#define P_SHARP_SR2_MISC (volatile unsigned int *)((0x3260 << 2) + 0xff900000) ++//Bit 31:2, reserved ++//Bit 1, reg_sr2_cmpmux_bef : . unsigned , default = 0,0 no swap anf for YUV->YUV; 1, swapped and for RGB->GBR; ++//Bit 0, reg_sr2_cmpmux_aft : . unsigned , default = 0,0 no swap anf for YUV->YUV; 1, swapped and for GBR-RGB; ++#define SHARP_SR3_SAD_CTRL (0x3261) ++#define P_SHARP_SR3_SAD_CTRL (volatile unsigned int *)((0x3261 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:24 reg_sr3_pk_sad_core_rate // u6: rate of coring for sad(theta) - sad(theta+pi/2)*rate/64 ++//Bit 23:22 reserved ++//Bit 21:16 reg_sr3_lti_sad_core_rate // u6: rate of coring for sad(theta) - sad(theta+pi/2)*rate/64 , default= 6 ++//Bit 15:14 reserved ++//Bit 13:8 reg_sr3_cti_sad_core_rate // u6: rate of coring for sad(theta) - sad(theta+pi/2)*rate/64 , default= 6 ++//Bit 7, reg_sr3_lti_hsad_mode // u1: mode for hsad of lti caluclation; 0: block based; 1:othor shape; default= 1 ++//Bit 6, reg_sr3_cti_hsad_mode // u1: mode for hsad of cti caluclation; 0: block based; 1:othor shape; default= 1 ++//Bit 5, reg_sr3_lti_dsad_mode // u1: mode for dsad of lti caluclation, 0: block based; 1:othor shape; default= 1 ++//Bit 4, reg_sr3_cti_dsad_mode // u1: mode for dsad of cti caluclation, 0: block based; 1:othor shape; default= 1 ++//Bit 3, reg_sr3_lti_vsad_mode // u1: mode for vsad of lti caluclation, 0: block based; 1:othor shape; default= 1 ++//Bit 2, reg_sr3_cti_vsad_mode // u1: mode for vsad of cti caluclation, 0: block based; 1:othor shape; default= 1 ++//Bit 1, reg_sr3_lti_hsad_hlpf // u1: hlpf for hsad of lti caluclation, 0: no hlpf; 1: with [1 2 1] hlpf; default= 1 ++//Bit 0, reg_sr3_cti_hsad_hlpf // u1: hlpf for hsad of cti caluclation, 0: no hlpf; 1: with [1 2 1] hlpf; default= 1 ++#define SHARP_SR3_PK_CTRL0 (0x3262) ++#define P_SHARP_SR3_PK_CTRL0 (volatile unsigned int *)((0x3262 << 2) + 0xff900000) ++//Bit 31:12 reserved ++//Bit 11, reg_sr3_pk_sad_mode // u1: mode for sad of peaking and noise reduction, 0: block based; 1:othor shape; default= 1 ++//Bit 10, reg_sr3_pk_hsad_hlpf // u1: hlpf for hsad for peaking caluclation, 0: no hlpf; 1: with [1 2 2 2 1] hlpf; default= 1 ++//Bit 9, reg_sr3_pk_vsad_hlpf // u1: hlpf for vsad for peaking caluclation, 0: no hlpf; 1: with [1 2 2 2 1] hlpf; default= 1 ++//Bit 8, reg_sr3_pk_dsad_hlpf // u1: hlpf for dsad for peaking caluclation, 0: no hlpf; 1: with [1 2 2 2 1] hlpf; default= 1 ++//Bit 7:6, reg_sr3_pk_hpdrt_mode // u2: mode for HPdrt filter: default= 3 ++//Bit 5:4, reg_sr3_pk_bpdrt_mode // u2: mode for BPdrt filter: default= 3 ++//Bit 3:2, reg_sr3_pk_drtbld_range // u2: range of the min2 and min direction distance; default =1 ++//Bit 1, reserved ++//Bit 0, reg_sr3_pk_ti_blend_mode // u1: blend mode of the TI and PK results: default = 0; ++#define SHARP_SR3_PK_CTRL1 (0x3263) ++#define P_SHARP_SR3_PK_CTRL1 (volatile unsigned int *)((0x3263 << 2) + 0xff900000) ++//Bit 31, reserved ++//Bit 30:28, reg_sr3_pk_hp_hvcon_replace8_maxsad //u3: replace HP hvcon by maxsad, default =1 ++//Bit 27, reserved ++//Bit 26:24, reg_sr3_pk_bp_hvcon_replace8_maxsad //u3: replace HP hvcon by maxsad, default =1 ++//Bit 23:16, reg_sr3_pk_hp_hvcon_replace8lv_gain //u8: gain to local variant before calculating the hv gain for peaking, normalized to 32 as "1" default = 32; ++//Bit 15:8, reg_sr3_pk_bp_hvcon_replace8lv_gain //u8: gain to local variant before calculating the hv gain for peaking, normalized to 32 as "1" default = 32; ++//Bit 7, reg_sr3_sad_intlev_mode //u1: interleave detection xerr mode: 0 max; 1:sum default=1 ++//Bit 6, reg_sr3_sad_intlev_mode1 //u1: mode 1 of using diagonal protection: 0: no digonal protection; 1: with diagonal protection default=1 ++//Bit 5:0, reg_sr3_sad_intlev_gain //u6: interleave detection for sad gain applied, normalized to 8 as 1 default=12 ++#define SHARP_DEJ_CTRL (0x3264) ++#define P_SHARP_DEJ_CTRL (volatile unsigned int *)((0x3264 << 2) + 0xff900000) ++//Bit 31:4 reserved ++//Bit 3:2, reg_sr3_dejaggy_sameside_prtct // u2: enable of sr3 dejaggy same side curve protect from filter, [0] for proc, [1] for ctrl path, default=3 ++//Bit 1, reg_sr3_dejaggy_sameside_mode // u1: mode of the sameside flag decision: default =1 ++//Bit 0, reg_sr3_dejaggy_enable // u1: enable of sr3 dejaggy: default =0 ++#define SHARP_DEJ_ALPHA (0x3265) ++#define P_SHARP_DEJ_ALPHA (volatile unsigned int *)((0x3265 << 2) + 0xff900000) ++//Bit 31:28, reg_sr3_dejaggy_ctrlchrm_alpha_1 //u4: alpha for LR video LPF, default = 0 ++//Bit 27:24, reg_sr3_dejaggy_ctrlchrm_alpha_0 //u4: alpha for LR video LPF, default = 15 ++//Bit 23:20, reg_sr3_dejaggy_ctrlluma_alpha_1 //u4: alpha for LR video LPF, default = 0 ++//Bit 19:16, reg_sr3_dejaggy_ctrlluma_alpha_0 //u4: alpha for LR video LPF, default = 15 ++//Bit 15:12, reg_sr3_dejaggy_procchrm_alpha_1 //u4: alpha for LR video LPF, default = 4 ++//Bit 11:8, reg_sr3_dejaggy_procchrm_alpha_0 //u4: alpha for LR video LPF, default = 6 ++//Bit 7:4, reg_sr3_dejaggy_procluma_alpha_1 //u4: alpha for LR video LPF, default = 4 ++//Bit 3:0, reg_sr3_dejaggy_procluma_alpha_0 //u4: alpha for LR video LPF, default = 6 ++#define SHARP_SR3_DRTLPF_EN (0x3266) ++#define P_SHARP_SR3_DRTLPF_EN (volatile unsigned int *)((0x3266 << 2) + 0xff900000) ++//Bit 31:15 reserved ++//Bit 14:8, reg_pk_debug_edge . unsigned , default = 0 ++//Bit 7, reserved ++//Bit 6:4, reg_sr3_drtlpf_theta_en //u1x3 theta (pure vertical and horizontal HF burst protection) enable. 0: not enable, 1:enable protection ++//Bit 3, reserved ++//Bit 2:0 reg_sr3_drtlpf_enable //u1x3 directional lpf on luma U and V channels, default = 7 ++#define SHARP_SR3_DRTLPF_ALPHA_0 (0x3267) ++#define P_SHARP_SR3_DRTLPF_ALPHA_0 (volatile unsigned int *)((0x3267 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:24 reg_sr3_drtlpf_alpha3 //u6: directional lpf alpha coef for min_sad/max_sad comparied, default = 9 ++//Bit 23:22 reserved ++//Bit 21:16 reg_sr3_drtlpf_alpha2 //u6: default =10 ++//Bit 15:14 reserved ++//Bit 13:8 reg_sr3_drtlpf_alpha1 //u6: default = 11 ++//Bit 7:6 reserved ++//Bit 5:0 reg_sr3_drtlpf_alpha0 //u6: default = 12 ++#define SHARP_SR3_DRTLPF_ALPHA_1 (0x3268) ++#define P_SHARP_SR3_DRTLPF_ALPHA_1 (volatile unsigned int *)((0x3268 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:24 reg_sr3_drtlpf_alpha7 //u6: directional lpf alpha coef for min_sad/max_sad comparied, default = 1 ++//Bit 23:22 reserved ++//Bit 21:16 reg_sr3_drtlpf_alpha6 //u6: default = 4 ++//Bit 15:14 reserved ++//Bit 13:8 reg_sr3_drtlpf_alpha5 //u6: default = 7 ++//Bit 7:6 reserved ++//Bit 5:0 reg_sr3_drtlpf_alpha4 //u6: default = 8 ++#define SHARP_SR3_DRTLPF_ALPHA_2 (0x3269) ++#define P_SHARP_SR3_DRTLPF_ALPHA_2 (volatile unsigned int *)((0x3269 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:24 reg_sr3_drtlpf_alpha11 //u6: directional lpf alpha coef for min_sad/max_sad comparied, default = 0 ++//Bit 23:22 reserved ++//Bit 21:16 reg_sr3_drtlpf_alpha10 //u6: default = 0 ++//Bit 15:14 reserved ++//Bit 13:8 reg_sr3_drtlpf_alpha9 //u6: default = 0 ++//Bit 7:6 reserved ++//Bit 5:0 reg_sr3_drtlpf_alpha8 //u6: default = 0 ++#define SHARP_SR3_DRTLPF_ALPHA_OFST (0x326a) ++#define P_SHARP_SR3_DRTLPF_ALPHA_OFST (volatile unsigned int *)((0x326a << 2) + 0xff900000) ++//Bit 31:28 reg_sr3_drtlpf_alpha_ofst7 //s4: directional lpf alpha coef ofset of each directions, default = -8 ++//Bit 27:24 reg_sr3_drtlpf_alpha_ofst6 //s4: default = -8 ++//Bit 23:20 reg_sr3_drtlpf_alpha_ofst5 //s4: default = -8 ++//Bit 19:16 reg_sr3_drtlpf_alpha_ofst4 //s4: default = -8 ++//Bit 15:12 reg_sr3_drtlpf_alpha_ofst3 //s4: default = -8 ++//Bit 11:8 reg_sr3_drtlpf_alpha_ofst2 //s4: default = -8 ++//Bit 7:4 reg_sr3_drtlpf_alpha_ofst1 //s4: default = -8 ++//Bit 3:0 reg_sr3_drtlpf_alpha_ofst0 //s4: default = -8 ++#define SHARP_SR3_DERING_CTRL (0x326b) ++#define P_SHARP_SR3_DERING_CTRL (volatile unsigned int *)((0x326b << 2) + 0xff900000) ++//Bit 31 reserved ++//Bit 30:28 reg_sr3_dering_enable // u3: dering enable bits; default = 1 ++//Bit 27 reserved ++//Bit 26:24 reg_sr3_dering_varlpf_mode // u3: local variant LPF mode: 0 no filter, 1, errosion 3x3; 2: 3x3 lpf; 3 and up: 3x3 errosion + lpf default = 3 ++//Bit 23:20 reg_sr3_dering_maxrange // u4: maximum:range of dering in LR resolution, max to 12; default = 9 ++//Bit 19:18 reserved ++//Bit 17:16 reg_sr3_dering_lcvar_blend_mode // u2: mode for lcvar calculation: 0: HVblend; 1: diagblend; 2: HVblend+V (for hring); 3: HVblend+ DiagBlend default = 2 ++//Bit 15:8 reg_sr3_dering_lcvar_gain // u8: gain to local variant and normalized to 32 as "1" default = 64 ++//Bit 7:0 reg_sr3_dering_lcvar_nearby_maxsad_th // u8: threshold to use nearer side maxsad if that side sad is larger than this threshold, ortherwise, use the max one default = 28 ++#define SHARP_SR3_DERING_LUMA2PKGAIN_0TO3 (0x326c) ++#define P_SHARP_SR3_DERING_LUMA2PKGAIN_0TO3 (volatile unsigned int *)((0x326c << 2) + 0xff900000) ++//Bit 31:24 reg_sr3_dering_luma2pkgain3 // u8: level limit(for th0th1) of curve for dering pkgain based on LPF luma level. default =24 ++//Bit 15:8 reg_sr3_dering_luma2pkgain5 // u8: rate0 (for bpconth1) of curve for dering pkgain based on LPF luma level. default =255 ++#define SHARP_SR3_DERING_LUMA2PKOS_0TO3 (0x326e) ++#define P_SHARP_SR3_DERING_LUMA2PKOS_0TO3 (volatile unsigned int *)((0x326e << 2) + 0xff900000) ++//Bit 31:24 reg_sr3_dering_luma2pkos3 // u8: level limit(for th0th1) of curve for dering pkOS based on LPF luma level. default =24 ++//Bit 15:8 reg_sr3_dering_luma2pkos5 // u8: rate0 (for bpconth1) of curve for dering pkOS based on LPF luma level. default =255 ++#define SHARP_SR3_DERING_GAINVS_MADSAD (0x3270) ++#define P_SHARP_SR3_DERING_GAINVS_MADSAD (volatile unsigned int *)((0x3270 << 2) + 0xff900000) ++//Bit 31:28 reg_sr3_dering_gainvs_maxsad7 //u4: pkgain vs maxsad value, 8 node interpolations, default = 0 ++//Bit 27:24 reg_sr3_dering_gainvs_maxsad6 //u4: default = 0 ++//Bit 23:20 reg_sr3_dering_gainvs_maxsad5 //u4: default = 0 ++//Bit 19:16 reg_sr3_dering_gainvs_maxsad4 //u4: default = 0 ++//Bit 15:12 reg_sr3_dering_gainvs_maxsad3 //u4: default = 0 ++//Bit 11:8 reg_sr3_dering_gainvs_maxsad2 //u4: default = 0 ++//Bit 7:4 reg_sr3_dering_gainvs_maxsad1 //u4: default = 4 ++//Bit 3:0 reg_sr3_dering_gainvs_maxsad0 //u4: default = 8 ++#define SHARP_SR3_DERING_GAINVS_VR2MAX (0x3271) ++#define P_SHARP_SR3_DERING_GAINVS_VR2MAX (volatile unsigned int *)((0x3271 << 2) + 0xff900000) ++//Bit 31:28 reg_sr3_dering_gainvs_vr2max7 //u4: pkgain vs ratio = max(local_var, floor)/maxsad nearby, default = 15 ++//Bit 27:24 reg_sr3_dering_gainvs_vr2max6 //u4: default = 15 ++//Bit 23:20 reg_sr3_dering_gainvs_vr2max5 //u4: default = 15 ++//Bit 19:16 reg_sr3_dering_gainvs_vr2max4 //u4: default = 15 ++//Bit 15:12 reg_sr3_dering_gainvs_vr2max3 //u4: default = 14 ++//Bit 11:8 reg_sr3_dering_gainvs_vr2max2 //u4: default = 12 ++//Bit 7:4 reg_sr3_dering_gainvs_vr2max1 //u4: default = 2 ++//Bit 3:0 reg_sr3_dering_gainvs_vr2max0 //u4: default = 0 ++#define SHARP_SR3_DERING_PARAM0 (0x3272) ++#define P_SHARP_SR3_DERING_PARAM0 (volatile unsigned int *)((0x3272 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:16 reg_sr3_dering_lcvar_floor //u8: local varianet no smaller than this value to calculate dgain max(localvar,x)/maxsad. default = 10 ++//Bit 15:8 reg_sr3_dering_vr2max_gain //u8: gain to max(local_var, floor)/maxsad before feeding to LUT. default = 32 ++//Bit 7:6 reserved ++//Bit 5:0 reg_sr3_dering_vr2max_limt //u6: limit of maxsad to max(local_var, floor)*(max(maxsad, lmit))/maxsad. default = 16 ++#define SHARP_SR3_DRTLPF_THETA (0x3273) ++#define P_SHARP_SR3_DRTLPF_THETA (volatile unsigned int *)((0x3273 << 2) + 0xff900000) ++//Bit 31:0 reg_sr3_drtlpf_theta //u4x8: directional lpf beta coef for min_sad/min2_sad compared to x=0:7 correspond to[1:8]/16; 0 means no drtLPF, 15: 100% alpha dependant drtLPF ++#define SHARP_SATPRT_CTRL (0x3274) ++#define P_SHARP_SATPRT_CTRL (volatile unsigned int *)((0x3274 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:16 reg_satprt_sat_core //u8: 4x will be coring to cor(irgb_max-irgb_min) to calculate the oy_delt, the smaller the more protection to color, the larger only the rich color will be protected; ++//Bit 15:8 reg_satprt_sat_rate //u8: rate to cor(irgb_max-irgb_min) to calculate the oy_delt, the larger the more protection to rich color; norm 16 as 1 ++//Bit 7:4 reserved ++//Bit 3:2 reg_satprt_csc_mode //u2: csc mode of current yuv input: 0:601, 1:709, 2:BT2020 NCL, 3:reserved ++//Bit 1 reg_satprt_is_lmt //u1: flag telling the YUV is limited range data or full range data, 0 full range, 1: limited range ++//Bit 0 reg_satprt_enable //u1: enable of saturation protection for dnlp adjustments ++#define SHARP_SATPRT_DIVM (0x3275) ++#define P_SHARP_SATPRT_DIVM (volatile unsigned int *)((0x3275 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:0 reg_satprt_div_m //u8x3, 1/m, normalized to 128 as 1, default=1 ++#define SHARP_SATPRT_LMT_RGB (0x3276) ++#define P_SHARP_SATPRT_LMT_RGB (volatile unsigned int *)((0x3276 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:0 reg_satprt_lmt_rgb //u10x3, limit of the rgb channel, for limited range RGB, set to 960, otherwise set to 1023 ++#define SHARP_DB_FLT_CTRL (0x3277) ++#define P_SHARP_DB_FLT_CTRL (volatile unsigned int *)((0x3277 << 2) + 0xff900000) ++//Bit 31:27 reserved ++//Bit 26 reg_nrdeband_reset1 ++//Bit 25 reg_nrdeband_reset0 ++//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 0:yuv 1:RGB ++//Bit 23 reg_nrdeband_en11 // unsigned , default = 1 debanding registers of side lines, [0] for luma, same for below ++//Bit 22 reg_nrdeband_en10 // unsigned , default = 1 debanding registers of side lines, [1] for chroma, same for below ++//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y; ++//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m]) ++//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6 ++//Bit 16 reserved ++//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6 ++//Bit 12 reserved ++//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6 ++//Bit 8 reserved ++//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 debanding random hp portion xor, [0] for luma ++//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 debanding random hp portion xor, [1] for chroma ++//Bit 5 reg_nrdeband_en1 // unsigned , default = 1 debanding registers, for luma ++//Bit 4 reg_nrdeband_en0 // unsigned , default = 1 debanding registers, for chroma ++//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7 ++//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7 ++#define SHARP_DB_FLT_YC_THRD (0x3278) ++#define P_SHARP_DB_FLT_YC_THRD (volatile unsigned int *)((0x3278 << 2) + 0xff900000) ++//Bit 31:28 reg_nrdeband_luma_th3 // unsigned , default = 9 threshold to |Y-Ylpf|, if < th[0] use lpf ++//Bit 27:24 reg_nrdeband_luma_th2 // unsigned , default = 7 elseif req_th, then send the request ++//bit[18:16] R-RW 0~7 0 reg_arsize : axi arsize ++//bit[14:12] R-RW 0~7 0 reg_arprot : axi arprot ++//bit[11:8] R-RW 0~15 0 reg_aruser : axi aruser ++//bit[5:4] R-RW 0~3 0 reg_arid : axi arid ++//bit[3:0] R-RW 0~2 0 reg_lens : default request lens, each burst has "reg_lens+1" data ++#define DOLBY_TV_AXI2DMA_CTRL1 (0x33fb) ++#define P_DOLBY_TV_AXI2DMA_CTRL1 (volatile unsigned int *)((0x33fb << 2) + 0xff900000) ++//bit[31] R-RW 0~1 0 axi_addr_mode : 1 "canvas mode", 0 "normal mode" ++//bit[27:16] R-RW 0~4095 0 dma_size0 : total data number in dma0 ++//bit[11:0] R-RW 0~4095 0 dma_size1 : total data number in dma1 ++#define DOLBY_TV_AXI2DMA_CTRL2 (0x33fc) ++#define P_DOLBY_TV_AXI2DMA_CTRL2 (volatile unsigned int *)((0x33fc << 2) + 0xff900000) ++//bit[31:0] R-RW 0~4294967295 0 axi_start_addr : axi start address ++#define DOLBY_TV_AXI2DMA_CTRL3 (0x33fd) ++#define P_DOLBY_TV_AXI2DMA_CTRL3 (volatile unsigned int *)((0x33fd << 2) + 0xff900000) ++//bit[11:0] R-RW 0~4095 0 hold_line : after hold_line the axi slave start requesting ++#define DOLBY_TV_STATUS0 (0x33fe) ++#define P_DOLBY_TV_STATUS0 (volatile unsigned int *)((0x33fe << 2) + 0xff900000) ++#define DOLBY_TV_STATUS1 (0x33ff) ++#define P_DOLBY_TV_STATUS1 (volatile unsigned int *)((0x33ff << 2) + 0xff900000) ++#define DOLBY_TV_ADAPTIVE_SCALE_REGADDR (0x33e0) ++#define P_DOLBY_TV_ADAPTIVE_SCALE_REGADDR (volatile unsigned int *)((0x33e0 << 2) + 0xff900000) ++#define DOLBY_TV_ADAPTIVE_SCALE_REGDATA (0x33e1) ++#define P_DOLBY_TV_ADAPTIVE_SCALE_REGDATA (volatile unsigned int *)((0x33e1 << 2) + 0xff900000) ++#define DOLBY_TV_ADAPTIVE_SCALE_LUTADDR (0x33e2) ++#define P_DOLBY_TV_ADAPTIVE_SCALE_LUTADDR (volatile unsigned int *)((0x33e2 << 2) + 0xff900000) ++#define DOLBY_TV_ADAPTIVE_SCALE_LUTDATA (0x33e3) ++#define P_DOLBY_TV_ADAPTIVE_SCALE_LUTDATA (volatile unsigned int *)((0x33e3 << 2) + 0xff900000) ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: dolby_regs.h ++// ++// ----------------------------------------------- ++// CBUS_BASE: DOLBY1A_VCBUS_BASE = 0x34 ++// ----------------------------------------------- ++// ++// Reading file: dolby1a_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++#define DOLBY_CORE2A_REG_START (0x3400) ++#define P_DOLBY_CORE2A_REG_START (volatile unsigned int *)((0x3400 << 2) + 0xff900000) ++#define DOLBY_CORE2A_CLKGATE_CTRL (0x3432) ++#define P_DOLBY_CORE2A_CLKGATE_CTRL (volatile unsigned int *)((0x3432 << 2) + 0xff900000) ++#define DOLBY_CORE2A_SWAP_CTRL0 (0x3433) ++#define P_DOLBY_CORE2A_SWAP_CTRL0 (volatile unsigned int *)((0x3433 << 2) + 0xff900000) ++#define DOLBY_CORE2A_SWAP_CTRL1 (0x3434) ++#define P_DOLBY_CORE2A_SWAP_CTRL1 (volatile unsigned int *)((0x3434 << 2) + 0xff900000) ++#define DOLBY_CORE2A_SWAP_CTRL2 (0x3435) ++#define P_DOLBY_CORE2A_SWAP_CTRL2 (volatile unsigned int *)((0x3435 << 2) + 0xff900000) ++#define DOLBY_CORE2A_SWAP_CTRL3 (0x3436) ++#define P_DOLBY_CORE2A_SWAP_CTRL3 (volatile unsigned int *)((0x3436 << 2) + 0xff900000) ++#define DOLBY_CORE2A_SWAP_CTRL4 (0x3437) ++#define P_DOLBY_CORE2A_SWAP_CTRL4 (volatile unsigned int *)((0x3437 << 2) + 0xff900000) ++#define DOLBY_CORE2A_SWAP_CTRL5 (0x3438) ++#define P_DOLBY_CORE2A_SWAP_CTRL5 (volatile unsigned int *)((0x3438 << 2) + 0xff900000) ++#define DOLBY_CORE2A_DMA_CTRL (0x3439) ++#define P_DOLBY_CORE2A_DMA_CTRL (volatile unsigned int *)((0x3439 << 2) + 0xff900000) ++#define DOLBY_CORE2A_DMA_STATUS (0x343a) ++#define P_DOLBY_CORE2A_DMA_STATUS (volatile unsigned int *)((0x343a << 2) + 0xff900000) ++#define DOLBY_CORE2A_STATUS0 (0x343b) ++#define P_DOLBY_CORE2A_STATUS0 (volatile unsigned int *)((0x343b << 2) + 0xff900000) ++#define DOLBY_CORE2A_STATUS1 (0x343c) ++#define P_DOLBY_CORE2A_STATUS1 (volatile unsigned int *)((0x343c << 2) + 0xff900000) ++#define DOLBY_CORE2A_STATUS2 (0x343d) ++#define P_DOLBY_CORE2A_STATUS2 (volatile unsigned int *)((0x343d << 2) + 0xff900000) ++#define DOLBY_CORE2A_STATUS3 (0x343e) ++#define P_DOLBY_CORE2A_STATUS3 (volatile unsigned int *)((0x343e << 2) + 0xff900000) ++#define DOLBY_CORE2A_DMA_PORT (0x343f) ++#define P_DOLBY_CORE2A_DMA_PORT (volatile unsigned int *)((0x343f << 2) + 0xff900000) ++#define DOLBY_CORE2A_AXI2DMA_CTRL0 (0x3440) ++#define P_DOLBY_CORE2A_AXI2DMA_CTRL0 (volatile unsigned int *)((0x3440 << 2) + 0xff900000) ++#define DOLBY_CORE2A_AXI2DMA_CTRL1 (0x3441) ++#define P_DOLBY_CORE2A_AXI2DMA_CTRL1 (volatile unsigned int *)((0x3441 << 2) + 0xff900000) ++#define DOLBY_CORE2A_AXI2DMA_CTRL2 (0x3442) ++#define P_DOLBY_CORE2A_AXI2DMA_CTRL2 (volatile unsigned int *)((0x3442 << 2) + 0xff900000) ++#define DOLBY_CORE2A_AXI2DMA_CTRL3 (0x3443) ++#define P_DOLBY_CORE2A_AXI2DMA_CTRL3 (volatile unsigned int *)((0x3443 << 2) + 0xff900000) ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: dolby1a_regs.h ++// ++// ----------------------------------------------- ++// CBUS_BASE: DOLBY1B_VCBUS_BASE = 0x35 ++// ----------------------------------------------- ++//`include "dolby1b_regs.h" ++// ----------------------------------------------- ++// CBUS_BASE: DOLBY2_VCBUS_BASE = 0x36 ++// ----------------------------------------------- ++// ++// Reading file: dolby2_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++#define DOLBY_CORE3_REG_START (0x3600) ++#define P_DOLBY_CORE3_REG_START (volatile unsigned int *)((0x3600 << 2) + 0xff900000) ++#define DOLBY_CORE3_CLKGATE_CTRL (0x36f0) ++#define P_DOLBY_CORE3_CLKGATE_CTRL (volatile unsigned int *)((0x36f0 << 2) + 0xff900000) ++#define DOLBY_CORE3_SWAP_CTRL0 (0x36f1) ++#define P_DOLBY_CORE3_SWAP_CTRL0 (volatile unsigned int *)((0x36f1 << 2) + 0xff900000) ++#define DOLBY_CORE3_SWAP_CTRL1 (0x36f2) ++#define P_DOLBY_CORE3_SWAP_CTRL1 (volatile unsigned int *)((0x36f2 << 2) + 0xff900000) ++#define DOLBY_CORE3_SWAP_CTRL2 (0x36f3) ++#define P_DOLBY_CORE3_SWAP_CTRL2 (volatile unsigned int *)((0x36f3 << 2) + 0xff900000) ++#define DOLBY_CORE3_SWAP_CTRL3 (0x36f4) ++#define P_DOLBY_CORE3_SWAP_CTRL3 (volatile unsigned int *)((0x36f4 << 2) + 0xff900000) ++#define DOLBY_CORE3_SWAP_CTRL4 (0x36f5) ++#define P_DOLBY_CORE3_SWAP_CTRL4 (volatile unsigned int *)((0x36f5 << 2) + 0xff900000) ++#define DOLBY_CORE3_SWAP_CTRL5 (0x36f6) ++#define P_DOLBY_CORE3_SWAP_CTRL5 (volatile unsigned int *)((0x36f6 << 2) + 0xff900000) ++#define DOLBY_CORE3_SWAP_CTRL6 (0x36f7) ++#define P_DOLBY_CORE3_SWAP_CTRL6 (volatile unsigned int *)((0x36f7 << 2) + 0xff900000) ++#define DOLBY_CORE3_SWAP_CTRL7 (0x36f8) ++#define P_DOLBY_CORE3_SWAP_CTRL7 (volatile unsigned int *)((0x36f8 << 2) + 0xff900000) ++#define DOLBY_CORE3_SWAP_CTRL8 (0x36f9) ++#define P_DOLBY_CORE3_SWAP_CTRL8 (volatile unsigned int *)((0x36f9 << 2) + 0xff900000) ++#define DOLBY_CORE3_SWAP_CTRL9 (0x36fa) ++#define P_DOLBY_CORE3_SWAP_CTRL9 (volatile unsigned int *)((0x36fa << 2) + 0xff900000) ++#define DOLBY_CORE3_STATUS0 (0x36fb) ++#define P_DOLBY_CORE3_STATUS0 (volatile unsigned int *)((0x36fb << 2) + 0xff900000) ++#define DOLBY_CORE3_STATUS1 (0x36fc) ++#define P_DOLBY_CORE3_STATUS1 (volatile unsigned int *)((0x36fc << 2) + 0xff900000) ++#define DOLBY_CORE3_STATUS2 (0x36fd) ++#define P_DOLBY_CORE3_STATUS2 (volatile unsigned int *)((0x36fd << 2) + 0xff900000) ++#define DOLBY_CORE3_STATUS3 (0x36fe) ++#define P_DOLBY_CORE3_STATUS3 (volatile unsigned int *)((0x36fe << 2) + 0xff900000) ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: dolby2_regs.h ++// ++//`define MADC_VCBUS_BASE 8'h37 ++// ++// Reading file: vpu_madc_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++// ----------------------------------------------- ++// CBUS_BASE: MADC_VCBUS_BASE = 0x37 ++// ----------------------------------------------- ++// 0x00-0x1f ++// ++// Reading file: nr4_nm_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++#define NR4_MCNR_SAD_GAIN (0x3700) ++#define P_NR4_MCNR_SAD_GAIN (volatile unsigned int *)((0x3700 << 2) + 0xff900000) ++//Bit 31:25 reserved ++//Bit 24 reg_nr4_bld12vs3_usemaxsad // unsigned , default = 0 use minsad/maxsad instead of minsad/avgsad to decision if it was texture or flat region, 1: use minsad/maxsad ++//Bit 23:16 reg_nr4_bld12vs3_rate_gain // unsigned , default = 64 gain to minsad/maxsad or minsad/avgsad before LUT, 64 normalized as "1" ++//Bit 15: 8 reg_nr4_bld1vs2_rate_gain // unsigned , default = 32 gain to minsad/maxsad or minsad/avgsad before the LUT, 64 normalized as"1" ++//Bit 7: 0 reg_nr4_coefblt_gain // unsigned , default = 64 gain to final coefblt, normalized 64 as "1" ++#define NR4_MCNR_LPF_CTRL (0x3701) ++#define P_NR4_MCNR_LPF_CTRL (volatile unsigned int *)((0x3701 << 2) + 0xff900000) ++//Bit 31 reserved ++//Bit 30:22 reg_nr4_preflt_alpofst // signed , default = 0 pre filter alpha ofst ++//Bit 21:16 reg_nr4_preflt_alpgain // unsigned , default = 16 pre filter alpha gain ++//Bit 15:14 reg_nr4_preflt_alpsel // unsigned , default = 3 pre filter alpha selection for adaptive blending, 0: mv pointed sad, 1: weighted mv pointed sad, 2or3: coefblt ++//Bit 13: 8 reg_nr4_avgsad_gain // unsigned , default = 8 gain for avg sad before luts ++//Bit 7 reserved ++//Bit 6 reg_nr4_maxsad_mod // unsigned , default = 1 max sad select mode, 0: mx2_sad, 1: max sad ++//Bit 5 reg_nr4_minsad_mod // unsigned , default = 1 min sad select mode, 0: sad with min err, 1: min sad ++//Bit 4 reg_nr4_minmaxsad_lpf // unsigned , default = 1 mode of lpf for minmaxsad, 0: no LPF, 1: [1 2 1]/4 ++//Bit 3 reg_nr4_avgsad_lpf // unsigned , default = 1 mode of lpf for avgsad, 0: no LPF, 1: [1 2 1]/4 ++//Bit 2 reg_nr4_minavgsad_ratio_lpf // unsigned , default = 1 mode of lpf for minsad/avgsad and zmvsad/avgsad, 0: no LPF, 1: [1 2 1]/4 ++//Bit 1 reg_nr4_bldvs_lut_lpf // unsigned , default = 1 mode of lpf for bld12vs3 and bld1vs2 LUT results, 0: no LPF, 1: [1 2 1]/4 ++//Bit 0 reg_nr4_final_coef_lpf // unsigned , default = 1 mode of lpf for final coef_blt_blend123, 0: no LPF, 1: [1 2 1]/4 ++#define NR4_MCNR_BLD_VS3LUT0 (0x3702) ++#define P_NR4_MCNR_BLD_VS3LUT0 (volatile unsigned int *)((0x3702 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:24 reg_nr4_bld12vs3_lut0 // unsigned , default = 0 ++//Bit 23:22 reserved ++//Bit 21:16 reg_nr4_bld12vs3_lut1 // unsigned , default = 8 ++//Bit 15:14 reserved ++//Bit 13: 8 reg_nr4_bld12vs3_lut2 // unsigned , default = 10 ++//Bit 7: 6 reserved ++//Bit 5: 0 reg_nr4_bld12vs3_lut3 // unsigned , default = 11 ++#define NR4_MCNR_BLD_VS3LUT1 (0x3703) ++#define P_NR4_MCNR_BLD_VS3LUT1 (volatile unsigned int *)((0x3703 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:24 reg_nr4_bld12vs3_lut4 // unsigned , default = 12 ++//Bit 23:22 reserved ++//Bit 21:16 reg_nr4_bld12vs3_lut5 // unsigned , default = 14 ++//Bit 15:14 reserved ++//Bit 13: 8 reg_nr4_bld12vs3_lut6 // unsigned , default = 16 ++//Bit 7: 6 reserved ++//Bit 5: 0 reg_nr4_bld12vs3_lut7 // unsigned , default = 24 ++#define NR4_MCNR_BLD_VS3LUT2 (0x3704) ++#define P_NR4_MCNR_BLD_VS3LUT2 (volatile unsigned int *)((0x3704 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:24 reg_nr4_bld12vs3_lut8 // unsigned , default = 50 ++//Bit 23:22 reserved ++//Bit 21:16 reg_nr4_bld12vs3_lut9 // unsigned , default = 58 ++//Bit 15:14 reserved ++//Bit 13: 8 reg_nr4_bld12vs3_lut10 // unsigned , default = 63 ++//Bit 7: 6 reserved ++//Bit 5: 0 reg_nr4_bld12vs3_lut11 // unsigned , default = 63 ++#define NR4_MCNR_BLD_VS2LUT0 (0x3705) ++#define P_NR4_MCNR_BLD_VS2LUT0 (volatile unsigned int *)((0x3705 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:24 reg_nr4_bld1vs2_lut0 // unsigned , default = 63 ++//Bit 23:22 reserved ++//Bit 21:16 reg_nr4_bld1vs2_lut1 // unsigned , default = 32 ++//Bit 15:14 reserved ++//Bit 13: 8 reg_nr4_bld1vs2_lut2 // unsigned , default = 16 ++//Bit 7: 6 reserved ++//Bit 5: 0 reg_nr4_bld1vs2_lut3 // unsigned , default = 8 ++#define NR4_MCNR_BLD_VS2LUT1 (0x3706) ++#define P_NR4_MCNR_BLD_VS2LUT1 (volatile unsigned int *)((0x3706 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:24 reg_nr4_bld1vs2_lut4 // unsigned , default = 4 ++//Bit 23:22 reserved ++//Bit 21:16 reg_nr4_bld1vs2_lut5 // unsigned , default = 2 ++//Bit 15:14 reserved ++//Bit 13: 8 reg_nr4_bld1vs2_lut6 // unsigned , default = 1 ++//Bit 7: 6 reserved ++//Bit 5: 0 reg_nr4_bld1vs2_lut7 // unsigned , default = 0 ++#define NR4_COEFBLT_LUT10 (0x3707) ++#define P_NR4_COEFBLT_LUT10 (volatile unsigned int *)((0x3707 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_coefblt_lut10 // signed , default = -128 ++//Bit 23:16 reg_nr4_coefblt_lut11 // signed , default = -128 ++//Bit 15: 8 reg_nr4_coefblt_lut12 // signed , default = -126 ++//Bit 7: 0 reg_nr4_coefblt_lut13 // signed , default = -124 ++#define NR4_COEFBLT_LUT11 (0x3708) ++#define P_NR4_COEFBLT_LUT11 (volatile unsigned int *)((0x3708 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_coefblt_lut14 // signed , default = -120 ++//Bit 23:16 reg_nr4_coefblt_lut15 // signed , default = -110 ++//Bit 15: 8 reg_nr4_coefblt_lut16 // signed , default = -100 ++//Bit 7: 0 reg_nr4_coefblt_lut17 // signed , default = -90 ++#define NR4_COEFBLT_LUT12 (0x3709) ++#define P_NR4_COEFBLT_LUT12 (volatile unsigned int *)((0x3709 << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_coefblt_lut18 // signed , default = -56 ++//Bit 23:16 reg_nr4_coefblt_lut19 // signed , default = -32 ++//Bit 15: 8 reg_nr4_coefblt_lut110 // signed , default = -64 ++//Bit 7: 0 reg_nr4_coefblt_lut111 // signed , default = -128 ++#define NR4_COEFBLT_LUT20 (0x370a) ++#define P_NR4_COEFBLT_LUT20 (volatile unsigned int *)((0x370a << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_coefblt_lut20 // signed , default = -128 ++//Bit 23:16 reg_nr4_coefblt_lut21 // signed , default = -120 ++//Bit 15: 8 reg_nr4_coefblt_lut22 // signed , default = -112 ++//Bit 7: 0 reg_nr4_coefblt_lut23 // signed , default = -104 ++#define NR4_COEFBLT_LUT21 (0x370b) ++#define P_NR4_COEFBLT_LUT21 (volatile unsigned int *)((0x370b << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_coefblt_lut24 // signed , default = -96 ++//Bit 23:16 reg_nr4_coefblt_lut25 // signed , default = -88 ++//Bit 15: 8 reg_nr4_coefblt_lut26 // signed , default = -76 ++//Bit 7: 0 reg_nr4_coefblt_lut27 // signed , default = -64 ++#define NR4_COEFBLT_LUT22 (0x370c) ++#define P_NR4_COEFBLT_LUT22 (volatile unsigned int *)((0x370c << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_coefblt_lut28 // signed , default = -48 ++//Bit 23:16 reg_nr4_coefblt_lut29 // signed , default = -32 ++//Bit 15: 8 reg_nr4_coefblt_lut210 // signed , default = -64 ++//Bit 7: 0 reg_nr4_coefblt_lut211 // signed , default = -108 ++#define NR4_COEFBLT_LUT30 (0x370d) ++#define P_NR4_COEFBLT_LUT30 (volatile unsigned int *)((0x370d << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_coefblt_lut30 // signed , default = 8 ++//Bit 23:16 reg_nr4_coefblt_lut31 // signed , default = 16 ++//Bit 15: 8 reg_nr4_coefblt_lut32 // signed , default = 24 ++//Bit 7: 0 reg_nr4_coefblt_lut33 // signed , default = 30 ++#define NR4_COEFBLT_LUT31 (0x370e) ++#define P_NR4_COEFBLT_LUT31 (volatile unsigned int *)((0x370e << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_coefblt_lut34 // signed , default = 36 ++//Bit 23:16 reg_nr4_coefblt_lut35 // signed , default = 48 ++//Bit 15: 8 reg_nr4_coefblt_lut36 // signed , default = 70 ++//Bit 7: 0 reg_nr4_coefblt_lut37 // signed , default = 96 ++#define NR4_COEFBLT_LUT32 (0x370f) ++#define P_NR4_COEFBLT_LUT32 (volatile unsigned int *)((0x370f << 2) + 0xff900000) ++//Bit 31:24 reg_nr4_coefblt_lut38 // signed , default = 120 ++//Bit 23:16 reg_nr4_coefblt_lut39 // signed , default = 64 ++//Bit 15: 8 reg_nr4_coefblt_lut310 // signed , default = 16 ++//Bit 7: 0 reg_nr4_coefblt_lut311 // signed , default = -8 ++#define NR4_COEFBLT_CONV (0x3710) ++#define P_NR4_COEFBLT_CONV (volatile unsigned int *)((0x3710 << 2) + 0xff900000) ++//Bit 31:24 reserved ++//Bit 23:16 reg_nr4_coefblt_convmin // unsigned , default = 0 minimum of coef. bilateral conversion ++//Bit 15: 8 reg_nr4_coefblt_convmax // unsigned , default = 255 maximum of coef. bilateral conversion ++//Bit 7: 0 reg_nr4_coefblt_convmid // unsigned , default = 128 value at midpoint of coef. bilateral conversion ++#define NR4_DBGWIN_YX0 (0x3711) ++#define P_NR4_DBGWIN_YX0 (volatile unsigned int *)((0x3711 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:16 reg_nr4_dgbwin_yx0 // unsigned , default = 100 ystart for debug window ++//Bit 15:14 reserved ++//Bit 13: 0 reg_nr4_dgbwin_yx1 // unsigned , default = 160 yend for debug window ++#define NR4_DBGWIN_YX1 (0x3712) ++#define P_NR4_DBGWIN_YX1 (volatile unsigned int *)((0x3712 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:16 reg_nr4_dgbwin_yx2 // unsigned , default = 200 xstart for debug window ++//Bit 15:14 reserved ++//Bit 13: 0 reg_nr4_dgbwin_yx3 // unsigned , default = 300 xend for debug window ++#define NR4_NM_X_CFG (0x3713) ++#define P_NR4_NM_X_CFG (volatile unsigned int *)((0x3713 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:16 reg_nr4_nm_xst // unsigned , default = 8 start for noise meter statistic, dft = 8 ++//Bit 15:14 reserved ++//Bit 13: 0 reg_nr4_nm_xed // unsigned , default = 711 end for noise meter statistic, dft = HSIZE-8-1; ++#define NR4_NM_Y_CFG (0x3714) ++#define P_NR4_NM_Y_CFG (volatile unsigned int *)((0x3714 << 2) + 0xff900000) ++//Bit 31:30 reserved ++//Bit 29:16 reg_nr4_nm_yst // unsigned , default = 8 start for noise meter statistic, dft = 8; ++//Bit 15:14 reserved ++//Bit 13: 0 reg_nr4_nm_yed // unsigned , default = 231 end for noise meter statistic, dft = VSIZE-8-1; ++#define NR4_NM_SAD_THD (0x3715) ++#define P_NR4_NM_SAD_THD (volatile unsigned int *)((0x3715 << 2) + 0xff900000) ++//Bit 31: 8 reserved ++//Bit 7: 0 reg_nr4_nm_sad_thd // unsigned , default = 255 threshold for (flat region) sad count, dft = 4 ++#define NR4_MCNR_BANDSPLIT_PRAM (0x3716) ++#define P_NR4_MCNR_BANDSPLIT_PRAM (volatile unsigned int *)((0x3716 << 2) + 0xff900000) ++//Bit 31: 5 reserved ++//Bit 4 reg_nr4_mc_use_bandsplit // unsigned , default = 1 separate lp and us for mc IIR filter, 0: no BS used; 1: use BS ++//Bit 3 reg_nr4_mc_apply_on_lp // unsigned , default = 1 use mcnr only on lowpass portion; ++//Bit 2 reg_nr4_mc_apply_on_us // unsigned , default = 1 use mcnr only on lp complimentary portion; ++//Bit 1: 0 reg_nr4_mc_zmvbs_use_adplpf // unsigned , default = 1 use adapptive LPF for the zmv pointing data for MCNR, for abs(mvx)reg_nrdeband_bandrand[m]), noise[m]) ++//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6 ++//Bit 16 reserved ++//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6 ++//Bit 12 reserved ++//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6 ++//Bit 8 reserved ++//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 debanding random hp portion xor, [0] for luma ++//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 debanding random hp portion xor, [1] for chroma ++//Bit 5 reg_nrdeband_en1 // unsigned , default = 1 debanding registers, for luma ++//Bit 4 reg_nrdeband_en0 // unsigned , default = 1 debanding registers, for chroma ++//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7 ++//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7 ++#define NR_DB_FLT_YC_THRD (0x3739) ++#define P_NR_DB_FLT_YC_THRD (volatile unsigned int *)((0x3739 << 2) + 0xff900000) ++//Bit 31:28 reg_nrdeband_luma_th3 // unsigned , default = 9 threshold to |Y-Ylpf|, if < th[0] use lpf ++//Bit 27:24 reg_nrdeband_luma_th2 // unsigned , default = 7 elseif th3, use filter3 ++//Bit 23:16, color antiflick filter2 n3 ++//Bit 15:8, color antiflick filter2 n2 ++//Bit 7:0, color antiflick filter2 n1 ++#define GE2D_ANTIFLICK_COLOR_FILT2 (0x00dc) ++#define P_GE2D_ANTIFLICK_COLOR_FILT2 (volatile unsigned int *)((0x00dc << 2) + 0xff940000) ++//Bit 23:16, color antiflick filter3 n3 ++//Bit 15:8, color antiflick filter3 n2 ++//Bit 7:0, color antiflick filter3 n1 ++#define GE2D_ANTIFLICK_COLOR_FILT3 (0x00dd) ++#define P_GE2D_ANTIFLICK_COLOR_FILT3 (volatile unsigned int *)((0x00dd << 2) + 0xff940000) ++//Bit 31:24, Alpha threhold1, when 0th3, use filter3 ++//Bit 23:16, Alpha antiflick filter2 n3 ++//Bit 15:8, Alpha antiflick filter2 n2 ++//Bit 7:0, Alpha antiflick filter2 n1 ++#define GE2D_ANTIFLICK_ALPHA_FILT2 (0x00e0) ++#define P_GE2D_ANTIFLICK_ALPHA_FILT2 (volatile unsigned int *)((0x00e0 << 2) + 0xff940000) ++//Bit 23:16, Alpha antiflick filter3 n3 ++//Bit 15:8, Alpha antiflick filter3 n2 ++//Bit 7:0, Alpha antiflick filter3 n1 ++#define GE2D_ANTIFLICK_ALPHA_FILT3 (0x00e1) ++#define P_GE2D_ANTIFLICK_ALPHA_FILT3 (volatile unsigned int *)((0x00e1 << 2) + 0xff940000) ++//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset) ++//Bit 30:22 din_offset (signed data) ++//Bit 21:14 map_coef (unsigned data) ++//Bit 13:10 map_sr (unsigned data) ++//Bit 9:1 dout_offset (signed data) ++//Bit 0 enable ++#define GE2D_SRC1_RANGE_MAP_Y_CTRL (0x00e3) ++#define P_GE2D_SRC1_RANGE_MAP_Y_CTRL (volatile unsigned int *)((0x00e3 << 2) + 0xff940000) ++//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset) ++//Bit 30:22 din_offset (signed data) ++//Bit 21:14 map_coef (unsigned data) ++//Bit 13:10 map_sr (unsigned data) ++//Bit 9:1 dout_offset (signed data) ++//Bit 0 enable ++#define GE2D_SRC1_RANGE_MAP_CB_CTRL (0x00e4) ++#define P_GE2D_SRC1_RANGE_MAP_CB_CTRL (volatile unsigned int *)((0x00e4 << 2) + 0xff940000) ++//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset) ++//Bit 30:22 din_offset (signed data) ++//Bit 21:14 map_coef (unsigned data) ++//Bit 13:10 map_sr (unsigned data) ++//Bit 9:1 dout_offset (signed data) ++//Bit 0 enable ++#define GE2D_SRC1_RANGE_MAP_CR_CTRL (0x00e5) ++#define P_GE2D_SRC1_RANGE_MAP_CR_CTRL (volatile unsigned int *)((0x00e5 << 2) + 0xff940000) ++//Bit 21:16 src1 prearbitor burst number ++//Bit 13:8 src2 prearbitor burst number ++//Bit 5:0 dst prearbitor burst number ++#define GE2D_ARB_BURST_NUM (0x00e6) ++#define P_GE2D_ARB_BURST_NUM (volatile unsigned int *)((0x00e6 << 2) + 0xff940000) ++//each 6bit ID, high 4bit are thread ID, low 2bits are the token ++//Bit 21:16 src1 ID ++//Bit 13:8 src2 ID ++//Bit 5:0 dst ID ++#define GE2D_TID_TOKEN (0x00e7) ++#define P_GE2D_TID_TOKEN (volatile unsigned int *)((0x00e7 << 2) + 0xff940000) ++//Bit 31:28 dst2_bytemask_val. 1-bit mask for each byte (8-bit). Applicable only if both dst_bitmask_en=1 and dst_bytemask_only=1. ++//Bit 27:26, dst2 picture struct, 00: frame, 10:top, 11: bottom ++//Bit 25:24, dst2 8bit mode component selection, ++// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha ++//Bit 22:19 dst2 color_map ++// dst2_format=0 : output 8-bit; ++// dst2_format=1, dst2_color_map=1: output 16-bit YCbCr 655; ++// dst2_format=1, dst2_color_map=2: output 16-bit YCbCr 844; ++// dst2_format=1, dst2_color_map=3: output 16-bit YCbCrA 6442; ++// dst2_format=1, dst2_color_map=4: output 16-bit YCbCrA 4444; ++// dst2_format=1, dst2_color_map=5: output 16-bit YCbCr 565; ++// dst2_format=1, dst2_color_map=6: output 16-bit AYCbCr 4444; ++// dst2_format=1, dst2_color_map=7: output 16-bit AYCbCr 1555; ++// dst2_format=1, dst2_color_map=8: output 16-bit YCbCrA 4642; ++// dst2_format=1, dst2_color_map=9: output 16-bit CbCr 88; ++// dst2_format=1, dst2_color_map=10:output 16-bit CrCb 88; ++// dst2_format=2, dst2_color_map=0: output 24-bit YCbCr 888; ++// dst2_format=2, dst2_color_map=1: output 24-bit YCbCrA 5658; ++// dst2_format=2, dst2_color_map=2: output 24-bit AYCbCr 8565; ++// dst2_format=2, dst2_color_map=3: output 24-bit YCbCrA 6666; ++// dst2_format=2, dst2_color_map=4: output 24-bit AYCbCr 6666; ++// dst2_format=2, dst2_color_map=5: output 24-bit CrCbY 888; ++// dst2_format=3, dst2_color_map=0: output 32-bit YCbCrA 8888; ++// dst2_format=3, dst2_color_map=1: output 32-bit AYCbCr 8888; ++// dst2_format=3, dst2_color_map=2: output 32-bit ACrCbY 8888; ++// dst2_format=3, dst2_color_map=3: output 32-bit CrCbYA 8888. ++//Bit 17:16 dst2_format, 00: 8bit, 01:16bit, 10:24bit, 11: 32bit ++//Bit 15 reserved ++//Bit 14 dst2_color_round_mode, 0: truncate, 1: + 0.5 rounding ++//Bit 13:12, dst2_x_discard_mode. 00: no discard; 10=discard even x; 11=discard odd x. Note: x is post reverse/rotation. ++//Bit 11:10, dst2_y_discard_mode. 00: no discard; 10=discard even y; 11=discard odd y. Note: y is post reverse/rotation. ++//Bit 9 reserved ++//Bit 8, dst2_enable. 0: disable dst2 (default); 1=enable dst2. ++//Bit 7: 6 reserved ++//Bit 5: 4, dst1_x_discard_mode. 00: no discard; 10=discard even x; 11=discard odd x. Note: x is post reverse/rotation. ++//Bit 3: 2, dst1_y_discard_mode. 00: no discard; 10=discard even y; 11=discard odd y. Note: y is post reverse/rotation. ++//Bit 1 reserved ++//Bit 0, dst1_enable. 0: disable dst1; 1=enable dst1 (default). ++#define GE2D_GEN_CTRL3 (0x00e8) ++#define P_GE2D_GEN_CTRL3 (volatile unsigned int *)((0x00e8 << 2) + 0xff940000) ++//Read only ++// Bit 13:0 ge2d_dst2_status, for debug only ++#define GE2D_STATUS2 (0x00e9) ++#define P_GE2D_STATUS2 (volatile unsigned int *)((0x00e9 << 2) + 0xff940000) ++//Bit 27:26 src1 Y fifo size control, 00: 512, 01: 256, 10: 128 11: 96 ++//Bit 25:24 src2 fifo size control, 00: 512, 01: 256, 10: 128 11: 96 ++//Bit 23:22 dst1 fifo size control, 00: 512, 01: 256, 10: 128 11: 64 ++//Bit 21:20 dst2 fifo size control, 00: 512, 01: 256, 10: 128 11: 64 ++//Bit 19:18, dst1 fifo burst control, 00: 24x64, 01: 32x64, 10: 48x64, 11:64x64 ++//Bit 17:16, dst2 fifo burst control, 00: 24x64, 01: 32x64, 10: 48x64, 11:64x64 ++//Bit 15:1, top_wrap_ctrl ++//bit 0, if true, disable bug fix about the dp_out_done/scale_out_done(test1823) hang issue when scaling down ratio is high. ++#define GE2D_GEN_CTRL4 (0x00ea) ++#define P_GE2D_GEN_CTRL4 (volatile unsigned int *)((0x00ea << 2) + 0xff940000) ++#define GE2D_GCLK_CTRL0 (0x00ef) ++#define P_GE2D_GCLK_CTRL0 (volatile unsigned int *)((0x00ef << 2) + 0xff940000) ++#define GE2D_GCLK_CTRL1 (0x00f0) ++#define P_GE2D_GCLK_CTRL1 (volatile unsigned int *)((0x00f0 << 2) + 0xff940000) ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: ./ge2d_regs.h ++// ++ ++// canvas.h ++// --------------------------- ++#define DC_CAV_LUT_DATAL (0x0012 << 2) ++#define P_DC_CAV_LUT_DATAL (volatile unsigned int *)((0x0012 << 2) + 0xff638000) ++#define DC_CAV_LUT_DATAH (0x0013 << 2) ++#define P_DC_CAV_LUT_DATAH (volatile unsigned int *)((0x0013 << 2) + 0xff638000) ++#define DC_CAV_LUT_ADDR (0x0014 << 2) ++#define P_DC_CAV_LUT_ADDR (volatile unsigned int *)((0x0014 << 2) + 0xff638000) ++#define DC_CAV_LUT_RDATAL (0x0015 << 2) ++#define P_DC_CAV_LUT_RDATAL (volatile unsigned int *)((0x0015 << 2) + 0xff638000) ++#define DC_CAV_LUT_RDATAH (0x0016 << 2) ++#define P_DC_CAV_LUT_RDATAH (volatile unsigned int *)((0x0016 << 2) + 0xff638000) ++ ++ ++#define VPU_RDARB_MODE_L1C1 (0x2790) ++#define VPU_RDARB_MODE_L1C2 (0x2799) ++#define VPU_RDARB_MODE_L2C1 (0x279d) ++#define VPU_WRARB_MODE_L2C1 (0x27a2) ++ ++// secure_apb.h ++ ++// registers for mipi_dsi (12'h8a0 - 12'h8ff) ++//======================================================================== ++// ++// Reading file: dsi_regs.h ++// ++// synopsys translate_off ++// synopsys translate_on ++//=========================================================================== ++// MIPI DSI HOST CONTROLLER Registers 0x1c00 - 0x1cff ++//=========================================================================== ++// ----------------------------------------------- ++// CBUS_BASE: DSI_CBUS_BASE = 0x1c ++#define MIPI_DSI_REGISTER ++// ----------------------------------------------- ++//------------------------------------------------------------------------------ ++// DWC IP registers: Synopsys IP, please refer to MIPI DSI HOST Databook ++//------------------------------------------------------------------------------ ++#define MIPI_DSI_DWC_VERSION_OS 0x1c00 ++#define MIPI_DSI_DWC_PWR_UP_OS 0x1c01 ++#define MIPI_DSI_DWC_CLKMGR_CFG_OS 0x1c02 ++#define MIPI_DSI_DWC_DPI_VCID_OS 0x1c03 ++#define MIPI_DSI_DWC_DPI_COLOR_CODING_OS 0x1c04 ++#define MIPI_DSI_DWC_DPI_CFG_POL_OS 0x1c05 ++#define MIPI_DSI_DWC_DPI_LP_CMD_TIM_OS 0x1c06 ++#define MIPI_DSI_DWC_PCKHDL_CFG_OS 0x1c0b ++#define MIPI_DSI_DWC_GEN_VCID_OS 0x1c0c ++#define MIPI_DSI_DWC_MODE_CFG_OS 0x1c0d ++#define MIPI_DSI_DWC_VID_MODE_CFG_OS 0x1c0e ++#define MIPI_DSI_DWC_VID_PKT_SIZE_OS 0x1c0f ++#define MIPI_DSI_DWC_VID_NUM_CHUNKS_OS 0x1c10 ++#define MIPI_DSI_DWC_VID_NULL_SIZE_OS 0x1c11 ++#define MIPI_DSI_DWC_VID_HSA_TIME_OS 0x1c12 ++#define MIPI_DSI_DWC_VID_HBP_TIME_OS 0x1c13 ++#define MIPI_DSI_DWC_VID_HLINE_TIME_OS 0x1c14 ++#define MIPI_DSI_DWC_VID_VSA_LINES_OS 0x1c15 ++#define MIPI_DSI_DWC_VID_VBP_LINES_OS 0x1c16 ++#define MIPI_DSI_DWC_VID_VFP_LINES_OS 0x1c17 ++#define MIPI_DSI_DWC_VID_VACTIVE_LINES_OS 0x1c18 ++#define MIPI_DSI_DWC_EDPI_CMD_SIZE_OS 0x1c19 ++#define MIPI_DSI_DWC_CMD_MODE_CFG_OS 0x1c1a ++#define MIPI_DSI_DWC_GEN_HDR_OS 0x1c1b ++#define MIPI_DSI_DWC_GEN_PLD_DATA_OS 0x1c1c ++#define MIPI_DSI_DWC_CMD_PKT_STATUS_OS 0x1c1d ++#define MIPI_DSI_DWC_TO_CNT_CFG_OS 0x1c1e ++#define MIPI_DSI_DWC_HS_RD_TO_CNT_OS 0x1c1f ++#define MIPI_DSI_DWC_LP_RD_TO_CNT_OS 0x1c20 ++#define MIPI_DSI_DWC_HS_WR_TO_CNT_OS 0x1c21 ++#define MIPI_DSI_DWC_LP_WR_TO_CNT_OS 0x1c22 ++#define MIPI_DSI_DWC_BTA_TO_CNT_OS 0x1c23 ++#define MIPI_DSI_DWC_SDF_3D_OS 0x1c24 ++#define MIPI_DSI_DWC_LPCLK_CTRL_OS 0x1c25 ++#define MIPI_DSI_DWC_PHY_TMR_LPCLK_CFG_OS 0x1c26 ++#define MIPI_DSI_DWC_PHY_TMR_CFG_OS 0x1c27 ++#define MIPI_DSI_DWC_PHY_RSTZ_OS 0x1c28 ++#define MIPI_DSI_DWC_PHY_IF_CFG_OS 0x1c29 ++#define MIPI_DSI_DWC_PHY_ULPS_CTRL_OS 0x1c2a ++#define MIPI_DSI_DWC_PHY_TX_TRIGGERS_OS 0x1c2b ++#define MIPI_DSI_DWC_PHY_STATUS_OS 0x1c2c ++#define MIPI_DSI_DWC_PHY_TST_CTRL0_OS 0x1c2d ++#define MIPI_DSI_DWC_PHY_TST_CTRL1_OS 0x1c2e ++#define MIPI_DSI_DWC_INT_ST0_OS 0x1c2f ++#define MIPI_DSI_DWC_INT_ST1_OS 0x1c30 ++#define MIPI_DSI_DWC_INT_MSK0_OS 0x1c31 ++#define MIPI_DSI_DWC_INT_MSK1_OS 0x1c32 ++//------------------------------------------------------------------------------ ++// Top-level registers: AmLogic proprietary ++//------------------------------------------------------------------------------ ++// 31: 4 Reserved. Default 0. ++// 3 RW ~tim_rst_n: 1=Assert SW reset on mipi_dsi_host_timing block. 0=Release reset. Default 1. ++// 2 RW ~dpi_rst_n: 1=Assert SW reset on mipi_dsi_host_dpi block. 0=Release reset. Default 1. ++// 1 RW ~intr_rst_n: 1=Assert SW reset on mipi_dsi_host_intr block. 0=Release reset. Default 1. ++// 0 RW ~dwc_rst_n: 1=Assert SW reset on IP core. 0=Release reset. Default 1. ++#define MIPI_DSI_TOP_SW_RESET 0x1cf0 ++// 31: 5 Reserved. Default 0. ++// 4 RW manual_edpihalt: 1=Manual suspend VencL; 0=do not suspend VencL. Default 0. ++// 3 RW auto_edpihalt_en: 1=Enable IP's edpihalt signal to suspend VencL; 0=IP's edpihalt signal does not affect VencL. Default 0. ++// 2 RW clock_freerun: Apply to auto-clock gate only. Default 0. ++// 0=Default, use auto-clock gating to save power; ++// 1=use free-run clock, disable auto-clock gating, for debug mode. ++// 1 RW enable_pixclk: A manual clock gate option, due to DWC IP does not have auto-clock gating. 1=Enable pixclk. Default 0. ++// 0 RW enable_sysclk: A manual clock gate option, due to DWC IP does not have auto-clock gating. 1=Enable sysclk. Default 0. ++#define MIPI_DSI_TOP_CLK_CNTL 0x1cf1 ++// 31:27 Reserved. Default 0. ++// 26 RW de_dpi_pol: 1= Invert DE polarity from mipi_dsi_host_dpi. Default 0. ++// 25 RW hsync_dpi_pol: 1= Invert HS polarity from mipi_dsi_host_dpi. Default 0. ++// 24 RW vsync_dpi_pol: 1= Invert VS polarity from mipi_dsi_host_dpi. Default 0. ++// 23:20 RW dpi_color_mode: Define DPI pixel format. Default 0. ++// 0=16-bit RGB565 config 1; ++// 1=16-bit RGB565 config 2; ++// 2=16-bit RGB565 config 3; ++// 3=18-bit RGB666 config 1; ++// 4=18-bit RGB666 config 2; ++// 5=24-bit RGB888; ++// 6=20-bit YCbCr 4:2:2; ++// 7=24-bit YCbCr 4:2:2; ++// 8=16-bit YCbCr 4:2:2; ++// 9=30-bit RGB; ++// 10=36-bit RGB; ++// 11=12-bit YCbCr 4:2:0. ++// 19 Reserved. Default 0. ++// 18:16 RW in_color_mode: Define VENC data width. Default 0. ++// 0=30-bit pixel; ++// 1=24-bit pixel; ++// 2=18-bit pixel, RGB666; ++// 3=16-bit pixel, RGB565. ++// 15:14 RW chroma_subsample: Define method of chroma subsampling. Default 0. ++// Applicable to YUV422 or YUV420 only. ++// 0=Use even pixel's chroma; ++// 1=Use odd pixel's chroma; ++// 2=Use averaged value between even and odd pair. ++// 13:12 RW comp2_sel: Select which component to be Cr or B: 0=comp0; 1=comp1; 2=comp2. Default 2. ++// 11:10 RW comp1_sel: Select which component to be Cb or G: 0=comp0; 1=comp1; 2=comp2. Default 1. ++// 9: 8 RW comp0_sel: Select which component to be Y or R: 0=comp0; 1=comp1; 2=comp2. Default 0. ++// 7 Reserved. Default 0. ++// 6 RW de_venc_pol: 1= Invert DE polarity from VENC. Default 0. ++// 5 RW hsync_venc_pol: 1= Invert HS polarity from VENC. Default 0. ++// 4 RW vsync_venc_pol: 1= Invert VS polarity from VENC. Default 0. ++// 3 RW dpicolorm: Signal to IP. Default 0. ++// 2 RW dpishutdn: Signal to IP. Default 0. ++// 1 Reserved. Default 0. ++// 0 Reserved. Default 0. ++#define MIPI_DSI_TOP_CNTL 0x1cf2 ++// 31:16 Reserved. Default 0. ++// 15: 8 RW suspend_frame_rate: Define rate of timed-suspend. Default 0. ++// 0=Execute suspend every frame; 1=Every other frame; ...; 255=Every 256 frame. ++// 7: 3 Reserved. Default 0. ++// 2 RW timed_suspend_en: 1=Enable timed suspend VencL. 0=Disable timed suspend. Default 0. ++// 1 RW manual_suspend_en: 1=Enable manual suspend VencL. 1=Cancel manual suspend VencL. Default 0. ++// 0 RW suspend_on_edpihalt:1=Enable IP's edpihalt signal to suspend VencL; 0=IP's edpihalt signal does not affect VencL. Default 1. ++#define MIPI_DSI_TOP_SUSPEND_CNTL 0x1cf3 ++// 31:29 Reserved. Default 0. ++// 28:16 RW suspend_line_end: Define timed-suspend region. Suspend from [pix_start,line_start] to [pix_end,line_end]. Default 0. ++// 15:13 Reserved. Default 0. ++// 12: 0 RW suspend_line_start: Define timed-suspend region. Suspend from [pix_start,line_start] to [pix_end,line_end]. Default 0. ++#define MIPI_DSI_TOP_SUSPEND_LINE 0x1cf4 ++// 31:29 Reserved. Default 0. ++// 28:16 RW suspend_pix_end: Define timed-suspend region. Suspend from [pix_start,line_start] to [pix_end,line_end]. Default 0. ++// 15:13 Reserved. Default 0. ++// 12: 0 RW suspend_pix_start: Define timed-suspend region. Suspend from [pix_start,line_start] to [pix_end,line_end]. Default 0. ++#define MIPI_DSI_TOP_SUSPEND_PIX 0x1cf5 ++// 31:20 Reserved. Default 0. ++// 19:10 RW meas_vsync: Control on measuring Host Controller's vsync. Default 0. ++// [ 19] meas_en: 1=Enable measurement ++// [ 18] accum_meas_en: 0=meas_count is cleared at the end of each measure; ++// 1=meas_count is accumulated at the end of each measure. ++// [17:10] vsync_span: Define the duration of a measure is to last for how many Vsyncs. ++// 9: 0 RW meas_edpite: Control on measuring Display Slave's edpite. Default 0. ++// [ 9] meas_en: 1=Enable measurement ++// [ 8] accum_meas_en: 0=meas_count is cleared at the end of each measure; ++// 1=meas_count is accumulated at the end of each measure. ++// [ 7: 0] edpite_span: Define the duration of a measure is to last for how many edpite. ++#define MIPI_DSI_TOP_MEAS_CNTL 0x1cf6 ++// 31 R stat_edpihalt: status of edpihalt signal from IP. Default 0. ++// 30:29 Reserved. Default 0. ++// 28:16 R stat_te_line: Snapshot of Host's line position at edpite. Default 0. ++// 15:13 Reserved. Default 0. ++// 12: 0 R stat_te_pix: Snapshot of Host's pixel position at edpite. Default 0. ++#define MIPI_DSI_TOP_STAT 0x1cf7 ++// To measure display slave's frame rate, we can use a reference clock to measure the duration of one of more edpite pulse(s). ++// Measurement control is by register MIPI_DSI_TOP_MEAS_CNTL bit[9:0]. ++// Reference clock comes from clk_rst_tst.cts_dsi_meas_clk, and is defined by HIU register HHI_VDIN_MEAS_CLK_CNTL bit[23:12]. ++// Mesurement result is in MIPI_DSI_TOP_MEAS_STAT_TE0 and MIPI_DSI_TOP_MEAS_STAT_TE1, as below: ++// edpite_meas_count[47:0]: Number of reference clock cycles counted during one measure period (non-incremental measure), or ++// during all measure periods so far (incremental measure). ++// edpite_meas_count_n[3:0]:Number of measure periods has been done. Number can wrap over. ++// ++// 31: 0 R edpite_meas_count[31:0]. Default 0. ++#define MIPI_DSI_TOP_MEAS_STAT_TE0 0x1cf8 ++// 19:16 R edpite_meas_count_n. Default 0. ++// 15: 0 R edpite_meas_count[47:32]. Default 0. ++#define MIPI_DSI_TOP_MEAS_STAT_TE1 0x1cf9 ++// To measure Host's frame rate, we can use a reference clock to measure the duration of one of more Vsync pulse(s). ++// Measurement control is by register MIPI_DSI_TOP_MEAS_CNTL bit[19:10]. ++// Reference clock comes from clk_rst_tst.cts_dsi_meas_clk, and is defined by HIU register HHI_VDIN_MEAS_CLK_CNTL bit[23:12]. ++// Mesurement result is in MIPI_DSI_TOP_MEAS_STAT_VS0 and MIPI_DSI_TOP_MEAS_STAT_VS1, as below: ++// vsync_meas_count[47:0]: Number of reference clock cycles counted during one measure period (non-incremental measure), or ++// during all measure periods so far (incremental measure). ++// vsync_meas_count_n[3:0]: Number of measure periods has been done. Number can wrap over. ++// ++// 31: 0 R vsync_meas_count[31:0]. Default 0. ++#define MIPI_DSI_TOP_MEAS_STAT_VS0 0x1cfa ++// 19:16 R vsync_meas_count_n. Default 0. ++// 15: 0 R vsync_meas_count[47:32]. Default 0. ++#define MIPI_DSI_TOP_MEAS_STAT_VS1 0x1cfb ++// 31:16 RW intr_stat/clr. For each bit, read as this interrupt level status, write 1 to clear. Default 0. ++// Note: To clear the interrupt level, simply write 1 to the specific bit, no need to write 0 afterwards. ++// [31:22] Reserved ++// [ 21] stat/clr of EOF interrupt ++// [ 20] stat/clr of de_fall interrupt ++// [ 19] stat/clr of de_rise interrupt ++// [ 18] stat/clr of vs_fall interrupt ++// [ 17] stat/clr of vs_rise interrupt ++// [ 16] stat/clr of dwc_edpite interrupt ++// 15: 0 RW intr_enable. For each bit, 1=enable this interrupt, 0=disable. Default 0. ++// [15: 6] Reserved ++// [ 5] EOF (End_Of_Field) interrupt ++// [ 4] de_fall interrupt ++// [ 3] de_rise interrupt ++// [ 2] vs_fall interrupt ++// [ 1] vs_rise interrupt ++// [ 0] dwc_edpite interrupt ++#define MIPI_DSI_TOP_INTR_CNTL_STAT 0x1cfc ++// 31: 2 Reserved. Default 0. ++// 1: 0 RW mem_pd. Default 3. ++#define MIPI_DSI_TOP_MEM_PD 0x1cfd ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: dsi_regs.h ++#define VD1_HDR2_CTRL 0x3800 ++#define VD1_HDR2_CLK_GATE 0x3801 ++#define VD1_HDR2_MATRIXI_COEF00_01 0x3802 ++#define VD1_HDR2_MATRIXI_COEF02_10 0x3803 ++#define VD1_HDR2_MATRIXI_COEF11_12 0x3804 ++#define VD1_HDR2_MATRIXI_COEF20_21 0x3805 ++#define VD1_HDR2_MATRIXI_COEF22 0x3806 ++#define VD1_HDR2_MATRIXI_COEF30_31 0x3807 ++#define VD1_HDR2_MATRIXI_COEF32_40 0x3808 ++#define VD1_HDR2_MATRIXI_COEF41_42 0x3809 ++#define VD1_HDR2_MATRIXI_OFFSET0_1 0x380a ++#define VD1_HDR2_MATRIXI_OFFSET2 0x380b ++#define VD1_HDR2_MATRIXI_PRE_OFFSET0_1 0x380c ++#define VD1_HDR2_MATRIXI_PRE_OFFSET2 0x380d ++#define VD1_HDR2_MATRIXO_COEF00_01 0x380e ++#define VD1_HDR2_MATRIXO_COEF02_10 0x380f ++#define VD1_HDR2_MATRIXO_COEF11_12 0x3810 ++#define VD1_HDR2_MATRIXO_COEF20_21 0x3811 ++#define VD1_HDR2_MATRIXO_COEF22 0x3812 ++#define VD1_HDR2_MATRIXO_COEF30_31 0x3813 ++#define VD1_HDR2_MATRIXO_COEF32_40 0x3814 ++#define VD1_HDR2_MATRIXO_COEF41_42 0x3815 ++#define VD1_HDR2_MATRIXO_OFFSET0_1 0x3816 ++#define VD1_HDR2_MATRIXO_OFFSET2 0x3817 ++#define VD1_HDR2_MATRIXO_PRE_OFFSET0_1 0x3818 ++#define VD1_HDR2_MATRIXO_PRE_OFFSET2 0x3819 ++#define VD1_HDR2_MATRIXI_CLIP 0x381a ++#define VD1_HDR2_MATRIXO_CLIP 0x381b ++#define VD1_HDR2_CGAIN_OFFT 0x381c ++#define VD1_EOTF_LUT_ADDR_PORT 0x381e ++#define VD1_EOTF_LUT_DATA_PORT 0x381f ++#define VD1_OETF_LUT_ADDR_PORT 0x3820 ++#define VD1_OETF_LUT_DATA_PORT 0x3821 ++#define VD1_CGAIN_LUT_ADDR_PORT 0x3822 ++#define VD1_CGAIN_LUT_DATA_PORT 0x3823 ++#define VD1_HDR2_CGAIN_COEF0 0x3824 ++#define VD1_HDR2_CGAIN_COEF1 0x3825 ++#define VD1_OGAIN_LUT_ADDR_PORT 0x3826 ++#define VD1_OGAIN_LUT_DATA_PORT 0x3827 ++#define VD1_HDR2_ADPS_CTRL 0x3828 ++#define VD1_HDR2_ADPS_ALPHA0 0x3829 ++#define VD1_HDR2_ADPS_ALPHA1 0x382a ++#define VD1_HDR2_ADPS_BETA0 0x382b ++#define VD1_HDR2_ADPS_BETA1 0x382c ++#define VD1_HDR2_ADPS_BETA2 0x382d ++#define VD1_HDR2_ADPS_COEF0 0x382e ++#define VD1_HDR2_ADPS_COEF1 0x382f ++#define VD1_HDR2_GMUT_CTRL 0x3830 ++#define VD1_HDR2_GMUT_COEF0 0x3831 ++#define VD1_HDR2_GMUT_COEF1 0x3832 ++#define VD1_HDR2_GMUT_COEF2 0x3833 ++#define VD1_HDR2_GMUT_COEF3 0x3834 ++#define VD1_HDR2_GMUT_COEF4 0x3835 ++#define VD1_HDR2_PIPE_CTRL1 0x3836 ++#define VD1_HDR2_PIPE_CTRL2 0x3837 ++#define VD1_HDR2_PIPE_CTRL3 0x3838 ++#define VD1_HDR2_PROC_WIN1 0x3839 ++#define VD1_HDR2_PROC_WIN2 0x383a ++#define VD1_HDR2_MATRIXI_EN_CTRL 0x383b ++#define VD1_HDR2_MATRIXO_EN_CTRL 0x383c ++ ++#define VD2_HDR2_CTRL 0x3850 ++#define VD2_HDR2_CLK_GATE 0x3851 ++#define VD2_HDR2_MATRIXI_COEF00_01 0x3852 ++#define VD2_HDR2_MATRIXI_COEF02_10 0x3853 ++#define VD2_HDR2_MATRIXI_COEF11_12 0x3854 ++#define VD2_HDR2_MATRIXI_COEF20_21 0x3855 ++#define VD2_HDR2_MATRIXI_COEF22 0x3856 ++#define VD2_HDR2_MATRIXI_COEF30_31 0x3857 ++#define VD2_HDR2_MATRIXI_COEF32_40 0x3858 ++#define VD2_HDR2_MATRIXI_COEF41_42 0x3859 ++#define VD2_HDR2_MATRIXI_OFFSET0_1 0x385a ++#define VD2_HDR2_MATRIXI_OFFSET2 0x385b ++#define VD2_HDR2_MATRIXI_PRE_OFFSET0_1 0x385c ++#define VD2_HDR2_MATRIXI_PRE_OFFSET2 0x385d ++#define VD2_HDR2_MATRIXO_COEF00_01 0x385e ++#define VD2_HDR2_MATRIXO_COEF02_10 0x385f ++#define VD2_HDR2_MATRIXO_COEF11_12 0x3860 ++#define VD2_HDR2_MATRIXO_COEF20_21 0x3861 ++#define VD2_HDR2_MATRIXO_COEF22 0x3862 ++#define VD2_HDR2_MATRIXO_COEF30_31 0x3863 ++#define VD2_HDR2_MATRIXO_COEF32_40 0x3864 ++#define VD2_HDR2_MATRIXO_COEF41_42 0x3865 ++#define VD2_HDR2_MATRIXO_OFFSET0_1 0x3866 ++#define VD2_HDR2_MATRIXO_OFFSET2 0x3867 ++#define VD2_HDR2_MATRIXO_PRE_OFFSET0_1 0x3868 ++#define VD2_HDR2_MATRIXO_PRE_OFFSET2 0x3869 ++#define VD2_HDR2_MATRIXI_CLIP 0x386a ++#define VD2_HDR2_MATRIXO_CLIP 0x386b ++#define VD2_HDR2_CGAIN_OFFT 0x386c ++#define VD2_EOTF_LUT_ADDR_PORT 0x386e ++#define VD2_EOTF_LUT_DATA_PORT 0x386f ++#define VD2_OETF_LUT_ADDR_PORT 0x3870 ++#define VD2_OETF_LUT_DATA_PORT 0x3871 ++#define VD2_CGAIN_LUT_ADDR_PORT 0x3872 ++#define VD2_CGAIN_LUT_DATA_PORT 0x3873 ++#define VD2_HDR2_CGAIN_COEF0 0x3874 ++#define VD2_HDR2_CGAIN_COEF1 0x3875 ++#define VD2_OGAIN_LUT_ADDR_PORT 0x3876 ++#define VD2_OGAIN_LUT_DATA_PORT 0x3877 ++#define VD2_HDR2_ADPS_CTRL 0x3878 ++#define VD2_HDR2_ADPS_ALPHA0 0x3879 ++#define VD2_HDR2_ADPS_ALPHA1 0x387a ++#define VD2_HDR2_ADPS_BETA0 0x387b ++#define VD2_HDR2_ADPS_BETA1 0x387c ++#define VD2_HDR2_ADPS_BETA2 0x387d ++#define VD2_HDR2_ADPS_COEF0 0x387e ++#define VD2_HDR2_ADPS_COEF1 0x387f ++#define VD2_HDR2_GMUT_CTRL 0x3880 ++#define VD2_HDR2_GMUT_COEF0 0x3881 ++#define VD2_HDR2_GMUT_COEF1 0x3882 ++#define VD2_HDR2_GMUT_COEF2 0x3883 ++#define VD2_HDR2_GMUT_COEF3 0x3884 ++#define VD2_HDR2_GMUT_COEF4 0x3885 ++#define VD2_HDR2_PIPE_CTRL1 0x3886 ++#define VD2_HDR2_PIPE_CTRL2 0x3887 ++#define VD2_HDR2_PIPE_CTRL3 0x3888 ++#define VD2_HDR2_PROC_WIN1 0x3889 ++#define VD2_HDR2_PROC_WIN2 0x388a ++#define VD2_HDR2_MATRIXI_EN_CTRL 0x388b ++#define VD2_HDR2_MATRIXO_EN_CTRL 0x388c ++ ++#define OSD1_HDR2_CTRL 0x38a0 ++#define OSD1_HDR2_CLK_GATE 0x38a1 ++#define OSD1_HDR2_MATRIXI_COEF00_01 0x38a2 ++#define OSD1_HDR2_MATRIXI_COEF02_10 0x38a3 ++#define OSD1_HDR2_MATRIXI_COEF11_12 0x38a4 ++#define OSD1_HDR2_MATRIXI_COEF20_21 0x38a5 ++#define OSD1_HDR2_MATRIXI_COEF22 0x38a6 ++#define OSD1_HDR2_MATRIXI_COEF30_31 0x38a7 ++#define OSD1_HDR2_MATRIXI_COEF32_40 0x38a8 ++#define OSD1_HDR2_MATRIXI_COEF41_42 0x38a9 ++#define OSD1_HDR2_MATRIXI_OFFSET0_1 0x38aa ++#define OSD1_HDR2_MATRIXI_OFFSET2 0x38ab ++#define OSD1_HDR2_MATRIXI_PRE_OFFSET0_1 0x38ac ++#define OSD1_HDR2_MATRIXI_PRE_OFFSET2 0x38ad ++#define OSD1_HDR2_MATRIXO_COEF00_01 0x38ae ++#define OSD1_HDR2_MATRIXO_COEF02_10 0x38af ++#define OSD1_HDR2_MATRIXO_COEF11_12 0x38b0 ++#define OSD1_HDR2_MATRIXO_COEF20_21 0x38b1 ++#define OSD1_HDR2_MATRIXO_COEF22 0x38b2 ++#define OSD1_HDR2_MATRIXO_COEF30_31 0x38b3 ++#define OSD1_HDR2_MATRIXO_COEF32_40 0x38b4 ++#define OSD1_HDR2_MATRIXO_COEF41_42 0x38b5 ++#define OSD1_HDR2_MATRIXO_OFFSET0_1 0x38b6 ++#define OSD1_HDR2_MATRIXO_OFFSET2 0x38b7 ++#define OSD1_HDR2_MATRIXO_PRE_OFFSET0_1 0x38b8 ++#define OSD1_HDR2_MATRIXO_PRE_OFFSET2 0x38b9 ++#define OSD1_HDR2_MATRIXI_CLIP 0x38ba ++#define OSD1_HDR2_MATRIXO_CLIP 0x38bb ++#define OSD1_HDR2_CGAIN_OFFT 0x38bc ++#define OSD1_EOTF_LUT_ADDR_PORT 0x38be ++#define OSD1_EOTF_LUT_DATA_PORT 0x38bf ++#define OSD1_OETF_LUT_ADDR_PORT 0x38c0 ++#define OSD1_OETF_LUT_DATA_PORT 0x38c1 ++#define OSD1_CGAIN_LUT_ADDR_PORT 0x38c2 ++#define OSD1_CGAIN_LUT_DATA_PORT 0x38c3 ++#define OSD1_HDR2_CGAIN_COEF0 0x38c4 ++#define OSD1_HDR2_CGAIN_COEF1 0x38c5 ++#define OSD1_OGAIN_LUT_ADDR_PORT 0x38c6 ++#define OSD1_OGAIN_LUT_DATA_PORT 0x38c7 ++#define OSD1_HDR2_ADPS_CTRL 0x38c8 ++#define OSD1_HDR2_ADPS_ALPHA0 0x38c9 ++#define OSD1_HDR2_ADPS_ALPHA1 0x38ca ++#define OSD1_HDR2_ADPS_BETA0 0x38cb ++#define OSD1_HDR2_ADPS_BETA1 0x38cc ++#define OSD1_HDR2_ADPS_BETA2 0x38cd ++#define OSD1_HDR2_ADPS_COEF0 0x38ce ++#define OSD1_HDR2_ADPS_COEF1 0x38cf ++#define OSD1_HDR2_GMUT_CTRL 0x38d0 ++#define OSD1_HDR2_GMUT_COEF0 0x38d1 ++#define OSD1_HDR2_GMUT_COEF1 0x38d2 ++#define OSD1_HDR2_GMUT_COEF2 0x38d3 ++#define OSD1_HDR2_GMUT_COEF3 0x38d4 ++#define OSD1_HDR2_GMUT_COEF4 0x38d5 ++#define OSD1_HDR2_PIPE_CTRL1 0x38d6 ++#define OSD1_HDR2_PIPE_CTRL2 0x38d7 ++#define OSD1_HDR2_PIPE_CTRL3 0x38d8 ++#define OSD1_HDR2_PROC_WIN1 0x38d9 ++#define OSD1_HDR2_PROC_WIN2 0x38da ++#define OSD1_HDR2_MATRIXI_EN_CTRL 0x38db ++#define OSD1_HDR2_MATRIXO_EN_CTRL 0x38dc +diff --git a/include/amlogic/asm/romboot.h b/include/amlogic/asm/romboot.h +new file mode 100644 +index 00000000000..338365e87a6 +--- /dev/null ++++ b/include/amlogic/asm/romboot.h +@@ -0,0 +1,53 @@ ++ ++/* ++ * arch/arm/include/asm/arch-txl/romboot.h ++ * ++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++*/ ++ ++#ifndef __BOOT_ROM_H_ ++#define __BOOT_ROM_H_ ++#ifndef __ASSEMBLY__ ++//#include ++//uint8_t simple_i2c(uint8_t adr); ++//void spi_pin_mux(void); ++//void spi_init(void); ++//uint32_t spi_read(uint32_t src, uint32_t mem, uint32_t size); ++//void udelay(uint32_t usec); ++//void boot_des_decrypt(uint8_t *ct, uint8_t *pt, uint32_t size); ++ ++#endif /* ! __ASSEMBLY__ */ ++#include "config.h" ++ ++/* Magic number to "boot" up A53 */ ++#define AO_SEC_SD_CFG10_CB 0x80000000 ++ ++/*BOOT device and ddr size*/ ++/*31-28: boot device id, 27-24: boot device para, 23-20: reserved*/ ++/*19-8: ddr size, 7-0: board revision*/ ++//#define P_AO_SEC_GP_CFG0 0xDA100240 //defined in secure_apb.h ++#define AO_SEC_GP_CFG7_W0_BIT 8 ++#define AO_SEC_GP_CFG7_W0 0x100 ++ ++#define BOOT_ID_RESERVED 0 ++#define BOOT_ID_EMMC 1 ++#define BOOT_ID_NAND 2 ++#define BOOT_ID_SPI 3 ++#define BOOT_ID_SDCARD 4 ++#define BOOT_ID_USB 5 ++ ++#endif /* __BOOT_ROM_H_ */ +diff --git a/include/amlogic/asm/sd_emmc.h b/include/amlogic/asm/sd_emmc.h +new file mode 100644 +index 00000000000..81de3a9674c +--- /dev/null ++++ b/include/amlogic/asm/sd_emmc.h +@@ -0,0 +1,136 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * (C) Copyright 2016 Carlo Caione ++ */ ++ ++#ifndef __SD_EMMC_H__ ++#define __SD_EMMC_H__ ++ ++#include ++ ++#define SDIO_PORT_A 0 ++#define SDIO_PORT_B 1 ++#define SDIO_PORT_C 2 ++ ++#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */ ++#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */ ++ ++#define MESON_SD_EMMC_CLOCK 0x00 ++#define CLK_MAX_DIV GENMASK(5, 0) ++#define CLK_MAX_SRC GENMASK(7, 6) ++#define Cfg_div 0 ++#define Cfg_src 6 ++#define Cfg_co_phase 8 ++#define Cfg_tx_phase 10 ++#define Cfg_rx_phase 12 ++#define Cfg_sram_pd 14 ++#define Cfg_tx_delay 16 ++#define Cfg_rx_delay 22 ++#define Cfg_always_on 28 ++#define Cfg_irq_sdio_sleep 29 ++#define Cfg_irq_sdio_sleep_ds 30 ++ ++#define MESON_SD_EMMC_DELAY1 0x4 ++#define DLY_D0_MASK GENMASK(5, 0) ++#define DLY_D1_MASK GENMASK(11, 6) ++#define DLY_D2_MASK GENMASK(17, 12) ++#define DLY_D3_MASK GENMASK(23, 18) ++#define DLY_D4_MASK GENMASK(31, 24) ++#define Dly_d0 0 ++#define Dly_d1 6 ++#define Dly_d2 12 ++#define Dly_d3 18 ++#define Dly_d4 24 ++ ++#define MESON_SD_EMMC_DELAY2 0x8 ++#define DLY_D5_MASK GENMASK(5, 0) ++#define DLY_D6_MASK GENMASK(11, 6) ++#define DLY_D7_MASK GENMASK(17, 12) ++#define DLY_D8_MASK GENMASK(23, 18) ++#define DLY_D9_MASK GENMASK(31, 24) ++#define Dly_d5 0 ++#define Dly_d6 6 ++#define Dly_d7 12 ++#define Dly_d8 18 ++#define Dly_d9 24 ++ ++#define MESON_SD_EMMC_ADJUST 0xC ++#define CALI_SEL_MASK GENMASK(11, 8) ++#define ADJ_DLY_MASK GENMASK(21, 16) ++#define Cfg_cali_sel 8 ++#define Cfg_cali_en 12 ++#define Cfg_adj_en 13 ++#define Cfg_cali_rise 14 ++#define Cfg_ds_en 15 ++#define Cfg_adj_dly 16 ++#define Cfg_adj_auto 22 ++#define Cfg_adj_init 23 ++ ++#define MESON_SD_EMMC_START 0x40 ++#define CFG_DESC_INIT BIT(0) ++#define CFG_DESC_BUSY BIT(1) ++#define CFG_DESC_ADDR 2 ++ ++#define MESON_SD_EMMC_CFG 0x44 ++#define CFG_BUS_WIDTH_MASK GENMASK(1, 0) ++#define CFG_BUS_WIDTH_1 0 ++#define CFG_BUS_WIDTH_4 1 ++#define CFG_BUS_WIDTH_8 2 ++#define CFG_DDR BIT(2) ++#define CFG_BL_LEN_MASK GENMASK(7, 4) ++#define CFG_BL_LEN_SHIFT 4 ++#define CFG_BL_LEN_512 (9 << 4) ++#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) ++#define CFG_RESP_TIMEOUT_256 (8 << 8) ++#define CFG_RC_CC_MASK GENMASK(15, 12) ++#define CFG_RC_CC_16 (4 << 12) ++#define CFG_SDCLK_ALWAYS_ON BIT(18) ++#define CFG_AUTO_CLK BIT(23) ++ ++#define MESON_SD_EMMC_STATUS 0x48 ++#define STATUS_MASK GENMASK(15, 0) ++#define STATUS_ERR_MASK GENMASK(12, 0) ++#define STATUS_RXD_ERR_MASK GENMASK(7, 0) ++#define STATUS_TXD_ERR BIT(8) ++#define STATUS_DESC_ERR BIT(9) ++#define STATUS_RESP_ERR BIT(10) ++#define STATUS_RESP_TIMEOUT BIT(11) ++#define STATUS_DESC_TIMEOUT BIT(12) ++#define STATUS_END_OF_CHAIN BIT(13) ++ ++#define MESON_SD_EMMC_IRQ_EN 0x4c ++ ++#define MESON_SD_EMMC_CMD_CFG 0x50 ++#define CMD_CFG_LENGTH_MASK GENMASK(8, 0) ++#define CMD_CFG_BLOCK_MODE BIT(9) ++#define CMD_CFG_R1B BIT(10) ++#define CMD_CFG_END_OF_CHAIN BIT(11) ++#define CMD_CFG_TIMEOUT_4S (12 << 12) ++#define CMD_CFG_NO_RESP BIT(16) ++#define CMD_CFG_NO_CMD BIT(17) ++#define CMD_CFG_DATA_IO BIT(18) ++#define CMD_CFG_DATA_WR BIT(19) ++#define CMD_CFG_RESP_NOCRC BIT(20) ++#define CMD_CFG_RESP_128 BIT(21) ++#define CMD_CFG_RESP_NUM BIT(22) ++#define CMD_CFG_DATA_NUM BIT(23) ++#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24) ++#define CMD_CFG_CMD_INDEX_SHIFT 24 ++#define CMD_CFG_ERR BIT(30) ++#define CMD_CFG_OWNER BIT(31) ++ ++#define MESON_SD_EMMC_CMD_ARG 0x54 ++#define MESON_SD_EMMC_CMD_DAT 0x58 ++#define MESON_SD_EMMC_CMD_RSP 0x5c ++#define MESON_SD_EMMC_CMD_RSP1 0x60 ++#define MESON_SD_EMMC_CMD_RSP2 0x64 ++#define MESON_SD_EMMC_CMD_RSP3 0x68 ++ ++#define SD_EMMC_RXD_ERROR (1 << 0) ++#define SD_EMMC_TXD_ERROR (1 << 1) ++#define SD_EMMC_DESC_ERROR (1 << 2) ++#define SD_EMMC_RESP_CRC_ERROR (1 << 3) ++#define SD_EMMC_RESP_TIMEOUT_ERROR (1 << 4) ++#define SD_EMMC_DESC_TIMEOUT_ERROR (1 << 5) ++ ++#endif +diff --git a/include/amlogic/asm/secure_apb.h b/include/amlogic/asm/secure_apb.h +new file mode 100644 +index 00000000000..a146334e50f +--- /dev/null ++++ b/include/amlogic/asm/secure_apb.h +@@ -0,0 +1,4235 @@ ++// ---------------------------------------------------------------------- ++// This file is automatically generated from the script: ++// ++// ./create_headers_from_register_map_h.pl ++// ++// and was applied to the file ++// ++// ./register_map.h ++// ++// DO NOT EDIT!!!!! ++// ---------------------------------------------------------------------- ++// ++#include ++ ++#ifdef REGISTER_H ++#else ++#define REGISTER_H ++#endif ++ ++// ---------------------------------------------------------------------- ++// This file is automatically generated from the script: ++// ++// ./create_headers_from_secure_apb4_h.pl ++// ++// and was applied to the file ++// ++// ./secure_apb4_ee.h ./ao_rti_reg.h ++// ++// DO NOT EDIT!!!!! ++// ---------------------------------------------------------------------- ++// ++ ++#ifdef SECURE_APB_H ++#else ++#define SECURE_APB_H ++ ++// ++// Reading file: ./secure_apb4_ee.h ++// ++// synopsys translate_off ++// synopsys translate_on ++//======================================================================== ++// MIPI_DSI_PHY ++//======================================================================== ++// APB4_DECODER_NON_SECURE_BASE 32'hFF644000 ++// APB4_DECODER_SECURE_BASE 32'hFF644000 ++//`define MIPI_DSI_PHY_START 8'h00 ++//`define MIPI_DSI_PHY_END 16'hffff ++#define MIPI_DSI_PHY_CTRL (0xff644000 + (0x000 << 2)) ++#define SEC_MIPI_DSI_PHY_CTRL (0xff644000 + (0x000 << 2)) ++#define P_MIPI_DSI_PHY_CTRL (volatile uint32_t *)(0xff644000 + (0x000 << 2)) ++#define MIPI_DSI_CHAN_CTRL (0xff644000 + (0x001 << 2)) ++#define SEC_MIPI_DSI_CHAN_CTRL (0xff644000 + (0x001 << 2)) ++#define P_MIPI_DSI_CHAN_CTRL (volatile uint32_t *)(0xff644000 + (0x001 << 2)) ++#define MIPI_DSI_CHAN_STS (0xff644000 + (0x002 << 2)) ++#define SEC_MIPI_DSI_CHAN_STS (0xff644000 + (0x002 << 2)) ++#define P_MIPI_DSI_CHAN_STS (volatile uint32_t *)(0xff644000 + (0x002 << 2)) ++#define MIPI_DSI_CLK_TIM (0xff644000 + (0x003 << 2)) ++#define SEC_MIPI_DSI_CLK_TIM (0xff644000 + (0x003 << 2)) ++#define P_MIPI_DSI_CLK_TIM (volatile uint32_t *)(0xff644000 + (0x003 << 2)) ++#define MIPI_DSI_HS_TIM (0xff644000 + (0x004 << 2)) ++#define SEC_MIPI_DSI_HS_TIM (0xff644000 + (0x004 << 2)) ++#define P_MIPI_DSI_HS_TIM (volatile uint32_t *)(0xff644000 + (0x004 << 2)) ++#define MIPI_DSI_LP_TIM (0xff644000 + (0x005 << 2)) ++#define SEC_MIPI_DSI_LP_TIM (0xff644000 + (0x005 << 2)) ++#define P_MIPI_DSI_LP_TIM (volatile uint32_t *)(0xff644000 + (0x005 << 2)) ++#define MIPI_DSI_ANA_UP_TIM (0xff644000 + (0x006 << 2)) ++#define SEC_MIPI_DSI_ANA_UP_TIM (0xff644000 + (0x006 << 2)) ++#define P_MIPI_DSI_ANA_UP_TIM (volatile uint32_t *)(0xff644000 + (0x006 << 2)) ++#define MIPI_DSI_INIT_TIM (0xff644000 + (0x007 << 2)) ++#define SEC_MIPI_DSI_INIT_TIM (0xff644000 + (0x007 << 2)) ++#define P_MIPI_DSI_INIT_TIM (volatile uint32_t *)(0xff644000 + (0x007 << 2)) ++#define MIPI_DSI_WAKEUP_TIM (0xff644000 + (0x008 << 2)) ++#define SEC_MIPI_DSI_WAKEUP_TIM (0xff644000 + (0x008 << 2)) ++#define P_MIPI_DSI_WAKEUP_TIM (volatile uint32_t *)(0xff644000 + (0x008 << 2)) ++#define MIPI_DSI_LPOK_TIM (0xff644000 + (0x009 << 2)) ++#define SEC_MIPI_DSI_LPOK_TIM (0xff644000 + (0x009 << 2)) ++#define P_MIPI_DSI_LPOK_TIM (volatile uint32_t *)(0xff644000 + (0x009 << 2)) ++#define MIPI_DSI_LP_WCHDOG (0xff644000 + (0x00a << 2)) ++#define SEC_MIPI_DSI_LP_WCHDOG (0xff644000 + (0x00a << 2)) ++#define P_MIPI_DSI_LP_WCHDOG (volatile uint32_t *)(0xff644000 + (0x00a << 2)) ++#define MIPI_DSI_ANA_CTRL (0xff644000 + (0x00b << 2)) ++#define SEC_MIPI_DSI_ANA_CTRL (0xff644000 + (0x00b << 2)) ++#define P_MIPI_DSI_ANA_CTRL (volatile uint32_t *)(0xff644000 + (0x00b << 2)) ++#define MIPI_DSI_CLK_TIM1 (0xff644000 + (0x00c << 2)) ++#define SEC_MIPI_DSI_CLK_TIM1 (0xff644000 + (0x00c << 2)) ++#define P_MIPI_DSI_CLK_TIM1 (volatile uint32_t *)(0xff644000 + (0x00c << 2)) ++#define MIPI_DSI_TURN_WCHDOG (0xff644000 + (0x00d << 2)) ++#define SEC_MIPI_DSI_TURN_WCHDOG (0xff644000 + (0x00d << 2)) ++#define P_MIPI_DSI_TURN_WCHDOG (volatile uint32_t *)(0xff644000 + (0x00d << 2)) ++#define MIPI_DSI_ULPS_CHECK (0xff644000 + (0x00e << 2)) ++#define SEC_MIPI_DSI_ULPS_CHECK (0xff644000 + (0x00e << 2)) ++#define P_MIPI_DSI_ULPS_CHECK (volatile uint32_t *)(0xff644000 + (0x00e << 2)) ++#define MIPI_DSI_TEST_CTRL0 (0xff644000 + (0x00f << 2)) ++#define SEC_MIPI_DSI_TEST_CTRL0 (0xff644000 + (0x00f << 2)) ++#define P_MIPI_DSI_TEST_CTRL0 (volatile uint32_t *)(0xff644000 + (0x00f << 2)) ++#define MIPI_DSI_TEST_CTRL1 (0xff644000 + (0x010 << 2)) ++#define SEC_MIPI_DSI_TEST_CTRL1 (0xff644000 + (0x010 << 2)) ++#define P_MIPI_DSI_TEST_CTRL1 (volatile uint32_t *)(0xff644000 + (0x010 << 2)) ++//======================================================================== ++// Temp sensor PLL ++//======================================================================== ++// APB4_DECODER_NON_SECURE_BASE 32'hFF634800 ++// APB4_DECODER_SECURE_BASE 32'hFF634800 ++#define TS_PLL_CFG_REG1 (0xff634800 + (0x001 << 2)) ++#define SEC_TS_PLL_CFG_REG1 (0xff634800 + (0x001 << 2)) ++#define P_TS_PLL_CFG_REG1 (volatile uint32_t *)(0xff634800 + (0x001 << 2)) ++#define TS_PLL_CFG_REG2 (0xff634800 + (0x002 << 2)) ++#define SEC_TS_PLL_CFG_REG2 (0xff634800 + (0x002 << 2)) ++#define P_TS_PLL_CFG_REG2 (volatile uint32_t *)(0xff634800 + (0x002 << 2)) ++#define TS_PLL_CFG_REG3 (0xff634800 + (0x003 << 2)) ++#define SEC_TS_PLL_CFG_REG3 (0xff634800 + (0x003 << 2)) ++#define P_TS_PLL_CFG_REG3 (volatile uint32_t *)(0xff634800 + (0x003 << 2)) ++#define TS_PLL_CFG_REG4 (0xff634800 + (0x004 << 2)) ++#define SEC_TS_PLL_CFG_REG4 (0xff634800 + (0x004 << 2)) ++#define P_TS_PLL_CFG_REG4 (volatile uint32_t *)(0xff634800 + (0x004 << 2)) ++#define TS_PLL_CFG_REG5 (0xff634800 + (0x005 << 2)) ++#define SEC_TS_PLL_CFG_REG5 (0xff634800 + (0x005 << 2)) ++#define P_TS_PLL_CFG_REG5 (volatile uint32_t *)(0xff634800 + (0x005 << 2)) ++#define TS_PLL_CFG_REG6 (0xff634800 + (0x006 << 2)) ++#define SEC_TS_PLL_CFG_REG6 (0xff634800 + (0x006 << 2)) ++#define P_TS_PLL_CFG_REG6 (volatile uint32_t *)(0xff634800 + (0x006 << 2)) ++#define TS_PLL_CFG_REG7 (0xff634800 + (0x007 << 2)) ++#define SEC_TS_PLL_CFG_REG7 (0xff634800 + (0x007 << 2)) ++#define P_TS_PLL_CFG_REG7 (volatile uint32_t *)(0xff634800 + (0x007 << 2)) ++#define TS_PLL_STAT0 (0xff634800 + (0x010 << 2)) ++#define SEC_TS_PLL_STAT0 (0xff634800 + (0x010 << 2)) ++#define P_TS_PLL_STAT0 (volatile uint32_t *)(0xff634800 + (0x010 << 2)) ++#define TS_PLL_STAT1 (0xff634800 + (0x011 << 2)) ++#define SEC_TS_PLL_STAT1 (0xff634800 + (0x011 << 2)) ++#define P_TS_PLL_STAT1 (volatile uint32_t *)(0xff634800 + (0x011 << 2)) ++#define TS_PLL_STAT2 (0xff634800 + (0x012 << 2)) ++#define SEC_TS_PLL_STAT2 (0xff634800 + (0x012 << 2)) ++#define P_TS_PLL_STAT2 (volatile uint32_t *)(0xff634800 + (0x012 << 2)) ++#define TS_PLL_STAT3 (0xff634800 + (0x013 << 2)) ++#define SEC_TS_PLL_STAT3 (0xff634800 + (0x013 << 2)) ++#define P_TS_PLL_STAT3 (volatile uint32_t *)(0xff634800 + (0x013 << 2)) ++#define TS_PLL_STAT4 (0xff634800 + (0x014 << 2)) ++#define SEC_TS_PLL_STAT4 (0xff634800 + (0x014 << 2)) ++#define P_TS_PLL_STAT4 (volatile uint32_t *)(0xff634800 + (0x014 << 2)) ++#define TS_PLL_STAT5 (0xff634800 + (0x015 << 2)) ++#define SEC_TS_PLL_STAT5 (0xff634800 + (0x015 << 2)) ++#define P_TS_PLL_STAT5 (volatile uint32_t *)(0xff634800 + (0x015 << 2)) ++#define TS_PLL_STAT6 (0xff634800 + (0x016 << 2)) ++#define SEC_TS_PLL_STAT6 (0xff634800 + (0x016 << 2)) ++#define P_TS_PLL_STAT6 (volatile uint32_t *)(0xff634800 + (0x016 << 2)) ++#define TS_PLL_STAT7 (0xff634800 + (0x017 << 2)) ++#define SEC_TS_PLL_STAT7 (0xff634800 + (0x017 << 2)) ++#define P_TS_PLL_STAT7 (volatile uint32_t *)(0xff634800 + (0x017 << 2)) ++#define TS_PLL_STAT8 (0xff634800 + (0x018 << 2)) ++#define SEC_TS_PLL_STAT8 (0xff634800 + (0x018 << 2)) ++#define P_TS_PLL_STAT8 (volatile uint32_t *)(0xff634800 + (0x018 << 2)) ++#define TS_PLL_STAT9 (0xff634800 + (0x019 << 2)) ++#define SEC_TS_PLL_STAT9 (0xff634800 + (0x019 << 2)) ++#define P_TS_PLL_STAT9 (volatile uint32_t *)(0xff634800 + (0x019 << 2)) ++//======================================================================== ++// Temp sensor DDR ++//======================================================================== ++// APB4_DECODER_NON_SECURE_BASE 32'hFF634C00 ++// APB4_DECODER_SECURE_BASE 32'hFF634C00 ++#define TS_DDR_CFG_REG1 (0xff634c00 + (0x001 << 2)) ++#define SEC_TS_DDR_CFG_REG1 (0xff634c00 + (0x001 << 2)) ++#define P_TS_DDR_CFG_REG1 (volatile uint32_t *)(0xff634c00 + (0x001 << 2)) ++#define TS_DDR_CFG_REG2 (0xff634c00 + (0x002 << 2)) ++#define SEC_TS_DDR_CFG_REG2 (0xff634c00 + (0x002 << 2)) ++#define P_TS_DDR_CFG_REG2 (volatile uint32_t *)(0xff634c00 + (0x002 << 2)) ++#define TS_DDR_CFG_REG3 (0xff634c00 + (0x003 << 2)) ++#define SEC_TS_DDR_CFG_REG3 (0xff634c00 + (0x003 << 2)) ++#define P_TS_DDR_CFG_REG3 (volatile uint32_t *)(0xff634c00 + (0x003 << 2)) ++#define TS_DDR_CFG_REG4 (0xff634c00 + (0x004 << 2)) ++#define SEC_TS_DDR_CFG_REG4 (0xff634c00 + (0x004 << 2)) ++#define P_TS_DDR_CFG_REG4 (volatile uint32_t *)(0xff634c00 + (0x004 << 2)) ++#define TS_DDR_CFG_REG5 (0xff634c00 + (0x005 << 2)) ++#define SEC_TS_DDR_CFG_REG5 (0xff634c00 + (0x005 << 2)) ++#define P_TS_DDR_CFG_REG5 (volatile uint32_t *)(0xff634c00 + (0x005 << 2)) ++#define TS_DDR_CFG_REG6 (0xff634c00 + (0x006 << 2)) ++#define SEC_TS_DDR_CFG_REG6 (0xff634c00 + (0x006 << 2)) ++#define P_TS_DDR_CFG_REG6 (volatile uint32_t *)(0xff634c00 + (0x006 << 2)) ++#define TS_DDR_CFG_REG7 (0xff634c00 + (0x007 << 2)) ++#define SEC_TS_DDR_CFG_REG7 (0xff634c00 + (0x007 << 2)) ++#define P_TS_DDR_CFG_REG7 (volatile uint32_t *)(0xff634c00 + (0x007 << 2)) ++#define TS_DDR_STAT0 (0xff634c00 + (0x010 << 2)) ++#define SEC_TS_DDR_STAT0 (0xff634c00 + (0x010 << 2)) ++#define P_TS_DDR_STAT0 (volatile uint32_t *)(0xff634c00 + (0x010 << 2)) ++#define TS_DDR_STAT1 (0xff634c00 + (0x011 << 2)) ++#define SEC_TS_DDR_STAT1 (0xff634c00 + (0x011 << 2)) ++#define P_TS_DDR_STAT1 (volatile uint32_t *)(0xff634c00 + (0x011 << 2)) ++#define TS_DDR_STAT2 (0xff634c00 + (0x012 << 2)) ++#define SEC_TS_DDR_STAT2 (0xff634c00 + (0x012 << 2)) ++#define P_TS_DDR_STAT2 (volatile uint32_t *)(0xff634c00 + (0x012 << 2)) ++#define TS_DDR_STAT3 (0xff634c00 + (0x013 << 2)) ++#define SEC_TS_DDR_STAT3 (0xff634c00 + (0x013 << 2)) ++#define P_TS_DDR_STAT3 (volatile uint32_t *)(0xff634c00 + (0x013 << 2)) ++#define TS_DDR_STAT4 (0xff634c00 + (0x014 << 2)) ++#define SEC_TS_DDR_STAT4 (0xff634c00 + (0x014 << 2)) ++#define P_TS_DDR_STAT4 (volatile uint32_t *)(0xff634c00 + (0x014 << 2)) ++#define TS_DDR_STAT5 (0xff634c00 + (0x015 << 2)) ++#define SEC_TS_DDR_STAT5 (0xff634c00 + (0x015 << 2)) ++#define P_TS_DDR_STAT5 (volatile uint32_t *)(0xff634c00 + (0x015 << 2)) ++#define TS_DDR_STAT6 (0xff634c00 + (0x016 << 2)) ++#define SEC_TS_DDR_STAT6 (0xff634c00 + (0x016 << 2)) ++#define P_TS_DDR_STAT6 (volatile uint32_t *)(0xff634c00 + (0x016 << 2)) ++#define TS_DDR_STAT7 (0xff634c00 + (0x017 << 2)) ++#define SEC_TS_DDR_STAT7 (0xff634c00 + (0x017 << 2)) ++#define P_TS_DDR_STAT7 (volatile uint32_t *)(0xff634c00 + (0x017 << 2)) ++#define TS_DDR_STAT8 (0xff634c00 + (0x018 << 2)) ++#define SEC_TS_DDR_STAT8 (0xff634c00 + (0x018 << 2)) ++#define P_TS_DDR_STAT8 (volatile uint32_t *)(0xff634c00 + (0x018 << 2)) ++#define TS_DDR_STAT9 (0xff634c00 + (0x019 << 2)) ++#define SEC_TS_DDR_STAT9 (0xff634c00 + (0x019 << 2)) ++#define P_TS_DDR_STAT9 (volatile uint32_t *)(0xff634c00 + (0x019 << 2)) ++//======================================================================== ++// Temp sensor GPU ++//======================================================================== ++// APB4_DECODER_NON_SECURE_BASE 32'hFF635000 ++// APB4_DECODER_SECURE_BASE 32'hFF635000 ++//`define TS_GPU_CFG_REG1 8'h01 ++//`define TS_GPU_CFG_REG2 8'h02 ++//`define TS_GPU_CFG_REG3 8'h03 ++//`define TS_GPU_CFG_REG4 8'h04 ++//`define TS_GPU_CFG_REG5 8'h05 ++//`define TS_GPU_CFG_REG6 8'h06 ++//`define TS_GPU_CFG_REG7 8'h07 ++//`define TS_GPU_STAT0 8'h10 ++//`define TS_GPU_STAT1 8'h11 ++//`define TS_GPU_STAT2 8'h12 ++//`define TS_GPU_STAT3 8'h13 ++//`define TS_GPU_STAT4 8'h14 ++//`define TS_GPU_STAT5 8'h15 ++//`define TS_GPU_STAT6 8'h16 ++//`define TS_GPU_STAT7 8'h17 ++//`define TS_GPU_STAT8 8'h18 ++//`define TS_GPU_STAT9 8'h19 ++//======================================================================== ++// RNG ++//======================================================================== ++// APB4_DECODER_NON_SECURE_BASE 32'hFF634000 ++// APB4_DECODER_SECURE_BASE 32'hFF634000 ++//======================================================================== ++// ACODEC ++//======================================================================== ++// APB4_DECODER_NON_SECURE_BASE 32'hFF632000 ++// APB4_DECODER_SECURE_BASE 32'hFF632000 ++#define ACODEC_0 (0xff632000 + (0x000 << 2)) ++#define SEC_ACODEC_0 (0xff632000 + (0x000 << 2)) ++#define P_ACODEC_0 (volatile uint32_t *)(0xff632000 + (0x000 << 2)) ++#define ACODEC_1 (0xff632000 + (0x001 << 2)) ++#define SEC_ACODEC_1 (0xff632000 + (0x001 << 2)) ++#define P_ACODEC_1 (volatile uint32_t *)(0xff632000 + (0x001 << 2)) ++#define ACODEC_2 (0xff632000 + (0x002 << 2)) ++#define SEC_ACODEC_2 (0xff632000 + (0x002 << 2)) ++#define P_ACODEC_2 (volatile uint32_t *)(0xff632000 + (0x002 << 2)) ++#define ACODEC_3 (0xff632000 + (0x003 << 2)) ++#define SEC_ACODEC_3 (0xff632000 + (0x003 << 2)) ++#define P_ACODEC_3 (volatile uint32_t *)(0xff632000 + (0x003 << 2)) ++#define ACODEC_4 (0xff632000 + (0x004 << 2)) ++#define SEC_ACODEC_4 (0xff632000 + (0x004 << 2)) ++#define P_ACODEC_4 (volatile uint32_t *)(0xff632000 + (0x004 << 2)) ++#define ACODEC_5 (0xff632000 + (0x005 << 2)) ++#define SEC_ACODEC_5 (0xff632000 + (0x005 << 2)) ++#define P_ACODEC_5 (volatile uint32_t *)(0xff632000 + (0x005 << 2)) ++#define ACODEC_6 (0xff632000 + (0x006 << 2)) ++#define SEC_ACODEC_6 (0xff632000 + (0x006 << 2)) ++#define P_ACODEC_6 (volatile uint32_t *)(0xff632000 + (0x006 << 2)) ++#define ACODEC_7 (0xff632000 + (0x007 << 2)) ++#define SEC_ACODEC_7 (0xff632000 + (0x007 << 2)) ++#define P_ACODEC_7 (volatile uint32_t *)(0xff632000 + (0x007 << 2)) ++//======================================================================== ++// AML USB PHY A ++//======================================================================== ++// APB4_DECODER_NON_SECURE_BASE 32'hFF636000 ++// APB4_DECODER_SECURE_BASE 32'hFF636000 ++#define AMLUSB_A0 (0xff636000 + (0x000 << 2)) ++#define SEC_AMLUSB_A0 (0xff636000 + (0x000 << 2)) ++#define P_AMLUSB_A0 (volatile uint32_t *)(0xff636000 + (0x000 << 2)) ++#define AMLUSB_A1 (0xff636000 + (0x001 << 2)) ++#define SEC_AMLUSB_A1 (0xff636000 + (0x001 << 2)) ++#define P_AMLUSB_A1 (volatile uint32_t *)(0xff636000 + (0x001 << 2)) ++#define AMLUSB_A2 (0xff636000 + (0x002 << 2)) ++#define SEC_AMLUSB_A2 (0xff636000 + (0x002 << 2)) ++#define P_AMLUSB_A2 (volatile uint32_t *)(0xff636000 + (0x002 << 2)) ++#define AMLUSB_A3 (0xff636000 + (0x003 << 2)) ++#define SEC_AMLUSB_A3 (0xff636000 + (0x003 << 2)) ++#define P_AMLUSB_A3 (volatile uint32_t *)(0xff636000 + (0x003 << 2)) ++#define AMLUSB_A4 (0xff636000 + (0x004 << 2)) ++#define SEC_AMLUSB_A4 (0xff636000 + (0x004 << 2)) ++#define P_AMLUSB_A4 (volatile uint32_t *)(0xff636000 + (0x004 << 2)) ++#define AMLUSB_A5 (0xff636000 + (0x005 << 2)) ++#define SEC_AMLUSB_A5 (0xff636000 + (0x005 << 2)) ++#define P_AMLUSB_A5 (volatile uint32_t *)(0xff636000 + (0x005 << 2)) ++#define AMLUSB_A6 (0xff636000 + (0x006 << 2)) ++#define SEC_AMLUSB_A6 (0xff636000 + (0x006 << 2)) ++#define P_AMLUSB_A6 (volatile uint32_t *)(0xff636000 + (0x006 << 2)) ++#define AMLUSB_A7 (0xff636000 + (0x007 << 2)) ++#define SEC_AMLUSB_A7 (0xff636000 + (0x007 << 2)) ++#define P_AMLUSB_A7 (volatile uint32_t *)(0xff636000 + (0x007 << 2)) ++#define AMLUSB_A8 (0xff636000 + (0x008 << 2)) ++#define SEC_AMLUSB_A8 (0xff636000 + (0x008 << 2)) ++#define P_AMLUSB_A8 (volatile uint32_t *)(0xff636000 + (0x008 << 2)) ++#define AMLUSB_A9 (0xff636000 + (0x009 << 2)) ++#define SEC_AMLUSB_A9 (0xff636000 + (0x009 << 2)) ++#define P_AMLUSB_A9 (volatile uint32_t *)(0xff636000 + (0x009 << 2)) ++#define AMLUSB_A10 (0xff636000 + (0x00a << 2)) ++#define SEC_AMLUSB_A10 (0xff636000 + (0x00a << 2)) ++#define P_AMLUSB_A10 (volatile uint32_t *)(0xff636000 + (0x00a << 2)) ++#define AMLUSB_A11 (0xff636000 + (0x00b << 2)) ++#define SEC_AMLUSB_A11 (0xff636000 + (0x00b << 2)) ++#define P_AMLUSB_A11 (volatile uint32_t *)(0xff636000 + (0x00b << 2)) ++#define AMLUSB_A12 (0xff636000 + (0x00c << 2)) ++#define SEC_AMLUSB_A12 (0xff636000 + (0x00c << 2)) ++#define P_AMLUSB_A12 (volatile uint32_t *)(0xff636000 + (0x00c << 2)) ++#define AMLUSB_A13 (0xff636000 + (0x00d << 2)) ++#define SEC_AMLUSB_A13 (0xff636000 + (0x00d << 2)) ++#define P_AMLUSB_A13 (volatile uint32_t *)(0xff636000 + (0x00d << 2)) ++#define AMLUSB_A14 (0xff636000 + (0x00e << 2)) ++#define SEC_AMLUSB_A14 (0xff636000 + (0x00e << 2)) ++#define P_AMLUSB_A14 (volatile uint32_t *)(0xff636000 + (0x00e << 2)) ++#define AMLUSB_A15 (0xff636000 + (0x00f << 2)) ++#define SEC_AMLUSB_A15 (0xff636000 + (0x00f << 2)) ++#define P_AMLUSB_A15 (volatile uint32_t *)(0xff636000 + (0x00f << 2)) ++#define AMLUSB_A16 (0xff636000 + (0x010 << 2)) ++#define SEC_AMLUSB_A16 (0xff636000 + (0x010 << 2)) ++#define P_AMLUSB_A16 (volatile uint32_t *)(0xff636000 + (0x010 << 2)) ++#define AMLUSB_A17 (0xff636000 + (0x011 << 2)) ++#define SEC_AMLUSB_A17 (0xff636000 + (0x011 << 2)) ++#define P_AMLUSB_A17 (volatile uint32_t *)(0xff636000 + (0x011 << 2)) ++#define AMLUSB_A18 (0xff636000 + (0x012 << 2)) ++#define SEC_AMLUSB_A18 (0xff636000 + (0x012 << 2)) ++#define P_AMLUSB_A18 (volatile uint32_t *)(0xff636000 + (0x012 << 2)) ++#define AMLUSB_A19 (0xff636000 + (0x013 << 2)) ++#define SEC_AMLUSB_A19 (0xff636000 + (0x013 << 2)) ++#define P_AMLUSB_A19 (volatile uint32_t *)(0xff636000 + (0x013 << 2)) ++#define AMLUSB_A20 (0xff636000 + (0x014 << 2)) ++#define SEC_AMLUSB_A20 (0xff636000 + (0x014 << 2)) ++#define P_AMLUSB_A20 (volatile uint32_t *)(0xff636000 + (0x014 << 2)) ++#define AMLUSB_A21 (0xff636000 + (0x015 << 2)) ++#define SEC_AMLUSB_A21 (0xff636000 + (0x015 << 2)) ++#define P_AMLUSB_A21 (volatile uint32_t *)(0xff636000 + (0x015 << 2)) ++#define AMLUSB_A22 (0xff636000 + (0x016 << 2)) ++#define SEC_AMLUSB_A22 (0xff636000 + (0x016 << 2)) ++#define P_AMLUSB_A22 (volatile uint32_t *)(0xff636000 + (0x016 << 2)) ++#define AMLUSB_A23 (0xff636000 + (0x017 << 2)) ++#define SEC_AMLUSB_A23 (0xff636000 + (0x017 << 2)) ++#define P_AMLUSB_A23 (volatile uint32_t *)(0xff636000 + (0x017 << 2)) ++#define AMLUSB_A24 (0xff636000 + (0x018 << 2)) ++#define SEC_AMLUSB_A24 (0xff636000 + (0x018 << 2)) ++#define P_AMLUSB_A24 (volatile uint32_t *)(0xff636000 + (0x018 << 2)) ++#define AMLUSB_A25 (0xff636000 + (0x019 << 2)) ++#define SEC_AMLUSB_A25 (0xff636000 + (0x019 << 2)) ++#define P_AMLUSB_A25 (volatile uint32_t *)(0xff636000 + (0x019 << 2)) ++#define AMLUSB_A26 (0xff636000 + (0x01a << 2)) ++#define SEC_AMLUSB_A26 (0xff636000 + (0x01a << 2)) ++#define P_AMLUSB_A26 (volatile uint32_t *)(0xff636000 + (0x01a << 2)) ++#define AMLUSB_A27 (0xff636000 + (0x01b << 2)) ++#define SEC_AMLUSB_A27 (0xff636000 + (0x01b << 2)) ++#define P_AMLUSB_A27 (volatile uint32_t *)(0xff636000 + (0x01b << 2)) ++#define AMLUSB_A28 (0xff636000 + (0x01c << 2)) ++#define SEC_AMLUSB_A28 (0xff636000 + (0x01c << 2)) ++#define P_AMLUSB_A28 (volatile uint32_t *)(0xff636000 + (0x01c << 2)) ++#define AMLUSB_A29 (0xff636000 + (0x01d << 2)) ++#define SEC_AMLUSB_A29 (0xff636000 + (0x01d << 2)) ++#define P_AMLUSB_A29 (volatile uint32_t *)(0xff636000 + (0x01d << 2)) ++#define AMLUSB_A30 (0xff636000 + (0x01e << 2)) ++#define SEC_AMLUSB_A30 (0xff636000 + (0x01e << 2)) ++#define P_AMLUSB_A30 (volatile uint32_t *)(0xff636000 + (0x01e << 2)) ++#define AMLUSB_A31 (0xff636000 + (0x01f << 2)) ++#define SEC_AMLUSB_A31 (0xff636000 + (0x01f << 2)) ++#define P_AMLUSB_A31 (volatile uint32_t *)(0xff636000 + (0x01f << 2)) ++//======================================================================== ++// AML USB PHY B ++//======================================================================== ++// APB4_DECODER_NON_SECURE_BASE 32'hFF63A000 ++// APB4_DECODER_SECURE_BASE 32'hFF63A000 ++#define AMLUSB_B0 (0xff63a000 + (0x000 << 2)) ++#define SEC_AMLUSB_B0 (0xff63a000 + (0x000 << 2)) ++#define P_AMLUSB_B0 (volatile uint32_t *)(0xff63a000 + (0x000 << 2)) ++#define AMLUSB_B1 (0xff63a000 + (0x001 << 2)) ++#define SEC_AMLUSB_B1 (0xff63a000 + (0x001 << 2)) ++#define P_AMLUSB_B1 (volatile uint32_t *)(0xff63a000 + (0x001 << 2)) ++#define AMLUSB_B2 (0xff63a000 + (0x002 << 2)) ++#define SEC_AMLUSB_B2 (0xff63a000 + (0x002 << 2)) ++#define P_AMLUSB_B2 (volatile uint32_t *)(0xff63a000 + (0x002 << 2)) ++#define AMLUSB_B3 (0xff63a000 + (0x003 << 2)) ++#define SEC_AMLUSB_B3 (0xff63a000 + (0x003 << 2)) ++#define P_AMLUSB_B3 (volatile uint32_t *)(0xff63a000 + (0x003 << 2)) ++#define AMLUSB_B4 (0xff63a000 + (0x004 << 2)) ++#define SEC_AMLUSB_B4 (0xff63a000 + (0x004 << 2)) ++#define P_AMLUSB_B4 (volatile uint32_t *)(0xff63a000 + (0x004 << 2)) ++#define AMLUSB_B5 (0xff63a000 + (0x005 << 2)) ++#define SEC_AMLUSB_B5 (0xff63a000 + (0x005 << 2)) ++#define P_AMLUSB_B5 (volatile uint32_t *)(0xff63a000 + (0x005 << 2)) ++#define AMLUSB_B6 (0xff63a000 + (0x006 << 2)) ++#define SEC_AMLUSB_B6 (0xff63a000 + (0x006 << 2)) ++#define P_AMLUSB_B6 (volatile uint32_t *)(0xff63a000 + (0x006 << 2)) ++#define AMLUSB_B7 (0xff63a000 + (0x007 << 2)) ++#define SEC_AMLUSB_B7 (0xff63a000 + (0x007 << 2)) ++#define P_AMLUSB_B7 (volatile uint32_t *)(0xff63a000 + (0x007 << 2)) ++#define AMLUSB_B8 (0xff63a000 + (0x008 << 2)) ++#define SEC_AMLUSB_B8 (0xff63a000 + (0x008 << 2)) ++#define P_AMLUSB_B8 (volatile uint32_t *)(0xff63a000 + (0x008 << 2)) ++#define AMLUSB_B9 (0xff63a000 + (0x009 << 2)) ++#define SEC_AMLUSB_B9 (0xff63a000 + (0x009 << 2)) ++#define P_AMLUSB_B9 (volatile uint32_t *)(0xff63a000 + (0x009 << 2)) ++#define AMLUSB_B10 (0xff63a000 + (0x00a << 2)) ++#define SEC_AMLUSB_B10 (0xff63a000 + (0x00a << 2)) ++#define P_AMLUSB_B10 (volatile uint32_t *)(0xff63a000 + (0x00a << 2)) ++#define AMLUSB_B11 (0xff63a000 + (0x00b << 2)) ++#define SEC_AMLUSB_B11 (0xff63a000 + (0x00b << 2)) ++#define P_AMLUSB_B11 (volatile uint32_t *)(0xff63a000 + (0x00b << 2)) ++#define AMLUSB_B12 (0xff63a000 + (0x00c << 2)) ++#define SEC_AMLUSB_B12 (0xff63a000 + (0x00c << 2)) ++#define P_AMLUSB_B12 (volatile uint32_t *)(0xff63a000 + (0x00c << 2)) ++#define AMLUSB_B13 (0xff63a000 + (0x00d << 2)) ++#define SEC_AMLUSB_B13 (0xff63a000 + (0x00d << 2)) ++#define P_AMLUSB_B13 (volatile uint32_t *)(0xff63a000 + (0x00d << 2)) ++#define AMLUSB_B14 (0xff63a000 + (0x00e << 2)) ++#define SEC_AMLUSB_B14 (0xff63a000 + (0x00e << 2)) ++#define P_AMLUSB_B14 (volatile uint32_t *)(0xff63a000 + (0x00e << 2)) ++#define AMLUSB_B15 (0xff63a000 + (0x00f << 2)) ++#define SEC_AMLUSB_B15 (0xff63a000 + (0x00f << 2)) ++#define P_AMLUSB_B15 (volatile uint32_t *)(0xff63a000 + (0x00f << 2)) ++#define AMLUSB_B16 (0xff63a000 + (0x010 << 2)) ++#define SEC_AMLUSB_B16 (0xff63a000 + (0x010 << 2)) ++#define P_AMLUSB_B16 (volatile uint32_t *)(0xff63a000 + (0x010 << 2)) ++#define AMLUSB_B17 (0xff63a000 + (0x011 << 2)) ++#define SEC_AMLUSB_B17 (0xff63a000 + (0x011 << 2)) ++#define P_AMLUSB_B17 (volatile uint32_t *)(0xff63a000 + (0x011 << 2)) ++#define AMLUSB_B18 (0xff63a000 + (0x012 << 2)) ++#define SEC_AMLUSB_B18 (0xff63a000 + (0x012 << 2)) ++#define P_AMLUSB_B18 (volatile uint32_t *)(0xff63a000 + (0x012 << 2)) ++#define AMLUSB_B19 (0xff63a000 + (0x013 << 2)) ++#define SEC_AMLUSB_B19 (0xff63a000 + (0x013 << 2)) ++#define P_AMLUSB_B19 (volatile uint32_t *)(0xff63a000 + (0x013 << 2)) ++#define AMLUSB_B20 (0xff63a000 + (0x014 << 2)) ++#define SEC_AMLUSB_B20 (0xff63a000 + (0x014 << 2)) ++#define P_AMLUSB_B20 (volatile uint32_t *)(0xff63a000 + (0x014 << 2)) ++#define AMLUSB_B21 (0xff63a000 + (0x015 << 2)) ++#define SEC_AMLUSB_B21 (0xff63a000 + (0x015 << 2)) ++#define P_AMLUSB_B21 (volatile uint32_t *)(0xff63a000 + (0x015 << 2)) ++#define AMLUSB_B22 (0xff63a000 + (0x016 << 2)) ++#define SEC_AMLUSB_B22 (0xff63a000 + (0x016 << 2)) ++#define P_AMLUSB_B22 (volatile uint32_t *)(0xff63a000 + (0x016 << 2)) ++#define AMLUSB_B23 (0xff63a000 + (0x017 << 2)) ++#define SEC_AMLUSB_B23 (0xff63a000 + (0x017 << 2)) ++#define P_AMLUSB_B23 (volatile uint32_t *)(0xff63a000 + (0x017 << 2)) ++#define AMLUSB_B24 (0xff63a000 + (0x018 << 2)) ++#define SEC_AMLUSB_B24 (0xff63a000 + (0x018 << 2)) ++#define P_AMLUSB_B24 (volatile uint32_t *)(0xff63a000 + (0x018 << 2)) ++#define AMLUSB_B25 (0xff63a000 + (0x019 << 2)) ++#define SEC_AMLUSB_B25 (0xff63a000 + (0x019 << 2)) ++#define P_AMLUSB_B25 (volatile uint32_t *)(0xff63a000 + (0x019 << 2)) ++#define AMLUSB_B26 (0xff63a000 + (0x01a << 2)) ++#define SEC_AMLUSB_B26 (0xff63a000 + (0x01a << 2)) ++#define P_AMLUSB_B26 (volatile uint32_t *)(0xff63a000 + (0x01a << 2)) ++#define AMLUSB_B27 (0xff63a000 + (0x01b << 2)) ++#define SEC_AMLUSB_B27 (0xff63a000 + (0x01b << 2)) ++#define P_AMLUSB_B27 (volatile uint32_t *)(0xff63a000 + (0x01b << 2)) ++#define AMLUSB_B28 (0xff63a000 + (0x01c << 2)) ++#define SEC_AMLUSB_B28 (0xff63a000 + (0x01c << 2)) ++#define P_AMLUSB_B28 (volatile uint32_t *)(0xff63a000 + (0x01c << 2)) ++#define AMLUSB_B29 (0xff63a000 + (0x01d << 2)) ++#define SEC_AMLUSB_B29 (0xff63a000 + (0x01d << 2)) ++#define P_AMLUSB_B29 (volatile uint32_t *)(0xff63a000 + (0x01d << 2)) ++#define AMLUSB_B30 (0xff63a000 + (0x01e << 2)) ++#define SEC_AMLUSB_B30 (0xff63a000 + (0x01e << 2)) ++#define P_AMLUSB_B30 (volatile uint32_t *)(0xff63a000 + (0x01e << 2)) ++#define AMLUSB_B31 (0xff63a000 + (0x01f << 2)) ++#define SEC_AMLUSB_B31 (0xff63a000 + (0x01f << 2)) ++#define P_AMLUSB_B31 (volatile uint32_t *)(0xff63a000 + (0x01f << 2)) ++//======================================================================== ++// PERIPHS ++//======================================================================== ++// APB4_DECODER_NON_SECURE_BASE 32'hFF634400 ++// APB4_DECODER_SECURE_BASE 32'hFF634400 ++// The following are handled by $periphs/rtl/periphs_reg.v ++//`define PREG_CTLREG0_ADDR 8'h00 ++// ---------------------------- ++// ---------------------------- ++//`define PREG_JTAG_GPIO_ADDR 8'h0b // DWORD base address (0xc120002c >> 2) ++// ---------------------------- ++// Pre-defined GPIO addresses ++// ---------------------------- ++#define PREG_PAD_GPIO0_EN_N (0xff634400 + (0x010 << 2)) ++#define SEC_PREG_PAD_GPIO0_EN_N (0xff634400 + (0x010 << 2)) ++#define P_PREG_PAD_GPIO0_EN_N (volatile uint32_t *)(0xff634400 + (0x010 << 2)) ++#define PREG_PAD_GPIO0_O (0xff634400 + (0x011 << 2)) ++#define SEC_PREG_PAD_GPIO0_O (0xff634400 + (0x011 << 2)) ++#define P_PREG_PAD_GPIO0_O (volatile uint32_t *)(0xff634400 + (0x011 << 2)) ++#define PREG_PAD_GPIO0_I (0xff634400 + (0x012 << 2)) ++#define SEC_PREG_PAD_GPIO0_I (0xff634400 + (0x012 << 2)) ++#define P_PREG_PAD_GPIO0_I (volatile uint32_t *)(0xff634400 + (0x012 << 2)) ++// ---------------------------- ++#define PREG_PAD_GPIO1_EN_N (0xff634400 + (0x013 << 2)) ++#define SEC_PREG_PAD_GPIO1_EN_N (0xff634400 + (0x013 << 2)) ++#define P_PREG_PAD_GPIO1_EN_N (volatile uint32_t *)(0xff634400 + (0x013 << 2)) ++#define PREG_PAD_GPIO1_O (0xff634400 + (0x014 << 2)) ++#define SEC_PREG_PAD_GPIO1_O (0xff634400 + (0x014 << 2)) ++#define P_PREG_PAD_GPIO1_O (volatile uint32_t *)(0xff634400 + (0x014 << 2)) ++#define PREG_PAD_GPIO1_I (0xff634400 + (0x015 << 2)) ++#define SEC_PREG_PAD_GPIO1_I (0xff634400 + (0x015 << 2)) ++#define P_PREG_PAD_GPIO1_I (volatile uint32_t *)(0xff634400 + (0x015 << 2)) ++// ---------------------------- ++#define PREG_PAD_GPIO2_EN_N (0xff634400 + (0x016 << 2)) ++#define SEC_PREG_PAD_GPIO2_EN_N (0xff634400 + (0x016 << 2)) ++#define P_PREG_PAD_GPIO2_EN_N (volatile uint32_t *)(0xff634400 + (0x016 << 2)) ++#define PREG_PAD_GPIO2_O (0xff634400 + (0x017 << 2)) ++#define SEC_PREG_PAD_GPIO2_O (0xff634400 + (0x017 << 2)) ++#define P_PREG_PAD_GPIO2_O (volatile uint32_t *)(0xff634400 + (0x017 << 2)) ++#define PREG_PAD_GPIO2_I (0xff634400 + (0x018 << 2)) ++#define SEC_PREG_PAD_GPIO2_I (0xff634400 + (0x018 << 2)) ++#define P_PREG_PAD_GPIO2_I (volatile uint32_t *)(0xff634400 + (0x018 << 2)) ++// ---------------------------- ++#define PREG_PAD_GPIO3_EN_N (0xff634400 + (0x019 << 2)) ++#define SEC_PREG_PAD_GPIO3_EN_N (0xff634400 + (0x019 << 2)) ++#define P_PREG_PAD_GPIO3_EN_N (volatile uint32_t *)(0xff634400 + (0x019 << 2)) ++#define PREG_PAD_GPIO3_O (0xff634400 + (0x01a << 2)) ++#define SEC_PREG_PAD_GPIO3_O (0xff634400 + (0x01a << 2)) ++#define P_PREG_PAD_GPIO3_O (volatile uint32_t *)(0xff634400 + (0x01a << 2)) ++#define PREG_PAD_GPIO3_I (0xff634400 + (0x01b << 2)) ++#define SEC_PREG_PAD_GPIO3_I (0xff634400 + (0x01b << 2)) ++#define P_PREG_PAD_GPIO3_I (volatile uint32_t *)(0xff634400 + (0x01b << 2)) ++// ---------------------------- ++#define PREG_PAD_GPIO4_EN_N (0xff634400 + (0x01c << 2)) ++#define SEC_PREG_PAD_GPIO4_EN_N (0xff634400 + (0x01c << 2)) ++#define P_PREG_PAD_GPIO4_EN_N (volatile uint32_t *)(0xff634400 + (0x01c << 2)) ++#define PREG_PAD_GPIO4_O (0xff634400 + (0x01d << 2)) ++#define SEC_PREG_PAD_GPIO4_O (0xff634400 + (0x01d << 2)) ++#define P_PREG_PAD_GPIO4_O (volatile uint32_t *)(0xff634400 + (0x01d << 2)) ++#define PREG_PAD_GPIO4_I (0xff634400 + (0x01e << 2)) ++#define SEC_PREG_PAD_GPIO4_I (0xff634400 + (0x01e << 2)) ++#define P_PREG_PAD_GPIO4_I (volatile uint32_t *)(0xff634400 + (0x01e << 2)) ++// ---------------------------- ++#define PREG_PAD_GPIO5_EN_N (0xff634400 + (0x020 << 2)) ++#define SEC_PREG_PAD_GPIO5_EN_N (0xff634400 + (0x020 << 2)) ++#define P_PREG_PAD_GPIO5_EN_N (volatile uint32_t *)(0xff634400 + (0x020 << 2)) ++#define PREG_PAD_GPIO5_O (0xff634400 + (0x021 << 2)) ++#define SEC_PREG_PAD_GPIO5_O (0xff634400 + (0x021 << 2)) ++#define P_PREG_PAD_GPIO5_O (volatile uint32_t *)(0xff634400 + (0x021 << 2)) ++#define PREG_PAD_GPIO5_I (0xff634400 + (0x022 << 2)) ++#define SEC_PREG_PAD_GPIO5_I (0xff634400 + (0x022 << 2)) ++#define P_PREG_PAD_GPIO5_I (volatile uint32_t *)(0xff634400 + (0x022 << 2)) ++// ---------------------------- ++// ---------------------------- ++// Pad conntrols ++// ---------------------------- ++//`define PAD_PULL_UP_REG6 8'h39 ++#define PAD_PULL_UP_REG0 (0xff634400 + (0x03a << 2)) ++#define SEC_PAD_PULL_UP_REG0 (0xff634400 + (0x03a << 2)) ++#define P_PAD_PULL_UP_REG0 (volatile uint32_t *)(0xff634400 + (0x03a << 2)) ++#define PAD_PULL_UP_REG1 (0xff634400 + (0x03b << 2)) ++#define SEC_PAD_PULL_UP_REG1 (0xff634400 + (0x03b << 2)) ++#define P_PAD_PULL_UP_REG1 (volatile uint32_t *)(0xff634400 + (0x03b << 2)) ++#define PAD_PULL_UP_REG2 (0xff634400 + (0x03c << 2)) ++#define SEC_PAD_PULL_UP_REG2 (0xff634400 + (0x03c << 2)) ++#define P_PAD_PULL_UP_REG2 (volatile uint32_t *)(0xff634400 + (0x03c << 2)) ++#define PAD_PULL_UP_REG3 (0xff634400 + (0x03d << 2)) ++#define SEC_PAD_PULL_UP_REG3 (0xff634400 + (0x03d << 2)) ++#define P_PAD_PULL_UP_REG3 (volatile uint32_t *)(0xff634400 + (0x03d << 2)) ++#define PAD_PULL_UP_REG4 (0xff634400 + (0x03e << 2)) ++#define SEC_PAD_PULL_UP_REG4 (0xff634400 + (0x03e << 2)) ++#define P_PAD_PULL_UP_REG4 (volatile uint32_t *)(0xff634400 + (0x03e << 2)) ++#define PAD_PULL_UP_REG5 (0xff634400 + (0x03f << 2)) ++#define SEC_PAD_PULL_UP_REG5 (0xff634400 + (0x03f << 2)) ++#define P_PAD_PULL_UP_REG5 (volatile uint32_t *)(0xff634400 + (0x03f << 2)) ++// ---------------------------- ++// Random (2) ++// ---------------------------- ++//`define RAND64_ADDR0 8'h40 // DWORD base address (0xc1200138 >> 2) ++//`define RAND64_ADDR1 8'h41 // DWORD base address (0xc120013c >> 2) ++// --------------------------- ++// Ethernet (1) ++// ---------------------------- ++//`define PREG_ETHERNET_ADDR0 8'h42 // DWORD base address (0xc1200290 >> 2) ++// --------------------------- ++// AM_ANALOG_TOP ++// ---------------------------- ++//`define PREG_AM_ANALOG_ADDR 8'h43 // DWORD base address (0xc1200298 >> 2) ++// --------------------------- ++// Mali55 (1) ++// ---------------------------- ++//`define PREG_MALI_BYTE_CNTL 8'h44 ++// --------------------------- ++// WIFI (1) ++// ---------------------------- ++//`define PREG_WIFI_CNTL 8'h45 ++#define PAD_PULL_UP_EN_REG0 (0xff634400 + (0x048 << 2)) ++#define SEC_PAD_PULL_UP_EN_REG0 (0xff634400 + (0x048 << 2)) ++#define P_PAD_PULL_UP_EN_REG0 (volatile uint32_t *)(0xff634400 + (0x048 << 2)) ++#define PAD_PULL_UP_EN_REG1 (0xff634400 + (0x049 << 2)) ++#define SEC_PAD_PULL_UP_EN_REG1 (0xff634400 + (0x049 << 2)) ++#define P_PAD_PULL_UP_EN_REG1 (volatile uint32_t *)(0xff634400 + (0x049 << 2)) ++#define PAD_PULL_UP_EN_REG2 (0xff634400 + (0x04a << 2)) ++#define SEC_PAD_PULL_UP_EN_REG2 (0xff634400 + (0x04a << 2)) ++#define P_PAD_PULL_UP_EN_REG2 (volatile uint32_t *)(0xff634400 + (0x04a << 2)) ++#define PAD_PULL_UP_EN_REG3 (0xff634400 + (0x04b << 2)) ++#define SEC_PAD_PULL_UP_EN_REG3 (0xff634400 + (0x04b << 2)) ++#define P_PAD_PULL_UP_EN_REG3 (volatile uint32_t *)(0xff634400 + (0x04b << 2)) ++#define PAD_PULL_UP_EN_REG4 (0xff634400 + (0x04c << 2)) ++#define SEC_PAD_PULL_UP_EN_REG4 (0xff634400 + (0x04c << 2)) ++#define P_PAD_PULL_UP_EN_REG4 (volatile uint32_t *)(0xff634400 + (0x04c << 2)) ++#define PAD_PULL_UP_EN_REG5 (0xff634400 + (0x04d << 2)) ++#define SEC_PAD_PULL_UP_EN_REG5 (0xff634400 + (0x04d << 2)) ++#define P_PAD_PULL_UP_EN_REG5 (volatile uint32_t *)(0xff634400 + (0x04d << 2)) ++//`define PAD_PULL_UP_EN_REG6 8'h4e ++// --------------------------- ++#define PREG_ETH_REG0 (0xff634400 + (0x050 << 2)) ++#define SEC_PREG_ETH_REG0 (0xff634400 + (0x050 << 2)) ++#define P_PREG_ETH_REG0 (volatile uint32_t *)(0xff634400 + (0x050 << 2)) ++#define PREG_ETH_REG1 (0xff634400 + (0x051 << 2)) ++#define SEC_PREG_ETH_REG1 (0xff634400 + (0x051 << 2)) ++#define P_PREG_ETH_REG1 (volatile uint32_t *)(0xff634400 + (0x051 << 2)) ++#define PREG_NAND_CFG_KEY0 (0xff634400 + (0x052 << 2)) ++#define SEC_PREG_NAND_CFG_KEY0 (0xff634400 + (0x052 << 2)) ++#define P_PREG_NAND_CFG_KEY0 (volatile uint32_t *)(0xff634400 + (0x052 << 2)) ++#define PREG_NAND_CFG_KEY1 (0xff634400 + (0x053 << 2)) ++#define SEC_PREG_NAND_CFG_KEY1 (0xff634400 + (0x053 << 2)) ++#define P_PREG_NAND_CFG_KEY1 (volatile uint32_t *)(0xff634400 + (0x053 << 2)) ++#define PREG_VPU_SECURE0 (0xff634400 + (0x054 << 2)) ++#define SEC_PREG_VPU_SECURE0 (0xff634400 + (0x054 << 2)) ++#define P_PREG_VPU_SECURE0 (volatile uint32_t *)(0xff634400 + (0x054 << 2)) ++#define PREG_VPU_SECURE1 (0xff634400 + (0x055 << 2)) ++#define SEC_PREG_VPU_SECURE1 (0xff634400 + (0x055 << 2)) ++#define P_PREG_VPU_SECURE1 (volatile uint32_t *)(0xff634400 + (0x055 << 2)) ++#define PREG_ETH_REG2 (0xff634400 + (0x056 << 2)) ++#define SEC_PREG_ETH_REG2 (0xff634400 + (0x056 << 2)) ++#define P_PREG_ETH_REG2 (volatile uint32_t *)(0xff634400 + (0x056 << 2)) ++#define PREG_ETH_REG3 (0xff634400 + (0x057 << 2)) ++#define SEC_PREG_ETH_REG3 (0xff634400 + (0x057 << 2)) ++#define P_PREG_ETH_REG3 (volatile uint32_t *)(0xff634400 + (0x057 << 2)) ++#define PREG_ETH_REG4 (0xff634400 + (0x058 << 2)) ++#define SEC_PREG_ETH_REG4 (0xff634400 + (0x058 << 2)) ++#define P_PREG_ETH_REG4 (volatile uint32_t *)(0xff634400 + (0x058 << 2)) ++// --------------------------- ++// Generic production test ++// ---------------------------- ++#define PROD_TEST_REG0 (0xff634400 + (0x060 << 2)) ++#define SEC_PROD_TEST_REG0 (0xff634400 + (0x060 << 2)) ++#define P_PROD_TEST_REG0 (volatile uint32_t *)(0xff634400 + (0x060 << 2)) ++#define PROD_TEST_REG1 (0xff634400 + (0x061 << 2)) ++#define SEC_PROD_TEST_REG1 (0xff634400 + (0x061 << 2)) ++#define P_PROD_TEST_REG1 (volatile uint32_t *)(0xff634400 + (0x061 << 2)) ++#define PROD_TEST_REG2 (0xff634400 + (0x062 << 2)) ++#define SEC_PROD_TEST_REG2 (0xff634400 + (0x062 << 2)) ++#define P_PROD_TEST_REG2 (volatile uint32_t *)(0xff634400 + (0x062 << 2)) ++#define PROD_TEST_REG3 (0xff634400 + (0x063 << 2)) ++#define SEC_PROD_TEST_REG3 (0xff634400 + (0x063 << 2)) ++#define P_PROD_TEST_REG3 (volatile uint32_t *)(0xff634400 + (0x063 << 2)) ++// am_analog_top ++// ---------------------------- ++//`define METAL_REVISION 8'h6a ++//`define ADC_TOP_MISC 8'h6b ++//`define DPLL_TOP_MISC 8'h6c ++//`define ANALOG_TOP_MISC 8'h6d ++//`define AM_ANALOG_TOP_REG0 8'h6e ++//`define AM_ANALOG_TOP_REG1 8'h6f ++// --------------------------- ++// Sticky regs ++// ---------------------------- ++#define PREG_STICKY_REG0 (0xff634400 + (0x070 << 2)) ++#define SEC_PREG_STICKY_REG0 (0xff634400 + (0x070 << 2)) ++#define P_PREG_STICKY_REG0 (volatile uint32_t *)(0xff634400 + (0x070 << 2)) ++#define PREG_STICKY_REG1 (0xff634400 + (0x071 << 2)) ++#define SEC_PREG_STICKY_REG1 (0xff634400 + (0x071 << 2)) ++#define P_PREG_STICKY_REG1 (volatile uint32_t *)(0xff634400 + (0x071 << 2)) ++#define PREG_STICKY_REG2 (0xff634400 + (0x072 << 2)) ++#define SEC_PREG_STICKY_REG2 (0xff634400 + (0x072 << 2)) ++#define P_PREG_STICKY_REG2 (volatile uint32_t *)(0xff634400 + (0x072 << 2)) ++#define PREG_STICKY_REG3 (0xff634400 + (0x073 << 2)) ++#define SEC_PREG_STICKY_REG3 (0xff634400 + (0x073 << 2)) ++#define P_PREG_STICKY_REG3 (volatile uint32_t *)(0xff634400 + (0x073 << 2)) ++#define PREG_STICKY_REG4 (0xff634400 + (0x074 << 2)) ++#define SEC_PREG_STICKY_REG4 (0xff634400 + (0x074 << 2)) ++#define P_PREG_STICKY_REG4 (volatile uint32_t *)(0xff634400 + (0x074 << 2)) ++#define PREG_STICKY_REG5 (0xff634400 + (0x075 << 2)) ++#define SEC_PREG_STICKY_REG5 (0xff634400 + (0x075 << 2)) ++#define P_PREG_STICKY_REG5 (volatile uint32_t *)(0xff634400 + (0x075 << 2)) ++#define PREG_STICKY_REG6 (0xff634400 + (0x076 << 2)) ++#define SEC_PREG_STICKY_REG6 (0xff634400 + (0x076 << 2)) ++#define P_PREG_STICKY_REG6 (volatile uint32_t *)(0xff634400 + (0x076 << 2)) ++#define PREG_STICKY_REG7 (0xff634400 + (0x077 << 2)) ++#define SEC_PREG_STICKY_REG7 (0xff634400 + (0x077 << 2)) ++#define P_PREG_STICKY_REG7 (volatile uint32_t *)(0xff634400 + (0x077 << 2)) ++#define PREG_STICKY_REG8 (0xff634400 + (0x078 << 2)) ++#define SEC_PREG_STICKY_REG8 (0xff634400 + (0x078 << 2)) ++#define P_PREG_STICKY_REG8 (volatile uint32_t *)(0xff634400 + (0x078 << 2)) ++#define PREG_STICKY_REG9 (0xff634400 + (0x079 << 2)) ++#define SEC_PREG_STICKY_REG9 (0xff634400 + (0x079 << 2)) ++#define P_PREG_STICKY_REG9 (volatile uint32_t *)(0xff634400 + (0x079 << 2)) ++//`define PREG_WRITE_ONCE_REG 8'h7e ++// --------------------------- ++// AM Ring Oscillator ++// ---------------------------- ++#define AM_RING_OSC_REG0 (0xff634400 + (0x07f << 2)) ++#define SEC_AM_RING_OSC_REG0 (0xff634400 + (0x07f << 2)) ++#define P_AM_RING_OSC_REG0 (volatile uint32_t *)(0xff634400 + (0x07f << 2)) ++// Control whether to provide random number to HDMITX20 ++//`define HDMITX20_RNDNUM 8'h80 ++// --------------------------- ++// Bus Monitoring ++// ---------------------------- ++#define BUS_MONITOR_CNTL (0xff634400 + (0x081 << 2)) ++#define SEC_BUS_MONITOR_CNTL (0xff634400 + (0x081 << 2)) ++#define P_BUS_MONITOR_CNTL (volatile uint32_t *)(0xff634400 + (0x081 << 2)) ++#define BUS_MON0_ADDR (0xff634400 + (0x082 << 2)) ++#define SEC_BUS_MON0_ADDR (0xff634400 + (0x082 << 2)) ++#define P_BUS_MON0_ADDR (volatile uint32_t *)(0xff634400 + (0x082 << 2)) ++#define BUS_MON0_DATA (0xff634400 + (0x083 << 2)) ++#define SEC_BUS_MON0_DATA (0xff634400 + (0x083 << 2)) ++#define P_BUS_MON0_DATA (volatile uint32_t *)(0xff634400 + (0x083 << 2)) ++#define BUS_MON0_DATA_MSK (0xff634400 + (0x084 << 2)) ++#define SEC_BUS_MON0_DATA_MSK (0xff634400 + (0x084 << 2)) ++#define P_BUS_MON0_DATA_MSK (volatile uint32_t *)(0xff634400 + (0x084 << 2)) ++#define BUS_MON1_ADDR (0xff634400 + (0x085 << 2)) ++#define SEC_BUS_MON1_ADDR (0xff634400 + (0x085 << 2)) ++#define P_BUS_MON1_ADDR (volatile uint32_t *)(0xff634400 + (0x085 << 2)) ++#define BUS_MON1_DATA (0xff634400 + (0x086 << 2)) ++#define SEC_BUS_MON1_DATA (0xff634400 + (0x086 << 2)) ++#define P_BUS_MON1_DATA (volatile uint32_t *)(0xff634400 + (0x086 << 2)) ++#define BUS_MON1_DATA_MSK (0xff634400 + (0x087 << 2)) ++#define SEC_BUS_MON1_DATA_MSK (0xff634400 + (0x087 << 2)) ++#define P_BUS_MON1_DATA_MSK (volatile uint32_t *)(0xff634400 + (0x087 << 2)) ++#define ASYNC_FIFO_LOCK_ADR (0xff634400 + (0x088 << 2)) ++#define SEC_ASYNC_FIFO_LOCK_ADR (0xff634400 + (0x088 << 2)) ++#define P_ASYNC_FIFO_LOCK_ADR (volatile uint32_t *)(0xff634400 + (0x088 << 2)) ++#define SECE_TIMER_CTRL (0xff634400 + (0x089 << 2)) ++#define SEC_SECE_TIMER_CTRL (0xff634400 + (0x089 << 2)) ++#define P_SECE_TIMER_CTRL (volatile uint32_t *)(0xff634400 + (0x089 << 2)) ++#define SECE_TIMER_LOW (0xff634400 + (0x08a << 2)) ++#define SEC_SECE_TIMER_LOW (0xff634400 + (0x08a << 2)) ++#define P_SECE_TIMER_LOW (volatile uint32_t *)(0xff634400 + (0x08a << 2)) ++#define SECE_TIMER_HIG (0xff634400 + (0x08b << 2)) ++#define SEC_SECE_TIMER_HIG (0xff634400 + (0x08b << 2)) ++#define P_SECE_TIMER_HIG (volatile uint32_t *)(0xff634400 + (0x08b << 2)) ++// --------------------------- ++// System CPU control registers ++// ---------------------------- ++#define SYS_CPU_POR_CFG0 (0xff634400 + (0x090 << 2)) ++#define SEC_SYS_CPU_POR_CFG0 (0xff634400 + (0x090 << 2)) ++#define P_SYS_CPU_POR_CFG0 (volatile uint32_t *)(0xff634400 + (0x090 << 2)) ++#define SYS_CPU_POR_CFG1 (0xff634400 + (0x091 << 2)) ++#define SEC_SYS_CPU_POR_CFG1 (0xff634400 + (0x091 << 2)) ++#define P_SYS_CPU_POR_CFG1 (volatile uint32_t *)(0xff634400 + (0x091 << 2)) ++#define SYS_CPU_CFG0 (0xff634400 + (0x092 << 2)) ++#define SEC_SYS_CPU_CFG0 (0xff634400 + (0x092 << 2)) ++#define P_SYS_CPU_CFG0 (volatile uint32_t *)(0xff634400 + (0x092 << 2)) ++#define SYS_CPU_CFG1 (0xff634400 + (0x093 << 2)) ++#define SEC_SYS_CPU_CFG1 (0xff634400 + (0x093 << 2)) ++#define P_SYS_CPU_CFG1 (volatile uint32_t *)(0xff634400 + (0x093 << 2)) ++#define SYS_CPU_CFG2 (0xff634400 + (0x094 << 2)) ++#define SEC_SYS_CPU_CFG2 (0xff634400 + (0x094 << 2)) ++#define P_SYS_CPU_CFG2 (volatile uint32_t *)(0xff634400 + (0x094 << 2)) ++#define SYS_CPU_CFG3 (0xff634400 + (0x095 << 2)) ++#define SEC_SYS_CPU_CFG3 (0xff634400 + (0x095 << 2)) ++#define P_SYS_CPU_CFG3 (volatile uint32_t *)(0xff634400 + (0x095 << 2)) ++#define SYS_CPU_CFG4 (0xff634400 + (0x096 << 2)) ++#define SEC_SYS_CPU_CFG4 (0xff634400 + (0x096 << 2)) ++#define P_SYS_CPU_CFG4 (volatile uint32_t *)(0xff634400 + (0x096 << 2)) ++#define SYS_CPU_CFG5 (0xff634400 + (0x097 << 2)) ++#define SEC_SYS_CPU_CFG5 (0xff634400 + (0x097 << 2)) ++#define P_SYS_CPU_CFG5 (volatile uint32_t *)(0xff634400 + (0x097 << 2)) ++#define SYS_CPU_CFG6 (0xff634400 + (0x098 << 2)) ++#define SEC_SYS_CPU_CFG6 (0xff634400 + (0x098 << 2)) ++#define P_SYS_CPU_CFG6 (volatile uint32_t *)(0xff634400 + (0x098 << 2)) ++#define SYS_CPU_CFG7 (0xff634400 + (0x099 << 2)) ++#define SEC_SYS_CPU_CFG7 (0xff634400 + (0x099 << 2)) ++#define P_SYS_CPU_CFG7 (volatile uint32_t *)(0xff634400 + (0x099 << 2)) ++#define SYS_CPU_CFG8 (0xff634400 + (0x09a << 2)) ++#define SEC_SYS_CPU_CFG8 (0xff634400 + (0x09a << 2)) ++#define P_SYS_CPU_CFG8 (volatile uint32_t *)(0xff634400 + (0x09a << 2)) ++#define SYS_CPU_CFG9 (0xff634400 + (0x09b << 2)) ++#define SEC_SYS_CPU_CFG9 (0xff634400 + (0x09b << 2)) ++#define P_SYS_CPU_CFG9 (volatile uint32_t *)(0xff634400 + (0x09b << 2)) ++#define SYS_CPU_CFG10 (0xff634400 + (0x09c << 2)) ++#define SEC_SYS_CPU_CFG10 (0xff634400 + (0x09c << 2)) ++#define P_SYS_CPU_CFG10 (volatile uint32_t *)(0xff634400 + (0x09c << 2)) ++//`define SYS_CPU_CFG11 8'h9d ++//`define SYS_CPU_CFG12 8'h9e ++//`define SYS_CPU_CFG13 8'h9f ++#define SYS_CPU_STATUS0 (0xff634400 + (0x0a0 << 2)) ++#define SEC_SYS_CPU_STATUS0 (0xff634400 + (0x0a0 << 2)) ++#define P_SYS_CPU_STATUS0 (volatile uint32_t *)(0xff634400 + (0x0a0 << 2)) ++#define SYS_CPU_STATUS1 (0xff634400 + (0x0a1 << 2)) ++#define SEC_SYS_CPU_STATUS1 (0xff634400 + (0x0a1 << 2)) ++#define P_SYS_CPU_STATUS1 (volatile uint32_t *)(0xff634400 + (0x0a1 << 2)) ++#define SYS_CPU_STATUS2 (0xff634400 + (0x0a2 << 2)) ++#define SEC_SYS_CPU_STATUS2 (0xff634400 + (0x0a2 << 2)) ++#define P_SYS_CPU_STATUS2 (volatile uint32_t *)(0xff634400 + (0x0a2 << 2)) ++#define SYS_CPU_STATUS3 (0xff634400 + (0x0a3 << 2)) ++#define SEC_SYS_CPU_STATUS3 (0xff634400 + (0x0a3 << 2)) ++#define P_SYS_CPU_STATUS3 (volatile uint32_t *)(0xff634400 + (0x0a3 << 2)) ++#define SYS_CPU_STATUS4 (0xff634400 + (0x0a4 << 2)) ++#define SEC_SYS_CPU_STATUS4 (0xff634400 + (0x0a4 << 2)) ++#define P_SYS_CPU_STATUS4 (volatile uint32_t *)(0xff634400 + (0x0a4 << 2)) ++#define SYS_CPU_STATUS5 (0xff634400 + (0x0a5 << 2)) ++#define SEC_SYS_CPU_STATUS5 (0xff634400 + (0x0a5 << 2)) ++#define P_SYS_CPU_STATUS5 (volatile uint32_t *)(0xff634400 + (0x0a5 << 2)) ++#define SYS_CPU_MISC (0xff634400 + (0x0a8 << 2)) ++#define SEC_SYS_CPU_MISC (0xff634400 + (0x0a8 << 2)) ++#define P_SYS_CPU_MISC (volatile uint32_t *)(0xff634400 + (0x0a8 << 2)) ++// ---------------------------- ++// Pin Mux (9) ++// ---------------------------- ++#define PERIPHS_LOCK_PAD (0xff634400 + (0x0ae << 2)) ++#define SEC_PERIPHS_LOCK_PAD (0xff634400 + (0x0ae << 2)) ++#define P_PERIPHS_LOCK_PAD (volatile uint32_t *)(0xff634400 + (0x0ae << 2)) ++#define PERIPHS_LOCK_PIN_MUX (0xff634400 + (0x0af << 2)) ++#define SEC_PERIPHS_LOCK_PIN_MUX (0xff634400 + (0x0af << 2)) ++#define P_PERIPHS_LOCK_PIN_MUX (volatile uint32_t *)(0xff634400 + (0x0af << 2)) ++#define PERIPHS_PIN_MUX_0 (0xff634400 + (0x0b0 << 2)) ++#define SEC_PERIPHS_PIN_MUX_0 (0xff634400 + (0x0b0 << 2)) ++#define P_PERIPHS_PIN_MUX_0 (volatile uint32_t *)(0xff634400 + (0x0b0 << 2)) ++#define PERIPHS_PIN_MUX_1 (0xff634400 + (0x0b1 << 2)) ++#define SEC_PERIPHS_PIN_MUX_1 (0xff634400 + (0x0b1 << 2)) ++#define P_PERIPHS_PIN_MUX_1 (volatile uint32_t *)(0xff634400 + (0x0b1 << 2)) ++#define PERIPHS_PIN_MUX_2 (0xff634400 + (0x0b2 << 2)) ++#define SEC_PERIPHS_PIN_MUX_2 (0xff634400 + (0x0b2 << 2)) ++#define P_PERIPHS_PIN_MUX_2 (volatile uint32_t *)(0xff634400 + (0x0b2 << 2)) ++#define PERIPHS_PIN_MUX_3 (0xff634400 + (0x0b3 << 2)) ++#define SEC_PERIPHS_PIN_MUX_3 (0xff634400 + (0x0b3 << 2)) ++#define P_PERIPHS_PIN_MUX_3 (volatile uint32_t *)(0xff634400 + (0x0b3 << 2)) ++#define PERIPHS_PIN_MUX_4 (0xff634400 + (0x0b4 << 2)) ++#define SEC_PERIPHS_PIN_MUX_4 (0xff634400 + (0x0b4 << 2)) ++#define P_PERIPHS_PIN_MUX_4 (volatile uint32_t *)(0xff634400 + (0x0b4 << 2)) ++#define PERIPHS_PIN_MUX_5 (0xff634400 + (0x0b5 << 2)) ++#define SEC_PERIPHS_PIN_MUX_5 (0xff634400 + (0x0b5 << 2)) ++#define P_PERIPHS_PIN_MUX_5 (volatile uint32_t *)(0xff634400 + (0x0b5 << 2)) ++#define PERIPHS_PIN_MUX_6 (0xff634400 + (0x0b6 << 2)) ++#define SEC_PERIPHS_PIN_MUX_6 (0xff634400 + (0x0b6 << 2)) ++#define P_PERIPHS_PIN_MUX_6 (volatile uint32_t *)(0xff634400 + (0x0b6 << 2)) ++#define PERIPHS_PIN_MUX_7 (0xff634400 + (0x0b7 << 2)) ++#define SEC_PERIPHS_PIN_MUX_7 (0xff634400 + (0x0b7 << 2)) ++#define P_PERIPHS_PIN_MUX_7 (volatile uint32_t *)(0xff634400 + (0x0b7 << 2)) ++#define PERIPHS_PIN_MUX_8 (0xff634400 + (0x0b8 << 2)) ++#define SEC_PERIPHS_PIN_MUX_8 (0xff634400 + (0x0b8 << 2)) ++#define P_PERIPHS_PIN_MUX_8 (volatile uint32_t *)(0xff634400 + (0x0b8 << 2)) ++#define PERIPHS_PIN_MUX_9 (0xff634400 + (0x0b9 << 2)) ++#define SEC_PERIPHS_PIN_MUX_9 (0xff634400 + (0x0b9 << 2)) ++#define P_PERIPHS_PIN_MUX_9 (volatile uint32_t *)(0xff634400 + (0x0b9 << 2)) ++#define PERIPHS_PIN_MUX_A (0xff634400 + (0x0ba << 2)) ++#define SEC_PERIPHS_PIN_MUX_A (0xff634400 + (0x0ba << 2)) ++#define P_PERIPHS_PIN_MUX_A (volatile uint32_t *)(0xff634400 + (0x0ba << 2)) ++#define PERIPHS_PIN_MUX_B (0xff634400 + (0x0bb << 2)) ++#define SEC_PERIPHS_PIN_MUX_B (0xff634400 + (0x0bb << 2)) ++#define P_PERIPHS_PIN_MUX_B (volatile uint32_t *)(0xff634400 + (0x0bb << 2)) ++#define PERIPHS_PIN_MUX_C (0xff634400 + (0x0bc << 2)) ++#define SEC_PERIPHS_PIN_MUX_C (0xff634400 + (0x0bc << 2)) ++#define P_PERIPHS_PIN_MUX_C (volatile uint32_t *)(0xff634400 + (0x0bc << 2)) ++#define PERIPHS_PIN_MUX_D (0xff634400 + (0x0bd << 2)) ++#define SEC_PERIPHS_PIN_MUX_D (0xff634400 + (0x0bd << 2)) ++#define P_PERIPHS_PIN_MUX_D (volatile uint32_t *)(0xff634400 + (0x0bd << 2)) ++#define PERIPHS_PIN_MUX_E (0xff634400 + (0x0be << 2)) ++#define SEC_PERIPHS_PIN_MUX_E (0xff634400 + (0x0be << 2)) ++#define P_PERIPHS_PIN_MUX_E (volatile uint32_t *)(0xff634400 + (0x0be << 2)) ++#define PERIPHS_PIN_MUX_F (0xff634400 + (0x0bf << 2)) ++#define SEC_PERIPHS_PIN_MUX_F (0xff634400 + (0x0bf << 2)) ++#define P_PERIPHS_PIN_MUX_F (volatile uint32_t *)(0xff634400 + (0x0bf << 2)) ++#define EFUSE_CFG_LOCK (0xff634400 + (0x0c0 << 2)) ++#define SEC_EFUSE_CFG_LOCK (0xff634400 + (0x0c0 << 2)) ++#define P_EFUSE_CFG_LOCK (volatile uint32_t *)(0xff634400 + (0x0c0 << 2)) ++#define EFUSE_CLK_A53_CFG01 (0xff634400 + (0x0c1 << 2)) ++#define SEC_EFUSE_CLK_A53_CFG01 (0xff634400 + (0x0c1 << 2)) ++#define P_EFUSE_CLK_A53_CFG01 (volatile uint32_t *)(0xff634400 + (0x0c1 << 2)) ++#define EFUSE_CLK_A53_CFG2 (0xff634400 + (0x0c2 << 2)) ++#define SEC_EFUSE_CLK_A53_CFG2 (0xff634400 + (0x0c2 << 2)) ++#define P_EFUSE_CLK_A53_CFG2 (volatile uint32_t *)(0xff634400 + (0x0c2 << 2)) ++#define EFUSE_CLK_ENCP_CFG0 (0xff634400 + (0x0c3 << 2)) ++#define SEC_EFUSE_CLK_ENCP_CFG0 (0xff634400 + (0x0c3 << 2)) ++#define P_EFUSE_CLK_ENCP_CFG0 (volatile uint32_t *)(0xff634400 + (0x0c3 << 2)) ++#define EFUSE_CLK_MALI_CFG0 (0xff634400 + (0x0c4 << 2)) ++#define SEC_EFUSE_CLK_MALI_CFG0 (0xff634400 + (0x0c4 << 2)) ++#define P_EFUSE_CLK_MALI_CFG0 (volatile uint32_t *)(0xff634400 + (0x0c4 << 2)) ++#define EFUSE_CLK_HEVCB_CFG0 (0xff634400 + (0x0c5 << 2)) ++#define SEC_EFUSE_CLK_HEVCB_CFG0 (0xff634400 + (0x0c5 << 2)) ++#define P_EFUSE_CLK_HEVCB_CFG0 (volatile uint32_t *)(0xff634400 + (0x0c5 << 2)) ++#define PAD_DS_REG0A (0xff634400 + (0x0d0 << 2)) ++#define SEC_PAD_DS_REG0A (0xff634400 + (0x0d0 << 2)) ++#define P_PAD_DS_REG0A (volatile uint32_t *)(0xff634400 + (0x0d0 << 2)) ++#define PAD_DS_REG1A (0xff634400 + (0x0d1 << 2)) ++#define SEC_PAD_DS_REG1A (0xff634400 + (0x0d1 << 2)) ++#define P_PAD_DS_REG1A (volatile uint32_t *)(0xff634400 + (0x0d1 << 2)) ++#define PAD_DS_REG2A (0xff634400 + (0x0d2 << 2)) ++#define SEC_PAD_DS_REG2A (0xff634400 + (0x0d2 << 2)) ++#define P_PAD_DS_REG2A (volatile uint32_t *)(0xff634400 + (0x0d2 << 2)) ++#define PAD_DS_REG2B (0xff634400 + (0x0d3 << 2)) ++#define SEC_PAD_DS_REG2B (0xff634400 + (0x0d3 << 2)) ++#define P_PAD_DS_REG2B (volatile uint32_t *)(0xff634400 + (0x0d3 << 2)) ++#define PAD_DS_REG3A (0xff634400 + (0x0d4 << 2)) ++#define SEC_PAD_DS_REG3A (0xff634400 + (0x0d4 << 2)) ++#define P_PAD_DS_REG3A (volatile uint32_t *)(0xff634400 + (0x0d4 << 2)) ++#define PAD_DS_REG4A (0xff634400 + (0x0d5 << 2)) ++#define SEC_PAD_DS_REG4A (0xff634400 + (0x0d5 << 2)) ++#define P_PAD_DS_REG4A (volatile uint32_t *)(0xff634400 + (0x0d5 << 2)) ++#define PAD_DS_REG5A (0xff634400 + (0x0d6 << 2)) ++#define SEC_PAD_DS_REG5A (0xff634400 + (0x0d6 << 2)) ++#define P_PAD_DS_REG5A (volatile uint32_t *)(0xff634400 + (0x0d6 << 2)) ++//======================================================================== ++// RESET_SEC - Registers ++//======================================================================== ++// APB4_DECODER_NON_SECURE_BASE 32'hFF64E000 ++// APB4_DECODER_SECURE_BASE 32'hFF64E000 ++#define RESET0_SEC_REGISTER (0xff64e000 + (0x000 << 2)) ++#define SEC_RESET0_SEC_REGISTER (0xff64e000 + (0x000 << 2)) ++#define P_RESET0_SEC_REGISTER (volatile uint32_t *)(0xff64e000 + (0x000 << 2)) ++#define RESET1_SEC_REGISTER (0xff64e000 + (0x001 << 2)) ++#define SEC_RESET1_SEC_REGISTER (0xff64e000 + (0x001 << 2)) ++#define P_RESET1_SEC_REGISTER (volatile uint32_t *)(0xff64e000 + (0x001 << 2)) ++#define RESET2_SEC_REGISTER (0xff64e000 + (0x002 << 2)) ++#define SEC_RESET2_SEC_REGISTER (0xff64e000 + (0x002 << 2)) ++#define P_RESET2_SEC_REGISTER (volatile uint32_t *)(0xff64e000 + (0x002 << 2)) ++#define RESET0_SEC_LEVEL (0xff64e000 + (0x010 << 2)) ++#define SEC_RESET0_SEC_LEVEL (0xff64e000 + (0x010 << 2)) ++#define P_RESET0_SEC_LEVEL (volatile uint32_t *)(0xff64e000 + (0x010 << 2)) ++#define RESET1_SEC_LEVEL (0xff64e000 + (0x011 << 2)) ++#define SEC_RESET1_SEC_LEVEL (0xff64e000 + (0x011 << 2)) ++#define P_RESET1_SEC_LEVEL (volatile uint32_t *)(0xff64e000 + (0x011 << 2)) ++#define RESET2_SEC_LEVEL (0xff64e000 + (0x012 << 2)) ++#define SEC_RESET2_SEC_LEVEL (0xff64e000 + (0x012 << 2)) ++#define P_RESET2_SEC_LEVEL (volatile uint32_t *)(0xff64e000 + (0x012 << 2)) ++#define RESET0_SEC_MASK (0xff64e000 + (0x020 << 2)) ++#define SEC_RESET0_SEC_MASK (0xff64e000 + (0x020 << 2)) ++#define P_RESET0_SEC_MASK (volatile uint32_t *)(0xff64e000 + (0x020 << 2)) ++#define RESET1_SEC_MASK (0xff64e000 + (0x021 << 2)) ++#define SEC_RESET1_SEC_MASK (0xff64e000 + (0x021 << 2)) ++#define P_RESET1_SEC_MASK (volatile uint32_t *)(0xff64e000 + (0x021 << 2)) ++#define RESET2_SEC_MASK (0xff64e000 + (0x022 << 2)) ++#define SEC_RESET2_SEC_MASK (0xff64e000 + (0x022 << 2)) ++#define P_RESET2_SEC_MASK (volatile uint32_t *)(0xff64e000 + (0x022 << 2)) ++//======================================================================== ++// AUDIO locker - Registers ++//======================================================================== ++// APB4_DECODER_NON_SECURE_BASE 32'hFF64a000 ++// APB4_DECODER_SECURE_BASE 32'hFF64a000 ++#define AUD_LOCK_EN (0xff64a000 + (0x000 << 2)) ++#define SEC_AUD_LOCK_EN (0xff64a000 + (0x000 << 2)) ++#define P_AUD_LOCK_EN (volatile uint32_t *)(0xff64a000 + (0x000 << 2)) ++#define AUD_LOCK_SW_RESET (0xff64a000 + (0x001 << 2)) ++#define SEC_AUD_LOCK_SW_RESET (0xff64a000 + (0x001 << 2)) ++#define P_AUD_LOCK_SW_RESET (volatile uint32_t *)(0xff64a000 + (0x001 << 2)) ++#define AUD_LOCK_SW_LATCH (0xff64a000 + (0x002 << 2)) ++#define SEC_AUD_LOCK_SW_LATCH (0xff64a000 + (0x002 << 2)) ++#define P_AUD_LOCK_SW_LATCH (volatile uint32_t *)(0xff64a000 + (0x002 << 2)) ++#define AUD_LOCK_HW_LATCH (0xff64a000 + (0x003 << 2)) ++#define SEC_AUD_LOCK_HW_LATCH (0xff64a000 + (0x003 << 2)) ++#define P_AUD_LOCK_HW_LATCH (volatile uint32_t *)(0xff64a000 + (0x003 << 2)) ++#define AUD_LOCK_REFCLK_SRC (0xff64a000 + (0x004 << 2)) ++#define SEC_AUD_LOCK_REFCLK_SRC (0xff64a000 + (0x004 << 2)) ++#define P_AUD_LOCK_REFCLK_SRC (volatile uint32_t *)(0xff64a000 + (0x004 << 2)) ++#define AUD_LOCK_REFCLK_LAT_INT (0xff64a000 + (0x005 << 2)) ++#define SEC_AUD_LOCK_REFCLK_LAT_INT (0xff64a000 + (0x005 << 2)) ++#define P_AUD_LOCK_REFCLK_LAT_INT (volatile uint32_t *)(0xff64a000 + (0x005 << 2)) ++#define AUD_LOCK_IMCLK_LAT_INT (0xff64a000 + (0x006 << 2)) ++#define SEC_AUD_LOCK_IMCLK_LAT_INT (0xff64a000 + (0x006 << 2)) ++#define P_AUD_LOCK_IMCLK_LAT_INT (volatile uint32_t *)(0xff64a000 + (0x006 << 2)) ++#define AUD_LOCK_OMCLK_LAT_INT (0xff64a000 + (0x007 << 2)) ++#define SEC_AUD_LOCK_OMCLK_LAT_INT (0xff64a000 + (0x007 << 2)) ++#define P_AUD_LOCK_OMCLK_LAT_INT (volatile uint32_t *)(0xff64a000 + (0x007 << 2)) ++#define AUD_LOCK_REFCLK_DS_INT (0xff64a000 + (0x008 << 2)) ++#define SEC_AUD_LOCK_REFCLK_DS_INT (0xff64a000 + (0x008 << 2)) ++#define P_AUD_LOCK_REFCLK_DS_INT (volatile uint32_t *)(0xff64a000 + (0x008 << 2)) ++#define AUD_LOCK_IMCLK_DS_INT (0xff64a000 + (0x009 << 2)) ++#define SEC_AUD_LOCK_IMCLK_DS_INT (0xff64a000 + (0x009 << 2)) ++#define P_AUD_LOCK_IMCLK_DS_INT (volatile uint32_t *)(0xff64a000 + (0x009 << 2)) ++#define AUD_LOCK_OMCLK_DS_INT (0xff64a000 + (0x00a << 2)) ++#define SEC_AUD_LOCK_OMCLK_DS_INT (0xff64a000 + (0x00a << 2)) ++#define P_AUD_LOCK_OMCLK_DS_INT (volatile uint32_t *)(0xff64a000 + (0x00a << 2)) ++#define AUD_LOCK_INT_CLR (0xff64a000 + (0x00b << 2)) ++#define SEC_AUD_LOCK_INT_CLR (0xff64a000 + (0x00b << 2)) ++#define P_AUD_LOCK_INT_CLR (volatile uint32_t *)(0xff64a000 + (0x00b << 2)) ++#define AUD_LOCK_GCLK_CTRL (0xff64a000 + (0x00c << 2)) ++#define SEC_AUD_LOCK_GCLK_CTRL (0xff64a000 + (0x00c << 2)) ++#define P_AUD_LOCK_GCLK_CTRL (volatile uint32_t *)(0xff64a000 + (0x00c << 2)) ++#define AUD_LOCK_INT_CTRL (0xff64a000 + (0x00d << 2)) ++#define SEC_AUD_LOCK_INT_CTRL (0xff64a000 + (0x00d << 2)) ++#define P_AUD_LOCK_INT_CTRL (volatile uint32_t *)(0xff64a000 + (0x00d << 2)) ++#define RO_REF2IMCLK_CNT_L (0xff64a000 + (0x010 << 2)) ++#define SEC_RO_REF2IMCLK_CNT_L (0xff64a000 + (0x010 << 2)) ++#define P_RO_REF2IMCLK_CNT_L (volatile uint32_t *)(0xff64a000 + (0x010 << 2)) ++#define RO_REF2IMCLK_CNT_H (0xff64a000 + (0x011 << 2)) ++#define SEC_RO_REF2IMCLK_CNT_H (0xff64a000 + (0x011 << 2)) ++#define P_RO_REF2IMCLK_CNT_H (volatile uint32_t *)(0xff64a000 + (0x011 << 2)) ++#define RO_REF2OMCLK_CNT_L (0xff64a000 + (0x012 << 2)) ++#define SEC_RO_REF2OMCLK_CNT_L (0xff64a000 + (0x012 << 2)) ++#define P_RO_REF2OMCLK_CNT_L (volatile uint32_t *)(0xff64a000 + (0x012 << 2)) ++#define RO_REF2OMCLK_CNT_H (0xff64a000 + (0x013 << 2)) ++#define SEC_RO_REF2OMCLK_CNT_H (0xff64a000 + (0x013 << 2)) ++#define P_RO_REF2OMCLK_CNT_H (volatile uint32_t *)(0xff64a000 + (0x013 << 2)) ++#define RO_IMCLK2REF_CNT_L (0xff64a000 + (0x014 << 2)) ++#define SEC_RO_IMCLK2REF_CNT_L (0xff64a000 + (0x014 << 2)) ++#define P_RO_IMCLK2REF_CNT_L (volatile uint32_t *)(0xff64a000 + (0x014 << 2)) ++#define RO_IMCLK2REF_CNT_H (0xff64a000 + (0x015 << 2)) ++#define SEC_RO_IMCLK2REF_CNT_H (0xff64a000 + (0x015 << 2)) ++#define P_RO_IMCLK2REF_CNT_H (volatile uint32_t *)(0xff64a000 + (0x015 << 2)) ++#define RO_OMCLK2REF_CNT_L (0xff64a000 + (0x016 << 2)) ++#define SEC_RO_OMCLK2REF_CNT_L (0xff64a000 + (0x016 << 2)) ++#define P_RO_OMCLK2REF_CNT_L (volatile uint32_t *)(0xff64a000 + (0x016 << 2)) ++#define RO_OMCLK2REF_CNT_H (0xff64a000 + (0x017 << 2)) ++#define SEC_RO_OMCLK2REF_CNT_H (0xff64a000 + (0x017 << 2)) ++#define P_RO_OMCLK2REF_CNT_H (volatile uint32_t *)(0xff64a000 + (0x017 << 2)) ++#define RO_REFCLK_PKG_CNT (0xff64a000 + (0x018 << 2)) ++#define SEC_RO_REFCLK_PKG_CNT (0xff64a000 + (0x018 << 2)) ++#define P_RO_REFCLK_PKG_CNT (volatile uint32_t *)(0xff64a000 + (0x018 << 2)) ++#define RO_IMCLK_PKG_CNT (0xff64a000 + (0x019 << 2)) ++#define SEC_RO_IMCLK_PKG_CNT (0xff64a000 + (0x019 << 2)) ++#define P_RO_IMCLK_PKG_CNT (volatile uint32_t *)(0xff64a000 + (0x019 << 2)) ++#define RO_OMCLK_PKG_CNT (0xff64a000 + (0x01a << 2)) ++#define SEC_RO_OMCLK_PKG_CNT (0xff64a000 + (0x01a << 2)) ++#define P_RO_OMCLK_PKG_CNT (volatile uint32_t *)(0xff64a000 + (0x01a << 2)) ++#define RO_AUD_LOCK_INT_STATUS (0xff64a000 + (0x01b << 2)) ++#define SEC_RO_AUD_LOCK_INT_STATUS (0xff64a000 + (0x01b << 2)) ++#define P_RO_AUD_LOCK_INT_STATUS (volatile uint32_t *)(0xff64a000 + (0x01b << 2)) ++//======================================================================== ++// AUDIO - Registers ++//======================================================================== ++// APB4_DECODER_NON_SECURE_BASE 32'hFF642000 ++// APB4_DECODER_SECURE_BASE 32'hFF642000 ++#define EE_AUDIO_CLK_GATE_EN (0xff642000 + (0x000 << 2)) ++#define SEC_EE_AUDIO_CLK_GATE_EN (0xff642000 + (0x000 << 2)) ++#define P_EE_AUDIO_CLK_GATE_EN (volatile uint32_t *)(0xff642000 + (0x000 << 2)) ++#define EE_AUDIO_MCLK_A_CTRL (0xff642000 + (0x001 << 2)) ++#define SEC_EE_AUDIO_MCLK_A_CTRL (0xff642000 + (0x001 << 2)) ++#define P_EE_AUDIO_MCLK_A_CTRL (volatile uint32_t *)(0xff642000 + (0x001 << 2)) ++#define EE_AUDIO_MCLK_B_CTRL (0xff642000 + (0x002 << 2)) ++#define SEC_EE_AUDIO_MCLK_B_CTRL (0xff642000 + (0x002 << 2)) ++#define P_EE_AUDIO_MCLK_B_CTRL (volatile uint32_t *)(0xff642000 + (0x002 << 2)) ++#define EE_AUDIO_MCLK_C_CTRL (0xff642000 + (0x003 << 2)) ++#define SEC_EE_AUDIO_MCLK_C_CTRL (0xff642000 + (0x003 << 2)) ++#define P_EE_AUDIO_MCLK_C_CTRL (volatile uint32_t *)(0xff642000 + (0x003 << 2)) ++#define EE_AUDIO_MCLK_D_CTRL (0xff642000 + (0x004 << 2)) ++#define SEC_EE_AUDIO_MCLK_D_CTRL (0xff642000 + (0x004 << 2)) ++#define P_EE_AUDIO_MCLK_D_CTRL (volatile uint32_t *)(0xff642000 + (0x004 << 2)) ++#define EE_AUDIO_MCLK_E_CTRL (0xff642000 + (0x005 << 2)) ++#define SEC_EE_AUDIO_MCLK_E_CTRL (0xff642000 + (0x005 << 2)) ++#define P_EE_AUDIO_MCLK_E_CTRL (volatile uint32_t *)(0xff642000 + (0x005 << 2)) ++#define EE_AUDIO_MCLK_F_CTRL (0xff642000 + (0x006 << 2)) ++#define SEC_EE_AUDIO_MCLK_F_CTRL (0xff642000 + (0x006 << 2)) ++#define P_EE_AUDIO_MCLK_F_CTRL (volatile uint32_t *)(0xff642000 + (0x006 << 2)) ++#define EE_AUDIO_PAD_CTRL0 (0xff642000 + (0x007 << 2)) ++#define SEC_EE_AUDIO_PAD_CTRL0 (0xff642000 + (0x007 << 2)) ++#define P_EE_AUDIO_PAD_CTRL0 (volatile uint32_t *)(0xff642000 + (0x007 << 2)) ++#define EE_AUDIO_PAD_CTRL1 (0xff642000 + (0x008 << 2)) ++#define SEC_EE_AUDIO_PAD_CTRL1 (0xff642000 + (0x008 << 2)) ++#define P_EE_AUDIO_PAD_CTRL1 (volatile uint32_t *)(0xff642000 + (0x008 << 2)) ++#define EE_AUDIO_SW_RESET (0xff642000 + (0x009 << 2)) ++#define SEC_EE_AUDIO_SW_RESET (0xff642000 + (0x009 << 2)) ++#define P_EE_AUDIO_SW_RESET (volatile uint32_t *)(0xff642000 + (0x009 << 2)) ++#define EE_AUDIO_MST_A_SCLK_CTRL0 (0xff642000 + (0x010 << 2)) ++#define SEC_EE_AUDIO_MST_A_SCLK_CTRL0 (0xff642000 + (0x010 << 2)) ++#define P_EE_AUDIO_MST_A_SCLK_CTRL0 (volatile uint32_t *)(0xff642000 + (0x010 << 2)) ++#define EE_AUDIO_MST_A_SCLK_CTRL1 (0xff642000 + (0x011 << 2)) ++#define SEC_EE_AUDIO_MST_A_SCLK_CTRL1 (0xff642000 + (0x011 << 2)) ++#define P_EE_AUDIO_MST_A_SCLK_CTRL1 (volatile uint32_t *)(0xff642000 + (0x011 << 2)) ++#define EE_AUDIO_MST_B_SCLK_CTRL0 (0xff642000 + (0x012 << 2)) ++#define SEC_EE_AUDIO_MST_B_SCLK_CTRL0 (0xff642000 + (0x012 << 2)) ++#define P_EE_AUDIO_MST_B_SCLK_CTRL0 (volatile uint32_t *)(0xff642000 + (0x012 << 2)) ++#define EE_AUDIO_MST_B_SCLK_CTRL1 (0xff642000 + (0x013 << 2)) ++#define SEC_EE_AUDIO_MST_B_SCLK_CTRL1 (0xff642000 + (0x013 << 2)) ++#define P_EE_AUDIO_MST_B_SCLK_CTRL1 (volatile uint32_t *)(0xff642000 + (0x013 << 2)) ++#define EE_AUDIO_MST_C_SCLK_CTRL0 (0xff642000 + (0x014 << 2)) ++#define SEC_EE_AUDIO_MST_C_SCLK_CTRL0 (0xff642000 + (0x014 << 2)) ++#define P_EE_AUDIO_MST_C_SCLK_CTRL0 (volatile uint32_t *)(0xff642000 + (0x014 << 2)) ++#define EE_AUDIO_MST_C_SCLK_CTRL1 (0xff642000 + (0x015 << 2)) ++#define SEC_EE_AUDIO_MST_C_SCLK_CTRL1 (0xff642000 + (0x015 << 2)) ++#define P_EE_AUDIO_MST_C_SCLK_CTRL1 (volatile uint32_t *)(0xff642000 + (0x015 << 2)) ++#define EE_AUDIO_MST_D_SCLK_CTRL0 (0xff642000 + (0x016 << 2)) ++#define SEC_EE_AUDIO_MST_D_SCLK_CTRL0 (0xff642000 + (0x016 << 2)) ++#define P_EE_AUDIO_MST_D_SCLK_CTRL0 (volatile uint32_t *)(0xff642000 + (0x016 << 2)) ++#define EE_AUDIO_MST_D_SCLK_CTRL1 (0xff642000 + (0x017 << 2)) ++#define SEC_EE_AUDIO_MST_D_SCLK_CTRL1 (0xff642000 + (0x017 << 2)) ++#define P_EE_AUDIO_MST_D_SCLK_CTRL1 (volatile uint32_t *)(0xff642000 + (0x017 << 2)) ++#define EE_AUDIO_MST_E_SCLK_CTRL0 (0xff642000 + (0x018 << 2)) ++#define SEC_EE_AUDIO_MST_E_SCLK_CTRL0 (0xff642000 + (0x018 << 2)) ++#define P_EE_AUDIO_MST_E_SCLK_CTRL0 (volatile uint32_t *)(0xff642000 + (0x018 << 2)) ++#define EE_AUDIO_MST_E_SCLK_CTRL1 (0xff642000 + (0x019 << 2)) ++#define SEC_EE_AUDIO_MST_E_SCLK_CTRL1 (0xff642000 + (0x019 << 2)) ++#define P_EE_AUDIO_MST_E_SCLK_CTRL1 (volatile uint32_t *)(0xff642000 + (0x019 << 2)) ++#define EE_AUDIO_MST_F_SCLK_CTRL0 (0xff642000 + (0x01a << 2)) ++#define SEC_EE_AUDIO_MST_F_SCLK_CTRL0 (0xff642000 + (0x01a << 2)) ++#define P_EE_AUDIO_MST_F_SCLK_CTRL0 (volatile uint32_t *)(0xff642000 + (0x01a << 2)) ++#define EE_AUDIO_MST_F_SCLK_CTRL1 (0xff642000 + (0x01b << 2)) ++#define SEC_EE_AUDIO_MST_F_SCLK_CTRL1 (0xff642000 + (0x01b << 2)) ++#define P_EE_AUDIO_MST_F_SCLK_CTRL1 (volatile uint32_t *)(0xff642000 + (0x01b << 2)) ++#define EE_AUDIO_CLK_TDMIN_A_CTRL (0xff642000 + (0x020 << 2)) ++#define SEC_EE_AUDIO_CLK_TDMIN_A_CTRL (0xff642000 + (0x020 << 2)) ++#define P_EE_AUDIO_CLK_TDMIN_A_CTRL (volatile uint32_t *)(0xff642000 + (0x020 << 2)) ++#define EE_AUDIO_CLK_TDMIN_B_CTRL (0xff642000 + (0x021 << 2)) ++#define SEC_EE_AUDIO_CLK_TDMIN_B_CTRL (0xff642000 + (0x021 << 2)) ++#define P_EE_AUDIO_CLK_TDMIN_B_CTRL (volatile uint32_t *)(0xff642000 + (0x021 << 2)) ++#define EE_AUDIO_CLK_TDMIN_C_CTRL (0xff642000 + (0x022 << 2)) ++#define SEC_EE_AUDIO_CLK_TDMIN_C_CTRL (0xff642000 + (0x022 << 2)) ++#define P_EE_AUDIO_CLK_TDMIN_C_CTRL (volatile uint32_t *)(0xff642000 + (0x022 << 2)) ++#define EE_AUDIO_CLK_TDMIN_LB_CTRL (0xff642000 + (0x023 << 2)) ++#define SEC_EE_AUDIO_CLK_TDMIN_LB_CTRL (0xff642000 + (0x023 << 2)) ++#define P_EE_AUDIO_CLK_TDMIN_LB_CTRL (volatile uint32_t *)(0xff642000 + (0x023 << 2)) ++#define EE_AUDIO_CLK_TDMOUT_A_CTRL (0xff642000 + (0x024 << 2)) ++#define SEC_EE_AUDIO_CLK_TDMOUT_A_CTRL (0xff642000 + (0x024 << 2)) ++#define P_EE_AUDIO_CLK_TDMOUT_A_CTRL (volatile uint32_t *)(0xff642000 + (0x024 << 2)) ++#define EE_AUDIO_CLK_TDMOUT_B_CTRL (0xff642000 + (0x025 << 2)) ++#define SEC_EE_AUDIO_CLK_TDMOUT_B_CTRL (0xff642000 + (0x025 << 2)) ++#define P_EE_AUDIO_CLK_TDMOUT_B_CTRL (volatile uint32_t *)(0xff642000 + (0x025 << 2)) ++#define EE_AUDIO_CLK_TDMOUT_C_CTRL (0xff642000 + (0x026 << 2)) ++#define SEC_EE_AUDIO_CLK_TDMOUT_C_CTRL (0xff642000 + (0x026 << 2)) ++#define P_EE_AUDIO_CLK_TDMOUT_C_CTRL (volatile uint32_t *)(0xff642000 + (0x026 << 2)) ++#define EE_AUDIO_CLK_SPDIFIN_CTRL (0xff642000 + (0x027 << 2)) ++#define SEC_EE_AUDIO_CLK_SPDIFIN_CTRL (0xff642000 + (0x027 << 2)) ++#define P_EE_AUDIO_CLK_SPDIFIN_CTRL (volatile uint32_t *)(0xff642000 + (0x027 << 2)) ++#define EE_AUDIO_CLK_SPDIFOUT_CTRL (0xff642000 + (0x028 << 2)) ++#define SEC_EE_AUDIO_CLK_SPDIFOUT_CTRL (0xff642000 + (0x028 << 2)) ++#define P_EE_AUDIO_CLK_SPDIFOUT_CTRL (volatile uint32_t *)(0xff642000 + (0x028 << 2)) ++#define EE_AUDIO_CLK_RESAMPLE_CTRL (0xff642000 + (0x029 << 2)) ++#define SEC_EE_AUDIO_CLK_RESAMPLE_CTRL (0xff642000 + (0x029 << 2)) ++#define P_EE_AUDIO_CLK_RESAMPLE_CTRL (volatile uint32_t *)(0xff642000 + (0x029 << 2)) ++#define EE_AUDIO_CLK_LOCKER_CTRL (0xff642000 + (0x02a << 2)) ++#define SEC_EE_AUDIO_CLK_LOCKER_CTRL (0xff642000 + (0x02a << 2)) ++#define P_EE_AUDIO_CLK_LOCKER_CTRL (volatile uint32_t *)(0xff642000 + (0x02a << 2)) ++#define EE_AUDIO_CLK_PDMIN_CTRL0 (0xff642000 + (0x02b << 2)) ++#define SEC_EE_AUDIO_CLK_PDMIN_CTRL0 (0xff642000 + (0x02b << 2)) ++#define P_EE_AUDIO_CLK_PDMIN_CTRL0 (volatile uint32_t *)(0xff642000 + (0x02b << 2)) ++#define EE_AUDIO_CLK_PDMIN_CTRL1 (0xff642000 + (0x02c << 2)) ++#define SEC_EE_AUDIO_CLK_PDMIN_CTRL1 (0xff642000 + (0x02c << 2)) ++#define P_EE_AUDIO_CLK_PDMIN_CTRL1 (volatile uint32_t *)(0xff642000 + (0x02c << 2)) ++#define EE_AUDIO_CLK_SPDIFOUT_B_CTRL (0xff642000 + (0x02d << 2)) ++#define SEC_EE_AUDIO_CLK_SPDIFOUT_B_CTRL (0xff642000 + (0x02d << 2)) ++#define P_EE_AUDIO_CLK_SPDIFOUT_B_CTRL (volatile uint32_t *)(0xff642000 + (0x02d << 2)) ++#define EE_AUDIO_TODDR_A_CTRL0 (0xff642000 + (0x040 << 2)) ++#define SEC_EE_AUDIO_TODDR_A_CTRL0 (0xff642000 + (0x040 << 2)) ++#define P_EE_AUDIO_TODDR_A_CTRL0 (volatile uint32_t *)(0xff642000 + (0x040 << 2)) ++#define EE_AUDIO_TODDR_A_CTRL1 (0xff642000 + (0x041 << 2)) ++#define SEC_EE_AUDIO_TODDR_A_CTRL1 (0xff642000 + (0x041 << 2)) ++#define P_EE_AUDIO_TODDR_A_CTRL1 (volatile uint32_t *)(0xff642000 + (0x041 << 2)) ++#define EE_AUDIO_TODDR_A_START_ADDR (0xff642000 + (0x042 << 2)) ++#define SEC_EE_AUDIO_TODDR_A_START_ADDR (0xff642000 + (0x042 << 2)) ++#define P_EE_AUDIO_TODDR_A_START_ADDR (volatile uint32_t *)(0xff642000 + (0x042 << 2)) ++#define EE_AUDIO_TODDR_A_FINISH_ADDR (0xff642000 + (0x043 << 2)) ++#define SEC_EE_AUDIO_TODDR_A_FINISH_ADDR (0xff642000 + (0x043 << 2)) ++#define P_EE_AUDIO_TODDR_A_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x043 << 2)) ++#define EE_AUDIO_TODDR_A_INT_ADDR (0xff642000 + (0x044 << 2)) ++#define SEC_EE_AUDIO_TODDR_A_INT_ADDR (0xff642000 + (0x044 << 2)) ++#define P_EE_AUDIO_TODDR_A_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x044 << 2)) ++#define EE_AUDIO_TODDR_A_STATUS1 (0xff642000 + (0x045 << 2)) ++#define SEC_EE_AUDIO_TODDR_A_STATUS1 (0xff642000 + (0x045 << 2)) ++#define P_EE_AUDIO_TODDR_A_STATUS1 (volatile uint32_t *)(0xff642000 + (0x045 << 2)) ++#define EE_AUDIO_TODDR_A_STATUS2 (0xff642000 + (0x046 << 2)) ++#define SEC_EE_AUDIO_TODDR_A_STATUS2 (0xff642000 + (0x046 << 2)) ++#define P_EE_AUDIO_TODDR_A_STATUS2 (volatile uint32_t *)(0xff642000 + (0x046 << 2)) ++#define EE_AUDIO_TODDR_A_START_ADDRB (0xff642000 + (0x047 << 2)) ++#define SEC_EE_AUDIO_TODDR_A_START_ADDRB (0xff642000 + (0x047 << 2)) ++#define P_EE_AUDIO_TODDR_A_START_ADDRB (volatile uint32_t *)(0xff642000 + (0x047 << 2)) ++#define EE_AUDIO_TODDR_A_FINISH_ADDRB (0xff642000 + (0x048 << 2)) ++#define SEC_EE_AUDIO_TODDR_A_FINISH_ADDRB (0xff642000 + (0x048 << 2)) ++#define P_EE_AUDIO_TODDR_A_FINISH_ADDRB (volatile uint32_t *)(0xff642000 + (0x048 << 2)) ++#define EE_AUDIO_TODDR_A_INIT_ADDR (0xff642000 + (0x049 << 2)) ++#define SEC_EE_AUDIO_TODDR_A_INIT_ADDR (0xff642000 + (0x049 << 2)) ++#define P_EE_AUDIO_TODDR_A_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x049 << 2)) ++#define EE_AUDIO_TODDR_B_CTRL0 (0xff642000 + (0x050 << 2)) ++#define SEC_EE_AUDIO_TODDR_B_CTRL0 (0xff642000 + (0x050 << 2)) ++#define P_EE_AUDIO_TODDR_B_CTRL0 (volatile uint32_t *)(0xff642000 + (0x050 << 2)) ++#define EE_AUDIO_TODDR_B_CTRL1 (0xff642000 + (0x051 << 2)) ++#define SEC_EE_AUDIO_TODDR_B_CTRL1 (0xff642000 + (0x051 << 2)) ++#define P_EE_AUDIO_TODDR_B_CTRL1 (volatile uint32_t *)(0xff642000 + (0x051 << 2)) ++#define EE_AUDIO_TODDR_B_START_ADDR (0xff642000 + (0x052 << 2)) ++#define SEC_EE_AUDIO_TODDR_B_START_ADDR (0xff642000 + (0x052 << 2)) ++#define P_EE_AUDIO_TODDR_B_START_ADDR (volatile uint32_t *)(0xff642000 + (0x052 << 2)) ++#define EE_AUDIO_TODDR_B_FINISH_ADDR (0xff642000 + (0x053 << 2)) ++#define SEC_EE_AUDIO_TODDR_B_FINISH_ADDR (0xff642000 + (0x053 << 2)) ++#define P_EE_AUDIO_TODDR_B_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x053 << 2)) ++#define EE_AUDIO_TODDR_B_INT_ADDR (0xff642000 + (0x054 << 2)) ++#define SEC_EE_AUDIO_TODDR_B_INT_ADDR (0xff642000 + (0x054 << 2)) ++#define P_EE_AUDIO_TODDR_B_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x054 << 2)) ++#define EE_AUDIO_TODDR_B_STATUS1 (0xff642000 + (0x055 << 2)) ++#define SEC_EE_AUDIO_TODDR_B_STATUS1 (0xff642000 + (0x055 << 2)) ++#define P_EE_AUDIO_TODDR_B_STATUS1 (volatile uint32_t *)(0xff642000 + (0x055 << 2)) ++#define EE_AUDIO_TODDR_B_STATUS2 (0xff642000 + (0x056 << 2)) ++#define SEC_EE_AUDIO_TODDR_B_STATUS2 (0xff642000 + (0x056 << 2)) ++#define P_EE_AUDIO_TODDR_B_STATUS2 (volatile uint32_t *)(0xff642000 + (0x056 << 2)) ++#define EE_AUDIO_TODDR_B_START_ADDRB (0xff642000 + (0x057 << 2)) ++#define SEC_EE_AUDIO_TODDR_B_START_ADDRB (0xff642000 + (0x057 << 2)) ++#define P_EE_AUDIO_TODDR_B_START_ADDRB (volatile uint32_t *)(0xff642000 + (0x057 << 2)) ++#define EE_AUDIO_TODDR_B_FINISH_ADDRB (0xff642000 + (0x058 << 2)) ++#define SEC_EE_AUDIO_TODDR_B_FINISH_ADDRB (0xff642000 + (0x058 << 2)) ++#define P_EE_AUDIO_TODDR_B_FINISH_ADDRB (volatile uint32_t *)(0xff642000 + (0x058 << 2)) ++#define EE_AUDIO_TODDR_B_INIT_ADDR (0xff642000 + (0x059 << 2)) ++#define SEC_EE_AUDIO_TODDR_B_INIT_ADDR (0xff642000 + (0x059 << 2)) ++#define P_EE_AUDIO_TODDR_B_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x059 << 2)) ++#define EE_AUDIO_TODDR_C_CTRL0 (0xff642000 + (0x060 << 2)) ++#define SEC_EE_AUDIO_TODDR_C_CTRL0 (0xff642000 + (0x060 << 2)) ++#define P_EE_AUDIO_TODDR_C_CTRL0 (volatile uint32_t *)(0xff642000 + (0x060 << 2)) ++#define EE_AUDIO_TODDR_C_CTRL1 (0xff642000 + (0x061 << 2)) ++#define SEC_EE_AUDIO_TODDR_C_CTRL1 (0xff642000 + (0x061 << 2)) ++#define P_EE_AUDIO_TODDR_C_CTRL1 (volatile uint32_t *)(0xff642000 + (0x061 << 2)) ++#define EE_AUDIO_TODDR_C_START_ADDR (0xff642000 + (0x062 << 2)) ++#define SEC_EE_AUDIO_TODDR_C_START_ADDR (0xff642000 + (0x062 << 2)) ++#define P_EE_AUDIO_TODDR_C_START_ADDR (volatile uint32_t *)(0xff642000 + (0x062 << 2)) ++#define EE_AUDIO_TODDR_C_FINISH_ADDR (0xff642000 + (0x063 << 2)) ++#define SEC_EE_AUDIO_TODDR_C_FINISH_ADDR (0xff642000 + (0x063 << 2)) ++#define P_EE_AUDIO_TODDR_C_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x063 << 2)) ++#define EE_AUDIO_TODDR_C_INT_ADDR (0xff642000 + (0x064 << 2)) ++#define SEC_EE_AUDIO_TODDR_C_INT_ADDR (0xff642000 + (0x064 << 2)) ++#define P_EE_AUDIO_TODDR_C_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x064 << 2)) ++#define EE_AUDIO_TODDR_C_STATUS1 (0xff642000 + (0x065 << 2)) ++#define SEC_EE_AUDIO_TODDR_C_STATUS1 (0xff642000 + (0x065 << 2)) ++#define P_EE_AUDIO_TODDR_C_STATUS1 (volatile uint32_t *)(0xff642000 + (0x065 << 2)) ++#define EE_AUDIO_TODDR_C_STATUS2 (0xff642000 + (0x066 << 2)) ++#define SEC_EE_AUDIO_TODDR_C_STATUS2 (0xff642000 + (0x066 << 2)) ++#define P_EE_AUDIO_TODDR_C_STATUS2 (volatile uint32_t *)(0xff642000 + (0x066 << 2)) ++#define EE_AUDIO_TODDR_C_START_ADDRB (0xff642000 + (0x067 << 2)) ++#define SEC_EE_AUDIO_TODDR_C_START_ADDRB (0xff642000 + (0x067 << 2)) ++#define P_EE_AUDIO_TODDR_C_START_ADDRB (volatile uint32_t *)(0xff642000 + (0x067 << 2)) ++#define EE_AUDIO_TODDR_C_FINISH_ADDRB (0xff642000 + (0x068 << 2)) ++#define SEC_EE_AUDIO_TODDR_C_FINISH_ADDRB (0xff642000 + (0x068 << 2)) ++#define P_EE_AUDIO_TODDR_C_FINISH_ADDRB (volatile uint32_t *)(0xff642000 + (0x068 << 2)) ++#define EE_AUDIO_TODDR_C_INIT_ADDR (0xff642000 + (0x069 << 2)) ++#define SEC_EE_AUDIO_TODDR_C_INIT_ADDR (0xff642000 + (0x069 << 2)) ++#define P_EE_AUDIO_TODDR_C_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x069 << 2)) ++#define EE_AUDIO_FRDDR_A_CTRL0 (0xff642000 + (0x070 << 2)) ++#define SEC_EE_AUDIO_FRDDR_A_CTRL0 (0xff642000 + (0x070 << 2)) ++#define P_EE_AUDIO_FRDDR_A_CTRL0 (volatile uint32_t *)(0xff642000 + (0x070 << 2)) ++#define EE_AUDIO_FRDDR_A_CTRL1 (0xff642000 + (0x071 << 2)) ++#define SEC_EE_AUDIO_FRDDR_A_CTRL1 (0xff642000 + (0x071 << 2)) ++#define P_EE_AUDIO_FRDDR_A_CTRL1 (volatile uint32_t *)(0xff642000 + (0x071 << 2)) ++#define EE_AUDIO_FRDDR_A_START_ADDR (0xff642000 + (0x072 << 2)) ++#define SEC_EE_AUDIO_FRDDR_A_START_ADDR (0xff642000 + (0x072 << 2)) ++#define P_EE_AUDIO_FRDDR_A_START_ADDR (volatile uint32_t *)(0xff642000 + (0x072 << 2)) ++#define EE_AUDIO_FRDDR_A_FINISH_ADDR (0xff642000 + (0x073 << 2)) ++#define SEC_EE_AUDIO_FRDDR_A_FINISH_ADDR (0xff642000 + (0x073 << 2)) ++#define P_EE_AUDIO_FRDDR_A_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x073 << 2)) ++#define EE_AUDIO_FRDDR_A_INT_ADDR (0xff642000 + (0x074 << 2)) ++#define SEC_EE_AUDIO_FRDDR_A_INT_ADDR (0xff642000 + (0x074 << 2)) ++#define P_EE_AUDIO_FRDDR_A_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x074 << 2)) ++#define EE_AUDIO_FRDDR_A_STATUS1 (0xff642000 + (0x075 << 2)) ++#define SEC_EE_AUDIO_FRDDR_A_STATUS1 (0xff642000 + (0x075 << 2)) ++#define P_EE_AUDIO_FRDDR_A_STATUS1 (volatile uint32_t *)(0xff642000 + (0x075 << 2)) ++#define EE_AUDIO_FRDDR_A_STATUS2 (0xff642000 + (0x076 << 2)) ++#define SEC_EE_AUDIO_FRDDR_A_STATUS2 (0xff642000 + (0x076 << 2)) ++#define P_EE_AUDIO_FRDDR_A_STATUS2 (volatile uint32_t *)(0xff642000 + (0x076 << 2)) ++#define EE_AUDIO_FRDDR_A_START_ADDRB (0xff642000 + (0x077 << 2)) ++#define SEC_EE_AUDIO_FRDDR_A_START_ADDRB (0xff642000 + (0x077 << 2)) ++#define P_EE_AUDIO_FRDDR_A_START_ADDRB (volatile uint32_t *)(0xff642000 + (0x077 << 2)) ++#define EE_AUDIO_FRDDR_A_FINISH_ADDRB (0xff642000 + (0x078 << 2)) ++#define SEC_EE_AUDIO_FRDDR_A_FINISH_ADDRB (0xff642000 + (0x078 << 2)) ++#define P_EE_AUDIO_FRDDR_A_FINISH_ADDRB (volatile uint32_t *)(0xff642000 + (0x078 << 2)) ++#define EE_AUDIO_FRDDR_A_INIT_ADDR (0xff642000 + (0x079 << 2)) ++#define SEC_EE_AUDIO_FRDDR_A_INIT_ADDR (0xff642000 + (0x079 << 2)) ++#define P_EE_AUDIO_FRDDR_A_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x079 << 2)) ++#define EE_AUDIO_FRDDR_B_CTRL0 (0xff642000 + (0x080 << 2)) ++#define SEC_EE_AUDIO_FRDDR_B_CTRL0 (0xff642000 + (0x080 << 2)) ++#define P_EE_AUDIO_FRDDR_B_CTRL0 (volatile uint32_t *)(0xff642000 + (0x080 << 2)) ++#define EE_AUDIO_FRDDR_B_CTRL1 (0xff642000 + (0x081 << 2)) ++#define SEC_EE_AUDIO_FRDDR_B_CTRL1 (0xff642000 + (0x081 << 2)) ++#define P_EE_AUDIO_FRDDR_B_CTRL1 (volatile uint32_t *)(0xff642000 + (0x081 << 2)) ++#define EE_AUDIO_FRDDR_B_START_ADDR (0xff642000 + (0x082 << 2)) ++#define SEC_EE_AUDIO_FRDDR_B_START_ADDR (0xff642000 + (0x082 << 2)) ++#define P_EE_AUDIO_FRDDR_B_START_ADDR (volatile uint32_t *)(0xff642000 + (0x082 << 2)) ++#define EE_AUDIO_FRDDR_B_FINISH_ADDR (0xff642000 + (0x083 << 2)) ++#define SEC_EE_AUDIO_FRDDR_B_FINISH_ADDR (0xff642000 + (0x083 << 2)) ++#define P_EE_AUDIO_FRDDR_B_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x083 << 2)) ++#define EE_AUDIO_FRDDR_B_INT_ADDR (0xff642000 + (0x084 << 2)) ++#define SEC_EE_AUDIO_FRDDR_B_INT_ADDR (0xff642000 + (0x084 << 2)) ++#define P_EE_AUDIO_FRDDR_B_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x084 << 2)) ++#define EE_AUDIO_FRDDR_B_STATUS1 (0xff642000 + (0x085 << 2)) ++#define SEC_EE_AUDIO_FRDDR_B_STATUS1 (0xff642000 + (0x085 << 2)) ++#define P_EE_AUDIO_FRDDR_B_STATUS1 (volatile uint32_t *)(0xff642000 + (0x085 << 2)) ++#define EE_AUDIO_FRDDR_B_STATUS2 (0xff642000 + (0x086 << 2)) ++#define SEC_EE_AUDIO_FRDDR_B_STATUS2 (0xff642000 + (0x086 << 2)) ++#define P_EE_AUDIO_FRDDR_B_STATUS2 (volatile uint32_t *)(0xff642000 + (0x086 << 2)) ++#define EE_AUDIO_FRDDR_B_START_ADDRB (0xff642000 + (0x087 << 2)) ++#define SEC_EE_AUDIO_FRDDR_B_START_ADDRB (0xff642000 + (0x087 << 2)) ++#define P_EE_AUDIO_FRDDR_B_START_ADDRB (volatile uint32_t *)(0xff642000 + (0x087 << 2)) ++#define EE_AUDIO_FRDDR_B_FINISH_ADDRB (0xff642000 + (0x088 << 2)) ++#define SEC_EE_AUDIO_FRDDR_B_FINISH_ADDRB (0xff642000 + (0x088 << 2)) ++#define P_EE_AUDIO_FRDDR_B_FINISH_ADDRB (volatile uint32_t *)(0xff642000 + (0x088 << 2)) ++#define EE_AUDIO_FRDDR_B_INIT_ADDR (0xff642000 + (0x089 << 2)) ++#define SEC_EE_AUDIO_FRDDR_B_INIT_ADDR (0xff642000 + (0x089 << 2)) ++#define P_EE_AUDIO_FRDDR_B_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x089 << 2)) ++#define EE_AUDIO_FRDDR_C_CTRL0 (0xff642000 + (0x090 << 2)) ++#define SEC_EE_AUDIO_FRDDR_C_CTRL0 (0xff642000 + (0x090 << 2)) ++#define P_EE_AUDIO_FRDDR_C_CTRL0 (volatile uint32_t *)(0xff642000 + (0x090 << 2)) ++#define EE_AUDIO_FRDDR_C_CTRL1 (0xff642000 + (0x091 << 2)) ++#define SEC_EE_AUDIO_FRDDR_C_CTRL1 (0xff642000 + (0x091 << 2)) ++#define P_EE_AUDIO_FRDDR_C_CTRL1 (volatile uint32_t *)(0xff642000 + (0x091 << 2)) ++#define EE_AUDIO_FRDDR_C_START_ADDR (0xff642000 + (0x092 << 2)) ++#define SEC_EE_AUDIO_FRDDR_C_START_ADDR (0xff642000 + (0x092 << 2)) ++#define P_EE_AUDIO_FRDDR_C_START_ADDR (volatile uint32_t *)(0xff642000 + (0x092 << 2)) ++#define EE_AUDIO_FRDDR_C_FINISH_ADDR (0xff642000 + (0x093 << 2)) ++#define SEC_EE_AUDIO_FRDDR_C_FINISH_ADDR (0xff642000 + (0x093 << 2)) ++#define P_EE_AUDIO_FRDDR_C_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x093 << 2)) ++#define EE_AUDIO_FRDDR_C_INT_ADDR (0xff642000 + (0x094 << 2)) ++#define SEC_EE_AUDIO_FRDDR_C_INT_ADDR (0xff642000 + (0x094 << 2)) ++#define P_EE_AUDIO_FRDDR_C_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x094 << 2)) ++#define EE_AUDIO_FRDDR_C_STATUS1 (0xff642000 + (0x095 << 2)) ++#define SEC_EE_AUDIO_FRDDR_C_STATUS1 (0xff642000 + (0x095 << 2)) ++#define P_EE_AUDIO_FRDDR_C_STATUS1 (volatile uint32_t *)(0xff642000 + (0x095 << 2)) ++#define EE_AUDIO_FRDDR_C_STATUS2 (0xff642000 + (0x096 << 2)) ++#define SEC_EE_AUDIO_FRDDR_C_STATUS2 (0xff642000 + (0x096 << 2)) ++#define P_EE_AUDIO_FRDDR_C_STATUS2 (volatile uint32_t *)(0xff642000 + (0x096 << 2)) ++#define EE_AUDIO_FRDDR_C_START_ADDRB (0xff642000 + (0x097 << 2)) ++#define SEC_EE_AUDIO_FRDDR_C_START_ADDRB (0xff642000 + (0x097 << 2)) ++#define P_EE_AUDIO_FRDDR_C_START_ADDRB (volatile uint32_t *)(0xff642000 + (0x097 << 2)) ++#define EE_AUDIO_FRDDR_C_FINISH_ADDRB (0xff642000 + (0x098 << 2)) ++#define SEC_EE_AUDIO_FRDDR_C_FINISH_ADDRB (0xff642000 + (0x098 << 2)) ++#define P_EE_AUDIO_FRDDR_C_FINISH_ADDRB (volatile uint32_t *)(0xff642000 + (0x098 << 2)) ++#define EE_AUDIO_FRDDR_C_INIT_ADDR (0xff642000 + (0x099 << 2)) ++#define SEC_EE_AUDIO_FRDDR_C_INIT_ADDR (0xff642000 + (0x099 << 2)) ++#define P_EE_AUDIO_FRDDR_C_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x099 << 2)) ++#define EE_AUDIO_ARB_CTRL (0xff642000 + (0x0a0 << 2)) ++#define SEC_EE_AUDIO_ARB_CTRL (0xff642000 + (0x0a0 << 2)) ++#define P_EE_AUDIO_ARB_CTRL (volatile uint32_t *)(0xff642000 + (0x0a0 << 2)) ++#define EE_AUDIO_LB_CTRL0 (0xff642000 + (0x0b0 << 2)) ++#define SEC_EE_AUDIO_LB_CTRL0 (0xff642000 + (0x0b0 << 2)) ++#define P_EE_AUDIO_LB_CTRL0 (volatile uint32_t *)(0xff642000 + (0x0b0 << 2)) ++#define EE_AUDIO_LB_CTRL1 (0xff642000 + (0x0b1 << 2)) ++#define SEC_EE_AUDIO_LB_CTRL1 (0xff642000 + (0x0b1 << 2)) ++#define P_EE_AUDIO_LB_CTRL1 (volatile uint32_t *)(0xff642000 + (0x0b1 << 2)) ++#define EE_AUDIO_LB_DAT_CH_ID0 (0xff642000 + (0x0b2 << 2)) ++#define SEC_EE_AUDIO_LB_DAT_CH_ID0 (0xff642000 + (0x0b2 << 2)) ++#define P_EE_AUDIO_LB_DAT_CH_ID0 (volatile uint32_t *)(0xff642000 + (0x0b2 << 2)) ++#define EE_AUDIO_LB_DAT_CH_ID1 (0xff642000 + (0x0b3 << 2)) ++#define SEC_EE_AUDIO_LB_DAT_CH_ID1 (0xff642000 + (0x0b3 << 2)) ++#define P_EE_AUDIO_LB_DAT_CH_ID1 (volatile uint32_t *)(0xff642000 + (0x0b3 << 2)) ++#define EE_AUDIO_LB_LB_CH_ID0 (0xff642000 + (0x0b4 << 2)) ++#define SEC_EE_AUDIO_LB_LB_CH_ID0 (0xff642000 + (0x0b4 << 2)) ++#define P_EE_AUDIO_LB_LB_CH_ID0 (volatile uint32_t *)(0xff642000 + (0x0b4 << 2)) ++#define EE_AUDIO_LB_LB_CH_ID1 (0xff642000 + (0x0b5 << 2)) ++#define SEC_EE_AUDIO_LB_LB_CH_ID1 (0xff642000 + (0x0b5 << 2)) ++#define P_EE_AUDIO_LB_LB_CH_ID1 (volatile uint32_t *)(0xff642000 + (0x0b5 << 2)) ++#define EE_AUDIO_LB_STS (0xff642000 + (0x0b6 << 2)) ++#define SEC_EE_AUDIO_LB_STS (0xff642000 + (0x0b6 << 2)) ++#define P_EE_AUDIO_LB_STS (volatile uint32_t *)(0xff642000 + (0x0b6 << 2)) ++#define EE_AUDIO_TDMIN_A_CTRL (0xff642000 + (0x0c0 << 2)) ++#define SEC_EE_AUDIO_TDMIN_A_CTRL (0xff642000 + (0x0c0 << 2)) ++#define P_EE_AUDIO_TDMIN_A_CTRL (volatile uint32_t *)(0xff642000 + (0x0c0 << 2)) ++#define EE_AUDIO_TDMIN_A_SWAP (0xff642000 + (0x0c1 << 2)) ++#define SEC_EE_AUDIO_TDMIN_A_SWAP (0xff642000 + (0x0c1 << 2)) ++#define P_EE_AUDIO_TDMIN_A_SWAP (volatile uint32_t *)(0xff642000 + (0x0c1 << 2)) ++#define EE_AUDIO_TDMIN_A_MASK0 (0xff642000 + (0x0c2 << 2)) ++#define SEC_EE_AUDIO_TDMIN_A_MASK0 (0xff642000 + (0x0c2 << 2)) ++#define P_EE_AUDIO_TDMIN_A_MASK0 (volatile uint32_t *)(0xff642000 + (0x0c2 << 2)) ++#define EE_AUDIO_TDMIN_A_MASK1 (0xff642000 + (0x0c3 << 2)) ++#define SEC_EE_AUDIO_TDMIN_A_MASK1 (0xff642000 + (0x0c3 << 2)) ++#define P_EE_AUDIO_TDMIN_A_MASK1 (volatile uint32_t *)(0xff642000 + (0x0c3 << 2)) ++#define EE_AUDIO_TDMIN_A_MASK2 (0xff642000 + (0x0c4 << 2)) ++#define SEC_EE_AUDIO_TDMIN_A_MASK2 (0xff642000 + (0x0c4 << 2)) ++#define P_EE_AUDIO_TDMIN_A_MASK2 (volatile uint32_t *)(0xff642000 + (0x0c4 << 2)) ++#define EE_AUDIO_TDMIN_A_MASK3 (0xff642000 + (0x0c5 << 2)) ++#define SEC_EE_AUDIO_TDMIN_A_MASK3 (0xff642000 + (0x0c5 << 2)) ++#define P_EE_AUDIO_TDMIN_A_MASK3 (volatile uint32_t *)(0xff642000 + (0x0c5 << 2)) ++#define EE_AUDIO_TDMIN_A_STAT (0xff642000 + (0x0c6 << 2)) ++#define SEC_EE_AUDIO_TDMIN_A_STAT (0xff642000 + (0x0c6 << 2)) ++#define P_EE_AUDIO_TDMIN_A_STAT (volatile uint32_t *)(0xff642000 + (0x0c6 << 2)) ++#define EE_AUDIO_TDMIN_A_MUTE_VAL (0xff642000 + (0x0c7 << 2)) ++#define SEC_EE_AUDIO_TDMIN_A_MUTE_VAL (0xff642000 + (0x0c7 << 2)) ++#define P_EE_AUDIO_TDMIN_A_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x0c7 << 2)) ++#define EE_AUDIO_TDMIN_A_MUTE0 (0xff642000 + (0x0c8 << 2)) ++#define SEC_EE_AUDIO_TDMIN_A_MUTE0 (0xff642000 + (0x0c8 << 2)) ++#define P_EE_AUDIO_TDMIN_A_MUTE0 (volatile uint32_t *)(0xff642000 + (0x0c8 << 2)) ++#define EE_AUDIO_TDMIN_A_MUTE1 (0xff642000 + (0x0c9 << 2)) ++#define SEC_EE_AUDIO_TDMIN_A_MUTE1 (0xff642000 + (0x0c9 << 2)) ++#define P_EE_AUDIO_TDMIN_A_MUTE1 (volatile uint32_t *)(0xff642000 + (0x0c9 << 2)) ++#define EE_AUDIO_TDMIN_A_MUTE2 (0xff642000 + (0x0ca << 2)) ++#define SEC_EE_AUDIO_TDMIN_A_MUTE2 (0xff642000 + (0x0ca << 2)) ++#define P_EE_AUDIO_TDMIN_A_MUTE2 (volatile uint32_t *)(0xff642000 + (0x0ca << 2)) ++#define EE_AUDIO_TDMIN_A_MUTE3 (0xff642000 + (0x0cb << 2)) ++#define SEC_EE_AUDIO_TDMIN_A_MUTE3 (0xff642000 + (0x0cb << 2)) ++#define P_EE_AUDIO_TDMIN_A_MUTE3 (volatile uint32_t *)(0xff642000 + (0x0cb << 2)) ++#define EE_AUDIO_TDMIN_B_CTRL (0xff642000 + (0x0d0 << 2)) ++#define SEC_EE_AUDIO_TDMIN_B_CTRL (0xff642000 + (0x0d0 << 2)) ++#define P_EE_AUDIO_TDMIN_B_CTRL (volatile uint32_t *)(0xff642000 + (0x0d0 << 2)) ++#define EE_AUDIO_TDMIN_B_SWAP (0xff642000 + (0x0d1 << 2)) ++#define SEC_EE_AUDIO_TDMIN_B_SWAP (0xff642000 + (0x0d1 << 2)) ++#define P_EE_AUDIO_TDMIN_B_SWAP (volatile uint32_t *)(0xff642000 + (0x0d1 << 2)) ++#define EE_AUDIO_TDMIN_B_MASK0 (0xff642000 + (0x0d2 << 2)) ++#define SEC_EE_AUDIO_TDMIN_B_MASK0 (0xff642000 + (0x0d2 << 2)) ++#define P_EE_AUDIO_TDMIN_B_MASK0 (volatile uint32_t *)(0xff642000 + (0x0d2 << 2)) ++#define EE_AUDIO_TDMIN_B_MASK1 (0xff642000 + (0x0d3 << 2)) ++#define SEC_EE_AUDIO_TDMIN_B_MASK1 (0xff642000 + (0x0d3 << 2)) ++#define P_EE_AUDIO_TDMIN_B_MASK1 (volatile uint32_t *)(0xff642000 + (0x0d3 << 2)) ++#define EE_AUDIO_TDMIN_B_MASK2 (0xff642000 + (0x0d4 << 2)) ++#define SEC_EE_AUDIO_TDMIN_B_MASK2 (0xff642000 + (0x0d4 << 2)) ++#define P_EE_AUDIO_TDMIN_B_MASK2 (volatile uint32_t *)(0xff642000 + (0x0d4 << 2)) ++#define EE_AUDIO_TDMIN_B_MASK3 (0xff642000 + (0x0d5 << 2)) ++#define SEC_EE_AUDIO_TDMIN_B_MASK3 (0xff642000 + (0x0d5 << 2)) ++#define P_EE_AUDIO_TDMIN_B_MASK3 (volatile uint32_t *)(0xff642000 + (0x0d5 << 2)) ++#define EE_AUDIO_TDMIN_B_STAT (0xff642000 + (0x0d6 << 2)) ++#define SEC_EE_AUDIO_TDMIN_B_STAT (0xff642000 + (0x0d6 << 2)) ++#define P_EE_AUDIO_TDMIN_B_STAT (volatile uint32_t *)(0xff642000 + (0x0d6 << 2)) ++#define EE_AUDIO_TDMIN_B_MUTE_VAL (0xff642000 + (0x0d7 << 2)) ++#define SEC_EE_AUDIO_TDMIN_B_MUTE_VAL (0xff642000 + (0x0d7 << 2)) ++#define P_EE_AUDIO_TDMIN_B_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x0d7 << 2)) ++#define EE_AUDIO_TDMIN_B_MUTE0 (0xff642000 + (0x0d8 << 2)) ++#define SEC_EE_AUDIO_TDMIN_B_MUTE0 (0xff642000 + (0x0d8 << 2)) ++#define P_EE_AUDIO_TDMIN_B_MUTE0 (volatile uint32_t *)(0xff642000 + (0x0d8 << 2)) ++#define EE_AUDIO_TDMIN_B_MUTE1 (0xff642000 + (0x0d9 << 2)) ++#define SEC_EE_AUDIO_TDMIN_B_MUTE1 (0xff642000 + (0x0d9 << 2)) ++#define P_EE_AUDIO_TDMIN_B_MUTE1 (volatile uint32_t *)(0xff642000 + (0x0d9 << 2)) ++#define EE_AUDIO_TDMIN_B_MUTE2 (0xff642000 + (0x0da << 2)) ++#define SEC_EE_AUDIO_TDMIN_B_MUTE2 (0xff642000 + (0x0da << 2)) ++#define P_EE_AUDIO_TDMIN_B_MUTE2 (volatile uint32_t *)(0xff642000 + (0x0da << 2)) ++#define EE_AUDIO_TDMIN_B_MUTE3 (0xff642000 + (0x0db << 2)) ++#define SEC_EE_AUDIO_TDMIN_B_MUTE3 (0xff642000 + (0x0db << 2)) ++#define P_EE_AUDIO_TDMIN_B_MUTE3 (volatile uint32_t *)(0xff642000 + (0x0db << 2)) ++#define EE_AUDIO_TDMIN_C_CTRL (0xff642000 + (0x0e0 << 2)) ++#define SEC_EE_AUDIO_TDMIN_C_CTRL (0xff642000 + (0x0e0 << 2)) ++#define P_EE_AUDIO_TDMIN_C_CTRL (volatile uint32_t *)(0xff642000 + (0x0e0 << 2)) ++#define EE_AUDIO_TDMIN_C_SWAP (0xff642000 + (0x0e1 << 2)) ++#define SEC_EE_AUDIO_TDMIN_C_SWAP (0xff642000 + (0x0e1 << 2)) ++#define P_EE_AUDIO_TDMIN_C_SWAP (volatile uint32_t *)(0xff642000 + (0x0e1 << 2)) ++#define EE_AUDIO_TDMIN_C_MASK0 (0xff642000 + (0x0e2 << 2)) ++#define SEC_EE_AUDIO_TDMIN_C_MASK0 (0xff642000 + (0x0e2 << 2)) ++#define P_EE_AUDIO_TDMIN_C_MASK0 (volatile uint32_t *)(0xff642000 + (0x0e2 << 2)) ++#define EE_AUDIO_TDMIN_C_MASK1 (0xff642000 + (0x0e3 << 2)) ++#define SEC_EE_AUDIO_TDMIN_C_MASK1 (0xff642000 + (0x0e3 << 2)) ++#define P_EE_AUDIO_TDMIN_C_MASK1 (volatile uint32_t *)(0xff642000 + (0x0e3 << 2)) ++#define EE_AUDIO_TDMIN_C_MASK2 (0xff642000 + (0x0e4 << 2)) ++#define SEC_EE_AUDIO_TDMIN_C_MASK2 (0xff642000 + (0x0e4 << 2)) ++#define P_EE_AUDIO_TDMIN_C_MASK2 (volatile uint32_t *)(0xff642000 + (0x0e4 << 2)) ++#define EE_AUDIO_TDMIN_C_MASK3 (0xff642000 + (0x0e5 << 2)) ++#define SEC_EE_AUDIO_TDMIN_C_MASK3 (0xff642000 + (0x0e5 << 2)) ++#define P_EE_AUDIO_TDMIN_C_MASK3 (volatile uint32_t *)(0xff642000 + (0x0e5 << 2)) ++#define EE_AUDIO_TDMIN_C_STAT (0xff642000 + (0x0e6 << 2)) ++#define SEC_EE_AUDIO_TDMIN_C_STAT (0xff642000 + (0x0e6 << 2)) ++#define P_EE_AUDIO_TDMIN_C_STAT (volatile uint32_t *)(0xff642000 + (0x0e6 << 2)) ++#define EE_AUDIO_TDMIN_C_MUTE_VAL (0xff642000 + (0x0e7 << 2)) ++#define SEC_EE_AUDIO_TDMIN_C_MUTE_VAL (0xff642000 + (0x0e7 << 2)) ++#define P_EE_AUDIO_TDMIN_C_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x0e7 << 2)) ++#define EE_AUDIO_TDMIN_C_MUTE0 (0xff642000 + (0x0e8 << 2)) ++#define SEC_EE_AUDIO_TDMIN_C_MUTE0 (0xff642000 + (0x0e8 << 2)) ++#define P_EE_AUDIO_TDMIN_C_MUTE0 (volatile uint32_t *)(0xff642000 + (0x0e8 << 2)) ++#define EE_AUDIO_TDMIN_C_MUTE1 (0xff642000 + (0x0e9 << 2)) ++#define SEC_EE_AUDIO_TDMIN_C_MUTE1 (0xff642000 + (0x0e9 << 2)) ++#define P_EE_AUDIO_TDMIN_C_MUTE1 (volatile uint32_t *)(0xff642000 + (0x0e9 << 2)) ++#define EE_AUDIO_TDMIN_C_MUTE2 (0xff642000 + (0x0ea << 2)) ++#define SEC_EE_AUDIO_TDMIN_C_MUTE2 (0xff642000 + (0x0ea << 2)) ++#define P_EE_AUDIO_TDMIN_C_MUTE2 (volatile uint32_t *)(0xff642000 + (0x0ea << 2)) ++#define EE_AUDIO_TDMIN_C_MUTE3 (0xff642000 + (0x0eb << 2)) ++#define SEC_EE_AUDIO_TDMIN_C_MUTE3 (0xff642000 + (0x0eb << 2)) ++#define P_EE_AUDIO_TDMIN_C_MUTE3 (volatile uint32_t *)(0xff642000 + (0x0eb << 2)) ++#define EE_AUDIO_TDMIN_LB_CTRL (0xff642000 + (0x0f0 << 2)) ++#define SEC_EE_AUDIO_TDMIN_LB_CTRL (0xff642000 + (0x0f0 << 2)) ++#define P_EE_AUDIO_TDMIN_LB_CTRL (volatile uint32_t *)(0xff642000 + (0x0f0 << 2)) ++#define EE_AUDIO_TDMIN_LB_SWAP (0xff642000 + (0x0f1 << 2)) ++#define SEC_EE_AUDIO_TDMIN_LB_SWAP (0xff642000 + (0x0f1 << 2)) ++#define P_EE_AUDIO_TDMIN_LB_SWAP (volatile uint32_t *)(0xff642000 + (0x0f1 << 2)) ++#define EE_AUDIO_TDMIN_LB_MASK0 (0xff642000 + (0x0f2 << 2)) ++#define SEC_EE_AUDIO_TDMIN_LB_MASK0 (0xff642000 + (0x0f2 << 2)) ++#define P_EE_AUDIO_TDMIN_LB_MASK0 (volatile uint32_t *)(0xff642000 + (0x0f2 << 2)) ++#define EE_AUDIO_TDMIN_LB_MASK1 (0xff642000 + (0x0f3 << 2)) ++#define SEC_EE_AUDIO_TDMIN_LB_MASK1 (0xff642000 + (0x0f3 << 2)) ++#define P_EE_AUDIO_TDMIN_LB_MASK1 (volatile uint32_t *)(0xff642000 + (0x0f3 << 2)) ++#define EE_AUDIO_TDMIN_LB_MASK2 (0xff642000 + (0x0f4 << 2)) ++#define SEC_EE_AUDIO_TDMIN_LB_MASK2 (0xff642000 + (0x0f4 << 2)) ++#define P_EE_AUDIO_TDMIN_LB_MASK2 (volatile uint32_t *)(0xff642000 + (0x0f4 << 2)) ++#define EE_AUDIO_TDMIN_LB_MASK3 (0xff642000 + (0x0f5 << 2)) ++#define SEC_EE_AUDIO_TDMIN_LB_MASK3 (0xff642000 + (0x0f5 << 2)) ++#define P_EE_AUDIO_TDMIN_LB_MASK3 (volatile uint32_t *)(0xff642000 + (0x0f5 << 2)) ++#define EE_AUDIO_TDMIN_LB_STAT (0xff642000 + (0x0f6 << 2)) ++#define SEC_EE_AUDIO_TDMIN_LB_STAT (0xff642000 + (0x0f6 << 2)) ++#define P_EE_AUDIO_TDMIN_LB_STAT (volatile uint32_t *)(0xff642000 + (0x0f6 << 2)) ++#define EE_AUDIO_TDMIN_LB_MUTE_VAL (0xff642000 + (0x0f7 << 2)) ++#define SEC_EE_AUDIO_TDMIN_LB_MUTE_VAL (0xff642000 + (0x0f7 << 2)) ++#define P_EE_AUDIO_TDMIN_LB_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x0f7 << 2)) ++#define EE_AUDIO_TDMIN_LB_MUTE0 (0xff642000 + (0x0f8 << 2)) ++#define SEC_EE_AUDIO_TDMIN_LB_MUTE0 (0xff642000 + (0x0f8 << 2)) ++#define P_EE_AUDIO_TDMIN_LB_MUTE0 (volatile uint32_t *)(0xff642000 + (0x0f8 << 2)) ++#define EE_AUDIO_TDMIN_LB_MUTE1 (0xff642000 + (0x0f9 << 2)) ++#define SEC_EE_AUDIO_TDMIN_LB_MUTE1 (0xff642000 + (0x0f9 << 2)) ++#define P_EE_AUDIO_TDMIN_LB_MUTE1 (volatile uint32_t *)(0xff642000 + (0x0f9 << 2)) ++#define EE_AUDIO_TDMIN_LB_MUTE2 (0xff642000 + (0x0fa << 2)) ++#define SEC_EE_AUDIO_TDMIN_LB_MUTE2 (0xff642000 + (0x0fa << 2)) ++#define P_EE_AUDIO_TDMIN_LB_MUTE2 (volatile uint32_t *)(0xff642000 + (0x0fa << 2)) ++#define EE_AUDIO_TDMIN_LB_MUTE3 (0xff642000 + (0x0fb << 2)) ++#define SEC_EE_AUDIO_TDMIN_LB_MUTE3 (0xff642000 + (0x0fb << 2)) ++#define P_EE_AUDIO_TDMIN_LB_MUTE3 (volatile uint32_t *)(0xff642000 + (0x0fb << 2)) ++#define EE_AUDIO_SPDIFIN_CTRL0 (0xff642000 + (0x100 << 2)) ++#define SEC_EE_AUDIO_SPDIFIN_CTRL0 (0xff642000 + (0x100 << 2)) ++#define P_EE_AUDIO_SPDIFIN_CTRL0 (volatile uint32_t *)(0xff642000 + (0x100 << 2)) ++#define EE_AUDIO_SPDIFIN_CTRL1 (0xff642000 + (0x101 << 2)) ++#define SEC_EE_AUDIO_SPDIFIN_CTRL1 (0xff642000 + (0x101 << 2)) ++#define P_EE_AUDIO_SPDIFIN_CTRL1 (volatile uint32_t *)(0xff642000 + (0x101 << 2)) ++#define EE_AUDIO_SPDIFIN_CTRL2 (0xff642000 + (0x102 << 2)) ++#define SEC_EE_AUDIO_SPDIFIN_CTRL2 (0xff642000 + (0x102 << 2)) ++#define P_EE_AUDIO_SPDIFIN_CTRL2 (volatile uint32_t *)(0xff642000 + (0x102 << 2)) ++#define EE_AUDIO_SPDIFIN_CTRL3 (0xff642000 + (0x103 << 2)) ++#define SEC_EE_AUDIO_SPDIFIN_CTRL3 (0xff642000 + (0x103 << 2)) ++#define P_EE_AUDIO_SPDIFIN_CTRL3 (volatile uint32_t *)(0xff642000 + (0x103 << 2)) ++#define EE_AUDIO_SPDIFIN_CTRL4 (0xff642000 + (0x104 << 2)) ++#define SEC_EE_AUDIO_SPDIFIN_CTRL4 (0xff642000 + (0x104 << 2)) ++#define P_EE_AUDIO_SPDIFIN_CTRL4 (volatile uint32_t *)(0xff642000 + (0x104 << 2)) ++#define EE_AUDIO_SPDIFIN_CTRL5 (0xff642000 + (0x105 << 2)) ++#define SEC_EE_AUDIO_SPDIFIN_CTRL5 (0xff642000 + (0x105 << 2)) ++#define P_EE_AUDIO_SPDIFIN_CTRL5 (volatile uint32_t *)(0xff642000 + (0x105 << 2)) ++#define EE_AUDIO_SPDIFIN_CTRL6 (0xff642000 + (0x106 << 2)) ++#define SEC_EE_AUDIO_SPDIFIN_CTRL6 (0xff642000 + (0x106 << 2)) ++#define P_EE_AUDIO_SPDIFIN_CTRL6 (volatile uint32_t *)(0xff642000 + (0x106 << 2)) ++#define EE_AUDIO_SPDIFIN_STAT0 (0xff642000 + (0x107 << 2)) ++#define SEC_EE_AUDIO_SPDIFIN_STAT0 (0xff642000 + (0x107 << 2)) ++#define P_EE_AUDIO_SPDIFIN_STAT0 (volatile uint32_t *)(0xff642000 + (0x107 << 2)) ++#define EE_AUDIO_SPDIFIN_STAT1 (0xff642000 + (0x108 << 2)) ++#define SEC_EE_AUDIO_SPDIFIN_STAT1 (0xff642000 + (0x108 << 2)) ++#define P_EE_AUDIO_SPDIFIN_STAT1 (volatile uint32_t *)(0xff642000 + (0x108 << 2)) ++#define EE_AUDIO_SPDIFIN_STAT2 (0xff642000 + (0x109 << 2)) ++#define SEC_EE_AUDIO_SPDIFIN_STAT2 (0xff642000 + (0x109 << 2)) ++#define P_EE_AUDIO_SPDIFIN_STAT2 (volatile uint32_t *)(0xff642000 + (0x109 << 2)) ++#define EE_AUDIO_SPDIFIN_MUTE_VAL (0xff642000 + (0x10a << 2)) ++#define SEC_EE_AUDIO_SPDIFIN_MUTE_VAL (0xff642000 + (0x10a << 2)) ++#define P_EE_AUDIO_SPDIFIN_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x10a << 2)) ++#define EE_AUDIO_RESAMPLE_CTRL0 (0xff642000 + (0x110 << 2)) ++#define SEC_EE_AUDIO_RESAMPLE_CTRL0 (0xff642000 + (0x110 << 2)) ++#define P_EE_AUDIO_RESAMPLE_CTRL0 (volatile uint32_t *)(0xff642000 + (0x110 << 2)) ++#define EE_AUDIO_RESAMPLE_CTRL1 (0xff642000 + (0x111 << 2)) ++#define SEC_EE_AUDIO_RESAMPLE_CTRL1 (0xff642000 + (0x111 << 2)) ++#define P_EE_AUDIO_RESAMPLE_CTRL1 (volatile uint32_t *)(0xff642000 + (0x111 << 2)) ++#define EE_AUDIO_RESAMPLE_CTRL2 (0xff642000 + (0x112 << 2)) ++#define SEC_EE_AUDIO_RESAMPLE_CTRL2 (0xff642000 + (0x112 << 2)) ++#define P_EE_AUDIO_RESAMPLE_CTRL2 (volatile uint32_t *)(0xff642000 + (0x112 << 2)) ++#define EE_AUDIO_RESAMPLE_CTRL3 (0xff642000 + (0x113 << 2)) ++#define SEC_EE_AUDIO_RESAMPLE_CTRL3 (0xff642000 + (0x113 << 2)) ++#define P_EE_AUDIO_RESAMPLE_CTRL3 (volatile uint32_t *)(0xff642000 + (0x113 << 2)) ++#define EE_AUDIO_RESAMPLE_COEF0 (0xff642000 + (0x114 << 2)) ++#define SEC_EE_AUDIO_RESAMPLE_COEF0 (0xff642000 + (0x114 << 2)) ++#define P_EE_AUDIO_RESAMPLE_COEF0 (volatile uint32_t *)(0xff642000 + (0x114 << 2)) ++#define EE_AUDIO_RESAMPLE_COEF1 (0xff642000 + (0x115 << 2)) ++#define SEC_EE_AUDIO_RESAMPLE_COEF1 (0xff642000 + (0x115 << 2)) ++#define P_EE_AUDIO_RESAMPLE_COEF1 (volatile uint32_t *)(0xff642000 + (0x115 << 2)) ++#define EE_AUDIO_RESAMPLE_COEF2 (0xff642000 + (0x116 << 2)) ++#define SEC_EE_AUDIO_RESAMPLE_COEF2 (0xff642000 + (0x116 << 2)) ++#define P_EE_AUDIO_RESAMPLE_COEF2 (volatile uint32_t *)(0xff642000 + (0x116 << 2)) ++#define EE_AUDIO_RESAMPLE_COEF3 (0xff642000 + (0x117 << 2)) ++#define SEC_EE_AUDIO_RESAMPLE_COEF3 (0xff642000 + (0x117 << 2)) ++#define P_EE_AUDIO_RESAMPLE_COEF3 (volatile uint32_t *)(0xff642000 + (0x117 << 2)) ++#define EE_AUDIO_RESAMPLE_COEF4 (0xff642000 + (0x118 << 2)) ++#define SEC_EE_AUDIO_RESAMPLE_COEF4 (0xff642000 + (0x118 << 2)) ++#define P_EE_AUDIO_RESAMPLE_COEF4 (volatile uint32_t *)(0xff642000 + (0x118 << 2)) ++#define EE_AUDIO_RESAMPLE_STATUS1 (0xff642000 + (0x119 << 2)) ++#define SEC_EE_AUDIO_RESAMPLE_STATUS1 (0xff642000 + (0x119 << 2)) ++#define P_EE_AUDIO_RESAMPLE_STATUS1 (volatile uint32_t *)(0xff642000 + (0x119 << 2)) ++#define EE_AUDIO_SPDIFOUT_STAT (0xff642000 + (0x120 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_STAT (0xff642000 + (0x120 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_STAT (volatile uint32_t *)(0xff642000 + (0x120 << 2)) ++#define EE_AUDIO_SPDIFOUT_GAIN0 (0xff642000 + (0x121 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_GAIN0 (0xff642000 + (0x121 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_GAIN0 (volatile uint32_t *)(0xff642000 + (0x121 << 2)) ++#define EE_AUDIO_SPDIFOUT_GAIN1 (0xff642000 + (0x122 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_GAIN1 (0xff642000 + (0x122 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_GAIN1 (volatile uint32_t *)(0xff642000 + (0x122 << 2)) ++#define EE_AUDIO_SPDIFOUT_CTRL0 (0xff642000 + (0x123 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_CTRL0 (0xff642000 + (0x123 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_CTRL0 (volatile uint32_t *)(0xff642000 + (0x123 << 2)) ++#define EE_AUDIO_SPDIFOUT_CTRL1 (0xff642000 + (0x124 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_CTRL1 (0xff642000 + (0x124 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_CTRL1 (volatile uint32_t *)(0xff642000 + (0x124 << 2)) ++#define EE_AUDIO_SPDIFOUT_PREAMB (0xff642000 + (0x125 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_PREAMB (0xff642000 + (0x125 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_PREAMB (volatile uint32_t *)(0xff642000 + (0x125 << 2)) ++#define EE_AUDIO_SPDIFOUT_SWAP (0xff642000 + (0x126 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_SWAP (0xff642000 + (0x126 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_SWAP (volatile uint32_t *)(0xff642000 + (0x126 << 2)) ++#define EE_AUDIO_SPDIFOUT_CHSTS0 (0xff642000 + (0x127 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_CHSTS0 (0xff642000 + (0x127 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_CHSTS0 (volatile uint32_t *)(0xff642000 + (0x127 << 2)) ++#define EE_AUDIO_SPDIFOUT_CHSTS1 (0xff642000 + (0x128 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_CHSTS1 (0xff642000 + (0x128 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_CHSTS1 (volatile uint32_t *)(0xff642000 + (0x128 << 2)) ++#define EE_AUDIO_SPDIFOUT_CHSTS2 (0xff642000 + (0x129 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_CHSTS2 (0xff642000 + (0x129 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_CHSTS2 (volatile uint32_t *)(0xff642000 + (0x129 << 2)) ++#define EE_AUDIO_SPDIFOUT_CHSTS3 (0xff642000 + (0x12a << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_CHSTS3 (0xff642000 + (0x12a << 2)) ++#define P_EE_AUDIO_SPDIFOUT_CHSTS3 (volatile uint32_t *)(0xff642000 + (0x12a << 2)) ++#define EE_AUDIO_SPDIFOUT_CHSTS4 (0xff642000 + (0x12b << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_CHSTS4 (0xff642000 + (0x12b << 2)) ++#define P_EE_AUDIO_SPDIFOUT_CHSTS4 (volatile uint32_t *)(0xff642000 + (0x12b << 2)) ++#define EE_AUDIO_SPDIFOUT_CHSTS5 (0xff642000 + (0x12c << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_CHSTS5 (0xff642000 + (0x12c << 2)) ++#define P_EE_AUDIO_SPDIFOUT_CHSTS5 (volatile uint32_t *)(0xff642000 + (0x12c << 2)) ++#define EE_AUDIO_SPDIFOUT_CHSTS6 (0xff642000 + (0x12d << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_CHSTS6 (0xff642000 + (0x12d << 2)) ++#define P_EE_AUDIO_SPDIFOUT_CHSTS6 (volatile uint32_t *)(0xff642000 + (0x12d << 2)) ++#define EE_AUDIO_SPDIFOUT_CHSTS7 (0xff642000 + (0x12e << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_CHSTS7 (0xff642000 + (0x12e << 2)) ++#define P_EE_AUDIO_SPDIFOUT_CHSTS7 (volatile uint32_t *)(0xff642000 + (0x12e << 2)) ++#define EE_AUDIO_SPDIFOUT_CHSTS8 (0xff642000 + (0x12f << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_CHSTS8 (0xff642000 + (0x12f << 2)) ++#define P_EE_AUDIO_SPDIFOUT_CHSTS8 (volatile uint32_t *)(0xff642000 + (0x12f << 2)) ++#define EE_AUDIO_SPDIFOUT_CHSTS9 (0xff642000 + (0x130 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_CHSTS9 (0xff642000 + (0x130 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_CHSTS9 (volatile uint32_t *)(0xff642000 + (0x130 << 2)) ++#define EE_AUDIO_SPDIFOUT_CHSTSA (0xff642000 + (0x131 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_CHSTSA (0xff642000 + (0x131 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_CHSTSA (volatile uint32_t *)(0xff642000 + (0x131 << 2)) ++#define EE_AUDIO_SPDIFOUT_CHSTSB (0xff642000 + (0x132 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_CHSTSB (0xff642000 + (0x132 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_CHSTSB (volatile uint32_t *)(0xff642000 + (0x132 << 2)) ++#define EE_AUDIO_SPDIFOUT_MUTE_VAL (0xff642000 + (0x133 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_MUTE_VAL (0xff642000 + (0x133 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x133 << 2)) ++#define EE_AUDIO_TDMOUT_A_CTRL0 (0xff642000 + (0x140 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_A_CTRL0 (0xff642000 + (0x140 << 2)) ++#define P_EE_AUDIO_TDMOUT_A_CTRL0 (volatile uint32_t *)(0xff642000 + (0x140 << 2)) ++#define EE_AUDIO_TDMOUT_A_CTRL1 (0xff642000 + (0x141 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_A_CTRL1 (0xff642000 + (0x141 << 2)) ++#define P_EE_AUDIO_TDMOUT_A_CTRL1 (volatile uint32_t *)(0xff642000 + (0x141 << 2)) ++#define EE_AUDIO_TDMOUT_A_SWAP (0xff642000 + (0x142 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_A_SWAP (0xff642000 + (0x142 << 2)) ++#define P_EE_AUDIO_TDMOUT_A_SWAP (volatile uint32_t *)(0xff642000 + (0x142 << 2)) ++#define EE_AUDIO_TDMOUT_A_MASK0 (0xff642000 + (0x143 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_A_MASK0 (0xff642000 + (0x143 << 2)) ++#define P_EE_AUDIO_TDMOUT_A_MASK0 (volatile uint32_t *)(0xff642000 + (0x143 << 2)) ++#define EE_AUDIO_TDMOUT_A_MASK1 (0xff642000 + (0x144 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_A_MASK1 (0xff642000 + (0x144 << 2)) ++#define P_EE_AUDIO_TDMOUT_A_MASK1 (volatile uint32_t *)(0xff642000 + (0x144 << 2)) ++#define EE_AUDIO_TDMOUT_A_MASK2 (0xff642000 + (0x145 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_A_MASK2 (0xff642000 + (0x145 << 2)) ++#define P_EE_AUDIO_TDMOUT_A_MASK2 (volatile uint32_t *)(0xff642000 + (0x145 << 2)) ++#define EE_AUDIO_TDMOUT_A_MASK3 (0xff642000 + (0x146 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_A_MASK3 (0xff642000 + (0x146 << 2)) ++#define P_EE_AUDIO_TDMOUT_A_MASK3 (volatile uint32_t *)(0xff642000 + (0x146 << 2)) ++#define EE_AUDIO_TDMOUT_A_STAT (0xff642000 + (0x147 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_A_STAT (0xff642000 + (0x147 << 2)) ++#define P_EE_AUDIO_TDMOUT_A_STAT (volatile uint32_t *)(0xff642000 + (0x147 << 2)) ++#define EE_AUDIO_TDMOUT_A_GAIN0 (0xff642000 + (0x148 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_A_GAIN0 (0xff642000 + (0x148 << 2)) ++#define P_EE_AUDIO_TDMOUT_A_GAIN0 (volatile uint32_t *)(0xff642000 + (0x148 << 2)) ++#define EE_AUDIO_TDMOUT_A_GAIN1 (0xff642000 + (0x149 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_A_GAIN1 (0xff642000 + (0x149 << 2)) ++#define P_EE_AUDIO_TDMOUT_A_GAIN1 (volatile uint32_t *)(0xff642000 + (0x149 << 2)) ++#define EE_AUDIO_TDMOUT_A_MUTE_VAL (0xff642000 + (0x14a << 2)) ++#define SEC_EE_AUDIO_TDMOUT_A_MUTE_VAL (0xff642000 + (0x14a << 2)) ++#define P_EE_AUDIO_TDMOUT_A_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x14a << 2)) ++#define EE_AUDIO_TDMOUT_A_MUTE0 (0xff642000 + (0x14b << 2)) ++#define SEC_EE_AUDIO_TDMOUT_A_MUTE0 (0xff642000 + (0x14b << 2)) ++#define P_EE_AUDIO_TDMOUT_A_MUTE0 (volatile uint32_t *)(0xff642000 + (0x14b << 2)) ++#define EE_AUDIO_TDMOUT_A_MUTE1 (0xff642000 + (0x14c << 2)) ++#define SEC_EE_AUDIO_TDMOUT_A_MUTE1 (0xff642000 + (0x14c << 2)) ++#define P_EE_AUDIO_TDMOUT_A_MUTE1 (volatile uint32_t *)(0xff642000 + (0x14c << 2)) ++#define EE_AUDIO_TDMOUT_A_MUTE2 (0xff642000 + (0x14d << 2)) ++#define SEC_EE_AUDIO_TDMOUT_A_MUTE2 (0xff642000 + (0x14d << 2)) ++#define P_EE_AUDIO_TDMOUT_A_MUTE2 (volatile uint32_t *)(0xff642000 + (0x14d << 2)) ++#define EE_AUDIO_TDMOUT_A_MUTE3 (0xff642000 + (0x14e << 2)) ++#define SEC_EE_AUDIO_TDMOUT_A_MUTE3 (0xff642000 + (0x14e << 2)) ++#define P_EE_AUDIO_TDMOUT_A_MUTE3 (volatile uint32_t *)(0xff642000 + (0x14e << 2)) ++#define EE_AUDIO_TDMOUT_A_MASK_VAL (0xff642000 + (0x14f << 2)) ++#define SEC_EE_AUDIO_TDMOUT_A_MASK_VAL (0xff642000 + (0x14f << 2)) ++#define P_EE_AUDIO_TDMOUT_A_MASK_VAL (volatile uint32_t *)(0xff642000 + (0x14f << 2)) ++#define EE_AUDIO_TDMOUT_B_CTRL0 (0xff642000 + (0x150 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_B_CTRL0 (0xff642000 + (0x150 << 2)) ++#define P_EE_AUDIO_TDMOUT_B_CTRL0 (volatile uint32_t *)(0xff642000 + (0x150 << 2)) ++#define EE_AUDIO_TDMOUT_B_CTRL1 (0xff642000 + (0x151 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_B_CTRL1 (0xff642000 + (0x151 << 2)) ++#define P_EE_AUDIO_TDMOUT_B_CTRL1 (volatile uint32_t *)(0xff642000 + (0x151 << 2)) ++#define EE_AUDIO_TDMOUT_B_SWAP (0xff642000 + (0x152 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_B_SWAP (0xff642000 + (0x152 << 2)) ++#define P_EE_AUDIO_TDMOUT_B_SWAP (volatile uint32_t *)(0xff642000 + (0x152 << 2)) ++#define EE_AUDIO_TDMOUT_B_MASK0 (0xff642000 + (0x153 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_B_MASK0 (0xff642000 + (0x153 << 2)) ++#define P_EE_AUDIO_TDMOUT_B_MASK0 (volatile uint32_t *)(0xff642000 + (0x153 << 2)) ++#define EE_AUDIO_TDMOUT_B_MASK1 (0xff642000 + (0x154 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_B_MASK1 (0xff642000 + (0x154 << 2)) ++#define P_EE_AUDIO_TDMOUT_B_MASK1 (volatile uint32_t *)(0xff642000 + (0x154 << 2)) ++#define EE_AUDIO_TDMOUT_B_MASK2 (0xff642000 + (0x155 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_B_MASK2 (0xff642000 + (0x155 << 2)) ++#define P_EE_AUDIO_TDMOUT_B_MASK2 (volatile uint32_t *)(0xff642000 + (0x155 << 2)) ++#define EE_AUDIO_TDMOUT_B_MASK3 (0xff642000 + (0x156 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_B_MASK3 (0xff642000 + (0x156 << 2)) ++#define P_EE_AUDIO_TDMOUT_B_MASK3 (volatile uint32_t *)(0xff642000 + (0x156 << 2)) ++#define EE_AUDIO_TDMOUT_B_STAT (0xff642000 + (0x157 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_B_STAT (0xff642000 + (0x157 << 2)) ++#define P_EE_AUDIO_TDMOUT_B_STAT (volatile uint32_t *)(0xff642000 + (0x157 << 2)) ++#define EE_AUDIO_TDMOUT_B_GAIN0 (0xff642000 + (0x158 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_B_GAIN0 (0xff642000 + (0x158 << 2)) ++#define P_EE_AUDIO_TDMOUT_B_GAIN0 (volatile uint32_t *)(0xff642000 + (0x158 << 2)) ++#define EE_AUDIO_TDMOUT_B_GAIN1 (0xff642000 + (0x159 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_B_GAIN1 (0xff642000 + (0x159 << 2)) ++#define P_EE_AUDIO_TDMOUT_B_GAIN1 (volatile uint32_t *)(0xff642000 + (0x159 << 2)) ++#define EE_AUDIO_TDMOUT_B_MUTE_VAL (0xff642000 + (0x15a << 2)) ++#define SEC_EE_AUDIO_TDMOUT_B_MUTE_VAL (0xff642000 + (0x15a << 2)) ++#define P_EE_AUDIO_TDMOUT_B_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x15a << 2)) ++#define EE_AUDIO_TDMOUT_B_MUTE0 (0xff642000 + (0x15b << 2)) ++#define SEC_EE_AUDIO_TDMOUT_B_MUTE0 (0xff642000 + (0x15b << 2)) ++#define P_EE_AUDIO_TDMOUT_B_MUTE0 (volatile uint32_t *)(0xff642000 + (0x15b << 2)) ++#define EE_AUDIO_TDMOUT_B_MUTE1 (0xff642000 + (0x15c << 2)) ++#define SEC_EE_AUDIO_TDMOUT_B_MUTE1 (0xff642000 + (0x15c << 2)) ++#define P_EE_AUDIO_TDMOUT_B_MUTE1 (volatile uint32_t *)(0xff642000 + (0x15c << 2)) ++#define EE_AUDIO_TDMOUT_B_MUTE2 (0xff642000 + (0x15d << 2)) ++#define SEC_EE_AUDIO_TDMOUT_B_MUTE2 (0xff642000 + (0x15d << 2)) ++#define P_EE_AUDIO_TDMOUT_B_MUTE2 (volatile uint32_t *)(0xff642000 + (0x15d << 2)) ++#define EE_AUDIO_TDMOUT_B_MUTE3 (0xff642000 + (0x15e << 2)) ++#define SEC_EE_AUDIO_TDMOUT_B_MUTE3 (0xff642000 + (0x15e << 2)) ++#define P_EE_AUDIO_TDMOUT_B_MUTE3 (volatile uint32_t *)(0xff642000 + (0x15e << 2)) ++#define EE_AUDIO_TDMOUT_B_MASK_VAL (0xff642000 + (0x15f << 2)) ++#define SEC_EE_AUDIO_TDMOUT_B_MASK_VAL (0xff642000 + (0x15f << 2)) ++#define P_EE_AUDIO_TDMOUT_B_MASK_VAL (volatile uint32_t *)(0xff642000 + (0x15f << 2)) ++#define EE_AUDIO_TDMOUT_C_CTRL0 (0xff642000 + (0x160 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_C_CTRL0 (0xff642000 + (0x160 << 2)) ++#define P_EE_AUDIO_TDMOUT_C_CTRL0 (volatile uint32_t *)(0xff642000 + (0x160 << 2)) ++#define EE_AUDIO_TDMOUT_C_CTRL1 (0xff642000 + (0x161 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_C_CTRL1 (0xff642000 + (0x161 << 2)) ++#define P_EE_AUDIO_TDMOUT_C_CTRL1 (volatile uint32_t *)(0xff642000 + (0x161 << 2)) ++#define EE_AUDIO_TDMOUT_C_SWAP (0xff642000 + (0x162 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_C_SWAP (0xff642000 + (0x162 << 2)) ++#define P_EE_AUDIO_TDMOUT_C_SWAP (volatile uint32_t *)(0xff642000 + (0x162 << 2)) ++#define EE_AUDIO_TDMOUT_C_MASK0 (0xff642000 + (0x163 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_C_MASK0 (0xff642000 + (0x163 << 2)) ++#define P_EE_AUDIO_TDMOUT_C_MASK0 (volatile uint32_t *)(0xff642000 + (0x163 << 2)) ++#define EE_AUDIO_TDMOUT_C_MASK1 (0xff642000 + (0x164 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_C_MASK1 (0xff642000 + (0x164 << 2)) ++#define P_EE_AUDIO_TDMOUT_C_MASK1 (volatile uint32_t *)(0xff642000 + (0x164 << 2)) ++#define EE_AUDIO_TDMOUT_C_MASK2 (0xff642000 + (0x165 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_C_MASK2 (0xff642000 + (0x165 << 2)) ++#define P_EE_AUDIO_TDMOUT_C_MASK2 (volatile uint32_t *)(0xff642000 + (0x165 << 2)) ++#define EE_AUDIO_TDMOUT_C_MASK3 (0xff642000 + (0x166 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_C_MASK3 (0xff642000 + (0x166 << 2)) ++#define P_EE_AUDIO_TDMOUT_C_MASK3 (volatile uint32_t *)(0xff642000 + (0x166 << 2)) ++#define EE_AUDIO_TDMOUT_C_STAT (0xff642000 + (0x167 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_C_STAT (0xff642000 + (0x167 << 2)) ++#define P_EE_AUDIO_TDMOUT_C_STAT (volatile uint32_t *)(0xff642000 + (0x167 << 2)) ++#define EE_AUDIO_TDMOUT_C_GAIN0 (0xff642000 + (0x168 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_C_GAIN0 (0xff642000 + (0x168 << 2)) ++#define P_EE_AUDIO_TDMOUT_C_GAIN0 (volatile uint32_t *)(0xff642000 + (0x168 << 2)) ++#define EE_AUDIO_TDMOUT_C_GAIN1 (0xff642000 + (0x169 << 2)) ++#define SEC_EE_AUDIO_TDMOUT_C_GAIN1 (0xff642000 + (0x169 << 2)) ++#define P_EE_AUDIO_TDMOUT_C_GAIN1 (volatile uint32_t *)(0xff642000 + (0x169 << 2)) ++#define EE_AUDIO_TDMOUT_C_MUTE_VAL (0xff642000 + (0x16a << 2)) ++#define SEC_EE_AUDIO_TDMOUT_C_MUTE_VAL (0xff642000 + (0x16a << 2)) ++#define P_EE_AUDIO_TDMOUT_C_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x16a << 2)) ++#define EE_AUDIO_TDMOUT_C_MUTE0 (0xff642000 + (0x16b << 2)) ++#define SEC_EE_AUDIO_TDMOUT_C_MUTE0 (0xff642000 + (0x16b << 2)) ++#define P_EE_AUDIO_TDMOUT_C_MUTE0 (volatile uint32_t *)(0xff642000 + (0x16b << 2)) ++#define EE_AUDIO_TDMOUT_C_MUTE1 (0xff642000 + (0x16c << 2)) ++#define SEC_EE_AUDIO_TDMOUT_C_MUTE1 (0xff642000 + (0x16c << 2)) ++#define P_EE_AUDIO_TDMOUT_C_MUTE1 (volatile uint32_t *)(0xff642000 + (0x16c << 2)) ++#define EE_AUDIO_TDMOUT_C_MUTE2 (0xff642000 + (0x16d << 2)) ++#define SEC_EE_AUDIO_TDMOUT_C_MUTE2 (0xff642000 + (0x16d << 2)) ++#define P_EE_AUDIO_TDMOUT_C_MUTE2 (volatile uint32_t *)(0xff642000 + (0x16d << 2)) ++#define EE_AUDIO_TDMOUT_C_MUTE3 (0xff642000 + (0x16e << 2)) ++#define SEC_EE_AUDIO_TDMOUT_C_MUTE3 (0xff642000 + (0x16e << 2)) ++#define P_EE_AUDIO_TDMOUT_C_MUTE3 (volatile uint32_t *)(0xff642000 + (0x16e << 2)) ++#define EE_AUDIO_TDMOUT_C_MASK_VAL (0xff642000 + (0x16f << 2)) ++#define SEC_EE_AUDIO_TDMOUT_C_MASK_VAL (0xff642000 + (0x16f << 2)) ++#define P_EE_AUDIO_TDMOUT_C_MASK_VAL (volatile uint32_t *)(0xff642000 + (0x16f << 2)) ++#define EE_AUDIO_POW_DET_CTRL0 (0xff642000 + (0x180 << 2)) ++#define SEC_EE_AUDIO_POW_DET_CTRL0 (0xff642000 + (0x180 << 2)) ++#define P_EE_AUDIO_POW_DET_CTRL0 (volatile uint32_t *)(0xff642000 + (0x180 << 2)) ++#define EE_AUDIO_POW_DET_CTRL1 (0xff642000 + (0x181 << 2)) ++#define SEC_EE_AUDIO_POW_DET_CTRL1 (0xff642000 + (0x181 << 2)) ++#define P_EE_AUDIO_POW_DET_CTRL1 (volatile uint32_t *)(0xff642000 + (0x181 << 2)) ++#define EE_AUDIO_POW_DET_TH_HI (0xff642000 + (0x182 << 2)) ++#define SEC_EE_AUDIO_POW_DET_TH_HI (0xff642000 + (0x182 << 2)) ++#define P_EE_AUDIO_POW_DET_TH_HI (volatile uint32_t *)(0xff642000 + (0x182 << 2)) ++#define EE_AUDIO_POW_DET_TH_LO (0xff642000 + (0x183 << 2)) ++#define SEC_EE_AUDIO_POW_DET_TH_LO (0xff642000 + (0x183 << 2)) ++#define P_EE_AUDIO_POW_DET_TH_LO (volatile uint32_t *)(0xff642000 + (0x183 << 2)) ++#define EE_AUDIO_POW_DET_VALUE (0xff642000 + (0x184 << 2)) ++#define SEC_EE_AUDIO_POW_DET_VALUE (0xff642000 + (0x184 << 2)) ++#define P_EE_AUDIO_POW_DET_VALUE (volatile uint32_t *)(0xff642000 + (0x184 << 2)) ++#define EE_AUDIO_SECURITY_CTRL (0xff642000 + (0x193 << 2)) ++#define SEC_EE_AUDIO_SECURITY_CTRL (0xff642000 + (0x193 << 2)) ++#define P_EE_AUDIO_SECURITY_CTRL (volatile uint32_t *)(0xff642000 + (0x193 << 2)) ++#define EE_AUDIO_SPDIFOUT_B_STAT (0xff642000 + (0x1a0 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_STAT (0xff642000 + (0x1a0 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_STAT (volatile uint32_t *)(0xff642000 + (0x1a0 << 2)) ++#define EE_AUDIO_SPDIFOUT_B_GAIN0 (0xff642000 + (0x1a1 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_GAIN0 (0xff642000 + (0x1a1 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_GAIN0 (volatile uint32_t *)(0xff642000 + (0x1a1 << 2)) ++#define EE_AUDIO_SPDIFOUT_B_GAIN1 (0xff642000 + (0x1a2 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_GAIN1 (0xff642000 + (0x1a2 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_GAIN1 (volatile uint32_t *)(0xff642000 + (0x1a2 << 2)) ++#define EE_AUDIO_SPDIFOUT_B_CTRL0 (0xff642000 + (0x1a3 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_CTRL0 (0xff642000 + (0x1a3 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_CTRL0 (volatile uint32_t *)(0xff642000 + (0x1a3 << 2)) ++#define EE_AUDIO_SPDIFOUT_B_CTRL1 (0xff642000 + (0x1a4 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_CTRL1 (0xff642000 + (0x1a4 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_CTRL1 (volatile uint32_t *)(0xff642000 + (0x1a4 << 2)) ++#define EE_AUDIO_SPDIFOUT_B_PREAMB (0xff642000 + (0x1a5 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_PREAMB (0xff642000 + (0x1a5 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_PREAMB (volatile uint32_t *)(0xff642000 + (0x1a5 << 2)) ++#define EE_AUDIO_SPDIFOUT_B_SWAP (0xff642000 + (0x1a6 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_SWAP (0xff642000 + (0x1a6 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_SWAP (volatile uint32_t *)(0xff642000 + (0x1a6 << 2)) ++#define EE_AUDIO_SPDIFOUT_B_CHSTS0 (0xff642000 + (0x1a7 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS0 (0xff642000 + (0x1a7 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_CHSTS0 (volatile uint32_t *)(0xff642000 + (0x1a7 << 2)) ++#define EE_AUDIO_SPDIFOUT_B_CHSTS1 (0xff642000 + (0x1a8 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS1 (0xff642000 + (0x1a8 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_CHSTS1 (volatile uint32_t *)(0xff642000 + (0x1a8 << 2)) ++#define EE_AUDIO_SPDIFOUT_B_CHSTS2 (0xff642000 + (0x1a9 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS2 (0xff642000 + (0x1a9 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_CHSTS2 (volatile uint32_t *)(0xff642000 + (0x1a9 << 2)) ++#define EE_AUDIO_SPDIFOUT_B_CHSTS3 (0xff642000 + (0x1aa << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS3 (0xff642000 + (0x1aa << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_CHSTS3 (volatile uint32_t *)(0xff642000 + (0x1aa << 2)) ++#define EE_AUDIO_SPDIFOUT_B_CHSTS4 (0xff642000 + (0x1ab << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS4 (0xff642000 + (0x1ab << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_CHSTS4 (volatile uint32_t *)(0xff642000 + (0x1ab << 2)) ++#define EE_AUDIO_SPDIFOUT_B_CHSTS5 (0xff642000 + (0x1ac << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS5 (0xff642000 + (0x1ac << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_CHSTS5 (volatile uint32_t *)(0xff642000 + (0x1ac << 2)) ++#define EE_AUDIO_SPDIFOUT_B_CHSTS6 (0xff642000 + (0x1ad << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS6 (0xff642000 + (0x1ad << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_CHSTS6 (volatile uint32_t *)(0xff642000 + (0x1ad << 2)) ++#define EE_AUDIO_SPDIFOUT_B_CHSTS7 (0xff642000 + (0x1ae << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS7 (0xff642000 + (0x1ae << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_CHSTS7 (volatile uint32_t *)(0xff642000 + (0x1ae << 2)) ++#define EE_AUDIO_SPDIFOUT_B_CHSTS8 (0xff642000 + (0x1af << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS8 (0xff642000 + (0x1af << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_CHSTS8 (volatile uint32_t *)(0xff642000 + (0x1af << 2)) ++#define EE_AUDIO_SPDIFOUT_B_CHSTS9 (0xff642000 + (0x1b0 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS9 (0xff642000 + (0x1b0 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_CHSTS9 (volatile uint32_t *)(0xff642000 + (0x1b0 << 2)) ++#define EE_AUDIO_SPDIFOUT_B_CHSTSA (0xff642000 + (0x1b1 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTSA (0xff642000 + (0x1b1 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_CHSTSA (volatile uint32_t *)(0xff642000 + (0x1b1 << 2)) ++#define EE_AUDIO_SPDIFOUT_B_CHSTSB (0xff642000 + (0x1b2 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTSB (0xff642000 + (0x1b2 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_CHSTSB (volatile uint32_t *)(0xff642000 + (0x1b2 << 2)) ++#define EE_AUDIO_SPDIFOUT_B_MUTE_VAL (0xff642000 + (0x1b3 << 2)) ++#define SEC_EE_AUDIO_SPDIFOUT_B_MUTE_VAL (0xff642000 + (0x1b3 << 2)) ++#define P_EE_AUDIO_SPDIFOUT_B_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x1b3 << 2)) ++#define EE_AUDIO_TORAM_CTRL0 (0xff642000 + (0x1c0 << 2)) ++#define SEC_EE_AUDIO_TORAM_CTRL0 (0xff642000 + (0x1c0 << 2)) ++#define P_EE_AUDIO_TORAM_CTRL0 (volatile uint32_t *)(0xff642000 + (0x1c0 << 2)) ++#define EE_AUDIO_TORAM_CTRL1 (0xff642000 + (0x1c1 << 2)) ++#define SEC_EE_AUDIO_TORAM_CTRL1 (0xff642000 + (0x1c1 << 2)) ++#define P_EE_AUDIO_TORAM_CTRL1 (volatile uint32_t *)(0xff642000 + (0x1c1 << 2)) ++#define EE_AUDIO_TORAM_START_ADDR (0xff642000 + (0x1c2 << 2)) ++#define SEC_EE_AUDIO_TORAM_START_ADDR (0xff642000 + (0x1c2 << 2)) ++#define P_EE_AUDIO_TORAM_START_ADDR (volatile uint32_t *)(0xff642000 + (0x1c2 << 2)) ++#define EE_AUDIO_TORAM_FINISH_ADDR (0xff642000 + (0x1c3 << 2)) ++#define SEC_EE_AUDIO_TORAM_FINISH_ADDR (0xff642000 + (0x1c3 << 2)) ++#define P_EE_AUDIO_TORAM_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x1c3 << 2)) ++#define EE_AUDIO_TORAM_INT_ADDR (0xff642000 + (0x1c4 << 2)) ++#define SEC_EE_AUDIO_TORAM_INT_ADDR (0xff642000 + (0x1c4 << 2)) ++#define P_EE_AUDIO_TORAM_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x1c4 << 2)) ++#define EE_AUDIO_TORAM_STATUS1 (0xff642000 + (0x1c5 << 2)) ++#define SEC_EE_AUDIO_TORAM_STATUS1 (0xff642000 + (0x1c5 << 2)) ++#define P_EE_AUDIO_TORAM_STATUS1 (volatile uint32_t *)(0xff642000 + (0x1c5 << 2)) ++#define EE_AUDIO_TORAM_STATUS2 (0xff642000 + (0x1c6 << 2)) ++#define SEC_EE_AUDIO_TORAM_STATUS2 (0xff642000 + (0x1c6 << 2)) ++#define P_EE_AUDIO_TORAM_STATUS2 (volatile uint32_t *)(0xff642000 + (0x1c6 << 2)) ++#define EE_AUDIO_TORAM_INIT_ADDR (0xff642000 + (0x1c7 << 2)) ++#define SEC_EE_AUDIO_TORAM_INIT_ADDR (0xff642000 + (0x1c7 << 2)) ++#define P_EE_AUDIO_TORAM_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x1c7 << 2)) ++#define EE_AUDIO_TOACODEC_CTRL0 (0xff642000 + (0x1d0 << 2)) ++#define SEC_EE_AUDIO_TOACODEC_CTRL0 (0xff642000 + (0x1d0 << 2)) ++#define P_EE_AUDIO_TOACODEC_CTRL0 (volatile uint32_t *)(0xff642000 + (0x1d0 << 2)) ++#define EE_AUDIO_TOHDMITX_CTRL0 (0xff642000 + (0x1d1 << 2)) ++#define SEC_EE_AUDIO_TOHDMITX_CTRL0 (0xff642000 + (0x1d1 << 2)) ++#define P_EE_AUDIO_TOHDMITX_CTRL0 (volatile uint32_t *)(0xff642000 + (0x1d1 << 2)) ++//eq drc register ++#define AED_EQ_CH1_COEF00 (0xff642000 + (0x200 << 2)) ++#define SEC_AED_EQ_CH1_COEF00 (0xff642000 + (0x200 << 2)) ++#define P_AED_EQ_CH1_COEF00 (volatile uint32_t *)(0xff642000 + (0x200 << 2)) ++#define AED_EQ_CH1_COEF01 (0xff642000 + (0x201 << 2)) ++#define SEC_AED_EQ_CH1_COEF01 (0xff642000 + (0x201 << 2)) ++#define P_AED_EQ_CH1_COEF01 (volatile uint32_t *)(0xff642000 + (0x201 << 2)) ++#define AED_EQ_CH1_COEF02 (0xff642000 + (0x202 << 2)) ++#define SEC_AED_EQ_CH1_COEF02 (0xff642000 + (0x202 << 2)) ++#define P_AED_EQ_CH1_COEF02 (volatile uint32_t *)(0xff642000 + (0x202 << 2)) ++#define AED_EQ_CH1_COEF03 (0xff642000 + (0x203 << 2)) ++#define SEC_AED_EQ_CH1_COEF03 (0xff642000 + (0x203 << 2)) ++#define P_AED_EQ_CH1_COEF03 (volatile uint32_t *)(0xff642000 + (0x203 << 2)) ++#define AED_EQ_CH1_COEF04 (0xff642000 + (0x204 << 2)) ++#define SEC_AED_EQ_CH1_COEF04 (0xff642000 + (0x204 << 2)) ++#define P_AED_EQ_CH1_COEF04 (volatile uint32_t *)(0xff642000 + (0x204 << 2)) ++#define AED_EQ_CH1_COEF10 (0xff642000 + (0x205 << 2)) ++#define SEC_AED_EQ_CH1_COEF10 (0xff642000 + (0x205 << 2)) ++#define P_AED_EQ_CH1_COEF10 (volatile uint32_t *)(0xff642000 + (0x205 << 2)) ++#define AED_EQ_CH1_COEF11 (0xff642000 + (0x206 << 2)) ++#define SEC_AED_EQ_CH1_COEF11 (0xff642000 + (0x206 << 2)) ++#define P_AED_EQ_CH1_COEF11 (volatile uint32_t *)(0xff642000 + (0x206 << 2)) ++#define AED_EQ_CH1_COEF12 (0xff642000 + (0x207 << 2)) ++#define SEC_AED_EQ_CH1_COEF12 (0xff642000 + (0x207 << 2)) ++#define P_AED_EQ_CH1_COEF12 (volatile uint32_t *)(0xff642000 + (0x207 << 2)) ++#define AED_EQ_CH1_COEF13 (0xff642000 + (0x208 << 2)) ++#define SEC_AED_EQ_CH1_COEF13 (0xff642000 + (0x208 << 2)) ++#define P_AED_EQ_CH1_COEF13 (volatile uint32_t *)(0xff642000 + (0x208 << 2)) ++#define AED_EQ_CH1_COEF14 (0xff642000 + (0x209 << 2)) ++#define SEC_AED_EQ_CH1_COEF14 (0xff642000 + (0x209 << 2)) ++#define P_AED_EQ_CH1_COEF14 (volatile uint32_t *)(0xff642000 + (0x209 << 2)) ++#define AED_EQ_CH1_COEF20 (0xff642000 + (0x20a << 2)) ++#define SEC_AED_EQ_CH1_COEF20 (0xff642000 + (0x20a << 2)) ++#define P_AED_EQ_CH1_COEF20 (volatile uint32_t *)(0xff642000 + (0x20a << 2)) ++#define AED_EQ_CH1_COEF21 (0xff642000 + (0x20b << 2)) ++#define SEC_AED_EQ_CH1_COEF21 (0xff642000 + (0x20b << 2)) ++#define P_AED_EQ_CH1_COEF21 (volatile uint32_t *)(0xff642000 + (0x20b << 2)) ++#define AED_EQ_CH1_COEF22 (0xff642000 + (0x20c << 2)) ++#define SEC_AED_EQ_CH1_COEF22 (0xff642000 + (0x20c << 2)) ++#define P_AED_EQ_CH1_COEF22 (volatile uint32_t *)(0xff642000 + (0x20c << 2)) ++#define AED_EQ_CH1_COEF23 (0xff642000 + (0x20d << 2)) ++#define SEC_AED_EQ_CH1_COEF23 (0xff642000 + (0x20d << 2)) ++#define P_AED_EQ_CH1_COEF23 (volatile uint32_t *)(0xff642000 + (0x20d << 2)) ++#define AED_EQ_CH1_COEF24 (0xff642000 + (0x20e << 2)) ++#define SEC_AED_EQ_CH1_COEF24 (0xff642000 + (0x20e << 2)) ++#define P_AED_EQ_CH1_COEF24 (volatile uint32_t *)(0xff642000 + (0x20e << 2)) ++#define AED_EQ_CH1_COEF30 (0xff642000 + (0x20f << 2)) ++#define SEC_AED_EQ_CH1_COEF30 (0xff642000 + (0x20f << 2)) ++#define P_AED_EQ_CH1_COEF30 (volatile uint32_t *)(0xff642000 + (0x20f << 2)) ++#define AED_EQ_CH1_COEF31 (0xff642000 + (0x210 << 2)) ++#define SEC_AED_EQ_CH1_COEF31 (0xff642000 + (0x210 << 2)) ++#define P_AED_EQ_CH1_COEF31 (volatile uint32_t *)(0xff642000 + (0x210 << 2)) ++#define AED_EQ_CH1_COEF32 (0xff642000 + (0x211 << 2)) ++#define SEC_AED_EQ_CH1_COEF32 (0xff642000 + (0x211 << 2)) ++#define P_AED_EQ_CH1_COEF32 (volatile uint32_t *)(0xff642000 + (0x211 << 2)) ++#define AED_EQ_CH1_COEF33 (0xff642000 + (0x212 << 2)) ++#define SEC_AED_EQ_CH1_COEF33 (0xff642000 + (0x212 << 2)) ++#define P_AED_EQ_CH1_COEF33 (volatile uint32_t *)(0xff642000 + (0x212 << 2)) ++#define AED_EQ_CH1_COEF34 (0xff642000 + (0x213 << 2)) ++#define SEC_AED_EQ_CH1_COEF34 (0xff642000 + (0x213 << 2)) ++#define P_AED_EQ_CH1_COEF34 (volatile uint32_t *)(0xff642000 + (0x213 << 2)) ++#define AED_EQ_CH1_COEF40 (0xff642000 + (0x214 << 2)) ++#define SEC_AED_EQ_CH1_COEF40 (0xff642000 + (0x214 << 2)) ++#define P_AED_EQ_CH1_COEF40 (volatile uint32_t *)(0xff642000 + (0x214 << 2)) ++#define AED_EQ_CH1_COEF41 (0xff642000 + (0x215 << 2)) ++#define SEC_AED_EQ_CH1_COEF41 (0xff642000 + (0x215 << 2)) ++#define P_AED_EQ_CH1_COEF41 (volatile uint32_t *)(0xff642000 + (0x215 << 2)) ++#define AED_EQ_CH1_COEF42 (0xff642000 + (0x216 << 2)) ++#define SEC_AED_EQ_CH1_COEF42 (0xff642000 + (0x216 << 2)) ++#define P_AED_EQ_CH1_COEF42 (volatile uint32_t *)(0xff642000 + (0x216 << 2)) ++#define AED_EQ_CH1_COEF43 (0xff642000 + (0x217 << 2)) ++#define SEC_AED_EQ_CH1_COEF43 (0xff642000 + (0x217 << 2)) ++#define P_AED_EQ_CH1_COEF43 (volatile uint32_t *)(0xff642000 + (0x217 << 2)) ++#define AED_EQ_CH1_COEF44 (0xff642000 + (0x218 << 2)) ++#define SEC_AED_EQ_CH1_COEF44 (0xff642000 + (0x218 << 2)) ++#define P_AED_EQ_CH1_COEF44 (volatile uint32_t *)(0xff642000 + (0x218 << 2)) ++#define AED_EQ_CH1_COEF50 (0xff642000 + (0x219 << 2)) ++#define SEC_AED_EQ_CH1_COEF50 (0xff642000 + (0x219 << 2)) ++#define P_AED_EQ_CH1_COEF50 (volatile uint32_t *)(0xff642000 + (0x219 << 2)) ++#define AED_EQ_CH1_COEF51 (0xff642000 + (0x21a << 2)) ++#define SEC_AED_EQ_CH1_COEF51 (0xff642000 + (0x21a << 2)) ++#define P_AED_EQ_CH1_COEF51 (volatile uint32_t *)(0xff642000 + (0x21a << 2)) ++#define AED_EQ_CH1_COEF52 (0xff642000 + (0x21b << 2)) ++#define SEC_AED_EQ_CH1_COEF52 (0xff642000 + (0x21b << 2)) ++#define P_AED_EQ_CH1_COEF52 (volatile uint32_t *)(0xff642000 + (0x21b << 2)) ++#define AED_EQ_CH1_COEF53 (0xff642000 + (0x21c << 2)) ++#define SEC_AED_EQ_CH1_COEF53 (0xff642000 + (0x21c << 2)) ++#define P_AED_EQ_CH1_COEF53 (volatile uint32_t *)(0xff642000 + (0x21c << 2)) ++#define AED_EQ_CH1_COEF54 (0xff642000 + (0x21d << 2)) ++#define SEC_AED_EQ_CH1_COEF54 (0xff642000 + (0x21d << 2)) ++#define P_AED_EQ_CH1_COEF54 (volatile uint32_t *)(0xff642000 + (0x21d << 2)) ++#define AED_EQ_CH1_COEF60 (0xff642000 + (0x21e << 2)) ++#define SEC_AED_EQ_CH1_COEF60 (0xff642000 + (0x21e << 2)) ++#define P_AED_EQ_CH1_COEF60 (volatile uint32_t *)(0xff642000 + (0x21e << 2)) ++#define AED_EQ_CH1_COEF61 (0xff642000 + (0x21f << 2)) ++#define SEC_AED_EQ_CH1_COEF61 (0xff642000 + (0x21f << 2)) ++#define P_AED_EQ_CH1_COEF61 (volatile uint32_t *)(0xff642000 + (0x21f << 2)) ++#define AED_EQ_CH1_COEF62 (0xff642000 + (0x220 << 2)) ++#define SEC_AED_EQ_CH1_COEF62 (0xff642000 + (0x220 << 2)) ++#define P_AED_EQ_CH1_COEF62 (volatile uint32_t *)(0xff642000 + (0x220 << 2)) ++#define AED_EQ_CH1_COEF63 (0xff642000 + (0x221 << 2)) ++#define SEC_AED_EQ_CH1_COEF63 (0xff642000 + (0x221 << 2)) ++#define P_AED_EQ_CH1_COEF63 (volatile uint32_t *)(0xff642000 + (0x221 << 2)) ++#define AED_EQ_CH1_COEF64 (0xff642000 + (0x222 << 2)) ++#define SEC_AED_EQ_CH1_COEF64 (0xff642000 + (0x222 << 2)) ++#define P_AED_EQ_CH1_COEF64 (volatile uint32_t *)(0xff642000 + (0x222 << 2)) ++#define AED_EQ_CH1_COEF70 (0xff642000 + (0x223 << 2)) ++#define SEC_AED_EQ_CH1_COEF70 (0xff642000 + (0x223 << 2)) ++#define P_AED_EQ_CH1_COEF70 (volatile uint32_t *)(0xff642000 + (0x223 << 2)) ++#define AED_EQ_CH1_COEF71 (0xff642000 + (0x224 << 2)) ++#define SEC_AED_EQ_CH1_COEF71 (0xff642000 + (0x224 << 2)) ++#define P_AED_EQ_CH1_COEF71 (volatile uint32_t *)(0xff642000 + (0x224 << 2)) ++#define AED_EQ_CH1_COEF72 (0xff642000 + (0x225 << 2)) ++#define SEC_AED_EQ_CH1_COEF72 (0xff642000 + (0x225 << 2)) ++#define P_AED_EQ_CH1_COEF72 (volatile uint32_t *)(0xff642000 + (0x225 << 2)) ++#define AED_EQ_CH1_COEF73 (0xff642000 + (0x226 << 2)) ++#define SEC_AED_EQ_CH1_COEF73 (0xff642000 + (0x226 << 2)) ++#define P_AED_EQ_CH1_COEF73 (volatile uint32_t *)(0xff642000 + (0x226 << 2)) ++#define AED_EQ_CH1_COEF74 (0xff642000 + (0x227 << 2)) ++#define SEC_AED_EQ_CH1_COEF74 (0xff642000 + (0x227 << 2)) ++#define P_AED_EQ_CH1_COEF74 (volatile uint32_t *)(0xff642000 + (0x227 << 2)) ++#define AED_EQ_CH1_COEF80 (0xff642000 + (0x228 << 2)) ++#define SEC_AED_EQ_CH1_COEF80 (0xff642000 + (0x228 << 2)) ++#define P_AED_EQ_CH1_COEF80 (volatile uint32_t *)(0xff642000 + (0x228 << 2)) ++#define AED_EQ_CH1_COEF81 (0xff642000 + (0x229 << 2)) ++#define SEC_AED_EQ_CH1_COEF81 (0xff642000 + (0x229 << 2)) ++#define P_AED_EQ_CH1_COEF81 (volatile uint32_t *)(0xff642000 + (0x229 << 2)) ++#define AED_EQ_CH1_COEF82 (0xff642000 + (0x22a << 2)) ++#define SEC_AED_EQ_CH1_COEF82 (0xff642000 + (0x22a << 2)) ++#define P_AED_EQ_CH1_COEF82 (volatile uint32_t *)(0xff642000 + (0x22a << 2)) ++#define AED_EQ_CH1_COEF83 (0xff642000 + (0x22b << 2)) ++#define SEC_AED_EQ_CH1_COEF83 (0xff642000 + (0x22b << 2)) ++#define P_AED_EQ_CH1_COEF83 (volatile uint32_t *)(0xff642000 + (0x22b << 2)) ++#define AED_EQ_CH1_COEF84 (0xff642000 + (0x22c << 2)) ++#define SEC_AED_EQ_CH1_COEF84 (0xff642000 + (0x22c << 2)) ++#define P_AED_EQ_CH1_COEF84 (volatile uint32_t *)(0xff642000 + (0x22c << 2)) ++#define AED_EQ_CH1_COEF90 (0xff642000 + (0x22d << 2)) ++#define SEC_AED_EQ_CH1_COEF90 (0xff642000 + (0x22d << 2)) ++#define P_AED_EQ_CH1_COEF90 (volatile uint32_t *)(0xff642000 + (0x22d << 2)) ++#define AED_EQ_CH1_COEF91 (0xff642000 + (0x22e << 2)) ++#define SEC_AED_EQ_CH1_COEF91 (0xff642000 + (0x22e << 2)) ++#define P_AED_EQ_CH1_COEF91 (volatile uint32_t *)(0xff642000 + (0x22e << 2)) ++#define AED_EQ_CH1_COEF92 (0xff642000 + (0x22f << 2)) ++#define SEC_AED_EQ_CH1_COEF92 (0xff642000 + (0x22f << 2)) ++#define P_AED_EQ_CH1_COEF92 (volatile uint32_t *)(0xff642000 + (0x22f << 2)) ++#define AED_EQ_CH1_COEF93 (0xff642000 + (0x230 << 2)) ++#define SEC_AED_EQ_CH1_COEF93 (0xff642000 + (0x230 << 2)) ++#define P_AED_EQ_CH1_COEF93 (volatile uint32_t *)(0xff642000 + (0x230 << 2)) ++#define AED_EQ_CH1_COEF94 (0xff642000 + (0x231 << 2)) ++#define SEC_AED_EQ_CH1_COEF94 (0xff642000 + (0x231 << 2)) ++#define P_AED_EQ_CH1_COEF94 (volatile uint32_t *)(0xff642000 + (0x231 << 2)) ++#define AED_EQ_CH2_COEF00 (0xff642000 + (0x232 << 2)) ++#define SEC_AED_EQ_CH2_COEF00 (0xff642000 + (0x232 << 2)) ++#define P_AED_EQ_CH2_COEF00 (volatile uint32_t *)(0xff642000 + (0x232 << 2)) ++#define AED_EQ_CH2_COEF01 (0xff642000 + (0x233 << 2)) ++#define SEC_AED_EQ_CH2_COEF01 (0xff642000 + (0x233 << 2)) ++#define P_AED_EQ_CH2_COEF01 (volatile uint32_t *)(0xff642000 + (0x233 << 2)) ++#define AED_EQ_CH2_COEF02 (0xff642000 + (0x234 << 2)) ++#define SEC_AED_EQ_CH2_COEF02 (0xff642000 + (0x234 << 2)) ++#define P_AED_EQ_CH2_COEF02 (volatile uint32_t *)(0xff642000 + (0x234 << 2)) ++#define AED_EQ_CH2_COEF03 (0xff642000 + (0x235 << 2)) ++#define SEC_AED_EQ_CH2_COEF03 (0xff642000 + (0x235 << 2)) ++#define P_AED_EQ_CH2_COEF03 (volatile uint32_t *)(0xff642000 + (0x235 << 2)) ++#define AED_EQ_CH2_COEF04 (0xff642000 + (0x236 << 2)) ++#define SEC_AED_EQ_CH2_COEF04 (0xff642000 + (0x236 << 2)) ++#define P_AED_EQ_CH2_COEF04 (volatile uint32_t *)(0xff642000 + (0x236 << 2)) ++#define AED_EQ_CH2_COEF10 (0xff642000 + (0x237 << 2)) ++#define SEC_AED_EQ_CH2_COEF10 (0xff642000 + (0x237 << 2)) ++#define P_AED_EQ_CH2_COEF10 (volatile uint32_t *)(0xff642000 + (0x237 << 2)) ++#define AED_EQ_CH2_COEF11 (0xff642000 + (0x238 << 2)) ++#define SEC_AED_EQ_CH2_COEF11 (0xff642000 + (0x238 << 2)) ++#define P_AED_EQ_CH2_COEF11 (volatile uint32_t *)(0xff642000 + (0x238 << 2)) ++#define AED_EQ_CH2_COEF12 (0xff642000 + (0x239 << 2)) ++#define SEC_AED_EQ_CH2_COEF12 (0xff642000 + (0x239 << 2)) ++#define P_AED_EQ_CH2_COEF12 (volatile uint32_t *)(0xff642000 + (0x239 << 2)) ++#define AED_EQ_CH2_COEF13 (0xff642000 + (0x23a << 2)) ++#define SEC_AED_EQ_CH2_COEF13 (0xff642000 + (0x23a << 2)) ++#define P_AED_EQ_CH2_COEF13 (volatile uint32_t *)(0xff642000 + (0x23a << 2)) ++#define AED_EQ_CH2_COEF14 (0xff642000 + (0x23b << 2)) ++#define SEC_AED_EQ_CH2_COEF14 (0xff642000 + (0x23b << 2)) ++#define P_AED_EQ_CH2_COEF14 (volatile uint32_t *)(0xff642000 + (0x23b << 2)) ++#define AED_EQ_CH2_COEF20 (0xff642000 + (0x23c << 2)) ++#define SEC_AED_EQ_CH2_COEF20 (0xff642000 + (0x23c << 2)) ++#define P_AED_EQ_CH2_COEF20 (volatile uint32_t *)(0xff642000 + (0x23c << 2)) ++#define AED_EQ_CH2_COEF21 (0xff642000 + (0x23d << 2)) ++#define SEC_AED_EQ_CH2_COEF21 (0xff642000 + (0x23d << 2)) ++#define P_AED_EQ_CH2_COEF21 (volatile uint32_t *)(0xff642000 + (0x23d << 2)) ++#define AED_EQ_CH2_COEF22 (0xff642000 + (0x23e << 2)) ++#define SEC_AED_EQ_CH2_COEF22 (0xff642000 + (0x23e << 2)) ++#define P_AED_EQ_CH2_COEF22 (volatile uint32_t *)(0xff642000 + (0x23e << 2)) ++#define AED_EQ_CH2_COEF23 (0xff642000 + (0x23f << 2)) ++#define SEC_AED_EQ_CH2_COEF23 (0xff642000 + (0x23f << 2)) ++#define P_AED_EQ_CH2_COEF23 (volatile uint32_t *)(0xff642000 + (0x23f << 2)) ++#define AED_EQ_CH2_COEF24 (0xff642000 + (0x240 << 2)) ++#define SEC_AED_EQ_CH2_COEF24 (0xff642000 + (0x240 << 2)) ++#define P_AED_EQ_CH2_COEF24 (volatile uint32_t *)(0xff642000 + (0x240 << 2)) ++#define AED_EQ_CH2_COEF30 (0xff642000 + (0x241 << 2)) ++#define SEC_AED_EQ_CH2_COEF30 (0xff642000 + (0x241 << 2)) ++#define P_AED_EQ_CH2_COEF30 (volatile uint32_t *)(0xff642000 + (0x241 << 2)) ++#define AED_EQ_CH2_COEF31 (0xff642000 + (0x242 << 2)) ++#define SEC_AED_EQ_CH2_COEF31 (0xff642000 + (0x242 << 2)) ++#define P_AED_EQ_CH2_COEF31 (volatile uint32_t *)(0xff642000 + (0x242 << 2)) ++#define AED_EQ_CH2_COEF32 (0xff642000 + (0x243 << 2)) ++#define SEC_AED_EQ_CH2_COEF32 (0xff642000 + (0x243 << 2)) ++#define P_AED_EQ_CH2_COEF32 (volatile uint32_t *)(0xff642000 + (0x243 << 2)) ++#define AED_EQ_CH2_COEF33 (0xff642000 + (0x244 << 2)) ++#define SEC_AED_EQ_CH2_COEF33 (0xff642000 + (0x244 << 2)) ++#define P_AED_EQ_CH2_COEF33 (volatile uint32_t *)(0xff642000 + (0x244 << 2)) ++#define AED_EQ_CH2_COEF34 (0xff642000 + (0x245 << 2)) ++#define SEC_AED_EQ_CH2_COEF34 (0xff642000 + (0x245 << 2)) ++#define P_AED_EQ_CH2_COEF34 (volatile uint32_t *)(0xff642000 + (0x245 << 2)) ++#define AED_EQ_CH2_COEF40 (0xff642000 + (0x246 << 2)) ++#define SEC_AED_EQ_CH2_COEF40 (0xff642000 + (0x246 << 2)) ++#define P_AED_EQ_CH2_COEF40 (volatile uint32_t *)(0xff642000 + (0x246 << 2)) ++#define AED_EQ_CH2_COEF41 (0xff642000 + (0x247 << 2)) ++#define SEC_AED_EQ_CH2_COEF41 (0xff642000 + (0x247 << 2)) ++#define P_AED_EQ_CH2_COEF41 (volatile uint32_t *)(0xff642000 + (0x247 << 2)) ++#define AED_EQ_CH2_COEF42 (0xff642000 + (0x248 << 2)) ++#define SEC_AED_EQ_CH2_COEF42 (0xff642000 + (0x248 << 2)) ++#define P_AED_EQ_CH2_COEF42 (volatile uint32_t *)(0xff642000 + (0x248 << 2)) ++#define AED_EQ_CH2_COEF43 (0xff642000 + (0x249 << 2)) ++#define SEC_AED_EQ_CH2_COEF43 (0xff642000 + (0x249 << 2)) ++#define P_AED_EQ_CH2_COEF43 (volatile uint32_t *)(0xff642000 + (0x249 << 2)) ++#define AED_EQ_CH2_COEF44 (0xff642000 + (0x24a << 2)) ++#define SEC_AED_EQ_CH2_COEF44 (0xff642000 + (0x24a << 2)) ++#define P_AED_EQ_CH2_COEF44 (volatile uint32_t *)(0xff642000 + (0x24a << 2)) ++#define AED_EQ_CH2_COEF50 (0xff642000 + (0x24b << 2)) ++#define SEC_AED_EQ_CH2_COEF50 (0xff642000 + (0x24b << 2)) ++#define P_AED_EQ_CH2_COEF50 (volatile uint32_t *)(0xff642000 + (0x24b << 2)) ++#define AED_EQ_CH2_COEF51 (0xff642000 + (0x24c << 2)) ++#define SEC_AED_EQ_CH2_COEF51 (0xff642000 + (0x24c << 2)) ++#define P_AED_EQ_CH2_COEF51 (volatile uint32_t *)(0xff642000 + (0x24c << 2)) ++#define AED_EQ_CH2_COEF52 (0xff642000 + (0x24d << 2)) ++#define SEC_AED_EQ_CH2_COEF52 (0xff642000 + (0x24d << 2)) ++#define P_AED_EQ_CH2_COEF52 (volatile uint32_t *)(0xff642000 + (0x24d << 2)) ++#define AED_EQ_CH2_COEF53 (0xff642000 + (0x24e << 2)) ++#define SEC_AED_EQ_CH2_COEF53 (0xff642000 + (0x24e << 2)) ++#define P_AED_EQ_CH2_COEF53 (volatile uint32_t *)(0xff642000 + (0x24e << 2)) ++#define AED_EQ_CH2_COEF54 (0xff642000 + (0x24f << 2)) ++#define SEC_AED_EQ_CH2_COEF54 (0xff642000 + (0x24f << 2)) ++#define P_AED_EQ_CH2_COEF54 (volatile uint32_t *)(0xff642000 + (0x24f << 2)) ++#define AED_EQ_CH2_COEF60 (0xff642000 + (0x250 << 2)) ++#define SEC_AED_EQ_CH2_COEF60 (0xff642000 + (0x250 << 2)) ++#define P_AED_EQ_CH2_COEF60 (volatile uint32_t *)(0xff642000 + (0x250 << 2)) ++#define AED_EQ_CH2_COEF61 (0xff642000 + (0x251 << 2)) ++#define SEC_AED_EQ_CH2_COEF61 (0xff642000 + (0x251 << 2)) ++#define P_AED_EQ_CH2_COEF61 (volatile uint32_t *)(0xff642000 + (0x251 << 2)) ++#define AED_EQ_CH2_COEF62 (0xff642000 + (0x252 << 2)) ++#define SEC_AED_EQ_CH2_COEF62 (0xff642000 + (0x252 << 2)) ++#define P_AED_EQ_CH2_COEF62 (volatile uint32_t *)(0xff642000 + (0x252 << 2)) ++#define AED_EQ_CH2_COEF63 (0xff642000 + (0x253 << 2)) ++#define SEC_AED_EQ_CH2_COEF63 (0xff642000 + (0x253 << 2)) ++#define P_AED_EQ_CH2_COEF63 (volatile uint32_t *)(0xff642000 + (0x253 << 2)) ++#define AED_EQ_CH2_COEF64 (0xff642000 + (0x254 << 2)) ++#define SEC_AED_EQ_CH2_COEF64 (0xff642000 + (0x254 << 2)) ++#define P_AED_EQ_CH2_COEF64 (volatile uint32_t *)(0xff642000 + (0x254 << 2)) ++#define AED_EQ_CH2_COEF70 (0xff642000 + (0x255 << 2)) ++#define SEC_AED_EQ_CH2_COEF70 (0xff642000 + (0x255 << 2)) ++#define P_AED_EQ_CH2_COEF70 (volatile uint32_t *)(0xff642000 + (0x255 << 2)) ++#define AED_EQ_CH2_COEF71 (0xff642000 + (0x256 << 2)) ++#define SEC_AED_EQ_CH2_COEF71 (0xff642000 + (0x256 << 2)) ++#define P_AED_EQ_CH2_COEF71 (volatile uint32_t *)(0xff642000 + (0x256 << 2)) ++#define AED_EQ_CH2_COEF72 (0xff642000 + (0x257 << 2)) ++#define SEC_AED_EQ_CH2_COEF72 (0xff642000 + (0x257 << 2)) ++#define P_AED_EQ_CH2_COEF72 (volatile uint32_t *)(0xff642000 + (0x257 << 2)) ++#define AED_EQ_CH2_COEF73 (0xff642000 + (0x258 << 2)) ++#define SEC_AED_EQ_CH2_COEF73 (0xff642000 + (0x258 << 2)) ++#define P_AED_EQ_CH2_COEF73 (volatile uint32_t *)(0xff642000 + (0x258 << 2)) ++#define AED_EQ_CH2_COEF74 (0xff642000 + (0x259 << 2)) ++#define SEC_AED_EQ_CH2_COEF74 (0xff642000 + (0x259 << 2)) ++#define P_AED_EQ_CH2_COEF74 (volatile uint32_t *)(0xff642000 + (0x259 << 2)) ++#define AED_EQ_CH2_COEF80 (0xff642000 + (0x25a << 2)) ++#define SEC_AED_EQ_CH2_COEF80 (0xff642000 + (0x25a << 2)) ++#define P_AED_EQ_CH2_COEF80 (volatile uint32_t *)(0xff642000 + (0x25a << 2)) ++#define AED_EQ_CH2_COEF81 (0xff642000 + (0x25b << 2)) ++#define SEC_AED_EQ_CH2_COEF81 (0xff642000 + (0x25b << 2)) ++#define P_AED_EQ_CH2_COEF81 (volatile uint32_t *)(0xff642000 + (0x25b << 2)) ++#define AED_EQ_CH2_COEF82 (0xff642000 + (0x25c << 2)) ++#define SEC_AED_EQ_CH2_COEF82 (0xff642000 + (0x25c << 2)) ++#define P_AED_EQ_CH2_COEF82 (volatile uint32_t *)(0xff642000 + (0x25c << 2)) ++#define AED_EQ_CH2_COEF83 (0xff642000 + (0x25d << 2)) ++#define SEC_AED_EQ_CH2_COEF83 (0xff642000 + (0x25d << 2)) ++#define P_AED_EQ_CH2_COEF83 (volatile uint32_t *)(0xff642000 + (0x25d << 2)) ++#define AED_EQ_CH2_COEF84 (0xff642000 + (0x25e << 2)) ++#define SEC_AED_EQ_CH2_COEF84 (0xff642000 + (0x25e << 2)) ++#define P_AED_EQ_CH2_COEF84 (volatile uint32_t *)(0xff642000 + (0x25e << 2)) ++#define AED_EQ_CH2_COEF90 (0xff642000 + (0x25f << 2)) ++#define SEC_AED_EQ_CH2_COEF90 (0xff642000 + (0x25f << 2)) ++#define P_AED_EQ_CH2_COEF90 (volatile uint32_t *)(0xff642000 + (0x25f << 2)) ++#define AED_EQ_CH2_COEF91 (0xff642000 + (0x260 << 2)) ++#define SEC_AED_EQ_CH2_COEF91 (0xff642000 + (0x260 << 2)) ++#define P_AED_EQ_CH2_COEF91 (volatile uint32_t *)(0xff642000 + (0x260 << 2)) ++#define AED_EQ_CH2_COEF92 (0xff642000 + (0x261 << 2)) ++#define SEC_AED_EQ_CH2_COEF92 (0xff642000 + (0x261 << 2)) ++#define P_AED_EQ_CH2_COEF92 (volatile uint32_t *)(0xff642000 + (0x261 << 2)) ++#define AED_EQ_CH2_COEF93 (0xff642000 + (0x262 << 2)) ++#define SEC_AED_EQ_CH2_COEF93 (0xff642000 + (0x262 << 2)) ++#define P_AED_EQ_CH2_COEF93 (volatile uint32_t *)(0xff642000 + (0x262 << 2)) ++#define AED_EQ_CH2_COEF94 (0xff642000 + (0x263 << 2)) ++#define SEC_AED_EQ_CH2_COEF94 (0xff642000 + (0x263 << 2)) ++#define P_AED_EQ_CH2_COEF94 (volatile uint32_t *)(0xff642000 + (0x263 << 2)) ++#define AED_EQ_EN (0xff642000 + (0x264 << 2)) ++#define SEC_AED_EQ_EN (0xff642000 + (0x264 << 2)) ++#define P_AED_EQ_EN (volatile uint32_t *)(0xff642000 + (0x264 << 2)) ++#define AED_EQ_VOLUME (0xff642000 + (0x265 << 2)) ++#define SEC_AED_EQ_VOLUME (0xff642000 + (0x265 << 2)) ++#define P_AED_EQ_VOLUME (volatile uint32_t *)(0xff642000 + (0x265 << 2)) ++#define AED_EQ_VOLUME_SLEW_CNT (0xff642000 + (0x266 << 2)) ++#define SEC_AED_EQ_VOLUME_SLEW_CNT (0xff642000 + (0x266 << 2)) ++#define P_AED_EQ_VOLUME_SLEW_CNT (volatile uint32_t *)(0xff642000 + (0x266 << 2)) ++#define AED_MUTE (0xff642000 + (0x267 << 2)) ++#define SEC_AED_MUTE (0xff642000 + (0x267 << 2)) ++#define P_AED_MUTE (volatile uint32_t *)(0xff642000 + (0x267 << 2)) ++#define AED_DRC_EN (0xff642000 + (0x268 << 2)) ++#define SEC_AED_DRC_EN (0xff642000 + (0x268 << 2)) ++#define P_AED_DRC_EN (volatile uint32_t *)(0xff642000 + (0x268 << 2)) ++#define AED_DRC_AE (0xff642000 + (0x269 << 2)) ++#define SEC_AED_DRC_AE (0xff642000 + (0x269 << 2)) ++#define P_AED_DRC_AE (volatile uint32_t *)(0xff642000 + (0x269 << 2)) ++#define AED_DRC_AA (0xff642000 + (0x26a << 2)) ++#define SEC_AED_DRC_AA (0xff642000 + (0x26a << 2)) ++#define P_AED_DRC_AA (volatile uint32_t *)(0xff642000 + (0x26a << 2)) ++#define AED_DRC_AD (0xff642000 + (0x26b << 2)) ++#define SEC_AED_DRC_AD (0xff642000 + (0x26b << 2)) ++#define P_AED_DRC_AD (volatile uint32_t *)(0xff642000 + (0x26b << 2)) ++#define AED_DRC_AE_1M (0xff642000 + (0x26c << 2)) ++#define SEC_AED_DRC_AE_1M (0xff642000 + (0x26c << 2)) ++#define P_AED_DRC_AE_1M (volatile uint32_t *)(0xff642000 + (0x26c << 2)) ++#define AED_DRC_AA_1M (0xff642000 + (0x26d << 2)) ++#define SEC_AED_DRC_AA_1M (0xff642000 + (0x26d << 2)) ++#define P_AED_DRC_AA_1M (volatile uint32_t *)(0xff642000 + (0x26d << 2)) ++#define AED_DRC_AD_1M (0xff642000 + (0x26e << 2)) ++#define SEC_AED_DRC_AD_1M (0xff642000 + (0x26e << 2)) ++#define P_AED_DRC_AD_1M (volatile uint32_t *)(0xff642000 + (0x26e << 2)) ++#define AED_DRC_OFFSET0 (0xff642000 + (0x26f << 2)) ++#define SEC_AED_DRC_OFFSET0 (0xff642000 + (0x26f << 2)) ++#define P_AED_DRC_OFFSET0 (volatile uint32_t *)(0xff642000 + (0x26f << 2)) ++#define AED_DRC_OFFSET1 (0xff642000 + (0x270 << 2)) ++#define SEC_AED_DRC_OFFSET1 (0xff642000 + (0x270 << 2)) ++#define P_AED_DRC_OFFSET1 (volatile uint32_t *)(0xff642000 + (0x270 << 2)) ++#define AED_DRC_THD0 (0xff642000 + (0x271 << 2)) ++#define SEC_AED_DRC_THD0 (0xff642000 + (0x271 << 2)) ++#define P_AED_DRC_THD0 (volatile uint32_t *)(0xff642000 + (0x271 << 2)) ++#define AED_DRC_THD1 (0xff642000 + (0x272 << 2)) ++#define SEC_AED_DRC_THD1 (0xff642000 + (0x272 << 2)) ++#define P_AED_DRC_THD1 (volatile uint32_t *)(0xff642000 + (0x272 << 2)) ++#define AED_DRC_K0 (0xff642000 + (0x273 << 2)) ++#define SEC_AED_DRC_K0 (0xff642000 + (0x273 << 2)) ++#define P_AED_DRC_K0 (volatile uint32_t *)(0xff642000 + (0x273 << 2)) ++#define AED_DRC_K1 (0xff642000 + (0x274 << 2)) ++#define SEC_AED_DRC_K1 (0xff642000 + (0x274 << 2)) ++#define P_AED_DRC_K1 (volatile uint32_t *)(0xff642000 + (0x274 << 2)) ++#define AED_CLIP_THD (0xff642000 + (0x275 << 2)) ++#define SEC_AED_CLIP_THD (0xff642000 + (0x275 << 2)) ++#define P_AED_CLIP_THD (volatile uint32_t *)(0xff642000 + (0x275 << 2)) ++#define AED_NG_THD0 (0xff642000 + (0x276 << 2)) ++#define SEC_AED_NG_THD0 (0xff642000 + (0x276 << 2)) ++#define P_AED_NG_THD0 (volatile uint32_t *)(0xff642000 + (0x276 << 2)) ++#define AED_NG_THD1 (0xff642000 + (0x277 << 2)) ++#define SEC_AED_NG_THD1 (0xff642000 + (0x277 << 2)) ++#define P_AED_NG_THD1 (volatile uint32_t *)(0xff642000 + (0x277 << 2)) ++#define AED_NG_CNT_THD (0xff642000 + (0x278 << 2)) ++#define SEC_AED_NG_CNT_THD (0xff642000 + (0x278 << 2)) ++#define P_AED_NG_CNT_THD (volatile uint32_t *)(0xff642000 + (0x278 << 2)) ++#define AED_NG_CTL (0xff642000 + (0x279 << 2)) ++#define SEC_AED_NG_CTL (0xff642000 + (0x279 << 2)) ++#define P_AED_NG_CTL (volatile uint32_t *)(0xff642000 + (0x279 << 2)) ++#define AED_ED_CTL (0xff642000 + (0x27a << 2)) ++#define SEC_AED_ED_CTL (0xff642000 + (0x27a << 2)) ++#define P_AED_ED_CTL (volatile uint32_t *)(0xff642000 + (0x27a << 2)) ++#define AED_DEBUG0 (0xff642000 + (0x27b << 2)) ++#define SEC_AED_DEBUG0 (0xff642000 + (0x27b << 2)) ++#define P_AED_DEBUG0 (volatile uint32_t *)(0xff642000 + (0x27b << 2)) ++#define AED_DEBUG1 (0xff642000 + (0x27c << 2)) ++#define SEC_AED_DEBUG1 (0xff642000 + (0x27c << 2)) ++#define P_AED_DEBUG1 (volatile uint32_t *)(0xff642000 + (0x27c << 2)) ++#define AED_DEBUG2 (0xff642000 + (0x27d << 2)) ++#define SEC_AED_DEBUG2 (0xff642000 + (0x27d << 2)) ++#define P_AED_DEBUG2 (volatile uint32_t *)(0xff642000 + (0x27d << 2)) ++#define AED_DEBUG3 (0xff642000 + (0x27e << 2)) ++#define SEC_AED_DEBUG3 (0xff642000 + (0x27e << 2)) ++#define P_AED_DEBUG3 (volatile uint32_t *)(0xff642000 + (0x27e << 2)) ++#define AED_DEBUG4 (0xff642000 + (0x27f << 2)) ++#define SEC_AED_DEBUG4 (0xff642000 + (0x27f << 2)) ++#define P_AED_DEBUG4 (volatile uint32_t *)(0xff642000 + (0x27f << 2)) ++#define AED_DEBUG5 (0xff642000 + (0x280 << 2)) ++#define SEC_AED_DEBUG5 (0xff642000 + (0x280 << 2)) ++#define P_AED_DEBUG5 (volatile uint32_t *)(0xff642000 + (0x280 << 2)) ++#define AED_DEBUG6 (0xff642000 + (0x281 << 2)) ++#define SEC_AED_DEBUG6 (0xff642000 + (0x281 << 2)) ++#define P_AED_DEBUG6 (volatile uint32_t *)(0xff642000 + (0x281 << 2)) ++#define AED_DRC_AA_H (0xff642000 + (0x282 << 2)) ++#define SEC_AED_DRC_AA_H (0xff642000 + (0x282 << 2)) ++#define P_AED_DRC_AA_H (volatile uint32_t *)(0xff642000 + (0x282 << 2)) ++#define AED_DRC_AD_H (0xff642000 + (0x283 << 2)) ++#define SEC_AED_DRC_AD_H (0xff642000 + (0x283 << 2)) ++#define P_AED_DRC_AD_H (volatile uint32_t *)(0xff642000 + (0x283 << 2)) ++#define AED_DRC_AA_1M_H (0xff642000 + (0x284 << 2)) ++#define SEC_AED_DRC_AA_1M_H (0xff642000 + (0x284 << 2)) ++#define P_AED_DRC_AA_1M_H (volatile uint32_t *)(0xff642000 + (0x284 << 2)) ++#define AED_DRC_AD_1M_H (0xff642000 + (0x285 << 2)) ++#define SEC_AED_DRC_AD_1M_H (0xff642000 + (0x285 << 2)) ++#define P_AED_DRC_AD_1M_H (volatile uint32_t *)(0xff642000 + (0x285 << 2)) ++#define AED_NG_CNT (0xff642000 + (0x286 << 2)) ++#define SEC_AED_NG_CNT (0xff642000 + (0x286 << 2)) ++#define P_AED_NG_CNT (volatile uint32_t *)(0xff642000 + (0x286 << 2)) ++#define AED_NG_STEP (0xff642000 + (0x287 << 2)) ++#define SEC_AED_NG_STEP (0xff642000 + (0x287 << 2)) ++#define P_AED_NG_STEP (volatile uint32_t *)(0xff642000 + (0x287 << 2)) ++#define AED_TOP_CTL (0xff642000 + (0x288 << 2)) ++#define SEC_AED_TOP_CTL (0xff642000 + (0x288 << 2)) ++#define P_AED_TOP_CTL (volatile uint32_t *)(0xff642000 + (0x288 << 2)) ++#define AED_TOP_REQ_CTL (0xff642000 + (0x289 << 2)) ++#define SEC_AED_TOP_REQ_CTL (0xff642000 + (0x289 << 2)) ++#define P_AED_TOP_REQ_CTL (volatile uint32_t *)(0xff642000 + (0x289 << 2)) ++//======================================================================== ++// HIU - Registers ++//======================================================================== ++// APB4_DECODER_NON_SECURE_BASE 32'hFF63C000 ++// APB4_DECODER_SECURE_BASE 32'hFF63C000 ++#define HHI_MIPI_CNTL0 (0xff63c000 + (0x000 << 2)) ++#define SEC_HHI_MIPI_CNTL0 (0xff63c000 + (0x000 << 2)) ++#define P_HHI_MIPI_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x000 << 2)) ++#define HHI_MIPI_CNTL1 (0xff63c000 + (0x001 << 2)) ++#define SEC_HHI_MIPI_CNTL1 (0xff63c000 + (0x001 << 2)) ++#define P_HHI_MIPI_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x001 << 2)) ++#define HHI_MIPI_CNTL2 (0xff63c000 + (0x002 << 2)) ++#define SEC_HHI_MIPI_CNTL2 (0xff63c000 + (0x002 << 2)) ++#define P_HHI_MIPI_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x002 << 2)) ++#define HHI_MIPI_STS (0xff63c000 + (0x003 << 2)) ++#define SEC_HHI_MIPI_STS (0xff63c000 + (0x003 << 2)) ++#define P_HHI_MIPI_STS (volatile uint32_t *)(0xff63c000 + (0x003 << 2)) ++#define HHI_CHECK_CLK_RESULT (0xff63c000 + (0x004 << 2)) ++#define SEC_HHI_CHECK_CLK_RESULT (0xff63c000 + (0x004 << 2)) ++#define P_HHI_CHECK_CLK_RESULT (volatile uint32_t *)(0xff63c000 + (0x004 << 2)) ++#define SCR_HIU (0xff63c000 + (0x00b << 2)) ++#define SEC_SCR_HIU (0xff63c000 + (0x00b << 2)) ++#define P_SCR_HIU (volatile uint32_t *)(0xff63c000 + (0x00b << 2)) ++//`define HHI_SYS_STS 8'h0c ++#define HPG_TIMER (0xff63c000 + (0x00f << 2)) ++#define SEC_HPG_TIMER (0xff63c000 + (0x00f << 2)) ++#define P_HPG_TIMER (volatile uint32_t *)(0xff63c000 + (0x00f << 2)) ++#define HHI_GP0_PLL_CNTL0 (0xff63c000 + (0x010 << 2)) ++#define SEC_HHI_GP0_PLL_CNTL0 (0xff63c000 + (0x010 << 2)) ++#define P_HHI_GP0_PLL_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x010 << 2)) ++#define HHI_GP0_PLL_CNTL1 (0xff63c000 + (0x011 << 2)) ++#define SEC_HHI_GP0_PLL_CNTL1 (0xff63c000 + (0x011 << 2)) ++#define P_HHI_GP0_PLL_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x011 << 2)) ++#define HHI_GP0_PLL_CNTL2 (0xff63c000 + (0x012 << 2)) ++#define SEC_HHI_GP0_PLL_CNTL2 (0xff63c000 + (0x012 << 2)) ++#define P_HHI_GP0_PLL_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x012 << 2)) ++#define HHI_GP0_PLL_CNTL3 (0xff63c000 + (0x013 << 2)) ++#define SEC_HHI_GP0_PLL_CNTL3 (0xff63c000 + (0x013 << 2)) ++#define P_HHI_GP0_PLL_CNTL3 (volatile uint32_t *)(0xff63c000 + (0x013 << 2)) ++#define HHI_GP0_PLL_CNTL4 (0xff63c000 + (0x014 << 2)) ++#define SEC_HHI_GP0_PLL_CNTL4 (0xff63c000 + (0x014 << 2)) ++#define P_HHI_GP0_PLL_CNTL4 (volatile uint32_t *)(0xff63c000 + (0x014 << 2)) ++#define HHI_GP0_PLL_CNTL5 (0xff63c000 + (0x015 << 2)) ++#define SEC_HHI_GP0_PLL_CNTL5 (0xff63c000 + (0x015 << 2)) ++#define P_HHI_GP0_PLL_CNTL5 (volatile uint32_t *)(0xff63c000 + (0x015 << 2)) ++#define HHI_GP0_PLL_CNTL6 (0xff63c000 + (0x016 << 2)) ++#define SEC_HHI_GP0_PLL_CNTL6 (0xff63c000 + (0x016 << 2)) ++#define P_HHI_GP0_PLL_CNTL6 (volatile uint32_t *)(0xff63c000 + (0x016 << 2)) ++#define HHI_GP0_PLL_STS (0xff63c000 + (0x017 << 2)) ++#define SEC_HHI_GP0_PLL_STS (0xff63c000 + (0x017 << 2)) ++#define P_HHI_GP0_PLL_STS (volatile uint32_t *)(0xff63c000 + (0x017 << 2)) ++//`define HHI_GP1_PLL_CNTL0 8'h18 ++//`define HHI_GP1_PLL_CNTL1 8'h19 ++//`define HHI_GP1_PLL_CNTL2 8'h1a ++//`define HHI_GP1_PLL_CNTL3 8'h1b ++//`define HHI_GP1_PLL_CNTL4 8'h1c ++//`define HHI_GP1_PLL_CNTL5 8'h1d ++//`define HHI_GP1_PLL_CNTL6 8'h1e ++//`define HHI_GP1_PLL_STS 8'h1f ++//`define HHI_CADC_CNTL 8'h20 ++//`define HHI_CADC_CNTL2 8'h21 ++//`define HHI_CADC_CNTL3 8'h22 ++//`define HHI_CADC_CNTL4 8'h23 ++//`define HHI_CADC_CNTL5 8'h24 ++//`define HHI_CADC_CNTL6 8'h25 ++#define HHI_PCIE_PLL_CNTL0 (0xff63c000 + (0x026 << 2)) ++#define SEC_HHI_PCIE_PLL_CNTL0 (0xff63c000 + (0x026 << 2)) ++#define P_HHI_PCIE_PLL_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x026 << 2)) ++#define HHI_PCIE_PLL_CNTL1 (0xff63c000 + (0x027 << 2)) ++#define SEC_HHI_PCIE_PLL_CNTL1 (0xff63c000 + (0x027 << 2)) ++#define P_HHI_PCIE_PLL_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x027 << 2)) ++#define HHI_PCIE_PLL_CNTL2 (0xff63c000 + (0x028 << 2)) ++#define SEC_HHI_PCIE_PLL_CNTL2 (0xff63c000 + (0x028 << 2)) ++#define P_HHI_PCIE_PLL_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x028 << 2)) ++#define HHI_PCIE_PLL_CNTL3 (0xff63c000 + (0x029 << 2)) ++#define SEC_HHI_PCIE_PLL_CNTL3 (0xff63c000 + (0x029 << 2)) ++#define P_HHI_PCIE_PLL_CNTL3 (volatile uint32_t *)(0xff63c000 + (0x029 << 2)) ++#define HHI_PCIE_PLL_CNTL4 (0xff63c000 + (0x02a << 2)) ++#define SEC_HHI_PCIE_PLL_CNTL4 (0xff63c000 + (0x02a << 2)) ++#define P_HHI_PCIE_PLL_CNTL4 (volatile uint32_t *)(0xff63c000 + (0x02a << 2)) ++#define HHI_PCIE_PLL_CNTL5 (0xff63c000 + (0x02b << 2)) ++#define SEC_HHI_PCIE_PLL_CNTL5 (0xff63c000 + (0x02b << 2)) ++#define P_HHI_PCIE_PLL_CNTL5 (volatile uint32_t *)(0xff63c000 + (0x02b << 2)) ++#define HHI_PCIE_PLL_STS (0xff63c000 + (0x02c << 2)) ++#define SEC_HHI_PCIE_PLL_STS (0xff63c000 + (0x02c << 2)) ++#define P_HHI_PCIE_PLL_STS (volatile uint32_t *)(0xff63c000 + (0x02c << 2)) ++//`define HHI_DADC_CNTL 8'h27 ++//`define HHI_DADC_CNTL2 8'h28 ++//`define HHI_DADC_RDBK0_I 8'h29 ++//`define HHI_DADC_CNTL3 8'h2a ++//`define HHI_DADC_CNTL4 8'h2b ++//`define HHI_AFE_TUNNING_CNTL 8'h2c ++//`define HHI_AFE_TUNNING_CNTL_I 8'h2d ++//`define HHI_CVBS_DETECT_CNTL 8'h2e ++#define HHI_XTAL_DIVN_CNTL (0xff63c000 + (0x02f << 2)) ++#define SEC_HHI_XTAL_DIVN_CNTL (0xff63c000 + (0x02f << 2)) ++#define P_HHI_XTAL_DIVN_CNTL (volatile uint32_t *)(0xff63c000 + (0x02f << 2)) ++#define HHI_GCLK2_MPEG0 (0xff63c000 + (0x030 << 2)) ++#define SEC_HHI_GCLK2_MPEG0 (0xff63c000 + (0x030 << 2)) ++#define P_HHI_GCLK2_MPEG0 (volatile uint32_t *)(0xff63c000 + (0x030 << 2)) ++#define HHI_GCLK2_MPEG1 (0xff63c000 + (0x031 << 2)) ++#define SEC_HHI_GCLK2_MPEG1 (0xff63c000 + (0x031 << 2)) ++#define P_HHI_GCLK2_MPEG1 (volatile uint32_t *)(0xff63c000 + (0x031 << 2)) ++#define HHI_GCLK2_MPEG2 (0xff63c000 + (0x032 << 2)) ++#define SEC_HHI_GCLK2_MPEG2 (0xff63c000 + (0x032 << 2)) ++#define P_HHI_GCLK2_MPEG2 (volatile uint32_t *)(0xff63c000 + (0x032 << 2)) ++#define HHI_GCLK2_OTHER (0xff63c000 + (0x034 << 2)) ++#define SEC_HHI_GCLK2_OTHER (0xff63c000 + (0x034 << 2)) ++#define P_HHI_GCLK2_OTHER (volatile uint32_t *)(0xff63c000 + (0x034 << 2)) ++//`define HHI_GCLK2_AO 8'h35 ++#define HHI_HIFI_PLL_CNTL0 (0xff63c000 + (0x036 << 2)) ++#define SEC_HHI_HIFI_PLL_CNTL0 (0xff63c000 + (0x036 << 2)) ++#define P_HHI_HIFI_PLL_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x036 << 2)) ++#define HHI_HIFI_PLL_CNTL1 (0xff63c000 + (0x037 << 2)) ++#define SEC_HHI_HIFI_PLL_CNTL1 (0xff63c000 + (0x037 << 2)) ++#define P_HHI_HIFI_PLL_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x037 << 2)) ++#define HHI_HIFI_PLL_CNTL2 (0xff63c000 + (0x038 << 2)) ++#define SEC_HHI_HIFI_PLL_CNTL2 (0xff63c000 + (0x038 << 2)) ++#define P_HHI_HIFI_PLL_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x038 << 2)) ++#define HHI_HIFI_PLL_CNTL3 (0xff63c000 + (0x039 << 2)) ++#define SEC_HHI_HIFI_PLL_CNTL3 (0xff63c000 + (0x039 << 2)) ++#define P_HHI_HIFI_PLL_CNTL3 (volatile uint32_t *)(0xff63c000 + (0x039 << 2)) ++#define HHI_HIFI_PLL_CNTL4 (0xff63c000 + (0x03a << 2)) ++#define SEC_HHI_HIFI_PLL_CNTL4 (0xff63c000 + (0x03a << 2)) ++#define P_HHI_HIFI_PLL_CNTL4 (volatile uint32_t *)(0xff63c000 + (0x03a << 2)) ++#define HHI_HIFI_PLL_CNTL5 (0xff63c000 + (0x03b << 2)) ++#define SEC_HHI_HIFI_PLL_CNTL5 (0xff63c000 + (0x03b << 2)) ++#define P_HHI_HIFI_PLL_CNTL5 (volatile uint32_t *)(0xff63c000 + (0x03b << 2)) ++#define HHI_HIFI_PLL_CNTL6 (0xff63c000 + (0x03c << 2)) ++#define SEC_HHI_HIFI_PLL_CNTL6 (0xff63c000 + (0x03c << 2)) ++#define P_HHI_HIFI_PLL_CNTL6 (volatile uint32_t *)(0xff63c000 + (0x03c << 2)) ++#define HHI_HIFI_PLL_STS (0xff63c000 + (0x03d << 2)) ++#define SEC_HHI_HIFI_PLL_STS (0xff63c000 + (0x03d << 2)) ++#define P_HHI_HIFI_PLL_STS (volatile uint32_t *)(0xff63c000 + (0x03d << 2)) ++#define HHI_TIMER90K (0xff63c000 + (0x03f << 2)) ++#define SEC_HHI_TIMER90K (0xff63c000 + (0x03f << 2)) ++#define P_HHI_TIMER90K (volatile uint32_t *)(0xff63c000 + (0x03f << 2)) ++#define HHI_MEM_PD_REG0 (0xff63c000 + (0x040 << 2)) ++#define SEC_HHI_MEM_PD_REG0 (0xff63c000 + (0x040 << 2)) ++#define P_HHI_MEM_PD_REG0 (volatile uint32_t *)(0xff63c000 + (0x040 << 2)) ++//VIU1 ++//bit 29:28 mem_pd_vi_sharp, 2'b00: Sharpness line buffer memory power on, 2'b11: power down ++//bit 29:28 mem_pd_vi_dipost, 2'b00: Deinterlace - di_post memory power on, 2'b11: power down ++//bit 27:26 mem_pd_vi_dipre, 2'b00: Deinterlace - di_pre memory power on, 2'b11: power down ++//bit 25:24 mem_pd_vi_prot3, 2'b00: picture rotation3 memory power on, 2'b11: power down ++//bit 23:22 mem_pd_vi_prot2, 2'b00: picture rotation2 memory power on, 2'b11: power down ++//bit 21:20 mem_pd_vi_prot1, 2'b00: picture rotation1 memory power on, 2'b11: power down ++//bit 19:18 mem_pd_vi_vdin1, 2'b00: vdin1 memory power on, 2'b11: power down ++//bit 17:16 mem_pd_vi_vdin0, 2'b00: vdin0 memory power on, 2'b11: power down ++//bit 15:14 mem_pd_vi_osd_sc, 2'b00: osd_scaler memory power on, 2'b11: power down ++//bit 13:12 mem_pd_vi_scale, 2'b00: scaler memory power on, 2'b11: power down ++//bit 11:10 mem_pd_vi_ofifo, 2'b00: vpp output fifo memory power on, 2'b11: power down ++//bit 9:8 mem_pd_vi_chroma, 2'b00: color management module memory power on, 2'b11: power down ++//bit 7:6 mem_pd_vi_vd2, 2'b00: vd2 memory power on, 2'b11: power down ++//bit 5:4 mem_pd_vi_vd1, 2'b00: vd1 memory power on, 2'b11: power down ++//bit 3:2 mem_pd_vi_osd2, 2'b00: osd2 memory power on, 2'b11: power down ++//bit 1:0 mem_pd_vi_osd1, 2'b00: osd1 memory power on, 2'b11: power down ++#define HHI_VPU_MEM_PD_REG0 (0xff63c000 + (0x041 << 2)) ++#define SEC_HHI_VPU_MEM_PD_REG0 (0xff63c000 + (0x041 << 2)) ++#define P_HHI_VPU_MEM_PD_REG0 (volatile uint32_t *)(0xff63c000 + (0x041 << 2)) ++//bit 29:28 mem_pd_atv_dmd, 2'b00: ATV DMD memory power on, 2'b11: power down ++//bit 29:28 mem_pd_cvd2, 2'b00: CVD2 memory power on, 2'b11: power down ++//bit 27:26 mem_pd_isp, 2'b00: ISP memory power on, 2'b11: power down ++//bit 25:24 mem_pd_venci_int, 2'b00: cvbs- enci interface memory power on, 2'b11: power down ++//bit 23:22 mem_pd_venc_l_top,2'b00: panel - encl top memory power on, 2'b11: power down ++//bit 21:20 mem_pd_vencp_int, 2'b00: hdmi - encp interface memory power on, 2'b11: power down ++//bit 13:12 mem_pd_vi2_osd_sc,2'b00: viu2 OSD scaler memory power on, 2'b11: power down ++//bit 11:10 mem_pd_vi2_scale, 2'b00: viu2 scaler memory power on, 2'b11: power down ++//bit 9:8 mem_pd_vi2_ofifo, 2'b00: viu2 vpp output fifo memory power on, 2'b11: power down ++//bit 7:6 mem_pd_vi2_chroma,2'b00: viu2 color management module memory power on, 2'b11: power down ++//bit 5:4 mem_pd_vi2_vd1, 2'b00: viu2 vd1 memory power on, 2'b11: power down ++//bit 3:2 mem_pd_vi2_osd2, 2'b00: viu2 osd2 memory power on, 2'b11: power down ++//bit 1:0 mem_pd_vi2_osd1, 2'b00: viu2 osd1 memory power on, 2'b11: power down ++#define HHI_VPU_MEM_PD_REG1 (0xff63c000 + (0x042 << 2)) ++#define SEC_HHI_VPU_MEM_PD_REG1 (0xff63c000 + (0x042 << 2)) ++#define P_HHI_VPU_MEM_PD_REG1 (volatile uint32_t *)(0xff63c000 + (0x042 << 2)) ++#define HHI_VPU_MEM_PD_REG3 (0xff63c000 + (0x043 << 2)) ++#define SEC_HHI_VPU_MEM_PD_REG3 (0xff63c000 + (0x043 << 2)) ++#define P_HHI_VPU_MEM_PD_REG3 (volatile uint32_t *)(0xff63c000 + (0x043 << 2)) ++#define HHI_VPU_MEM_PD_REG4 (0xff63c000 + (0x044 << 2)) ++#define SEC_HHI_VPU_MEM_PD_REG4 (0xff63c000 + (0x044 << 2)) ++#define P_HHI_VPU_MEM_PD_REG4 (volatile uint32_t *)(0xff63c000 + (0x044 << 2)) ++//`define HHI_DEMOD_MEM_PD_REG 8'h43 ++//`define HHI_AUD_DAC_CTRL 8'h44 ++// `define HHI_VIID_PLL_CNTL4 8'h46 // video PLL read back ++// `define HHI_VIID_PLL_CNTL 8'h47 // Video PLL control, word 1 ++// `define HHI_VIID_PLL_CNTL2 8'h48 // Video PLL control, word 2 ++// `define HHI_VIID_PLL_CNTL3 8'h49 // Video PLL control, word 3 ++#define HHI_VIID_CLK_DIV (0xff63c000 + (0x04a << 2)) ++#define SEC_HHI_VIID_CLK_DIV (0xff63c000 + (0x04a << 2)) ++#define P_HHI_VIID_CLK_DIV (volatile uint32_t *)(0xff63c000 + (0x04a << 2)) ++#define HHI_VIID_CLK_CNTL (0xff63c000 + (0x04b << 2)) ++#define SEC_HHI_VIID_CLK_CNTL (0xff63c000 + (0x04b << 2)) ++#define P_HHI_VIID_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x04b << 2)) ++//`define HHI_VIID_DIVIDER_CNTL 8'h4c ++//bit 1:0 mem_pd_vi_wm, 2'b00: viu1 wm memory power on, 2'b11: power down ++#define HHI_VPU_MEM_PD_REG2 (0xff63c000 + (0x04d << 2)) ++#define SEC_HHI_VPU_MEM_PD_REG2 (0xff63c000 + (0x04d << 2)) ++#define P_HHI_VPU_MEM_PD_REG2 (volatile uint32_t *)(0xff63c000 + (0x04d << 2)) ++// Gated clock enables. There are 64 enables for the MPEG clocks and 32 enables for other clock domains ++#define HHI_GCLK_LOCK (0xff63c000 + (0x04f << 2)) ++#define SEC_HHI_GCLK_LOCK (0xff63c000 + (0x04f << 2)) ++#define P_HHI_GCLK_LOCK (volatile uint32_t *)(0xff63c000 + (0x04f << 2)) ++#define HHI_GCLK_MPEG0 (0xff63c000 + (0x050 << 2)) ++#define SEC_HHI_GCLK_MPEG0 (0xff63c000 + (0x050 << 2)) ++#define P_HHI_GCLK_MPEG0 (volatile uint32_t *)(0xff63c000 + (0x050 << 2)) ++#define HHI_GCLK_MPEG1 (0xff63c000 + (0x051 << 2)) ++#define SEC_HHI_GCLK_MPEG1 (0xff63c000 + (0x051 << 2)) ++#define P_HHI_GCLK_MPEG1 (volatile uint32_t *)(0xff63c000 + (0x051 << 2)) ++#define HHI_GCLK_MPEG2 (0xff63c000 + (0x052 << 2)) ++#define SEC_HHI_GCLK_MPEG2 (0xff63c000 + (0x052 << 2)) ++#define P_HHI_GCLK_MPEG2 (volatile uint32_t *)(0xff63c000 + (0x052 << 2)) ++#define HHI_GCLK_OTHER (0xff63c000 + (0x054 << 2)) ++#define SEC_HHI_GCLK_OTHER (0xff63c000 + (0x054 << 2)) ++#define P_HHI_GCLK_OTHER (volatile uint32_t *)(0xff63c000 + (0x054 << 2)) ++#define HHI_GCLK_SP_MPEG (0xff63c000 + (0x055 << 2)) ++#define SEC_HHI_GCLK_SP_MPEG (0xff63c000 + (0x055 << 2)) ++#define P_HHI_GCLK_SP_MPEG (volatile uint32_t *)(0xff63c000 + (0x055 << 2)) ++//`define HHI_SYS_OSCIN_CNTL 8'h56 ++#define HHI_SYS_CPU_CLK_CNTL1 (0xff63c000 + (0x057 << 2)) ++#define SEC_HHI_SYS_CPU_CLK_CNTL1 (0xff63c000 + (0x057 << 2)) ++#define P_HHI_SYS_CPU_CLK_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x057 << 2)) ++#define HHI_SYS_CPU_RESET_CNTL (0xff63c000 + (0x058 << 2)) ++#define SEC_HHI_SYS_CPU_RESET_CNTL (0xff63c000 + (0x058 << 2)) ++#define P_HHI_SYS_CPU_RESET_CNTL (volatile uint32_t *)(0xff63c000 + (0x058 << 2)) ++// PLL Controls ++#define HHI_VID_CLK_DIV (0xff63c000 + (0x059 << 2)) ++#define SEC_HHI_VID_CLK_DIV (0xff63c000 + (0x059 << 2)) ++#define P_HHI_VID_CLK_DIV (volatile uint32_t *)(0xff63c000 + (0x059 << 2)) ++#define HHI_MPEG_CLK_CNTL (0xff63c000 + (0x05d << 2)) ++#define SEC_HHI_MPEG_CLK_CNTL (0xff63c000 + (0x05d << 2)) ++#define P_HHI_MPEG_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x05d << 2)) ++#define HHI_VID_CLK_CNTL (0xff63c000 + (0x05f << 2)) ++#define SEC_HHI_VID_CLK_CNTL (0xff63c000 + (0x05f << 2)) ++#define P_HHI_VID_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x05f << 2)) ++//`define HHI_WIFI_CLK_CNTL 8'h60 // MPEG clock control ++//`define HHI_WIFI_PLL_CNTL 8'h61 // WIFI PLL control, word 1 ++//`define HHI_WIFI_PLL_CNTL2 8'h62 // WIFI PLL control, word 2 ++//`define HHI_WIFI_PLL_CNTL3 8'h63 // WIFI PLL control, word 3 ++#define HHI_TS_CLK_CNTL (0xff63c000 + (0x064 << 2)) ++#define SEC_HHI_TS_CLK_CNTL (0xff63c000 + (0x064 << 2)) ++#define P_HHI_TS_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x064 << 2)) ++#define HHI_VID_CLK_CNTL2 (0xff63c000 + (0x065 << 2)) ++#define SEC_HHI_VID_CLK_CNTL2 (0xff63c000 + (0x065 << 2)) ++#define P_HHI_VID_CLK_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x065 << 2)) ++//`define HHI_VID_DIVIDER_CNTL 8'h66 ++#define HHI_SYS_CPU_CLK_CNTL (0xff63c000 + (0x067 << 2)) ++#define SEC_HHI_SYS_CPU_CLK_CNTL (0xff63c000 + (0x067 << 2)) ++#define P_HHI_SYS_CPU_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x067 << 2)) ++#define HHI_VID_PLL_CLK_DIV (0xff63c000 + (0x068 << 2)) ++#define SEC_HHI_VID_PLL_CLK_DIV (0xff63c000 + (0x068 << 2)) ++#define P_HHI_VID_PLL_CLK_DIV (volatile uint32_t *)(0xff63c000 + (0x068 << 2)) ++// Moved to Martin's domain `define HHI_DDR_PLL_CNTL 8'h68 // DDR PLL control, word 1 ++// Moved to Martin's domain `define HHI_DDR_PLL_CNTL2 8'h69 // DDR PLL control, word 2 ++// Moved to Martin's domain `define HHI_DDR_PLL_CNTL3 8'h6a // DDR PLL control, word 3 ++// Moved to Martin's domain `define HHI_DDR_PLL_CNTL4 8'h6b // DDR PLL control, word 3 ++#define HHI_MALI_CLK_CNTL (0xff63c000 + (0x06c << 2)) ++#define SEC_HHI_MALI_CLK_CNTL (0xff63c000 + (0x06c << 2)) ++#define P_HHI_MALI_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x06c << 2)) ++#define HHI_VPU_CLKC_CNTL (0xff63c000 + (0x06d << 2)) ++#define SEC_HHI_VPU_CLKC_CNTL (0xff63c000 + (0x06d << 2)) ++#define P_HHI_VPU_CLKC_CNTL (volatile uint32_t *)(0xff63c000 + (0x06d << 2)) ++//`define HHI_MIPI_PHY_CLK_CNTL 8'h6e ++#define HHI_VPU_CLK_CNTL (0xff63c000 + (0x06f << 2)) ++#define SEC_HHI_VPU_CLK_CNTL (0xff63c000 + (0x06f << 2)) ++#define P_HHI_VPU_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x06f << 2)) ++//`define HHI_OTHER_PLL_CNTL 8'h70 // OTHER PLL control, word 1 ++//`define HHI_OTHER_PLL_CNTL2 8'h71 // OTHER PLL control, word 2 ++//`define HHI_OTHER_PLL_CNTL3 8'h72 // OTHER PLL control, word 3 ++#define HHI_HDMI_CLK_CNTL (0xff63c000 + (0x073 << 2)) ++#define SEC_HHI_HDMI_CLK_CNTL (0xff63c000 + (0x073 << 2)) ++#define P_HHI_HDMI_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x073 << 2)) ++//`define HHI_DEMOD_CLK_CNTL 8'h74 // DEMOD clock control ++//`define HHI_SATA_CLK_CNTL 8'h75 // SATA clock control ++#define HHI_ETH_CLK_CNTL (0xff63c000 + (0x076 << 2)) ++#define SEC_HHI_ETH_CLK_CNTL (0xff63c000 + (0x076 << 2)) ++#define P_HHI_ETH_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x076 << 2)) ++//`define HHI_CLK_DOUBLE_CNTL 8'h77 // Ethernet clock control ++#define HHI_VDEC_CLK_CNTL (0xff63c000 + (0x078 << 2)) ++#define SEC_HHI_VDEC_CLK_CNTL (0xff63c000 + (0x078 << 2)) ++#define P_HHI_VDEC_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x078 << 2)) ++#define HHI_VDEC2_CLK_CNTL (0xff63c000 + (0x079 << 2)) ++#define SEC_HHI_VDEC2_CLK_CNTL (0xff63c000 + (0x079 << 2)) ++#define P_HHI_VDEC2_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x079 << 2)) ++#define HHI_VDEC3_CLK_CNTL (0xff63c000 + (0x07a << 2)) ++#define SEC_HHI_VDEC3_CLK_CNTL (0xff63c000 + (0x07a << 2)) ++#define P_HHI_VDEC3_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x07a << 2)) ++#define HHI_VDEC4_CLK_CNTL (0xff63c000 + (0x07b << 2)) ++#define SEC_HHI_VDEC4_CLK_CNTL (0xff63c000 + (0x07b << 2)) ++#define P_HHI_VDEC4_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x07b << 2)) ++#define HHI_HDCP22_CLK_CNTL (0xff63c000 + (0x07c << 2)) ++#define SEC_HHI_HDCP22_CLK_CNTL (0xff63c000 + (0x07c << 2)) ++#define P_HHI_HDCP22_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x07c << 2)) ++#define HHI_VAPBCLK_CNTL (0xff63c000 + (0x07d << 2)) ++#define SEC_HHI_VAPBCLK_CNTL (0xff63c000 + (0x07d << 2)) ++#define P_HHI_VAPBCLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x07d << 2)) ++//`define HHI_VP9DEC_CLK_CNTL 8'h7e ++// `define HHI_SYS_CPU_AUTO_CLK0 8'h78 never used ++// `define HHI_SYS_CPU_AUTO_CLK1 8'h79 never used ++// `define HHI_MEDIA_CPU_AUTO_CLK0 8'h7a never used ++// `define HHI_MEDIA_CPU_AUTO_CLK1 8'h7b never used ++//`define HHI_HDMI_AFC_CNTL 8'h7f ++//`define HHI_HDMIRX_CLK_CNTL 8'h80 ++//`define HHI_HDMIRX_AUD_CLK_CNTL 8'h81 ++//`define HHI_EDP_APB_CLK_CNTL 8'h82 ++#define HHI_VPU_CLKB_CNTL (0xff63c000 + (0x083 << 2)) ++#define SEC_HHI_VPU_CLKB_CNTL (0xff63c000 + (0x083 << 2)) ++#define P_HHI_VPU_CLKB_CNTL (volatile uint32_t *)(0xff63c000 + (0x083 << 2)) ++//`define HHI_VID_PLL_MOD_CNTL0 8'h84 ++//`define HHI_VID_PLL_MOD_LOW_TCNT 8'h85 ++//`define HHI_VID_PLL_MOD_HIGH_TCNT 8'h86 ++//`define HHI_VID_PLL_MOD_NOM_TCNT 8'h87 ++// Removed `define HHI_DDR_CLK_CNTL 8'h88 ++//`define HHI_32K_CLK_CNTL 8'h89 ++#define HHI_GEN_CLK_CNTL (0xff63c000 + (0x08a << 2)) ++#define SEC_HHI_GEN_CLK_CNTL (0xff63c000 + (0x08a << 2)) ++#define P_HHI_GEN_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x08a << 2)) ++//`define HHI_GEN_CLK_CNTL2 8'h8b ++//`define HHI_AUDPLL_CLK_OUT_CNTL 8'h8c ++//`define HHI_JTAG_CONFIG 8'h8e ++//`define HHI_VAFE_CLKXTALIN_CNTL 8'h8f ++//`define HHI_VAFE_CLKOSCIN_CNTL 8'h90 ++//`define HHI_VAFE_CLKIN_CNTL 8'h91 ++//`define HHI_TVFE_AUTOMODE_CLK_CNTL 8'h92 ++//`define HHI_VAFE_CLKPI_CNTL 8'h93 ++#define HHI_VDIN_MEAS_CLK_CNTL (0xff63c000 + (0x094 << 2)) ++#define SEC_HHI_VDIN_MEAS_CLK_CNTL (0xff63c000 + (0x094 << 2)) ++#define P_HHI_VDIN_MEAS_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x094 << 2)) ++#define HHI_MIPIDSI_PHY_CLK_CNTL (0xff63c000 + (0x095 << 2)) ++#define SEC_HHI_MIPIDSI_PHY_CLK_CNTL (0xff63c000 + (0x095 << 2)) ++#define P_HHI_MIPIDSI_PHY_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x095 << 2)) ++#define HHI_NAND_CLK_CNTL (0xff63c000 + (0x097 << 2)) ++#define SEC_HHI_NAND_CLK_CNTL (0xff63c000 + (0x097 << 2)) ++#define P_HHI_NAND_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x097 << 2)) ++//`define HHI_ISP_LED_CLK_CNTL 8'h98 ++#define HHI_SD_EMMC_CLK_CNTL (0xff63c000 + (0x099 << 2)) ++#define SEC_HHI_SD_EMMC_CLK_CNTL (0xff63c000 + (0x099 << 2)) ++#define P_HHI_SD_EMMC_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x099 << 2)) ++#define HHI_WAVE420L_CLK_CNTL (0xff63c000 + (0x09a << 2)) ++#define SEC_HHI_WAVE420L_CLK_CNTL (0xff63c000 + (0x09a << 2)) ++#define P_HHI_WAVE420L_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x09a << 2)) ++#define HHI_WAVE420L_CLK_CNTL2 (0xff63c000 + (0x09b << 2)) ++#define SEC_HHI_WAVE420L_CLK_CNTL2 (0xff63c000 + (0x09b << 2)) ++#define P_HHI_WAVE420L_CLK_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x09b << 2)) ++//`define HHI_EDP_TX_PHY_CNTL0 8'h9c ++//`define HHI_EDP_TX_PHY_CNTL1 8'h9d ++//`define HHI_ADC_PLL_CNTL5 8'h9e ++//`define HHI_ADC_PLL_CNTL6 8'h9f ++#define HHI_MPLL_CNTL0 (0xff63c000 + (0x09e << 2)) ++#define SEC_HHI_MPLL_CNTL0 (0xff63c000 + (0x09e << 2)) ++#define P_HHI_MPLL_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x09e << 2)) ++#define HHI_MPLL_CNTL1 (0xff63c000 + (0x09f << 2)) ++#define SEC_HHI_MPLL_CNTL1 (0xff63c000 + (0x09f << 2)) ++#define P_HHI_MPLL_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x09f << 2)) ++#define HHI_MPLL_CNTL2 (0xff63c000 + (0x0a0 << 2)) ++#define SEC_HHI_MPLL_CNTL2 (0xff63c000 + (0x0a0 << 2)) ++#define P_HHI_MPLL_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x0a0 << 2)) ++#define HHI_MPLL_CNTL3 (0xff63c000 + (0x0a1 << 2)) ++#define SEC_HHI_MPLL_CNTL3 (0xff63c000 + (0x0a1 << 2)) ++#define P_HHI_MPLL_CNTL3 (volatile uint32_t *)(0xff63c000 + (0x0a1 << 2)) ++#define HHI_MPLL_CNTL4 (0xff63c000 + (0x0a2 << 2)) ++#define SEC_HHI_MPLL_CNTL4 (0xff63c000 + (0x0a2 << 2)) ++#define P_HHI_MPLL_CNTL4 (volatile uint32_t *)(0xff63c000 + (0x0a2 << 2)) ++#define HHI_MPLL_CNTL5 (0xff63c000 + (0x0a3 << 2)) ++#define SEC_HHI_MPLL_CNTL5 (0xff63c000 + (0x0a3 << 2)) ++#define P_HHI_MPLL_CNTL5 (volatile uint32_t *)(0xff63c000 + (0x0a3 << 2)) ++#define HHI_MPLL_CNTL6 (0xff63c000 + (0x0a4 << 2)) ++#define SEC_HHI_MPLL_CNTL6 (0xff63c000 + (0x0a4 << 2)) ++#define P_HHI_MPLL_CNTL6 (volatile uint32_t *)(0xff63c000 + (0x0a4 << 2)) ++#define HHI_MPLL_CNTL7 (0xff63c000 + (0x0a5 << 2)) ++#define SEC_HHI_MPLL_CNTL7 (0xff63c000 + (0x0a5 << 2)) ++#define P_HHI_MPLL_CNTL7 (volatile uint32_t *)(0xff63c000 + (0x0a5 << 2)) ++#define HHI_MPLL_CNTL8 (0xff63c000 + (0x0a6 << 2)) ++#define SEC_HHI_MPLL_CNTL8 (0xff63c000 + (0x0a6 << 2)) ++#define P_HHI_MPLL_CNTL8 (volatile uint32_t *)(0xff63c000 + (0x0a6 << 2)) ++#define HHI_MPLL_STS (0xff63c000 + (0x0a7 << 2)) ++#define SEC_HHI_MPLL_STS (0xff63c000 + (0x0a7 << 2)) ++#define P_HHI_MPLL_STS (volatile uint32_t *)(0xff63c000 + (0x0a7 << 2)) ++#define HHI_FIX_PLL_CNTL0 (0xff63c000 + (0x0a8 << 2)) ++#define SEC_HHI_FIX_PLL_CNTL0 (0xff63c000 + (0x0a8 << 2)) ++#define P_HHI_FIX_PLL_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x0a8 << 2)) ++#define HHI_FIX_PLL_CNTL1 (0xff63c000 + (0x0a9 << 2)) ++#define SEC_HHI_FIX_PLL_CNTL1 (0xff63c000 + (0x0a9 << 2)) ++#define P_HHI_FIX_PLL_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x0a9 << 2)) ++#define HHI_FIX_PLL_CNTL2 (0xff63c000 + (0x0aa << 2)) ++#define SEC_HHI_FIX_PLL_CNTL2 (0xff63c000 + (0x0aa << 2)) ++#define P_HHI_FIX_PLL_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x0aa << 2)) ++#define HHI_FIX_PLL_CNTL3 (0xff63c000 + (0x0ab << 2)) ++#define SEC_HHI_FIX_PLL_CNTL3 (0xff63c000 + (0x0ab << 2)) ++#define P_HHI_FIX_PLL_CNTL3 (volatile uint32_t *)(0xff63c000 + (0x0ab << 2)) ++#define HHI_FIX_PLL_CNTL4 (0xff63c000 + (0x0ac << 2)) ++#define SEC_HHI_FIX_PLL_CNTL4 (0xff63c000 + (0x0ac << 2)) ++#define P_HHI_FIX_PLL_CNTL4 (volatile uint32_t *)(0xff63c000 + (0x0ac << 2)) ++#define HHI_FIX_PLL_CNTL5 (0xff63c000 + (0x0ad << 2)) ++#define SEC_HHI_FIX_PLL_CNTL5 (0xff63c000 + (0x0ad << 2)) ++#define P_HHI_FIX_PLL_CNTL5 (volatile uint32_t *)(0xff63c000 + (0x0ad << 2)) ++#define HHI_FIX_PLL_CNTL6 (0xff63c000 + (0x0ae << 2)) ++#define SEC_HHI_FIX_PLL_CNTL6 (0xff63c000 + (0x0ae << 2)) ++#define P_HHI_FIX_PLL_CNTL6 (volatile uint32_t *)(0xff63c000 + (0x0ae << 2)) ++#define HHI_FIX_PLL_STS (0xff63c000 + (0x0af << 2)) ++#define SEC_HHI_FIX_PLL_STS (0xff63c000 + (0x0af << 2)) ++#define P_HHI_FIX_PLL_STS (volatile uint32_t *)(0xff63c000 + (0x0af << 2)) ++//`define HHI_ADC_PLL_CNTL 8'haa ++//`define HHI_ADC_PLL_CNTL2 8'hab ++//`define HHI_ADC_PLL_CNTL3 8'hac ++//`define HHI_ADC_PLL_CNTL4 8'had ++//`define HHI_ADC_PLL_STS 8'hae ++//`define HHI_ADC_PLL_CNTL1 8'haf ++//`define HHI_AUDCLK_PLL_CNTL 8'hb0 ++//`define HHI_AUDCLK_PLL_CNTL2 8'hb1 ++//`define HHI_AUDCLK_PLL_CNTL3 8'hb2 ++//`define HHI_AUDCLK_PLL_CNTL4 8'hb3 ++//`define HHI_AUDCLK_PLL_CNTL5 8'hb4 ++//`define HHI_AUDCLK_PLL_CNTL6 8'hb5 ++//`define HHI_L2_DDR_CLK_CNTL 8'hb6 ++//`define HHI_PLL_TOP_MISC 8'hba ++#define HHI_VDAC_CNTL0 (0xff63c000 + (0x0bb << 2)) ++#define SEC_HHI_VDAC_CNTL0 (0xff63c000 + (0x0bb << 2)) ++#define P_HHI_VDAC_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x0bb << 2)) ++#define HHI_VDAC_CNTL1 (0xff63c000 + (0x0bc << 2)) ++#define SEC_HHI_VDAC_CNTL1 (0xff63c000 + (0x0bc << 2)) ++#define P_HHI_VDAC_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x0bc << 2)) ++#define HHI_SYS_PLL_CNTL0 (0xff63c000 + (0x0bd << 2)) ++#define SEC_HHI_SYS_PLL_CNTL0 (0xff63c000 + (0x0bd << 2)) ++#define P_HHI_SYS_PLL_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x0bd << 2)) ++#define HHI_SYS_PLL_CNTL1 (0xff63c000 + (0x0be << 2)) ++#define SEC_HHI_SYS_PLL_CNTL1 (0xff63c000 + (0x0be << 2)) ++#define P_HHI_SYS_PLL_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x0be << 2)) ++#define HHI_SYS_PLL_CNTL2 (0xff63c000 + (0x0bf << 2)) ++#define SEC_HHI_SYS_PLL_CNTL2 (0xff63c000 + (0x0bf << 2)) ++#define P_HHI_SYS_PLL_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x0bf << 2)) ++#define HHI_SYS_PLL_CNTL3 (0xff63c000 + (0x0c0 << 2)) ++#define SEC_HHI_SYS_PLL_CNTL3 (0xff63c000 + (0x0c0 << 2)) ++#define P_HHI_SYS_PLL_CNTL3 (volatile uint32_t *)(0xff63c000 + (0x0c0 << 2)) ++#define HHI_SYS_PLL_CNTL4 (0xff63c000 + (0x0c1 << 2)) ++#define SEC_HHI_SYS_PLL_CNTL4 (0xff63c000 + (0x0c1 << 2)) ++#define P_HHI_SYS_PLL_CNTL4 (volatile uint32_t *)(0xff63c000 + (0x0c1 << 2)) ++#define HHI_SYS_PLL_CNTL5 (0xff63c000 + (0x0c2 << 2)) ++#define SEC_HHI_SYS_PLL_CNTL5 (0xff63c000 + (0x0c2 << 2)) ++#define P_HHI_SYS_PLL_CNTL5 (volatile uint32_t *)(0xff63c000 + (0x0c2 << 2)) ++#define HHI_SYS_PLL_CNTL6 (0xff63c000 + (0x0c3 << 2)) ++#define SEC_HHI_SYS_PLL_CNTL6 (0xff63c000 + (0x0c3 << 2)) ++#define P_HHI_SYS_PLL_CNTL6 (volatile uint32_t *)(0xff63c000 + (0x0c3 << 2)) ++#define HHI_SYS_PLL_STS (0xff63c000 + (0x0c4 << 2)) ++#define SEC_HHI_SYS_PLL_STS (0xff63c000 + (0x0c4 << 2)) ++#define P_HHI_SYS_PLL_STS (volatile uint32_t *)(0xff63c000 + (0x0c4 << 2)) ++#define HHI_HDMI_PLL_CNTL0 (0xff63c000 + (0x0c8 << 2)) ++#define SEC_HHI_HDMI_PLL_CNTL0 (0xff63c000 + (0x0c8 << 2)) ++#define P_HHI_HDMI_PLL_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x0c8 << 2)) ++#define HHI_HDMI_PLL_CNTL1 (0xff63c000 + (0x0c9 << 2)) ++#define SEC_HHI_HDMI_PLL_CNTL1 (0xff63c000 + (0x0c9 << 2)) ++#define P_HHI_HDMI_PLL_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x0c9 << 2)) ++#define HHI_HDMI_PLL_CNTL2 (0xff63c000 + (0x0ca << 2)) ++#define SEC_HHI_HDMI_PLL_CNTL2 (0xff63c000 + (0x0ca << 2)) ++#define P_HHI_HDMI_PLL_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x0ca << 2)) ++#define HHI_HDMI_PLL_CNTL3 (0xff63c000 + (0x0cb << 2)) ++#define SEC_HHI_HDMI_PLL_CNTL3 (0xff63c000 + (0x0cb << 2)) ++#define P_HHI_HDMI_PLL_CNTL3 (volatile uint32_t *)(0xff63c000 + (0x0cb << 2)) ++#define HHI_HDMI_PLL_CNTL4 (0xff63c000 + (0x0cc << 2)) ++#define SEC_HHI_HDMI_PLL_CNTL4 (0xff63c000 + (0x0cc << 2)) ++#define P_HHI_HDMI_PLL_CNTL4 (volatile uint32_t *)(0xff63c000 + (0x0cc << 2)) ++#define HHI_HDMI_PLL_CNTL5 (0xff63c000 + (0x0cd << 2)) ++#define SEC_HHI_HDMI_PLL_CNTL5 (0xff63c000 + (0x0cd << 2)) ++#define P_HHI_HDMI_PLL_CNTL5 (volatile uint32_t *)(0xff63c000 + (0x0cd << 2)) ++#define HHI_HDMI_PLL_CNTL6 (0xff63c000 + (0x0ce << 2)) ++#define SEC_HHI_HDMI_PLL_CNTL6 (0xff63c000 + (0x0ce << 2)) ++#define P_HHI_HDMI_PLL_CNTL6 (volatile uint32_t *)(0xff63c000 + (0x0ce << 2)) ++#define HHI_HDMI_PLL_STS (0xff63c000 + (0x0cf << 2)) ++#define SEC_HHI_HDMI_PLL_STS (0xff63c000 + (0x0cf << 2)) ++#define P_HHI_HDMI_PLL_STS (volatile uint32_t *)(0xff63c000 + (0x0cf << 2)) ++//`define HHI_MIPI_CSI_PHY_CLK_CNTL 8'hd0 ++//`define HHI_DSI_LVDS_EDP_CNTL0 8'hd1 ++//`define HHI_DSI_LVDS_EDP_CNTL1 8'hd2 ++//`define HHI_CSI_PHY_CNTL0 8'hd3 ++//`define HHI_CSI_PHY_CNTL1 8'hd4 ++//`define HHI_CSI_PHY_CNTL2 8'hd5 ++//`define HHI_CSI_PHY_CNTL3 8'hd6 ++//`define HHI_CSI_PHY_CNTL4 8'hd7 ++//`define HHI_DIF_CSI_PHY_CNTL0 8'hd8 ++//`define HHI_DIF_CSI_PHY_CNTL1 8'hd9 ++//`define HHI_DIF_CSI_PHY_CNTL2 8'hda ++//`define HHI_DIF_CSI_PHY_CNTL3 8'hdb ++//`define HHI_DIF_CSI_PHY_CNTL4 8'hdc ++//`define HHI_DIF_CSI_PHY_CNTL5 8'hdd ++//`define HHI_LVDS_TX_PHY_CNTL0 8'hde ++//`define HHI_LVDS_TX_PHY_CNTL1 8'hdf ++//`define HHI_VID2_PLL_CNTL 8'he0 ++//`define HHI_VID2_PLL_CNTL2 8'he1 ++//`define HHI_VID2_PLL_CNTL3 8'he2 ++//`define HHI_VID2_PLL_CNTL4 8'he3 ++//`define HHI_VID2_PLL_CNTL5 8'he4 ++//`define HHI_VID2_PLL_CNTL_I 8'he5 ++#define HHI_HDMI_PHY_CNTL0 (0xff63c000 + (0x0e8 << 2)) ++#define SEC_HHI_HDMI_PHY_CNTL0 (0xff63c000 + (0x0e8 << 2)) ++#define P_HHI_HDMI_PHY_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x0e8 << 2)) ++#define HHI_HDMI_PHY_CNTL1 (0xff63c000 + (0x0e9 << 2)) ++#define SEC_HHI_HDMI_PHY_CNTL1 (0xff63c000 + (0x0e9 << 2)) ++#define P_HHI_HDMI_PHY_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x0e9 << 2)) ++#define HHI_HDMI_PHY_CNTL2 (0xff63c000 + (0x0ea << 2)) ++#define SEC_HHI_HDMI_PHY_CNTL2 (0xff63c000 + (0x0ea << 2)) ++#define P_HHI_HDMI_PHY_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x0ea << 2)) ++#define HHI_HDMI_PHY_CNTL3 (0xff63c000 + (0x0eb << 2)) ++#define SEC_HHI_HDMI_PHY_CNTL3 (0xff63c000 + (0x0eb << 2)) ++#define P_HHI_HDMI_PHY_CNTL3 (volatile uint32_t *)(0xff63c000 + (0x0eb << 2)) ++#define HHI_HDMI_PHY_CNTL4 (0xff63c000 + (0x0ec << 2)) ++#define SEC_HHI_HDMI_PHY_CNTL4 (0xff63c000 + (0x0ec << 2)) ++#define P_HHI_HDMI_PHY_CNTL4 (volatile uint32_t *)(0xff63c000 + (0x0ec << 2)) ++#define HHI_HDMI_PHY_CNTL5 (0xff63c000 + (0x0ed << 2)) ++#define SEC_HHI_HDMI_PHY_CNTL5 (0xff63c000 + (0x0ed << 2)) ++#define P_HHI_HDMI_PHY_CNTL5 (volatile uint32_t *)(0xff63c000 + (0x0ed << 2)) ++#define HHI_HDMI_PHY_STATUS (0xff63c000 + (0x0ee << 2)) ++#define SEC_HHI_HDMI_PHY_STATUS (0xff63c000 + (0x0ee << 2)) ++#define P_HHI_HDMI_PHY_STATUS (volatile uint32_t *)(0xff63c000 + (0x0ee << 2)) ++//`define HHI_ADEC_SYS_CLK_CNTL 8'hf1 ++#define HHI_VID_LOCK_CLK_CNTL (0xff63c000 + (0x0f2 << 2)) ++#define SEC_HHI_VID_LOCK_CLK_CNTL (0xff63c000 + (0x0f2 << 2)) ++#define P_HHI_VID_LOCK_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x0f2 << 2)) ++//`define HHI_ATV_DMD_SYS_CLK_CNTL 8'hf3 ++#define HHI_AXI_PIPEL_CNTL (0xff63c000 + (0x0f4 << 2)) ++#define SEC_HHI_AXI_PIPEL_CNTL (0xff63c000 + (0x0f4 << 2)) ++#define P_HHI_AXI_PIPEL_CNTL (volatile uint32_t *)(0xff63c000 + (0x0f4 << 2)) ++#define HHI_BT656_CLK_CNTL (0xff63c000 + (0x0f5 << 2)) ++#define SEC_HHI_BT656_CLK_CNTL (0xff63c000 + (0x0f5 << 2)) ++#define P_HHI_BT656_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x0f5 << 2)) ++#define HHI_CDAC_CLK_CNTL (0xff63c000 + (0x0f6 << 2)) ++#define SEC_HHI_CDAC_CLK_CNTL (0xff63c000 + (0x0f6 << 2)) ++#define P_HHI_CDAC_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x0f6 << 2)) ++#define HHI_SPICC_CLK_CNTL (0xff63c000 + (0x0f7 << 2)) ++#define SEC_HHI_SPICC_CLK_CNTL (0xff63c000 + (0x0f7 << 2)) ++#define P_HHI_SPICC_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x0f7 << 2)) ++//`define HHI_HDMIRX_AUD_PLL_CNTL 8'hf8 ++//`define HHI_HDMIRX_AUD_PLL_CNTL2 8'hf9 ++//`define HHI_HDMIRX_AUD_PLL_CNTL3 8'hfa ++//`define HHI_HDMIRX_AUD_PLL_CNTL4 8'hfb ++//`define HHI_HDMIRX_AUD_PLL_CNTL5 8'hfc ++//`define HHI_HDMIRX_AUD_PLL_CNTL6 8'hfd ++//`define HHI_HDMIRX_AUD_PLL_CNTL_I 8'hfe ++//======================================================================== ++// HIU - Mailbox ++//======================================================================== ++// APB4_DECODER_NON_SECURE_BASE 32'hFF63C400 ++// APB4_DECODER_SECURE_BASE 32'hFF63C400 ++#define HIU_MAILBOX_SET_0 (0xff63c400 + (0x001 << 2)) ++#define SEC_HIU_MAILBOX_SET_0 (0xff63c400 + (0x001 << 2)) ++#define P_HIU_MAILBOX_SET_0 (volatile uint32_t *)(0xff63c400 + (0x001 << 2)) ++#define HIU_MAILBOX_STAT_0 (0xff63c400 + (0x002 << 2)) ++#define SEC_HIU_MAILBOX_STAT_0 (0xff63c400 + (0x002 << 2)) ++#define P_HIU_MAILBOX_STAT_0 (volatile uint32_t *)(0xff63c400 + (0x002 << 2)) ++#define HIU_MAILBOX_CLR_0 (0xff63c400 + (0x003 << 2)) ++#define SEC_HIU_MAILBOX_CLR_0 (0xff63c400 + (0x003 << 2)) ++#define P_HIU_MAILBOX_CLR_0 (volatile uint32_t *)(0xff63c400 + (0x003 << 2)) ++#define HIU_MAILBOX_SET_1 (0xff63c400 + (0x004 << 2)) ++#define SEC_HIU_MAILBOX_SET_1 (0xff63c400 + (0x004 << 2)) ++#define P_HIU_MAILBOX_SET_1 (volatile uint32_t *)(0xff63c400 + (0x004 << 2)) ++#define HIU_MAILBOX_STAT_1 (0xff63c400 + (0x005 << 2)) ++#define SEC_HIU_MAILBOX_STAT_1 (0xff63c400 + (0x005 << 2)) ++#define P_HIU_MAILBOX_STAT_1 (volatile uint32_t *)(0xff63c400 + (0x005 << 2)) ++#define HIU_MAILBOX_CLR_1 (0xff63c400 + (0x006 << 2)) ++#define SEC_HIU_MAILBOX_CLR_1 (0xff63c400 + (0x006 << 2)) ++#define P_HIU_MAILBOX_CLR_1 (volatile uint32_t *)(0xff63c400 + (0x006 << 2)) ++#define HIU_MAILBOX_SET_2 (0xff63c400 + (0x007 << 2)) ++#define SEC_HIU_MAILBOX_SET_2 (0xff63c400 + (0x007 << 2)) ++#define P_HIU_MAILBOX_SET_2 (volatile uint32_t *)(0xff63c400 + (0x007 << 2)) ++#define HIU_MAILBOX_STAT_2 (0xff63c400 + (0x008 << 2)) ++#define SEC_HIU_MAILBOX_STAT_2 (0xff63c400 + (0x008 << 2)) ++#define P_HIU_MAILBOX_STAT_2 (volatile uint32_t *)(0xff63c400 + (0x008 << 2)) ++#define HIU_MAILBOX_CLR_2 (0xff63c400 + (0x009 << 2)) ++#define SEC_HIU_MAILBOX_CLR_2 (0xff63c400 + (0x009 << 2)) ++#define P_HIU_MAILBOX_CLR_2 (volatile uint32_t *)(0xff63c400 + (0x009 << 2)) ++#define HIU_MAILBOX_SET_3 (0xff63c400 + (0x00a << 2)) ++#define SEC_HIU_MAILBOX_SET_3 (0xff63c400 + (0x00a << 2)) ++#define P_HIU_MAILBOX_SET_3 (volatile uint32_t *)(0xff63c400 + (0x00a << 2)) ++#define HIU_MAILBOX_STAT_3 (0xff63c400 + (0x00b << 2)) ++#define SEC_HIU_MAILBOX_STAT_3 (0xff63c400 + (0x00b << 2)) ++#define P_HIU_MAILBOX_STAT_3 (volatile uint32_t *)(0xff63c400 + (0x00b << 2)) ++#define HIU_MAILBOX_CLR_3 (0xff63c400 + (0x00c << 2)) ++#define SEC_HIU_MAILBOX_CLR_3 (0xff63c400 + (0x00c << 2)) ++#define P_HIU_MAILBOX_CLR_3 (volatile uint32_t *)(0xff63c400 + (0x00c << 2)) ++#define HIU_MAILBOX_SET_4 (0xff63c400 + (0x00d << 2)) ++#define SEC_HIU_MAILBOX_SET_4 (0xff63c400 + (0x00d << 2)) ++#define P_HIU_MAILBOX_SET_4 (volatile uint32_t *)(0xff63c400 + (0x00d << 2)) ++#define HIU_MAILBOX_STAT_4 (0xff63c400 + (0x00e << 2)) ++#define SEC_HIU_MAILBOX_STAT_4 (0xff63c400 + (0x00e << 2)) ++#define P_HIU_MAILBOX_STAT_4 (volatile uint32_t *)(0xff63c400 + (0x00e << 2)) ++#define HIU_MAILBOX_CLR_4 (0xff63c400 + (0x00f << 2)) ++#define SEC_HIU_MAILBOX_CLR_4 (0xff63c400 + (0x00f << 2)) ++#define P_HIU_MAILBOX_CLR_4 (volatile uint32_t *)(0xff63c400 + (0x00f << 2)) ++#define HIU_MAILBOX_SET_5 (0xff63c400 + (0x010 << 2)) ++#define SEC_HIU_MAILBOX_SET_5 (0xff63c400 + (0x010 << 2)) ++#define P_HIU_MAILBOX_SET_5 (volatile uint32_t *)(0xff63c400 + (0x010 << 2)) ++#define HIU_MAILBOX_STAT_5 (0xff63c400 + (0x011 << 2)) ++#define SEC_HIU_MAILBOX_STAT_5 (0xff63c400 + (0x011 << 2)) ++#define P_HIU_MAILBOX_STAT_5 (volatile uint32_t *)(0xff63c400 + (0x011 << 2)) ++#define HIU_MAILBOX_CLR_5 (0xff63c400 + (0x012 << 2)) ++#define SEC_HIU_MAILBOX_CLR_5 (0xff63c400 + (0x012 << 2)) ++#define P_HIU_MAILBOX_CLR_5 (volatile uint32_t *)(0xff63c400 + (0x012 << 2)) ++#define HIU_MAILBOX_SET_6 (0xff63c400 + (0x013 << 2)) ++#define SEC_HIU_MAILBOX_SET_6 (0xff63c400 + (0x013 << 2)) ++#define P_HIU_MAILBOX_SET_6 (volatile uint32_t *)(0xff63c400 + (0x013 << 2)) ++#define HIU_MAILBOX_STAT_6 (0xff63c400 + (0x014 << 2)) ++#define SEC_HIU_MAILBOX_STAT_6 (0xff63c400 + (0x014 << 2)) ++#define P_HIU_MAILBOX_STAT_6 (volatile uint32_t *)(0xff63c400 + (0x014 << 2)) ++#define HIU_MAILBOX_CLR_6 (0xff63c400 + (0x015 << 2)) ++#define SEC_HIU_MAILBOX_CLR_6 (0xff63c400 + (0x015 << 2)) ++#define P_HIU_MAILBOX_CLR_6 (volatile uint32_t *)(0xff63c400 + (0x015 << 2)) ++#define HIU_MAILBOX_SET_7 (0xff63c400 + (0x016 << 2)) ++#define SEC_HIU_MAILBOX_SET_7 (0xff63c400 + (0x016 << 2)) ++#define P_HIU_MAILBOX_SET_7 (volatile uint32_t *)(0xff63c400 + (0x016 << 2)) ++#define HIU_MAILBOX_STAT_7 (0xff63c400 + (0x017 << 2)) ++#define SEC_HIU_MAILBOX_STAT_7 (0xff63c400 + (0x017 << 2)) ++#define P_HIU_MAILBOX_STAT_7 (volatile uint32_t *)(0xff63c400 + (0x017 << 2)) ++#define HIU_MAILBOX_CLR_7 (0xff63c400 + (0x018 << 2)) ++#define SEC_HIU_MAILBOX_CLR_7 (0xff63c400 + (0x018 << 2)) ++#define P_HIU_MAILBOX_CLR_7 (volatile uint32_t *)(0xff63c400 + (0x018 << 2)) ++//======================================================================== ++// EFUSE ++//======================================================================== ++// APB4_DECODER_NON_SECURE_BASE 32'hFF630000 ++// APB4_DECODER_SECURE_BASE 32'hFF630000 ++#define EFUSE_CLR (0xff630000 + (0x000 << 2)) ++#define SEC_EFUSE_CLR (0xff630000 + (0x000 << 2)) ++#define P_EFUSE_CLR (volatile uint32_t *)(0xff630000 + (0x000 << 2)) ++#define EFUSE_START (0xff630000 + (0x001 << 2)) ++#define SEC_EFUSE_START (0xff630000 + (0x001 << 2)) ++#define P_EFUSE_START (volatile uint32_t *)(0xff630000 + (0x001 << 2)) ++#define EFUSE_WDATA0 (0xff630000 + (0x004 << 2)) ++#define SEC_EFUSE_WDATA0 (0xff630000 + (0x004 << 2)) ++#define P_EFUSE_WDATA0 (volatile uint32_t *)(0xff630000 + (0x004 << 2)) ++#define EFUSE_WDATA1 (0xff630000 + (0x005 << 2)) ++#define SEC_EFUSE_WDATA1 (0xff630000 + (0x005 << 2)) ++#define P_EFUSE_WDATA1 (volatile uint32_t *)(0xff630000 + (0x005 << 2)) ++#define EFUSE_WDATA2 (0xff630000 + (0x006 << 2)) ++#define SEC_EFUSE_WDATA2 (0xff630000 + (0x006 << 2)) ++#define P_EFUSE_WDATA2 (volatile uint32_t *)(0xff630000 + (0x006 << 2)) ++#define EFUSE_WDATA3 (0xff630000 + (0x007 << 2)) ++#define SEC_EFUSE_WDATA3 (0xff630000 + (0x007 << 2)) ++#define P_EFUSE_WDATA3 (volatile uint32_t *)(0xff630000 + (0x007 << 2)) ++#define EFUSE_RDATA0 (0xff630000 + (0x008 << 2)) ++#define SEC_EFUSE_RDATA0 (0xff630000 + (0x008 << 2)) ++#define P_EFUSE_RDATA0 (volatile uint32_t *)(0xff630000 + (0x008 << 2)) ++#define EFUSE_RDATA1 (0xff630000 + (0x009 << 2)) ++#define SEC_EFUSE_RDATA1 (0xff630000 + (0x009 << 2)) ++#define P_EFUSE_RDATA1 (volatile uint32_t *)(0xff630000 + (0x009 << 2)) ++#define EFUSE_RDATA2 (0xff630000 + (0x00a << 2)) ++#define SEC_EFUSE_RDATA2 (0xff630000 + (0x00a << 2)) ++#define P_EFUSE_RDATA2 (volatile uint32_t *)(0xff630000 + (0x00a << 2)) ++#define EFUSE_RDATA3 (0xff630000 + (0x00b << 2)) ++#define SEC_EFUSE_RDATA3 (0xff630000 + (0x00b << 2)) ++#define P_EFUSE_RDATA3 (volatile uint32_t *)(0xff630000 + (0x00b << 2)) ++#define EFUSE_LIC0 (0xff630000 + (0x00c << 2)) ++#define SEC_EFUSE_LIC0 (0xff630000 + (0x00c << 2)) ++#define P_EFUSE_LIC0 (volatile uint32_t *)(0xff630000 + (0x00c << 2)) ++#define EFUSE_LIC1 (0xff630000 + (0x00d << 2)) ++#define SEC_EFUSE_LIC1 (0xff630000 + (0x00d << 2)) ++#define P_EFUSE_LIC1 (volatile uint32_t *)(0xff630000 + (0x00d << 2)) ++#define EFUSE_LIC2 (0xff630000 + (0x00e << 2)) ++#define SEC_EFUSE_LIC2 (0xff630000 + (0x00e << 2)) ++#define P_EFUSE_LIC2 (volatile uint32_t *)(0xff630000 + (0x00e << 2)) ++#define EFUSE_LIC3 (0xff630000 + (0x00f << 2)) ++#define SEC_EFUSE_LIC3 (0xff630000 + (0x00f << 2)) ++#define P_EFUSE_LIC3 (volatile uint32_t *)(0xff630000 + (0x00f << 2)) ++#define KL_START0 (0xff630000 + (0x020 << 2)) ++#define SEC_KL_START0 (0xff630000 + (0x020 << 2)) ++#define P_KL_START0 (volatile uint32_t *)(0xff630000 + (0x020 << 2)) ++#define KL_START1 (0xff630000 + (0x021 << 2)) ++#define SEC_KL_START1 (0xff630000 + (0x021 << 2)) ++#define P_KL_START1 (volatile uint32_t *)(0xff630000 + (0x021 << 2)) ++#define KL_RESP0_0 (0xff630000 + (0x024 << 2)) ++#define SEC_KL_RESP0_0 (0xff630000 + (0x024 << 2)) ++#define P_KL_RESP0_0 (volatile uint32_t *)(0xff630000 + (0x024 << 2)) ++#define KL_RESP0_1 (0xff630000 + (0x025 << 2)) ++#define SEC_KL_RESP0_1 (0xff630000 + (0x025 << 2)) ++#define P_KL_RESP0_1 (volatile uint32_t *)(0xff630000 + (0x025 << 2)) ++#define KL_RESP0_2 (0xff630000 + (0x026 << 2)) ++#define SEC_KL_RESP0_2 (0xff630000 + (0x026 << 2)) ++#define P_KL_RESP0_2 (volatile uint32_t *)(0xff630000 + (0x026 << 2)) ++#define KL_RESP0_3 (0xff630000 + (0x027 << 2)) ++#define SEC_KL_RESP0_3 (0xff630000 + (0x027 << 2)) ++#define P_KL_RESP0_3 (volatile uint32_t *)(0xff630000 + (0x027 << 2)) ++#define KL_RESP1_0 (0xff630000 + (0x028 << 2)) ++#define SEC_KL_RESP1_0 (0xff630000 + (0x028 << 2)) ++#define P_KL_RESP1_0 (volatile uint32_t *)(0xff630000 + (0x028 << 2)) ++#define KL_RESP1_1 (0xff630000 + (0x029 << 2)) ++#define SEC_KL_RESP1_1 (0xff630000 + (0x029 << 2)) ++#define P_KL_RESP1_1 (volatile uint32_t *)(0xff630000 + (0x029 << 2)) ++#define KL_RESP1_2 (0xff630000 + (0x02a << 2)) ++#define SEC_KL_RESP1_2 (0xff630000 + (0x02a << 2)) ++#define P_KL_RESP1_2 (volatile uint32_t *)(0xff630000 + (0x02a << 2)) ++#define KL_RESP1_3 (0xff630000 + (0x02b << 2)) ++#define SEC_KL_RESP1_3 (0xff630000 + (0x02b << 2)) ++#define P_KL_RESP1_3 (volatile uint32_t *)(0xff630000 + (0x02b << 2)) ++#define KL_RAM (0xff630000 + (0x040 << 2)) ++#define SEC_KL_RAM (0xff630000 + (0x040 << 2)) ++#define P_KL_RAM (volatile uint32_t *)(0xff630000 + (0x040 << 2)) ++#define RNG_SEC_CONFIG_REG1 (0xff630000 + (0x081 << 2)) ++#define SEC_RNG_SEC_CONFIG_REG1 (0xff630000 + (0x081 << 2)) ++#define P_RNG_SEC_CONFIG_REG1 (volatile uint32_t *)(0xff630000 + (0x081 << 2)) ++#define RNG_SEC_CONFIG_REG2 (0xff630000 + (0x082 << 2)) ++#define SEC_RNG_SEC_CONFIG_REG2 (0xff630000 + (0x082 << 2)) ++#define P_RNG_SEC_CONFIG_REG2 (volatile uint32_t *)(0xff630000 + (0x082 << 2)) ++#define RNG_SEC_DATA (0xff630000 + (0x084 << 2)) ++#define SEC_RNG_SEC_DATA (0xff630000 + (0x084 << 2)) ++#define P_RNG_SEC_DATA (volatile uint32_t *)(0xff630000 + (0x084 << 2)) ++#define RNG_SEC_STS (0xff630000 + (0x085 << 2)) ++#define SEC_RNG_SEC_STS (0xff630000 + (0x085 << 2)) ++#define P_RNG_SEC_STS (volatile uint32_t *)(0xff630000 + (0x085 << 2)) ++#define RNG_USR_DATA (0xff630000 + (0x086 << 2)) ++#define SEC_RNG_USR_DATA (0xff630000 + (0x086 << 2)) ++#define P_RNG_USR_DATA (volatile uint32_t *)(0xff630000 + (0x086 << 2)) ++#define RNG_USR_STS (0xff630000 + (0x087 << 2)) ++#define SEC_RNG_USR_STS (0xff630000 + (0x087 << 2)) ++#define P_RNG_USR_STS (volatile uint32_t *)(0xff630000 + (0x087 << 2)) ++//======================================================================== ++// Ethernet Phy ++//======================================================================== ++// APB4_DECODER_NON_SECURE_BASE 32'hFF64C000 ++// APB4_DECODER_SECURE_BASE 32'hFF64C000 ++#define ETH_PHY_DBG_CTL0 (0xff64c000 + (0x000 << 2)) ++#define SEC_ETH_PHY_DBG_CTL0 (0xff64c000 + (0x000 << 2)) ++#define P_ETH_PHY_DBG_CTL0 (volatile uint32_t *)(0xff64c000 + (0x000 << 2)) ++#define ETH_PHY_DBG_CTL1 (0xff64c000 + (0x001 << 2)) ++#define SEC_ETH_PHY_DBG_CTL1 (0xff64c000 + (0x001 << 2)) ++#define P_ETH_PHY_DBG_CTL1 (volatile uint32_t *)(0xff64c000 + (0x001 << 2)) ++#define ETH_PHY_DBG_CFG0 (0xff64c000 + (0x002 << 2)) ++#define SEC_ETH_PHY_DBG_CFG0 (0xff64c000 + (0x002 << 2)) ++#define P_ETH_PHY_DBG_CFG0 (volatile uint32_t *)(0xff64c000 + (0x002 << 2)) ++#define ETH_PHY_DBG_CFG1 (0xff64c000 + (0x003 << 2)) ++#define SEC_ETH_PHY_DBG_CFG1 (0xff64c000 + (0x003 << 2)) ++#define P_ETH_PHY_DBG_CFG1 (volatile uint32_t *)(0xff64c000 + (0x003 << 2)) ++#define ETH_PHY_DBG_CFG2 (0xff64c000 + (0x004 << 2)) ++#define SEC_ETH_PHY_DBG_CFG2 (0xff64c000 + (0x004 << 2)) ++#define P_ETH_PHY_DBG_CFG2 (volatile uint32_t *)(0xff64c000 + (0x004 << 2)) ++#define ETH_PHY_DBG_CFG3 (0xff64c000 + (0x005 << 2)) ++#define SEC_ETH_PHY_DBG_CFG3 (0xff64c000 + (0x005 << 2)) ++#define P_ETH_PHY_DBG_CFG3 (volatile uint32_t *)(0xff64c000 + (0x005 << 2)) ++#define ETH_PHY_DBG_CFG4 (0xff64c000 + (0x006 << 2)) ++#define SEC_ETH_PHY_DBG_CFG4 (0xff64c000 + (0x006 << 2)) ++#define P_ETH_PHY_DBG_CFG4 (volatile uint32_t *)(0xff64c000 + (0x006 << 2)) ++#define ETH_PLL_STS (0xff64c000 + (0x010 << 2)) ++#define SEC_ETH_PLL_STS (0xff64c000 + (0x010 << 2)) ++#define P_ETH_PLL_STS (volatile uint32_t *)(0xff64c000 + (0x010 << 2)) ++#define ETH_PLL_CTL0 (0xff64c000 + (0x011 << 2)) ++#define SEC_ETH_PLL_CTL0 (0xff64c000 + (0x011 << 2)) ++#define P_ETH_PLL_CTL0 (volatile uint32_t *)(0xff64c000 + (0x011 << 2)) ++#define ETH_PLL_CTL1 (0xff64c000 + (0x012 << 2)) ++#define SEC_ETH_PLL_CTL1 (0xff64c000 + (0x012 << 2)) ++#define P_ETH_PLL_CTL1 (volatile uint32_t *)(0xff64c000 + (0x012 << 2)) ++#define ETH_PLL_CTL2 (0xff64c000 + (0x013 << 2)) ++#define SEC_ETH_PLL_CTL2 (0xff64c000 + (0x013 << 2)) ++#define P_ETH_PLL_CTL2 (volatile uint32_t *)(0xff64c000 + (0x013 << 2)) ++#define ETH_PLL_CTL3 (0xff64c000 + (0x014 << 2)) ++#define SEC_ETH_PLL_CTL3 (0xff64c000 + (0x014 << 2)) ++#define P_ETH_PLL_CTL3 (volatile uint32_t *)(0xff64c000 + (0x014 << 2)) ++#define ETH_PLL_CTL4 (0xff64c000 + (0x015 << 2)) ++#define SEC_ETH_PLL_CTL4 (0xff64c000 + (0x015 << 2)) ++#define P_ETH_PLL_CTL4 (volatile uint32_t *)(0xff64c000 + (0x015 << 2)) ++#define ETH_PLL_CTL5 (0xff64c000 + (0x016 << 2)) ++#define SEC_ETH_PLL_CTL5 (0xff64c000 + (0x016 << 2)) ++#define P_ETH_PLL_CTL5 (volatile uint32_t *)(0xff64c000 + (0x016 << 2)) ++#define ETH_PLL_CTL6 (0xff64c000 + (0x017 << 2)) ++#define SEC_ETH_PLL_CTL6 (0xff64c000 + (0x017 << 2)) ++#define P_ETH_PLL_CTL6 (volatile uint32_t *)(0xff64c000 + (0x017 << 2)) ++#define ETH_PLL_CTL7 (0xff64c000 + (0x018 << 2)) ++#define SEC_ETH_PLL_CTL7 (0xff64c000 + (0x018 << 2)) ++#define P_ETH_PLL_CTL7 (volatile uint32_t *)(0xff64c000 + (0x018 << 2)) ++#define ETH_PHY_CNTL0 (0xff64c000 + (0x020 << 2)) ++#define SEC_ETH_PHY_CNTL0 (0xff64c000 + (0x020 << 2)) ++#define P_ETH_PHY_CNTL0 (volatile uint32_t *)(0xff64c000 + (0x020 << 2)) ++#define ETH_PHY_CNTL1 (0xff64c000 + (0x021 << 2)) ++#define SEC_ETH_PHY_CNTL1 (0xff64c000 + (0x021 << 2)) ++#define P_ETH_PHY_CNTL1 (volatile uint32_t *)(0xff64c000 + (0x021 << 2)) ++#define ETH_PHY_CNTL2 (0xff64c000 + (0x022 << 2)) ++#define SEC_ETH_PHY_CNTL2 (0xff64c000 + (0x022 << 2)) ++#define P_ETH_PHY_CNTL2 (volatile uint32_t *)(0xff64c000 + (0x022 << 2)) ++#define ETH_PHY_STS0 (0xff64c000 + (0x025 << 2)) ++#define SEC_ETH_PHY_STS0 (0xff64c000 + (0x025 << 2)) ++#define P_ETH_PHY_STS0 (volatile uint32_t *)(0xff64c000 + (0x025 << 2)) ++#define ETH_PHY_STS1 (0xff64c000 + (0x026 << 2)) ++#define SEC_ETH_PHY_STS1 (0xff64c000 + (0x026 << 2)) ++#define P_ETH_PHY_STS1 (volatile uint32_t *)(0xff64c000 + (0x026 << 2)) ++#define ETH_PHY_STS2 (0xff64c000 + (0x027 << 2)) ++#define SEC_ETH_PHY_STS2 (0xff64c000 + (0x027 << 2)) ++#define P_ETH_PHY_STS2 (volatile uint32_t *)(0xff64c000 + (0x027 << 2)) ++#define ETH_PHY_DBG_REG (0xff64c000 + (0x028 << 2)) ++#define SEC_ETH_PHY_DBG_REG (0xff64c000 + (0x028 << 2)) ++#define P_ETH_PHY_DBG_REG (volatile uint32_t *)(0xff64c000 + (0x028 << 2)) ++//======================================================================== ++// PDM ++//======================================================================== ++// ++// Reading file: ../audio/rtl/pdm_reg.vh ++// ++// APB4_DECODER_NON_SECURE_BASE 32'hFF640000 ++// APB4_DECODER_SECURE_BASE 32'hFF640000 ++#define PDM_CTRL (0xff640000 + (0x000 << 2)) ++#define SEC_PDM_CTRL (0xff640000 + (0x000 << 2)) ++#define P_PDM_CTRL (volatile uint32_t *)(0xff640000 + (0x000 << 2)) ++#define PDM_HCIC_CTRL1 (0xff640000 + (0x001 << 2)) ++#define SEC_PDM_HCIC_CTRL1 (0xff640000 + (0x001 << 2)) ++#define P_PDM_HCIC_CTRL1 (volatile uint32_t *)(0xff640000 + (0x001 << 2)) ++#define PDM_HCIC_CTRL2 (0xff640000 + (0x002 << 2)) ++#define SEC_PDM_HCIC_CTRL2 (0xff640000 + (0x002 << 2)) ++#define P_PDM_HCIC_CTRL2 (volatile uint32_t *)(0xff640000 + (0x002 << 2)) ++#define PDM_F1_CTRL (0xff640000 + (0x003 << 2)) ++#define SEC_PDM_F1_CTRL (0xff640000 + (0x003 << 2)) ++#define P_PDM_F1_CTRL (volatile uint32_t *)(0xff640000 + (0x003 << 2)) ++#define PDM_F2_CTRL (0xff640000 + (0x004 << 2)) ++#define SEC_PDM_F2_CTRL (0xff640000 + (0x004 << 2)) ++#define P_PDM_F2_CTRL (volatile uint32_t *)(0xff640000 + (0x004 << 2)) ++#define PDM_F3_CTRL (0xff640000 + (0x005 << 2)) ++#define SEC_PDM_F3_CTRL (0xff640000 + (0x005 << 2)) ++#define P_PDM_F3_CTRL (volatile uint32_t *)(0xff640000 + (0x005 << 2)) ++#define PDM_HPF_CTRL (0xff640000 + (0x006 << 2)) ++#define SEC_PDM_HPF_CTRL (0xff640000 + (0x006 << 2)) ++#define P_PDM_HPF_CTRL (volatile uint32_t *)(0xff640000 + (0x006 << 2)) ++#define PDM_CHAN_CTRL (0xff640000 + (0x007 << 2)) ++#define SEC_PDM_CHAN_CTRL (0xff640000 + (0x007 << 2)) ++#define P_PDM_CHAN_CTRL (volatile uint32_t *)(0xff640000 + (0x007 << 2)) ++#define PDM_CHAN_CTRL1 (0xff640000 + (0x008 << 2)) ++#define SEC_PDM_CHAN_CTRL1 (0xff640000 + (0x008 << 2)) ++#define P_PDM_CHAN_CTRL1 (volatile uint32_t *)(0xff640000 + (0x008 << 2)) ++#define PDM_COEFF_ADDR (0xff640000 + (0x009 << 2)) ++#define SEC_PDM_COEFF_ADDR (0xff640000 + (0x009 << 2)) ++#define P_PDM_COEFF_ADDR (volatile uint32_t *)(0xff640000 + (0x009 << 2)) ++#define PDM_COEFF_DATA (0xff640000 + (0x00a << 2)) ++#define SEC_PDM_COEFF_DATA (0xff640000 + (0x00a << 2)) ++#define P_PDM_COEFF_DATA (volatile uint32_t *)(0xff640000 + (0x00a << 2)) ++#define PDM_CLKG_CTRL (0xff640000 + (0x00b << 2)) ++#define SEC_PDM_CLKG_CTRL (0xff640000 + (0x00b << 2)) ++#define P_PDM_CLKG_CTRL (volatile uint32_t *)(0xff640000 + (0x00b << 2)) ++#define PDM_STS (0xff640000 + (0x00c << 2)) ++#define SEC_PDM_STS (0xff640000 + (0x00c << 2)) ++#define P_PDM_STS (volatile uint32_t *)(0xff640000 + (0x00c << 2)) ++//bit 1 HPF filter output overflow. means the PCLK is too slow. ++//bit 0 HCIC filter output overflow. means the CTS_PDM_CLK is too slow. can't finished the filter function. ++#define PDM_MUTE_VALUE (0xff640000 + (0x00d << 2)) ++#define SEC_PDM_MUTE_VALUE (0xff640000 + (0x00d << 2)) ++#define P_PDM_MUTE_VALUE (volatile uint32_t *)(0xff640000 + (0x00d << 2)) ++// ++// Closing file: ../audio/rtl/pdm_reg.vh ++// ++// synopsys translate_off ++// synopsys translate_on ++// ++// Closing file: ./secure_apb4_ee.h ++// ++// ++// Reading file: ./ao_rti_reg.h ++// ++//#define AO_RTI_REG_BASE 0x00 ++// APB4_DECODER_NON_SECURE_BASE 32'hFF800000 ++// APB4_DECODER_SECURE_BASE 32'hFF800000 ++// Registers not affected by the Watchdog timer ++#define AO_RTI_STATUS_REG0 (0xff800000 + (0x000 << 2)) ++#define SEC_AO_RTI_STATUS_REG0 (0xff800000 + (0x000 << 2)) ++#define P_AO_RTI_STATUS_REG0 (volatile uint32_t *)(0xff800000 + (0x000 << 2)) ++#define AO_RTI_STATUS_REG1 (0xff800000 + (0x001 << 2)) ++#define SEC_AO_RTI_STATUS_REG1 (0xff800000 + (0x001 << 2)) ++#define P_AO_RTI_STATUS_REG1 (volatile uint32_t *)(0xff800000 + (0x001 << 2)) ++#define AO_RTI_STATUS_REG2 (0xff800000 + (0x002 << 2)) ++#define SEC_AO_RTI_STATUS_REG2 (0xff800000 + (0x002 << 2)) ++#define P_AO_RTI_STATUS_REG2 (volatile uint32_t *)(0xff800000 + (0x002 << 2)) ++#define AO_RTI_STATUS_REG3 (0xff800000 + (0x003 << 2)) ++#define SEC_AO_RTI_STATUS_REG3 (0xff800000 + (0x003 << 2)) ++#define P_AO_RTI_STATUS_REG3 (volatile uint32_t *)(0xff800000 + (0x003 << 2)) ++//`define AO_RTI_PWR_CNTL_REG1 8'h03 ++#define AO_RTI_PWR_CNTL_REG0 (0xff800000 + (0x004 << 2)) ++#define SEC_AO_RTI_PWR_CNTL_REG0 (0xff800000 + (0x004 << 2)) ++#define P_AO_RTI_PWR_CNTL_REG0 (volatile uint32_t *)(0xff800000 + (0x004 << 2)) ++#define AO_RTI_PINMUX_REG0 (0xff800000 + (0x005 << 2)) ++#define SEC_AO_RTI_PINMUX_REG0 (0xff800000 + (0x005 << 2)) ++#define P_AO_RTI_PINMUX_REG0 (volatile uint32_t *)(0xff800000 + (0x005 << 2)) ++#define AO_RTI_PINMUX_REG1 (0xff800000 + (0x006 << 2)) ++#define SEC_AO_RTI_PINMUX_REG1 (0xff800000 + (0x006 << 2)) ++#define P_AO_RTI_PINMUX_REG1 (volatile uint32_t *)(0xff800000 + (0x006 << 2)) ++//`define AO_REMAP_REG1 8'h08 ++#define AO_PAD_DS_A (0xff800000 + (0x007 << 2)) ++#define SEC_AO_PAD_DS_A (0xff800000 + (0x007 << 2)) ++#define P_AO_PAD_DS_A (volatile uint32_t *)(0xff800000 + (0x007 << 2)) ++#define AO_PAD_DS_B (0xff800000 + (0x008 << 2)) ++#define SEC_AO_PAD_DS_B (0xff800000 + (0x008 << 2)) ++#define P_AO_PAD_DS_B (volatile uint32_t *)(0xff800000 + (0x008 << 2)) ++#define AO_GPIO_O_EN_N (0xff800000 + (0x009 << 2)) ++#define SEC_AO_GPIO_O_EN_N (0xff800000 + (0x009 << 2)) ++#define P_AO_GPIO_O_EN_N (volatile uint32_t *)(0xff800000 + (0x009 << 2)) ++#define AO_GPIO_I (0xff800000 + (0x00a << 2)) ++#define SEC_AO_GPIO_I (0xff800000 + (0x00a << 2)) ++#define P_AO_GPIO_I (volatile uint32_t *)(0xff800000 + (0x00a << 2)) ++#define AO_RTI_PULL_UP_REG (0xff800000 + (0x00b << 2)) ++#define SEC_AO_RTI_PULL_UP_REG (0xff800000 + (0x00b << 2)) ++#define P_AO_RTI_PULL_UP_REG (volatile uint32_t *)(0xff800000 + (0x00b << 2)) ++#define AO_RTI_PULL_UP_EN_REG (0xff800000 + (0x00c << 2)) ++#define SEC_AO_RTI_PULL_UP_EN_REG (0xff800000 + (0x00c << 2)) ++#define P_AO_RTI_PULL_UP_EN_REG (volatile uint32_t *)(0xff800000 + (0x00c << 2)) ++#define AO_GPIO_O (0xff800000 + (0x00d << 2)) ++#define SEC_AO_GPIO_O (0xff800000 + (0x00d << 2)) ++#define P_AO_GPIO_O (volatile uint32_t *)(0xff800000 + (0x00d << 2)) ++//`define AO_RTI_JTAG_CONFIG_REG 8'h0C ++//`define AO_RTI_WD_MARK 8'h0D ++#define AO_CPU_CNTL (0xff800000 + (0x00e << 2)) ++#define SEC_AO_CPU_CNTL (0xff800000 + (0x00e << 2)) ++#define P_AO_CPU_CNTL (volatile uint32_t *)(0xff800000 + (0x00e << 2)) ++#define AO_CPU_CNTL2 (0xff800000 + (0x00f << 2)) ++#define SEC_AO_CPU_CNTL2 (0xff800000 + (0x00f << 2)) ++#define P_AO_CPU_CNTL2 (volatile uint32_t *)(0xff800000 + (0x00f << 2)) ++#define AO_RTI_GEN_CNTL_REG0 (0xff800000 + (0x010 << 2)) ++#define SEC_AO_RTI_GEN_CNTL_REG0 (0xff800000 + (0x010 << 2)) ++#define P_AO_RTI_GEN_CNTL_REG0 (volatile uint32_t *)(0xff800000 + (0x010 << 2)) ++#define AO_CPU_CNTL_NS (0xff800000 + (0x011 << 2)) ++#define SEC_AO_CPU_CNTL_NS (0xff800000 + (0x011 << 2)) ++#define P_AO_CPU_CNTL_NS (volatile uint32_t *)(0xff800000 + (0x011 << 2)) ++#define AO_METAL_REVISION_1 (0xff800000 + (0x012 << 2)) ++#define SEC_AO_METAL_REVISION_1 (0xff800000 + (0x012 << 2)) ++#define P_AO_METAL_REVISION_1 (volatile uint32_t *)(0xff800000 + (0x012 << 2)) ++#define AO_CLK_GATE0 (0xff800000 + (0x013 << 2)) ++#define SEC_AO_CLK_GATE0 (0xff800000 + (0x013 << 2)) ++#define P_AO_CLK_GATE0 (volatile uint32_t *)(0xff800000 + (0x013 << 2)) ++#define AO_CLK_GATE0_SP (0xff800000 + (0x014 << 2)) ++#define SEC_AO_CLK_GATE0_SP (0xff800000 + (0x014 << 2)) ++#define P_AO_CLK_GATE0_SP (volatile uint32_t *)(0xff800000 + (0x014 << 2)) ++#define AO_TIMEBASE_CNTL1 (0xff800000 + (0x015 << 2)) ++#define SEC_AO_TIMEBASE_CNTL1 (0xff800000 + (0x015 << 2)) ++#define P_AO_TIMEBASE_CNTL1 (volatile uint32_t *)(0xff800000 + (0x015 << 2)) ++#define AO_OSCIN_CNTL (0xff800000 + (0x016 << 2)) ++#define SEC_AO_OSCIN_CNTL (0xff800000 + (0x016 << 2)) ++#define P_AO_OSCIN_CNTL (volatile uint32_t *)(0xff800000 + (0x016 << 2)) ++#define AO_PINMUX_LOCK (0xff800000 + (0x017 << 2)) ++#define SEC_AO_PINMUX_LOCK (0xff800000 + (0x017 << 2)) ++#define P_AO_PINMUX_LOCK (volatile uint32_t *)(0xff800000 + (0x017 << 2)) ++#define AO_AHB2DDR_CNTL (0xff800000 + (0x018 << 2)) ++#define SEC_AO_AHB2DDR_CNTL (0xff800000 + (0x018 << 2)) ++#define P_AO_AHB2DDR_CNTL (volatile uint32_t *)(0xff800000 + (0x018 << 2)) ++#define AO_TIMEBASE_CNTL (0xff800000 + (0x019 << 2)) ++#define SEC_AO_TIMEBASE_CNTL (0xff800000 + (0x019 << 2)) ++#define P_AO_TIMEBASE_CNTL (volatile uint32_t *)(0xff800000 + (0x019 << 2)) ++#define AO_GEN_CLK_CNTL (0xff800000 + (0x01a << 2)) ++#define SEC_AO_GEN_CLK_CNTL (0xff800000 + (0x01a << 2)) ++#define P_AO_GEN_CLK_CNTL (volatile uint32_t *)(0xff800000 + (0x01a << 2)) ++//`define AO_RTI_INTER_OSC_CTL0 8'h1b ++//`define AO_RTI_INTER_OSC_CTL1 8'h1c ++#define AO_CEC_CLK_CNTL_REG0 (0xff800000 + (0x01d << 2)) ++#define SEC_AO_CEC_CLK_CNTL_REG0 (0xff800000 + (0x01d << 2)) ++#define P_AO_CEC_CLK_CNTL_REG0 (volatile uint32_t *)(0xff800000 + (0x01d << 2)) ++#define AO_CEC_CLK_CNTL_REG1 (0xff800000 + (0x01e << 2)) ++#define SEC_AO_CEC_CLK_CNTL_REG1 (0xff800000 + (0x01e << 2)) ++#define P_AO_CEC_CLK_CNTL_REG1 (volatile uint32_t *)(0xff800000 + (0x01e << 2)) ++#define AO_METAL_REVISION (0xff800000 + (0x01f << 2)) ++#define SEC_AO_METAL_REVISION (0xff800000 + (0x01f << 2)) ++#define P_AO_METAL_REVISION (volatile uint32_t *)(0xff800000 + (0x01f << 2)) ++//`define AO_IRQ_MASK_FIQ_SEL 8'h20 ++#define AO_IRQ_GPIO_REG (0xff800000 + (0x021 << 2)) ++#define SEC_AO_IRQ_GPIO_REG (0xff800000 + (0x021 << 2)) ++#define P_AO_IRQ_GPIO_REG (volatile uint32_t *)(0xff800000 + (0x021 << 2)) ++//`define AO_IRQ_STAT 8'h22 ++//`define AO_IRQ_STAT_CLR 8'h23 ++#define AO_SAR_CLK (0xff800000 + (0x024 << 2)) ++#define SEC_AO_SAR_CLK (0xff800000 + (0x024 << 2)) ++#define P_AO_SAR_CLK (volatile uint32_t *)(0xff800000 + (0x024 << 2)) ++#define AO_RTC_ALT_CLK_CNTL0 (0xff800000 + (0x025 << 2)) ++#define SEC_AO_RTC_ALT_CLK_CNTL0 (0xff800000 + (0x025 << 2)) ++#define P_AO_RTC_ALT_CLK_CNTL0 (volatile uint32_t *)(0xff800000 + (0x025 << 2)) ++#define AO_RTC_ALT_CLK_CNTL1 (0xff800000 + (0x026 << 2)) ++#define SEC_AO_RTC_ALT_CLK_CNTL1 (0xff800000 + (0x026 << 2)) ++#define P_AO_RTC_ALT_CLK_CNTL1 (volatile uint32_t *)(0xff800000 + (0x026 << 2)) ++#define AO_TIMESTAMP_CNTL2 (0xff800000 + (0x027 << 2)) ++#define SEC_AO_TIMESTAMP_CNTL2 (0xff800000 + (0x027 << 2)) ++#define P_AO_TIMESTAMP_CNTL2 (volatile uint32_t *)(0xff800000 + (0x027 << 2)) ++#define AO_DEBUG_REG0 (0xff800000 + (0x028 << 2)) ++#define SEC_AO_DEBUG_REG0 (0xff800000 + (0x028 << 2)) ++#define P_AO_DEBUG_REG0 (volatile uint32_t *)(0xff800000 + (0x028 << 2)) ++#define AO_DEBUG_REG1 (0xff800000 + (0x029 << 2)) ++#define SEC_AO_DEBUG_REG1 (0xff800000 + (0x029 << 2)) ++#define P_AO_DEBUG_REG1 (volatile uint32_t *)(0xff800000 + (0x029 << 2)) ++#define AO_DEBUG_REG2 (0xff800000 + (0x02a << 2)) ++#define SEC_AO_DEBUG_REG2 (0xff800000 + (0x02a << 2)) ++#define P_AO_DEBUG_REG2 (volatile uint32_t *)(0xff800000 + (0x02a << 2)) ++#define AO_DEBUG_REG3 (0xff800000 + (0x02b << 2)) ++#define SEC_AO_DEBUG_REG3 (0xff800000 + (0x02b << 2)) ++#define P_AO_DEBUG_REG3 (volatile uint32_t *)(0xff800000 + (0x02b << 2)) ++#define AO_TIMESTAMP_CNTL1 (0xff800000 + (0x02c << 2)) ++#define SEC_AO_TIMESTAMP_CNTL1 (0xff800000 + (0x02c << 2)) ++#define P_AO_TIMESTAMP_CNTL1 (volatile uint32_t *)(0xff800000 + (0x02c << 2)) ++#define AO_TIMESTAMP_CNTL (0xff800000 + (0x02d << 2)) ++#define SEC_AO_TIMESTAMP_CNTL (0xff800000 + (0x02d << 2)) ++#define P_AO_TIMESTAMP_CNTL (volatile uint32_t *)(0xff800000 + (0x02d << 2)) ++#define AO_TIMESTAMP_RD0 (0xff800000 + (0x02e << 2)) ++#define SEC_AO_TIMESTAMP_RD0 (0xff800000 + (0x02e << 2)) ++#define P_AO_TIMESTAMP_RD0 (volatile uint32_t *)(0xff800000 + (0x02e << 2)) ++#define AO_TIMESTAMP_RD1 (0xff800000 + (0x02f << 2)) ++#define SEC_AO_TIMESTAMP_RD1 (0xff800000 + (0x02f << 2)) ++#define P_AO_TIMESTAMP_RD1 (volatile uint32_t *)(0xff800000 + (0x02f << 2)) ++#define SP_HOLD_CTRL (0xff800000 + (0x031 << 2)) ++#define SEC_SP_HOLD_CTRL (0xff800000 + (0x031 << 2)) ++#define P_SP_HOLD_CTRL (volatile uint32_t *)(0xff800000 + (0x031 << 2)) ++#define AO_FR_EE_WR_ONCE (0xff800000 + (0x032 << 2)) ++#define SEC_AO_FR_EE_WR_ONCE (0xff800000 + (0x032 << 2)) ++#define P_AO_FR_EE_WR_ONCE (volatile uint32_t *)(0xff800000 + (0x032 << 2)) ++#define AO_CPU_STAT1 (0xff800000 + (0x033 << 2)) ++#define SEC_AO_CPU_STAT1 (0xff800000 + (0x033 << 2)) ++#define P_AO_CPU_STAT1 (volatile uint32_t *)(0xff800000 + (0x033 << 2)) ++#define AO_CPU_STAT2 (0xff800000 + (0x034 << 2)) ++#define SEC_AO_CPU_STAT2 (0xff800000 + (0x034 << 2)) ++#define P_AO_CPU_STAT2 (volatile uint32_t *)(0xff800000 + (0x034 << 2)) ++#define AO_CPU_TIMESTAMP (0xff800000 + (0x035 << 2)) ++#define SEC_AO_CPU_TIMESTAMP (0xff800000 + (0x035 << 2)) ++#define P_AO_CPU_TIMESTAMP (volatile uint32_t *)(0xff800000 + (0x035 << 2)) ++#define AO_CPU_TIMESTAMP2 (0xff800000 + (0x036 << 2)) ++#define SEC_AO_CPU_TIMESTAMP2 (0xff800000 + (0x036 << 2)) ++#define P_AO_CPU_TIMESTAMP2 (volatile uint32_t *)(0xff800000 + (0x036 << 2)) ++#define AO_CPU_CNTL3 (0xff800000 + (0x037 << 2)) ++#define SEC_AO_CPU_CNTL3 (0xff800000 + (0x037 << 2)) ++#define P_AO_CPU_CNTL3 (volatile uint32_t *)(0xff800000 + (0x037 << 2)) ++// general Power control ++#define AO_RTI_PWR_SYS_CPU_CNTL0 (0xff800000 + (0x038 << 2)) ++#define SEC_AO_RTI_PWR_SYS_CPU_CNTL0 (0xff800000 + (0x038 << 2)) ++#define P_AO_RTI_PWR_SYS_CPU_CNTL0 (volatile uint32_t *)(0xff800000 + (0x038 << 2)) ++#define AO_RTI_PWR_SYS_CPU_CNTL1 (0xff800000 + (0x039 << 2)) ++#define SEC_AO_RTI_PWR_SYS_CPU_CNTL1 (0xff800000 + (0x039 << 2)) ++#define P_AO_RTI_PWR_SYS_CPU_CNTL1 (volatile uint32_t *)(0xff800000 + (0x039 << 2)) ++#define AO_RTI_GEN_PWR_SLEEP0 (0xff800000 + (0x03a << 2)) ++#define SEC_AO_RTI_GEN_PWR_SLEEP0 (0xff800000 + (0x03a << 2)) ++#define P_AO_RTI_GEN_PWR_SLEEP0 (volatile uint32_t *)(0xff800000 + (0x03a << 2)) ++#define AO_RTI_GEN_PWR_ISO0 (0xff800000 + (0x03b << 2)) ++#define SEC_AO_RTI_GEN_PWR_ISO0 (0xff800000 + (0x03b << 2)) ++#define P_AO_RTI_GEN_PWR_ISO0 (volatile uint32_t *)(0xff800000 + (0x03b << 2)) ++#define AO_RTI_GEN_PWR_ACK0 (0xff800000 + (0x03c << 2)) ++#define SEC_AO_RTI_GEN_PWR_ACK0 (0xff800000 + (0x03c << 2)) ++#define P_AO_RTI_GEN_PWR_ACK0 (volatile uint32_t *)(0xff800000 + (0x03c << 2)) ++#define AO_RTI_PWR_SYS_CPU_MEM_PD0 (0xff800000 + (0x03d << 2)) ++#define SEC_AO_RTI_PWR_SYS_CPU_MEM_PD0 (0xff800000 + (0x03d << 2)) ++#define P_AO_RTI_PWR_SYS_CPU_MEM_PD0 (volatile uint32_t *)(0xff800000 + (0x03d << 2)) ++#define AO_RTI_PWR_SYS_CPU_MEM_PD1 (0xff800000 + (0x03e << 2)) ++#define SEC_AO_RTI_PWR_SYS_CPU_MEM_PD1 (0xff800000 + (0x03e << 2)) ++#define P_AO_RTI_PWR_SYS_CPU_MEM_PD1 (volatile uint32_t *)(0xff800000 + (0x03e << 2)) ++#define AO_CPU_CNTL4 (0xff800000 + (0x03f << 2)) ++#define SEC_AO_CPU_CNTL4 (0xff800000 + (0x03f << 2)) ++#define P_AO_CPU_CNTL4 (volatile uint32_t *)(0xff800000 + (0x03f << 2)) ++#define AO_CEC_GEN_CNTL (0xff800000 + (0x040 << 2)) ++#define SEC_AO_CEC_GEN_CNTL (0xff800000 + (0x040 << 2)) ++#define P_AO_CEC_GEN_CNTL (volatile uint32_t *)(0xff800000 + (0x040 << 2)) ++#define AO_CEC_RW_REG (0xff800000 + (0x041 << 2)) ++#define SEC_AO_CEC_RW_REG (0xff800000 + (0x041 << 2)) ++#define P_AO_CEC_RW_REG (volatile uint32_t *)(0xff800000 + (0x041 << 2)) ++#define AO_CEC_INTR_MASKN (0xff800000 + (0x042 << 2)) ++#define SEC_AO_CEC_INTR_MASKN (0xff800000 + (0x042 << 2)) ++#define P_AO_CEC_INTR_MASKN (volatile uint32_t *)(0xff800000 + (0x042 << 2)) ++#define AO_CEC_INTR_CLR (0xff800000 + (0x043 << 2)) ++#define SEC_AO_CEC_INTR_CLR (0xff800000 + (0x043 << 2)) ++#define P_AO_CEC_INTR_CLR (volatile uint32_t *)(0xff800000 + (0x043 << 2)) ++#define AO_CEC_INTR_STAT (0xff800000 + (0x044 << 2)) ++#define SEC_AO_CEC_INTR_STAT (0xff800000 + (0x044 << 2)) ++#define P_AO_CEC_INTR_STAT (volatile uint32_t *)(0xff800000 + (0x044 << 2)) ++#define AO_CPU_CNTL5 (0xff800000 + (0x045 << 2)) ++#define SEC_AO_CPU_CNTL5 (0xff800000 + (0x045 << 2)) ++#define P_AO_CPU_CNTL5 (volatile uint32_t *)(0xff800000 + (0x045 << 2)) ++#define AO_WATCHDOG_CNTL (0xff800000 + (0x048 << 2)) ++#define SEC_AO_WATCHDOG_CNTL (0xff800000 + (0x048 << 2)) ++#define P_AO_WATCHDOG_CNTL (volatile uint32_t *)(0xff800000 + (0x048 << 2)) ++#define AO_WATCHDOG_CNTL1 (0xff800000 + (0x049 << 2)) ++#define SEC_AO_WATCHDOG_CNTL1 (0xff800000 + (0x049 << 2)) ++#define P_AO_WATCHDOG_CNTL1 (volatile uint32_t *)(0xff800000 + (0x049 << 2)) ++#define AO_WATCHDOG_TCNT (0xff800000 + (0x04a << 2)) ++#define SEC_AO_WATCHDOG_TCNT (0xff800000 + (0x04a << 2)) ++#define P_AO_WATCHDOG_TCNT (volatile uint32_t *)(0xff800000 + (0x04a << 2)) ++#define AO_WATCHDOG_RESET (0xff800000 + (0x04b << 2)) ++#define SEC_AO_WATCHDOG_RESET (0xff800000 + (0x04b << 2)) ++#define P_AO_WATCHDOG_RESET (volatile uint32_t *)(0xff800000 + (0x04b << 2)) ++#define AO_RTI_STICKY_REG0 (0xff800000 + (0x04c << 2)) ++#define SEC_AO_RTI_STICKY_REG0 (0xff800000 + (0x04c << 2)) ++#define P_AO_RTI_STICKY_REG0 (volatile uint32_t *)(0xff800000 + (0x04c << 2)) ++#define AO_RTI_STICKY_REG1 (0xff800000 + (0x04d << 2)) ++#define SEC_AO_RTI_STICKY_REG1 (0xff800000 + (0x04d << 2)) ++#define P_AO_RTI_STICKY_REG1 (volatile uint32_t *)(0xff800000 + (0x04d << 2)) ++#define AO_RTI_STICKY_REG2 (0xff800000 + (0x04e << 2)) ++#define SEC_AO_RTI_STICKY_REG2 (0xff800000 + (0x04e << 2)) ++#define P_AO_RTI_STICKY_REG2 (volatile uint32_t *)(0xff800000 + (0x04e << 2)) ++#define AO_RTI_STICKY_REG3 (0xff800000 + (0x04f << 2)) ++#define SEC_AO_RTI_STICKY_REG3 (0xff800000 + (0x04f << 2)) ++#define P_AO_RTI_STICKY_REG3 (volatile uint32_t *)(0xff800000 + (0x04f << 2)) ++// ++// Secure APB3 Slot 2 registers ++// ++#define AO_SEC_REG0 (0xff800000 + (0x050 << 2)) ++#define SEC_AO_SEC_REG0 (0xff800000 + (0x050 << 2)) ++#define P_AO_SEC_REG0 (volatile uint32_t *)(0xff800000 + (0x050 << 2)) ++//`define AO_SEC_REG1 8'h51 ++#define AO_IR_BLASTER_ADDR0 (0xff800000 + (0x053 << 2)) ++#define SEC_AO_IR_BLASTER_ADDR0 (0xff800000 + (0x053 << 2)) ++#define P_AO_IR_BLASTER_ADDR0 (volatile uint32_t *)(0xff800000 + (0x053 << 2)) ++#define AO_IR_BLASTER_ADDR1 (0xff800000 + (0x054 << 2)) ++#define SEC_AO_IR_BLASTER_ADDR1 (0xff800000 + (0x054 << 2)) ++#define P_AO_IR_BLASTER_ADDR1 (volatile uint32_t *)(0xff800000 + (0x054 << 2)) ++#define AO_IR_BLASTER_ADDR2 (0xff800000 + (0x055 << 2)) ++#define SEC_AO_IR_BLASTER_ADDR2 (0xff800000 + (0x055 << 2)) ++#define P_AO_IR_BLASTER_ADDR2 (volatile uint32_t *)(0xff800000 + (0x055 << 2)) ++#define AO_IR_BLASTER_ADDR3 (0xff800000 + (0x056 << 2)) ++#define SEC_AO_IR_BLASTER_ADDR3 (0xff800000 + (0x056 << 2)) ++#define P_AO_IR_BLASTER_ADDR3 (volatile uint32_t *)(0xff800000 + (0x056 << 2)) ++#define AO_SEC_TMODE_PWD0 (0xff800000 + (0x058 << 2)) ++#define SEC_AO_SEC_TMODE_PWD0 (0xff800000 + (0x058 << 2)) ++#define P_AO_SEC_TMODE_PWD0 (volatile uint32_t *)(0xff800000 + (0x058 << 2)) ++#define AO_SEC_TMODE_PWD1 (0xff800000 + (0x059 << 2)) ++#define SEC_AO_SEC_TMODE_PWD1 (0xff800000 + (0x059 << 2)) ++#define P_AO_SEC_TMODE_PWD1 (volatile uint32_t *)(0xff800000 + (0x059 << 2)) ++#define AO_SEC_TMODE_PWD2 (0xff800000 + (0x05a << 2)) ++#define SEC_AO_SEC_TMODE_PWD2 (0xff800000 + (0x05a << 2)) ++#define P_AO_SEC_TMODE_PWD2 (volatile uint32_t *)(0xff800000 + (0x05a << 2)) ++#define AO_SEC_TMODE_PWD3 (0xff800000 + (0x05b << 2)) ++#define SEC_AO_SEC_TMODE_PWD3 (0xff800000 + (0x05b << 2)) ++#define P_AO_SEC_TMODE_PWD3 (volatile uint32_t *)(0xff800000 + (0x05b << 2)) ++#define AO_WRITE_ONCE0 (0xff800000 + (0x05c << 2)) ++#define SEC_AO_WRITE_ONCE0 (0xff800000 + (0x05c << 2)) ++#define P_AO_WRITE_ONCE0 (volatile uint32_t *)(0xff800000 + (0x05c << 2)) ++#define AO_WRITE_ONCE1 (0xff800000 + (0x05d << 2)) ++#define SEC_AO_WRITE_ONCE1 (0xff800000 + (0x05d << 2)) ++#define P_AO_WRITE_ONCE1 (volatile uint32_t *)(0xff800000 + (0x05d << 2)) ++#define AO_WRITE_ONCE2 (0xff800000 + (0x05e << 2)) ++#define SEC_AO_WRITE_ONCE2 (0xff800000 + (0x05e << 2)) ++#define P_AO_WRITE_ONCE2 (volatile uint32_t *)(0xff800000 + (0x05e << 2)) ++#define AO_SEC_SCRATCH (0xff800000 + (0x05f << 2)) ++#define SEC_AO_SEC_SCRATCH (0xff800000 + (0x05f << 2)) ++#define P_AO_SEC_SCRATCH (volatile uint32_t *)(0xff800000 + (0x05f << 2)) ++#define AO_MSG_INDEX0 (0xff800000 + (0x060 << 2)) ++#define SEC_AO_MSG_INDEX0 (0xff800000 + (0x060 << 2)) ++#define P_AO_MSG_INDEX0 (volatile uint32_t *)(0xff800000 + (0x060 << 2)) ++#define AO_MSG_INDEX1 (0xff800000 + (0x061 << 2)) ++#define SEC_AO_MSG_INDEX1 (0xff800000 + (0x061 << 2)) ++#define P_AO_MSG_INDEX1 (volatile uint32_t *)(0xff800000 + (0x061 << 2)) ++#define AO_MSG_INDEX2 (0xff800000 + (0x062 << 2)) ++#define SEC_AO_MSG_INDEX2 (0xff800000 + (0x062 << 2)) ++#define P_AO_MSG_INDEX2 (volatile uint32_t *)(0xff800000 + (0x062 << 2)) ++#define AO_MSG_INDEX3 (0xff800000 + (0x063 << 2)) ++#define SEC_AO_MSG_INDEX3 (0xff800000 + (0x063 << 2)) ++#define P_AO_MSG_INDEX3 (volatile uint32_t *)(0xff800000 + (0x063 << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_MASK_0 (0xff800000 + (0x066 << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_MASK_0 (0xff800000 + (0x066 << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_MASK_0 (volatile uint32_t *)(0xff800000 + (0x066 << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_MASK_1 (0xff800000 + (0x067 << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_MASK_1 (0xff800000 + (0x067 << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_MASK_1 (volatile uint32_t *)(0xff800000 + (0x067 << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_MASK_2 (0xff800000 + (0x068 << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_MASK_2 (0xff800000 + (0x068 << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_MASK_2 (volatile uint32_t *)(0xff800000 + (0x068 << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_REG0_0 (0xff800000 + (0x069 << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_REG0_0 (0xff800000 + (0x069 << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_REG0_0 (volatile uint32_t *)(0xff800000 + (0x069 << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_REG0_1 (0xff800000 + (0x06a << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_REG0_1 (0xff800000 + (0x06a << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_REG0_1 (volatile uint32_t *)(0xff800000 + (0x06a << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_REG0_2 (0xff800000 + (0x06b << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_REG0_2 (0xff800000 + (0x06b << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_REG0_2 (volatile uint32_t *)(0xff800000 + (0x06b << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_REG1_0 (0xff800000 + (0x06c << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_REG1_0 (0xff800000 + (0x06c << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_REG1_0 (volatile uint32_t *)(0xff800000 + (0x06c << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_REG1_1 (0xff800000 + (0x06d << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_REG1_1 (0xff800000 + (0x06d << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_REG1_1 (volatile uint32_t *)(0xff800000 + (0x06d << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_REG1_2 (0xff800000 + (0x06e << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_REG1_2 (0xff800000 + (0x06e << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_REG1_2 (volatile uint32_t *)(0xff800000 + (0x06e << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_REG2_0 (0xff800000 + (0x06f << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_REG2_0 (0xff800000 + (0x06f << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_REG2_0 (volatile uint32_t *)(0xff800000 + (0x06f << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_REG2_1 (0xff800000 + (0x070 << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_REG2_1 (0xff800000 + (0x070 << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_REG2_1 (volatile uint32_t *)(0xff800000 + (0x070 << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_REG2_2 (0xff800000 + (0x071 << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_REG2_2 (0xff800000 + (0x071 << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_REG2_2 (volatile uint32_t *)(0xff800000 + (0x071 << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_REG3_0 (0xff800000 + (0x072 << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_REG3_0 (0xff800000 + (0x072 << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_REG3_0 (volatile uint32_t *)(0xff800000 + (0x072 << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_REG3_1 (0xff800000 + (0x073 << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_REG3_1 (0xff800000 + (0x073 << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_REG3_1 (volatile uint32_t *)(0xff800000 + (0x073 << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_REG3_2 (0xff800000 + (0x074 << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_REG3_2 (0xff800000 + (0x074 << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_REG3_2 (volatile uint32_t *)(0xff800000 + (0x074 << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_REG4_0 (0xff800000 + (0x075 << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_REG4_0 (0xff800000 + (0x075 << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_REG4_0 (volatile uint32_t *)(0xff800000 + (0x075 << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_REG4_1 (0xff800000 + (0x076 << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_REG4_1 (0xff800000 + (0x076 << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_REG4_1 (volatile uint32_t *)(0xff800000 + (0x076 << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_REG4_2 (0xff800000 + (0x077 << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_REG4_2 (0xff800000 + (0x077 << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_REG4_2 (volatile uint32_t *)(0xff800000 + (0x077 << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_REG5_0 (0xff800000 + (0x078 << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_REG5_0 (0xff800000 + (0x078 << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_REG5_0 (volatile uint32_t *)(0xff800000 + (0x078 << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_REG5_1 (0xff800000 + (0x079 << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_REG5_1 (0xff800000 + (0x079 << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_REG5_1 (volatile uint32_t *)(0xff800000 + (0x079 << 2)) ++#define AO_SEC_SHARED_AHB_SRAM_REG5_2 (0xff800000 + (0x07a << 2)) ++#define SEC_AO_SEC_SHARED_AHB_SRAM_REG5_2 (0xff800000 + (0x07a << 2)) ++#define P_AO_SEC_SHARED_AHB_SRAM_REG5_2 (volatile uint32_t *)(0xff800000 + (0x07a << 2)) ++#define AO_SEC_AO_CPU_SRAM_REG0_0 (0xff800000 + (0x07c << 2)) ++#define SEC_AO_SEC_AO_CPU_SRAM_REG0_0 (0xff800000 + (0x07c << 2)) ++#define P_AO_SEC_AO_CPU_SRAM_REG0_0 (volatile uint32_t *)(0xff800000 + (0x07c << 2)) ++#define AO_SEC_AO_CPU_SRAM_REG0_1 (0xff800000 + (0x07d << 2)) ++#define SEC_AO_SEC_AO_CPU_SRAM_REG0_1 (0xff800000 + (0x07d << 2)) ++#define P_AO_SEC_AO_CPU_SRAM_REG0_1 (volatile uint32_t *)(0xff800000 + (0x07d << 2)) ++#define AO_SEC_AO_CPU_SRAM_REG1_0 (0xff800000 + (0x07e << 2)) ++#define SEC_AO_SEC_AO_CPU_SRAM_REG1_0 (0xff800000 + (0x07e << 2)) ++#define P_AO_SEC_AO_CPU_SRAM_REG1_0 (volatile uint32_t *)(0xff800000 + (0x07e << 2)) ++#define AO_SEC_AO_CPU_SRAM_REG1_1 (0xff800000 + (0x07f << 2)) ++#define SEC_AO_SEC_AO_CPU_SRAM_REG1_1 (0xff800000 + (0x07f << 2)) ++#define P_AO_SEC_AO_CPU_SRAM_REG1_1 (volatile uint32_t *)(0xff800000 + (0x07f << 2)) ++#define AO_SEC_SD_CFG0 (0xff800000 + (0x080 << 2)) ++#define SEC_AO_SEC_SD_CFG0 (0xff800000 + (0x080 << 2)) ++#define P_AO_SEC_SD_CFG0 (volatile uint32_t *)(0xff800000 + (0x080 << 2)) ++#define AO_SEC_SD_CFG1 (0xff800000 + (0x081 << 2)) ++#define SEC_AO_SEC_SD_CFG1 (0xff800000 + (0x081 << 2)) ++#define P_AO_SEC_SD_CFG1 (volatile uint32_t *)(0xff800000 + (0x081 << 2)) ++#define AO_SEC_SD_CFG2 (0xff800000 + (0x082 << 2)) ++#define SEC_AO_SEC_SD_CFG2 (0xff800000 + (0x082 << 2)) ++#define P_AO_SEC_SD_CFG2 (volatile uint32_t *)(0xff800000 + (0x082 << 2)) ++#define AO_SEC_SD_CFG3 (0xff800000 + (0x083 << 2)) ++#define SEC_AO_SEC_SD_CFG3 (0xff800000 + (0x083 << 2)) ++#define P_AO_SEC_SD_CFG3 (volatile uint32_t *)(0xff800000 + (0x083 << 2)) ++#define AO_SEC_SD_CFG4 (0xff800000 + (0x084 << 2)) ++#define SEC_AO_SEC_SD_CFG4 (0xff800000 + (0x084 << 2)) ++#define P_AO_SEC_SD_CFG4 (volatile uint32_t *)(0xff800000 + (0x084 << 2)) ++#define AO_SEC_SD_CFG5 (0xff800000 + (0x085 << 2)) ++#define SEC_AO_SEC_SD_CFG5 (0xff800000 + (0x085 << 2)) ++#define P_AO_SEC_SD_CFG5 (volatile uint32_t *)(0xff800000 + (0x085 << 2)) ++#define AO_SEC_SD_CFG6 (0xff800000 + (0x086 << 2)) ++#define SEC_AO_SEC_SD_CFG6 (0xff800000 + (0x086 << 2)) ++#define P_AO_SEC_SD_CFG6 (volatile uint32_t *)(0xff800000 + (0x086 << 2)) ++#define AO_SEC_SD_CFG7 (0xff800000 + (0x087 << 2)) ++#define SEC_AO_SEC_SD_CFG7 (0xff800000 + (0x087 << 2)) ++#define P_AO_SEC_SD_CFG7 (volatile uint32_t *)(0xff800000 + (0x087 << 2)) ++#define AO_SEC_SD_CFG8 (0xff800000 + (0x088 << 2)) ++#define SEC_AO_SEC_SD_CFG8 (0xff800000 + (0x088 << 2)) ++#define P_AO_SEC_SD_CFG8 (volatile uint32_t *)(0xff800000 + (0x088 << 2)) ++#define AO_SEC_SD_CFG9 (0xff800000 + (0x089 << 2)) ++#define SEC_AO_SEC_SD_CFG9 (0xff800000 + (0x089 << 2)) ++#define P_AO_SEC_SD_CFG9 (volatile uint32_t *)(0xff800000 + (0x089 << 2)) ++#define AO_SEC_SD_CFG10 (0xff800000 + (0x08a << 2)) ++#define SEC_AO_SEC_SD_CFG10 (0xff800000 + (0x08a << 2)) ++#define P_AO_SEC_SD_CFG10 (volatile uint32_t *)(0xff800000 + (0x08a << 2)) ++#define AO_SEC_SD_CFG11 (0xff800000 + (0x08b << 2)) ++#define SEC_AO_SEC_SD_CFG11 (0xff800000 + (0x08b << 2)) ++#define P_AO_SEC_SD_CFG11 (volatile uint32_t *)(0xff800000 + (0x08b << 2)) ++#define AO_SEC_SD_CFG12 (0xff800000 + (0x08c << 2)) ++#define SEC_AO_SEC_SD_CFG12 (0xff800000 + (0x08c << 2)) ++#define P_AO_SEC_SD_CFG12 (volatile uint32_t *)(0xff800000 + (0x08c << 2)) ++#define AO_SEC_SD_CFG13 (0xff800000 + (0x08d << 2)) ++#define SEC_AO_SEC_SD_CFG13 (0xff800000 + (0x08d << 2)) ++#define P_AO_SEC_SD_CFG13 (volatile uint32_t *)(0xff800000 + (0x08d << 2)) ++#define AO_SEC_SD_CFG14 (0xff800000 + (0x08e << 2)) ++#define SEC_AO_SEC_SD_CFG14 (0xff800000 + (0x08e << 2)) ++#define P_AO_SEC_SD_CFG14 (volatile uint32_t *)(0xff800000 + (0x08e << 2)) ++#define AO_SEC_SD_CFG15 (0xff800000 + (0x08f << 2)) ++#define SEC_AO_SEC_SD_CFG15 (0xff800000 + (0x08f << 2)) ++#define P_AO_SEC_SD_CFG15 (volatile uint32_t *)(0xff800000 + (0x08f << 2)) ++#define AO_SEC_GP_CFG0 (0xff800000 + (0x090 << 2)) ++#define SEC_AO_SEC_GP_CFG0 (0xff800000 + (0x090 << 2)) ++#define P_AO_SEC_GP_CFG0 (volatile uint32_t *)(0xff800000 + (0x090 << 2)) ++#define AO_SEC_GP_CFG1 (0xff800000 + (0x091 << 2)) ++#define SEC_AO_SEC_GP_CFG1 (0xff800000 + (0x091 << 2)) ++#define P_AO_SEC_GP_CFG1 (volatile uint32_t *)(0xff800000 + (0x091 << 2)) ++#define AO_SEC_GP_CFG2 (0xff800000 + (0x092 << 2)) ++#define SEC_AO_SEC_GP_CFG2 (0xff800000 + (0x092 << 2)) ++#define P_AO_SEC_GP_CFG2 (volatile uint32_t *)(0xff800000 + (0x092 << 2)) ++#define AO_SEC_GP_CFG3 (0xff800000 + (0x093 << 2)) ++#define SEC_AO_SEC_GP_CFG3 (0xff800000 + (0x093 << 2)) ++#define P_AO_SEC_GP_CFG3 (volatile uint32_t *)(0xff800000 + (0x093 << 2)) ++#define AO_SEC_GP_CFG4 (0xff800000 + (0x094 << 2)) ++#define SEC_AO_SEC_GP_CFG4 (0xff800000 + (0x094 << 2)) ++#define P_AO_SEC_GP_CFG4 (volatile uint32_t *)(0xff800000 + (0x094 << 2)) ++#define AO_SEC_GP_CFG5 (0xff800000 + (0x095 << 2)) ++#define SEC_AO_SEC_GP_CFG5 (0xff800000 + (0x095 << 2)) ++#define P_AO_SEC_GP_CFG5 (volatile uint32_t *)(0xff800000 + (0x095 << 2)) ++#define AO_SEC_GP_CFG6 (0xff800000 + (0x096 << 2)) ++#define SEC_AO_SEC_GP_CFG6 (0xff800000 + (0x096 << 2)) ++#define P_AO_SEC_GP_CFG6 (volatile uint32_t *)(0xff800000 + (0x096 << 2)) ++#define AO_SEC_GP_CFG7 (0xff800000 + (0x097 << 2)) ++#define SEC_AO_SEC_GP_CFG7 (0xff800000 + (0x097 << 2)) ++#define P_AO_SEC_GP_CFG7 (volatile uint32_t *)(0xff800000 + (0x097 << 2)) ++#define AO_SEC_GP_CFG8 (0xff800000 + (0x098 << 2)) ++#define SEC_AO_SEC_GP_CFG8 (0xff800000 + (0x098 << 2)) ++#define P_AO_SEC_GP_CFG8 (volatile uint32_t *)(0xff800000 + (0x098 << 2)) ++#define AO_SEC_GP_CFG9 (0xff800000 + (0x099 << 2)) ++#define SEC_AO_SEC_GP_CFG9 (0xff800000 + (0x099 << 2)) ++#define P_AO_SEC_GP_CFG9 (volatile uint32_t *)(0xff800000 + (0x099 << 2)) ++#define AO_SEC_GP_CFG10 (0xff800000 + (0x09a << 2)) ++#define SEC_AO_SEC_GP_CFG10 (0xff800000 + (0x09a << 2)) ++#define P_AO_SEC_GP_CFG10 (volatile uint32_t *)(0xff800000 + (0x09a << 2)) ++#define AO_SEC_GP_CFG11 (0xff800000 + (0x09b << 2)) ++#define SEC_AO_SEC_GP_CFG11 (0xff800000 + (0x09b << 2)) ++#define P_AO_SEC_GP_CFG11 (volatile uint32_t *)(0xff800000 + (0x09b << 2)) ++#define AO_SEC_GP_CFG12 (0xff800000 + (0x09c << 2)) ++#define SEC_AO_SEC_GP_CFG12 (0xff800000 + (0x09c << 2)) ++#define P_AO_SEC_GP_CFG12 (volatile uint32_t *)(0xff800000 + (0x09c << 2)) ++#define AO_SEC_GP_CFG13 (0xff800000 + (0x09d << 2)) ++#define SEC_AO_SEC_GP_CFG13 (0xff800000 + (0x09d << 2)) ++#define P_AO_SEC_GP_CFG13 (volatile uint32_t *)(0xff800000 + (0x09d << 2)) ++#define AO_SEC_GP_CFG14 (0xff800000 + (0x09e << 2)) ++#define SEC_AO_SEC_GP_CFG14 (0xff800000 + (0x09e << 2)) ++#define P_AO_SEC_GP_CFG14 (volatile uint32_t *)(0xff800000 + (0x09e << 2)) ++#define AO_SEC_GP_CFG15 (0xff800000 + (0x09f << 2)) ++#define SEC_AO_SEC_GP_CFG15 (0xff800000 + (0x09f << 2)) ++#define P_AO_SEC_GP_CFG15 (volatile uint32_t *)(0xff800000 + (0x09f << 2)) ++#define AO_CECB_CLK_CNTL_REG0 (0xff800000 + (0x0a0 << 2)) ++#define SEC_AO_CECB_CLK_CNTL_REG0 (0xff800000 + (0x0a0 << 2)) ++#define P_AO_CECB_CLK_CNTL_REG0 (volatile uint32_t *)(0xff800000 + (0x0a0 << 2)) ++#define AO_CECB_CLK_CNTL_REG1 (0xff800000 + (0x0a1 << 2)) ++#define SEC_AO_CECB_CLK_CNTL_REG1 (0xff800000 + (0x0a1 << 2)) ++#define P_AO_CECB_CLK_CNTL_REG1 (volatile uint32_t *)(0xff800000 + (0x0a1 << 2)) ++#define AO_CECB_GEN_CNTL (0xff800000 + (0x0a2 << 2)) ++#define SEC_AO_CECB_GEN_CNTL (0xff800000 + (0x0a2 << 2)) ++#define P_AO_CECB_GEN_CNTL (volatile uint32_t *)(0xff800000 + (0x0a2 << 2)) ++#define AO_CECB_RW_REG (0xff800000 + (0x0a3 << 2)) ++#define SEC_AO_CECB_RW_REG (0xff800000 + (0x0a3 << 2)) ++#define P_AO_CECB_RW_REG (volatile uint32_t *)(0xff800000 + (0x0a3 << 2)) ++#define AO_CECB_INTR_MASKN (0xff800000 + (0x0a4 << 2)) ++#define SEC_AO_CECB_INTR_MASKN (0xff800000 + (0x0a4 << 2)) ++#define P_AO_CECB_INTR_MASKN (volatile uint32_t *)(0xff800000 + (0x0a4 << 2)) ++#define AO_CECB_INTR_CLR (0xff800000 + (0x0a5 << 2)) ++#define SEC_AO_CECB_INTR_CLR (0xff800000 + (0x0a5 << 2)) ++#define P_AO_CECB_INTR_CLR (volatile uint32_t *)(0xff800000 + (0x0a5 << 2)) ++#define AO_CECB_INTR_STAT (0xff800000 + (0x0a6 << 2)) ++#define SEC_AO_CECB_INTR_STAT (0xff800000 + (0x0a6 << 2)) ++#define P_AO_CECB_INTR_STAT (volatile uint32_t *)(0xff800000 + (0x0a6 << 2)) ++#define AO_SEC_M4_CPU_SRAM_REG0_0 (0xff800000 + (0x0a7 << 2)) ++#define SEC_AO_SEC_M4_CPU_SRAM_REG0_0 (0xff800000 + (0x0a7 << 2)) ++#define P_AO_SEC_M4_CPU_SRAM_REG0_0 (volatile uint32_t *)(0xff800000 + (0x0a7 << 2)) ++#define AO_SEC_M4_CPU_SRAM_REG0_1 (0xff800000 + (0x0a8 << 2)) ++#define SEC_AO_SEC_M4_CPU_SRAM_REG0_1 (0xff800000 + (0x0a8 << 2)) ++#define P_AO_SEC_M4_CPU_SRAM_REG0_1 (volatile uint32_t *)(0xff800000 + (0x0a8 << 2)) ++#define AO_SEC_M4_CPU_SRAM_REG1_0 (0xff800000 + (0x0a9 << 2)) ++#define SEC_AO_SEC_M4_CPU_SRAM_REG1_0 (0xff800000 + (0x0a9 << 2)) ++#define P_AO_SEC_M4_CPU_SRAM_REG1_0 (volatile uint32_t *)(0xff800000 + (0x0a9 << 2)) ++#define AO_SEC_M4_CPU_SRAM_REG1_1 (0xff800000 + (0x0aa << 2)) ++#define SEC_AO_SEC_M4_CPU_SRAM_REG1_1 (0xff800000 + (0x0aa << 2)) ++#define P_AO_SEC_M4_CPU_SRAM_REG1_1 (volatile uint32_t *)(0xff800000 + (0x0aa << 2)) ++#define AO_SEC_M4_CPU_SRAM_REG2_0 (0xff800000 + (0x0ab << 2)) ++#define SEC_AO_SEC_M4_CPU_SRAM_REG2_0 (0xff800000 + (0x0ab << 2)) ++#define P_AO_SEC_M4_CPU_SRAM_REG2_0 (volatile uint32_t *)(0xff800000 + (0x0ab << 2)) ++//`define AO_RTC_ADDR0 8'h70 //TODO: DEFINE IF WE'RE IMPLEMENTING AO_RTC ++//`define AO_RTC_ADDR1 8'h71 //TODO: DEFINE IF WE'RE IMPLEMENTING AO_RTC ++//`define AO_RTC_ADDR2 8'h72 //TODO: DEFINE IF WE'RE IMPLEMENTING AO_RTC ++//`define AO_RTC_ADDR3 8'h73 //TODO: DEFINE IF WE'RE IMPLEMENTING AO_RTC ++//`define AO_RTC_ADDR4 8'h74 //TODO: DEFINE IF WE'RE IMPLEMENTING AO_RTC ++#define AO_SEC_JTAG_SP_CTRL (0xff800000 + (0x0ac << 2)) ++#define SEC_AO_SEC_JTAG_SP_CTRL (0xff800000 + (0x0ac << 2)) ++#define P_AO_SEC_JTAG_SP_CTRL (volatile uint32_t *)(0xff800000 + (0x0ac << 2)) ++#define AO_SEC_JTAG_PWD_SP_0 (0xff800000 + (0x0ad << 2)) ++#define SEC_AO_SEC_JTAG_PWD_SP_0 (0xff800000 + (0x0ad << 2)) ++#define P_AO_SEC_JTAG_PWD_SP_0 (volatile uint32_t *)(0xff800000 + (0x0ad << 2)) ++#define AO_SEC_JTAG_PWD_SP_1 (0xff800000 + (0x0ae << 2)) ++#define SEC_AO_SEC_JTAG_PWD_SP_1 (0xff800000 + (0x0ae << 2)) ++#define P_AO_SEC_JTAG_PWD_SP_1 (volatile uint32_t *)(0xff800000 + (0x0ae << 2)) ++#define AO_SEC_JTAG_PWD_SP_2 (0xff800000 + (0x0af << 2)) ++#define SEC_AO_SEC_JTAG_PWD_SP_2 (0xff800000 + (0x0af << 2)) ++#define P_AO_SEC_JTAG_PWD_SP_2 (volatile uint32_t *)(0xff800000 + (0x0af << 2)) ++#define AO_SEC_JTAG_PWD_SP_3 (0xff800000 + (0x0b0 << 2)) ++#define SEC_AO_SEC_JTAG_PWD_SP_3 (0xff800000 + (0x0b0 << 2)) ++#define P_AO_SEC_JTAG_PWD_SP_3 (volatile uint32_t *)(0xff800000 + (0x0b0 << 2)) ++#define AO_SEC_JTAG_PWD_SP_CNTL (0xff800000 + (0x0b1 << 2)) ++#define SEC_AO_SEC_JTAG_PWD_SP_CNTL (0xff800000 + (0x0b1 << 2)) ++#define P_AO_SEC_JTAG_PWD_SP_CNTL (volatile uint32_t *)(0xff800000 + (0x0b1 << 2)) ++#define AO_SEC_JTAG_PWD_SP_ADDR0 (0xff800000 + (0x0b2 << 2)) ++#define SEC_AO_SEC_JTAG_PWD_SP_ADDR0 (0xff800000 + (0x0b2 << 2)) ++#define P_AO_SEC_JTAG_PWD_SP_ADDR0 (volatile uint32_t *)(0xff800000 + (0x0b2 << 2)) ++#define AO_SEC_JTAG_PWD_SP_ADDR1 (0xff800000 + (0x0b3 << 2)) ++#define SEC_AO_SEC_JTAG_PWD_SP_ADDR1 (0xff800000 + (0x0b3 << 2)) ++#define P_AO_SEC_JTAG_PWD_SP_ADDR1 (volatile uint32_t *)(0xff800000 + (0x0b3 << 2)) ++#define AO_SEC_JTAG_PWD_SP_ADDR2 (0xff800000 + (0x0b4 << 2)) ++#define SEC_AO_SEC_JTAG_PWD_SP_ADDR2 (0xff800000 + (0x0b4 << 2)) ++#define P_AO_SEC_JTAG_PWD_SP_ADDR2 (volatile uint32_t *)(0xff800000 + (0x0b4 << 2)) ++#define AO_SEC_JTAG_PWD_SP_ADDR3 (0xff800000 + (0x0b5 << 2)) ++#define SEC_AO_SEC_JTAG_PWD_SP_ADDR3 (0xff800000 + (0x0b5 << 2)) ++#define P_AO_SEC_JTAG_PWD_SP_ADDR3 (volatile uint32_t *)(0xff800000 + (0x0b5 << 2)) ++#define AO_SEC_JTAG_SCP_CTRL (0xff800000 + (0x0b6 << 2)) ++#define SEC_AO_SEC_JTAG_SCP_CTRL (0xff800000 + (0x0b6 << 2)) ++#define P_AO_SEC_JTAG_SCP_CTRL (volatile uint32_t *)(0xff800000 + (0x0b6 << 2)) ++#define AO_SEC_JTAG_PWD_SCP_0 (0xff800000 + (0x0b7 << 2)) ++#define SEC_AO_SEC_JTAG_PWD_SCP_0 (0xff800000 + (0x0b7 << 2)) ++#define P_AO_SEC_JTAG_PWD_SCP_0 (volatile uint32_t *)(0xff800000 + (0x0b7 << 2)) ++#define AO_SEC_JTAG_PWD_SCP_1 (0xff800000 + (0x0b8 << 2)) ++#define SEC_AO_SEC_JTAG_PWD_SCP_1 (0xff800000 + (0x0b8 << 2)) ++#define P_AO_SEC_JTAG_PWD_SCP_1 (volatile uint32_t *)(0xff800000 + (0x0b8 << 2)) ++#define AO_SEC_JTAG_PWD_SCP_2 (0xff800000 + (0x0b9 << 2)) ++#define SEC_AO_SEC_JTAG_PWD_SCP_2 (0xff800000 + (0x0b9 << 2)) ++#define P_AO_SEC_JTAG_PWD_SCP_2 (volatile uint32_t *)(0xff800000 + (0x0b9 << 2)) ++#define AO_SEC_JTAG_PWD_SCP_3 (0xff800000 + (0x0ba << 2)) ++#define SEC_AO_SEC_JTAG_PWD_SCP_3 (0xff800000 + (0x0ba << 2)) ++#define P_AO_SEC_JTAG_PWD_SCP_3 (volatile uint32_t *)(0xff800000 + (0x0ba << 2)) ++#define AO_SEC_JTAG_PWD_SCP_CNTL (0xff800000 + (0x0bb << 2)) ++#define SEC_AO_SEC_JTAG_PWD_SCP_CNTL (0xff800000 + (0x0bb << 2)) ++#define P_AO_SEC_JTAG_PWD_SCP_CNTL (volatile uint32_t *)(0xff800000 + (0x0bb << 2)) ++#define AO_SEC_JTAG_PWD_SCP_ADDR0 (0xff800000 + (0x0bc << 2)) ++#define SEC_AO_SEC_JTAG_PWD_SCP_ADDR0 (0xff800000 + (0x0bc << 2)) ++#define P_AO_SEC_JTAG_PWD_SCP_ADDR0 (volatile uint32_t *)(0xff800000 + (0x0bc << 2)) ++#define AO_SEC_JTAG_PWD_SCP_ADDR1 (0xff800000 + (0x0bd << 2)) ++#define SEC_AO_SEC_JTAG_PWD_SCP_ADDR1 (0xff800000 + (0x0bd << 2)) ++#define P_AO_SEC_JTAG_PWD_SCP_ADDR1 (volatile uint32_t *)(0xff800000 + (0x0bd << 2)) ++#define AO_SEC_JTAG_PWD_SCP_ADDR2 (0xff800000 + (0x0be << 2)) ++#define SEC_AO_SEC_JTAG_PWD_SCP_ADDR2 (0xff800000 + (0x0be << 2)) ++#define P_AO_SEC_JTAG_PWD_SCP_ADDR2 (volatile uint32_t *)(0xff800000 + (0x0be << 2)) ++#define AO_SEC_JTAG_PWD_SCP_ADDR3 (0xff800000 + (0x0bf << 2)) ++#define SEC_AO_SEC_JTAG_PWD_SCP_ADDR3 (0xff800000 + (0x0bf << 2)) ++#define P_AO_SEC_JTAG_PWD_SCP_ADDR3 (volatile uint32_t *)(0xff800000 + (0x0bf << 2)) ++#define M4_CPU_CNTL (0xff800000 + (0x0c0 << 2)) ++#define SEC_M4_CPU_CNTL (0xff800000 + (0x0c0 << 2)) ++#define P_M4_CPU_CNTL (volatile uint32_t *)(0xff800000 + (0x0c0 << 2)) ++#define M4_CPU_CNTL_NS (0xff800000 + (0x0c1 << 2)) ++#define SEC_M4_CPU_CNTL_NS (0xff800000 + (0x0c1 << 2)) ++#define P_M4_CPU_CNTL_NS (volatile uint32_t *)(0xff800000 + (0x0c1 << 2)) ++#define M4_CPU_CNTL2 (0xff800000 + (0x0c2 << 2)) ++#define SEC_M4_CPU_CNTL2 (0xff800000 + (0x0c2 << 2)) ++#define P_M4_CPU_CNTL2 (volatile uint32_t *)(0xff800000 + (0x0c2 << 2)) ++#define M4_CPU_CNTL3 (0xff800000 + (0x0c3 << 2)) ++#define SEC_M4_CPU_CNTL3 (0xff800000 + (0x0c3 << 2)) ++#define P_M4_CPU_CNTL3 (volatile uint32_t *)(0xff800000 + (0x0c3 << 2)) ++#define M4_CPU_CNTL4 (0xff800000 + (0x0c4 << 2)) ++#define SEC_M4_CPU_CNTL4 (0xff800000 + (0x0c4 << 2)) ++#define P_M4_CPU_CNTL4 (volatile uint32_t *)(0xff800000 + (0x0c4 << 2)) ++#define M4_CPU_CNTL5 (0xff800000 + (0x0c5 << 2)) ++#define SEC_M4_CPU_CNTL5 (0xff800000 + (0x0c5 << 2)) ++#define P_M4_CPU_CNTL5 (volatile uint32_t *)(0xff800000 + (0x0c5 << 2)) ++#define M4_CPU_TIMESTAMP (0xff800000 + (0x0c6 << 2)) ++#define SEC_M4_CPU_TIMESTAMP (0xff800000 + (0x0c6 << 2)) ++#define P_M4_CPU_TIMESTAMP (volatile uint32_t *)(0xff800000 + (0x0c6 << 2)) ++#define M4_CPU_TIMESTAMP2 (0xff800000 + (0x0c7 << 2)) ++#define SEC_M4_CPU_TIMESTAMP2 (0xff800000 + (0x0c7 << 2)) ++#define P_M4_CPU_TIMESTAMP2 (volatile uint32_t *)(0xff800000 + (0x0c7 << 2)) ++#define M4_CPU_STAT1 (0xff800000 + (0x0c8 << 2)) ++#define SEC_M4_CPU_STAT1 (0xff800000 + (0x0c8 << 2)) ++#define P_M4_CPU_STAT1 (volatile uint32_t *)(0xff800000 + (0x0c8 << 2)) ++#define M4_CPU_STAT2 (0xff800000 + (0x0c9 << 2)) ++#define SEC_M4_CPU_STAT2 (0xff800000 + (0x0c9 << 2)) ++#define P_M4_CPU_STAT2 (volatile uint32_t *)(0xff800000 + (0x0c9 << 2)) ++#define AO_CEC_STICKY_DATA0 (0xff800000 + (0x0ca << 2)) ++#define SEC_AO_CEC_STICKY_DATA0 (0xff800000 + (0x0ca << 2)) ++#define P_AO_CEC_STICKY_DATA0 (volatile uint32_t *)(0xff800000 + (0x0ca << 2)) ++#define AO_CEC_STICKY_DATA1 (0xff800000 + (0x0cb << 2)) ++#define SEC_AO_CEC_STICKY_DATA1 (0xff800000 + (0x0cb << 2)) ++#define P_AO_CEC_STICKY_DATA1 (volatile uint32_t *)(0xff800000 + (0x0cb << 2)) ++#define AO_CEC_STICKY_DATA2 (0xff800000 + (0x0cc << 2)) ++#define SEC_AO_CEC_STICKY_DATA2 (0xff800000 + (0x0cc << 2)) ++#define P_AO_CEC_STICKY_DATA2 (volatile uint32_t *)(0xff800000 + (0x0cc << 2)) ++#define AO_CEC_STICKY_DATA3 (0xff800000 + (0x0cd << 2)) ++#define SEC_AO_CEC_STICKY_DATA3 (0xff800000 + (0x0cd << 2)) ++#define P_AO_CEC_STICKY_DATA3 (volatile uint32_t *)(0xff800000 + (0x0cd << 2)) ++#define AO_CEC_STICKY_DATA4 (0xff800000 + (0x0ce << 2)) ++#define SEC_AO_CEC_STICKY_DATA4 (0xff800000 + (0x0ce << 2)) ++#define P_AO_CEC_STICKY_DATA4 (volatile uint32_t *)(0xff800000 + (0x0ce << 2)) ++#define AO_CEC_STICKY_DATA5 (0xff800000 + (0x0cf << 2)) ++#define SEC_AO_CEC_STICKY_DATA5 (0xff800000 + (0x0cf << 2)) ++#define P_AO_CEC_STICKY_DATA5 (volatile uint32_t *)(0xff800000 + (0x0cf << 2)) ++#define AO_CEC_STICKY_DATA6 (0xff800000 + (0x0d0 << 2)) ++#define SEC_AO_CEC_STICKY_DATA6 (0xff800000 + (0x0d0 << 2)) ++#define P_AO_CEC_STICKY_DATA6 (volatile uint32_t *)(0xff800000 + (0x0d0 << 2)) ++#define AO_CEC_STICKY_DATA7 (0xff800000 + (0x0d1 << 2)) ++#define SEC_AO_CEC_STICKY_DATA7 (0xff800000 + (0x0d1 << 2)) ++#define P_AO_CEC_STICKY_DATA7 (volatile uint32_t *)(0xff800000 + (0x0d1 << 2)) ++#define AO_SEC_SP_CFG0 (0xff800000 + (0x0e0 << 2)) ++#define SEC_AO_SEC_SP_CFG0 (0xff800000 + (0x0e0 << 2)) ++#define P_AO_SEC_SP_CFG0 (volatile uint32_t *)(0xff800000 + (0x0e0 << 2)) ++#define AO_SEC_SP_CFG1 (0xff800000 + (0x0e1 << 2)) ++#define SEC_AO_SEC_SP_CFG1 (0xff800000 + (0x0e1 << 2)) ++#define P_AO_SEC_SP_CFG1 (volatile uint32_t *)(0xff800000 + (0x0e1 << 2)) ++#define AO_SEC_SP_CFG2 (0xff800000 + (0x0e2 << 2)) ++#define SEC_AO_SEC_SP_CFG2 (0xff800000 + (0x0e2 << 2)) ++#define P_AO_SEC_SP_CFG2 (volatile uint32_t *)(0xff800000 + (0x0e2 << 2)) ++#define AO_SEC_SP_CFG3 (0xff800000 + (0x0e3 << 2)) ++#define SEC_AO_SEC_SP_CFG3 (0xff800000 + (0x0e3 << 2)) ++#define P_AO_SEC_SP_CFG3 (volatile uint32_t *)(0xff800000 + (0x0e3 << 2)) ++#define AO_SEC_SP_CFG4 (0xff800000 + (0x0e4 << 2)) ++#define SEC_AO_SEC_SP_CFG4 (0xff800000 + (0x0e4 << 2)) ++#define P_AO_SEC_SP_CFG4 (volatile uint32_t *)(0xff800000 + (0x0e4 << 2)) ++#define AO_SEC_SP_CFG5 (0xff800000 + (0x0e5 << 2)) ++#define SEC_AO_SEC_SP_CFG5 (0xff800000 + (0x0e5 << 2)) ++#define P_AO_SEC_SP_CFG5 (volatile uint32_t *)(0xff800000 + (0x0e5 << 2)) ++#define AO_SEC_SP_CFG6 (0xff800000 + (0x0e6 << 2)) ++#define SEC_AO_SEC_SP_CFG6 (0xff800000 + (0x0e6 << 2)) ++#define P_AO_SEC_SP_CFG6 (volatile uint32_t *)(0xff800000 + (0x0e6 << 2)) ++#define AO_SEC_SP_CFG7 (0xff800000 + (0x0e7 << 2)) ++#define SEC_AO_SEC_SP_CFG7 (0xff800000 + (0x0e7 << 2)) ++#define P_AO_SEC_SP_CFG7 (volatile uint32_t *)(0xff800000 + (0x0e7 << 2)) ++#define AO_SEC_SP_CFG8 (0xff800000 + (0x0e8 << 2)) ++#define SEC_AO_SEC_SP_CFG8 (0xff800000 + (0x0e8 << 2)) ++#define P_AO_SEC_SP_CFG8 (volatile uint32_t *)(0xff800000 + (0x0e8 << 2)) ++#define AO_SEC_SP_CFG9 (0xff800000 + (0x0e9 << 2)) ++#define SEC_AO_SEC_SP_CFG9 (0xff800000 + (0x0e9 << 2)) ++#define P_AO_SEC_SP_CFG9 (volatile uint32_t *)(0xff800000 + (0x0e9 << 2)) ++#define AO_SEC_SP_CFG10 (0xff800000 + (0x0ea << 2)) ++#define SEC_AO_SEC_SP_CFG10 (0xff800000 + (0x0ea << 2)) ++#define P_AO_SEC_SP_CFG10 (volatile uint32_t *)(0xff800000 + (0x0ea << 2)) ++#define AO_SEC_SP_CFG11 (0xff800000 + (0x0eb << 2)) ++#define SEC_AO_SEC_SP_CFG11 (0xff800000 + (0x0eb << 2)) ++#define P_AO_SEC_SP_CFG11 (volatile uint32_t *)(0xff800000 + (0x0eb << 2)) ++#define AO_SEC_SP_CFG12 (0xff800000 + (0x0ec << 2)) ++#define SEC_AO_SEC_SP_CFG12 (0xff800000 + (0x0ec << 2)) ++#define P_AO_SEC_SP_CFG12 (volatile uint32_t *)(0xff800000 + (0x0ec << 2)) ++#define AO_SEC_SP_CFG13 (0xff800000 + (0x0ed << 2)) ++#define SEC_AO_SEC_SP_CFG13 (0xff800000 + (0x0ed << 2)) ++#define P_AO_SEC_SP_CFG13 (volatile uint32_t *)(0xff800000 + (0x0ed << 2)) ++#define AO_SEC_SP_CFG14 (0xff800000 + (0x0ee << 2)) ++#define SEC_AO_SEC_SP_CFG14 (0xff800000 + (0x0ee << 2)) ++#define P_AO_SEC_SP_CFG14 (volatile uint32_t *)(0xff800000 + (0x0ee << 2)) ++#define AO_SEC_SP_CFG15 (0xff800000 + (0x0ef << 2)) ++#define SEC_AO_SEC_SP_CFG15 (0xff800000 + (0x0ef << 2)) ++#define P_AO_SEC_SP_CFG15 (volatile uint32_t *)(0xff800000 + (0x0ef << 2)) ++#define AO_TIMER_CTRL (0xff800000 + (0x0f0 << 2)) ++#define SEC_AO_TIMER_CTRL (0xff800000 + (0x0f0 << 2)) ++#define P_AO_TIMER_CTRL (volatile uint32_t *)(0xff800000 + (0x0f0 << 2)) ++#define AO_TIMER_SEC_SCP_CTRL (0xff800000 + (0x0f1 << 2)) ++#define SEC_AO_TIMER_SEC_SCP_CTRL (0xff800000 + (0x0f1 << 2)) ++#define P_AO_TIMER_SEC_SCP_CTRL (volatile uint32_t *)(0xff800000 + (0x0f1 << 2)) ++#define AO_TIMER_SEC_SP_CTRL (0xff800000 + (0x0f2 << 2)) ++#define SEC_AO_TIMER_SEC_SP_CTRL (0xff800000 + (0x0f2 << 2)) ++#define P_AO_TIMER_SEC_SP_CTRL (volatile uint32_t *)(0xff800000 + (0x0f2 << 2)) ++#define AO_TIMERA_REG (0xff800000 + (0x0f3 << 2)) ++#define SEC_AO_TIMERA_REG (0xff800000 + (0x0f3 << 2)) ++#define P_AO_TIMERA_REG (volatile uint32_t *)(0xff800000 + (0x0f3 << 2)) ++#define AO_TIMERA_CUR_REG (0xff800000 + (0x0f4 << 2)) ++#define SEC_AO_TIMERA_CUR_REG (0xff800000 + (0x0f4 << 2)) ++#define P_AO_TIMERA_CUR_REG (volatile uint32_t *)(0xff800000 + (0x0f4 << 2)) ++#define AO_TIMERB_REG (0xff800000 + (0x0f5 << 2)) ++#define SEC_AO_TIMERB_REG (0xff800000 + (0x0f5 << 2)) ++#define P_AO_TIMERB_REG (volatile uint32_t *)(0xff800000 + (0x0f5 << 2)) ++#define AO_TIMERB_CUR_REG (0xff800000 + (0x0f6 << 2)) ++#define SEC_AO_TIMERB_CUR_REG (0xff800000 + (0x0f6 << 2)) ++#define P_AO_TIMERB_CUR_REG (volatile uint32_t *)(0xff800000 + (0x0f6 << 2)) ++#define AO_TIMERC_REG (0xff800000 + (0x0f7 << 2)) ++#define SEC_AO_TIMERC_REG (0xff800000 + (0x0f7 << 2)) ++#define P_AO_TIMERC_REG (volatile uint32_t *)(0xff800000 + (0x0f7 << 2)) ++#define AO_TIMERC_CUR_REG (0xff800000 + (0x0f8 << 2)) ++#define SEC_AO_TIMERC_CUR_REG (0xff800000 + (0x0f8 << 2)) ++#define P_AO_TIMERC_CUR_REG (volatile uint32_t *)(0xff800000 + (0x0f8 << 2)) ++#define AO_TIMERE_REG (0xff800000 + (0x0f9 << 2)) ++#define SEC_AO_TIMERE_REG (0xff800000 + (0x0f9 << 2)) ++#define P_AO_TIMERE_REG (volatile uint32_t *)(0xff800000 + (0x0f9 << 2)) ++#define AO_TIMERE_HI_REG (0xff800000 + (0x0fa << 2)) ++#define SEC_AO_TIMERE_HI_REG (0xff800000 + (0x0fa << 2)) ++#define P_AO_TIMERE_HI_REG (volatile uint32_t *)(0xff800000 + (0x0fa << 2)) ++#define AO_TIMERF_REG (0xff800000 + (0x0fb << 2)) ++#define SEC_AO_TIMERF_REG (0xff800000 + (0x0fb << 2)) ++#define P_AO_TIMERF_REG (volatile uint32_t *)(0xff800000 + (0x0fb << 2)) ++#define AO_TIMERF_HI_REG (0xff800000 + (0x0fc << 2)) ++#define SEC_AO_TIMERF_HI_REG (0xff800000 + (0x0fc << 2)) ++#define P_AO_TIMERF_HI_REG (volatile uint32_t *)(0xff800000 + (0x0fc << 2)) ++#define AO_TIMERG_REG (0xff800000 + (0x0fd << 2)) ++#define SEC_AO_TIMERG_REG (0xff800000 + (0x0fd << 2)) ++#define P_AO_TIMERG_REG (volatile uint32_t *)(0xff800000 + (0x0fd << 2)) ++#define AO_TIMERG_HI_REG (0xff800000 + (0x0fe << 2)) ++#define SEC_AO_TIMERG_HI_REG (0xff800000 + (0x0fe << 2)) ++#define P_AO_TIMERG_HI_REG (volatile uint32_t *)(0xff800000 + (0x0fe << 2)) ++// ---------------------------- ++// PWM C-D ++// ---------------------------- ++//#define AO_PWM_CD_REG_BASE 0x02 ++// APB4_DECODER_NON_SECURE_BASE 32'hFF802000 ++// APB4_DECODER_SECURE_BASE 32'hFF802000 ++#define AO_PWM_PWM_C (0xff802000 + (0x000 << 2)) ++#define SEC_AO_PWM_PWM_C (0xff802000 + (0x000 << 2)) ++#define P_AO_PWM_PWM_C (volatile uint32_t *)(0xff802000 + (0x000 << 2)) ++#define AO_PWM_PWM_D (0xff802000 + (0x001 << 2)) ++#define SEC_AO_PWM_PWM_D (0xff802000 + (0x001 << 2)) ++#define P_AO_PWM_PWM_D (volatile uint32_t *)(0xff802000 + (0x001 << 2)) ++#define AO_PWM_MISC_REG_CD (0xff802000 + (0x002 << 2)) ++#define SEC_AO_PWM_MISC_REG_CD (0xff802000 + (0x002 << 2)) ++#define P_AO_PWM_MISC_REG_CD (volatile uint32_t *)(0xff802000 + (0x002 << 2)) ++#define AO_PWM_DELTA_SIGMA_CD (0xff802000 + (0x003 << 2)) ++#define SEC_AO_PWM_DELTA_SIGMA_CD (0xff802000 + (0x003 << 2)) ++#define P_AO_PWM_DELTA_SIGMA_CD (volatile uint32_t *)(0xff802000 + (0x003 << 2)) ++#define AO_PWM_TIME_CD (0xff802000 + (0x004 << 2)) ++#define SEC_AO_PWM_TIME_CD (0xff802000 + (0x004 << 2)) ++#define P_AO_PWM_TIME_CD (volatile uint32_t *)(0xff802000 + (0x004 << 2)) ++#define AO_PWM_C2 (0xff802000 + (0x005 << 2)) ++#define SEC_AO_PWM_C2 (0xff802000 + (0x005 << 2)) ++#define P_AO_PWM_C2 (volatile uint32_t *)(0xff802000 + (0x005 << 2)) ++#define AO_PWM_D2 (0xff802000 + (0x006 << 2)) ++#define SEC_AO_PWM_D2 (0xff802000 + (0x006 << 2)) ++#define P_AO_PWM_D2 (volatile uint32_t *)(0xff802000 + (0x006 << 2)) ++#define AO_PWM_BLINK_CD (0xff802000 + (0x007 << 2)) ++#define SEC_AO_PWM_BLINK_CD (0xff802000 + (0x007 << 2)) ++#define P_AO_PWM_BLINK_CD (volatile uint32_t *)(0xff802000 + (0x007 << 2)) ++#define AO_PWM_LOCK_CD (0xff802000 + (0x008 << 2)) ++#define SEC_AO_PWM_LOCK_CD (0xff802000 + (0x008 << 2)) ++#define P_AO_PWM_LOCK_CD (volatile uint32_t *)(0xff802000 + (0x008 << 2)) ++// ---------------------------- ++// UART ++// ---------------------------- ++//#define AO_UART_REG_BASE 0x03 ++// APB4_DECODER_NON_SECURE_BASE 32'hFF803000 ++// APB4_DECODER_SECURE_BASE 32'hFF803000 ++#define AO_UART_WFIFO (0xff803000 + (0x000 << 2)) ++#define SEC_AO_UART_WFIFO (0xff803000 + (0x000 << 2)) ++#define P_AO_UART_WFIFO (volatile uint32_t *)(0xff803000 + (0x000 << 2)) ++#define AO_UART_RFIFO (0xff803000 + (0x001 << 2)) ++#define SEC_AO_UART_RFIFO (0xff803000 + (0x001 << 2)) ++#define P_AO_UART_RFIFO (volatile uint32_t *)(0xff803000 + (0x001 << 2)) ++#define AO_UART_CONTROL (0xff803000 + (0x002 << 2)) ++#define SEC_AO_UART_CONTROL (0xff803000 + (0x002 << 2)) ++#define P_AO_UART_CONTROL (volatile uint32_t *)(0xff803000 + (0x002 << 2)) ++#define AO_UART_STATUS (0xff803000 + (0x003 << 2)) ++#define SEC_AO_UART_STATUS (0xff803000 + (0x003 << 2)) ++#define P_AO_UART_STATUS (volatile uint32_t *)(0xff803000 + (0x003 << 2)) ++#define AO_UART_MISC (0xff803000 + (0x004 << 2)) ++#define SEC_AO_UART_MISC (0xff803000 + (0x004 << 2)) ++#define P_AO_UART_MISC (volatile uint32_t *)(0xff803000 + (0x004 << 2)) ++#define AO_UART_REG5 (0xff803000 + (0x005 << 2)) ++#define SEC_AO_UART_REG5 (0xff803000 + (0x005 << 2)) ++#define P_AO_UART_REG5 (volatile uint32_t *)(0xff803000 + (0x005 << 2)) ++// ---------------------------- ++// UART2 ++// ---------------------------- ++//#define AO_UART2_REG_BASE 0x04 ++// APB4_DECODER_NON_SECURE_BASE 32'hFF804000 ++// APB4_DECODER_SECURE_BASE 32'hFF804000 ++#define AO_UART2_WFIFO (0xff804000 + (0x000 << 2)) ++#define SEC_AO_UART2_WFIFO (0xff804000 + (0x000 << 2)) ++#define P_AO_UART2_WFIFO (volatile uint32_t *)(0xff804000 + (0x000 << 2)) ++#define AO_UART2_RFIFO (0xff804000 + (0x001 << 2)) ++#define SEC_AO_UART2_RFIFO (0xff804000 + (0x001 << 2)) ++#define P_AO_UART2_RFIFO (volatile uint32_t *)(0xff804000 + (0x001 << 2)) ++#define AO_UART2_CONTROL (0xff804000 + (0x002 << 2)) ++#define SEC_AO_UART2_CONTROL (0xff804000 + (0x002 << 2)) ++#define P_AO_UART2_CONTROL (volatile uint32_t *)(0xff804000 + (0x002 << 2)) ++#define AO_UART2_STATUS (0xff804000 + (0x003 << 2)) ++#define SEC_AO_UART2_STATUS (0xff804000 + (0x003 << 2)) ++#define P_AO_UART2_STATUS (volatile uint32_t *)(0xff804000 + (0x003 << 2)) ++#define AO_UART2_MISC (0xff804000 + (0x004 << 2)) ++#define SEC_AO_UART2_MISC (0xff804000 + (0x004 << 2)) ++#define P_AO_UART2_MISC (volatile uint32_t *)(0xff804000 + (0x004 << 2)) ++#define AO_UART2_REG5 (0xff804000 + (0x005 << 2)) ++#define SEC_AO_UART2_REG5 (0xff804000 + (0x005 << 2)) ++#define P_AO_UART2_REG5 (volatile uint32_t *)(0xff804000 + (0x005 << 2)) ++// ---------------------------- ++// I2C Master (8) ++// ---------------------------- ++//#define AO_I2C_M_REG_BASE 0x05 ++// APB4_DECODER_NON_SECURE_BASE 32'hFF805000 ++// APB4_DECODER_SECURE_BASE 32'hFF805000 ++#define AO_I2C_M_0_CONTROL_REG (0xff805000 + (0x000 << 2)) ++#define SEC_AO_I2C_M_0_CONTROL_REG (0xff805000 + (0x000 << 2)) ++#define P_AO_I2C_M_0_CONTROL_REG (volatile uint32_t *)(0xff805000 + (0x000 << 2)) ++#define AO_I2C_M_0_SLAVE_ADDR (0xff805000 + (0x001 << 2)) ++#define SEC_AO_I2C_M_0_SLAVE_ADDR (0xff805000 + (0x001 << 2)) ++#define P_AO_I2C_M_0_SLAVE_ADDR (volatile uint32_t *)(0xff805000 + (0x001 << 2)) ++#define AO_I2C_M_0_TOKEN_LIST0 (0xff805000 + (0x002 << 2)) ++#define SEC_AO_I2C_M_0_TOKEN_LIST0 (0xff805000 + (0x002 << 2)) ++#define P_AO_I2C_M_0_TOKEN_LIST0 (volatile uint32_t *)(0xff805000 + (0x002 << 2)) ++#define AO_I2C_M_0_TOKEN_LIST1 (0xff805000 + (0x003 << 2)) ++#define SEC_AO_I2C_M_0_TOKEN_LIST1 (0xff805000 + (0x003 << 2)) ++#define P_AO_I2C_M_0_TOKEN_LIST1 (volatile uint32_t *)(0xff805000 + (0x003 << 2)) ++#define AO_I2C_M_0_WDATA_REG0 (0xff805000 + (0x004 << 2)) ++#define SEC_AO_I2C_M_0_WDATA_REG0 (0xff805000 + (0x004 << 2)) ++#define P_AO_I2C_M_0_WDATA_REG0 (volatile uint32_t *)(0xff805000 + (0x004 << 2)) ++#define AO_I2C_M_0_WDATA_REG1 (0xff805000 + (0x005 << 2)) ++#define SEC_AO_I2C_M_0_WDATA_REG1 (0xff805000 + (0x005 << 2)) ++#define P_AO_I2C_M_0_WDATA_REG1 (volatile uint32_t *)(0xff805000 + (0x005 << 2)) ++#define AO_I2C_M_0_RDATA_REG0 (0xff805000 + (0x006 << 2)) ++#define SEC_AO_I2C_M_0_RDATA_REG0 (0xff805000 + (0x006 << 2)) ++#define P_AO_I2C_M_0_RDATA_REG0 (volatile uint32_t *)(0xff805000 + (0x006 << 2)) ++#define AO_I2C_M_0_RDATA_REG1 (0xff805000 + (0x007 << 2)) ++#define SEC_AO_I2C_M_0_RDATA_REG1 (0xff805000 + (0x007 << 2)) ++#define P_AO_I2C_M_0_RDATA_REG1 (volatile uint32_t *)(0xff805000 + (0x007 << 2)) ++#define AO_I2C_M_0_TIMEOUT_TH (0xff805000 + (0x008 << 2)) ++#define SEC_AO_I2C_M_0_TIMEOUT_TH (0xff805000 + (0x008 << 2)) ++#define P_AO_I2C_M_0_TIMEOUT_TH (volatile uint32_t *)(0xff805000 + (0x008 << 2)) ++// ---------------------------- ++// I2C Slave (3) ++// ---------------------------- ++//#define AO_I2C_S_REG_BASE 0x06 ++// APB4_DECODER_NON_SECURE_BASE 32'hFF806000 ++// APB4_DECODER_SECURE_BASE 32'hFF806000 ++#define AO_I2C_S_CONTROL_REG (0xff806000 + (0x000 << 2)) ++#define SEC_AO_I2C_S_CONTROL_REG (0xff806000 + (0x000 << 2)) ++#define P_AO_I2C_S_CONTROL_REG (volatile uint32_t *)(0xff806000 + (0x000 << 2)) ++#define AO_I2C_S_SEND_REG (0xff806000 + (0x001 << 2)) ++#define SEC_AO_I2C_S_SEND_REG (0xff806000 + (0x001 << 2)) ++#define P_AO_I2C_S_SEND_REG (volatile uint32_t *)(0xff806000 + (0x001 << 2)) ++#define AO_I2C_S_RECV_REG (0xff806000 + (0x002 << 2)) ++#define SEC_AO_I2C_S_RECV_REG (0xff806000 + (0x002 << 2)) ++#define P_AO_I2C_S_RECV_REG (volatile uint32_t *)(0xff806000 + (0x002 << 2)) ++#define AO_I2C_S_CNTL1_REG (0xff806000 + (0x003 << 2)) ++#define SEC_AO_I2C_S_CNTL1_REG (0xff806000 + (0x003 << 2)) ++#define P_AO_I2C_S_CNTL1_REG (volatile uint32_t *)(0xff806000 + (0x003 << 2)) ++// ---------------------------- ++// PWM A-B ++// ---------------------------- ++//#define AO_PWM_AB_REG_BASE 0x07 ++// APB4_DECODER_NON_SECURE_BASE 32'hFF807000 ++// APB4_DECODER_SECURE_BASE 32'hFF807000 ++#define AO_PWM_PWM_A (0xff807000 + (0x000 << 2)) ++#define SEC_AO_PWM_PWM_A (0xff807000 + (0x000 << 2)) ++#define P_AO_PWM_PWM_A (volatile uint32_t *)(0xff807000 + (0x000 << 2)) ++#define AO_PWM_PWM_B (0xff807000 + (0x001 << 2)) ++#define SEC_AO_PWM_PWM_B (0xff807000 + (0x001 << 2)) ++#define P_AO_PWM_PWM_B (volatile uint32_t *)(0xff807000 + (0x001 << 2)) ++#define AO_PWM_MISC_REG_AB (0xff807000 + (0x002 << 2)) ++#define SEC_AO_PWM_MISC_REG_AB (0xff807000 + (0x002 << 2)) ++#define P_AO_PWM_MISC_REG_AB (volatile uint32_t *)(0xff807000 + (0x002 << 2)) ++#define AO_PWM_DELTA_SIGMA_AB (0xff807000 + (0x003 << 2)) ++#define SEC_AO_PWM_DELTA_SIGMA_AB (0xff807000 + (0x003 << 2)) ++#define P_AO_PWM_DELTA_SIGMA_AB (volatile uint32_t *)(0xff807000 + (0x003 << 2)) ++#define AO_PWM_TIME_AB (0xff807000 + (0x004 << 2)) ++#define SEC_AO_PWM_TIME_AB (0xff807000 + (0x004 << 2)) ++#define P_AO_PWM_TIME_AB (volatile uint32_t *)(0xff807000 + (0x004 << 2)) ++#define AO_PWM_A2 (0xff807000 + (0x005 << 2)) ++#define SEC_AO_PWM_A2 (0xff807000 + (0x005 << 2)) ++#define P_AO_PWM_A2 (volatile uint32_t *)(0xff807000 + (0x005 << 2)) ++#define AO_PWM_B2 (0xff807000 + (0x006 << 2)) ++#define SEC_AO_PWM_B2 (0xff807000 + (0x006 << 2)) ++#define P_AO_PWM_B2 (volatile uint32_t *)(0xff807000 + (0x006 << 2)) ++#define AO_PWM_BLINK_AB (0xff807000 + (0x007 << 2)) ++#define SEC_AO_PWM_BLINK_AB (0xff807000 + (0x007 << 2)) ++#define P_AO_PWM_BLINK_AB (volatile uint32_t *)(0xff807000 + (0x007 << 2)) ++#define AO_PWM_LOCK_AB (0xff807000 + (0x008 << 2)) ++#define SEC_AO_PWM_LOCK_AB (0xff807000 + (0x008 << 2)) ++#define P_AO_PWM_LOCK_AB (volatile uint32_t *)(0xff807000 + (0x008 << 2)) ++// ---------------------------- ++// Multiformat IR Remote ++// ---------------------------- ++//#define AO_MF_IR_DEC_REG_BASE 0x08 ++// APB4_DECODER_NON_SECURE_BASE 32'hFF808000 ++// APB4_DECODER_SECURE_BASE 32'hFF808000 ++#define AO_IR_DEC_LDR_ACTIVE (0xff808000 + (0x000 << 2)) ++#define SEC_AO_IR_DEC_LDR_ACTIVE (0xff808000 + (0x000 << 2)) ++#define P_AO_IR_DEC_LDR_ACTIVE (volatile uint32_t *)(0xff808000 + (0x000 << 2)) ++#define AO_IR_DEC_LDR_IDLE (0xff808000 + (0x001 << 2)) ++#define SEC_AO_IR_DEC_LDR_IDLE (0xff808000 + (0x001 << 2)) ++#define P_AO_IR_DEC_LDR_IDLE (volatile uint32_t *)(0xff808000 + (0x001 << 2)) ++#define AO_IR_DEC_LDR_REPEAT (0xff808000 + (0x002 << 2)) ++#define SEC_AO_IR_DEC_LDR_REPEAT (0xff808000 + (0x002 << 2)) ++#define P_AO_IR_DEC_LDR_REPEAT (volatile uint32_t *)(0xff808000 + (0x002 << 2)) ++#define AO_IR_DEC_BIT_0 (0xff808000 + (0x003 << 2)) ++#define SEC_AO_IR_DEC_BIT_0 (0xff808000 + (0x003 << 2)) ++#define P_AO_IR_DEC_BIT_0 (volatile uint32_t *)(0xff808000 + (0x003 << 2)) ++#define AO_IR_DEC_REG0 (0xff808000 + (0x004 << 2)) ++#define SEC_AO_IR_DEC_REG0 (0xff808000 + (0x004 << 2)) ++#define P_AO_IR_DEC_REG0 (volatile uint32_t *)(0xff808000 + (0x004 << 2)) ++#define AO_IR_DEC_FRAME (0xff808000 + (0x005 << 2)) ++#define SEC_AO_IR_DEC_FRAME (0xff808000 + (0x005 << 2)) ++#define P_AO_IR_DEC_FRAME (volatile uint32_t *)(0xff808000 + (0x005 << 2)) ++#define AO_IR_DEC_STATUS (0xff808000 + (0x006 << 2)) ++#define SEC_AO_IR_DEC_STATUS (0xff808000 + (0x006 << 2)) ++#define P_AO_IR_DEC_STATUS (volatile uint32_t *)(0xff808000 + (0x006 << 2)) ++#define AO_IR_DEC_REG1 (0xff808000 + (0x007 << 2)) ++#define SEC_AO_IR_DEC_REG1 (0xff808000 + (0x007 << 2)) ++#define P_AO_IR_DEC_REG1 (volatile uint32_t *)(0xff808000 + (0x007 << 2)) ++#define AO_MF_IR_DEC_LDR_ACTIVE (0xff808000 + (0x010 << 2)) ++#define SEC_AO_MF_IR_DEC_LDR_ACTIVE (0xff808000 + (0x010 << 2)) ++#define P_AO_MF_IR_DEC_LDR_ACTIVE (volatile uint32_t *)(0xff808000 + (0x010 << 2)) ++#define AO_MF_IR_DEC_LDR_IDLE (0xff808000 + (0x011 << 2)) ++#define SEC_AO_MF_IR_DEC_LDR_IDLE (0xff808000 + (0x011 << 2)) ++#define P_AO_MF_IR_DEC_LDR_IDLE (volatile uint32_t *)(0xff808000 + (0x011 << 2)) ++#define AO_MF_IR_DEC_LDR_REPEAT (0xff808000 + (0x012 << 2)) ++#define SEC_AO_MF_IR_DEC_LDR_REPEAT (0xff808000 + (0x012 << 2)) ++#define P_AO_MF_IR_DEC_LDR_REPEAT (volatile uint32_t *)(0xff808000 + (0x012 << 2)) ++#define AO_MF_IR_DEC_BIT_0 (0xff808000 + (0x013 << 2)) ++#define SEC_AO_MF_IR_DEC_BIT_0 (0xff808000 + (0x013 << 2)) ++#define P_AO_MF_IR_DEC_BIT_0 (volatile uint32_t *)(0xff808000 + (0x013 << 2)) ++#define AO_MF_IR_DEC_REG0 (0xff808000 + (0x014 << 2)) ++#define SEC_AO_MF_IR_DEC_REG0 (0xff808000 + (0x014 << 2)) ++#define P_AO_MF_IR_DEC_REG0 (volatile uint32_t *)(0xff808000 + (0x014 << 2)) ++#define AO_MF_IR_DEC_FRAME (0xff808000 + (0x015 << 2)) ++#define SEC_AO_MF_IR_DEC_FRAME (0xff808000 + (0x015 << 2)) ++#define P_AO_MF_IR_DEC_FRAME (volatile uint32_t *)(0xff808000 + (0x015 << 2)) ++#define AO_MF_IR_DEC_STATUS (0xff808000 + (0x016 << 2)) ++#define SEC_AO_MF_IR_DEC_STATUS (0xff808000 + (0x016 << 2)) ++#define P_AO_MF_IR_DEC_STATUS (volatile uint32_t *)(0xff808000 + (0x016 << 2)) ++#define AO_MF_IR_DEC_REG1 (0xff808000 + (0x017 << 2)) ++#define SEC_AO_MF_IR_DEC_REG1 (0xff808000 + (0x017 << 2)) ++#define P_AO_MF_IR_DEC_REG1 (volatile uint32_t *)(0xff808000 + (0x017 << 2)) ++#define AO_MF_IR_DEC_REG2 (0xff808000 + (0x018 << 2)) ++#define SEC_AO_MF_IR_DEC_REG2 (0xff808000 + (0x018 << 2)) ++#define P_AO_MF_IR_DEC_REG2 (volatile uint32_t *)(0xff808000 + (0x018 << 2)) ++#define AO_MF_IR_DEC_DURATN2 (0xff808000 + (0x019 << 2)) ++#define SEC_AO_MF_IR_DEC_DURATN2 (0xff808000 + (0x019 << 2)) ++#define P_AO_MF_IR_DEC_DURATN2 (volatile uint32_t *)(0xff808000 + (0x019 << 2)) ++#define AO_MF_IR_DEC_DURATN3 (0xff808000 + (0x01a << 2)) ++#define SEC_AO_MF_IR_DEC_DURATN3 (0xff808000 + (0x01a << 2)) ++#define P_AO_MF_IR_DEC_DURATN3 (volatile uint32_t *)(0xff808000 + (0x01a << 2)) ++#define AO_MF_IR_DEC_FRAME1 (0xff808000 + (0x01b << 2)) ++#define SEC_AO_MF_IR_DEC_FRAME1 (0xff808000 + (0x01b << 2)) ++#define P_AO_MF_IR_DEC_FRAME1 (volatile uint32_t *)(0xff808000 + (0x01b << 2)) ++#define AO_MF_IR_DEC_STATUS1 (0xff808000 + (0x01c << 2)) ++#define SEC_AO_MF_IR_DEC_STATUS1 (0xff808000 + (0x01c << 2)) ++#define P_AO_MF_IR_DEC_STATUS1 (volatile uint32_t *)(0xff808000 + (0x01c << 2)) ++#define AO_MF_IR_DEC_STATUS2 (0xff808000 + (0x01d << 2)) ++#define SEC_AO_MF_IR_DEC_STATUS2 (0xff808000 + (0x01d << 2)) ++#define P_AO_MF_IR_DEC_STATUS2 (volatile uint32_t *)(0xff808000 + (0x01d << 2)) ++#define AO_MF_IR_DEC_REG3 (0xff808000 + (0x01e << 2)) ++#define SEC_AO_MF_IR_DEC_REG3 (0xff808000 + (0x01e << 2)) ++#define P_AO_MF_IR_DEC_REG3 (volatile uint32_t *)(0xff808000 + (0x01e << 2)) ++#define AO_MF_IR_DEC_FRAME_RSV0 (0xff808000 + (0x01f << 2)) ++#define SEC_AO_MF_IR_DEC_FRAME_RSV0 (0xff808000 + (0x01f << 2)) ++#define P_AO_MF_IR_DEC_FRAME_RSV0 (volatile uint32_t *)(0xff808000 + (0x01f << 2)) ++#define AO_MF_IR_DEC_FRAME_RSV1 (0xff808000 + (0x020 << 2)) ++#define SEC_AO_MF_IR_DEC_FRAME_RSV1 (0xff808000 + (0x020 << 2)) ++#define P_AO_MF_IR_DEC_FRAME_RSV1 (volatile uint32_t *)(0xff808000 + (0x020 << 2)) ++#define AO_MF_IR_DEC_FILTE (0xff808000 + (0x021 << 2)) ++#define SEC_AO_MF_IR_DEC_FILTE (0xff808000 + (0x021 << 2)) ++#define P_AO_MF_IR_DEC_FILTE (volatile uint32_t *)(0xff808000 + (0x021 << 2)) ++#define AO_MF_IR_DEC_IRQ_CTL (0xff808000 + (0x022 << 2)) ++#define SEC_AO_MF_IR_DEC_IRQ_CTL (0xff808000 + (0x022 << 2)) ++#define P_AO_MF_IR_DEC_IRQ_CTL (volatile uint32_t *)(0xff808000 + (0x022 << 2)) ++#define AO_MF_IR_DEC_FIFO_CTL (0xff808000 + (0x023 << 2)) ++#define SEC_AO_MF_IR_DEC_FIFO_CTL (0xff808000 + (0x023 << 2)) ++#define P_AO_MF_IR_DEC_FIFO_CTL (volatile uint32_t *)(0xff808000 + (0x023 << 2)) ++#define AO_MF_IR_DEC_WIDTH_NEW (0xff808000 + (0x024 << 2)) ++#define SEC_AO_MF_IR_DEC_WIDTH_NEW (0xff808000 + (0x024 << 2)) ++#define P_AO_MF_IR_DEC_WIDTH_NEW (volatile uint32_t *)(0xff808000 + (0x024 << 2)) ++#define AO_MF_IR_DEC_REPEAT_DET (0xff808000 + (0x025 << 2)) ++#define SEC_AO_MF_IR_DEC_REPEAT_DET (0xff808000 + (0x025 << 2)) ++#define P_AO_MF_IR_DEC_REPEAT_DET (volatile uint32_t *)(0xff808000 + (0x025 << 2)) ++#define AO_IR_DEC_DEMOD_CNTL0 (0xff808000 + (0x030 << 2)) ++#define SEC_AO_IR_DEC_DEMOD_CNTL0 (0xff808000 + (0x030 << 2)) ++#define P_AO_IR_DEC_DEMOD_CNTL0 (volatile uint32_t *)(0xff808000 + (0x030 << 2)) ++#define AO_IR_DEC_DEMOD_CNTL1 (0xff808000 + (0x031 << 2)) ++#define SEC_AO_IR_DEC_DEMOD_CNTL1 (0xff808000 + (0x031 << 2)) ++#define P_AO_IR_DEC_DEMOD_CNTL1 (volatile uint32_t *)(0xff808000 + (0x031 << 2)) ++#define AO_IR_DEC_DEMOD_IIR_THD (0xff808000 + (0x032 << 2)) ++#define SEC_AO_IR_DEC_DEMOD_IIR_THD (0xff808000 + (0x032 << 2)) ++#define P_AO_IR_DEC_DEMOD_IIR_THD (volatile uint32_t *)(0xff808000 + (0x032 << 2)) ++#define AO_IR_DEC_DEMOD_THD0 (0xff808000 + (0x033 << 2)) ++#define SEC_AO_IR_DEC_DEMOD_THD0 (0xff808000 + (0x033 << 2)) ++#define P_AO_IR_DEC_DEMOD_THD0 (volatile uint32_t *)(0xff808000 + (0x033 << 2)) ++#define AO_IR_DEC_DEMOD_THD1 (0xff808000 + (0x034 << 2)) ++#define SEC_AO_IR_DEC_DEMOD_THD1 (0xff808000 + (0x034 << 2)) ++#define P_AO_IR_DEC_DEMOD_THD1 (volatile uint32_t *)(0xff808000 + (0x034 << 2)) ++#define AO_IR_DEC_DEMOD_SUM_CNT0 (0xff808000 + (0x035 << 2)) ++#define SEC_AO_IR_DEC_DEMOD_SUM_CNT0 (0xff808000 + (0x035 << 2)) ++#define P_AO_IR_DEC_DEMOD_SUM_CNT0 (volatile uint32_t *)(0xff808000 + (0x035 << 2)) ++#define AO_IR_DEC_DEMOD_SUM_CNT1 (0xff808000 + (0x036 << 2)) ++#define SEC_AO_IR_DEC_DEMOD_SUM_CNT1 (0xff808000 + (0x036 << 2)) ++#define P_AO_IR_DEC_DEMOD_SUM_CNT1 (volatile uint32_t *)(0xff808000 + (0x036 << 2)) ++#define AO_IR_DEC_DEMOD_CNT0 (0xff808000 + (0x037 << 2)) ++#define SEC_AO_IR_DEC_DEMOD_CNT0 (0xff808000 + (0x037 << 2)) ++#define P_AO_IR_DEC_DEMOD_CNT0 (volatile uint32_t *)(0xff808000 + (0x037 << 2)) ++#define AO_IR_DEC_DEMOD_CNT1 (0xff808000 + (0x038 << 2)) ++#define SEC_AO_IR_DEC_DEMOD_CNT1 (0xff808000 + (0x038 << 2)) ++#define P_AO_IR_DEC_DEMOD_CNT1 (volatile uint32_t *)(0xff808000 + (0x038 << 2)) ++// --------------------------- ++// SAR ADC ++// --------------------------- ++//#define AO_SAR_ADC_REG_BASE 0x09 ++// APB4_DECODER_NON_SECURE_BASE 32'hFF809000 ++// APB4_DECODER_SECURE_BASE 32'hFF809000 ++#define AO_SAR_ADC_REG0 (0xff809000 + (0x000 << 2)) ++#define SEC_AO_SAR_ADC_REG0 (0xff809000 + (0x000 << 2)) ++#define P_AO_SAR_ADC_REG0 (volatile uint32_t *)(0xff809000 + (0x000 << 2)) ++#define AO_SAR_ADC_CHAN_LIST (0xff809000 + (0x001 << 2)) ++#define SEC_AO_SAR_ADC_CHAN_LIST (0xff809000 + (0x001 << 2)) ++#define P_AO_SAR_ADC_CHAN_LIST (volatile uint32_t *)(0xff809000 + (0x001 << 2)) ++#define AO_SAR_ADC_AVG_CNTL (0xff809000 + (0x002 << 2)) ++#define SEC_AO_SAR_ADC_AVG_CNTL (0xff809000 + (0x002 << 2)) ++#define P_AO_SAR_ADC_AVG_CNTL (volatile uint32_t *)(0xff809000 + (0x002 << 2)) ++#define AO_SAR_ADC_REG3 (0xff809000 + (0x003 << 2)) ++#define SEC_AO_SAR_ADC_REG3 (0xff809000 + (0x003 << 2)) ++#define P_AO_SAR_ADC_REG3 (volatile uint32_t *)(0xff809000 + (0x003 << 2)) ++#define AO_SAR_ADC_DELAY (0xff809000 + (0x004 << 2)) ++#define SEC_AO_SAR_ADC_DELAY (0xff809000 + (0x004 << 2)) ++#define P_AO_SAR_ADC_DELAY (volatile uint32_t *)(0xff809000 + (0x004 << 2)) ++#define AO_SAR_ADC_LAST_RD (0xff809000 + (0x005 << 2)) ++#define SEC_AO_SAR_ADC_LAST_RD (0xff809000 + (0x005 << 2)) ++#define P_AO_SAR_ADC_LAST_RD (volatile uint32_t *)(0xff809000 + (0x005 << 2)) ++#define AO_SAR_ADC_FIFO_RD (0xff809000 + (0x006 << 2)) ++#define SEC_AO_SAR_ADC_FIFO_RD (0xff809000 + (0x006 << 2)) ++#define P_AO_SAR_ADC_FIFO_RD (volatile uint32_t *)(0xff809000 + (0x006 << 2)) ++#define AO_SAR_ADC_AUX_SW (0xff809000 + (0x007 << 2)) ++#define SEC_AO_SAR_ADC_AUX_SW (0xff809000 + (0x007 << 2)) ++#define P_AO_SAR_ADC_AUX_SW (volatile uint32_t *)(0xff809000 + (0x007 << 2)) ++#define AO_SAR_ADC_CHAN_10_SW (0xff809000 + (0x008 << 2)) ++#define SEC_AO_SAR_ADC_CHAN_10_SW (0xff809000 + (0x008 << 2)) ++#define P_AO_SAR_ADC_CHAN_10_SW (volatile uint32_t *)(0xff809000 + (0x008 << 2)) ++#define AO_SAR_ADC_DETECT_IDLE_SW (0xff809000 + (0x009 << 2)) ++#define SEC_AO_SAR_ADC_DETECT_IDLE_SW (0xff809000 + (0x009 << 2)) ++#define P_AO_SAR_ADC_DETECT_IDLE_SW (volatile uint32_t *)(0xff809000 + (0x009 << 2)) ++#define AO_SAR_ADC_DELTA_10 (0xff809000 + (0x00a << 2)) ++#define SEC_AO_SAR_ADC_DELTA_10 (0xff809000 + (0x00a << 2)) ++#define P_AO_SAR_ADC_DELTA_10 (volatile uint32_t *)(0xff809000 + (0x00a << 2)) ++#define AO_SAR_ADC_REG11 (0xff809000 + (0x00b << 2)) ++#define SEC_AO_SAR_ADC_REG11 (0xff809000 + (0x00b << 2)) ++#define P_AO_SAR_ADC_REG11 (volatile uint32_t *)(0xff809000 + (0x00b << 2)) ++#define AO_SAR_ADC_REG12 (0xff809000 + (0x00c << 2)) ++#define SEC_AO_SAR_ADC_REG12 (0xff809000 + (0x00c << 2)) ++#define P_AO_SAR_ADC_REG12 (volatile uint32_t *)(0xff809000 + (0x00c << 2)) ++#define AO_SAR_ADC_REG13 (0xff809000 + (0x00d << 2)) ++#define SEC_AO_SAR_ADC_REG13 (0xff809000 + (0x00d << 2)) ++#define P_AO_SAR_ADC_REG13 (volatile uint32_t *)(0xff809000 + (0x00d << 2)) ++#define AO_SAR_ADC_CHNL01 (0xff809000 + (0x00e << 2)) ++#define SEC_AO_SAR_ADC_CHNL01 (0xff809000 + (0x00e << 2)) ++#define P_AO_SAR_ADC_CHNL01 (volatile uint32_t *)(0xff809000 + (0x00e << 2)) ++#define AO_SAR_ADC_CHNL23 (0xff809000 + (0x00f << 2)) ++#define SEC_AO_SAR_ADC_CHNL23 (0xff809000 + (0x00f << 2)) ++#define P_AO_SAR_ADC_CHNL23 (volatile uint32_t *)(0xff809000 + (0x00f << 2)) ++#define AO_SAR_ADC_CHNL45 (0xff809000 + (0x010 << 2)) ++#define SEC_AO_SAR_ADC_CHNL45 (0xff809000 + (0x010 << 2)) ++#define P_AO_SAR_ADC_CHNL45 (volatile uint32_t *)(0xff809000 + (0x010 << 2)) ++#define AO_SAR_ADC_CHNL67 (0xff809000 + (0x011 << 2)) ++#define SEC_AO_SAR_ADC_CHNL67 (0xff809000 + (0x011 << 2)) ++#define P_AO_SAR_ADC_CHNL67 (volatile uint32_t *)(0xff809000 + (0x011 << 2)) ++// --------------------------- ++// MAIL BOX (M3/M4) ++// --------------------------- ++//#define AO_MAILBOX_REG_BASE 0x0a ++// APB4_DECODER_NON_SECURE_BASE 32'hFF80a000 ++// APB4_DECODER_SECURE_BASE 32'hFF80a000 ++#define AO_MAILBOX_SET_0 (0xff80a000 + (0x001 << 2)) ++#define SEC_AO_MAILBOX_SET_0 (0xff80a000 + (0x001 << 2)) ++#define P_AO_MAILBOX_SET_0 (volatile uint32_t *)(0xff80a000 + (0x001 << 2)) ++#define AO_MAILBOX_STAT_0 (0xff80a000 + (0x002 << 2)) ++#define SEC_AO_MAILBOX_STAT_0 (0xff80a000 + (0x002 << 2)) ++#define P_AO_MAILBOX_STAT_0 (volatile uint32_t *)(0xff80a000 + (0x002 << 2)) ++#define AO_MAILBOX_CLR_0 (0xff80a000 + (0x003 << 2)) ++#define SEC_AO_MAILBOX_CLR_0 (0xff80a000 + (0x003 << 2)) ++#define P_AO_MAILBOX_CLR_0 (volatile uint32_t *)(0xff80a000 + (0x003 << 2)) ++#define AO_MAILBOX_SET_1 (0xff80a000 + (0x004 << 2)) ++#define SEC_AO_MAILBOX_SET_1 (0xff80a000 + (0x004 << 2)) ++#define P_AO_MAILBOX_SET_1 (volatile uint32_t *)(0xff80a000 + (0x004 << 2)) ++#define AO_MAILBOX_STAT_1 (0xff80a000 + (0x005 << 2)) ++#define SEC_AO_MAILBOX_STAT_1 (0xff80a000 + (0x005 << 2)) ++#define P_AO_MAILBOX_STAT_1 (volatile uint32_t *)(0xff80a000 + (0x005 << 2)) ++#define AO_MAILBOX_CLR_1 (0xff80a000 + (0x006 << 2)) ++#define SEC_AO_MAILBOX_CLR_1 (0xff80a000 + (0x006 << 2)) ++#define P_AO_MAILBOX_CLR_1 (volatile uint32_t *)(0xff80a000 + (0x006 << 2)) ++#define AO_MAILBOX_SET_2 (0xff80a000 + (0x007 << 2)) ++#define SEC_AO_MAILBOX_SET_2 (0xff80a000 + (0x007 << 2)) ++#define P_AO_MAILBOX_SET_2 (volatile uint32_t *)(0xff80a000 + (0x007 << 2)) ++#define AO_MAILBOX_STAT_2 (0xff80a000 + (0x008 << 2)) ++#define SEC_AO_MAILBOX_STAT_2 (0xff80a000 + (0x008 << 2)) ++#define P_AO_MAILBOX_STAT_2 (volatile uint32_t *)(0xff80a000 + (0x008 << 2)) ++#define AO_MAILBOX_CLR_2 (0xff80a000 + (0x009 << 2)) ++#define SEC_AO_MAILBOX_CLR_2 (0xff80a000 + (0x009 << 2)) ++#define P_AO_MAILBOX_CLR_2 (volatile uint32_t *)(0xff80a000 + (0x009 << 2)) ++#define AO_MAILBOX_SET_3 (0xff80a000 + (0x00a << 2)) ++#define SEC_AO_MAILBOX_SET_3 (0xff80a000 + (0x00a << 2)) ++#define P_AO_MAILBOX_SET_3 (volatile uint32_t *)(0xff80a000 + (0x00a << 2)) ++#define AO_MAILBOX_STAT_3 (0xff80a000 + (0x00b << 2)) ++#define SEC_AO_MAILBOX_STAT_3 (0xff80a000 + (0x00b << 2)) ++#define P_AO_MAILBOX_STAT_3 (volatile uint32_t *)(0xff80a000 + (0x00b << 2)) ++#define AO_MAILBOX_CLR_3 (0xff80a000 + (0x00c << 2)) ++#define SEC_AO_MAILBOX_CLR_3 (0xff80a000 + (0x00c << 2)) ++#define P_AO_MAILBOX_CLR_3 (volatile uint32_t *)(0xff80a000 + (0x00c << 2)) ++// --------------------------- ++// RTC (4) ++// --------------------------- ++// Moved to the secure APB3 bus ++// `define AO_RTC_ADDR0 8'hd0 ++// `define AO_RTC_ADDR1 8'hd1 ++// `define AO_RTC_ADDR2 8'hd2 ++// `define AO_RTC_ADDR3 8'hd3 ++// `define AO_RTC_ADDR4 8'hd4 ++// ++// Closing file: ./ao_rti_reg.h ++// ++ ++#define P_DMA_T0 (volatile uint32_t *)0xff63e000 ++#define P_DMA_T1 (volatile uint32_t *)0xff63e004 ++#define P_DMA_T2 (volatile uint32_t *)0xff63e008 ++#define P_DMA_T3 (volatile uint32_t *)0xff63e00c ++#define P_DMA_T4 (volatile uint32_t *)0xff63e010 ++#define P_DMA_T5 (volatile uint32_t *)0xff63e014 ++#define P_DMA_STS0 (volatile uint32_t *)0xff63e020 ++#define P_DMA_STS1 (volatile uint32_t *)0xff63e024 ++#define P_DMA_STS2 (volatile uint32_t *)0xff63e028 ++#define P_DMA_STS3 (volatile uint32_t *)0xff63e02c ++#define P_DMA_STS4 (volatile uint32_t *)0xff63e030 ++#define P_DMA_STS5 (volatile uint32_t *)0xff63e034 ++#define P_DMA_CFG (volatile uint32_t *)0xff63e040 ++#define P_DMA_SEC (volatile uint32_t *)0xff63e044 ++ ++#endif // SECURE_APB_H ++ ++ +diff --git a/include/amlogic/auge_sound.h b/include/amlogic/auge_sound.h +new file mode 100644 +index 00000000000..2defa8018ab +--- /dev/null ++++ b/include/amlogic/auge_sound.h +@@ -0,0 +1,24 @@ ++/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ ++/* ++ * include/amlogic/auge_sound.h ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the named License, ++ * or any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++ ++#ifndef __AUGE_SOUND_H__ ++#define __AUGE_SOUND_H__ ++ ++/* auge audio register is defined in asm/arch/secure_apb.h */ ++ ++int aml_audio_init(void); ++ ++#endif +diff --git a/include/amlogic/blxx2bl33_param.h b/include/amlogic/blxx2bl33_param.h +new file mode 100644 +index 00000000000..b2a5304e148 +--- /dev/null ++++ b/include/amlogic/blxx2bl33_param.h +@@ -0,0 +1,27 @@ ++#ifndef __BLXX2BL33_PARAM_H__ ++#define __BLXX2BL33_PARAM_H__ ++#include ++ ++/* !!! don't try to modify the Micro unless make a consistency with blxx */ ++ ++#define BL2E2BL33_PARAM_START (0x0e00000) ++#define BL2E2BL33_PARAM_END (0x1000000) ++ ++#define BLXX2BL33_PARAM_DEBUG (0) ++ ++/* define the parameter type here and make sure the same with blxx */ ++enum { ++ STORAGE_PARAM_TPYE = 1, ++ BL2PARMA_PARAM_TYPE = 2, ++ /* other */ ++}; ++ ++struct param_e { ++ unsigned int type; ++ unsigned int len; /* must be 8 bytes align */ ++ unsigned char data[1]; /* user defined parameter */ ++}; ++ ++struct param_e *param_of(int type); ++ ++#endif +\ No newline at end of file +diff --git a/include/amlogic/canvas.h b/include/amlogic/canvas.h +new file mode 100644 +index 00000000000..dc9ed10f022 +--- /dev/null ++++ b/include/amlogic/canvas.h +@@ -0,0 +1,68 @@ ++/* ++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++*/ ++ ++#ifndef CANVAS_H ++#define CANVAS_H ++ ++#define CANVAS_ADDR_LMASK 0x1fffffff ++#define CANVAS_WIDTH_LMASK 0x7 ++#define CANVAS_WIDTH_LWID 3 ++#define CANVAS_WIDTH_LBIT 29 ++ ++#define CANVAS_WIDTH_HMASK 0x1ff ++#define CANVAS_WIDTH_HBIT 0 ++#define CANVAS_HEIGHT_MASK 0x1fff ++#define CANVAS_HEIGHT_BIT 9 ++#define CANVAS_YWRAP (1<<23) ++#define CANVAS_XWRAP (1<<22) ++#define CANVAS_ADDR_NOWRAP 0x00 ++#define CANVAS_ADDR_WRAPX 0x01 ++#define CANVAS_ADDR_WRAPY 0x02 ++#define CANVAS_BLKMODE_MASK 3 ++#define CANVAS_BLKMODE_BIT 24 ++#define CANVAS_BLKMODE_LINEAR 0x00 ++#define CANVAS_BLKMODE_32X32 0x01 ++#define CANVAS_BLKMODE_64X32 0x02 ++ ++#define CANVAS_LUT_INDEX_BIT 0 ++#define CANVAS_LUT_INDEX_MASK 0x7 ++#define CANVAS_LUT_WR_EN (0x2 << 8) ++#define CANVAS_LUT_RD_EN (0x1 << 8) ++ ++typedef struct { ++ ulong addr; ++ u32 width; ++ u32 height; ++ u32 wrap; ++ u32 blkmode; ++} canvas_t; ++ ++#define OSD1_CANVAS_INDEX 0x40 ++#define OSD2_CANVAS_INDEX 0x43 ++ ++extern void canvas_init(void); ++ ++extern void canvas_config(u32 index, ulong addr, u32 width, ++ u32 height, u32 wrap, u32 blkmode); ++ ++extern void canvas_read(u32 index, canvas_t *p); ++ ++extern void canvas_copy(unsigned src, unsigned dst); ++ ++extern void canvas_update_addr(u32 index, u32 addr); ++ ++extern unsigned int canvas_get_addr(u32 index); ++ ++#endif /* CANVAS_H */ +diff --git a/include/amlogic/color.h b/include/amlogic/color.h +new file mode 100644 +index 00000000000..9839d119997 +--- /dev/null ++++ b/include/amlogic/color.h +@@ -0,0 +1,51 @@ ++/* ++ * include/linux/amlogic/vout/color.h ++ * ++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++*/ ++ ++ ++#ifndef _COLOR_H_ ++#define _COLOR_H_ ++ ++enum color_index_e { ++ COLOR_INDEX_NULL = 0, ++ COLOR_INDEX_02_PAL4 = 2, ++ COLOR_INDEX_04_PAL16 = 4, ++ COLOR_INDEX_08_PAL256 = 8, ++ COLOR_INDEX_16_655 = 9, ++ COLOR_INDEX_16_844 = 10, ++ COLOR_INDEX_16_6442 = 11 , ++ COLOR_INDEX_16_4444_R = 12, ++ COLOR_INDEX_16_4642_R = 13, ++ COLOR_INDEX_16_1555_A = 14, ++ COLOR_INDEX_16_4444_A = 15, ++ COLOR_INDEX_16_565 = 16, ++ ++ COLOR_INDEX_24_6666_A = 19, ++ COLOR_INDEX_24_6666_R = 20, ++ COLOR_INDEX_24_8565 = 21, ++ COLOR_INDEX_24_5658 = 22, ++ COLOR_INDEX_24_888_B = 23, ++ COLOR_INDEX_24_RGB = 24, ++ ++ COLOR_INDEX_32_BGRA = 29, ++ COLOR_INDEX_32_ABGR = 30, ++ COLOR_INDEX_32_RGBA = 31, ++ COLOR_INDEX_32_ARGB = 32, ++ ++ COLOR_INDEX_YUV_422 = 33, ++}; ++ ++#endif +diff --git a/include/amlogic/cpu_id.h b/include/amlogic/cpu_id.h +new file mode 100644 +index 00000000000..588c131262d +--- /dev/null ++++ b/include/amlogic/cpu_id.h +@@ -0,0 +1,90 @@ ++/* ++ * include/amlogic/cpu_id.h ++ * ++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++*/ ++ ++#define MESON_CPU_MAJOR_ID_M6 0x16 ++#define MESON_CPU_MAJOR_ID_M6TV 0x17 ++#define MESON_CPU_MAJOR_ID_M6TVL 0x18 ++#define MESON_CPU_MAJOR_ID_M8 0x19 ++#define MESON_CPU_MAJOR_ID_MTVD 0x1A ++#define MESON_CPU_MAJOR_ID_M8B 0x1B ++#define MESON_CPU_MAJOR_ID_MG9TV 0x1C ++#define MESON_CPU_MAJOR_ID_M8M2 0x1D ++#define MESON_CPU_MAJOR_ID_GXBB 0x1F ++#define MESON_CPU_MAJOR_ID_GXTVBB 0x20 ++#define MESON_CPU_MAJOR_ID_GXL 0x21 ++#define MESON_CPU_MAJOR_ID_GXM 0x22 ++#define MESON_CPU_MAJOR_ID_TXL 0x23 ++#define MESON_CPU_MAJOR_ID_TXLX 0x24 ++#define MESON_CPU_MAJOR_ID_AXG 0x25 ++#define MESON_CPU_MAJOR_ID_GXLX 0x26 ++#define MESON_CPU_MAJOR_ID_TXHD 0x27 ++#define MESON_CPU_MAJOR_ID_G12A 0x28 ++#define MESON_CPU_MAJOR_ID_G12B 0x29 ++#define MESON_CPU_MAJOR_ID_SM1 0x2B ++#define MESON_CPU_MAJOR_ID_A1 0x2C ++#define MESON_CPU_MAJOR_ID_TL1 0x2E ++#define MESON_CPU_MAJOR_ID_TM2 0x2F ++#define MESON_CPU_MAJOR_ID_C1 0x30 ++#define MESON_CPU_MAJOR_ID_SC2 0x32 ++#define MESON_CPU_MAJOR_ID_C2 0x33 ++ ++ ++#define MESON_CPU_PACKAGE_ID_905D 0X00 ++#define MESON_CPU_PACKAGE_ID_905M 0x20 ++#define MESON_CPU_PACKAGE_ID_905X 0X80 ++#define MESON_CPU_PACKAGE_ID_905L 0XC0 ++#define MESON_CPU_PACKAGE_ID_905M2 0XE0 ++ ++#define MESON_CPU_PACKAGE_ID_T962X 0x10 ++#define MESON_CPU_PACKAGE_ID_T962E 0x20 ++ ++#define MESON_CPU_PACKAGE_ID_A113X 0x37 ++#define MESON_CPU_PACKAGE_ID_A113D 0xD0 ++ ++#define MESON_CPU_CHIP_REVISION_A 0xA ++#define MESON_CPU_CHIP_REVISION_B 0xB ++#define MESON_CPU_CHIP_REVISION_C 0xC ++#define MESON_CPU_CHIP_REVISION_D 0xD ++ ++typedef struct cpu_id { ++ unsigned int family_id:8; ++ unsigned int package_id:8; ++ unsigned int chip_rev:8; //RevA/RevB etc. ++ unsigned int reserve:4; ++ unsigned int layout_ver:4; ++} cpu_id_t; ++ ++typedef struct chip_id { ++ unsigned int version; ++ unsigned char chipid[16]; ++} chip_id_t; ++ ++cpu_id_t get_cpu_id(void); ++ ++extern chip_id_t aml_chip_id; ++int get_chip_id(unsigned char *buff, unsigned int size); ++ ++/** ++ * TODO: Remove this API after move static system information to RO ++ * register or SRAM ++ * ++ * Should *NOT* call this API directly, always use get_chip_id() ++ */ ++int __get_chip_id(unsigned char *buff, unsigned int size); +diff --git a/include/amlogic/enc_clk_config.h b/include/amlogic/enc_clk_config.h +new file mode 100644 +index 00000000000..8b137891791 +--- /dev/null ++++ b/include/amlogic/enc_clk_config.h +@@ -0,0 +1 @@ ++ +diff --git a/include/amlogic/fb.h b/include/amlogic/fb.h +new file mode 100644 +index 00000000000..d19e96928e5 +--- /dev/null ++++ b/include/amlogic/fb.h +@@ -0,0 +1,399 @@ ++#ifndef _LINUX_FB_H ++#define _LINUX_FB_H ++ ++/* Definitions of frame buffers */ ++ ++#define FB_MAX 32 /* sufficient for now */ ++ ++/* ioctls ++ 0x46 is 'F' */ ++#define FBIOGET_VSCREENINFO 0x4600 ++#define FBIOPUT_VSCREENINFO 0x4601 ++#define FBIOGET_FSCREENINFO 0x4602 ++#define FBIOGETCMAP 0x4604 ++#define FBIOPUTCMAP 0x4605 ++#define FBIOPAN_DISPLAY 0x4606 ++#ifdef __KERNEL__ ++#define FBIO_CURSOR _IOWR('F', 0x08, struct fb_cursor_user) ++#else ++#define FBIO_CURSOR _IOWR('F', 0x08, struct fb_cursor) ++#endif ++/* 0x4607-0x460B are defined below */ ++/* #define FBIOGET_MONITORSPEC 0x460C */ ++/* #define FBIOPUT_MONITORSPEC 0x460D */ ++/* #define FBIOSWITCH_MONIBIT 0x460E */ ++#define FBIOGET_CON2FBMAP 0x460F ++#define FBIOPUT_CON2FBMAP 0x4610 ++#define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */ ++#define FBIOGET_VBLANK _IOR('F', 0x12, struct fb_vblank) ++#define FBIO_ALLOC 0x4613 ++#define FBIO_FREE 0x4614 ++#define FBIOGET_GLYPH 0x4615 ++#define FBIOGET_HWCINFO 0x4616 ++#define FBIOPUT_MODEINFO 0x4617 ++#define FBIOGET_DISPINFO 0x4618 ++ ++ ++#define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */ ++#define FB_TYPE_PLANES 1 /* Non interleaved planes */ ++#define FB_TYPE_INTERLEAVED_PLANES 2 /* Interleaved planes */ ++#define FB_TYPE_TEXT 3 /* Text/attributes */ ++#define FB_TYPE_VGA_PLANES 4 /* EGA/VGA planes */ ++ ++#define FB_AUX_TEXT_MDA 0 /* Monochrome text */ ++#define FB_AUX_TEXT_CGA 1 /* CGA/EGA/VGA Color text */ ++#define FB_AUX_TEXT_S3_MMIO 2 /* S3 MMIO fasttext */ ++#define FB_AUX_TEXT_MGA_STEP16 3 /* MGA Millenium I: text, attr, 14 reserved bytes */ ++#define FB_AUX_TEXT_MGA_STEP8 4 /* other MGAs: text, attr, 6 reserved bytes */ ++#define FB_AUX_TEXT_SVGA_GROUP 8 /* 8-15: SVGA tileblit compatible modes */ ++#define FB_AUX_TEXT_SVGA_MASK 7 /* lower three bits says step */ ++#define FB_AUX_TEXT_SVGA_STEP2 8 /* SVGA text mode: text, attr */ ++#define FB_AUX_TEXT_SVGA_STEP4 9 /* SVGA text mode: text, attr, 2 reserved bytes */ ++#define FB_AUX_TEXT_SVGA_STEP8 10 /* SVGA text mode: text, attr, 6 reserved bytes */ ++#define FB_AUX_TEXT_SVGA_STEP16 11 /* SVGA text mode: text, attr, 14 reserved bytes */ ++#define FB_AUX_TEXT_SVGA_LAST 15 /* reserved up to 15 */ ++ ++#define FB_AUX_VGA_PLANES_VGA4 0 /* 16 color planes (EGA/VGA) */ ++#define FB_AUX_VGA_PLANES_CFB4 1 /* CFB4 in planes (VGA) */ ++#define FB_AUX_VGA_PLANES_CFB8 2 /* CFB8 in planes (VGA) */ ++ ++#define FB_VISUAL_MONO01 0 /* Monochr. 1=Black 0=White */ ++#define FB_VISUAL_MONO10 1 /* Monochr. 1=White 0=Black */ ++#define FB_VISUAL_TRUECOLOR 2 /* True color */ ++#define FB_VISUAL_PSEUDOCOLOR 3 /* Pseudo color (like atari) */ ++#define FB_VISUAL_DIRECTCOLOR 4 /* Direct color */ ++#define FB_VISUAL_STATIC_PSEUDOCOLOR 5 /* Pseudo color readonly */ ++ ++#define FB_ACCEL_NONE 0 /* no hardware accelerator */ ++#define FB_ACCEL_ATARIBLITT 1 /* Atari Blitter */ ++#define FB_ACCEL_AMIGABLITT 2 /* Amiga Blitter */ ++#define FB_ACCEL_S3_TRIO64 3 /* Cybervision64 (S3 Trio64) */ ++#define FB_ACCEL_NCR_77C32BLT 4 /* RetinaZ3 (NCR 77C32BLT) */ ++#define FB_ACCEL_S3_VIRGE 5 /* Cybervision64/3D (S3 ViRGE) */ ++#define FB_ACCEL_ATI_MACH64GX 6 /* ATI Mach 64GX family */ ++#define FB_ACCEL_DEC_TGA 7 /* DEC 21030 TGA */ ++#define FB_ACCEL_ATI_MACH64CT 8 /* ATI Mach 64CT family */ ++#define FB_ACCEL_ATI_MACH64VT 9 /* ATI Mach 64CT family VT class */ ++#define FB_ACCEL_ATI_MACH64GT 10 /* ATI Mach 64CT family GT class */ ++#define FB_ACCEL_SUN_CREATOR 11 /* Sun Creator/Creator3D */ ++#define FB_ACCEL_SUN_CGSIX 12 /* Sun cg6 */ ++#define FB_ACCEL_SUN_LEO 13 /* Sun leo/zx */ ++#define FB_ACCEL_IMS_TWINTURBO 14 /* IMS Twin Turbo */ ++#define FB_ACCEL_3DLABS_PERMEDIA2 15 /* 3Dlabs Permedia 2 */ ++#define FB_ACCEL_MATROX_MGA2064W 16 /* Matrox MGA2064W (Millenium) */ ++#define FB_ACCEL_MATROX_MGA1064SG 17 /* Matrox MGA1064SG (Mystique) */ ++#define FB_ACCEL_MATROX_MGA2164W 18 /* Matrox MGA2164W (Millenium II) */ ++#define FB_ACCEL_MATROX_MGA2164W_AGP 19 /* Matrox MGA2164W (Millenium II) */ ++#define FB_ACCEL_MATROX_MGAG100 20 /* Matrox G100 (Productiva G100) */ ++#define FB_ACCEL_MATROX_MGAG200 21 /* Matrox G200 (Myst, Mill, ...) */ ++#define FB_ACCEL_SUN_CG14 22 /* Sun cgfourteen */ ++#define FB_ACCEL_SUN_BWTWO 23 /* Sun bwtwo */ ++#define FB_ACCEL_SUN_CGTHREE 24 /* Sun cgthree */ ++#define FB_ACCEL_SUN_TCX 25 /* Sun tcx */ ++#define FB_ACCEL_MATROX_MGAG400 26 /* Matrox G400 */ ++#define FB_ACCEL_NV3 27 /* nVidia RIVA 128 */ ++#define FB_ACCEL_NV4 28 /* nVidia RIVA TNT */ ++#define FB_ACCEL_NV5 29 /* nVidia RIVA TNT2 */ ++#define FB_ACCEL_CT_6555x 30 /* C&T 6555x */ ++#define FB_ACCEL_3DFX_BANSHEE 31 /* 3Dfx Banshee */ ++#define FB_ACCEL_ATI_RAGE128 32 /* ATI Rage128 family */ ++#define FB_ACCEL_IGS_CYBER2000 33 /* CyberPro 2000 */ ++#define FB_ACCEL_IGS_CYBER2010 34 /* CyberPro 2010 */ ++#define FB_ACCEL_IGS_CYBER5000 35 /* CyberPro 5000 */ ++#define FB_ACCEL_SIS_GLAMOUR 36 /* SiS 300/630/540 */ ++#define FB_ACCEL_3DLABS_PERMEDIA3 37 /* 3Dlabs Permedia 3 */ ++#define FB_ACCEL_ATI_RADEON 38 /* ATI Radeon family */ ++#define FB_ACCEL_I810 39 /* Intel 810/815 */ ++#define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 650, 740 */ ++#define FB_ACCEL_SIS_XABRE 41 /* SiS 330 ("Xabre") */ ++#define FB_ACCEL_I830 42 /* Intel 830M/845G/85x/865G */ ++#define FB_ACCEL_NV_10 43 /* nVidia Arch 10 */ ++#define FB_ACCEL_NV_20 44 /* nVidia Arch 20 */ ++#define FB_ACCEL_NV_30 45 /* nVidia Arch 30 */ ++#define FB_ACCEL_NV_40 46 /* nVidia Arch 40 */ ++#define FB_ACCEL_XGI_VOLARI_V 47 /* XGI Volari V3XT, V5, V8 */ ++#define FB_ACCEL_XGI_VOLARI_Z 48 /* XGI Volari Z7 */ ++#define FB_ACCEL_OMAP1610 49 /* TI OMAP16xx */ ++#define FB_ACCEL_TRIDENT_TGUI 50 /* Trident TGUI */ ++#define FB_ACCEL_TRIDENT_3DIMAGE 51 /* Trident 3DImage */ ++#define FB_ACCEL_TRIDENT_BLADE3D 52 /* Trident Blade3D */ ++#define FB_ACCEL_TRIDENT_BLADEXP 53 /* Trident BladeXP */ ++#define FB_ACCEL_CIRRUS_ALPINE 53 /* Cirrus Logic 543x/544x/5480 */ ++#define FB_ACCEL_NEOMAGIC_NM2070 90 /* NeoMagic NM2070 */ ++#define FB_ACCEL_NEOMAGIC_NM2090 91 /* NeoMagic NM2090 */ ++#define FB_ACCEL_NEOMAGIC_NM2093 92 /* NeoMagic NM2093 */ ++#define FB_ACCEL_NEOMAGIC_NM2097 93 /* NeoMagic NM2097 */ ++#define FB_ACCEL_NEOMAGIC_NM2160 94 /* NeoMagic NM2160 */ ++#define FB_ACCEL_NEOMAGIC_NM2200 95 /* NeoMagic NM2200 */ ++#define FB_ACCEL_NEOMAGIC_NM2230 96 /* NeoMagic NM2230 */ ++#define FB_ACCEL_NEOMAGIC_NM2360 97 /* NeoMagic NM2360 */ ++#define FB_ACCEL_NEOMAGIC_NM2380 98 /* NeoMagic NM2380 */ ++#define FB_ACCEL_PXA3XX 99 /* PXA3xx */ ++ ++#define FB_ACCEL_SAVAGE4 0x80 /* S3 Savage4 */ ++#define FB_ACCEL_SAVAGE3D 0x81 /* S3 Savage3D */ ++#define FB_ACCEL_SAVAGE3D_MV 0x82 /* S3 Savage3D-MV */ ++#define FB_ACCEL_SAVAGE2000 0x83 /* S3 Savage2000 */ ++#define FB_ACCEL_SAVAGE_MX_MV 0x84 /* S3 Savage/MX-MV */ ++#define FB_ACCEL_SAVAGE_MX 0x85 /* S3 Savage/MX */ ++#define FB_ACCEL_SAVAGE_IX_MV 0x86 /* S3 Savage/IX-MV */ ++#define FB_ACCEL_SAVAGE_IX 0x87 /* S3 Savage/IX */ ++#define FB_ACCEL_PROSAVAGE_PM 0x88 /* S3 ProSavage PM133 */ ++#define FB_ACCEL_PROSAVAGE_KM 0x89 /* S3 ProSavage KM133 */ ++#define FB_ACCEL_S3TWISTER_P 0x8a /* S3 Twister */ ++#define FB_ACCEL_S3TWISTER_K 0x8b /* S3 TwisterK */ ++#define FB_ACCEL_SUPERSAVAGE 0x8c /* S3 Supersavage */ ++#define FB_ACCEL_PROSAVAGE_DDR 0x8d /* S3 ProSavage DDR */ ++#define FB_ACCEL_PROSAVAGE_DDRK 0x8e /* S3 ProSavage DDR-K */ ++ ++struct fb_fix_screeninfo { ++ char id[16]; /* identification string eg "TT Builtin" */ ++ unsigned long smem_start; /* Start of frame buffer mem */ ++ /* (physical address) */ ++ __u32 smem_len; /* Length of frame buffer mem */ ++ __u32 type; /* see FB_TYPE_* */ ++ __u32 type_aux; /* Interleave for interleaved Planes */ ++ __u32 visual; /* see FB_VISUAL_* */ ++ __u16 xpanstep; /* zero if no hardware panning */ ++ __u16 ypanstep; /* zero if no hardware panning */ ++ __u16 ywrapstep; /* zero if no hardware ywrap */ ++ __u32 line_length; /* length of a line in bytes */ ++ unsigned long mmio_start; /* Start of Memory Mapped I/O */ ++ /* (physical address) */ ++ __u32 mmio_len; /* Length of Memory Mapped I/O */ ++ __u32 accel; /* Indicate to driver which */ ++ /* specific chip/card we have */ ++ __u16 reserved[3]; /* Reserved for future compatibility */ ++}; ++ ++/* Interpretation of offset for color fields: All offsets are from the right, ++ * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you ++ * can use the offset as right argument to <<). A pixel afterwards is a bit ++ * stream and is written to video memory as that unmodified. ++ * ++ * For pseudocolor: offset and length should be the same for all color ++ * components. Offset specifies the position of the least significant bit ++ * of the pallette index in a pixel value. Length indicates the number ++ * of available palette entries (i.e. # of entries = 1 << length). ++ */ ++struct fb_bitfield { ++ __u32 offset; /* beginning of bitfield */ ++ __u32 length; /* length of bitfield */ ++ __u32 msb_right; /* != 0 : Most significant bit is */ ++ /* right */ ++}; ++ ++#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */ ++#define FB_NONSTD_REV_PIX_IN_B 2 /* order of pixels in each byte is reversed */ ++ ++#define FB_ACTIVATE_NOW 0 /* set values immediately (or vbl)*/ ++#define FB_ACTIVATE_NXTOPEN 1 /* activate on next open */ ++#define FB_ACTIVATE_TEST 2 /* don't set, round up impossible */ ++#define FB_ACTIVATE_MASK 15 ++ /* values */ ++#define FB_ACTIVATE_VBL 16 /* activate values on next vbl */ ++#define FB_CHANGE_CMAP_VBL 32 /* change colormap on vbl */ ++#define FB_ACTIVATE_ALL 64 /* change all VCs on this fb */ ++#define FB_ACTIVATE_FORCE 128 /* force apply even when no change*/ ++#define FB_ACTIVATE_INV_MODE 256 /* invalidate videomode */ ++ ++#define FB_ACCELF_TEXT 1 /* (OBSOLETE) see fb_info.flags and vc_mode */ ++ ++#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */ ++#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ ++#define FB_SYNC_EXT 4 /* external sync */ ++#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ ++#define FB_SYNC_BROADCAST 16 /* broadcast video timings */ ++ /* vtotal = 144d/288n/576i => PAL */ ++ /* vtotal = 121d/242n/484i => NTSC */ ++#define FB_SYNC_ON_GREEN 32 /* sync on green */ ++ ++#define FB_VMODE_NONINTERLACED 0 /* non interlaced */ ++#define FB_VMODE_INTERLACED 1 /* interlaced */ ++#define FB_VMODE_DOUBLE 2 /* double scan */ ++#define FB_VMODE_ODD_FLD_FIRST 4 /* interlaced: top line first */ ++#define FB_VMODE_MASK 255 ++ ++#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */ ++#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ ++#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */ ++ ++/* ++ * Display rotation support ++ */ ++#define FB_ROTATE_UR 0 ++#define FB_ROTATE_CW 1 ++#define FB_ROTATE_UD 2 ++#define FB_ROTATE_CCW 3 ++ ++#define PICOS2KHZ(a) (1000000000UL/(a)) ++#define KHZ2PICOS(a) (1000000000UL/(a)) ++ ++struct fb_var_screeninfo { ++ __u32 xres; /* visible resolution */ ++ __u32 yres; ++ __u32 xres_virtual; /* virtual resolution */ ++ __u32 yres_virtual; ++ __u32 xoffset; /* offset from virtual to visible */ ++ __u32 yoffset; /* resolution */ ++ ++ __u32 bits_per_pixel; /* guess what */ ++ __u32 grayscale; /* != 0 Graylevels instead of colors */ ++ ++ struct fb_bitfield red; /* bitfield in fb mem if true color, */ ++ struct fb_bitfield green; /* else only length is significant */ ++ struct fb_bitfield blue; ++ struct fb_bitfield transp; /* transparency */ ++ ++ __u32 nonstd; /* != 0 Non standard pixel format */ ++ ++ __u32 activate; /* see FB_ACTIVATE_* */ ++ ++ __u32 height; /* height of picture in mm */ ++ __u32 width; /* width of picture in mm */ ++ ++ __u32 accel_flags; /* (OBSOLETE) see fb_info.flags */ ++ ++ /* Timing: All values in pixclocks, except pixclock (of course) */ ++ __u32 pixclock; /* pixel clock in ps (pico seconds) */ ++ __u32 left_margin; /* time from sync to picture */ ++ __u32 right_margin; /* time from picture to sync */ ++ __u32 upper_margin; /* time from sync to picture */ ++ __u32 lower_margin; ++ __u32 hsync_len; /* length of horizontal sync */ ++ __u32 vsync_len; /* length of vertical sync */ ++ __u32 sync; /* see FB_SYNC_* */ ++ __u32 vmode; /* see FB_VMODE_* */ ++ __u32 rotate; /* angle we rotate counter clockwise */ ++ __u32 reserved[5]; /* Reserved for future compatibility */ ++}; ++ ++struct fb_cmap { ++ __u32 start; /* First entry */ ++ __u32 len; /* Number of entries */ ++ __u16 *red; /* Red values */ ++ __u16 *green; ++ __u16 *blue; ++ __u16 *transp; /* transparency, can be NULL */ ++}; ++ ++struct fb_con2fbmap { ++ __u32 console; ++ __u32 framebuffer; ++}; ++ ++/* VESA Blanking Levels */ ++#define VESA_NO_BLANKING 0 ++#define VESA_VSYNC_SUSPEND 1 ++#define VESA_HSYNC_SUSPEND 2 ++#define VESA_POWERDOWN 3 ++ ++#define CANVAS_ALIGNED(x) (((x) + 63) & ~63) ++ ++enum osd_index_e { ++ OSD1 = 0, ++ OSD2, ++ VIU2_OSD1 ++}; ++ ++enum { ++ /* screen: unblanked, hsync: on, vsync: on */ ++ FB_BLANK_UNBLANK = VESA_NO_BLANKING, ++ ++ /* screen: blanked, hsync: on, vsync: on */ ++ FB_BLANK_NORMAL = VESA_NO_BLANKING + 1, ++ ++ /* screen: blanked, hsync: on, vsync: off */ ++ FB_BLANK_VSYNC_SUSPEND = VESA_VSYNC_SUSPEND + 1, ++ ++ /* screen: blanked, hsync: off, vsync: on */ ++ FB_BLANK_HSYNC_SUSPEND = VESA_HSYNC_SUSPEND + 1, ++ ++ /* screen: blanked, hsync: off, vsync: off */ ++ FB_BLANK_POWERDOWN = VESA_POWERDOWN + 1 ++}; ++ ++#define FB_VBLANK_VBLANKING 0x001 /* currently in a vertical blank */ ++#define FB_VBLANK_HBLANKING 0x002 /* currently in a horizontal blank */ ++#define FB_VBLANK_HAVE_VBLANK 0x004 /* vertical blanks can be detected */ ++#define FB_VBLANK_HAVE_HBLANK 0x008 /* horizontal blanks can be detected */ ++#define FB_VBLANK_HAVE_COUNT 0x010 /* global retrace counter is available */ ++#define FB_VBLANK_HAVE_VCOUNT 0x020 /* the vcount field is valid */ ++#define FB_VBLANK_HAVE_HCOUNT 0x040 /* the hcount field is valid */ ++#define FB_VBLANK_VSYNCING 0x080 /* currently in a vsync */ ++#define FB_VBLANK_HAVE_VSYNC 0x100 /* verical syncs can be detected */ ++ ++struct fb_vblank { ++ __u32 flags; /* FB_VBLANK flags */ ++ __u32 count; /* counter of retraces since boot */ ++ __u32 vcount; /* current scanline position */ ++ __u32 hcount; /* current scandot position */ ++ __u32 reserved[4]; /* reserved for future compatibility */ ++}; ++ ++/* Internal HW accel */ ++#define ROP_COPY 0 ++#define ROP_XOR 1 ++ ++struct fb_copyarea { ++ __u32 dx; ++ __u32 dy; ++ __u32 width; ++ __u32 height; ++ __u32 sx; ++ __u32 sy; ++}; ++ ++struct fb_fillrect { ++ __u32 dx; /* screen-relative */ ++ __u32 dy; ++ __u32 width; ++ __u32 height; ++ __u32 color; ++ __u32 rop; ++}; ++ ++struct fb_image { ++ __u32 dx; /* Where to place image */ ++ __u32 dy; ++ __u32 width; /* Size of image */ ++ __u32 height; ++ __u32 fg_color; /* Only used when a mono bitmap */ ++ __u32 bg_color; ++ __u8 depth; /* Depth of the image */ ++ const char *data; /* Pointer to image data */ ++ struct fb_cmap cmap; /* color map info */ ++}; ++ ++/* ++ * hardware cursor control ++ */ ++ ++#define FB_CUR_SETIMAGE 0x01 ++#define FB_CUR_SETPOS 0x02 ++#define FB_CUR_SETHOT 0x04 ++#define FB_CUR_SETCMAP 0x08 ++#define FB_CUR_SETSHAPE 0x10 ++#define FB_CUR_SETSIZE 0x20 ++#define FB_CUR_SETALL 0xFF ++ ++struct fbcurpos { ++ __u16 x, y; ++}; ++ ++struct fb_cursor { ++ __u16 set; /* what to set */ ++ __u16 enable; /* cursor on/off */ ++ __u16 rop; /* bitop operation */ ++ const char *mask; /* cursor mask bits */ ++ struct fbcurpos hot; /* cursor hot spot */ ++ struct fb_image image; /* Cursor image */ ++}; ++ ++#ifdef CONFIG_FB_BACKLIGHT ++/* Settings for the generic backlight code */ ++#define FB_BACKLIGHT_LEVELS 128 ++#define FB_BACKLIGHT_MAX 0xFF ++#endif ++ ++#endif /* _LINUX_FB_H */ +diff --git a/include/amlogic/instaboot.h b/include/amlogic/instaboot.h +new file mode 100644 +index 00000000000..cfcae9ef4a9 +--- /dev/null ++++ b/include/amlogic/instaboot.h +@@ -0,0 +1,24 @@ ++#ifndef __INSTABOOT_H_ ++#define __INSTABOOT_H_ ++ ++#define __NEW_UTS_LEN 64 ++ ++struct new_utsname { ++ char sysname[__NEW_UTS_LEN + 1]; ++ char nodename[__NEW_UTS_LEN + 1]; ++ char release[__NEW_UTS_LEN + 1]; ++ char version[__NEW_UTS_LEN + 1]; ++ char machine[__NEW_UTS_LEN + 1]; ++ char domainname[__NEW_UTS_LEN + 1]; ++}; ++ ++struct instaboot_info { ++ struct new_utsname uts; ++ unsigned int version_code; ++}; ++#define INSTABOOT_SIG "INSTABOOT" ++ ++extern int get_instaboot_header(struct instaboot_info* ib_info); ++extern int fdt_instaboot(void *fdt); ++ ++#endif /* __INSTABOOT_H_ */ +diff --git a/include/amlogic/jtag.h b/include/amlogic/jtag.h +new file mode 100644 +index 00000000000..c85c513721c +--- /dev/null ++++ b/include/amlogic/jtag.h +@@ -0,0 +1,61 @@ ++#ifndef __MESON_JTAG_H__ ++#define __MESON_JTAG_H__ ++ ++#define INVALID_ID -1 ++ ++/* ioctl command */ ++#define JTAG_CLRPINMUX 0 ++#define JTAG_SETPINMUX 1 ++#define JTAG_EANBLE 2 ++#define JTAG_DISABLE 3 ++ ++/* jtag type */ ++#define JTAG_A 0 ++#define JTAG_B 1 ++#define SWD_A 2 ++ ++/* core type */ ++#define AP 1 /* a35 a53 a72 ... */ ++#define SCP 2 /* m3 */ ++#define SP 3 /* m4 */ ++#define DSPA 4 /* dsp-a */ ++#define DSPB 5 /* dsp-b */ ++#define DIF 6 /* dif */ ++#define AOCPU 7 /* aocpu */ ++#define AUCPU 8 /* aucpu */ ++ ++/* ++ * bitmap for jtag select ID: ++ * ++ * |---|---|---|---|---|---|---|------|------| ++ * | 9 | 8 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ++ * |---|---|---|---|---|---|---|------|------| ++ * | core type | jtag type |cluster type | ++ * |---------------|-----------|-------------| ++ */ ++#define CORE_TYPE_SHIFT 5 ++#define JTAG_TYPE_SHIFT 2 ++#define CLUSTER_TYPE_SHIFT 0 ++ ++#define CORE_TYPE_MASK 0xf ++#define JTAG_TYPE_MASK 0x7 ++#define CLUSTER_TYPE_MASK 0x3 ++ ++#define JTAG_SELECT_ID(core_type, jtag_type, cluster_type) \ ++ (((core_type & CORE_TYPE_MASK) << CORE_TYPE_SHIFT) |\ ++ ((jtag_type & JTAG_TYPE_MASK) << JTAG_TYPE_SHIFT) |\ ++ ((cluster_type & CLUSTER_TYPE_MASK) << CLUSTER_TYPE_SHIFT)) ++ ++#define CLUSTER_TYPE_UPDATE(id, cluster_type) \ ++ ((id & (~(CLUSTER_TYPE_MASK))) | cluster_type) ++ ++#define CORE_TYPE_GET(id) \ ++ ((id >> CORE_TYPE_SHIFT) & CORE_TYPE_MASK) ++ ++#define JTAG_TYPE_GET(id) \ ++ ((id >> JTAG_TYPE_SHIFT) & JTAG_TYPE_MASK) ++ ++#define CLUSTER_TYPE_GET(id) \ ++ ((id >> CLUSTER_TYPE_SHIFT) & CLUSTER_TYPE_MASK) ++ ++#endif /*_MESON_JTAG_H_*/ +diff --git a/include/amlogic/keyunify.h b/include/amlogic/keyunify.h +new file mode 100644 +index 00000000000..c89865f574d +--- /dev/null ++++ b/include/amlogic/keyunify.h +@@ -0,0 +1,56 @@ ++/* ++ * \file keymanage.h ++ * \brief API from drivers/keymange ++ * ++ * \version 1.0.0 ++ * \date 15/07/7 ++ * \author Sam.Wu ++ * ++ * Copyright (c) 2015 Amlogic. All Rights Reserved. ++ * ++ */ ++#ifndef __KEYUNIFY_H__ ++#define __KEYUNIFY_H__ ++ ++//APIs of key_unify*: unify interfaces for nandkeys/emmckeys/efuse keys ++ ++int key_unify_init(const char* seednum, const char* dtbaddr); ++ ++int key_unify_uninit(void); ++ ++//keyType: user type to define how to parse/check the key value before burn to target ++int key_unify_write(const char* keyname, const void* keydata, const unsigned datalen); ++ ++int key_unify_read(const char* keyname, void* keydata, const unsigned bufLen); ++ ++int key_unify_query_size(const char* keyname, ssize_t* keysize); ++ ++int key_unify_query_exist(const char* keyname, int* exist); ++ ++int key_unify_query_secure(const char* keyname, int* isSecure); ++ ++int key_unify_query_canOverWrite(const char* keyname, int* canOverWrite); ++ ++//Does the key configured in dts ++int key_unify_query_key_has_configure(const char* keyname); ++ ++//Another APIs with APP concers, like special flower hdcp2 ++//These APIs are based on key_unify_* ++// ++int key_manage_init(const char* seednum, const char* dtbaddr); ++int key_manage_exit(void); ++ ++int key_manage_write(const char* keyname, const void* keydata, const unsigned datalen); ++ ++int key_manage_read(const char* keyname, void* keydata, const unsigned bufLen); ++ ++int key_manage_query_size(const char* keyname, ssize_t* keysize); ++ ++int key_manage_query_exist(const char* keyname, int* exist); ++ ++int key_manage_query_secure(const char* keyname, int* isSecure); ++ ++int key_manage_query_canOverWrite(const char* keyname, int* canOverWrite); ++ ++#endif// #ifndef __KEYUNIFY_H__ ++ +diff --git a/include/amlogic/media/vout/aml_cvbs.h b/include/amlogic/media/vout/aml_cvbs.h +new file mode 100644 +index 00000000000..e4d0687d9b2 +--- /dev/null ++++ b/include/amlogic/media/vout/aml_cvbs.h +@@ -0,0 +1,13 @@ ++#ifndef __INC_AML_CVBS_H__ ++#define __INC_AML_CVBS_H__ ++ ++void cvbs_init(void); ++void cvbs_show_valid_vmode(void); ++int cvbs_outputmode_check(char *vmode_name, unsigned int frac); ++int cvbs_set_vmode(char* vmode_name); ++int cvbs_set_bist(char* bist_mode); ++int cvbs_set_vdac(int status); ++int cvbs_reg_debug(int argc, char* const argv[]); ++ ++#endif ++ +diff --git a/include/amlogic/media/vout/aml_vinfo.h b/include/amlogic/media/vout/aml_vinfo.h +new file mode 100644 +index 00000000000..7a453b26d6c +--- /dev/null ++++ b/include/amlogic/media/vout/aml_vinfo.h +@@ -0,0 +1,148 @@ ++#ifndef __AML_VINFO_H_ ++#define __AML_VINFO_H_ ++ ++struct vinfo_s { ++ ushort width; /* Number of columns (i.e. 160) */ ++ ushort height; /* Number of rows (i.e. 100) */ ++ ushort field_height; /* for interlace */ ++ u_char vl_bpix; /* Bits per pixel, 0 = 1 */ ++ ++ void *vd_base; /* Start of framebuffer memory */ ++ ++ void *vd_console_address; /* Start of console buffer */ ++ short console_col; ++ short console_row; ++ ++ int vd_color_fg; ++ int vd_color_bg; ++ ++ ushort *cmap; /* Pointer to the colormap */ ++ void *priv; /* Pointer to driver-specific data */ ++}; ++ ++ ++/************************************************************************/ ++/* ** BITMAP DISPLAY SUPPORT */ ++/************************************************************************/ ++#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) ++# include ++# include ++#endif ++ ++/* ++ * Information about displays we are using. This is for configuring ++ * the LCD controller and memory allocation. Someone has to know what ++ * is connected, as we can't autodetect anything. ++ */ ++#define CONFIG_SYS_HIGH 0 /* Pins are active high */ ++#define CONFIG_SYS_LOW 1 /* Pins are active low */ ++ ++#define LCD_COLOR2 2 ++#define LCD_COLOR4 4 ++#define LCD_COLOR8 8 ++#define LCD_COLOR16 16 ++#define LCD_COLOR24 24 ++#define LCD_COLOR32 32 ++ ++ ++/*----------------------------------------------------------------------*/ ++#if defined(CONFIG_LCD_INFO_BELOW_LOGO) ++# define LCD_INFO_X 0 ++# define LCD_INFO_Y (BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT) ++#elif defined(CONFIG_LCD_LOGO) ++# define LCD_INFO_X (BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH) ++# define LCD_INFO_Y (VIDEO_FONT_HEIGHT) ++#else ++# define LCD_INFO_X (VIDEO_FONT_WIDTH) ++# define LCD_INFO_Y (VIDEO_FONT_HEIGHT) ++#endif ++ ++/* Calculate nr. of bits per pixel and nr. of colors */ ++#define NBITS(bit_code) (bit_code) ++#define NCOLORS(bit_code) (1 << NBITS(bit_code)) ++ ++/************************************************************************/ ++/* ** CONSOLE CONSTANTS */ ++/************************************************************************/ ++#if LCD_BPP == LCD_MONOCHROME ++ ++/* ++ * Simple black/white definitions ++ */ ++# define CONSOLE_COLOR_BLACK 0 ++# define CONSOLE_COLOR_WHITE 1 /* Must remain last / highest */ ++ ++#elif LCD_BPP == LCD_COLOR8 ++ ++/* ++ * 8bpp color definitions ++ */ ++# define CONSOLE_COLOR_BLACK 0 ++# define CONSOLE_COLOR_RED 1 ++# define CONSOLE_COLOR_GREEN 2 ++# define CONSOLE_COLOR_YELLOW 3 ++# define CONSOLE_COLOR_BLUE 4 ++# define CONSOLE_COLOR_MAGENTA 5 ++# define CONSOLE_COLOR_CYAN 6 ++# define CONSOLE_COLOR_GREY 14 ++# define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ ++ ++#elif LCD_BPP == LCD_COLOR24 ++/* ++ * 24bpp color definitions ++ */ ++# define CONSOLE_COLOR_BLACK 0 ++# define CONSOLE_COLOR_RED 0x0000ff ++# define CONSOLE_COLOR_GREEN 0x00ff00 ++# define CONSOLE_COLOR_YELLOW 0x00ffff ++# define CONSOLE_COLOR_BLUE 0xff0000 ++# define CONSOLE_COLOR_MAGENTA 0xff00ff ++# define CONSOLE_COLOR_CYAN 0xffff00 ++# define CONSOLE_COLOR_GREY 0x808080 ++# define CONSOLE_COLOR_WHITE 0xffffff /* Must remain last / highest */ ++ ++#else ++ ++/* ++ * 16bpp color definitions ++ */ ++# define CONSOLE_COLOR_BLACK 0x0000 ++# define CONSOLE_COLOR_RED 0xf800 ++# define CONSOLE_COLOR_GREEN 0x07e0 ++# define CONSOLE_COLOR_YELLOW 0xffe0 ++# define CONSOLE_COLOR_BLUE 0x001f ++# define CONSOLE_COLOR_MAGENTA 0xf81f ++# define CONSOLE_COLOR_CYAN 0x07ff ++# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */ ++ ++#endif /* color definitions */ ++ ++/************************************************************************/ ++#ifndef PAGE_SIZE ++# define PAGE_SIZE 4096 ++#endif ++ ++/************************************************************************/ ++/* ** CONSOLE DEFINITIONS & FUNCTIONS */ ++/************************************************************************/ ++#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) ++# define CONSOLE_ROWS ((info->vl_row-BMP_LOGO_HEIGHT) \ ++ / VIDEO_FONT_HEIGHT) ++#else ++# define CONSOLE_ROWS (info->vl_row / VIDEO_FONT_HEIGHT) ++#endif ++ ++#define CONSOLE_COLS (panel_info.vl_col / VIDEO_FONT_WIDTH) ++#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * lcd_line_length) ++#define CONSOLE_ROW_FIRST (info->vd_console_address) ++#define CONSOLE_ROW_SECOND (info->vd_console_address + CONSOLE_ROW_SIZE) ++#define CONSOLE_ROW_LAST (info->vd_console_address + CONSOLE_SIZE \ ++ - CONSOLE_ROW_SIZE) ++#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) ++#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE) ++ ++# define COLOR_MASK(c) (c) ++ ++/************************************************************************/ ++ ++#endif +diff --git a/include/amlogic/media/vout/aml_vmode.h b/include/amlogic/media/vout/aml_vmode.h +new file mode 100644 +index 00000000000..738bcd73b24 +--- /dev/null ++++ b/include/amlogic/media/vout/aml_vmode.h +@@ -0,0 +1,98 @@ ++ ++#ifndef __AML_VMODE_H_ ++#define __AML_VMODE_H_ ++ ++typedef enum vmode_e { ++ VMODE_480I = 0, ++ VMODE_480I_RPT, ++ VMODE_480CVBS, ++ VMODE_480P, ++ VMODE_480P_RPT, ++ VMODE_480P_120HZ, ++ VMODE_576I, ++ VMODE_576I_RPT, ++ VMODE_576CVBS, ++ VMODE_576P, ++ VMODE_576P_RPT, ++ VMODE_576P_100HZ, ++ VMODE_720P, ++ VMODE_768P, ++ VMODE_1080I, ++ VMODE_1080P, ++ VMODE_720P_50HZ, ++ VMODE_720P_100HZ, ++ VMODE_720P_120HZ, ++ VMODE_1080I_50HZ, ++ VMODE_1080I_100HZ, ++ VMODE_1080I_120HZ, ++ VMODE_1080P_30HZ, ++ VMODE_1080P_50HZ, ++ VMODE_1080P_25HZ, ++ VMODE_1080P_24HZ, ++ VMODE_1080P_100HZ, ++ VMODE_1080P_120HZ, ++ VMODE_4K2K_30HZ, ++ VMODE_4K2K_25HZ, ++ VMODE_4K2K_24HZ, ++ VMODE_4K2K_SMPTE, ++ VMODE_4K2K_SMPTE_25HZ, ++ VMODE_4K2K_SMPTE_30HZ, ++ VMODE_4K2K_SMPTE_50HZ, ++ VMODE_4K2K_SMPTE_60HZ, ++ VMODE_4K2K_SMPTE_50HZ_Y420, ++ VMODE_4K2K_SMPTE_60HZ_Y420, ++ VMODE_4K2K_FAKE_5G, ++ VMODE_4K2K_60HZ, ++ VMODE_4K2K_60HZ_Y420, ++ VMODE_4K2K_50HZ, ++ VMODE_4K2K_50HZ_Y420, ++ VMODE_4K2K_5G, ++ VMODE_4K1K_120HZ, ++ VMODE_4K1K_120HZ_Y420, ++ VMODE_4K1K_100HZ, ++ VMODE_4K1K_100HZ_Y420, ++ VMODE_4K05K_240HZ, ++ VMODE_4K05K_240HZ_Y420, ++ VMODE_4K05K_200HZ, ++ VMODE_4K05K_200HZ_Y420, ++ VMODE_640x480p60hz, ++ VMODE_800x480p60hz, ++ VMODE_800x600p60hz, ++ VMODE_852x480p60hz, ++ VMODE_854x480p60hz, ++ VMODE_1024x600p60hz, ++ VMODE_1024x768p60hz, ++ VMODE_1152x864p75hz, ++ VMODE_1280x600p60hz, ++ VMODE_1280x768p60hz, ++ VMODE_1280x800p60hz, ++ VMODE_1280x960p60hz, ++ VMODE_1280x1024p60hz, ++ VMODE_1360x768p60hz, ++ VMODE_1366x768p60hz, ++ VMODE_1400x1050p60hz, ++ VMODE_1440x900p60hz, ++ VMODE_1440x2560p60hz, ++ VMODE_1440x2560p70hz, ++ VMODE_1600x900p60hz, ++ VMODE_1600x1200p60hz, ++ VMODE_1680x1050p60hz, ++ VMODE_1920x1200p60hz, ++ VMODE_2160x1200p90hz, ++ VMODE_2560x1080p60hz, ++ VMODE_2560x1440p60hz, ++ VMODE_2560x1600p60hz, ++ VMODE_3440x1440p60hz, ++ VMODE_VGA, ++ VMODE_SVGA, ++ VMODE_XGA, ++ VMODE_SXGA, ++ VMODE_WSXGA, ++ VMODE_FHDVGA, ++ VMODE_LCD, ++ VMODE_MAX, ++ VMODE_INIT_NULL, ++ VMODE_MASK = 0xFF, ++} vmode_t; ++ ++#endif +diff --git a/include/amlogic/media/vout/aml_vout.h b/include/amlogic/media/vout/aml_vout.h +new file mode 100644 +index 00000000000..53448bfc1e0 +--- /dev/null ++++ b/include/amlogic/media/vout/aml_vout.h +@@ -0,0 +1,25 @@ ++#ifndef __AML_VOUT_H_ ++#define __AML_VOUT_H_ ++ ++#include ++ ++#define VOUT_VIU1_SEL 1 ++#define VOUT_VIU2_SEL 2 ++ ++enum viu_mux_e { ++ VIU_MUX_ENCL = 0, ++ VIU_MUX_ENCI, ++ VIU_MUX_ENCP, ++ VIU_MUX_MAX, ++}; ++ ++void vout_init(void); ++void vout_vinfo_dump(void); ++int vout_get_current_vmode(void); ++int vout_get_current_axis(int *axis); ++void vout_set_current_vmode(int mode); ++struct vinfo_s *vout_get_current_vinfo(void); ++void vout_viu_mux(int viu_sel, int venc_sel); ++extern unsigned long get_fb_addr(void); ++#endif ++ +diff --git a/include/amlogic/media/vout/hdmitx/hdmi_common.h b/include/amlogic/media/vout/hdmitx/hdmi_common.h +new file mode 100644 +index 00000000000..66fdedd1d62 +--- /dev/null ++++ b/include/amlogic/media/vout/hdmitx/hdmi_common.h +@@ -0,0 +1,655 @@ ++#ifndef __HDMI_COMMON_H__ ++#define __HDMI_COMMON_H__ ++ ++/* Little-Endian format */ ++enum scdc_addr { ++ SINK_VER = 0x01, ++ SOURCE_VER, /* RW */ ++ UPDATE_0 = 0x10, /* RW */ ++ UPDATE_1, /* RW */ ++ TMDS_CFG = 0x20, /* RW */ ++ SCRAMBLER_ST, ++ CONFIG_0 = 0x30, /* RW */ ++ STATUS_FLAGS_0 = 0x40, ++ STATUS_FLAGS_1, ++ ERR_DET_0_L = 0x50, ++ ERR_DET_0_H, ++ ERR_DET_1_L, ++ ERR_DET_1_H, ++ ERR_DET_2_L, ++ ERR_DET_2_H, ++ ERR_DET_CHKSUM, ++ TEST_CONFIG_0 = 0xC0, /* RW */ ++ MANUFACT_IEEE_OUI_2 = 0xD0, ++ MANUFACT_IEEE_OUI_1, ++ MANUFACT_IEEE_OUI_0, ++ DEVICE_ID = 0xD3, /* 0xD3 ~ 0xDD */ ++ /* RW 0xDE ~ 0xFF */ ++ MANUFACT_SPECIFIC = 0xDE, ++}; ++ ++#define HDMITX_VIC420_OFFSET 0x100 ++#define HDMITX_VESA_OFFSET 0x300 ++ ++/* HDMI VIC definitions */ ++enum hdmi_vic { ++ /* Refer to CEA 861-D */ ++ HDMI_unkown = 0, ++ HDMI_640x480p60_4x3 = 1, ++ HDMI_720x480p60_4x3 = 2, ++ HDMI_720x480p60_16x9 = 3, ++ HDMI_1280x720p60_16x9 = 4, ++ HDMI_1920x1080i60_16x9 = 5, ++ HDMI_720x480i60_4x3 = 6, ++ HDMI_720x480i60_16x9 = 7, ++ HDMI_720x240p60_4x3 = 8, ++ HDMI_720x240p60_16x9 = 9, ++ HDMI_2880x480i60_4x3 = 10, ++ HDMI_2880x480i60_16x9 = 11, ++ HDMI_2880x240p60_4x3 = 12, ++ HDMI_2880x240p60_16x9 = 13, ++ HDMI_1440x480p60_4x3 = 14, ++ HDMI_1440x480p60_16x9 = 15, ++ HDMI_1920x1080p60_16x9 = 16, ++ HDMI_720x576p50_4x3 = 17, ++ HDMI_720x576p50_16x9 = 18, ++ HDMI_1280x720p50_16x9 = 19, ++ HDMI_1920x1080i50_16x9 = 20, ++ HDMI_720x576i50_4x3 = 21, ++ HDMI_720x576i50_16x9 = 22, ++ HDMI_720x288p_4x3 = 23, ++ HDMI_720x288p_16x9 = 24, ++ HDMI_2880x576i50_4x3 = 25, ++ HDMI_2880x576i50_16x9 = 26, ++ HDMI_2880x288p50_4x3 = 27, ++ HDMI_2880x288p50_16x9 = 28, ++ HDMI_1440x576p_4x3 = 29, ++ HDMI_1440x576p_16x9 = 30, ++ HDMI_1920x1080p50_16x9 = 31, ++ HDMI_1920x1080p24_16x9 = 32, ++ HDMI_1920x1080p25_16x9 = 33, ++ HDMI_1920x1080p30_16x9 = 34, ++ HDMI_2880x480p60_4x3 = 35, ++ HDMI_2880x480p60_16x9 = 36, ++ HDMI_2880x576p50_4x3 = 37, ++ HDMI_2880x576p50_16x9 = 38, ++ HDMI_1920x1080i_t1250_50_16x9 = 39, ++ HDMI_1920x1080i100_16x9 = 40, ++ HDMI_1280x720p100_16x9 = 41, ++ HDMI_720x576p100_4x3 = 42, ++ HDMI_720x576p100_16x9 = 43, ++ HDMI_720x576i100_4x3 = 44, ++ HDMI_720x576i100_16x9 = 45, ++ HDMI_1920x1080i120_16x9 = 46, ++ HDMI_1280x720p120_16x9 = 47, ++ HDMI_720x480p120_4x3 = 48, ++ HDMI_720x480p120_16x9 = 49, ++ HDMI_720x480i120_4x3 = 50, ++ HDMI_720x480i120_16x9 = 51, ++ HDMI_720x576p200_4x3 = 52, ++ HDMI_720x576p200_16x9 = 53, ++ HDMI_720x576i200_4x3 = 54, ++ HDMI_720x576i200_16x9 = 55, ++ HDMI_720x480p240_4x3 = 56, ++ HDMI_720x480p240_16x9 = 57, ++ HDMI_720x480i240_4x3 = 58, ++ HDMI_720x480i240_16x9 = 59, ++ /* Refet to CEA 861-F */ ++ HDMI_1280x720p24_16x9 = 60, ++ HDMI_1280x720p25_16x9 = 61, ++ HDMI_1280x720p30_16x9 = 62, ++ HDMI_1920x1080p120_16x9 = 63, ++ HDMI_1920x1080p100_16x9 = 64, ++ HDMI_1280x720p24_64x27 = 65, ++ HDMI_1280x720p25_64x27 = 66, ++ HDMI_1280x720p30_64x27 = 67, ++ HDMI_1280x720p50_64x27 = 68, ++ HDMI_1280x720p60_64x27 = 69, ++ HDMI_1280x720p100_64x27 = 70, ++ HDMI_1280x720p120_64x27 = 71, ++ HDMI_1920x1080p24_64x27 = 72, ++ HDMI_1920x1080p25_64x27 = 73, ++ HDMI_1920x1080p30_64x27 = 74, ++ HDMI_1920x1080p50_64x27 = 75, ++ HDMI_1920x1080p60_64x27 = 76, ++ HDMI_1920x1080p100_64x27 = 77, ++ HDMI_1920x1080p120_64x27 = 78, ++ HDMI_1680x720p24_64x27 = 79, ++ HDMI_1680x720p25_64x27 = 80, ++ HDMI_1680x720p30_64x27 = 81, ++ HDMI_1680x720p50_64x27 = 82, ++ HDMI_1680x720p60_64x27 = 83, ++ HDMI_1680x720p100_64x27 = 84, ++ HDMI_1680x720p120_64x27 = 85, ++ HDMI_2560x1080p24_64x27 = 86, ++ HDMI_2560x1080p25_64x27 = 87, ++ HDMI_2560x1080p30_64x27 = 88, ++ HDMI_2560x1080p50_64x27 = 89, ++ HDMI_2560x1080p60_64x27 = 90, ++ HDMI_2560x1080p100_64x27 = 91, ++ HDMI_2560x1080p120_64x27 = 92, ++ HDMI_3840x2160p24_16x9 = 93, ++ HDMI_3840x2160p25_16x9 = 94, ++ HDMI_3840x2160p30_16x9 = 95, ++ HDMI_3840x2160p50_16x9 = 96, ++ HDMI_3840x2160p60_16x9 = 97, ++ HDMI_4096x2160p24_256x135 = 98, ++ HDMI_4096x2160p25_256x135 = 99, ++ HDMI_4096x2160p30_256x135 = 100, ++ HDMI_4096x2160p50_256x135 = 101, ++ HDMI_4096x2160p60_256x135 = 102, ++ HDMI_3840x2160p24_64x27 = 103, ++ HDMI_3840x2160p25_64x27 = 104, ++ HDMI_3840x2160p30_64x27 = 105, ++ HDMI_3840x2160p50_64x27 = 106, ++ HDMI_3840x2160p60_64x27 = 107, ++ HDMI_RESERVED = 108, ++ /* ++ the following vic is for those y420 mode ++ they are all beyond OFFSET_HDMITX_VIC420(0x1000) ++ and they has same vic with normal vic in the lower bytes. ++ */ ++ HDMI_VIC_Y420 = HDMITX_VIC420_OFFSET, ++ HDMI_3840x2160p50_16x9_Y420 = ++ HDMITX_VIC420_OFFSET + HDMI_3840x2160p50_16x9, ++ HDMI_3840x2160p60_16x9_Y420 = ++ HDMITX_VIC420_OFFSET + HDMI_3840x2160p60_16x9, ++ HDMI_4096x2160p50_256x135_Y420 = ++ HDMITX_VIC420_OFFSET + HDMI_4096x2160p50_256x135, ++ HDMI_4096x2160p60_256x135_Y420 = ++ HDMITX_VIC420_OFFSET + HDMI_4096x2160p60_256x135, ++ HDMI_3840x2160p50_64x27_Y420 = ++ HDMITX_VIC420_OFFSET + HDMI_3840x2160p50_64x27, ++ HDMI_3840x2160p60_64x27_Y420 = ++ HDMITX_VIC420_OFFSET + HDMI_3840x2160p60_64x27, ++ HDMIV_640x480p60hz = HDMITX_VESA_OFFSET, ++ HDMIV_800x480p60hz, ++ HDMIV_800x600p60hz, ++ HDMIV_852x480p60hz, ++ HDMIV_854x480p60hz, ++ HDMIV_1024x600p60hz, ++ HDMIV_1024x768p60hz, ++ HDMIV_1152x864p75hz, ++ HDMIV_1280x600p60hz, ++ HDMIV_1280x768p60hz, ++ HDMIV_1280x800p60hz, ++ HDMIV_1280x960p60hz, ++ HDMIV_1280x1024p60hz, ++ HDMIV_1360x768p60hz, ++ HDMIV_1366x768p60hz, ++ HDMIV_1400x1050p60hz, ++ HDMIV_1440x900p60hz, ++ HDMIV_1440x2560p60hz, ++ HDMIV_1440x2560p70hz, ++ HDMIV_1600x900p60hz, ++ HDMIV_1600x1200p60hz, ++ HDMIV_1680x1050p60hz, ++ HDMIV_1920x1200p60hz, ++ HDMIV_2160x1200p90hz, ++ HDMIV_2560x1080p60hz, ++ HDMIV_2560x1440p60hz, ++ HDMIV_2560x1600p60hz, ++ HDMIV_3440x1440p60hz, ++ HDMIV_2400x1200p90hz, ++}; ++ ++/* Compliance with old definitions */ ++#define HDMI_640x480p60 HDMI_640x480p60_4x3 ++#define HDMI_480p60 HDMI_720x480p60_4x3 ++#define HDMI_480p60_16x9 HDMI_720x480p60_16x9 ++#define HDMI_720p60 HDMI_1280x720p60_16x9 ++#define HDMI_1080i60 HDMI_1920x1080i60_16x9 ++#define HDMI_480i60 HDMI_720x480i60_4x3 ++#define HDMI_480i60_16x9 HDMI_720x480i60_16x9 ++#define HDMI_480i60_16x9_rpt HDMI_2880x480i60_16x9 ++#define HDMI_1440x480p60 HDMI_1440x480p60_4x3 ++#define HDMI_1440x480p60_16x9 HDMI_1440x480p60_16x9 ++#define HDMI_1080p60 HDMI_1920x1080p60_16x9 ++#define HDMI_576p50 HDMI_720x576p50_4x3 ++#define HDMI_576p50_16x9 HDMI_720x576p50_16x9 ++#define HDMI_720p50 HDMI_1280x720p50_16x9 ++#define HDMI_1080i50 HDMI_1920x1080i50_16x9 ++#define HDMI_576i50 HDMI_720x576i50_4x3 ++#define HDMI_576i50_16x9 HDMI_720x576i50_16x9 ++#define HDMI_576i50_16x9_rpt HDMI_2880x576i50_16x9 ++#define HDMI_1080p50 HDMI_1920x1080p50_16x9 ++#define HDMI_1080p24 HDMI_1920x1080p24_16x9 ++#define HDMI_1080p25 HDMI_1920x1080p25_16x9 ++#define HDMI_1080p30 HDMI_1920x1080p30_16x9 ++#define HDMI_1080p120 HDMI_1920x1080p120_16x9 ++#define HDMI_480p60_16x9_rpt HDMI_2880x480p60_16x9 ++#define HDMI_576p50_16x9_rpt HDMI_2880x576p50_16x9 ++#define HDMI_4k2k_24 HDMI_3840x2160p24_16x9 ++#define HDMI_4k2k_25 HDMI_3840x2160p25_16x9 ++#define HDMI_4k2k_30 HDMI_3840x2160p30_16x9 ++#define HDMI_4k2k_50 HDMI_3840x2160p50_16x9 ++#define HDMI_4k2k_60 HDMI_3840x2160p60_16x9 ++#define HDMI_4k2k_smpte_24 HDMI_4096x2160p24_256x135 ++#define HDMI_4k2k_smpte_50 HDMI_4096x2160p50_256x135 ++#define HDMI_4k2k_smpte_60 HDMI_4096x2160p60_256x135 ++ ++/* CEA TIMING STRUCT DEFINITION */ ++struct hdmi_cea_timing { ++ unsigned int pixel_freq; /* Unit: 1000 */ ++ unsigned int h_freq; /* Unit: Hz */ ++ unsigned int v_freq; /* Unit: 0.001 Hz */ ++ unsigned int vsync_polarity:1; /* 1: positive 0: negative */ ++ unsigned int hsync_polarity:1; ++ unsigned short h_active; ++ unsigned short h_total; ++ unsigned short h_blank; ++ unsigned short h_front; ++ unsigned short h_sync; ++ unsigned short h_back; ++ unsigned short v_active; ++ unsigned short v_total; ++ unsigned short v_blank; ++ unsigned short v_front; ++ unsigned short v_sync; ++ unsigned short v_back; ++ unsigned short v_sync_ln; ++}; ++ ++/* Refer CEA861-D Page 116 Table 55 */ ++struct dtd { ++ unsigned short pixel_clock; ++ unsigned short h_active; ++ unsigned short h_blank; ++ unsigned short v_active; ++ unsigned short v_blank; ++ unsigned short h_sync_offset; ++ unsigned short h_sync; ++ unsigned short v_sync_offset; ++ unsigned short v_sync; ++ unsigned char h_image_size; ++ unsigned char v_image_size; ++ unsigned char h_border; ++ unsigned char v_border; ++ unsigned char flags; ++ enum hdmi_vic vic; ++}; ++ ++/* Dolby Version support information from EDID*/ ++/* Refer to DV Spec version2.9 page26 to page39*/ ++enum block_type { ++ ERROR_NULL = 0, ++ ERROR_LENGTH, ++ ERROR_OUI, ++ ERROR_VER, ++ CORRECT, ++}; ++ ++ ++ ++#define DV_IEEE_OUI 0x00D046 ++#define HDR10_PLUS_IEEE_OUI 0x90848B ++ ++#define HDMI_PACKET_VEND 1 ++#define HDMI_PACKET_DRM 0x86 ++ ++#define CMD_CONF_OFFSET (0x14 << 24) ++#define CONF_AVI_BT2020 (CMD_CONF_OFFSET + 0X2000 + 0x00) ++ #define CLR_AVI_BT2020 0x0 ++ #define SET_AVI_BT2020 0x1 ++/* set value as COLORSPACE_RGB444, YUV422, YUV444, YUV420 */ ++#define CONF_AVI_RGBYCC_INDIC (CMD_CONF_OFFSET + 0X2000 + 0x01) ++#define CONF_AVI_Q01 (CMD_CONF_OFFSET + 0X2000 + 0x02) ++ #define RGB_RANGE_DEFAULT 0 ++ #define RGB_RANGE_LIM 1 ++ #define RGB_RANGE_FUL 2 ++ #define RGB_RANGE_RSVD 3 ++#define CONF_AVI_YQ01 (CMD_CONF_OFFSET + 0X2000 + 0x03) ++ #define YCC_RANGE_LIM 0 ++ #define YCC_RANGE_FUL 1 ++ #define YCC_RANGE_RSVD 2 ++ ++struct hdr_info { ++ unsigned int hdr_sup_eotf_sdr:1; ++ unsigned int hdr_sup_eotf_hdr:1; ++ unsigned int hdr_sup_eotf_smpte_st_2084:1; ++ unsigned int hdr_sup_eotf_hlg:1; ++ unsigned int hdr_sup_SMD_type1:1; ++ unsigned char hdr_lum_max; ++ unsigned char hdr_lum_avg; ++ unsigned char hdr_lum_min; ++ unsigned char rawdata[7]; ++}; ++ ++struct hdr10_plus_info { ++ uint32_t ieeeoui; ++ uint8_t length; ++ uint8_t application_version; ++}; ++ ++enum hdmi_hdr_transfer { ++ T_UNKNOWN = 0, ++ T_BT709, ++ T_UNDEF, ++ T_BT601, ++ T_BT470M, ++ T_BT470BG, ++ T_SMPTE170M, ++ T_SMPTE240M, ++ T_LINEAR, ++ T_LOG100, ++ T_LOG316, ++ T_IEC61966_2_4, ++ T_BT1361E, ++ T_IEC61966_2_1, ++ T_BT2020_10, ++ T_BT2020_12, ++ T_SMPTE_ST_2084, ++ T_SMPTE_ST_28, ++ T_HLG, ++}; ++ ++enum hdmi_hdr_color { ++ C_UNKNOWN = 0, ++ C_BT709, ++ C_UNDEF, ++ C_BT601, ++ C_BT470M, ++ C_BT470BG, ++ C_SMPTE170M, ++ C_SMPTE240M, ++ C_FILM, ++ C_BT2020, ++}; ++ ++/* master_display_info for display device */ ++struct master_display_info_s { ++ u32 present_flag; ++ u32 features; /* feature bits bt2020/2084 */ ++ u32 primaries[3][2]; /* normalized 50000 in G,B,R order */ ++ u32 white_point[2]; /* normalized 50000 */ ++ u32 luminance[2]; /* max/min lumin, normalized 10000 */ ++ u32 max_content; /* Maximum Content Light Level */ ++ u32 max_frame_average; /* Maximum Frame-average Light Level */ ++}; ++ ++struct hdr10plus_para { ++ uint8_t application_version; ++ uint8_t targeted_max_lum; ++ uint8_t average_maxrgb; ++ uint8_t distribution_values[9]; ++ uint8_t num_bezier_curve_anchors; ++ uint32_t knee_point_x; ++ uint32_t knee_point_y; ++ uint8_t bezier_curve_anchors[9]; ++ uint8_t graphics_overlay_flag; ++ uint8_t no_delay_flag; ++}; ++ ++struct dv_info { ++ unsigned char rawdata[27]; ++ enum block_type block_flag; ++ uint32_t ieeeoui; ++ uint8_t ver; /* 0 or 1 or 2*/ ++ uint8_t length;/*ver1: 15 or 12*/ ++ ++ uint8_t sup_yuv422_12bit:1; ++ /* if as 0, then support RGB tunnel mode */ ++ uint8_t sup_2160p60hz:1; ++ /* if as 0, then support 2160p30hz */ ++ uint8_t sup_global_dimming:1; ++ uint16_t Rx; ++ uint16_t Ry; ++ uint16_t Gx; ++ uint16_t Gy; ++ uint16_t Bx; ++ uint16_t By; ++ uint16_t Wx; ++ uint16_t Wy; ++ uint16_t tminPQ; ++ uint16_t tmaxPQ; ++ uint8_t dm_major_ver; ++ uint8_t dm_minor_ver; ++ uint8_t dm_version; ++ uint8_t tmaxLUM; ++ uint8_t colorimetry:1;/* ver1*/ ++ uint8_t tminLUM; ++ uint8_t low_latency;/* ver1_12 and 2*/ ++ uint8_t sup_backlight_control:1;/*only ver2*/ ++ uint8_t backlt_min_luma;/*only ver2*/ ++ uint8_t Interface;/*only ver2*/ ++ uint8_t sup_10b_12b_444;/*only ver2*/ ++ uint8_t support_DV_RGB_444_8BIT; ++ uint8_t support_LL_YCbCr_422_12BIT; ++ uint8_t support_LL_RGB_444_10BIT; ++ uint8_t support_LL_RGB_444_12BIT; ++}; ++ ++enum eotf_type { ++ EOTF_T_NULL = 0, ++ EOTF_T_DOLBYVISION, ++ EOTF_T_HDR10, ++ EOTF_T_SDR, ++ EOTF_T_LL_MODE, ++ EOTF_T_MAX, ++}; ++ ++enum mode_type { ++ YUV422_BIT12 = 0, ++ RGB_8BIT, ++ RGB_10_12BIT, ++ YUV444_10_12BIT, ++}; ++ ++/* Dolby Version VSIF parameter*/ ++struct dv_vsif_para { ++ uint8_t ver; /* 0 or 1 or 2*/ ++ uint8_t length;/*ver1: 15 or 12*/ ++ union { ++ struct { ++ uint8_t low_latency:1; ++ uint8_t dobly_vision_signal:1; ++ uint8_t backlt_ctrl_MD_present:1; ++ uint8_t auxiliary_MD_present:1; ++ uint8_t eff_tmax_PQ_hi; ++ uint8_t eff_tmax_PQ_low; ++ uint8_t auxiliary_runmode; ++ uint8_t auxiliary_runversion; ++ uint8_t auxiliary_debug0; ++ } ver2; ++ } vers; ++}; ++ ++#define Y420CMDB_MAX 32 ++#define VIC_MAX_NUM 256 ++struct rx_cap { ++ unsigned int native_Mode; ++ /*video*/ ++ unsigned int VIC[VIC_MAX_NUM]; ++ unsigned int VIC_count; ++ unsigned int native_VIC; ++ /*vendor*/ ++ unsigned int IEEEOUI; ++ unsigned int Max_TMDS_Clock1; /* HDMI1.4b TMDS_CLK */ ++ unsigned int HF_IEEEOUI; /* For HDMI Forum */ ++ unsigned int Max_TMDS_Clock2; /* HDMI2.0 TMDS_CLK */ ++ /* CEA861-F, Table 56, Colorimetry Data Block */ ++ unsigned int colorimetry_data; ++ unsigned int scdc_present:1; ++ unsigned int scdc_rr_capable:1; /* SCDC read request */ ++ unsigned int lte_340mcsc_scramble:1; ++ unsigned support_ycbcr444_flag:1; ++ unsigned support_ycbcr422_flag:1; ++ unsigned int dc_y444:1; ++ unsigned int dc_30bit:1; ++ unsigned int dc_36bit:1; ++ unsigned int dc_48bit:1; ++ unsigned int dc_y420:1; ++ unsigned int dc_30bit_420:1; ++ unsigned int dc_36bit_420:1; ++ unsigned int dc_48bit_420:1; ++ unsigned char edid_version; ++ unsigned char edid_revision; ++ unsigned int ColorDeepSupport; ++ unsigned int Video_Latency; ++ unsigned int Audio_Latency; ++ unsigned int Interlaced_Video_Latency; ++ unsigned int Interlaced_Audio_Latency; ++ unsigned int threeD_present; ++ unsigned int threeD_Multi_present; ++ unsigned int hdmi_vic_LEN; ++ enum hdmi_vic preferred_mode; ++ struct dtd dtd[16]; ++ unsigned char dtd_idx; ++ unsigned char flag_vfpdb; ++ unsigned char number_of_dtd; ++ unsigned char pref_colorspace; ++ struct hdr_info hdr_info; ++ struct dv_info dv_info; ++ struct hdr10_plus_info hdr10plus_info; ++ /*blk0 check sum*/ ++ unsigned char chksum; ++ /*blk0-3 check sum*/ ++ char checksum[10]; ++ unsigned char edid_changed; ++ /* for total = 32*8 = 256 VICs */ ++ /* for Y420CMDB bitmap */ ++ unsigned char bitmap_valid; ++ unsigned char bitmap_length; ++ unsigned char y420_all_vic; ++ unsigned char y420cmdb_bitmap[Y420CMDB_MAX]; ++}; ++ ++enum color_attr_type { ++ COLOR_ATTR_YCBCR444_12BIT = 0, ++ COLOR_ATTR_YCBCR422_12BIT, ++ COLOR_ATTR_YCBCR420_12BIT, ++ COLOR_ATTR_RGB_12BIT, ++ COLOR_ATTR_YCBCR444_10BIT, ++ COLOR_ATTR_YCBCR422_10BIT, ++ COLOR_ATTR_YCBCR420_10BIT, ++ COLOR_ATTR_RGB_10BIT, ++ COLOR_ATTR_YCBCR444_8BIT, ++ COLOR_ATTR_YCBCR422_8BIT, ++ COLOR_ATTR_YCBCR420_8BIT, ++ COLOR_ATTR_RGB_8BIT, ++ COLOR_ATTR_RESERVED, ++}; ++ ++struct color_attr_to_string { ++ enum color_attr_type color_attr; ++ const char *color_attr_string; ++}; ++ ++enum hdmi_color_depth { ++ HDMI_COLOR_DEPTH_24B = 4, ++ HDMI_COLOR_DEPTH_30B = 5, ++ HDMI_COLOR_DEPTH_36B = 6, ++ HDMI_COLOR_DEPTH_48B = 7, ++}; ++ ++enum hdmi_color_format { ++ HDMI_COLOR_FORMAT_RGB, ++ HDMI_COLOR_FORMAT_422, ++ HDMI_COLOR_FORMAT_444, ++ HDMI_COLOR_FORMAT_420, ++}; ++ ++enum hdmi_color_range { ++ HDMI_COLOR_RANGE_LIM, ++ HDMI_COLOR_RANGE_FUL, ++}; ++ ++enum hdmi_audio_packet { ++ HDMI_AUDIO_PACKET_SMP = 0x02, ++ HDMI_AUDIO_PACKET_1BT = 0x07, ++ HDMI_AUDIO_PACKET_DST = 0x08, ++ HDMI_AUDIO_PACKET_HBR = 0x09, ++}; ++ ++enum hdmi_phy_para { ++ HDMI_PHYPARA_6G = 1, /* 2160p60hz 444 8bit */ ++ HDMI_PHYPARA_4p5G, /* 2160p50hz 420 12bit */ ++ HDMI_PHYPARA_3p7G, /* 2160p30hz 444 10bit */ ++ HDMI_PHYPARA_3G, /* 2160p24hz 444 8bit */ ++ HDMI_PHYPARA_LT3G, /* 1080p60hz 444 12bit */ ++ HDMI_PHYPARA_DEF = HDMI_PHYPARA_LT3G, ++ HDMI_PHYPARA_270M, /* 480p60hz 444 8bit */ ++}; ++ ++/* get hdmi cea timing ++ * t: struct hdmi_cea_timing * ++ */ ++#define GET_TIMING(name) (t->name) ++ ++struct parse_cd { ++ enum hdmi_color_depth cd; ++ const char *name; ++}; ++ ++struct parse_cs { ++ enum hdmi_color_format cs; ++ const char *name; ++}; ++ ++struct parse_cr { ++ enum hdmi_color_format cr; ++ const char *name; ++}; ++ ++#define EDID_BLK_NO 4 ++#define EDID_BLK_SIZE 128 ++struct hdmi_format_para { ++ enum hdmi_vic vic; ++ char *name; /* full name, 1280x720p60hz */ ++ char *sname; /* short name, 1280x720p60hz -> 720p60hz */ ++ char ext_name[32]; ++ enum hdmi_color_depth cd; /* cd8, cd10 or cd12 */ ++ enum hdmi_color_format cs; /* rgb, y444, y422, y420 */ ++ enum hdmi_color_range cr; /* limit, full */ ++ unsigned int pixel_repetition_factor; ++ unsigned int progress_mode:1; /* 0: Interlace 1: Progressive */ ++ unsigned int scrambler_en:1; ++ unsigned int tmds_clk_div40:1; ++ unsigned int tmds_clk; /* Unit: 1000 */ ++ struct hdmi_cea_timing timing; ++}; ++ ++struct hdmi_support_mode { ++ enum hdmi_vic vic; ++ char *sname; ++ char y420; ++}; ++ ++#define DOLBY_VISION_LL_RGB 3 ++#define DOLBY_VISION_LL_YUV 2 ++#define DOLBY_VISION_STD_ENABLE 1 ++#define DOLBY_VISION_DISABLE 0 ++#define DOLBY_VISION_ENABLE 1 ++ ++#define HDMI_IEEEOUI 0x000C03 ++#define MODE_LEN 32 ++#define VESA_MAX_TIMING 64 ++ ++typedef struct input_hdmi_data { ++ char ubootenv_hdmimode[MODE_LEN]; ++ char ubootenv_colorattribute[MODE_LEN]; ++ int ubootenv_dv_type; ++ #if 0 ++ bool isbestpolicy; ++ bool isSupport4K30Hz; ++ bool isSupport4K; ++ bool isDeepColor; ++ bool isframeratepriority; ++ bool isLowPowerMode; ++ #endif ++ struct rx_cap *pRXCap; ++} hdmi_data_t; ++ ++typedef struct scene_output_info { ++ char final_displaymode[MODE_LEN]; ++ char final_deepcolor[MODE_LEN]; ++ int final_dv_type; ++} scene_output_info_t; ++ ++struct dispmode_vic { ++ const char *disp_mode; ++ enum hdmi_vic VIC; ++}; ++ ++#endif ++ +diff --git a/include/amlogic/media/vout/hdmitx/hdmitx.h b/include/amlogic/media/vout/hdmitx/hdmitx.h +new file mode 100644 +index 00000000000..1458741089b +--- /dev/null ++++ b/include/amlogic/media/vout/hdmitx/hdmitx.h +@@ -0,0 +1,11 @@ ++#ifndef __HDMITX_H_ ++#define __HDMITX_H_ ++#include "hdmi_common.h" ++#include "hdmitx_module.h" ++#include "hdmitx_reg.h" ++#include "mach_reg.h" ++ ++int hdmitx_likely_frac_rate_mode(char *m); ++int hdmi_outputmode_check(char *mode, unsigned int frac); ++ ++#endif +diff --git a/include/amlogic/media/vout/hdmitx/hdmitx_ext.h b/include/amlogic/media/vout/hdmitx/hdmitx_ext.h +new file mode 100644 +index 00000000000..acf58a80910 +--- /dev/null ++++ b/include/amlogic/media/vout/hdmitx/hdmitx_ext.h +@@ -0,0 +1,6 @@ ++#ifndef __HDMITX_EXT_H__ ++#define __HDMITX_EXT_H__ ++ ++void hdmitx_init(void); ++ ++#endif +diff --git a/include/amlogic/media/vout/hdmitx/hdmitx_module.h b/include/amlogic/media/vout/hdmitx/hdmitx_module.h +new file mode 100644 +index 00000000000..60d22f63e3f +--- /dev/null ++++ b/include/amlogic/media/vout/hdmitx/hdmitx_module.h +@@ -0,0 +1,106 @@ ++#ifndef __HDMITX_MODULE_H__ ++#define __HDMITX_MODULE_H__ ++ ++#include "hdmi_common.h" ++#include "hdmitx_ext.h" ++ ++struct hdmitx_dev { ++ unsigned char rx_edid[512]; /* some RX may exceeds 256Bytes */ ++ struct { ++ int (*get_hpd_state)(void); ++ int (*read_edid)(unsigned char *buf, unsigned char addr, ++ unsigned char blk_no); ++ void (*turn_off)(void); ++ void (*list_support_modes)(void); ++ void (*dump_regs)(void); ++ void (*test_bist)(unsigned int mode); ++ void (*test_prbs)(void); ++ void (*set_div40)(bool div40); ++ void (*output_blank)(unsigned int blank); ++ } hwop; ++ unsigned char rawedid[EDID_BLK_SIZE * EDID_BLK_NO]; ++ struct rx_cap RXCap; ++ struct hdmi_format_para *para; ++ enum hdmi_vic vic; ++ unsigned int frac_rate_policy; ++ unsigned int mode420; ++ unsigned int dc30; ++ enum eotf_type hdmi_current_eotf_type; ++ enum mode_type hdmi_current_tunnel_mode; ++ /* Add dongle_mode, clock, phy may be different from mbox */ ++ unsigned int dongle_mode; ++}; ++ ++struct hdmitx_dev *hdmitx_get_hdev(void); ++ ++struct hdmi_format_para *hdmi_get_fmt_paras(enum hdmi_vic vic); ++enum hdmi_vic hdmi_get_fmt_vic(char const *name); ++void hdmi_parse_attr(struct hdmi_format_para *para, char const *name); ++int hdmitx_edid_VIC_support(enum hdmi_vic vic); ++enum hdmi_vic hdmitx_edid_vic_tab_map_vic(const char *disp_mode); ++const char *hdmitx_edid_vic_tab_map_string(enum hdmi_vic vic); ++const char *hdmitx_edid_vic_to_string(enum hdmi_vic vic); ++bool hdmitx_edid_check_valid_mode(struct hdmitx_dev *hdev, ++ struct hdmi_format_para *para); ++enum hdmi_vic hdmitx_edid_get_VIC(struct hdmitx_dev *hdev, ++ const char *disp_mode, char force_flag); ++bool edid_parsing_ok(struct hdmitx_dev *hdev); ++bool is_dolby_enabled(void); ++bool is_tv_support_dv(struct hdmitx_dev *hdev); ++void dolbyvision_scene_process(hdmi_data_t *hdmi_data, ++ scene_output_info_t *output_info); ++void sdr_scene_process(hdmi_data_t *hdmi_data, ++ scene_output_info_t *output_info); ++void get_hdmi_data(struct hdmitx_dev *hdev, hdmi_data_t *data); ++bool pre_process_str(char *name); ++struct hdmi_format_para *hdmi_tst_fmt_name(char const *name, char const *attr); ++bool is_supported_mode_attr(hdmi_data_t *hdmi_data, char *mode_attr); ++int get_ubootenv_dv_type(void); ++void hdmi_tx_set(struct hdmitx_dev *hdev); ++/* Parsing RAW EDID data from edid to pRXCap */ ++unsigned int hdmi_edid_parsing(unsigned char *edid, struct rx_cap *pRXCap); ++struct hdmi_format_para *hdmi_match_dtd_paras(struct dtd *t); ++bool hdmimode_is_interlaced(enum hdmi_vic vic); ++void hdmitx_ddc_init(void); ++void hdmitx_set_clk(struct hdmitx_dev *hdev); ++void hdmitx_turnoff(void); ++int hdmitx_get_hpd_state(void); ++void hdmitx_prbs(void); ++unsigned int hdmitx_rd_check_reg(unsigned int addr, unsigned int exp_data, ++ unsigned int mask); ++void hdmitx_hdcp_init(void); ++void hdmitx_set_phypara(enum hdmi_phy_para mode); ++void hdmitx_test_prbs(void); ++void hdmitx_set_div40(bool div40); ++ ++extern void hdmitx_set_drm_pkt(struct master_display_info_s *data); ++bool hdmitx_find_vendor(struct hdmitx_dev *hdev); ++#ifndef CONFIG_AML_HDMITX20 ++void __attribute__((weak))hdmitx_set_drm_pkt(struct master_display_info_s *data) ++{ ++} ++#endif ++ ++void hdmitx_set_vsif_pkt(enum eotf_type type, enum mode_type tunnel_mode, ++ struct dv_vsif_para *data); ++void hdmitx_set_hdr10plus_pkt(unsigned int flag, ++ struct hdr10plus_para *data); ++ ++#ifndef printk ++#define printk printf ++#endif ++#ifndef pr_info ++#define pr_info printf ++#endif ++ ++#define hdmitx_debug() /* printf("hd: %s[%d]\n", __func__, __LINE__) */ ++ ++extern struct hdr_info *hdmitx_get_rx_hdr_info(void); ++#ifndef CONFIG_AML_HDMITX20 ++struct hdr_info * __attribute__((weak))hdmitx_get_rx_hdr_info(void) ++{ ++ return NULL; ++} ++#endif ++ ++#endif +diff --git a/include/amlogic/media/vout/hdmitx/hdmitx_reg.h b/include/amlogic/media/vout/hdmitx/hdmitx_reg.h +new file mode 100644 +index 00000000000..b13e4ab986a +--- /dev/null ++++ b/include/amlogic/media/vout/hdmitx/hdmitx_reg.h +@@ -0,0 +1,1041 @@ ++/* ++ * driver/amlogic/media/vout/hdmitx/hdmitx_reg.h ++ * ++ * Copyright (C) 2018 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++*/ ++ ++#ifndef _HDMI_TX_REG_H ++#define _HDMI_TX_REG_H ++ ++/* TOP-level wrapper registers addresses */ ++/* bit24: 1 means secure access */ ++/* bit28: 1 means DWC, 0 means TOP */ ++#define SEC_OFFSET (0x1UL << 24) ++#define TOP_OFFSET_MASK (0x0UL << 24) ++#define TOP_SEC_OFFSET_MASK ((TOP_OFFSET_MASK) | (SEC_OFFSET)) ++#define DWC_OFFSET_MASK (0x10UL << 24) ++#define DWC_SEC_OFFSET_MASK ((DWC_OFFSET_MASK) | (SEC_OFFSET)) ++ ++/* Bit 7 RW Reserved. Default 1. */ ++/* Bit 6 RW Reserved. Default 1. */ ++/* Bit 5 RW Reserved. Default 1. */ ++/* Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset. ++ * Default 1. ++ * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset; ++ * 0=Release from reset. Default 1. ++ * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset. ++ * Default 1. ++ * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset; ++ * 0=Release from reset. Default 1. ++ * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset; ++ * 0=Release from reset. Default 1. ++ */ ++#define HDMITX_TOP_SW_RESET (TOP_OFFSET_MASK + 0x000) ++ ++/* Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0. */ ++/* Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0. */ ++/* Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0. */ ++/* Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0. */ ++/* Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0. */ ++/* Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. */ ++/* Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0. */ ++/* Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0. */ ++/* Bit 1 RW tmds_clk_en: 1=enable tmds_clk; 0=disable. Default 0. */ ++/* Bit 0 RW pixel_clk_en: 1=enable pixel_clk; 0=disable. Default 0. */ ++#define HDMITX_TOP_CLK_CNTL (TOP_OFFSET_MASK + 0x001) ++ ++/* Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024. Default 0. */ ++/* Bit 15:12 RW hpd_glitch_width: filter out glitch <= N. Default 0. */ ++#define HDMITX_TOP_HPD_FILTER (TOP_OFFSET_MASK + 0x002) ++ ++/* intr_maskn: MASK_N, one bit per interrupt source. ++ * 1=Enable interrupt source; 0=Disable interrupt source. Default 0. ++ * [ 4] hdcp22_rndnum_err ++ * [ 3] nonce_rfrsh_rise ++ * [ 2] hpd_fall_intr ++ * [ 1] hpd_rise_intr ++ * [ 0] core_intr ++ */ ++#define HDMITX_TOP_INTR_MASKN (TOP_OFFSET_MASK + 0x003) ++ ++/* Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt ++ * bit, read back the interrupt status. */ ++/* Bit 31 R IP interrupt status */ ++/* Bit 2 RW hpd_fall */ ++/* Bit 1 RW hpd_rise */ ++/* Bit 0 RW IP interrupt */ ++#define HDMITX_TOP_INTR_STAT (TOP_OFFSET_MASK + 0x004) ++ ++/* [4] hdcp22_rndnum_err */ ++/* [3] nonce_rfrsh_rise */ ++/* [2] hpd_fall */ ++/* [1] hpd_rise */ ++/* [0] core_intr_rise */ ++#define HDMITX_TOP_INTR_STAT_CLR (TOP_OFFSET_MASK + 0x005) ++ ++/* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data; ++ * 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0. ++ * Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern ++ * every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0. ++ * Bit 8 RW shift_pttn_en: 1= Eanble shift pattern generator; 0=Disable. ++ * Default 0. ++ * Bit 4: 3 RW prbs_pttn_mode: 0=PRBS11; 1=PRBS15; 2=PRBS7; 3=PRBS31. Default 0. ++ * Bit 2: 1 RW prbs_pttn_width: 0=idle; 1=output 8-bit pattern; ++ * 2=Output 1-bit pattern; 3=output 10-bit pattern. Default 0. ++ * Bit 0 RW prbs_pttn_en: 1=Enable PRBS generator; 0=Disable. Default 0. ++ */ ++#define HDMITX_TOP_BIST_CNTL (TOP_OFFSET_MASK + 0x006) ++ ++/* Bit 29:20 RW shift_pttn_data[59:50]. Default 0. */ ++/* Bit 19:10 RW shift_pttn_data[69:60]. Default 0. */ ++/* Bit 9: 0 RW shift_pttn_data[79:70]. Default 0. */ ++#define HDMITX_TOP_SHIFT_PTTN_012 (TOP_OFFSET_MASK + 0x007) ++ ++/* Bit 29:20 RW shift_pttn_data[29:20]. Default 0. */ ++/* Bit 19:10 RW shift_pttn_data[39:30]. Default 0. */ ++/* Bit 9: 0 RW shift_pttn_data[49:40]. Default 0. */ ++#define HDMITX_TOP_SHIFT_PTTN_345 (TOP_OFFSET_MASK + 0x008) ++ ++/* Bit 19:10 RW shift_pttn_data[ 9: 0]. Default 0. */ ++/* Bit 9: 0 RW shift_pttn_data[19:10]. Default 0. */ ++#define HDMITX_TOP_SHIFT_PTTN_67 (TOP_OFFSET_MASK + 0x009) ++ ++/* Bit 25:16 RW tmds_clk_pttn[19:10]. Default 0. */ ++/* Bit 9: 0 RW tmds_clk_pttn[ 9: 0]. Default 0. */ ++#define HDMITX_TOP_TMDS_CLK_PTTN_01 (TOP_OFFSET_MASK + 0x00A) ++ ++/* Bit 25:16 RW tmds_clk_pttn[39:30]. Default 0. */ ++/* Bit 9: 0 RW tmds_clk_pttn[29:20]. Default 0. */ ++#define HDMITX_TOP_TMDS_CLK_PTTN_23 (TOP_OFFSET_MASK + 0x00B) ++ ++/* Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern, ++ * used when TMDS CLK rate = TMDS character rate /4. Default 0. ++ * Bit 0 R Reserved. Default 0. ++ */ ++/* [ 1] shift_tmds_clk_pttn */ ++/* [ 0] load_tmds_clk_pttn */ ++#define HDMITX_TOP_TMDS_CLK_PTTN_CNTL (TOP_OFFSET_MASK + 0x00C) ++ ++/* Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM ++ * failure, write 1 to clear the failure flag. Default 0. ++ */ ++#define HDMITX_TOP_REVOCMEM_STAT (TOP_OFFSET_MASK + 0x00D) ++ ++/* Bit 0 R filtered HPD status. */ ++#define HDMITX_TOP_STAT0 (TOP_OFFSET_MASK + 0x00E) ++#define HDMITX_TOP_SKP_CNTL_STAT (TOP_SEC_OFFSET_MASK + 0x010) ++#define HDMITX_TOP_NONCE_0 (TOP_SEC_OFFSET_MASK + 0x011) ++#define HDMITX_TOP_NONCE_1 (TOP_SEC_OFFSET_MASK + 0x012) ++#define HDMITX_TOP_NONCE_2 (TOP_SEC_OFFSET_MASK + 0x013) ++#define HDMITX_TOP_NONCE_3 (TOP_SEC_OFFSET_MASK + 0x014) ++#define HDMITX_TOP_PKF_0 (TOP_SEC_OFFSET_MASK + 0x015) ++#define HDMITX_TOP_PKF_1 (TOP_SEC_OFFSET_MASK + 0x016) ++#define HDMITX_TOP_PKF_2 (TOP_SEC_OFFSET_MASK + 0x017) ++#define HDMITX_TOP_PKF_3 (TOP_SEC_OFFSET_MASK + 0x018) ++#define HDMITX_TOP_DUK_0 (TOP_SEC_OFFSET_MASK + 0x019) ++#define HDMITX_TOP_DUK_1 (TOP_SEC_OFFSET_MASK + 0x01A) ++#define HDMITX_TOP_DUK_2 (TOP_SEC_OFFSET_MASK + 0x01B) ++#define HDMITX_TOP_DUK_3 (TOP_SEC_OFFSET_MASK + 0x01C) ++/* [26:24] infilter_ddc_intern_clk_divide */ ++/* [23:16] infilter_ddc_sample_clk_divide */ ++/* [10: 8] infilter_cec_intern_clk_divide */ ++/* [ 7: 0] infilter_cec_sample_clk_divide */ ++#define HDMITX_TOP_INFILTER (TOP_OFFSET_MASK + 0x01D) ++#define HDMITX_TOP_NSEC_SCRATCH (TOP_OFFSET_MASK + 0x01E) ++#define HDMITX_TOP_SEC_SCRATCH (TOP_SEC_OFFSET_MASK + 0x01F) ++#define HDMITX_TOP_EMP_CNTL0 (TOP_OFFSET_MASK + 0x020) ++#define HDMITX_TOP_EMP_CNTL1 (TOP_OFFSET_MASK + 0x021) ++#define HDMITX_TOP_EMP_MEMADDR_START (TOP_OFFSET_MASK + 0x022) ++#define HDMITX_TOP_EMP_STAT0 (TOP_OFFSET_MASK + 0x023) ++#define HDMITX_TOP_EMP_STAT1 (TOP_OFFSET_MASK + 0x024) ++#define HDMITX_TOP_AXI_ASYNC_CNTL0 (TOP_OFFSET_MASK + 0x025) ++#define HDMITX_TOP_AXI_ASYNC_CNTL1 (TOP_OFFSET_MASK + 0x026) ++#define HDMITX_TOP_AXI_ASYNC_STAT0 (TOP_OFFSET_MASK + 0x027) ++#define HDMITX_TOP_I2C_BUSY_CNT_MAX (TOP_OFFSET_MASK + 0x028) ++#define HDMITX_TOP_I2C_BUSY_CNT_STAT (TOP_OFFSET_MASK + 0x029) ++#define HDMITX_TOP_HDCP22_BSOD (TOP_OFFSET_MASK + 0x02A) ++#define HDMITX_TOP_DDC_CNTL (TOP_OFFSET_MASK + 0x02B) ++#define HDMITX_TOP_REVOCMEM_ADDR_S (TOP_OFFSET_MASK + 0x2000 >> 2) ++#define HDMITX_TOP_REVOCMEM_ADDR_E (TOP_OFFSET_MASK + 0x365E >> 2) ++ ++#define HDMITX_TOP_DONT_TOUCH0 (TOP_OFFSET_MASK + 0x0FE) ++#define HDMITX_TOP_DONT_TOUCH1 (TOP_OFFSET_MASK + 0x0FF) ++ ++/* DWC_HDMI_TX Controller registers addresses */ ++ ++/* Identification Registers */ ++#define HDMITX_DWC_DESIGN_ID (DWC_OFFSET_MASK + 0x0000) ++#define HDMITX_DWC_REVISION_ID (DWC_OFFSET_MASK + 0x0001) ++#define HDMITX_DWC_PRODUCT_ID0 (DWC_OFFSET_MASK + 0x0002) ++#define HDMITX_DWC_PRODUCT_ID1 (DWC_OFFSET_MASK + 0x0003) ++#define HDMITX_DWC_CONFIG0_ID (DWC_OFFSET_MASK + 0x0004) ++#define HDMITX_DWC_CONFIG1_ID (DWC_OFFSET_MASK + 0x0005) ++#define HDMITX_DWC_CONFIG2_ID (DWC_OFFSET_MASK + 0x0006) ++#define HDMITX_DWC_CONFIG3_ID (DWC_OFFSET_MASK + 0x0007) ++ ++/* Interrupt Registers */ ++#define HDMITX_DWC_IH_FC_STAT0 (DWC_OFFSET_MASK + 0x0100) ++#define HDMITX_DWC_IH_FC_STAT1 (DWC_OFFSET_MASK + 0x0101) ++#define HDMITX_DWC_IH_FC_STAT2 (DWC_OFFSET_MASK + 0x0102) ++#define HDMITX_DWC_IH_AS_STAT0 (DWC_OFFSET_MASK + 0x0103) ++#define HDMITX_DWC_IH_PHY_STAT0 (DWC_OFFSET_MASK + 0x0104) ++#define HDMITX_DWC_IH_I2CM_STAT0 (DWC_OFFSET_MASK + 0x0105) ++#define HDMITX_DWC_IH_CEC_STAT0 (DWC_OFFSET_MASK + 0x0106) ++#define HDMITX_DWC_IH_VP_STAT0 (DWC_OFFSET_MASK + 0x0107) ++#define HDMITX_DWC_IH_I2CMPHY_STAT0 (DWC_OFFSET_MASK + 0x0108) ++#define HDMITX_DWC_IH_DECODE (DWC_OFFSET_MASK + 0x0170) ++/* [ 7] mute_AUDI */ ++/* [ 6] mute_ACP */ ++/* [ 5] mute_HBR */ ++/* [ 4] mute_MAS */ ++/* [ 3] mute_NVBI */ ++/* [ 2] mute_AUDS */ ++/* [ 1] mute_ACR */ ++/* [ 0] mute_NULL */ ++#define HDMITX_DWC_IH_MUTE_FC_STAT0 (DWC_OFFSET_MASK + 0x0180) ++/* [ 7] mute_GMD */ ++/* [ 6] mute_ISRC1 */ ++/* [ 5] mute_ISRC2 */ ++/* [ 4] mute_VSD */ ++/* [ 3] mute_SPD */ ++/* [ 2] mute_AMP */ ++/* [ 1] mute_AVI */ ++/* [ 0] mute_GCP */ ++#define HDMITX_DWC_IH_MUTE_FC_STAT1 (DWC_OFFSET_MASK + 0x0181) ++/* [ 1] mute_LowPriority_fifo_full */ ++/* [ 0] mute_HighPriority_fifo_full */ ++#define HDMITX_DWC_IH_MUTE_FC_STAT2 (DWC_OFFSET_MASK + 0x0182) ++/* [ 4] mute_aud_fifo_underrun */ ++/* [ 3] mute_aud_fifo_overrun */ ++/* [ 2] mute_aud_fifo_empty_thr. oififoemptythr tied to 0. */ ++/* [ 1] mute_aud_fifo_empty */ ++/* [ 0] mute_aud_fifo_full */ ++#define HDMITX_DWC_IH_MUTE_AS_STAT0 (DWC_OFFSET_MASK + 0x0183) ++#define HDMITX_DWC_IH_MUTE_PHY_STAT0 (DWC_OFFSET_MASK + 0x0184) ++/* [ 2] mute_scdc_readreq */ ++/* [ 1] mute_edid_i2c_master_done */ ++/* [ 0] mute_edid_i2c_master_error */ ++#define HDMITX_DWC_IH_MUTE_I2CM_STAT0 (DWC_OFFSET_MASK + 0x0185) ++/* [ 6] cec_wakeup */ ++/* [ 5] cec_error_follower */ ++/* [ 4] cec_error_initiator */ ++/* [ 3] cec_arb_lost */ ++/* [ 2] cec_nack */ ++/* [ 1] cec_eom */ ++/* [ 0] cec_done */ ++#define HDMITX_DWC_IH_MUTE_CEC_STAT0 (DWC_OFFSET_MASK + 0x0186) ++#define HDMITX_DWC_IH_MUTE_VP_STAT0 (DWC_OFFSET_MASK + 0x0187) ++#define HDMITX_DWC_IH_MUTE_I2CMPHY_STAT0 (DWC_OFFSET_MASK + 0x0188) ++/* [ 1] mute_wakeup_interrupt */ ++/* [ 0] mute_all_interrupt */ ++#define HDMITX_DWC_IH_MUTE (DWC_OFFSET_MASK + 0x01FF) ++ ++/* Video Sampler Registers */ ++/* [ 7] internal_de_generator */ ++/* [4:0] video_mapping */ ++#define HDMITX_DWC_TX_INVID0 (DWC_OFFSET_MASK + 0x0200) ++/* [ 2] bcbdata_stuffing */ ++/* [ 1] rcrdata_stuffing */ ++/* [ 0] gydata_stuffing */ ++#define HDMITX_DWC_TX_INSTUFFING (DWC_OFFSET_MASK + 0x0201) ++#define HDMITX_DWC_TX_GYDATA0 (DWC_OFFSET_MASK + 0x0202) ++#define HDMITX_DWC_TX_GYDATA1 (DWC_OFFSET_MASK + 0x0203) ++#define HDMITX_DWC_TX_RCRDATA0 (DWC_OFFSET_MASK + 0x0204) ++#define HDMITX_DWC_TX_RCRDATA1 (DWC_OFFSET_MASK + 0x0205) ++#define HDMITX_DWC_TX_BCBDATA0 (DWC_OFFSET_MASK + 0x0206) ++#define HDMITX_DWC_TX_BCBDATA1 (DWC_OFFSET_MASK + 0x0207) ++ ++/* Video Packetizer Registers */ ++#define HDMITX_DWC_VP_STATUS (DWC_OFFSET_MASK + 0x0800) ++/* [3:0] desired_pr_factor */ ++#define HDMITX_DWC_VP_PR_CD (DWC_OFFSET_MASK + 0x0801) ++/* [ 5] default_phase */ ++/* [ 2] ycc422_stuffing */ ++/* [ 1] pp_stuffing */ ++/* [ 0] pr_stuffing */ ++#define HDMITX_DWC_VP_STUFF (DWC_OFFSET_MASK + 0x0802) ++#define HDMITX_DWC_VP_REMAP (DWC_OFFSET_MASK + 0x0803) ++#define HDMITX_DWC_VP_CONF (DWC_OFFSET_MASK + 0x0804) ++/* [ 7] mask_int_full_prpt */ ++/* [ 6] mask_int_empty_prpt */ ++/* [ 5] mask_int_full_ppack */ ++/* [ 4] mask_int_empty_ppack */ ++/* [ 3] mask_int_full_remap */ ++/* [ 2] mask_int_empty_remap */ ++/* [ 1] mask_int_full_byp */ ++/* [ 0] mask_int_empty_byp */ ++#define HDMITX_DWC_VP_MASK (DWC_OFFSET_MASK + 0x0807) ++ ++/* Frmae Composer Registers */ ++/* [ 7] HDCP_keepout */ ++/* [ 6] vs_in_pol: 0=active low; 1=active high. */ ++/* [ 5] hs_in_pol: 0=active low; 1=active high. */ ++/* [ 4] de_in_pol: 0=active low; 1=active high. */ ++/* [ 3] dvi_modez: 0=dvi; 1=hdmi. */ ++/* [ 1] r_v_blank_in_osc */ ++/* [ 0] in_I_P: 0=progressive; 1=interlaced. */ ++#define HDMITX_DWC_FC_INVIDCONF (DWC_OFFSET_MASK + 0x1000) ++/* [7:0] H_in_active[7:0] */ ++#define HDMITX_DWC_FC_INHACTV0 (DWC_OFFSET_MASK + 0x1001) ++/* [5:0] H_in_active[13:8] */ ++#define HDMITX_DWC_FC_INHACTV1 (DWC_OFFSET_MASK + 0x1002) ++/* [7:0] H_in_blank[7:0] */ ++#define HDMITX_DWC_FC_INHBLANK0 (DWC_OFFSET_MASK + 0x1003) ++/* [4:0] H_in_blank[12:8] */ ++#define HDMITX_DWC_FC_INHBLANK1 (DWC_OFFSET_MASK + 0x1004) ++/* [7:0] V_in_active[7:0] */ ++#define HDMITX_DWC_FC_INVACTV0 (DWC_OFFSET_MASK + 0x1005) ++/* [4:0] V_in_active[12:8] */ ++#define HDMITX_DWC_FC_INVACTV1 (DWC_OFFSET_MASK + 0x1006) ++/* [7:0] V_in_blank */ ++#define HDMITX_DWC_FC_INVBLANK (DWC_OFFSET_MASK + 0x1007) ++/* [7:0] H_in_delay[7:0] */ ++#define HDMITX_DWC_FC_HSYNCINDELAY0 (DWC_OFFSET_MASK + 0x1008) ++/* [4:0] H_in_delay[12:8] */ ++#define HDMITX_DWC_FC_HSYNCINDELAY1 (DWC_OFFSET_MASK + 0x1009) ++/* [7:0] H_in_width[7:0] */ ++#define HDMITX_DWC_FC_HSYNCINWIDTH0 (DWC_OFFSET_MASK + 0x100A) ++/* [1:0] H_in_width[9:8] */ ++#define HDMITX_DWC_FC_HSYNCINWIDTH1 (DWC_OFFSET_MASK + 0x100B) ++/* [7:0] V_in_delay */ ++#define HDMITX_DWC_FC_VSYNCINDELAY (DWC_OFFSET_MASK + 0x100C) ++/* [5:0] V_in_width */ ++#define HDMITX_DWC_FC_VSYNCINWIDTH (DWC_OFFSET_MASK + 0x100D) ++#define HDMITX_DWC_FC_INFREQ0 (DWC_OFFSET_MASK + 0x100E) ++#define HDMITX_DWC_FC_INFREQ1 (DWC_OFFSET_MASK + 0x100F) ++#define HDMITX_DWC_FC_INFREQ2 (DWC_OFFSET_MASK + 0x1010) ++#define HDMITX_DWC_FC_CTRLDUR (DWC_OFFSET_MASK + 0x1011) ++#define HDMITX_DWC_FC_EXCTRLDUR (DWC_OFFSET_MASK + 0x1012) ++#define HDMITX_DWC_FC_EXCTRLSPAC (DWC_OFFSET_MASK + 0x1013) ++#define HDMITX_DWC_FC_CH0PREAM (DWC_OFFSET_MASK + 0x1014) ++#define HDMITX_DWC_FC_CH1PREAM (DWC_OFFSET_MASK + 0x1015) ++#define HDMITX_DWC_FC_CH2PREAM (DWC_OFFSET_MASK + 0x1016) ++/* [3:2] YQ */ ++/* [1:0] CN */ ++#define HDMITX_DWC_FC_AVICONF3 (DWC_OFFSET_MASK + 0x1017) ++/* [ 2] default_phase */ ++/* [ 1] set_avmute */ ++/* [ 0] clear_avmute */ ++#define HDMITX_DWC_FC_GCP (DWC_OFFSET_MASK + 0x1018) ++/* [ 7] rgb_ycc_indication[2] */ ++/* [ 6] active_format_present */ ++/* [5:4] scan_information */ ++/* [3:2] bar_information */ ++/* [1:0] rgb_ycc_indication[1:0] */ ++#define HDMITX_DWC_FC_AVICONF0 (DWC_OFFSET_MASK + 0x1019) ++/* [7:6] colorimetry */ ++/* [5:4] picture_aspect_ratio */ ++/* [3:0] active_aspect_ratio */ ++#define HDMITX_DWC_FC_AVICONF1 (DWC_OFFSET_MASK + 0x101A) ++/* [ 7] IT_content */ ++/* [6:4] extended_colorimetry */ ++/* [3:2] quantization_range */ ++/* [1:0] non_uniform_picture_scaling */ ++#define HDMITX_DWC_FC_AVICONF2 (DWC_OFFSET_MASK + 0x101B) ++#define HDMITX_DWC_FC_AVIVID (DWC_OFFSET_MASK + 0x101C) ++#define HDMITX_DWC_FC_AVIETB0 (DWC_OFFSET_MASK + 0x101D) ++#define HDMITX_DWC_FC_AVIETB1 (DWC_OFFSET_MASK + 0x101E) ++#define HDMITX_DWC_FC_AVISBB0 (DWC_OFFSET_MASK + 0x101F) ++#define HDMITX_DWC_FC_AVISBB1 (DWC_OFFSET_MASK + 0x1020) ++#define HDMITX_DWC_FC_AVIELB0 (DWC_OFFSET_MASK + 0x1021) ++#define HDMITX_DWC_FC_AVIELB1 (DWC_OFFSET_MASK + 0x1022) ++#define HDMITX_DWC_FC_AVISRB0 (DWC_OFFSET_MASK + 0x1023) ++#define HDMITX_DWC_FC_AVISRB1 (DWC_OFFSET_MASK + 0x1024) ++/* [3:0] CT: coding type */ ++#define HDMITX_DWC_FC_AUDICONF0 (DWC_OFFSET_MASK + 0x1025) ++/* [5:4] SS: sampling size */ ++/* [2:0] SF: sampling frequency */ ++#define HDMITX_DWC_FC_AUDICONF1 (DWC_OFFSET_MASK + 0x1026) ++/* CA: channel allocation */ ++#define HDMITX_DWC_FC_AUDICONF2 (DWC_OFFSET_MASK + 0x1027) ++/* [6:5] LFEPBL: LFE playback info */ ++/* [ 4] DM_INH: down mix enable */ ++/* [3:0] LSv: Level shift value */ ++#define HDMITX_DWC_FC_AUDICONF3 (DWC_OFFSET_MASK + 0x1028) ++#define HDMITX_DWC_FC_VSDIEEEID0 (DWC_OFFSET_MASK + 0x1029) ++#define HDMITX_DWC_FC_VSDSIZE (DWC_OFFSET_MASK + 0x102A) ++#define HDMITX_DWC_FC_VSDIEEEID1 (DWC_OFFSET_MASK + 0x1030) ++#define HDMITX_DWC_FC_VSDIEEEID2 (DWC_OFFSET_MASK + 0x1031) ++#define HDMITX_DWC_FC_VSDPAYLOAD0 (DWC_OFFSET_MASK + 0x1032) ++#define HDMITX_DWC_FC_VSDPAYLOAD1 (DWC_OFFSET_MASK + 0x1033) ++#define HDMITX_DWC_FC_VSDPAYLOAD2 (DWC_OFFSET_MASK + 0x1034) ++#define HDMITX_DWC_FC_VSDPAYLOAD3 (DWC_OFFSET_MASK + 0x1035) ++#define HDMITX_DWC_FC_VSDPAYLOAD4 (DWC_OFFSET_MASK + 0x1036) ++#define HDMITX_DWC_FC_VSDPAYLOAD5 (DWC_OFFSET_MASK + 0x1037) ++#define HDMITX_DWC_FC_VSDPAYLOAD6 (DWC_OFFSET_MASK + 0x1038) ++#define HDMITX_DWC_FC_VSDPAYLOAD7 (DWC_OFFSET_MASK + 0x1039) ++#define HDMITX_DWC_FC_VSDPAYLOAD8 (DWC_OFFSET_MASK + 0x103A) ++#define HDMITX_DWC_FC_VSDPAYLOAD9 (DWC_OFFSET_MASK + 0x103B) ++#define HDMITX_DWC_FC_VSDPAYLOAD10 (DWC_OFFSET_MASK + 0x103C) ++#define HDMITX_DWC_FC_VSDPAYLOAD11 (DWC_OFFSET_MASK + 0x103D) ++#define HDMITX_DWC_FC_VSDPAYLOAD12 (DWC_OFFSET_MASK + 0x103E) ++#define HDMITX_DWC_FC_VSDPAYLOAD13 (DWC_OFFSET_MASK + 0x103F) ++#define HDMITX_DWC_FC_VSDPAYLOAD14 (DWC_OFFSET_MASK + 0x1040) ++#define HDMITX_DWC_FC_VSDPAYLOAD15 (DWC_OFFSET_MASK + 0x1041) ++#define HDMITX_DWC_FC_VSDPAYLOAD16 (DWC_OFFSET_MASK + 0x1042) ++#define HDMITX_DWC_FC_VSDPAYLOAD17 (DWC_OFFSET_MASK + 0x1043) ++#define HDMITX_DWC_FC_VSDPAYLOAD18 (DWC_OFFSET_MASK + 0x1044) ++#define HDMITX_DWC_FC_VSDPAYLOAD19 (DWC_OFFSET_MASK + 0x1045) ++#define HDMITX_DWC_FC_VSDPAYLOAD20 (DWC_OFFSET_MASK + 0x1046) ++#define HDMITX_DWC_FC_VSDPAYLOAD21 (DWC_OFFSET_MASK + 0x1047) ++#define HDMITX_DWC_FC_VSDPAYLOAD22 (DWC_OFFSET_MASK + 0x1048) ++#define HDMITX_DWC_FC_VSDPAYLOAD23 (DWC_OFFSET_MASK + 0x1049) ++#define HDMITX_DWC_FC_SPDVENDORNAME0 (DWC_OFFSET_MASK + 0x104A) ++#define HDMITX_DWC_FC_SPDVENDORNAME1 (DWC_OFFSET_MASK + 0x104B) ++#define HDMITX_DWC_FC_SPDVENDORNAME2 (DWC_OFFSET_MASK + 0x104C) ++#define HDMITX_DWC_FC_SPDVENDORNAME3 (DWC_OFFSET_MASK + 0x104D) ++#define HDMITX_DWC_FC_SPDVENDORNAME4 (DWC_OFFSET_MASK + 0x104E) ++#define HDMITX_DWC_FC_SPDVENDORNAME5 (DWC_OFFSET_MASK + 0x104F) ++#define HDMITX_DWC_FC_SPDVENDORNAME6 (DWC_OFFSET_MASK + 0x1050) ++#define HDMITX_DWC_FC_SPDVENDORNAME7 (DWC_OFFSET_MASK + 0x1051) ++#define HDMITX_DWC_FC_SDPPRODUCTNAME0 (DWC_OFFSET_MASK + 0x1052) ++#define HDMITX_DWC_FC_SDPPRODUCTNAME1 (DWC_OFFSET_MASK + 0x1053) ++#define HDMITX_DWC_FC_SDPPRODUCTNAME2 (DWC_OFFSET_MASK + 0x1054) ++#define HDMITX_DWC_FC_SDPPRODUCTNAME3 (DWC_OFFSET_MASK + 0x1055) ++#define HDMITX_DWC_FC_SDPPRODUCTNAME4 (DWC_OFFSET_MASK + 0x1056) ++#define HDMITX_DWC_FC_SDPPRODUCTNAME5 (DWC_OFFSET_MASK + 0x1057) ++#define HDMITX_DWC_FC_SDPPRODUCTNAME6 (DWC_OFFSET_MASK + 0x1058) ++#define HDMITX_DWC_FC_SDPPRODUCTNAME7 (DWC_OFFSET_MASK + 0x1059) ++#define HDMITX_DWC_FC_SDPPRODUCTNAME8 (DWC_OFFSET_MASK + 0x105A) ++#define HDMITX_DWC_FC_SDPPRODUCTNAME9 (DWC_OFFSET_MASK + 0x105B) ++#define HDMITX_DWC_FC_SDPPRODUCTNAME10 (DWC_OFFSET_MASK + 0x105C) ++#define HDMITX_DWC_FC_SDPPRODUCTNAME11 (DWC_OFFSET_MASK + 0x105D) ++#define HDMITX_DWC_FC_SDPPRODUCTNAME12 (DWC_OFFSET_MASK + 0x105E) ++#define HDMITX_DWC_FC_SDPPRODUCTNAME13 (DWC_OFFSET_MASK + 0x105F) ++#define HDMITX_DWC_FC_SDPPRODUCTNAME14 (DWC_OFFSET_MASK + 0x1060) ++#define HDMITX_DWC_FC_SPDPRODUCTNAME15 (DWC_OFFSET_MASK + 0x1061) ++#define HDMITX_DWC_FC_SPDDEVICEINF (DWC_OFFSET_MASK + 0x1062) ++/* [7:4] aud_packet_sampflat */ ++/* [ 0] aud_packet_layout */ ++#define HDMITX_DWC_FC_AUDSCONF (DWC_OFFSET_MASK + 0x1063) ++#define HDMITX_DWC_FC_AUDSSTAT (DWC_OFFSET_MASK + 0x1064) ++/* [ 7] V3r */ ++/* [ 6] V2r */ ++/* [ 5] V1r */ ++/* [ 4] V0r */ ++/* [ 3] V3l */ ++/* [ 2] V2l */ ++/* [ 1] V1l */ ++/* [ 0] V0l */ ++#define HDMITX_DWC_FC_AUDSV (DWC_OFFSET_MASK + 0x1065) ++#define HDMITX_DWC_FC_AUDSU (DWC_OFFSET_MASK + 0x1066) ++#define HDMITX_DWC_FC_AUDSCHNLS0 (DWC_OFFSET_MASK + 0x1067) ++#define HDMITX_DWC_FC_AUDSCHNLS1 (DWC_OFFSET_MASK + 0x1068) ++#define HDMITX_DWC_FC_AUDSCHNLS2 (DWC_OFFSET_MASK + 0x1069) ++#define HDMITX_DWC_FC_AUDSCHNLS3 (DWC_OFFSET_MASK + 0x106A) ++#define HDMITX_DWC_FC_AUDSCHNLS4 (DWC_OFFSET_MASK + 0x106B) ++#define HDMITX_DWC_FC_AUDSCHNLS5 (DWC_OFFSET_MASK + 0x106C) ++#define HDMITX_DWC_FC_AUDSCHNLS6 (DWC_OFFSET_MASK + 0x106D) ++#define HDMITX_DWC_FC_AUDSCHNLS7 (DWC_OFFSET_MASK + 0x106E) ++#define HDMITX_DWC_FC_AUDSCHNLS8 (DWC_OFFSET_MASK + 0x106F) ++#define HDMITX_DWC_FC_DATACH0FILL (DWC_OFFSET_MASK + 0x1070) ++#define HDMITX_DWC_FC_DATACH1FILL (DWC_OFFSET_MASK + 0x1071) ++#define HDMITX_DWC_FC_DATACH2FILL (DWC_OFFSET_MASK + 0x1072) ++#define HDMITX_DWC_FC_CTRLQHIGH (DWC_OFFSET_MASK + 0x1073) ++#define HDMITX_DWC_FC_CTRLQLOW (DWC_OFFSET_MASK + 0x1074) ++#define HDMITX_DWC_FC_ACP0 (DWC_OFFSET_MASK + 0x1075) ++#define HDMITX_DWC_FC_ACP16 (DWC_OFFSET_MASK + 0x1082) ++#define HDMITX_DWC_FC_ACP15 (DWC_OFFSET_MASK + 0x1083) ++#define HDMITX_DWC_FC_ACP14 (DWC_OFFSET_MASK + 0x1084) ++#define HDMITX_DWC_FC_ACP13 (DWC_OFFSET_MASK + 0x1085) ++#define HDMITX_DWC_FC_ACP12 (DWC_OFFSET_MASK + 0x1086) ++#define HDMITX_DWC_FC_ACP11 (DWC_OFFSET_MASK + 0x1087) ++#define HDMITX_DWC_FC_ACP10 (DWC_OFFSET_MASK + 0x1088) ++#define HDMITX_DWC_FC_ACP9 (DWC_OFFSET_MASK + 0x1089) ++#define HDMITX_DWC_FC_ACP8 (DWC_OFFSET_MASK + 0x108A) ++#define HDMITX_DWC_FC_ACP7 (DWC_OFFSET_MASK + 0x108B) ++#define HDMITX_DWC_FC_ACP6 (DWC_OFFSET_MASK + 0x108C) ++#define HDMITX_DWC_FC_ACP5 (DWC_OFFSET_MASK + 0x108D) ++#define HDMITX_DWC_FC_ACP4 (DWC_OFFSET_MASK + 0x108E) ++#define HDMITX_DWC_FC_ACP3 (DWC_OFFSET_MASK + 0x108F) ++#define HDMITX_DWC_FC_ACP2 (DWC_OFFSET_MASK + 0x1090) ++#define HDMITX_DWC_FC_ACP1 (DWC_OFFSET_MASK + 0x1091) ++#define HDMITX_DWC_FC_ISCR1_0 (DWC_OFFSET_MASK + 0x1092) ++#define HDMITX_DWC_FC_ISCR1_16 (DWC_OFFSET_MASK + 0x1093) ++#define HDMITX_DWC_FC_ISCR1_15 (DWC_OFFSET_MASK + 0x1094) ++#define HDMITX_DWC_FC_ISCR1_14 (DWC_OFFSET_MASK + 0x1095) ++#define HDMITX_DWC_FC_ISCR1_13 (DWC_OFFSET_MASK + 0x1096) ++#define HDMITX_DWC_FC_ISCR1_12 (DWC_OFFSET_MASK + 0x1097) ++#define HDMITX_DWC_FC_ISCR1_11 (DWC_OFFSET_MASK + 0x1098) ++#define HDMITX_DWC_FC_ISCR1_10 (DWC_OFFSET_MASK + 0x1099) ++#define HDMITX_DWC_FC_ISCR1_9 (DWC_OFFSET_MASK + 0x109A) ++#define HDMITX_DWC_FC_ISCR1_8 (DWC_OFFSET_MASK + 0x109B) ++#define HDMITX_DWC_FC_ISCR1_7 (DWC_OFFSET_MASK + 0x109C) ++#define HDMITX_DWC_FC_ISCR1_6 (DWC_OFFSET_MASK + 0x109D) ++#define HDMITX_DWC_FC_ISCR1_5 (DWC_OFFSET_MASK + 0x109E) ++#define HDMITX_DWC_FC_ISCR1_4 (DWC_OFFSET_MASK + 0x109F) ++#define HDMITX_DWC_FC_ISCR1_3 (DWC_OFFSET_MASK + 0x10A0) ++#define HDMITX_DWC_FC_ISCR1_2 (DWC_OFFSET_MASK + 0x10A1) ++#define HDMITX_DWC_FC_ISCR1_1 (DWC_OFFSET_MASK + 0x10A2) ++#define HDMITX_DWC_FC_ISCR0_15 (DWC_OFFSET_MASK + 0x10A3) ++#define HDMITX_DWC_FC_ISCR0_14 (DWC_OFFSET_MASK + 0x10A4) ++#define HDMITX_DWC_FC_ISCR0_13 (DWC_OFFSET_MASK + 0x10A5) ++#define HDMITX_DWC_FC_ISCR0_12 (DWC_OFFSET_MASK + 0x10A6) ++#define HDMITX_DWC_FC_ISCR0_11 (DWC_OFFSET_MASK + 0x10A7) ++#define HDMITX_DWC_FC_ISCR0_10 (DWC_OFFSET_MASK + 0x10A8) ++#define HDMITX_DWC_FC_ISCR0_9 (DWC_OFFSET_MASK + 0x10A9) ++#define HDMITX_DWC_FC_ISCR0_8 (DWC_OFFSET_MASK + 0x10AA) ++#define HDMITX_DWC_FC_ISCR0_7 (DWC_OFFSET_MASK + 0x10AB) ++#define HDMITX_DWC_FC_ISCR0_6 (DWC_OFFSET_MASK + 0x10AC) ++#define HDMITX_DWC_FC_ISCR0_5 (DWC_OFFSET_MASK + 0x10AD) ++#define HDMITX_DWC_FC_ISCR0_4 (DWC_OFFSET_MASK + 0x10AE) ++#define HDMITX_DWC_FC_ISCR0_3 (DWC_OFFSET_MASK + 0x10AF) ++#define HDMITX_DWC_FC_ISCR0_2 (DWC_OFFSET_MASK + 0x10B0) ++#define HDMITX_DWC_FC_ISCR0_1 (DWC_OFFSET_MASK + 0x10B1) ++#define HDMITX_DWC_FC_ISCR0_0 (DWC_OFFSET_MASK + 0x10B2) ++/* [ 4] spd_auto */ ++/* [ 3] vsd_auto */ ++/* [ 2] isrc2_auto */ ++/* [ 1] isrc1_auto */ ++/* [ 0] acp_auto */ ++#define HDMITX_DWC_FC_DATAUTO0 (DWC_OFFSET_MASK + 0x10B3) ++#define HDMITX_DWC_FC_DATAUTO1 (DWC_OFFSET_MASK + 0x10B4) ++#define HDMITX_DWC_FC_DATAUTO2 (DWC_OFFSET_MASK + 0x10B5) ++#define HDMITX_DWC_FC_DATMAN (DWC_OFFSET_MASK + 0x10B6) ++/* [ 5] nvbi_auto: insert on Vsync */ ++/* [ 4] amp_auto: insert on Vsync */ ++/* [ 3] avi_auto: insert on Vsync */ ++/* [ 2] gcp_auto: insert on Vsync */ ++/* [ 1] audi_auto: insert on Vsync */ ++/* [ 0] acr_auto: insert on CTS update. Assert this bit later to avoid ++ * inital packets with false CTS value ++ */ ++#define HDMITX_DWC_FC_DATAUTO3 (DWC_OFFSET_MASK + 0x10B7) ++#define HDMITX_DWC_FC_RDRB0 (DWC_OFFSET_MASK + 0x10B8) ++#define HDMITX_DWC_FC_RDRB1 (DWC_OFFSET_MASK + 0x10B9) ++#define HDMITX_DWC_FC_RDRB2 (DWC_OFFSET_MASK + 0x10BA) ++#define HDMITX_DWC_FC_RDRB3 (DWC_OFFSET_MASK + 0x10BB) ++#define HDMITX_DWC_FC_RDRB4 (DWC_OFFSET_MASK + 0x10BC) ++#define HDMITX_DWC_FC_RDRB5 (DWC_OFFSET_MASK + 0x10BD) ++#define HDMITX_DWC_FC_RDRB6 (DWC_OFFSET_MASK + 0x10BE) ++#define HDMITX_DWC_FC_RDRB7 (DWC_OFFSET_MASK + 0x10BF) ++#define HDMITX_DWC_FC_RDRB8 (DWC_OFFSET_MASK + 0x10C0) ++#define HDMITX_DWC_FC_RDRB9 (DWC_OFFSET_MASK + 0x10C1) ++#define HDMITX_DWC_FC_RDRB10 (DWC_OFFSET_MASK + 0x10C2) ++#define HDMITX_DWC_FC_RDRB11 (DWC_OFFSET_MASK + 0x10C3) ++/* [ 7] AUDI_int_mask */ ++/* [ 6] ACP_int_mask */ ++/* [ 5] HBR_int_mask */ ++/* [ 2] AUDS_int_mask */ ++/* [ 1] ACR_int_mask */ ++/* [ 0] NULL_int_mask */ ++#define HDMITX_DWC_FC_MASK0 (DWC_OFFSET_MASK + 0x10D2) ++/* [ 7] GMD_int_mask */ ++/* [ 6] ISRC1_int_mask */ ++/* [ 5] ISRC2_int_mask */ ++/* [ 4] VSD_int_mask */ ++/* [ 3] SPD_int_mask */ ++/* [ 1] AVI_int_mask */ ++/* [ 0] GCP_int_mask */ ++#define HDMITX_DWC_FC_MASK1 (DWC_OFFSET_MASK + 0x10D6) ++/* [ 1] LowPriority_fifo_full */ ++/* [ 0] HighPriority_fifo_full */ ++#define HDMITX_DWC_FC_MASK2 (DWC_OFFSET_MASK + 0x10DA) ++/* [7:4] incoming_pr_factor */ ++/* [3:0] output_pr_factor */ ++#define HDMITX_DWC_FC_PRCONF (DWC_OFFSET_MASK + 0x10E0) ++/* [ 4] scrambler_ucp_line */ ++/* [ 0] scrambler_en. Only update this bit once we've sent SCDC message*/ ++#define HDMITX_DWC_FC_SCRAMBLER_CTRL (DWC_OFFSET_MASK + 0x10E1) ++#define HDMITX_DWC_FC_MULTISTREAM_CTRL (DWC_OFFSET_MASK + 0x10E2) ++/* [ 6] nvbi_tx_en */ ++/* [ 5] amp_tx_en */ ++/* [ 4] aut_tx_en */ ++/* [ 3] audi_tx_en */ ++/* [ 2] avi_tx_en */ ++/* [ 1] gcp_tx_en */ ++/* [ 0] acr_tx_en */ ++#define HDMITX_DWC_FC_PACKET_TX_EN (DWC_OFFSET_MASK + 0x10E3) ++/* [ 1] actspc_hdlr_tgl */ ++/* [ 0] actspc_hdlr_en */ ++#define HDMITX_DWC_FC_ACTSPC_HDLR_CFG (DWC_OFFSET_MASK + 0x10E8) ++#define HDMITX_DWC_FC_INVACT_2D_0 (DWC_OFFSET_MASK + 0x10E9) ++/* [3:0] fc_invact_2d_0[11:8] */ ++/* [7:0] fc_invact_2d_0[7:0] */ ++#define HDMITX_DWC_FC_INVACT_2D_1 (DWC_OFFSET_MASK + 0x10EA) ++ ++#define HDMITX_DWC_FC_GMD_STAT (DWC_OFFSET_MASK + 0x1100) ++#define HDMITX_DWC_FC_GMD_EN (DWC_OFFSET_MASK + 0x1101) ++#define HDMITX_DWC_FC_GMD_UP (DWC_OFFSET_MASK + 0x1102) ++#define HDMITX_DWC_FC_GMD_CONF (DWC_OFFSET_MASK + 0x1103) ++#define HDMITX_DWC_FC_GMD_HB (DWC_OFFSET_MASK + 0x1104) ++#define HDMITX_DWC_FC_GMD_PB0 (DWC_OFFSET_MASK + 0x1105) ++#define HDMITX_DWC_FC_GMD_PB1 (DWC_OFFSET_MASK + 0x1106) ++#define HDMITX_DWC_FC_GMD_PB2 (DWC_OFFSET_MASK + 0x1107) ++#define HDMITX_DWC_FC_GMD_PB3 (DWC_OFFSET_MASK + 0x1108) ++#define HDMITX_DWC_FC_GMD_PB4 (DWC_OFFSET_MASK + 0x1109) ++#define HDMITX_DWC_FC_GMD_PB5 (DWC_OFFSET_MASK + 0x110A) ++#define HDMITX_DWC_FC_GMD_PB6 (DWC_OFFSET_MASK + 0x110B) ++#define HDMITX_DWC_FC_GMD_PB7 (DWC_OFFSET_MASK + 0x110C) ++#define HDMITX_DWC_FC_GMD_PB8 (DWC_OFFSET_MASK + 0x110D) ++#define HDMITX_DWC_FC_GMD_PB9 (DWC_OFFSET_MASK + 0x110E) ++#define HDMITX_DWC_FC_GMD_PB10 (DWC_OFFSET_MASK + 0x110F) ++#define HDMITX_DWC_FC_GMD_PB11 (DWC_OFFSET_MASK + 0x1110) ++#define HDMITX_DWC_FC_GMD_PB12 (DWC_OFFSET_MASK + 0x1111) ++#define HDMITX_DWC_FC_GMD_PB13 (DWC_OFFSET_MASK + 0x1112) ++#define HDMITX_DWC_FC_GMD_PB14 (DWC_OFFSET_MASK + 0x1113) ++#define HDMITX_DWC_FC_GMD_PB15 (DWC_OFFSET_MASK + 0x1114) ++#define HDMITX_DWC_FC_GMD_PB16 (DWC_OFFSET_MASK + 0x1115) ++#define HDMITX_DWC_FC_GMD_PB17 (DWC_OFFSET_MASK + 0x1116) ++#define HDMITX_DWC_FC_GMD_PB18 (DWC_OFFSET_MASK + 0x1117) ++#define HDMITX_DWC_FC_GMD_PB19 (DWC_OFFSET_MASK + 0x1118) ++#define HDMITX_DWC_FC_GMD_PB20 (DWC_OFFSET_MASK + 0x1119) ++#define HDMITX_DWC_FC_GMD_PB21 (DWC_OFFSET_MASK + 0x111A) ++#define HDMITX_DWC_FC_GMD_PB22 (DWC_OFFSET_MASK + 0x111B) ++#define HDMITX_DWC_FC_GMD_PB23 (DWC_OFFSET_MASK + 0x111C) ++#define HDMITX_DWC_FC_GMD_PB24 (DWC_OFFSET_MASK + 0x111D) ++#define HDMITX_DWC_FC_GMD_PB25 (DWC_OFFSET_MASK + 0x111E) ++#define HDMITX_DWC_FC_GMD_PB26 (DWC_OFFSET_MASK + 0x111F) ++#define HDMITX_DWC_FC_GMD_PB27 (DWC_OFFSET_MASK + 0x1120) ++ ++/* Audio Metadata Packet Registers */ ++#define HDMITX_DWC_FC_AMP_HB01 (DWC_OFFSET_MASK + 0x1128) ++#define HDMITX_DWC_FC_AMP_HB02 (DWC_OFFSET_MASK + 0x1129) ++#define HDMITX_DWC_FC_AMP_PB00 (DWC_OFFSET_MASK + 0x112A) ++#define HDMITX_DWC_FC_AMP_PB01 (DWC_OFFSET_MASK + 0x112B) ++#define HDMITX_DWC_FC_AMP_PB02 (DWC_OFFSET_MASK + 0x112C) ++#define HDMITX_DWC_FC_AMP_PB03 (DWC_OFFSET_MASK + 0x112D) ++#define HDMITX_DWC_FC_AMP_PB04 (DWC_OFFSET_MASK + 0x112E) ++#define HDMITX_DWC_FC_AMP_PB05 (DWC_OFFSET_MASK + 0x112F) ++#define HDMITX_DWC_FC_AMP_PB06 (DWC_OFFSET_MASK + 0x1130) ++#define HDMITX_DWC_FC_AMP_PB07 (DWC_OFFSET_MASK + 0x1131) ++#define HDMITX_DWC_FC_AMP_PB08 (DWC_OFFSET_MASK + 0x1132) ++#define HDMITX_DWC_FC_AMP_PB09 (DWC_OFFSET_MASK + 0x1133) ++#define HDMITX_DWC_FC_AMP_PB10 (DWC_OFFSET_MASK + 0x1134) ++#define HDMITX_DWC_FC_AMP_PB11 (DWC_OFFSET_MASK + 0x1135) ++#define HDMITX_DWC_FC_AMP_PB12 (DWC_OFFSET_MASK + 0x1136) ++#define HDMITX_DWC_FC_AMP_PB13 (DWC_OFFSET_MASK + 0x1137) ++#define HDMITX_DWC_FC_AMP_PB14 (DWC_OFFSET_MASK + 0x1138) ++#define HDMITX_DWC_FC_AMP_PB15 (DWC_OFFSET_MASK + 0x1139) ++#define HDMITX_DWC_FC_AMP_PB16 (DWC_OFFSET_MASK + 0x113A) ++#define HDMITX_DWC_FC_AMP_PB17 (DWC_OFFSET_MASK + 0x113B) ++#define HDMITX_DWC_FC_AMP_PB18 (DWC_OFFSET_MASK + 0x113C) ++#define HDMITX_DWC_FC_AMP_PB19 (DWC_OFFSET_MASK + 0x113D) ++#define HDMITX_DWC_FC_AMP_PB20 (DWC_OFFSET_MASK + 0x113E) ++#define HDMITX_DWC_FC_AMP_PB21 (DWC_OFFSET_MASK + 0x113F) ++#define HDMITX_DWC_FC_AMP_PB22 (DWC_OFFSET_MASK + 0x1140) ++#define HDMITX_DWC_FC_AMP_PB23 (DWC_OFFSET_MASK + 0x1141) ++#define HDMITX_DWC_FC_AMP_PB24 (DWC_OFFSET_MASK + 0x1142) ++#define HDMITX_DWC_FC_AMP_PB25 (DWC_OFFSET_MASK + 0x1143) ++#define HDMITX_DWC_FC_AMP_PB26 (DWC_OFFSET_MASK + 0x1144) ++#define HDMITX_DWC_FC_AMP_PB27 (DWC_OFFSET_MASK + 0x1145) ++ ++/* NTSC VBI Packet Registers */ ++#define HDMITX_DWC_FC_NVBI_HB01 (DWC_OFFSET_MASK + 0x1148) ++#define HDMITX_DWC_FC_NVBI_HB02 (DWC_OFFSET_MASK + 0x1149) ++#define HDMITX_DWC_FC_NVBI_PB01 (DWC_OFFSET_MASK + 0x114A) ++#define HDMITX_DWC_FC_NVBI_PB02 (DWC_OFFSET_MASK + 0x114B) ++#define HDMITX_DWC_FC_NVBI_PB03 (DWC_OFFSET_MASK + 0x114C) ++#define HDMITX_DWC_FC_NVBI_PB04 (DWC_OFFSET_MASK + 0x114D) ++#define HDMITX_DWC_FC_NVBI_PB05 (DWC_OFFSET_MASK + 0x114E) ++#define HDMITX_DWC_FC_NVBI_PB06 (DWC_OFFSET_MASK + 0x114F) ++#define HDMITX_DWC_FC_NVBI_PB07 (DWC_OFFSET_MASK + 0x1150) ++#define HDMITX_DWC_FC_NVBI_PB08 (DWC_OFFSET_MASK + 0x1151) ++#define HDMITX_DWC_FC_NVBI_PB09 (DWC_OFFSET_MASK + 0x1152) ++#define HDMITX_DWC_FC_NVBI_PB10 (DWC_OFFSET_MASK + 0x1153) ++#define HDMITX_DWC_FC_NVBI_PB11 (DWC_OFFSET_MASK + 0x1154) ++#define HDMITX_DWC_FC_NVBI_PB12 (DWC_OFFSET_MASK + 0x1155) ++#define HDMITX_DWC_FC_NVBI_PB13 (DWC_OFFSET_MASK + 0x1156) ++#define HDMITX_DWC_FC_NVBI_PB14 (DWC_OFFSET_MASK + 0x1157) ++#define HDMITX_DWC_FC_NVBI_PB15 (DWC_OFFSET_MASK + 0x1158) ++#define HDMITX_DWC_FC_NVBI_PB16 (DWC_OFFSET_MASK + 0x1159) ++#define HDMITX_DWC_FC_NVBI_PB17 (DWC_OFFSET_MASK + 0x115A) ++#define HDMITX_DWC_FC_NVBI_PB18 (DWC_OFFSET_MASK + 0x115B) ++#define HDMITX_DWC_FC_NVBI_PB19 (DWC_OFFSET_MASK + 0x115C) ++#define HDMITX_DWC_FC_NVBI_PB20 (DWC_OFFSET_MASK + 0x115D) ++#define HDMITX_DWC_FC_NVBI_PB21 (DWC_OFFSET_MASK + 0x115E) ++#define HDMITX_DWC_FC_NVBI_PB22 (DWC_OFFSET_MASK + 0x115F) ++#define HDMITX_DWC_FC_NVBI_PB23 (DWC_OFFSET_MASK + 0x1160) ++#define HDMITX_DWC_FC_NVBI_PB24 (DWC_OFFSET_MASK + 0x1161) ++#define HDMITX_DWC_FC_NVBI_PB25 (DWC_OFFSET_MASK + 0x1162) ++#define HDMITX_DWC_FC_NVBI_PB26 (DWC_OFFSET_MASK + 0x1163) ++#define HDMITX_DWC_FC_NVBI_PB27 (DWC_OFFSET_MASK + 0x1164) ++#define HDMITX_DWC_FC_DRM_HB01 (DWC_OFFSET_MASK + 0x1168) ++#define HDMITX_DWC_FC_DRM_HB02 (DWC_OFFSET_MASK + 0x1169) ++#define HDMITX_DWC_FC_DRM_PB00 (DWC_OFFSET_MASK + 0x116A) ++#define HDMITX_DWC_FC_DRM_PB01 (DWC_OFFSET_MASK + 0x116B) ++#define HDMITX_DWC_FC_DRM_PB02 (DWC_OFFSET_MASK + 0x116C) ++#define HDMITX_DWC_FC_DRM_PB03 (DWC_OFFSET_MASK + 0x116D) ++#define HDMITX_DWC_FC_DRM_PB04 (DWC_OFFSET_MASK + 0x116E) ++#define HDMITX_DWC_FC_DRM_PB05 (DWC_OFFSET_MASK + 0x116F) ++#define HDMITX_DWC_FC_DRM_PB06 (DWC_OFFSET_MASK + 0x1170) ++#define HDMITX_DWC_FC_DRM_PB07 (DWC_OFFSET_MASK + 0x1171) ++#define HDMITX_DWC_FC_DRM_PB08 (DWC_OFFSET_MASK + 0x1172) ++#define HDMITX_DWC_FC_DRM_PB09 (DWC_OFFSET_MASK + 0x1173) ++#define HDMITX_DWC_FC_DRM_PB10 (DWC_OFFSET_MASK + 0x1174) ++#define HDMITX_DWC_FC_DRM_PB11 (DWC_OFFSET_MASK + 0x1175) ++#define HDMITX_DWC_FC_DRM_PB12 (DWC_OFFSET_MASK + 0x1176) ++#define HDMITX_DWC_FC_DRM_PB13 (DWC_OFFSET_MASK + 0x1177) ++#define HDMITX_DWC_FC_DRM_PB14 (DWC_OFFSET_MASK + 0x1178) ++#define HDMITX_DWC_FC_DRM_PB15 (DWC_OFFSET_MASK + 0x1179) ++#define HDMITX_DWC_FC_DRM_PB16 (DWC_OFFSET_MASK + 0x117A) ++#define HDMITX_DWC_FC_DRM_PB17 (DWC_OFFSET_MASK + 0x117B) ++#define HDMITX_DWC_FC_DRM_PB18 (DWC_OFFSET_MASK + 0x117C) ++#define HDMITX_DWC_FC_DRM_PB19 (DWC_OFFSET_MASK + 0x117D) ++#define HDMITX_DWC_FC_DRM_PB20 (DWC_OFFSET_MASK + 0x117E) ++#define HDMITX_DWC_FC_DRM_PB21 (DWC_OFFSET_MASK + 0x117F) ++#define HDMITX_DWC_FC_DRM_PB22 (DWC_OFFSET_MASK + 0x1180) ++#define HDMITX_DWC_FC_DRM_PB23 (DWC_OFFSET_MASK + 0x1181) ++#define HDMITX_DWC_FC_DRM_PB24 (DWC_OFFSET_MASK + 0x1182) ++#define HDMITX_DWC_FC_DRM_PB25 (DWC_OFFSET_MASK + 0x1183) ++#define HDMITX_DWC_FC_DRM_PB26 (DWC_OFFSET_MASK + 0x1184) ++ ++#define HDMITX_DWC_FC_DBGFORCE (DWC_OFFSET_MASK + 0x1200) ++#define HDMITX_DWC_FC_DBGAUD0CH0 (DWC_OFFSET_MASK + 0x1201) ++#define HDMITX_DWC_FC_DBGAUD1CH0 (DWC_OFFSET_MASK + 0x1202) ++#define HDMITX_DWC_FC_DBGAUD2CH0 (DWC_OFFSET_MASK + 0x1203) ++#define HDMITX_DWC_FC_DBGAUD0CH1 (DWC_OFFSET_MASK + 0x1204) ++#define HDMITX_DWC_FC_DBGAUD1CH1 (DWC_OFFSET_MASK + 0x1205) ++#define HDMITX_DWC_FC_DBGAUD2CH1 (DWC_OFFSET_MASK + 0x1206) ++#define HDMITX_DWC_FC_DBGAUD0CH2 (DWC_OFFSET_MASK + 0x1207) ++#define HDMITX_DWC_FC_DBGAUD1CH2 (DWC_OFFSET_MASK + 0x1208) ++#define HDMITX_DWC_FC_DBGAUD2CH2 (DWC_OFFSET_MASK + 0x1209) ++#define HDMITX_DWC_FC_DBGAUD0CH3 (DWC_OFFSET_MASK + 0x120A) ++#define HDMITX_DWC_FC_DBGAUD1CH3 (DWC_OFFSET_MASK + 0x120B) ++#define HDMITX_DWC_FC_DBGAUD2CH3 (DWC_OFFSET_MASK + 0x120C) ++#define HDMITX_DWC_FC_DBGAUD0CH4 (DWC_OFFSET_MASK + 0x120D) ++#define HDMITX_DWC_FC_DBGAUD1CH4 (DWC_OFFSET_MASK + 0x120E) ++#define HDMITX_DWC_FC_DBGAUD2CH4 (DWC_OFFSET_MASK + 0x120F) ++#define HDMITX_DWC_FC_DBGAUD0CH5 (DWC_OFFSET_MASK + 0x1210) ++#define HDMITX_DWC_FC_DBGAUD1CH5 (DWC_OFFSET_MASK + 0x1211) ++#define HDMITX_DWC_FC_DBGAUD2CH5 (DWC_OFFSET_MASK + 0x1212) ++#define HDMITX_DWC_FC_DBGAUD0CH6 (DWC_OFFSET_MASK + 0x1213) ++#define HDMITX_DWC_FC_DBGAUD1CH6 (DWC_OFFSET_MASK + 0x1214) ++#define HDMITX_DWC_FC_DBGAUD2CH6 (DWC_OFFSET_MASK + 0x1215) ++#define HDMITX_DWC_FC_DBGAUD0CH7 (DWC_OFFSET_MASK + 0x1216) ++#define HDMITX_DWC_FC_DBGAUD1CH7 (DWC_OFFSET_MASK + 0x1217) ++#define HDMITX_DWC_FC_DBGAUD2CH7 (DWC_OFFSET_MASK + 0x1218) ++#define HDMITX_DWC_FC_DBGTMDS0 (DWC_OFFSET_MASK + 0x1219) ++#define HDMITX_DWC_FC_DBGTMDS1 (DWC_OFFSET_MASK + 0x121A) ++#define HDMITX_DWC_FC_DBGTMDS2 (DWC_OFFSET_MASK + 0x121B) ++ ++/* HDMI Source PHY Registers */ ++#define HDMITX_DWC_PHY_CONF0 (DWC_OFFSET_MASK + 0x3000) ++#define HDMITX_DWC_PHY_TST0 (DWC_OFFSET_MASK + 0x3001) ++#define HDMITX_DWC_PHY_TST1 (DWC_OFFSET_MASK + 0x3002) ++#define HDMITX_DWC_PHY_TST2 (DWC_OFFSET_MASK + 0x3003) ++#define HDMITX_DWC_PHY_STAT0 (DWC_OFFSET_MASK + 0x3004) ++#define HDMITX_DWC_PHY_INT0 (DWC_OFFSET_MASK + 0x3005) ++#define HDMITX_DWC_PHY_MASK0 (DWC_OFFSET_MASK + 0x3006) ++#define HDMITX_DWC_PHY_POL0 (DWC_OFFSET_MASK + 0x3007) ++ ++/* I2C Master PHY Registers */ ++#define HDMITX_DWC_I2CM_PHY_SLAVE (DWC_OFFSET_MASK + 0x3020) ++#define HDMITX_DWC_I2CM_PHY_ADDRESS (DWC_OFFSET_MASK + 0x3021) ++#define HDMITX_DWC_I2CM_PHY_DATAO_1 (DWC_OFFSET_MASK + 0x3022) ++#define HDMITX_DWC_I2CM_PHY_DATAO_0 (DWC_OFFSET_MASK + 0x3023) ++#define HDMITX_DWC_I2CM_PHY_DATAI_1 (DWC_OFFSET_MASK + 0x3024) ++#define HDMITX_DWC_I2CM_PHY_DATAI_0 (DWC_OFFSET_MASK + 0x3025) ++#define HDMITX_DWC_I2CM_PHY_OPERATION (DWC_OFFSET_MASK + 0x3026) ++#define HDMITX_DWC_I2CM_PHY_INT (DWC_OFFSET_MASK + 0x3027) ++#define HDMITX_DWC_I2CM_PHY_CTLINT (DWC_OFFSET_MASK + 0x3028) ++#define HDMITX_DWC_I2CM_PHY_DIV (DWC_OFFSET_MASK + 0x3029) ++#define HDMITX_DWC_I2CM_PHY_SOFTRSTZ (DWC_OFFSET_MASK + 0x302A) ++#define HDMITX_DWC_I2CM_PHY_SS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x302B) ++#define HDMITX_DWC_I2CM_PHY_SS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x302C) ++#define HDMITX_DWC_I2CM_PHY_SS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x302D) ++#define HDMITX_DWC_I2CM_PHY_SS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x302E) ++#define HDMITX_DWC_I2CM_PHY_FS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x302F) ++#define HDMITX_DWC_I2CM_PHY_FS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x3030) ++#define HDMITX_DWC_I2CM_PHY_FS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x3031) ++#define HDMITX_DWC_I2CM_PHY_FS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x3032) ++#define HDMITX_DWC_I2CM_PHY_SDA_HOLD (DWC_OFFSET_MASK + 0x3033) ++ ++/* Audio Sampler Registers */ ++ ++ /* [ 7] sw_audio_fifo_rst */ ++ /* [ 5] 0=select SPDIF; 1=select I2S. */ ++ /* [3:0] i2s_in_en: enable it later in test.c */ ++ ++#define HDMITX_DWC_AUD_CONF0 (DWC_OFFSET_MASK + 0x3100) ++/* [4:0] i2s_width */ ++/* [7:5] i2s_mode: 0=standard I2S mode */ ++#define HDMITX_DWC_AUD_CONF1 (DWC_OFFSET_MASK + 0x3101) ++/* [ 3] fifo_empty_mask: 0=enable int; 1=mask int. */ ++/* [ 2] fifo_full_mask: 0=enable int; 1=mask int. */ ++#define HDMITX_DWC_AUD_INT (DWC_OFFSET_MASK + 0x3102) ++ /* [ 1] NLPCM */ ++#define HDMITX_DWC_AUD_CONF2 (DWC_OFFSET_MASK + 0x3103) ++ ++/* [ 4] fifo_overrun_mask: 0=enable int; 1=mask int. ++ * Enable it later when audio starts. ++ */ ++#define HDMITX_DWC_AUD_INT1 (DWC_OFFSET_MASK + 0x3104) ++ ++#define HDMITX_DWC_AUD_N1 (DWC_OFFSET_MASK + 0x3200) ++#define HDMITX_DWC_AUD_N2 (DWC_OFFSET_MASK + 0x3201) ++#define HDMITX_DWC_AUD_N3 (DWC_OFFSET_MASK + 0x3202) ++#define HDMITX_DWC_AUD_CTS1 (DWC_OFFSET_MASK + 0x3203) ++#define HDMITX_DWC_AUD_CTS2 (DWC_OFFSET_MASK + 0x3204) ++#define HDMITX_DWC_AUD_CTS3 (DWC_OFFSET_MASK + 0x3205) ++#define HDMITX_DWC_AUD_INPUTCLKFS (DWC_OFFSET_MASK + 0x3206) ++/* [ 7] sw_audio_fifo_rst */ ++#define HDMITX_DWC_AUD_SPDIF0 (DWC_OFFSET_MASK + 0x3300) ++/* [4:0] spdif_width */ ++/* [ 7] setnlpcm */ ++#define HDMITX_DWC_AUD_SPDIF1 (DWC_OFFSET_MASK + 0x3301) ++/* [ 3] SPDIF fifo_empty_mask: 0=enable int; 1=mask int. */ ++/* [ 2] SPDIF fifo_full_mask: 0=enable int; 1=mask int. */ ++#define HDMITX_DWC_AUD_SPDIFINT (DWC_OFFSET_MASK + 0x3302) ++/* [ 4] SPDIF fifo_overrun_mask: 0=enable int; 1=mask int. */ ++#define HDMITX_DWC_AUD_SPDIFINT1 (DWC_OFFSET_MASK + 0x3303) ++ ++/* Generic Parallel Audio Interface Registers (DWC_OFFSET_MASK + 0x3500) */ ++/* Audio DMA Registers (DWC_OFFSET_MASK + 0x3600) */ ++ ++/* Main Controller Registers */ ++/* [ 6] hdcpclk_disable */ ++/* [ 5] cecclk_disable */ ++/* [ 4] cscclk_disable */ ++/* [ 3] audclk_disable */ ++/* [ 2] prepclk_disable */ ++/* [ 1] tmdsclk_disable */ ++/* [ 0] pixelclk_disable */ ++#define HDMITX_DWC_MC_CLKDIS (DWC_OFFSET_MASK + 0x4001) ++/* ++ * [ 7] gpaswrst_req: 0=generate reset pulse; 1=no reset. ++ * [ 6] cecswrst_req: 0=generate reset pulse; 1=no reset. ++ * [ 4] spdifswrst_req: 0=generate reset pulse; 1=no reset. ++ * [ 3] i2sswrst_req: 0=generate reset pulse; 1=no reset. ++ * [ 2] prepswrst_req: 0=generate reset pulse; 1=no reset. ++ * [ 1] tmdsswrst_req: 0=generate reset pulse; 1=no reset. ++ * [ 0] pixelswrst_req: 0=generate reset pulse; 1=no reset. ++ */ ++#define HDMITX_DWC_MC_SWRSTZREQ (DWC_OFFSET_MASK + 0x4002) ++#define HDMITX_DWC_MC_OPCTRL (DWC_OFFSET_MASK + 0x4003) ++/* [ 0] CSC enable */ ++#define HDMITX_DWC_MC_FLOWCTRL (DWC_OFFSET_MASK + 0x4004) ++#define HDMITX_DWC_MC_PHYRSTZ (DWC_OFFSET_MASK + 0x4005) ++#define HDMITX_DWC_MC_LOCKONCLOCK (DWC_OFFSET_MASK + 0x4006) ++ ++/* Color Space Converter Registers */ ++/* [ 7] csc_limit */ ++#define HDMITX_DWC_CSC_CFG (DWC_OFFSET_MASK + 0x4100) ++#define HDMITX_DWC_CSC_SCALE (DWC_OFFSET_MASK + 0x4101) ++#define HDMITX_DWC_CSC_COEF_A1_MSB (DWC_OFFSET_MASK + 0x4102) ++#define HDMITX_DWC_CSC_COEF_A1_LSB (DWC_OFFSET_MASK + 0x4103) ++#define HDMITX_DWC_CSC_COEF_A2_MSB (DWC_OFFSET_MASK + 0x4104) ++#define HDMITX_DWC_CSC_COEF_A2_LSB (DWC_OFFSET_MASK + 0x4105) ++#define HDMITX_DWC_CSC_COEF_A3_MSB (DWC_OFFSET_MASK + 0x4106) ++#define HDMITX_DWC_CSC_COEF_A3_LSB (DWC_OFFSET_MASK + 0x4107) ++#define HDMITX_DWC_CSC_COEF_A4_MSB (DWC_OFFSET_MASK + 0x4108) ++#define HDMITX_DWC_CSC_COEF_A4_LSB (DWC_OFFSET_MASK + 0x4109) ++#define HDMITX_DWC_CSC_COEF_B1_MSB (DWC_OFFSET_MASK + 0x410A) ++#define HDMITX_DWC_CSC_COEF_B1_LSB (DWC_OFFSET_MASK + 0x410B) ++#define HDMITX_DWC_CSC_COEF_B2_MSB (DWC_OFFSET_MASK + 0x410C) ++#define HDMITX_DWC_CSC_COEF_B2_LSB (DWC_OFFSET_MASK + 0x410D) ++#define HDMITX_DWC_CSC_COEF_B3_MSB (DWC_OFFSET_MASK + 0x410E) ++#define HDMITX_DWC_CSC_COEF_B3_LSB (DWC_OFFSET_MASK + 0x410F) ++#define HDMITX_DWC_CSC_COEF_B4_MSB (DWC_OFFSET_MASK + 0x4110) ++#define HDMITX_DWC_CSC_COEF_B4_LSB (DWC_OFFSET_MASK + 0x4111) ++#define HDMITX_DWC_CSC_COEF_C1_MSB (DWC_OFFSET_MASK + 0x4112) ++#define HDMITX_DWC_CSC_COEF_C1_LSB (DWC_OFFSET_MASK + 0x4113) ++#define HDMITX_DWC_CSC_COEF_C2_MSB (DWC_OFFSET_MASK + 0x4114) ++#define HDMITX_DWC_CSC_COEF_C2_LSB (DWC_OFFSET_MASK + 0x4115) ++#define HDMITX_DWC_CSC_COEF_C3_MSB (DWC_OFFSET_MASK + 0x4116) ++#define HDMITX_DWC_CSC_COEF_C3_LSB (DWC_OFFSET_MASK + 0x4117) ++#define HDMITX_DWC_CSC_COEF_C4_MSB (DWC_OFFSET_MASK + 0x4118) ++#define HDMITX_DWC_CSC_COEF_C4_LSB (DWC_OFFSET_MASK + 0x4119) ++#define HDMITX_DWC_CSC_LIMIT_UP_MSB (DWC_OFFSET_MASK + 0x411A) ++#define HDMITX_DWC_CSC_LIMIT_UP_LSB (DWC_OFFSET_MASK + 0x411B) ++#define HDMITX_DWC_CSC_LIMIT_DN_MSB (DWC_OFFSET_MASK + 0x411C) ++#define HDMITX_DWC_CSC_LIMIT_DN_LSB (DWC_OFFSET_MASK + 0x411D) ++ ++/* HDCP Encryption Engine Registers */ ++#define HDMITX_DWC_A_HDCPCFG0 (DWC_SEC_OFFSET_MASK + 0x5000) ++/* [ 4] hdcp_lock */ ++/* [ 3] dissha1check */ ++/* [ 2] ph2upshiftenc */ ++/* [ 1] encryptiondisable */ ++/* [ 0] swresetn. Write 0 to activate, self-clear to 1. */ ++#define HDMITX_DWC_A_HDCPCFG1 (DWC_SEC_OFFSET_MASK + 0x5001) ++#define HDMITX_DWC_A_HDCPOBS0 (DWC_OFFSET_MASK + 0x5002) ++#define HDMITX_DWC_A_HDCPOBS1 (DWC_OFFSET_MASK + 0x5003) ++#define HDMITX_DWC_A_HDCPOBS2 (DWC_OFFSET_MASK + 0x5004) ++#define HDMITX_DWC_A_HDCPOBS3 (DWC_OFFSET_MASK + 0x5005) ++#define HDMITX_DWC_A_APIINTCLR (DWC_OFFSET_MASK + 0x5006) ++#define HDMITX_DWC_A_APIINTSTAT (DWC_OFFSET_MASK + 0x5007) ++/* [ 7] hdcp_engaged_int_mask */ ++/* [ 6] hdcp_failed_int_mask */ ++/* [ 4] i2c_nack_int_mask */ ++/* [ 3] lost_arbitration_int_mask */ ++/* [ 2] keepout_error_int_mask */ ++/* [ 1] ksv_sha1_calc_int_mask */ ++/* [ 0] ksv_access_int_mask */ ++#define HDMITX_DWC_A_APIINTMSK (DWC_OFFSET_MASK + 0x5008) ++/* [6:5] unencryptconf */ ++/* [ 4] dataenpol */ ++/* [ 3] vsyncpol */ ++/* [ 1] hsyncpol */ ++#define HDMITX_DWC_A_VIDPOLCFG (DWC_OFFSET_MASK + 0x5009) ++#define HDMITX_DWC_A_OESSWCFG (DWC_OFFSET_MASK + 0x500A) ++#define HDMITX_DWC_A_COREVERLSB (DWC_OFFSET_MASK + 0x5014) ++#define HDMITX_DWC_A_COREVERMSB (DWC_OFFSET_MASK + 0x5015) ++/* [ 3] sha1_fail */ ++/* [ 2] ksv_ctrl_update */ ++/* [ 1] Rsvd for read-only ksv_mem_access */ ++/* [ 0] ksv_mem_request */ ++#define HDMITX_DWC_A_KSVMEMCTRL (DWC_OFFSET_MASK + 0x5016) ++ ++#define HDMITX_DWC_HDCP_BSTATUS_0 (DWC_OFFSET_MASK + 0x5020) ++#define HDMITX_DWC_HDCP_BSTATUS_1 (DWC_OFFSET_MASK + 0x5021) ++#define HDMITX_DWC_HDCP_M0_0 (DWC_OFFSET_MASK + 0x5022) ++#define HDMITX_DWC_HDCP_M0_1 (DWC_OFFSET_MASK + 0x5023) ++#define HDMITX_DWC_HDCP_M0_2 (DWC_OFFSET_MASK + 0x5024) ++#define HDMITX_DWC_HDCP_M0_3 (DWC_OFFSET_MASK + 0x5025) ++#define HDMITX_DWC_HDCP_M0_4 (DWC_OFFSET_MASK + 0x5026) ++#define HDMITX_DWC_HDCP_M0_5 (DWC_OFFSET_MASK + 0x5027) ++#define HDMITX_DWC_HDCP_M0_6 (DWC_OFFSET_MASK + 0x5028) ++#define HDMITX_DWC_HDCP_M0_7 (DWC_OFFSET_MASK + 0x5029) ++#define HDMITX_DWC_HDCP_KSV (DWC_OFFSET_MASK + 0x502A) ++#define HDMITX_DWC_HDCP_VH (DWC_OFFSET_MASK + 0x52A5) ++#define HDMITX_DWC_HDCP_REVOC_SIZE_0 (DWC_OFFSET_MASK + 0x52B9) ++#define HDMITX_DWC_HDCP_REVOC_SIZE_1 (DWC_OFFSET_MASK + 0x52BA) ++#define HDMITX_DWC_HDCP_REVOC_LIST (DWC_OFFSET_MASK + 0x52BB) ++ ++/* HDCP BKSV Registers */ ++#define HDMITX_DWC_HDCPREG_BKSV0 (DWC_OFFSET_MASK + 0x7800) ++#define HDMITX_DWC_HDCPREG_BKSV1 (DWC_OFFSET_MASK + 0x7801) ++#define HDMITX_DWC_HDCPREG_BKSV2 (DWC_OFFSET_MASK + 0x7802) ++#define HDMITX_DWC_HDCPREG_BKSV3 (DWC_OFFSET_MASK + 0x7803) ++#define HDMITX_DWC_HDCPREG_BKSV4 (DWC_OFFSET_MASK + 0x7804) ++ ++/* HDCP AN Registers */ ++#define HDMITX_DWC_HDCPREG_ANCONF (DWC_OFFSET_MASK + 0x7805) ++#define HDMITX_DWC_HDCPREG_AN0 (DWC_OFFSET_MASK + 0x7806) ++#define HDMITX_DWC_HDCPREG_AN1 (DWC_OFFSET_MASK + 0x7807) ++#define HDMITX_DWC_HDCPREG_AN2 (DWC_OFFSET_MASK + 0x7808) ++#define HDMITX_DWC_HDCPREG_AN3 (DWC_OFFSET_MASK + 0x7809) ++#define HDMITX_DWC_HDCPREG_AN4 (DWC_OFFSET_MASK + 0x780A) ++#define HDMITX_DWC_HDCPREG_AN5 (DWC_OFFSET_MASK + 0x780B) ++#define HDMITX_DWC_HDCPREG_AN6 (DWC_OFFSET_MASK + 0x780C) ++#define HDMITX_DWC_HDCPREG_AN7 (DWC_OFFSET_MASK + 0x780D) ++#define HDMITX_DWC_HDCPREG_RMLCTL (DWC_OFFSET_MASK + 0x780E) ++ ++/* Encrypted DPK Embedded Storage Registers */ ++#define HDMITX_DWC_HDCPREG_RMLSTS (DWC_OFFSET_MASK + 0x780F) ++#define HDMITX_DWC_HDCPREG_SEED0 (DWC_SEC_OFFSET_MASK + 0x7810) ++#define HDMITX_DWC_HDCPREG_SEED1 (DWC_SEC_OFFSET_MASK + 0x7811) ++#define HDMITX_DWC_HDCPREG_DPK0 (DWC_SEC_OFFSET_MASK + 0x7812) ++#define HDMITX_DWC_HDCPREG_DPK1 (DWC_SEC_OFFSET_MASK + 0x7813) ++#define HDMITX_DWC_HDCPREG_DPK2 (DWC_SEC_OFFSET_MASK + 0x7814) ++#define HDMITX_DWC_HDCPREG_DPK3 (DWC_SEC_OFFSET_MASK + 0x7815) ++#define HDMITX_DWC_HDCPREG_DPK4 (DWC_SEC_OFFSET_MASK + 0x7816) ++#define HDMITX_DWC_HDCPREG_DPK5 (DWC_SEC_OFFSET_MASK + 0x7817) ++#define HDMITX_DWC_HDCPREG_DPK6 (DWC_SEC_OFFSET_MASK + 0x7818) ++ ++/* HDCP22 Registers */ ++#define HDMITX_DWC_HDCP22REG_ID (DWC_OFFSET_MASK + 0x7900) ++#define HDMITX_DWC_HDCP22REG_CTRL (DWC_SEC_OFFSET_MASK + 0x7904) ++#define HDMITX_DWC_HDCP22REG_CTRL1 (DWC_OFFSET_MASK + 0x7905) ++#define HDMITX_DWC_HDCP22REG_STS (DWC_OFFSET_MASK + 0x7908) ++#define HDMITX_DWC_HDCP22REG_MASK (DWC_OFFSET_MASK + 0x790C) ++#define HDMITX_DWC_HDCP22REG_STAT (DWC_OFFSET_MASK + 0x790D) ++#define HDMITX_DWC_HDCP22REG_MUTE (DWC_OFFSET_MASK + 0x790E) ++ ++ ++/* ********** CEC related ********** */ ++ ++/* CEC 2.0 Engine Registers */ ++#define HDMITX_DWC_CEC_CTRL (DWC_OFFSET_MASK + 0x7D00) ++#define HDMITX_DWC_CEC_INTR_MASK (DWC_OFFSET_MASK + 0x7D02) ++#define HDMITX_DWC_CEC_LADD_LOW (DWC_OFFSET_MASK + 0x7D05) ++#define HDMITX_DWC_CEC_LADD_HIGH (DWC_OFFSET_MASK + 0x7D06) ++#define HDMITX_DWC_CEC_TX_CNT (DWC_OFFSET_MASK + 0x7D07) ++#define HDMITX_DWC_CEC_RX_CNT (DWC_OFFSET_MASK + 0x7D08) ++#define HDMITX_DWC_CEC_TX_DATA00 (DWC_OFFSET_MASK + 0x7D10) ++#define HDMITX_DWC_CEC_TX_DATA01 (DWC_OFFSET_MASK + 0x7D11) ++#define HDMITX_DWC_CEC_TX_DATA02 (DWC_OFFSET_MASK + 0x7D12) ++#define HDMITX_DWC_CEC_TX_DATA03 (DWC_OFFSET_MASK + 0x7D13) ++#define HDMITX_DWC_CEC_TX_DATA04 (DWC_OFFSET_MASK + 0x7D14) ++#define HDMITX_DWC_CEC_TX_DATA05 (DWC_OFFSET_MASK + 0x7D15) ++#define HDMITX_DWC_CEC_TX_DATA06 (DWC_OFFSET_MASK + 0x7D16) ++#define HDMITX_DWC_CEC_TX_DATA07 (DWC_OFFSET_MASK + 0x7D17) ++#define HDMITX_DWC_CEC_TX_DATA08 (DWC_OFFSET_MASK + 0x7D18) ++#define HDMITX_DWC_CEC_TX_DATA09 (DWC_OFFSET_MASK + 0x7D19) ++#define HDMITX_DWC_CEC_TX_DATA10 (DWC_OFFSET_MASK + 0x7D1A) ++#define HDMITX_DWC_CEC_TX_DATA11 (DWC_OFFSET_MASK + 0x7D1B) ++#define HDMITX_DWC_CEC_TX_DATA12 (DWC_OFFSET_MASK + 0x7D1C) ++#define HDMITX_DWC_CEC_TX_DATA13 (DWC_OFFSET_MASK + 0x7D1D) ++#define HDMITX_DWC_CEC_TX_DATA14 (DWC_OFFSET_MASK + 0x7D1E) ++#define HDMITX_DWC_CEC_TX_DATA15 (DWC_OFFSET_MASK + 0x7D1F) ++#define HDMITX_DWC_CEC_RX_DATA00 (DWC_OFFSET_MASK + 0x7D20) ++#define HDMITX_DWC_CEC_RX_DATA01 (DWC_OFFSET_MASK + 0x7D21) ++#define HDMITX_DWC_CEC_RX_DATA02 (DWC_OFFSET_MASK + 0x7D22) ++#define HDMITX_DWC_CEC_RX_DATA03 (DWC_OFFSET_MASK + 0x7D23) ++#define HDMITX_DWC_CEC_RX_DATA04 (DWC_OFFSET_MASK + 0x7D24) ++#define HDMITX_DWC_CEC_RX_DATA05 (DWC_OFFSET_MASK + 0x7D25) ++#define HDMITX_DWC_CEC_RX_DATA06 (DWC_OFFSET_MASK + 0x7D26) ++#define HDMITX_DWC_CEC_RX_DATA07 (DWC_OFFSET_MASK + 0x7D27) ++#define HDMITX_DWC_CEC_RX_DATA08 (DWC_OFFSET_MASK + 0x7D28) ++#define HDMITX_DWC_CEC_RX_DATA09 (DWC_OFFSET_MASK + 0x7D29) ++#define HDMITX_DWC_CEC_RX_DATA10 (DWC_OFFSET_MASK + 0x7D2A) ++#define HDMITX_DWC_CEC_RX_DATA11 (DWC_OFFSET_MASK + 0x7D2B) ++#define HDMITX_DWC_CEC_RX_DATA12 (DWC_OFFSET_MASK + 0x7D2C) ++#define HDMITX_DWC_CEC_RX_DATA13 (DWC_OFFSET_MASK + 0x7D2D) ++#define HDMITX_DWC_CEC_RX_DATA14 (DWC_OFFSET_MASK + 0x7D2E) ++#define HDMITX_DWC_CEC_RX_DATA15 (DWC_OFFSET_MASK + 0x7D2F) ++#define HDMITX_DWC_CEC_LOCK_BUF (DWC_OFFSET_MASK + 0x7D30) ++#define HDMITX_DWC_CEC_WAKEUPCTRL (DWC_OFFSET_MASK + 0x7D31) ++ ++/* I2C Master Registers(E-DDC/SCDC) */ ++#define HDMITX_DWC_I2CM_SLAVE (DWC_OFFSET_MASK + 0x7E00) ++#define HDMITX_DWC_I2CM_ADDRESS (DWC_OFFSET_MASK + 0x7E01) ++#define HDMITX_DWC_I2CM_DATAO (DWC_OFFSET_MASK + 0x7E02) ++#define HDMITX_DWC_I2CM_DATAI (DWC_OFFSET_MASK + 0x7E03) ++#define HDMITX_DWC_I2CM_OPERATION (DWC_OFFSET_MASK + 0x7E04) ++/* [ 2] done_mask */ ++/* [ 6] read_req_mask */ ++#define HDMITX_DWC_I2CM_INT (DWC_OFFSET_MASK + 0x7E05) ++/* [ 6] nack_mask */ ++/* [ 2] arbitration_error_mask */ ++#define HDMITX_DWC_I2CM_CTLINT (DWC_OFFSET_MASK + 0x7E06) ++/* [ 3] i2c_fast_mode: 0=standard mode; 1=fast mode. */ ++#define HDMITX_DWC_I2CM_DIV (DWC_OFFSET_MASK + 0x7E07) ++#define HDMITX_DWC_I2CM_SEGADDR (DWC_OFFSET_MASK + 0x7E08) ++#define HDMITX_DWC_I2CM_SOFTRSTZ (DWC_OFFSET_MASK + 0x7E09) ++#define HDMITX_DWC_I2CM_SEGPTR (DWC_OFFSET_MASK + 0x7E0A) ++/* I2CM_SS_SCL_HCNT = RndUp(min_ss_scl_htime*Freq(sfrclkInMHz)/1000) */ ++/* I2CM_SS_SCL_LCNT = RndUp(min_ss_scl_ltime*Freq(sfrclkInMHz)/1000) */ ++/* I2CM_FS_SCL_HCNT = RndUp(min_fs_scl_htime*Freq(sfrclkInMHz)/1000) */ ++/* I2CM_FS_SCL_LCNT = RndUp(min_fs_scl_ltime*Freq(sfrclkInMHz)/1000) */ ++/* Where Freq(sfrclkInMHz)=24; */ ++#define HDMITX_DWC_I2CM_SS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x7E0B) ++#define HDMITX_DWC_I2CM_SS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x7E0C) ++#define HDMITX_DWC_I2CM_SS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x7E0D) ++#define HDMITX_DWC_I2CM_SS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x7E0E) ++#define HDMITX_DWC_I2CM_FS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x7E0F) ++#define HDMITX_DWC_I2CM_FS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x7E10) ++#define HDMITX_DWC_I2CM_FS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x7E11) ++#define HDMITX_DWC_I2CM_FS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x7E12) ++#define HDMITX_DWC_I2CM_SDA_HOLD (DWC_OFFSET_MASK + 0x7E13) ++/* [ 5] updt_rd_vsyncpoll_en */ ++/* [ 4] read_request_en */ ++/* [ 0] read_update */ ++#define HDMITX_DWC_I2CM_SCDC_UPDATE (DWC_OFFSET_MASK + 0x7E14) ++#define HDMITX_DWC_I2CM_READ_BUFF0 (DWC_OFFSET_MASK + 0x7E20) ++#define HDMITX_DWC_I2CM_READ_BUFF1 (DWC_OFFSET_MASK + 0x7E21) ++#define HDMITX_DWC_I2CM_READ_BUFF2 (DWC_OFFSET_MASK + 0x7E22) ++#define HDMITX_DWC_I2CM_READ_BUFF3 (DWC_OFFSET_MASK + 0x7E23) ++#define HDMITX_DWC_I2CM_READ_BUFF4 (DWC_OFFSET_MASK + 0x7E24) ++#define HDMITX_DWC_I2CM_READ_BUFF5 (DWC_OFFSET_MASK + 0x7E25) ++#define HDMITX_DWC_I2CM_READ_BUFF6 (DWC_OFFSET_MASK + 0x7E26) ++#define HDMITX_DWC_I2CM_READ_BUFF7 (DWC_OFFSET_MASK + 0x7E27) ++#define HDMITX_DWC_I2CM_SCDC_UPDATE0 (DWC_OFFSET_MASK + 0x7E30) ++#define HDMITX_DWC_I2CM_SCDC_UPDATE1 (DWC_OFFSET_MASK + 0x7E31) ++ ++#endif /* __HDMI_TX_REG_H_ */ +diff --git a/include/amlogic/media/vout/hdmitx/mach_reg.h b/include/amlogic/media/vout/hdmitx/mach_reg.h +new file mode 100644 +index 00000000000..865eddb198e +--- /dev/null ++++ b/include/amlogic/media/vout/hdmitx/mach_reg.h +@@ -0,0 +1,625 @@ ++#ifndef __MACH_REG_H__ ++#define __MACH_REG_H__ ++ ++/* ++ * RePacket HDMI related registers rd/wr ++ */ ++struct reg_map { ++ uint32_t base_addr; ++}; ++ ++#define CBUS_REG_IDX 0 ++#define PERIPHS_REG_IDX 1 ++#define VCBUS_REG_IDX 2 ++#define AOBUS_REG_IDX 3 ++#define HHI_REG_IDX 4 ++#define RESET_CBUS_REG_IDX 5 ++#define HDMITX_REG_IDX 6 ++#define HDMITX_SEC_REG_IDX 7 ++#define ELP_ESM_REG_IDX 8 ++/* new added in SC2 */ ++#define ANACTRL_REG_IDX 9 ++#define PWRCTRL_REG_IDX 10 ++#define RESETCTRL_REG_IDX 11 ++#define SYSCTRL_REG_IDX 12 ++#define REG_IDX_END 13 ++ ++#define BASE_REG_OFFSET 24 ++ ++#define PERIPHS_REG_ADDR(reg) \ ++ ((PERIPHS_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) ++#define VCBUS_REG_ADDR(reg) \ ++ ((VCBUS_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) ++#define AOBUS_REG_ADDR(reg) \ ++ ((AOBUS_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) ++#define HHI_REG_ADDR(reg) \ ++ ((HHI_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) ++#define RESET_CBUS_REG_ADDR(reg) \ ++ ((RESET_CBUS_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) ++#define HDMITX_SEC_REG_ADDR(reg) \ ++ ((HDMITX_SEC_REG_IDX << BASE_REG_OFFSET) + (reg))/*DWC*/ ++#define HDMITX_REG_ADDR(reg) \ ++ ((HDMITX_REG_IDX << BASE_REG_OFFSET) + (reg))/*TOP*/ ++#define ELP_ESM_REG_ADDR(reg) \ ++ ((ELP_ESM_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) ++#define ANACTRL_REG_ADDR(reg) \ ++ ((ANACTRL_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) ++#define PWRCTRL_REG_ADDR(reg) \ ++ ((PWRCTRL_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) ++#define RESETCTRL_REG_ADDR(reg) \ ++ ((RESETCTRL_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) ++#define SYSCTRL_REG_ADDR(reg) \ ++ ((SYSCTRL_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) ++ ++struct reg_s { ++ unsigned int reg; ++ unsigned int val; ++}; ++ ++unsigned int hd_read_reg(unsigned int addr); ++void hd_write_reg(unsigned int addr, unsigned int val); ++void hd_set_reg_bits(unsigned int addr, unsigned int value, unsigned int offset, ++ unsigned int len); ++uint32_t hd_get_paddr(uint32_t addr); ++unsigned int hdmitx_rd_reg(unsigned int addr); ++void hdmitx_wr_reg(unsigned int addr, unsigned int data); ++void hdmitx_set_reg_bits(unsigned int addr, unsigned int value, ++ unsigned int offset, unsigned int len); ++void hdmitx_poll_reg(unsigned int addr, unsigned int val, unsigned long timeout); ++ ++/* REG_BASE: REGISTER_BASE_ADDR = 0xfe000000 */ ++#define CLKCTRL_SYS_CLK_EN0_REG2 0x0013 ++#define P_CLKCTRL_SYS_CLK_EN0_REG2 HHI_REG_ADDR(CLKCTRL_SYS_CLK_EN0_REG2) ++#define CLKCTRL_VID_CLK_CTRL 0x0030 ++#define P_CLKCTRL_VID_CLK_CTRL HHI_REG_ADDR(CLKCTRL_VID_CLK_CTRL) ++#define CLKCTRL_VID_CLK_CTRL2 0x0031 ++#define P_CLKCTRL_VID_CLK_CTRL2 HHI_REG_ADDR(CLKCTRL_VID_CLK_CTRL2) ++#define CLKCTRL_VID_CLK_DIV 0x0032 ++#define P_CLKCTRL_VID_CLK_DIV HHI_REG_ADDR(CLKCTRL_VID_CLK_DIV) ++#define CLKCTRL_HDMI_CLK_CTRL 0x0038 ++#define P_CLKCTRL_HDMI_CLK_CTRL HHI_REG_ADDR(CLKCTRL_HDMI_CLK_CTRL) ++#define CLKCTRL_VID_PLL_CLK_DIV 0x0039 ++#define P_CLKCTRL_VID_PLL_CLK_DIV HHI_REG_ADDR(CLKCTRL_VID_PLL_CLK_DIV) ++#define CLKCTRL_HDCP22_CLK_CTRL 0x0040 ++#define P_CLKCTRL_HDCP22_CLK_CTRL HHI_REG_ADDR(CLKCTRL_HDCP22_CLK_CTRL) ++ ++/* REG_BASE: REGISTER_BASE_ADDR = 0xfe002000 */ ++#define RESETCTRL_RESET0 0x0000 ++#define P_RESETCTRL_RESET0 RESETCTRL_REG_ADDR(RESETCTRL_RESET0) ++#define RESETCTRL_RESET2 0x0002 ++#define P_RESETCTRL_RESET2 RESETCTRL_REG_ADDR(RESETCTRL_RESET2) ++ ++/* REG_BASE: REGISTER_BASE_ADDR = 0xfe004000 */ ++#define PADCTRL_PIN_MUX_REGB 0x0b ++#define P_PADCTRL_PIN_MUX_REGB PERIPHS_REG_ADDR(PADCTRL_PIN_MUX_REGB) ++#define PADCTRL_GPIOH_I 0x50 ++#define P_PADCTRL_GPIOH_I PERIPHS_REG_ADDR(PADCTRL_GPIOH_I) ++ ++/* REG_BASE: REGISTER_BASE_ADDR = 0xfe008000 */ ++#define ANACTRL_HDMIPLL_CTRL0 0x0070 ++#define P_ANACTRL_HDMIPLL_CTRL0 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL0) ++#define ANACTRL_HDMIPLL_CTRL1 0x0071 ++#define P_ANACTRL_HDMIPLL_CTRL1 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL1) ++#define ANACTRL_HDMIPLL_CTRL2 0x0072 ++#define P_ANACTRL_HDMIPLL_CTRL2 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL2) ++#define ANACTRL_HDMIPLL_CTRL3 0x0073 ++#define P_ANACTRL_HDMIPLL_CTRL3 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL3) ++#define ANACTRL_HDMIPLL_CTRL4 0x0074 ++#define P_ANACTRL_HDMIPLL_CTRL4 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL4) ++#define ANACTRL_HDMIPLL_CTRL5 0x0075 ++#define P_ANACTRL_HDMIPLL_CTRL5 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL5) ++#define ANACTRL_HDMIPLL_CTRL6 0x0076 ++#define P_ANACTRL_HDMIPLL_CTRL6 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL6) ++#define ANACTRL_HDMIPLL_STS 0x0077 ++#define P_ANACTRL_HDMIPLL_STS ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_STS) ++#define ANACTRL_HDMIPLL_VLOCK 0x0079 ++#define P_ANACTRL_HDMIPLL_VLOCK ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_VLOCK) ++#define ANACTRL_HDMIPHY_CTRL0 0x0080 ++#define P_ANACTRL_HDMIPHY_CTRL0 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL0) ++#define ANACTRL_HDMIPHY_CTRL1 0x0081 ++#define P_ANACTRL_HDMIPHY_CTRL1 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL1) ++#define ANACTRL_HDMIPHY_CTRL2 0x0082 ++#define P_ANACTRL_HDMIPHY_CTRL2 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL2) ++#define ANACTRL_HDMIPHY_CTRL3 0x0083 ++#define P_ANACTRL_HDMIPHY_CTRL3 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL3) ++#define ANACTRL_HDMIPHY_CTRL4 0x0084 ++#define P_ANACTRL_HDMIPHY_CTRL4 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL4) ++#define ANACTRL_HDMIPHY_CTRL5 0x0085 ++#define P_ANACTRL_HDMIPHY_CTRL5 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL5) ++#define ANACTRL_HDMIPHY_STS 0x0086 ++#define P_ANACTRL_HDMIPHY_STS ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_STS) ++ ++/* REG_BASE: REGISTER_BASE_ADDR = 0xfe00c000 */ ++#define PWRCTRL_MEM_PD11 0x001b ++#define P_PWRCTRL_MEM_PD11 PWRCTRL_REG_ADDR(PWRCTRL_MEM_PD11) ++ ++/* REG_BASE: REGISTER_BASE_ADDR = 0xfe010000 */ ++#define SYSCTRL_DEBUG_REG0 0x90 ++#define P_SYSCTRL_DEBUG_REG0 SYSCTRL_REG_ADDR(SYSCTRL_DEBUG_REG0) ++ ++/* REG_BASE: REGISTER_BASE_ADDR = 0xff000000 */ ++#define VENC_DVI_SETTING 0x1b62 /* register.h:8014 */ ++#define P_VENC_DVI_SETTING VCBUS_REG_ADDR(VENC_DVI_SETTING) ++ ++#define VENC_VIDEO_TST_EN 0x1b70 ++#define P_VENC_VIDEO_TST_EN VCBUS_REG_ADDR(VENC_VIDEO_TST_EN) ++#define VENC_VIDEO_TST_MDSEL 0x1b71 ++#define P_VENC_VIDEO_TST_MDSEL VCBUS_REG_ADDR(VENC_VIDEO_TST_MDSEL) ++#define VENC_VIDEO_TST_Y 0x1b72 ++#define P_VENC_VIDEO_TST_Y VCBUS_REG_ADDR(VENC_VIDEO_TST_Y) ++#define VENC_VIDEO_TST_CB 0x1b73 ++#define P_VENC_VIDEO_TST_CB VCBUS_REG_ADDR(VENC_VIDEO_TST_CB) ++#define VENC_VIDEO_TST_CR 0x1b74 ++#define P_VENC_VIDEO_TST_CR VCBUS_REG_ADDR(VENC_VIDEO_TST_CR) ++#define VENC_VIDEO_TST_CLRBAR_STRT 0x1b75 ++#define P_VENC_VIDEO_TST_CLRBAR_STRT VCBUS_REG_ADDR(VENC_VIDEO_TST_CLRBAR_STRT) ++#define VENC_VIDEO_TST_CLRBAR_WIDTH 0x1b76 ++#define P_VENC_VIDEO_TST_CLRBAR_WIDTH \ ++ VCBUS_REG_ADDR(VENC_VIDEO_TST_CLRBAR_WIDTH) ++#define VENC_VIDEO_TST_VDCNT_STSET 0x1b77 ++#define P_VENC_VIDEO_TST_VDCNT_STSET VCBUS_REG_ADDR(VENC_VIDEO_TST_VDCNT_STSET) ++#define VENC_VDAC_SETTING 0x1b7e ++#define P_VENC_VDAC_SETTING VCBUS_REG_ADDR(VENC_VDAC_SETTING) ++#define ENCP_VIDEO_EN 0x1b80 /* register.h:8078 */ ++#define P_ENCP_VIDEO_EN VCBUS_REG_ADDR(ENCP_VIDEO_EN) ++#define ENCP_VIDEO_SYNC_MODE 0x1b81 /* register.h:8079 */ ++#define P_ENCP_VIDEO_SYNC_MODE VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_MODE) ++#define ENCP_MACV_EN 0x1b82 /* register.h:8080 */ ++#define P_ENCP_MACV_EN VCBUS_REG_ADDR(ENCP_MACV_EN) ++#define ENCP_VIDEO_Y_SCL 0x1b83 /* register.h:8081 */ ++#define P_ENCP_VIDEO_Y_SCL VCBUS_REG_ADDR(ENCP_VIDEO_Y_SCL) ++#define ENCP_VIDEO_PB_SCL 0x1b84 /* register.h:8082 */ ++#define P_ENCP_VIDEO_PB_SCL VCBUS_REG_ADDR(ENCP_VIDEO_PB_SCL) ++#define ENCP_VIDEO_PR_SCL 0x1b85 /* register.h:8083 */ ++#define P_ENCP_VIDEO_PR_SCL VCBUS_REG_ADDR(ENCP_VIDEO_PR_SCL) ++#define ENCP_VIDEO_SYNC_SCL 0x1b86 /* register.h:8084 */ ++#define P_ENCP_VIDEO_SYNC_SCL VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_SCL) ++#define ENCP_VIDEO_MACV_SCL 0x1b87 /* register.h:8085 */ ++#define P_ENCP_VIDEO_MACV_SCL VCBUS_REG_ADDR(ENCP_VIDEO_MACV_SCL) ++#define ENCP_VIDEO_Y_OFFST 0x1b88 /* register.h:8086 */ ++#define P_ENCP_VIDEO_Y_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_Y_OFFST) ++#define ENCP_VIDEO_PB_OFFST 0x1b89 /* register.h:8087 */ ++#define P_ENCP_VIDEO_PB_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_PB_OFFST) ++#define ENCP_VIDEO_PR_OFFST 0x1b8a /* register.h:8088 */ ++#define P_ENCP_VIDEO_PR_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_PR_OFFST) ++#define ENCP_VIDEO_SYNC_OFFST 0x1b8b /* register.h:8089 */ ++#define P_ENCP_VIDEO_SYNC_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_OFFST) ++#define ENCP_VIDEO_MACV_OFFST 0x1b8c /* register.h:8090 */ ++#define P_ENCP_VIDEO_MACV_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_MACV_OFFST) ++#define ENCP_VIDEO_MODE 0x1b8d /* register.h:8092 */ ++#define P_ENCP_VIDEO_MODE VCBUS_REG_ADDR(ENCP_VIDEO_MODE) ++#define ENCP_VIDEO_MODE_ADV 0x1b8e /* register.h:8093 */ ++#define P_ENCP_VIDEO_MODE_ADV VCBUS_REG_ADDR(ENCP_VIDEO_MODE_ADV) ++#define ENCP_DBG_PX_RST 0x1b90 /* register.h:8095 */ ++#define P_ENCP_DBG_PX_RST VCBUS_REG_ADDR(ENCP_DBG_PX_RST) ++#define ENCP_DBG_LN_RST 0x1b91 /* register.h:8096 */ ++#define P_ENCP_DBG_LN_RST VCBUS_REG_ADDR(ENCP_DBG_LN_RST) ++#define ENCP_DBG_PX_INT 0x1b92 /* register.h:8097 */ ++#define P_ENCP_DBG_PX_INT VCBUS_REG_ADDR(ENCP_DBG_PX_INT) ++#define ENCP_DBG_LN_INT 0x1b93 /* register.h:8098 */ ++#define P_ENCP_DBG_LN_INT VCBUS_REG_ADDR(ENCP_DBG_LN_INT) ++#define ENCP_VIDEO_YFP1_HTIME 0x1b94 /* register.h:8100 */ ++#define P_ENCP_VIDEO_YFP1_HTIME VCBUS_REG_ADDR(ENCP_VIDEO_YFP1_HTIME) ++#define ENCP_VIDEO_YFP2_HTIME 0x1b95 /* register.h:8101 */ ++#define P_ENCP_VIDEO_YFP2_HTIME VCBUS_REG_ADDR(ENCP_VIDEO_YFP2_HTIME) ++#define ENCP_VIDEO_YC_DLY 0x1b96 /* register.h:8102 */ ++#define P_ENCP_VIDEO_YC_DLY VCBUS_REG_ADDR(ENCP_VIDEO_YC_DLY) ++#define ENCP_VIDEO_MAX_PXCNT 0x1b97 /* register.h:8103 */ ++#define P_ENCP_VIDEO_MAX_PXCNT VCBUS_REG_ADDR(ENCP_VIDEO_MAX_PXCNT) ++#define ENCP_VIDEO_HSPULS_BEGIN 0x1b98 /* register.h:8104 */ ++#define P_ENCP_VIDEO_HSPULS_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_HSPULS_BEGIN) ++#define ENCP_VIDEO_HSPULS_END 0x1b99 /* register.h:8105 */ ++#define P_ENCP_VIDEO_HSPULS_END VCBUS_REG_ADDR(ENCP_VIDEO_HSPULS_END) ++#define ENCP_VIDEO_HSPULS_SWITCH 0x1b9a /* register.h:8106 */ ++#define P_ENCP_VIDEO_HSPULS_SWITCH VCBUS_REG_ADDR(ENCP_VIDEO_HSPULS_SWITCH) ++#define ENCP_VIDEO_VSPULS_BEGIN 0x1b9b /* register.h:8107 */ ++#define P_ENCP_VIDEO_VSPULS_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_BEGIN) ++#define ENCP_VIDEO_VSPULS_END 0x1b9c /* register.h:8108 */ ++#define P_ENCP_VIDEO_VSPULS_END VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_END) ++#define ENCP_VIDEO_VSPULS_BLINE 0x1b9d /* register.h:8109 */ ++#define P_ENCP_VIDEO_VSPULS_BLINE VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_BLINE) ++#define ENCP_VIDEO_VSPULS_ELINE 0x1b9e /* register.h:8110 */ ++#define P_ENCP_VIDEO_VSPULS_ELINE VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_ELINE) ++#define ENCP_VIDEO_EQPULS_BEGIN 0x1b9f /* register.h:8111 */ ++#define P_ENCP_VIDEO_EQPULS_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_BEGIN) ++#define ENCP_VIDEO_EQPULS_END 0x1ba0 /* register.h:8112 */ ++#define P_ENCP_VIDEO_EQPULS_END VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_END) ++#define ENCP_VIDEO_EQPULS_BLINE 0x1ba1 /* register.h:8113 */ ++#define P_ENCP_VIDEO_EQPULS_BLINE VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_BLINE) ++#define ENCP_VIDEO_EQPULS_ELINE 0x1ba2 /* register.h:8114 */ ++#define P_ENCP_VIDEO_EQPULS_ELINE VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_ELINE) ++#define ENCP_VIDEO_HAVON_END 0x1ba3 /* register.h:8115 */ ++#define P_ENCP_VIDEO_HAVON_END VCBUS_REG_ADDR(ENCP_VIDEO_HAVON_END) ++#define ENCP_VIDEO_HAVON_BEGIN 0x1ba4 /* register.h:8116 */ ++#define P_ENCP_VIDEO_HAVON_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_HAVON_BEGIN) ++#define ENCP_VIDEO_VAVON_ELINE 0x1baf /* register.h:8117 */ ++#define P_ENCP_VIDEO_VAVON_ELINE VCBUS_REG_ADDR(ENCP_VIDEO_VAVON_ELINE) ++#define ENCP_VIDEO_VAVON_BLINE 0x1ba6 /* register.h:8118 */ ++#define P_ENCP_VIDEO_VAVON_BLINE VCBUS_REG_ADDR(ENCP_VIDEO_VAVON_BLINE) ++#define ENCP_VIDEO_HSO_BEGIN 0x1ba7 /* register.h:8119 */ ++#define P_ENCP_VIDEO_HSO_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_HSO_BEGIN) ++#define ENCP_VIDEO_HSO_END 0x1ba8 /* register.h:8120 */ ++#define P_ENCP_VIDEO_HSO_END VCBUS_REG_ADDR(ENCP_VIDEO_HSO_END) ++#define ENCP_VIDEO_VSO_BEGIN 0x1ba9 /* register.h:8121 */ ++#define P_ENCP_VIDEO_VSO_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_VSO_BEGIN) ++#define ENCP_VIDEO_VSO_END 0x1baa /* register.h:8122 */ ++#define P_ENCP_VIDEO_VSO_END VCBUS_REG_ADDR(ENCP_VIDEO_VSO_END) ++#define ENCP_VIDEO_VSO_BLINE 0x1bab /* register.h:8123 */ ++#define P_ENCP_VIDEO_VSO_BLINE VCBUS_REG_ADDR(ENCP_VIDEO_VSO_BLINE) ++#define ENCP_VIDEO_VSO_ELINE 0x1bac /* register.h:8124 */ ++#define P_ENCP_VIDEO_VSO_ELINE VCBUS_REG_ADDR(ENCP_VIDEO_VSO_ELINE) ++#define ENCP_VIDEO_SYNC_WAVE_CURVE 0x1bad /* register.h:8125 */ ++#define P_ENCP_VIDEO_SYNC_WAVE_CURVE VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_WAVE_CURVE) ++#define ENCP_VIDEO_MAX_LNCNT 0x1bae /* register.h:8126 */ ++#define P_ENCP_VIDEO_MAX_LNCNT VCBUS_REG_ADDR(ENCP_VIDEO_MAX_LNCNT) ++#define ENCP_VIDEO_SY_VAL 0x1bb0 /* register.h:8127 */ ++#define P_ENCP_VIDEO_SY_VAL VCBUS_REG_ADDR(ENCP_VIDEO_SY_VAL) ++#define ENCP_VIDEO_SY2_VAL 0x1bb1 /* register.h:8128 */ ++#define P_ENCP_VIDEO_SY2_VAL VCBUS_REG_ADDR(ENCP_VIDEO_SY2_VAL) ++#define ENCP_VIDEO_BLANKY_VAL 0x1bb2 /* register.h:8129 */ ++#define P_ENCP_VIDEO_BLANKY_VAL VCBUS_REG_ADDR(ENCP_VIDEO_BLANKY_VAL) ++#define ENCP_VIDEO_BLANKPB_VAL 0x1bb3 /* register.h:8130 */ ++#define P_ENCP_VIDEO_BLANKPB_VAL VCBUS_REG_ADDR(ENCP_VIDEO_BLANKPB_VAL) ++#define ENCP_VIDEO_BLANKPR_VAL 0x1bb4 /* register.h:8131 */ ++#define P_ENCP_VIDEO_BLANKPR_VAL VCBUS_REG_ADDR(ENCP_VIDEO_BLANKPR_VAL) ++#define ENCP_VIDEO_HOFFST 0x1bb5 /* register.h:8132 */ ++#define P_ENCP_VIDEO_HOFFST VCBUS_REG_ADDR(ENCP_VIDEO_HOFFST) ++#define ENCP_VIDEO_VOFFST 0x1bb6 /* register.h:8133 */ ++#define P_ENCP_VIDEO_VOFFST VCBUS_REG_ADDR(ENCP_VIDEO_VOFFST) ++#define ENCP_VIDEO_RGB_CTRL 0x1bb7 /* register.h:8134 */ ++#define P_ENCP_VIDEO_RGB_CTRL VCBUS_REG_ADDR(ENCP_VIDEO_RGB_CTRL) ++#define ENCP_VIDEO_FILT_CTRL 0x1bb8 /* register.h:8135 */ ++#define P_ENCP_VIDEO_FILT_CTRL VCBUS_REG_ADDR(ENCP_VIDEO_FILT_CTRL) ++#define ENCP_VIDEO_OFLD_VPEQ_OFST 0x1bb9 /* register.h:8136 */ ++#define P_ENCP_VIDEO_OFLD_VPEQ_OFST VCBUS_REG_ADDR(ENCP_VIDEO_OFLD_VPEQ_OFST) ++#define ENCP_VIDEO_OFLD_VOAV_OFST 0x1bba /* register.h:8137 */ ++#define P_ENCP_VIDEO_OFLD_VOAV_OFST VCBUS_REG_ADDR(ENCP_VIDEO_OFLD_VOAV_OFST) ++#define ENCP_VIDEO_MATRIX_CB 0x1bbb /* register.h:8138 */ ++#define P_ENCP_VIDEO_MATRIX_CB VCBUS_REG_ADDR(ENCP_VIDEO_MATRIX_CB) ++#define ENCP_VIDEO_MATRIX_CR 0x1bbc /* register.h:8139 */ ++#define P_ENCP_VIDEO_MATRIX_CR VCBUS_REG_ADDR(ENCP_VIDEO_MATRIX_CR) ++#define ENCP_VIDEO_RGBIN_CTRL 0x1bbd /* register.h:8140 */ ++#define P_ENCP_VIDEO_RGBIN_CTRL VCBUS_REG_ADDR(ENCP_VIDEO_RGBIN_CTRL) ++#define ENCP_MACV_BLANKY_VAL 0x1bc0 /* register.h:8142 */ ++#define P_ENCP_MACV_BLANKY_VAL VCBUS_REG_ADDR(ENCP_MACV_BLANKY_VAL) ++#define ENCP_MACV_MAXY_VAL 0x1bc1 /* register.h:8143 */ ++#define P_ENCP_MACV_MAXY_VAL VCBUS_REG_ADDR(ENCP_MACV_MAXY_VAL) ++#define ENCP_MACV_1ST_PSSYNC_STRT 0x1bc2 /* register.h:8144 */ ++#define P_ENCP_MACV_1ST_PSSYNC_STRT VCBUS_REG_ADDR(ENCP_MACV_1ST_PSSYNC_STRT) ++#define ENCP_MACV_PSSYNC_STRT 0x1bc3 /* register.h:8145 */ ++#define P_ENCP_MACV_PSSYNC_STRT VCBUS_REG_ADDR(ENCP_MACV_PSSYNC_STRT) ++#define ENCP_MACV_AGC_STRT 0x1bc4 /* register.h:8146 */ ++#define P_ENCP_MACV_AGC_STRT VCBUS_REG_ADDR(ENCP_MACV_AGC_STRT) ++#define ENCP_MACV_AGC_END 0x1bc5 /* register.h:8147 */ ++#define P_ENCP_MACV_AGC_END VCBUS_REG_ADDR(ENCP_MACV_AGC_END) ++#define ENCP_MACV_WAVE_END 0x1bc6 /* register.h:8148 */ ++#define P_ENCP_MACV_WAVE_END VCBUS_REG_ADDR(ENCP_MACV_WAVE_END) ++#define ENCP_MACV_STRTLINE 0x1bc7 /* register.h:8149 */ ++#define P_ENCP_MACV_STRTLINE VCBUS_REG_ADDR(ENCP_MACV_STRTLINE) ++#define ENCP_MACV_ENDLINE 0x1bc8 /* register.h:8150 */ ++#define P_ENCP_MACV_ENDLINE VCBUS_REG_ADDR(ENCP_MACV_ENDLINE) ++#define ENCP_MACV_TS_CNT_MAX_L 0x1bc9 /* register.h:8151 */ ++#define P_ENCP_MACV_TS_CNT_MAX_L VCBUS_REG_ADDR(ENCP_MACV_TS_CNT_MAX_L) ++#define ENCP_MACV_TS_CNT_MAX_H 0x1bca /* register.h:8152 */ ++#define P_ENCP_MACV_TS_CNT_MAX_H VCBUS_REG_ADDR(ENCP_MACV_TS_CNT_MAX_H) ++#define ENCP_MACV_TIME_DOWN 0x1bcb /* register.h:8153 */ ++#define P_ENCP_MACV_TIME_DOWN VCBUS_REG_ADDR(ENCP_MACV_TIME_DOWN) ++#define ENCP_MACV_TIME_LO 0x1bcc /* register.h:8154 */ ++#define P_ENCP_MACV_TIME_LO VCBUS_REG_ADDR(ENCP_MACV_TIME_LO) ++#define ENCP_MACV_TIME_UP 0x1bcd /* register.h:8155 */ ++#define P_ENCP_MACV_TIME_UP VCBUS_REG_ADDR(ENCP_MACV_TIME_UP) ++#define ENCP_MACV_TIME_RST 0x1bce /* register.h:8156 */ ++#define P_ENCP_MACV_TIME_RST VCBUS_REG_ADDR(ENCP_MACV_TIME_RST) ++#define ENCP_VBI_CTRL 0x1bd0 /* register.h:8158 */ ++#define P_ENCP_VBI_CTRL VCBUS_REG_ADDR(ENCP_VBI_CTRL) ++#define ENCP_VBI_SETTING 0x1bd1 /* register.h:8159 */ ++#define P_ENCP_VBI_SETTING VCBUS_REG_ADDR(ENCP_VBI_SETTING) ++#define ENCP_VBI_BEGIN 0x1bd2 /* register.h:8160 */ ++#define P_ENCP_VBI_BEGIN VCBUS_REG_ADDR(ENCP_VBI_BEGIN) ++#define ENCP_VBI_WIDTH 0x1bd3 /* register.h:8161 */ ++#define P_ENCP_VBI_WIDTH VCBUS_REG_ADDR(ENCP_VBI_WIDTH) ++#define ENCP_VBI_HVAL 0x1bd4 /* register.h:8162 */ ++#define P_ENCP_VBI_HVAL VCBUS_REG_ADDR(ENCP_VBI_HVAL) ++#define ENCP_VBI_DATA0 0x1bd5 /* register.h:8163 */ ++#define P_ENCP_VBI_DATA0 VCBUS_REG_ADDR(ENCP_VBI_DATA0) ++#define ENCP_VBI_DATA1 0x1bd6 /* register.h:8164 */ ++#define P_ENCP_VBI_DATA1 VCBUS_REG_ADDR(ENCP_VBI_DATA1) ++ ++#define ENCI_VIDEO_MODE 0x1b00 /* register.h:8185 */ ++#define P_ENCI_VIDEO_MODE VCBUS_REG_ADDR(ENCI_VIDEO_MODE) ++#define ENCI_VIDEO_MODE_ADV 0x1b01 /* register.h:8186 */ ++#define P_ENCI_VIDEO_MODE_ADV VCBUS_REG_ADDR(ENCI_VIDEO_MODE_ADV) ++#define ENCI_VIDEO_FSC_ADJ 0x1b02 /* register.h:8187 */ ++#define P_ENCI_VIDEO_FSC_ADJ VCBUS_REG_ADDR(ENCI_VIDEO_FSC_ADJ) ++#define ENCI_VIDEO_BRIGHT 0x1b03 /* register.h:8188 */ ++#define P_ENCI_VIDEO_BRIGHT VCBUS_REG_ADDR(ENCI_VIDEO_BRIGHT) ++#define ENCI_VIDEO_CONT 0x1b04 /* register.h:8189 */ ++#define P_ENCI_VIDEO_CONT VCBUS_REG_ADDR(ENCI_VIDEO_CONT) ++#define ENCI_VIDEO_SAT 0x1b05 /* register.h:8190 */ ++#define P_ENCI_VIDEO_SAT VCBUS_REG_ADDR(ENCI_VIDEO_SAT) ++#define ENCI_VIDEO_HUE 0x1b06 /* register.h:8191 */ ++#define P_ENCI_VIDEO_HUE VCBUS_REG_ADDR(ENCI_VIDEO_HUE) ++#define ENCI_VIDEO_SCH 0x1b07 /* register.h:8192 */ ++#define P_ENCI_VIDEO_SCH VCBUS_REG_ADDR(ENCI_VIDEO_SCH) ++#define ENCI_SYNC_MODE 0x1b08 /* register.h:8193 */ ++#define P_ENCI_SYNC_MODE VCBUS_REG_ADDR(ENCI_SYNC_MODE) ++#define ENCI_SYNC_CTRL 0x1b09 /* register.h:8194 */ ++#define P_ENCI_SYNC_CTRL VCBUS_REG_ADDR(ENCI_SYNC_CTRL) ++#define ENCI_SYNC_HSO_BEGIN 0x1b0a /* register.h:8195 */ ++#define P_ENCI_SYNC_HSO_BEGIN VCBUS_REG_ADDR(ENCI_SYNC_HSO_BEGIN) ++#define ENCI_SYNC_HSO_END 0x1b0b /* register.h:8196 */ ++#define P_ENCI_SYNC_HSO_END VCBUS_REG_ADDR(ENCI_SYNC_HSO_END) ++#define ENCI_SYNC_VSO_EVN 0x1b0c /* register.h:8197 */ ++#define P_ENCI_SYNC_VSO_EVN VCBUS_REG_ADDR(ENCI_SYNC_VSO_EVN) ++#define ENCI_SYNC_VSO_ODD 0x1b0d /* register.h:8198 */ ++#define P_ENCI_SYNC_VSO_ODD VCBUS_REG_ADDR(ENCI_SYNC_VSO_ODD) ++#define ENCI_SYNC_VSO_EVNLN 0x1b0e /* register.h:8199 */ ++#define P_ENCI_SYNC_VSO_EVNLN VCBUS_REG_ADDR(ENCI_SYNC_VSO_EVNLN) ++#define ENCI_SYNC_VSO_ODDLN 0x1b0f /* register.h:8200 */ ++#define P_ENCI_SYNC_VSO_ODDLN VCBUS_REG_ADDR(ENCI_SYNC_VSO_ODDLN) ++#define ENCI_SYNC_HOFFST 0x1b10 /* register.h:8201 */ ++#define P_ENCI_SYNC_HOFFST VCBUS_REG_ADDR(ENCI_SYNC_HOFFST) ++#define ENCI_SYNC_VOFFST 0x1b11 /* register.h:8202 */ ++#define P_ENCI_SYNC_VOFFST VCBUS_REG_ADDR(ENCI_SYNC_VOFFST) ++#define ENCI_SYNC_ADJ 0x1b12 /* register.h:8203 */ ++#define P_ENCI_SYNC_ADJ VCBUS_REG_ADDR(ENCI_SYNC_ADJ) ++#define ENCI_RGB_SETTING 0x1b13 /* register.h:8204 */ ++#define P_ENCI_RGB_SETTING VCBUS_REG_ADDR(ENCI_RGB_SETTING) ++#define ENCI_DE_H_BEGIN 0x1b16 /* register.h:8207 */ ++#define P_ENCI_DE_H_BEGIN VCBUS_REG_ADDR(ENCI_DE_H_BEGIN) ++#define ENCI_DE_H_END 0x1b17 /* register.h:8208 */ ++#define P_ENCI_DE_H_END VCBUS_REG_ADDR(ENCI_DE_H_END) ++#define ENCI_DE_V_BEGIN_EVEN 0x1b18 /* register.h:8209 */ ++#define P_ENCI_DE_V_BEGIN_EVEN VCBUS_REG_ADDR(ENCI_DE_V_BEGIN_EVEN) ++#define ENCI_DE_V_END_EVEN 0x1b19 /* register.h:8210 */ ++#define P_ENCI_DE_V_END_EVEN VCBUS_REG_ADDR(ENCI_DE_V_END_EVEN) ++#define ENCI_DE_V_BEGIN_ODD 0x1b1a /* register.h:8211 */ ++#define P_ENCI_DE_V_BEGIN_ODD VCBUS_REG_ADDR(ENCI_DE_V_BEGIN_ODD) ++#define ENCI_DE_V_END_ODD 0x1b1b /* register.h:8212 */ ++#define P_ENCI_DE_V_END_ODD VCBUS_REG_ADDR(ENCI_DE_V_END_ODD) ++#define ENCI_VBI_SETTING 0x1b20 /* register.h:8213 */ ++#define P_ENCI_VBI_SETTING VCBUS_REG_ADDR(ENCI_VBI_SETTING) ++#define ENCI_VBI_CCDT_EVN 0x1b21 /* register.h:8214 */ ++#define P_ENCI_VBI_CCDT_EVN VCBUS_REG_ADDR(ENCI_VBI_CCDT_EVN) ++#define ENCI_VBI_CCDT_ODD 0x1b22 /* register.h:8215 */ ++#define P_ENCI_VBI_CCDT_ODD VCBUS_REG_ADDR(ENCI_VBI_CCDT_ODD) ++#define ENCI_VBI_CC525_LN 0x1b23 /* register.h:8216 */ ++#define P_ENCI_VBI_CC525_LN VCBUS_REG_ADDR(ENCI_VBI_CC525_LN) ++#define ENCI_VBI_CC625_LN 0x1b24 /* register.h:8217 */ ++#define P_ENCI_VBI_CC625_LN VCBUS_REG_ADDR(ENCI_VBI_CC625_LN) ++#define ENCI_VBI_WSSDT 0x1b25 /* register.h:8218 */ ++#define P_ENCI_VBI_WSSDT VCBUS_REG_ADDR(ENCI_VBI_WSSDT) ++#define ENCI_VBI_WSS_LN 0x1b26 /* register.h:8219 */ ++#define P_ENCI_VBI_WSS_LN VCBUS_REG_ADDR(ENCI_VBI_WSS_LN) ++#define ENCI_VBI_CGMSDT_L 0x1b27 /* register.h:8220 */ ++#define P_ENCI_VBI_CGMSDT_L VCBUS_REG_ADDR(ENCI_VBI_CGMSDT_L) ++#define ENCI_VBI_CGMSDT_H 0x1b28 /* register.h:8221 */ ++#define P_ENCI_VBI_CGMSDT_H VCBUS_REG_ADDR(ENCI_VBI_CGMSDT_H) ++#define ENCI_VBI_CGMS_LN 0x1b29 /* register.h:8222 */ ++#define P_ENCI_VBI_CGMS_LN VCBUS_REG_ADDR(ENCI_VBI_CGMS_LN) ++#define ENCI_VBI_TTX_HTIME 0x1b2a /* register.h:8223 */ ++#define P_ENCI_VBI_TTX_HTIME VCBUS_REG_ADDR(ENCI_VBI_TTX_HTIME) ++#define ENCI_VBI_TTX_LN 0x1b2b /* register.h:8224 */ ++#define P_ENCI_VBI_TTX_LN VCBUS_REG_ADDR(ENCI_VBI_TTX_LN) ++#define ENCI_VBI_TTXDT0 0x1b2c /* register.h:8225 */ ++#define P_ENCI_VBI_TTXDT0 VCBUS_REG_ADDR(ENCI_VBI_TTXDT0) ++#define ENCI_VBI_TTXDT1 0x1b2d /* register.h:8226 */ ++#define P_ENCI_VBI_TTXDT1 VCBUS_REG_ADDR(ENCI_VBI_TTXDT1) ++#define ENCI_VBI_TTXDT2 0x1b2e /* register.h:8227 */ ++#define P_ENCI_VBI_TTXDT2 VCBUS_REG_ADDR(ENCI_VBI_TTXDT2) ++#define ENCI_VBI_TTXDT3 0x1b2f /* register.h:8228 */ ++#define P_ENCI_VBI_TTXDT3 VCBUS_REG_ADDR(ENCI_VBI_TTXDT3) ++#define ENCI_MACV_N0 0x1b30 /* register.h:8229 */ ++#define P_ENCI_MACV_N0 VCBUS_REG_ADDR(ENCI_MACV_N0) ++#define ENCI_MACV_N1 0x1b31 /* register.h:8230 */ ++#define P_ENCI_MACV_N1 VCBUS_REG_ADDR(ENCI_MACV_N1) ++#define ENCI_MACV_N2 0x1b32 /* register.h:8231 */ ++#define P_ENCI_MACV_N2 VCBUS_REG_ADDR(ENCI_MACV_N2) ++#define ENCI_MACV_N3 0x1b33 /* register.h:8232 */ ++#define P_ENCI_MACV_N3 VCBUS_REG_ADDR(ENCI_MACV_N3) ++#define ENCI_MACV_N4 0x1b34 /* register.h:8233 */ ++#define P_ENCI_MACV_N4 VCBUS_REG_ADDR(ENCI_MACV_N4) ++#define ENCI_MACV_N5 0x1b35 /* register.h:8234 */ ++#define P_ENCI_MACV_N5 VCBUS_REG_ADDR(ENCI_MACV_N5) ++#define ENCI_MACV_N6 0x1b36 /* register.h:8235 */ ++#define P_ENCI_MACV_N6 VCBUS_REG_ADDR(ENCI_MACV_N6) ++#define ENCI_MACV_N7 0x1b37 /* register.h:8236 */ ++#define P_ENCI_MACV_N7 VCBUS_REG_ADDR(ENCI_MACV_N7) ++#define ENCI_MACV_N8 0x1b38 /* register.h:8237 */ ++#define P_ENCI_MACV_N8 VCBUS_REG_ADDR(ENCI_MACV_N8) ++#define ENCI_MACV_N9 0x1b39 /* register.h:8238 */ ++#define P_ENCI_MACV_N9 VCBUS_REG_ADDR(ENCI_MACV_N9) ++#define ENCI_MACV_N10 0x1b3a /* register.h:8239 */ ++#define P_ENCI_MACV_N10 VCBUS_REG_ADDR(ENCI_MACV_N10) ++#define ENCI_MACV_N11 0x1b3b /* register.h:8240 */ ++#define P_ENCI_MACV_N11 VCBUS_REG_ADDR(ENCI_MACV_N11) ++#define ENCI_MACV_N12 0x1b3c /* register.h:8241 */ ++#define P_ENCI_MACV_N12 VCBUS_REG_ADDR(ENCI_MACV_N12) ++#define ENCI_MACV_N13 0x1b3d /* register.h:8242 */ ++#define P_ENCI_MACV_N13 VCBUS_REG_ADDR(ENCI_MACV_N13) ++#define ENCI_MACV_N14 0x1b3e /* register.h:8243 */ ++#define P_ENCI_MACV_N14 VCBUS_REG_ADDR(ENCI_MACV_N14) ++#define ENCI_MACV_N15 0x1b3f /* register.h:8244 */ ++#define P_ENCI_MACV_N15 VCBUS_REG_ADDR(ENCI_MACV_N15) ++#define ENCI_MACV_N16 0x1b40 /* register.h:8245 */ ++#define P_ENCI_MACV_N16 VCBUS_REG_ADDR(ENCI_MACV_N16) ++#define ENCI_MACV_N17 0x1b41 /* register.h:8246 */ ++#define P_ENCI_MACV_N17 VCBUS_REG_ADDR(ENCI_MACV_N17) ++#define ENCI_MACV_N18 0x1b42 /* register.h:8247 */ ++#define P_ENCI_MACV_N18 VCBUS_REG_ADDR(ENCI_MACV_N18) ++#define ENCI_MACV_N19 0x1b43 /* register.h:8248 */ ++#define P_ENCI_MACV_N19 VCBUS_REG_ADDR(ENCI_MACV_N19) ++#define ENCI_MACV_N20 0x1b44 /* register.h:8249 */ ++#define P_ENCI_MACV_N20 VCBUS_REG_ADDR(ENCI_MACV_N20) ++#define ENCI_MACV_N21 0x1b45 /* register.h:8250 */ ++#define P_ENCI_MACV_N21 VCBUS_REG_ADDR(ENCI_MACV_N21) ++#define ENCI_MACV_N22 0x1b46 /* register.h:8251 */ ++#define P_ENCI_MACV_N22 VCBUS_REG_ADDR(ENCI_MACV_N22) ++#define ENCI_DBG_PX_RST 0x1b48 /* register.h:8253 */ ++#define P_ENCI_DBG_PX_RST VCBUS_REG_ADDR(ENCI_DBG_PX_RST) ++#define ENCI_DBG_FLDLN_RST 0x1b49 /* register.h:8254 */ ++#define P_ENCI_DBG_FLDLN_RST VCBUS_REG_ADDR(ENCI_DBG_FLDLN_RST) ++#define ENCI_DBG_PX_INT 0x1b4a /* register.h:8255 */ ++#define P_ENCI_DBG_PX_INT VCBUS_REG_ADDR(ENCI_DBG_PX_INT) ++#define ENCI_DBG_FLDLN_INT 0x1b4b /* register.h:8256 */ ++#define P_ENCI_DBG_FLDLN_INT VCBUS_REG_ADDR(ENCI_DBG_FLDLN_INT) ++#define ENCI_DBG_MAXPX 0x1b4c /* register.h:8257 */ ++#define P_ENCI_DBG_MAXPX VCBUS_REG_ADDR(ENCI_DBG_MAXPX) ++#define ENCI_DBG_MAXLN 0x1b4d /* register.h:8258 */ ++#define P_ENCI_DBG_MAXLN VCBUS_REG_ADDR(ENCI_DBG_MAXLN) ++#define ENCI_MACV_MAX_AMP 0x1b50 /* register.h:8259 */ ++#define P_ENCI_MACV_MAX_AMP VCBUS_REG_ADDR(ENCI_MACV_MAX_AMP) ++#define ENCI_MACV_PULSE_LO 0x1b51 /* register.h:8260 */ ++#define P_ENCI_MACV_PULSE_LO VCBUS_REG_ADDR(ENCI_MACV_PULSE_LO) ++#define ENCI_MACV_PULSE_HI 0x1b52 /* register.h:8261 */ ++#define P_ENCI_MACV_PULSE_HI VCBUS_REG_ADDR(ENCI_MACV_PULSE_HI) ++#define ENCI_MACV_BKP_MAX 0x1b53 /* register.h:8262 */ ++#define P_ENCI_MACV_BKP_MAX VCBUS_REG_ADDR(ENCI_MACV_BKP_MAX) ++#define ENCI_CFILT_CTRL 0x1b54 /* register.h:8263 */ ++#define P_ENCI_CFILT_CTRL VCBUS_REG_ADDR(ENCI_CFILT_CTRL) ++#define ENCI_CFILT7 0x1b55 /* register.h:8264 */ ++#define P_ENCI_CFILT7 VCBUS_REG_ADDR(ENCI_CFILT7) ++#define ENCI_YC_DELAY 0x1b56 /* register.h:8265 */ ++#define P_ENCI_YC_DELAY VCBUS_REG_ADDR(ENCI_YC_DELAY) ++#define ENCI_VIDEO_EN 0x1b57 /* register.h:8266 */ ++#define P_ENCI_VIDEO_EN VCBUS_REG_ADDR(ENCI_VIDEO_EN) ++#define VENC_VIDEO_PROG_MODE 0x1b68 /* /../ucode/register.h:8023 */ ++#define P_VENC_VIDEO_PROG_MODE VCBUS_REG_ADDR(VENC_VIDEO_PROG_MODE) ++ ++#define ENCI_DVI_HSO_BEGIN 0x1c00 /* register.h:8280 */ ++#define P_ENCI_DVI_HSO_BEGIN VCBUS_REG_ADDR(ENCI_DVI_HSO_BEGIN) ++#define ENCI_DVI_HSO_END 0x1c01 /* register.h:8281 */ ++#define P_ENCI_DVI_HSO_END VCBUS_REG_ADDR(ENCI_DVI_HSO_END) ++#define ENCI_DVI_VSO_BLINE_EVN 0x1c02 /* register.h:8282 */ ++#define P_ENCI_DVI_VSO_BLINE_EVN VCBUS_REG_ADDR(ENCI_DVI_VSO_BLINE_EVN) ++#define ENCI_DVI_VSO_BLINE_ODD 0x1c03 /* register.h:8283 */ ++#define P_ENCI_DVI_VSO_BLINE_ODD VCBUS_REG_ADDR(ENCI_DVI_VSO_BLINE_ODD) ++#define ENCI_DVI_VSO_ELINE_EVN 0x1c04 /* register.h:8284 */ ++#define P_ENCI_DVI_VSO_ELINE_EVN VCBUS_REG_ADDR(ENCI_DVI_VSO_ELINE_EVN) ++#define ENCI_DVI_VSO_ELINE_ODD 0x1c05 /* register.h:8285 */ ++#define P_ENCI_DVI_VSO_ELINE_ODD VCBUS_REG_ADDR(ENCI_DVI_VSO_ELINE_ODD) ++#define ENCI_DVI_VSO_BEGIN_EVN 0x1c06 /* register.h:8286 */ ++#define P_ENCI_DVI_VSO_BEGIN_EVN VCBUS_REG_ADDR(ENCI_DVI_VSO_BEGIN_EVN) ++#define ENCI_DVI_VSO_BEGIN_ODD 0x1c07 /* register.h:8287 */ ++#define P_ENCI_DVI_VSO_BEGIN_ODD VCBUS_REG_ADDR(ENCI_DVI_VSO_BEGIN_ODD) ++#define ENCI_DVI_VSO_END_EVN 0x1c08 /* register.h:8288 */ ++#define P_ENCI_DVI_VSO_END_EVN VCBUS_REG_ADDR(ENCI_DVI_VSO_END_EVN) ++#define ENCI_DVI_VSO_END_ODD 0x1c09 /* register.h:8289 */ ++#define P_ENCI_DVI_VSO_END_ODD VCBUS_REG_ADDR(ENCI_DVI_VSO_END_ODD) ++#define ENCI_CFILT_CTRL2 0x1c0a /* register.h:8295 */ ++#define P_ENCI_CFILT_CTRL2 VCBUS_REG_ADDR(ENCI_CFILT_CTRL2) ++#define ENCI_DACSEL_0 0x1c0b /* register.h:8296 */ ++#define P_ENCI_DACSEL_0 VCBUS_REG_ADDR(ENCI_DACSEL_0) ++#define ENCI_DACSEL_1 0x1c0c /* register.h:8297 */ ++#define P_ENCI_DACSEL_1 VCBUS_REG_ADDR(ENCI_DACSEL_1) ++#define ENCP_DACSEL_0 0x1c0d /* register.h:8298 */ ++#define P_ENCP_DACSEL_0 VCBUS_REG_ADDR(ENCP_DACSEL_0) ++#define ENCP_DACSEL_1 0x1c0e /* register.h:8299 */ ++#define P_ENCP_DACSEL_1 VCBUS_REG_ADDR(ENCP_DACSEL_1) ++#define ENCP_MAX_LINE_SWITCH_POINT 0x1c0f /* register.h:8300 */ ++#define P_ENCP_MAX_LINE_SWITCH_POINT VCBUS_REG_ADDR(ENCP_MAX_LINE_SWITCH_POINT) ++#define ENCI_TST_EN 0x1c10 /* register.h:8301 */ ++#define P_ENCI_TST_EN VCBUS_REG_ADDR(ENCI_TST_EN) ++#define ENCI_TST_MDSEL 0x1c11 /* register.h:8302 */ ++#define P_ENCI_TST_MDSEL VCBUS_REG_ADDR(ENCI_TST_MDSEL) ++#define ENCI_TST_Y 0x1c12 /* register.h:8303 */ ++#define P_ENCI_TST_Y VCBUS_REG_ADDR(ENCI_TST_Y) ++#define ENCI_TST_CB 0x1c13 /* register.h:8304 */ ++#define P_ENCI_TST_CB VCBUS_REG_ADDR(ENCI_TST_CB) ++#define ENCI_TST_CR 0x1c14 /* register.h:8305 */ ++#define P_ENCI_TST_CR VCBUS_REG_ADDR(ENCI_TST_CR) ++#define ENCI_TST_CLRBAR_STRT 0x1c15 /* register.h:8306 */ ++#define P_ENCI_TST_CLRBAR_STRT VCBUS_REG_ADDR(ENCI_TST_CLRBAR_STRT) ++#define ENCI_TST_CLRBAR_WIDTH 0x1c16 /* register.h:8307 */ ++#define P_ENCI_TST_CLRBAR_WIDTH VCBUS_REG_ADDR(ENCI_TST_CLRBAR_WIDTH) ++#define ENCI_TST_VDCNT_STSET 0x1c17 /* register.h:8308 */ ++#define P_ENCI_TST_VDCNT_STSET VCBUS_REG_ADDR(ENCI_TST_VDCNT_STSET) ++#define ENCI_VFIFO2VD_CTL 0x1c18 /* register.h:8313 */ ++#define P_ENCI_VFIFO2VD_CTL VCBUS_REG_ADDR(ENCI_VFIFO2VD_CTL) ++#define ENCI_VFIFO2VD_PIXEL_START 0x1c19 /* register.h:8315 */ ++#define P_ENCI_VFIFO2VD_PIXEL_START \ ++ VCBUS_REG_ADDR(ENCI_VFIFO2VD_PIXEL_START) ++#define ENCI_VFIFO2VD_PIXEL_END 0x1c1a /* register.h:8317 */ ++#define P_ENCI_VFIFO2VD_PIXEL_END VCBUS_REG_ADDR(ENCI_VFIFO2VD_PIXEL_END) ++#define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b /* register.h:8319 */ ++#define P_ENCI_VFIFO2VD_LINE_TOP_START \ ++ VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_TOP_START) ++#define ENCI_VFIFO2VD_LINE_TOP_END 0x1c1c /* register.h:8321 */ ++#define P_ENCI_VFIFO2VD_LINE_TOP_END \ ++ VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_TOP_END) ++#define ENCI_VFIFO2VD_LINE_BOT_START 0x1c1d /* register.h:8323 */ ++#define P_ENCI_VFIFO2VD_LINE_BOT_START \ ++ VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_BOT_START) ++#define ENCI_VFIFO2VD_LINE_BOT_END 0x1c1e /* register.h:8325 */ ++#define P_ENCI_VFIFO2VD_LINE_BOT_END \ ++ VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_BOT_END) ++#define ENCI_VFIFO2VD_CTL2 0x1c1f /* register.h:8326 */ ++#define P_ENCI_VFIFO2VD_CTL2 VCBUS_REG_ADDR(ENCI_VFIFO2VD_CTL2) ++ ++#define ENCP_DVI_HSO_BEGIN 0x1c30 /* register.h:8354 */ ++#define P_ENCP_DVI_HSO_BEGIN VCBUS_REG_ADDR(ENCP_DVI_HSO_BEGIN) ++#define ENCP_DVI_HSO_END 0x1c31 /* register.h:8355 */ ++#define P_ENCP_DVI_HSO_END VCBUS_REG_ADDR(ENCP_DVI_HSO_END) ++#define ENCP_DVI_VSO_BLINE_EVN 0x1c32 /* register.h:8356 */ ++#define P_ENCP_DVI_VSO_BLINE_EVN VCBUS_REG_ADDR(ENCP_DVI_VSO_BLINE_EVN) ++#define ENCP_DVI_VSO_BLINE_ODD 0x1c33 /* register.h:8357 */ ++#define P_ENCP_DVI_VSO_BLINE_ODD VCBUS_REG_ADDR(ENCP_DVI_VSO_BLINE_ODD) ++#define ENCP_DVI_VSO_ELINE_EVN 0x1c34 /* register.h:8358 */ ++#define P_ENCP_DVI_VSO_ELINE_EVN VCBUS_REG_ADDR(ENCP_DVI_VSO_ELINE_EVN) ++#define ENCP_DVI_VSO_ELINE_ODD 0x1c35 /* register.h:8359 */ ++#define P_ENCP_DVI_VSO_ELINE_ODD VCBUS_REG_ADDR(ENCP_DVI_VSO_ELINE_ODD) ++#define ENCP_DVI_VSO_BEGIN_EVN 0x1c36 /* register.h:8360 */ ++#define P_ENCP_DVI_VSO_BEGIN_EVN VCBUS_REG_ADDR(ENCP_DVI_VSO_BEGIN_EVN) ++#define ENCP_DVI_VSO_BEGIN_ODD 0x1c37 /* register.h:8361 */ ++#define P_ENCP_DVI_VSO_BEGIN_ODD VCBUS_REG_ADDR(ENCP_DVI_VSO_BEGIN_ODD) ++#define ENCP_DVI_VSO_END_EVN 0x1c38 /* register.h:8362 */ ++#define P_ENCP_DVI_VSO_END_EVN VCBUS_REG_ADDR(ENCP_DVI_VSO_END_EVN) ++#define ENCP_DVI_VSO_END_ODD 0x1c39 /* register.h:8363 */ ++#define P_ENCP_DVI_VSO_END_ODD VCBUS_REG_ADDR(ENCP_DVI_VSO_END_ODD) ++#define ENCP_DE_H_BEGIN 0x1c3a /* register.h:8364 */ ++#define P_ENCP_DE_H_BEGIN VCBUS_REG_ADDR(ENCP_DE_H_BEGIN) ++#define ENCP_DE_H_END 0x1c3b /* register.h:8365 */ ++#define P_ENCP_DE_H_END VCBUS_REG_ADDR(ENCP_DE_H_END) ++#define ENCP_DE_V_BEGIN_EVEN 0x1c3c /* register.h:8366 */ ++#define P_ENCP_DE_V_BEGIN_EVEN VCBUS_REG_ADDR(ENCP_DE_V_BEGIN_EVEN) ++#define ENCP_DE_V_END_EVEN 0x1c3d /* register.h:8367 */ ++#define P_ENCP_DE_V_END_EVEN VCBUS_REG_ADDR(ENCP_DE_V_END_EVEN) ++#define ENCP_DE_V_BEGIN_ODD 0x1c3e /* register.h:8368 */ ++#define P_ENCP_DE_V_BEGIN_ODD VCBUS_REG_ADDR(ENCP_DE_V_BEGIN_ODD) ++#define ENCP_DE_V_END_ODD 0x1c3f /* register.h:8369 */ ++#define P_ENCP_DE_V_END_ODD VCBUS_REG_ADDR(ENCP_DE_V_END_ODD) ++#define ENCI_SYNC_LINE_LENGTH 0x1c40 /* register.h:8372 */ ++#define P_ENCI_SYNC_LINE_LENGTH VCBUS_REG_ADDR(ENCI_SYNC_LINE_LENGTH) ++#define ENCI_SYNC_PIXEL_EN 0x1c41 /* register.h:8375 */ ++#define P_ENCI_SYNC_PIXEL_EN VCBUS_REG_ADDR(ENCI_SYNC_PIXEL_EN) ++#define ENCI_SYNC_TO_LINE_EN 0x1c42 /* register.h:8382 */ ++#define P_ENCI_SYNC_TO_LINE_EN VCBUS_REG_ADDR(ENCI_SYNC_TO_LINE_EN) ++#define ENCI_SYNC_TO_PIXEL 0x1c43 /* register.h:8384 */ ++#define P_ENCI_SYNC_TO_PIXEL VCBUS_REG_ADDR(ENCI_SYNC_TO_PIXEL) ++#define ENCP_SYNC_LINE_LENGTH 0x1c44 /* register.h:8387 */ ++#define P_ENCP_SYNC_LINE_LENGTH VCBUS_REG_ADDR(ENCP_SYNC_LINE_LENGTH) ++#define ENCP_SYNC_PIXEL_EN 0x1c45 /* register.h:8390 */ ++#define P_ENCP_SYNC_PIXEL_EN VCBUS_REG_ADDR(ENCP_SYNC_PIXEL_EN) ++#define ENCP_SYNC_TO_LINE_EN 0x1c46 /* register.h:8397 */ ++#define P_ENCP_SYNC_TO_LINE_EN VCBUS_REG_ADDR(ENCP_SYNC_TO_LINE_EN) ++#define ENCP_SYNC_TO_PIXEL 0x1c47 /* register.h:8399 */ ++#define P_ENCP_SYNC_TO_PIXEL VCBUS_REG_ADDR(ENCP_SYNC_TO_PIXEL) ++ ++#define VPP_POSTBLEND_H_SIZE 0x1d21 ++#define P_VPP_POSTBLEND_H_SIZE VCBUS_REG_ADDR(VPP_POSTBLEND_H_SIZE) ++ ++ ++#define VPU_VIU_VENC_MUX_CTRL 0x271a /* register.h:9214 */ ++#define P_VPU_VIU_VENC_MUX_CTRL VCBUS_REG_ADDR(VPU_VIU_VENC_MUX_CTRL) ++#define VPU_HDMI_SETTING 0x271b /* register.h:9229 */ ++#define P_VPU_HDMI_SETTING VCBUS_REG_ADDR(VPU_HDMI_SETTING) ++ ++#define VPU_HDMI_DATA_OVR 0x2727 /* register.h:9270 */ ++#define P_VPU_HDMI_DATA_OVR VCBUS_REG_ADDR(VPU_HDMI_DATA_OVR) ++#define VPU_HDMI_FMT_CTRL 0x2743 ++#define P_VPU_HDMI_FMT_CTRL VCBUS_REG_ADDR(VPU_HDMI_FMT_CTRL) ++/* For GXM and later */ ++#define VPU_HDMI_DITH_CNTL 0x27fc ++#define P_VPU_HDMI_DITH_CNTL VCBUS_REG_ADDR(VPU_HDMI_DITH_CNTL) ++ ++#endif +diff --git a/include/amlogic/media/vout/lcd/aml_lcd.h b/include/amlogic/media/vout/lcd/aml_lcd.h +new file mode 100644 +index 00000000000..ef3334a5fb0 +--- /dev/null ++++ b/include/amlogic/media/vout/lcd/aml_lcd.h +@@ -0,0 +1,168 @@ ++/* ++ * include/amlogic/media/vout/lcd/aml_lcd.h ++ * ++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++ */ ++ ++#ifndef INC_AML_LCD_H ++#define INC_AML_LCD_H ++ ++#include ++#include ++#include ++#ifdef CONFIG_AML_LCD_EXTERN ++#include ++#endif ++#ifdef CONFIG_AML_BL_EXTERN ++#include ++#endif ++ ++#define LCD_GPIO_MAX 0xff ++#define LCD_GPIO_OUTPUT_LOW 0 ++#define LCD_GPIO_OUTPUT_HIGH 1 ++#define LCD_GPIO_INPUT 2 ++ ++ ++#define LCD_EXT_I2C_BUS_0 0 //A ++#define LCD_EXT_I2C_BUS_1 1 //B ++#define LCD_EXT_I2C_BUS_2 2 //C ++#define LCD_EXT_I2C_BUS_3 3 //D ++#define LCD_EXT_I2C_BUS_4 4 //AO ++#define LCD_EXT_I2C_BUS_MAX 0xff ++ ++ ++#define LCD_EXT_I2C_BUS_INVALID 0xff ++#define LCD_EXT_I2C_ADDR_INVALID 0xff ++#define LCD_EXT_GPIO_INVALID 0xff ++ ++#define LCD_EXT_SPI_CLK_FREQ_DFT 10 /* unit: KHz */ ++ ++ ++#define LCD_EXT_CMD_TYPE_CMD_DELAY 0x00 ++#define LCD_EXT_CMD_TYPE_CMD2_DELAY 0x01 /* for i2c device 2nd addr */ ++#define LCD_EXT_CMD_TYPE_NONE 0x10 ++#define LCD_EXT_CMD_TYPE_CMD 0xc0 ++#define LCD_EXT_CMD_TYPE_CMD2 0xc1 /* for i2c device 2nd addr */ ++#define LCD_EXT_CMD_TYPE_GPIO 0xf0 ++#define LCD_EXT_CMD_TYPE_CHECK 0xfc ++#define LCD_EXT_CMD_TYPE_DELAY 0xfd ++#define LCD_EXT_CMD_TYPE_END 0xff ++ ++#define LCD_EXT_CMD_SIZE_DYNAMIC 0xff ++#define LCD_EXT_DYNAMIC_SIZE_INDEX 1 ++ ++ ++#define LCD_GPIO_NAME_MAX 15 ++struct lcd_cpu_gpio_s { ++ char name[LCD_GPIO_NAME_MAX]; ++ struct gpio_desc gpio; ++ int probe_flag; ++ int register_flag; ++}; ++ ++ ++#define Rsv_val 0xffffffff ++struct ext_lcd_config_s { ++ const char panel_type[20]; ++ int lcd_type; ++ unsigned char lcd_bits; ++ ++ unsigned short h_active; ++ unsigned short v_active; ++ unsigned short h_period; ++ unsigned short v_period; ++ unsigned short hsync_width; ++ unsigned short hsync_bp; ++ unsigned short hsync_pol; ++ unsigned short vsync_width; ++ unsigned short vsync_bp; ++ unsigned short vsync_pol; ++ ++ unsigned int customer_val_0; //fr_adjust_type ++ unsigned int customer_val_1; //ss_level ++ unsigned int customer_val_2; //clk_auto_generate ++ unsigned int customer_val_3; //pixel clock(unit in Hz) ++ unsigned int customer_val_4; ++ unsigned int customer_val_5; ++ unsigned int customer_val_6; ++ unsigned int customer_val_7; ++ unsigned int customer_val_8; ++ unsigned int customer_val_9; ++ ++ unsigned int if_attr_val0; ++ unsigned int if_attr_val1; ++ unsigned int if_attr_val2; ++ unsigned int if_attr_val3; ++ unsigned int if_attr_val4; ++ unsigned int if_attr_val5; ++ unsigned int if_attr_val6; ++ unsigned int if_attr_val7; ++ unsigned int if_attr_val8; ++ unsigned int if_attr_val9; ++ ++ unsigned char *cmd_init_on; ++ unsigned char *cmd_init_off; ++ struct lcd_power_step_s *power_on_step; ++ struct lcd_power_step_s *power_off_step; ++ ++ /* backlight */ ++ unsigned int level_default; ++ unsigned int level_max; ++ unsigned int level_min; ++ unsigned int level_mid; ++ unsigned int level_mid_mapping; ++ ++ unsigned int bl_method; ++ unsigned int bl_en_gpio; ++ unsigned short bl_en_gpio_on; ++ unsigned short bl_en_gpio_off; ++ unsigned short bl_power_on_delay; ++ unsigned short bl_power_off_delay; ++ ++ unsigned int pwm_method; ++ unsigned int pwm_port; ++ unsigned int pwm_freq; ++ unsigned int pwm_duty_max; ++ unsigned int pwm_duty_min; ++ unsigned int pwm_gpio; ++ unsigned int pwm_gpio_off; ++ ++ unsigned int pwm2_method; ++ unsigned int pwm2_port; ++ unsigned int pwm2_freq; ++ unsigned int pwm2_duty_max; ++ unsigned int pwm2_duty_min; ++ unsigned int pwm2_gpio; ++ unsigned int pwm2_gpio_off; ++ ++ unsigned int pwm_level_max; ++ unsigned int pwm_level_min; ++ unsigned int pwm2_level_max; ++ unsigned int pwm2_level_min; ++ ++ unsigned int pwm_on_delay; ++ unsigned int pwm_off_delay; ++ ++ /* backlight extern */ ++ unsigned int bl_ext_index; ++}; ++ ++#define LCD_NUM_MAX 10 ++ ++extern struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX]; ++ ++#endif /* INC_AML_LCD_H */ +diff --git a/include/amlogic/media/vout/lcd/bl_extern.h b/include/amlogic/media/vout/lcd/bl_extern.h +new file mode 100644 +index 00000000000..6604672cea4 +--- /dev/null ++++ b/include/amlogic/media/vout/lcd/bl_extern.h +@@ -0,0 +1,88 @@ ++/* ++ * include/amlogicmedia/vout/lcd/bl_extern.h ++ * ++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++ */ ++ ++#ifndef _INC_AML_BL_EXTERN_H_ ++#define _INC_AML_BL_EXTERN_H_ ++ ++enum bl_extern_type_e { ++ BL_EXTERN_I2C = 0, ++ BL_EXTERN_SPI, ++ BL_EXTERN_MIPI, ++ BL_EXTERN_MAX, ++}; ++ ++#define BL_EXTERN_I2C_BUS_A 0 ++#define BL_EXTERN_I2C_BUS_B 1 ++#define BL_EXTERN_I2C_BUS_C 2 ++#define BL_EXTERN_I2C_BUS_D 3 ++#define BL_EXTERN_I2C_BUS_AO 4 ++ ++#define BL_EXTERN_I2C_BUS_0 BL_EXTERN_I2C_BUS_A ++#define BL_EXTERN_I2C_BUS_1 BL_EXTERN_I2C_BUS_B ++#define BL_EXTERN_I2C_BUS_2 BL_EXTERN_I2C_BUS_C ++#define BL_EXTERN_I2C_BUS_3 BL_EXTERN_I2C_BUS_D ++#define BL_EXTERN_I2C_BUS_4 BL_EXTERN_I2C_BUS_AO ++#define BL_EXTERN_I2C_BUS_MAX 5 ++ ++#define BL_EXTERN_INIT_ON_MAX 200 ++#define BL_EXTERN_INIT_OFF_MAX 50 ++ ++#define BL_EXTERN_GPIO_NUM_MAX 6 ++#define BL_EXTERN_INDEX_INVALID 0xff ++#define BL_EXTERN_NAME_LEN_MAX 30 ++struct bl_extern_config_s { ++ unsigned char index; ++ char name[BL_EXTERN_NAME_LEN_MAX]; ++ enum bl_extern_type_e type; ++ unsigned char i2c_addr; ++ unsigned char i2c_bus; ++ unsigned int dim_min; ++ unsigned int dim_max; ++ ++ unsigned char init_loaded; ++ unsigned char cmd_size; ++ unsigned char *init_on; ++ unsigned char *init_off; ++ unsigned int init_on_cnt; ++ unsigned int init_off_cnt; ++}; ++ ++/* global API */ ++#define BL_EXT_DRIVER_MAX 10 ++struct aml_bl_extern_driver_s { ++ int (*power_on)(void); ++ int (*power_off)(void); ++ int (*set_level)(unsigned int level); ++ void (*config_print)(void); ++ int (*device_power_on)(void); ++ int (*device_power_off)(void); ++ int (*device_bri_update)(unsigned int level); ++ struct bl_extern_config_s *config; ++}; ++ ++extern struct aml_bl_extern_driver_s *aml_bl_extern_get_driver(void); ++extern int aml_bl_extern_device_load(const void *dt_blob, int index); ++extern struct bl_extern_config_s bl_extern_config_dtf; ++#ifdef CONFIG_AML_LCD_TABLET ++extern int dsi_write_cmd(unsigned char *payload); ++#endif ++ ++#endif ++ +diff --git a/include/amlogic/media/vout/lcd/bl_ldim.h b/include/amlogic/media/vout/lcd/bl_ldim.h +new file mode 100644 +index 00000000000..fb42eb3f71d +--- /dev/null ++++ b/include/amlogic/media/vout/lcd/bl_ldim.h +@@ -0,0 +1,118 @@ ++/* ++ * include/amlogic/media/vout/lcd/bl_ldim.h ++ * ++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++ */ ++ ++#ifndef INC_AML_BL_LDIM_H ++#define INC_AML_BL_LDIM_H ++ ++#include ++#include ++#include ++#include ++ ++enum ldim_dev_type_e { ++ LDIM_DEV_TYPE_NORMAL = 0, ++ LDIM_DEV_TYPE_SPI, ++ LDIM_DEV_TYPE_I2C, ++ LDIM_DEV_TYPE_MAX, ++}; ++ ++#define LDIM_INIT_ON_MAX 300 ++#define LDIM_INIT_OFF_MAX 20 ++ ++struct ldim_pinmux_ctrl_s { ++ char *name; ++ unsigned int pinmux_set[LCD_PINMUX_NUM][2]; ++ unsigned int pinmux_clr[LCD_PINMUX_NUM][2]; ++}; ++ ++struct ldim_config_s { ++ unsigned char row; ++ unsigned char col; ++}; ++ ++struct ldim_dev_config_s { ++ char name[20]; ++ char pinmux_name[20]; ++ unsigned char type; ++ int cs_hold_delay; ++ int cs_clk_delay; ++ int en_gpio; ++ int en_gpio_on; ++ int en_gpio_off; ++ int lamp_err_gpio; ++ unsigned char fault_check; ++ unsigned char write_check; ++ ++ unsigned int dim_min; ++ unsigned int dim_max; ++ ++ unsigned char init_loaded; ++ unsigned char cmd_size; ++ unsigned char *init_on; ++ unsigned char *init_off; ++ unsigned int init_on_cnt; ++ unsigned int init_off_cnt; ++ ++ unsigned char pinctrl_ver; ++ struct ldim_pinmux_ctrl_s *ldim_pinmux; ++ struct bl_pwm_config_s pwm_config; ++ char gpio_name[BL_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX]; ++ ++ unsigned short bl_regnum; ++}; ++ ++#define LDIM_SPI_NAME_MAX 30 ++struct ldim_spi_dev_info_s { ++ char modalias[20]; ++ char spi_name[LDIM_SPI_NAME_MAX]; ++ int mode; ++ int max_speed_hz; ++ int bus_num; ++ int chip_select; ++ int wordlen; ++ ++ struct spi_slave *spi; ++}; ++ ++/*******global API******/ ++struct aml_ldim_driver_s { ++ int valid_flag; ++ int dev_index; ++ struct ldim_config_s *ldim_conf; ++ struct ldim_dev_config_s *ldev_conf; ++ unsigned short *ldim_matrix_buf; ++ int (*power_on)(void); ++ int (*power_off)(void); ++ int (*set_level)(unsigned int level); ++ void (*config_print)(void); ++ int (*pinmux_ctrl)(int status); ++ void (*device_config_print)(void); ++ int (*device_power_on)(void); ++ int (*device_power_off)(void); ++ int (*device_bri_update)(unsigned short *buf, unsigned char len); ++ struct ldim_spi_dev_info_s *spi_info; ++}; ++ ++extern struct ldim_dev_config_s ldim_config_dft; ++ ++extern struct aml_ldim_driver_s *aml_ldim_get_driver(void); ++extern int aml_ldim_probe(char *dt_addr, int flag); /* flag: 0=dts, 1=bsp, 2=unifykey */ ++ ++#endif /* INC_AML_BL_LDIM_H */ +diff --git a/include/amlogic/media/vout/lcd/lcd_extern.h b/include/amlogic/media/vout/lcd/lcd_extern.h +new file mode 100644 +index 00000000000..dc6ef565a8a +--- /dev/null ++++ b/include/amlogic/media/vout/lcd/lcd_extern.h +@@ -0,0 +1,116 @@ ++/* ++ * include/amlogic/media/vout/lcd/lcd_extern.h ++ * ++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++ */ ++ ++#ifndef _INC_AML_LCD_EXTERN_H_ ++#define _INC_AML_LCD_EXTERN_H_ ++#include ++ ++enum lcd_extern_type_e { ++ LCD_EXTERN_I2C = 0, ++ LCD_EXTERN_SPI, ++ LCD_EXTERN_MIPI, ++ LCD_EXTERN_MAX, ++}; ++ ++#define LCD_EXTERN_I2C_BUS_A 0 ++#define LCD_EXTERN_I2C_BUS_B 1 ++#define LCD_EXTERN_I2C_BUS_C 2 ++#define LCD_EXTERN_I2C_BUS_D 3 ++#define LCD_EXTERN_I2C_BUS_AO 4 ++ ++#define LCD_EXTERN_I2C_BUS_0 LCD_EXTERN_I2C_BUS_A ++#define LCD_EXTERN_I2C_BUS_1 LCD_EXTERN_I2C_BUS_B ++#define LCD_EXTERN_I2C_BUS_2 LCD_EXTERN_I2C_BUS_C ++#define LCD_EXTERN_I2C_BUS_3 LCD_EXTERN_I2C_BUS_D ++#define LCD_EXTERN_I2C_BUS_4 LCD_EXTERN_I2C_BUS_AO ++#define LCD_EXTERN_I2C_BUS_MAX 5 ++ ++ ++#define LCD_EXTERN_INIT_ON_MAX 3000 ++#define LCD_EXTERN_INIT_OFF_MAX 100 ++ ++#define LCD_EXTERN_GPIO_NUM_MAX 6 ++#define LCD_EXTERN_GPIO_LEN_MAX 10 ++#define LCD_EXTERN_INDEX_INVALID 0xff ++#define LCD_EXTERN_NAME_LEN_MAX 30 ++ ++#define LCD_EXTERN_NUM_MAX 20 ++ ++struct lcd_extern_config_s { ++ unsigned char index; ++ char name[LCD_EXTERN_NAME_LEN_MAX]; ++ enum lcd_extern_type_e type; ++ unsigned char status; ++ ++ unsigned char i2c_addr; ++ unsigned char i2c_addr2; ++ unsigned char i2c_bus; ++ ++ unsigned char spi_clk_pol; ++ unsigned short spi_clk_freq; /*KHz */ ++ unsigned short spi_delay_us; ++ ++ unsigned char cmd_size; ++ unsigned char table_init_loaded; /* internal use */ ++ unsigned int table_init_on_cnt; ++ unsigned int table_init_off_cnt; ++ unsigned char *table_init_on; ++ unsigned char *table_init_off; ++}; ++ ++struct lcd_extern_common_s { ++ unsigned char lcd_ext_key_valid; ++ char gpio_name[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX]; ++ ++ unsigned char i2c_bus; ++ unsigned char i2c_gpio_sck; ++ unsigned char i2c_gpio_sda; ++ ++ unsigned char spi_gpio_cs; ++ unsigned char spi_gpio_clk; ++ unsigned char spi_gpio_data; ++ ++ struct lcd_pinmux_ctrl_s *lcd_ext_pinmux; ++ unsigned int pinmux_set[LCD_PINMUX_NUM][2]; ++ unsigned int pinmux_clr[LCD_PINMUX_NUM][2]; ++ unsigned char pinmux_gpio_off; ++ unsigned char pinmux_valid; ++}; ++ ++//global API ++struct aml_lcd_extern_driver_s { ++ struct lcd_extern_config_s *config; ++ struct lcd_extern_common_s *common; ++ int (*reg_read) (unsigned char reg, unsigned char *buf); ++ int (*reg_write) (unsigned char reg, unsigned char value); ++ int (*power_on)(void); ++ int (*power_off)(void); ++ void (*info_print)(void); ++}; ++ ++extern struct aml_lcd_extern_driver_s *aml_lcd_extern_get_driver(void); ++extern int aml_lcd_extern_probe(const void *dt_blob, int index); ++extern int aml_lcd_extern_remove(void); ++ ++extern struct lcd_extern_config_s ext_config_dtf; ++extern struct lcd_extern_common_s ext_common_dft; ++ ++#endif ++ +diff --git a/include/amlogic/media/vout/lcd/lcd_vout.h b/include/amlogic/media/vout/lcd/lcd_vout.h +new file mode 100644 +index 00000000000..a5c0f3d817a +--- /dev/null ++++ b/include/amlogic/media/vout/lcd/lcd_vout.h +@@ -0,0 +1,520 @@ ++/* ++ * include/amlogic/media/vout/lcd/lcd_vout.h ++ * ++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++ */ ++ ++#ifndef INC_AML_LCD_VOUT_H ++#define INC_AML_LCD_VOUT_H ++ ++#include ++#include ++#include ++#include ++ ++/* ********************************** ++ * debug print define ++ * ********************************** */ ++//#define LCD_DEBUG_INFO ++extern unsigned int lcd_debug_print_flag; ++ ++#define LCDPR(fmt, args...) printf("lcd: "fmt"", ## args) ++#define LCDERR(fmt, args...) printf("lcd: error: "fmt"", ## args) ++ ++/* ********************************** ++ * clk parameter bit define ++ * pll_ctrl, div_ctrl, clk_ctrl ++ * ********************************** */ ++/* ******** pll_ctrl ******** */ ++#define PLL_CTRL_OD3 20 /* [21:20] */ ++#define PLL_CTRL_OD2 18 /* [19:18] */ ++#define PLL_CTRL_OD1 16 /* [17:16] */ ++#define PLL_CTRL_N 9 /* [13:9] */ ++#define PLL_CTRL_M 0 /* [8:0] */ ++ ++/* ******** div_ctrl ******** */ ++#define DIV_CTRL_EDP_DIV1 24 /* [26:24] */ ++#define DIV_CTRL_EDP_DIV0 20 /* [23:20] */ ++#define DIV_CTRL_DIV_SEL 8 /* [15:8] */ ++#define DIV_CTRL_XD 0 /* [7:0] */ ++ ++/* ******** clk_ctrl ******** */ ++#define CLK_CTRL_LEVEL 28 /* [30:28] */ ++#define CLK_CTRL_FRAC 0 /* [18:0] */ ++ ++ ++#define LCD_PINMUX_END 0xff ++#define LCD_PINMUX_NUM 15 ++ ++/* ********************************** ++ * VENC to TCON sync delay ++ * ********************************** */ ++#define TTL_DELAY 13 ++ ++ ++/* ********************************** ++ * global control define ++ * ********************************** */ ++enum lcd_mode_e { ++ LCD_MODE_TV = 0, ++ LCD_MODE_TABLET, ++ LCD_MODE_MAX, ++}; ++ ++enum lcd_chip_e { ++ LCD_CHIP_G12A = 0, ++ LCD_CHIP_G12B, /* 1 */ ++ LCD_CHIP_TL1, ++ LCD_CHIP_SM1, ++ LCD_CHIP_MAX, ++}; ++ ++enum lcd_type_e { ++ LCD_TTL = 0, ++ LCD_LVDS, ++ LCD_VBYONE, ++ LCD_MIPI, ++ LCD_MLVDS, ++ LCD_TYPE_MAX, ++}; ++ ++#define MOD_LEN_MAX 30 ++struct lcd_basic_s { ++ char model_name[MOD_LEN_MAX]; ++ enum lcd_type_e lcd_type; ++ unsigned char lcd_bits; ++ ++ unsigned short h_active; /* Horizontal display area */ ++ unsigned short v_active; /* Vertical display area */ ++ unsigned short h_period; /* Horizontal total period time */ ++ unsigned short v_period; /* Vertical total period time */ ++ unsigned short h_period_min; ++ unsigned short h_period_max; ++ unsigned short v_period_min; ++ unsigned short v_period_max; ++ unsigned int lcd_clk_min; ++ unsigned int lcd_clk_max; ++ ++ unsigned short screen_width; /* screen physical width in "mm" unit */ ++ unsigned short screen_height; /* screen physical height in "mm" unit */ ++}; ++ ++#define LCD_CLK_FRAC_UPDATE (1 << 0) ++#define LCD_CLK_PLL_CHANGE (1 << 1) ++struct lcd_timing_s { ++ unsigned char clk_auto; /* clk parameters auto generation */ ++ unsigned char fr_adjust_type; /* 0=clock, 1=htotal, 2=vtotal */ ++ unsigned char clk_change; /* internal used */ ++ unsigned int lcd_clk; /* pixel clock(unit: Hz) */ ++ unsigned int lcd_clk_dft; /* internal used */ ++ unsigned int h_period_dft; /* internal used */ ++ unsigned int v_period_dft; /* internal used */ ++ unsigned int pll_ctrl; /* pll settings */ ++ unsigned int div_ctrl; /* divider settings */ ++ unsigned int clk_ctrl; /* clock settings */ ++ ++ unsigned int ss_level; ++ ++ unsigned short sync_duration_num; ++ unsigned short sync_duration_den; ++ ++ unsigned short video_on_pixel; ++ unsigned short video_on_line; ++ ++ unsigned short hsync_width; ++ unsigned short hsync_bp; ++ unsigned short hsync_pol; ++ unsigned short vsync_width; ++ unsigned short vsync_bp; ++ unsigned short vsync_pol; ++ /* unsigned int vsync_h_phase; // [31]sign, [15:0]value */ ++ unsigned int h_offset; ++ unsigned int v_offset; ++ ++ unsigned short de_hs_addr; ++ unsigned short de_he_addr; ++ unsigned short de_vs_addr; ++ unsigned short de_ve_addr; ++ ++ unsigned short hs_hs_addr; ++ unsigned short hs_he_addr; ++ unsigned short hs_vs_addr; ++ unsigned short hs_ve_addr; ++ ++ unsigned short vs_hs_addr; ++ unsigned short vs_he_addr; ++ unsigned short vs_vs_addr; ++ unsigned short vs_ve_addr; ++}; ++ ++struct ttl_config_s { ++ unsigned int clk_pol; ++ unsigned int sync_valid; /* [1]DE, [0]hvsync */ ++ unsigned int swap_ctrl; /* [1]rb swap, [0]bit swap */ ++}; ++ ++#define LVDS_PHY_VSWING_DFT 3 ++#define LVDS_PHY_PREEM_DFT 0 ++#define LVDS_PHY_CLK_VSWING_DFT 0 ++#define LVDS_PHY_CLK_PREEM_DFT 0 ++struct lvds_config_s { ++ unsigned int lvds_repack; ++ unsigned int dual_port; ++ unsigned int pn_swap; ++ unsigned int port_swap; ++ unsigned int lane_reverse; ++ unsigned int port_sel; ++ unsigned int phy_vswing; ++ unsigned int phy_preem; ++ unsigned int phy_clk_vswing; ++ unsigned int phy_clk_preem; ++}; ++ ++#define VX1_PHY_VSWING_DFT 3 ++#define VX1_PHY_PREEM_DFT 0 ++ ++#define VX1_PWR_ON_RESET_DLY_DFT 500 /* 500ms */ ++#define VX1_HPD_DATA_DELAY_DFT 10 /* 10ms */ ++#define VX1_CDR_TRAINING_HOLD_DFT 200 /* 200ms */ ++ ++#define VX1_SW_FILTER_TIME_DFT 10 /* 10*100us=1ms */ ++#define VX1_SW_FILTER_CNT_DFT 6 ++#define VX1_SW_FILTER_RETRY_CNT_DFT 2 ++#define VX1_SW_FILTER_RETRY_DLY_DFT 100 /* 100ms */ ++#define VX1_SW_CDR_DET_TIME_DFT 20 /* 20us*100=2ms */ ++#define VX1_SW_CDR_DET_CNT_DFT 100 ++#define VX1_SW_CDR_TIMEOUT_CNT_DFT 100 ++ ++struct vbyone_config_s { ++ unsigned int lane_count; ++ unsigned int region_num; ++ unsigned int byte_mode; ++ unsigned int color_fmt; ++ unsigned int phy_div; ++ unsigned int bit_rate; ++ unsigned int phy_vswing; /*[5:4]:ext_pullup, [3:0]vswing*/ ++ unsigned int phy_preem; ++ unsigned int ctrl_flag; ++ /* bit[0]:power_on_reset_en ++ bit[1]:hpd_data_delay_en ++ bit[2]:cdr_training_hold_en ++ bit[3]:hw_filter_en ++ bit[5:4]:sw_filter */ ++ ++ /* ctrl timing */ ++ unsigned int power_on_reset_delay; /* ms */ ++ unsigned int hpd_data_delay; /* ms */ ++ unsigned int cdr_training_hold; /* ms */ ++ /* hw filter */ ++ unsigned int hpd_hw_filter_time; /* ms */ ++ unsigned int hpd_hw_filter_cnt; ++ unsigned int lockn_hw_filter_time; /* ms */ ++ unsigned int lockn_hw_filter_cnt; ++ /* sw filter */ ++ unsigned int vx1_sw_filter_en; /* 0=disable, 1=sw_filter, 2=sw_filter with sw_reset */ ++ unsigned int vx1_sw_filter_time; /* 100us base */ ++ unsigned int vx1_sw_filter_cnt; ++ unsigned int vx1_sw_filter_retry_cnt; ++ unsigned int vx1_sw_filter_retry_delay; /* ms base */ ++ unsigned int vx1_sw_cdr_detect_time; /* us base * 100 times, must cover tcon lockn pulse */ ++ unsigned int vx1_sw_cdr_detect_cnt; ++ unsigned int vx1_sw_cdr_timeout_cnt; ++}; ++ ++/* mipi-dsi config */ ++/* Operation mode parameters */ ++#define OPERATION_VIDEO_MODE 0 ++#define OPERATION_COMMAND_MODE 1 ++ ++#define SYNC_PULSE 0x0 ++#define SYNC_EVENT 0x1 ++#define BURST_MODE 0x2 ++ ++/* command config */ ++#define DSI_CMD_SIZE_INDEX 1 /* byte[1] */ ++#define DSI_GPIO_INDEX 2 /* byte[2] */ ++ ++#define DSI_INIT_ON_MAX 100 ++#define DSI_INIT_OFF_MAX 30 ++ ++struct dsi_config_s { ++ unsigned char lane_num; ++ unsigned int bit_rate_max; /* MHz */ ++ unsigned int bit_rate_min; /* MHz*/ ++ unsigned int bit_rate; /* Hz */ ++ unsigned int clk_factor; /* bit_rate/pclk */ ++ unsigned int factor_numerator; ++ unsigned int factor_denominator; /* 100 */ ++ unsigned char operation_mode_init; /* 0=video mode, 1=command mode */ ++ unsigned char operation_mode_display; /* 0=video mode, 1=command mode */ ++ unsigned char video_mode_type; /* 0=sync_pulse, 1=sync_event, 2=burst */ ++ unsigned char clk_always_hs; /* 0=disable, 1=enable */ ++ unsigned char phy_switch; /* 0=auto, 1=standard, 2=slow */ ++ ++ unsigned int venc_data_width; ++ unsigned int dpi_data_format; ++ ++ unsigned char *dsi_init_on; ++ unsigned char *dsi_init_off; ++ unsigned char extern_init; ++ ++ unsigned char check_en; ++ unsigned char check_reg; ++ unsigned char check_cnt; ++ unsigned char check_state; ++}; ++ ++struct mlvds_config_s { ++ unsigned int channel_num; ++ unsigned int channel_sel0; ++ unsigned int channel_sel1; ++ unsigned int clk_phase; /* [13:12]=clk01_sel, [11:8]=pi2, [7:4]=pi1, [3:0]=pi0 */ ++ unsigned int pn_swap; ++ unsigned int bit_swap; /* MSB/LSB reverse */ ++ unsigned int phy_vswing; ++ unsigned int phy_preem; ++ ++ /* internal used */ ++ unsigned int pi_clk_sel; /* bit[9:0] */ ++ unsigned int bit_rate; /* Hz */ ++}; ++ ++struct lcd_ctrl_config_s { ++ struct ttl_config_s *ttl_config; ++ struct lvds_config_s *lvds_config; ++ struct vbyone_config_s *vbyone_config; ++ struct dsi_config_s *mipi_config; ++ struct mlvds_config_s *mlvds_config; ++}; ++ ++/* ********************************** ++ * power control define ++ * ********************************** */ ++enum lcd_power_type_e { ++ LCD_POWER_TYPE_CPU = 0, ++ LCD_POWER_TYPE_PMU, ++ LCD_POWER_TYPE_SIGNAL, ++ LCD_POWER_TYPE_EXTERN, ++ LCD_POWER_TYPE_MAX, ++}; ++ ++#define LCD_CPU_GPIO_NAME_MAX 15 ++ ++/* Power Control */ ++#define LCD_CPU_GPIO_NUM_MAX 10 ++ ++#define LCD_PWR_STEP_MAX 15 ++struct lcd_power_step_s { ++ unsigned char type; ++ int index; /* point to lcd_cpu_gpio or lcd_extern */ ++ unsigned short value; ++ unsigned short delay; ++}; ++ ++struct lcd_power_ctrl_s { ++ char cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX]; ++ struct lcd_power_step_s power_on_step[LCD_PWR_STEP_MAX]; ++ struct lcd_power_step_s power_off_step[LCD_PWR_STEP_MAX]; ++}; ++ ++#define LCD_PINMX_MAX 20 ++#define BL_PINMUX_MAX 20 ++#define LCD_PINMUX_NAME_LEN_MAX 30 ++struct lcd_pinmux_ctrl_s { ++ char *name; ++ unsigned int pinmux_set[LCD_PINMUX_NUM][2]; ++ unsigned int pinmux_clr[LCD_PINMUX_NUM][2]; ++}; ++ ++#define LCD_ENABLE_RETRY_MAX 3 ++struct lcd_config_s { ++ unsigned char lcd_mode; ++ unsigned char lcd_key_valid; ++ unsigned char lcd_clk_path; /* 0=hpll, 1=gp0_pll */ ++ unsigned char retry_enable_flag; ++ unsigned char retry_enable_cnt; ++ unsigned int backlight_index; ++ struct lcd_basic_s lcd_basic; ++ struct lcd_timing_s lcd_timing; ++ struct lcd_ctrl_config_s lcd_control; ++ struct lcd_power_ctrl_s *lcd_power; ++ unsigned char pinctrl_ver; ++ struct lcd_pinmux_ctrl_s *lcd_pinmux; ++ unsigned int pinmux_set[LCD_PINMUX_NUM][2]; ++ unsigned int pinmux_clr[LCD_PINMUX_NUM][2]; ++}; ++ ++extern struct lcd_config_s lcd_config_dft; ++ ++/* ==============backlight control config================== */ ++enum bl_ctrl_method_e { ++ BL_CTRL_GPIO = 0, ++ BL_CTRL_PWM, ++ BL_CTRL_PWM_COMBO, ++ BL_CTRL_LOCAL_DIMMING, ++ BL_CTRL_EXTERN, ++ BL_CTRL_MAX, ++}; ++ ++enum bl_pwm_method_e { ++ BL_PWM_NEGATIVE = 0, ++ BL_PWM_POSITIVE, ++ BL_PWM_METHOD_MAX, ++}; ++ ++enum bl_pwm_port_e { ++ BL_PWM_A = 0, ++ BL_PWM_B, ++ BL_PWM_C, ++ BL_PWM_D, ++ BL_PWM_E, ++ BL_PWM_F, ++ BL_PWM_VS, ++ BL_PWM_MAX, ++}; ++ ++enum bl_off_policy_e { ++ BL_OFF_POLICY_NONE = 0, ++ BL_OFF_POLICY_ALWAYS, ++ BL_OFF_POLICY_ONCE, ++ BL_OFF_POLICY_MAX, ++}; ++ ++#define XTAL_FREQ_HZ (24*1000*1000) /* 24M in HZ */ ++#define XTAL_HALF_FREQ_HZ (24*1000*500) /* 24M/2 in HZ */ ++ ++#define BL_FREQ_DEFAULT 1000 /* unit: HZ */ ++#define BL_FREQ_VS_DEFAULT 2 /* multiple 2 of vfreq */ ++ ++#define BL_LEVEL_MAX 255 ++#define BL_LEVEL_MIN 10 ++#define BL_LEVEL_OFF 1 ++ ++#define BL_LEVEL_MID 128 ++#define BL_LEVEL_MID_MAPPED BL_LEVEL_MID //102 ++#define BL_LEVEL_DEFAULT BL_LEVEL_MID ++ ++#define BL_GPIO_NUM_MAX 5 ++ ++struct bl_pwm_config_s { ++ unsigned int index; ++ enum bl_pwm_method_e pwm_method; ++ enum bl_pwm_port_e pwm_port; ++ unsigned int level_max; ++ unsigned int level_min; ++ unsigned int pwm_freq; /* pwm_vs: 1~4(vfreq), pwm: freq(unit: Hz) */ ++ unsigned int pwm_duty; /* unit: % */ ++ unsigned int pwm_duty_max; /* unit: % */ ++ unsigned int pwm_duty_min; /* unit: % */ ++ unsigned int pwm_cnt; /* internal used for pwm control */ ++ unsigned int pwm_pre_div; /* internal used for pwm control */ ++ unsigned int pwm_max; /* internal used for pwm control */ ++ unsigned int pwm_min; /* internal used for pwm control */ ++ unsigned int pwm_level; /* internal used for pwm control */ ++ unsigned int pwm_gpio; ++ unsigned int pwm_gpio_off; ++ unsigned int pinmux_flag; ++ unsigned int pinmux_set[10][2]; ++ unsigned int pinmux_clr[10][2]; ++}; ++ ++struct bl_config_s { ++ unsigned char bl_key_valid; ++ char name[20]; ++ int level_default; ++ int level_min; ++ int level_max; ++ int level_mid; ++ int level_mid_mapping; ++ int level; ++ ++ enum bl_ctrl_method_e method; ++ unsigned int en_gpio; ++ unsigned int en_gpio_on; ++ unsigned int en_gpio_off; ++ unsigned short power_on_delay; ++ unsigned short power_off_delay; ++ unsigned int dim_max; ++ unsigned int dim_min; ++ unsigned int en_sequence_reverse; ++ ++ struct bl_pwm_config_s *bl_pwm; ++ struct bl_pwm_config_s *bl_pwm_combo0; ++ struct bl_pwm_config_s *bl_pwm_combo1; ++ unsigned int pwm_on_delay; ++ unsigned int pwm_off_delay; ++ ++ char gpio_name[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX]; ++ unsigned char pinctrl_ver; ++ struct lcd_pinmux_ctrl_s *bl_pinmux; ++ unsigned int pinmux_set[10][2]; ++ unsigned int pinmux_clr[10][2]; ++ int bl_extern_index; ++}; ++ ++extern struct bl_config_s bl_config_dft; ++ ++/* ==============lcd driver================== */ ++struct aml_lcd_drv_s { ++ char version[15]; ++ enum lcd_chip_e chip_type; ++ unsigned char lcd_status; ++ ++ struct lcd_config_s *lcd_config; ++ struct bl_config_s *bl_config; ++ ++ int (*outputmode_check)(char *mode, unsigned int frac); ++ int (*config_check)(char *mode, unsigned int frac); ++ void (*driver_init_pre)(void); ++ int (*driver_init)(void); ++ void (*driver_disable)(void); ++ void (*list_support_mode)(void); ++ int (*lcd_probe)(void); ++ int (*lcd_outputmode_check)(char *mode, unsigned int frac); ++ void (*lcd_prepare)(char *mode, unsigned int frac); ++ void (*lcd_enable)(char *mode, unsigned int frac); ++ void (*lcd_disable)(void); ++ void (*lcd_set_ss)(int level); ++ char *(*lcd_get_ss)(void); ++ void (*lcd_test)(int num); ++ void (*lcd_clk)(void); ++ void (*lcd_info)(void); ++ void (*lcd_reg)(void); ++ void (*lcd_tcon_reg)(void); ++ void (*lcd_tcon_table)(void); ++ void (*bl_power_ctrl)(int status); ++ void (*bl_set_level)(unsigned int level); ++ unsigned int (*bl_get_level)(void); ++ void (*bl_config_print)(void); ++ int unifykey_test_flag; ++ void (*unifykey_test)(void); ++ void (*unifykey_tcon_test)(void); ++ void (*unifykey_dump)(void); ++ void (*lcd_extern_info)(void); ++ ++ /* for factory test */ ++ struct lcd_power_step_s *factory_lcd_power_on_step; ++ int factory_bl_power_on_delay; ++}; ++ ++extern void lcd_config_bsp_init(void); ++ ++extern struct aml_lcd_drv_s *aml_lcd_get_driver(void); ++ ++extern int lcd_probe(void); ++ ++#endif /* INC_AML_LCD_VOUT_H */ +diff --git a/include/amlogic/media/vpp/vpp.h b/include/amlogic/media/vpp/vpp.h +new file mode 100644 +index 00000000000..d77ddd3879d +--- /dev/null ++++ b/include/amlogic/media/vpp/vpp.h +@@ -0,0 +1,24 @@ ++#ifndef _VPP_INC_H_ ++#define _VPP_INC_H_ ++ ++extern void vpp_init(void); ++void vpp_pq_init(int brightness, int contrast, int sat, int hue); ++void vpp_pq_load(void); ++ ++#define VPP_CM_RGB 0 /* same as COLOR_FMT_RGB444*/ ++#define VPP_CM_YUV 2 /* same as COLOR_FMT_YUV444*/ ++ ++enum vpp_gamma_sel_e { ++ VPP_GAMMA_R = 0, ++ VPP_GAMMA_G, ++ VPP_GAMMA_B ++}; ++ ++extern void vpp_load_gamma_table(unsigned short *data, unsigned int len, enum vpp_gamma_sel_e flag); ++extern void vpp_init_lcd_gamma_table(void); ++ ++extern void vpp_matrix_update(int type); ++extern void vpp_viu2_matrix_update(int type); ++extern void hdr_tx_pkt_cb(void); ++ ++#endif +diff --git a/include/amlogic/media/vpu/vpu.h b/include/amlogic/media/vpu/vpu.h +new file mode 100644 +index 00000000000..26bd575e07f +--- /dev/null ++++ b/include/amlogic/media/vpu/vpu.h +@@ -0,0 +1,11 @@ ++#ifndef _VPU_INC_H_ ++#define _VPU_INC_H_ ++ ++extern void vcbus_test(void); ++extern int vpu_probe(void); ++extern int vpu_remove(void); ++extern int vpu_clk_change(int level); ++extern void vpu_clk_get(void); ++extern void vpu_info_print(void); ++ ++#endif +diff --git a/include/amlogic/saradc.h b/include/amlogic/saradc.h +new file mode 100644 +index 00000000000..7344a2bfa1a +--- /dev/null ++++ b/include/amlogic/saradc.h +@@ -0,0 +1,103 @@ ++#ifndef __MESON_SARADC_H__ ++#define __MESON_SARADC_H__ ++ ++#include ++#include ++#include ++ ++enum ADC_CHANNEL_TYPE { ++ MESON_SARADC_CH0 = 0, ++ MESON_SARADC_CH1, ++ MESON_SARADC_CH2, ++ MESON_SARADC_CH3, ++ MESON_SARADC_CH4, ++ MESON_SARADC_CH5, ++ MESON_SARADC_CH6, ++ MESON_SARADC_CH7, ++ MESON_SARADC_CH_MAX, ++}; ++ ++enum MESON_SARADC_AVG_MODE { ++ NO_AVERAGING = 0x0, ++ MEAN_AVERAGING = 0x1, ++ MEDIAN_AVERAGING = 0x2, ++}; ++ ++enum MESON_SARADC_NUM_SAMPLES { ++ ONE_SAMPLE = 0x0, ++ TWO_SAMPLES = 0x1, ++ FOUR_SAMPLES = 0x2, ++ EIGHT_SAMPLES = 0x3, ++}; ++ ++enum MESON_SARADC_RESOLUTION { ++ SARADC_10BIT = 10, ++ SARADC_12BIT = 12, ++ SARADC_22BIT = 22, ++}; ++ ++enum MESON_SARADC_BIT_STATE { ++ BIT_LOW = 0, ++ BIT_HIGH = 1, ++}; ++ ++struct meson_saradc; ++ ++struct meson_saradc_diff_ops { ++ void (*extra_init)(struct meson_saradc *priv); ++ void (*set_ch7_mux)(struct meson_saradc *priv, int ch, int mux); ++ void (*enable_decim_filter)(struct meson_saradc *priv, ++ int ch, unsigned int mode); ++ void (*set_ref_voltage)(struct meson_saradc *priv, unsigned int mode); ++ int (*get_fifo_channel)(int val); ++ int (*get_fifo_data)(struct meson_saradc *priv, ++ struct adc_uclass_platdata *uc_pdata, int val); ++}; ++ ++/* ++ * struct meson_saradc_data - describe the differences of different platform ++ * ++ * @reg3_ring_counter_disable: to disable continuous ring counter. ++ * gxl and later: 1; others(gxtvbb etc): 0 ++ * @reg11_vref_en: g12a and later: 0; others(axg etc): 1 ++ * @reg11_cmv_sel: g12a and later: 0; others(axg etc): 1 ++ * @reg11_eoc: g12a and later: 1; others(axg etc): 0 ++ * @has_bl30_integration: ++ * @num_channels: the number of adc channels ++ * @self_test_channel: channel of self-test ++ * @resolution: gxl and later: 12bit; others(gxtvbb etc): 10bit ++ * @clock_rate: saradc clock rate ++ */ ++struct meson_saradc_data { ++ bool reg3_ring_counter_disable; ++ bool reg11_vref_en; ++ bool reg11_cmv_sel; ++ bool reg11_eoc; ++ bool has_bl30_integration; ++ unsigned char self_test_channel; ++ unsigned char num_channels; ++ unsigned int resolution; ++ const struct meson_saradc_diff_ops *dops; ++ unsigned int capacity; ++ unsigned long clock_rate; ++}; ++ ++struct meson_saradc { ++ phys_addr_t base; ++ int active_channel; ++ unsigned int current_mode; ++ struct clk xtal; ++ struct clk adc_mux; ++ struct clk adc_div; ++ struct clk adc_gate; ++ struct meson_saradc_data *data; ++}; ++ ++extern const struct adc_ops meson_saradc_ops; ++int meson_saradc_probe(struct udevice *dev); ++int meson_saradc_remove(struct udevice *dev); ++int meson_saradc_ofdata_to_platdata(struct udevice *dev); ++ ++#define SARADC_CH_SELF_TEST MESON_SARADC_CH7 ++ ++#endif /*_MESON_SARADC_H_*/ +diff --git a/include/amlogic/secure_storage.h b/include/amlogic/secure_storage.h +new file mode 100644 +index 00000000000..3a0148204b2 +--- /dev/null ++++ b/include/amlogic/secure_storage.h +@@ -0,0 +1,46 @@ ++#ifndef __SECURE_STORAGE_H__ ++#define __SECURE_STORAGE_H__ ++ ++/* return value*/ ++#define RET_OK 0 ++#define RET_EFAIL 1 ++#define RET_EINVAL 2 ++#define RET_EMEM 3 ++ ++#define RET_EUND -1 ++#define SMC_UNK 0xffffffff ++ ++ ++#ifdef CONFIG_SECURE_STORAGE ++/* funtion name: secure_storage_write ++ * keyname : key name is ascii string ++ * keybuf : key buf ++ * keylen : key buf len ++ * keyattr: Secure/Normal, ... ++ * ++ * return 0: ok, 0x1fe: no space, other fail ++ * */ ++int32_t secure_storage_write(uint8_t *keyname, uint8_t *keybuf, ++ uint32_t keylen, uint32_t keyattr); ++int32_t secure_storage_read(uint8_t *keyname, uint8_t *keybuf, ++ uint32_t keylen, uint32_t *reallen); ++int32_t secure_storage_query(uint8_t *keyname, uint32_t *retval); ++int32_t secure_storage_tell(uint8_t *keyname, uint32_t *retval); ++int32_t secure_storage_verify(uint8_t *keyname, uint8_t *hashbuf); ++int32_t secure_storage_status(uint8_t *keyname, uint32_t *retval); ++void *secure_storage_getbuffer(uint32_t *size); ++void secure_storage_notifier(void); ++void secure_storage_notifier_ex(uint32_t storagesize, uint32_t rsvarg); ++int32_t secure_storage_list(uint8_t *listbuf, uint32_t buflen, ++ uint32_t *readlen); ++int32_t secure_storage_remove(uint8_t *keyname); ++void secure_storage_set_info(uint32_t info); ++int32_t secure_storage_set_enctype(uint32_t type); ++/* return 0: success, -1: fail*/ ++int32_t secure_storage_get_enctype(void); ++/*return -1: no storage, 0: default enc, 1: efuse enc, 2: fixed enc*/ ++int32_t secure_storage_version(void); ++/*return -1: no storage, others: version*/ ++#endif ++ ++#endif +diff --git a/include/amlogic/sound.h b/include/amlogic/sound.h +new file mode 100644 +index 00000000000..4aceb7c9fd3 +--- /dev/null ++++ b/include/amlogic/sound.h +@@ -0,0 +1,180 @@ ++/* ++ * include/amlogic/sound.h ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the named License, ++ * or any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++ ++#ifndef _SOUND_H_ ++#define _SOUND_H_ ++ ++#define AIU_958_BPF 0x1500 ++#define AIU_958_BRST 0x1501 ++#define AIU_958_LENGTH 0x1502 ++#define AIU_958_PADDSIZE 0x1503 ++#define AIU_958_MISC 0x1504 ++#define AIU_958_FORCE_LEFT 0x1505 ++#define AIU_958_DISCARD_NUM 0x1506 ++#define AIU_958_DCU_FF_CTRL 0x1507 ++#define AIU_958_CHSTAT_L0 0x1508 ++#define AIU_958_CHSTAT_L1 0x1509 ++#define AIU_958_CTRL 0x150a ++#define AIU_958_RPT 0x150b ++#define AIU_I2S_MUTE_SWAP 0x150c ++#define AIU_I2S_SOURCE_DESC 0x150d ++#define AIU_I2S_MED_CTRL 0x150e ++#define AIU_I2S_MED_THRESH 0x150f ++#define AIU_I2S_DAC_CFG 0x1510 ++#define AIU_I2S_SYNC 0x1511 ++#define AIU_I2S_MISC 0x1512 ++#define AIU_I2S_OUT_CFG 0x1513 ++#define AIU_I2S_FF_CTRL 0x1514 ++#define AIU_RST_SOFT 0x1515 ++#define AIU_CLK_CTRL 0x1516 ++#define AIU_MIX_ADCCFG 0x1517 ++#define AIU_MIX_CTRL 0x1518 ++#define AIU_CLK_CTRL_MORE 0x1519 ++#define AIU_958_POP 0x151a ++#define AIU_MIX_GAIN 0x151b ++#define AIU_958_SYNWORD1 0x151c ++#define AIU_958_SYNWORD2 0x151d ++#define AIU_958_SYNWORD3 0x151e ++#define AIU_958_SYNWORD1_MASK 0x151f ++#define AIU_958_SYNWORD2_MASK 0x1520 ++#define AIU_958_SYNWORD3_MASK 0x1521 ++#define AIU_958_FFRDOUT_THD 0x1522 ++#define AIU_958_LENGTH_PER_PAUSE 0x1523 ++#define AIU_958_PAUSE_NUM 0x1524 ++#define AIU_958_PAUSE_PAYLOAD 0x1525 ++#define AIU_958_AUTO_PAUSE 0x1526 ++#define AIU_958_PAUSE_PD_LENGTH 0x1527 ++#define AIU_CODEC_DAC_LRCLK_CTRL 0x1528 ++#define AIU_CODEC_ADC_LRCLK_CTRL 0x1529 ++#define AIU_HDMI_CLK_DATA_CTRL 0x152a ++#define AIU_CODEC_CLK_DATA_CTRL 0x152b ++#define AIU_ACODEC_CTRL 0x152c ++#define AIU_958_CHSTAT_R0 0x1530 ++#define AIU_958_CHSTAT_R1 0x1531 ++#define AIU_958_VALID_CTRL 0x1532 ++#define AIU_AUDIO_AMP_REG0 0x153c ++#define AIU_AUDIO_AMP_REG1 0x153d ++#define AIU_AUDIO_AMP_REG2 0x153e ++#define AIU_AUDIO_AMP_REG3 0x153f ++#define AIU_AIFIFO2_CTRL 0x1540 ++#define AIU_AIFIFO2_STATUS 0x1541 ++#define AIU_AIFIFO2_GBIT 0x1542 ++#define AIU_AIFIFO2_CLB 0x1543 ++#define AIU_CRC_CTRL 0x1544 ++#define AIU_CRC_STATUS 0x1545 ++#define AIU_CRC_SHIFT_REG 0x1546 ++#define AIU_CRC_IREG 0x1547 ++#define AIU_CRC_CAL_REG1 0x1548 ++#define AIU_CRC_CAL_REG0 0x1549 ++#define AIU_CRC_POLY_COEF1 0x154a ++#define AIU_CRC_POLY_COEF0 0x154b ++#define AIU_CRC_BIT_SIZE1 0x154c ++#define AIU_CRC_BIT_SIZE0 0x154d ++#define AIU_CRC_BIT_CNT1 0x154e ++#define AIU_CRC_BIT_CNT0 0x154f ++#define AIU_AMCLK_GATE_HI 0x1550 ++#define AIU_AMCLK_GATE_LO 0x1551 ++#define AIU_AMCLK_MSR 0x1552 ++#define AIU_AUDAC_CTRL0 0x1553 ++#define AIU_DELTA_SIGMA0 0x1555 ++#define AIU_DELTA_SIGMA1 0x1556 ++#define AIU_DELTA_SIGMA2 0x1557 ++#define AIU_DELTA_SIGMA3 0x1558 ++#define AIU_DELTA_SIGMA4 0x1559 ++#define AIU_DELTA_SIGMA5 0x155a ++#define AIU_DELTA_SIGMA6 0x155b ++#define AIU_DELTA_SIGMA7 0x155c ++#define AIU_DELTA_SIGMA_LCNTS 0x155d ++#define AIU_DELTA_SIGMA_RCNTS 0x155e ++#define AIU_MEM_I2S_START_PTR 0x1560 ++#define AIU_MEM_I2S_RD_PTR 0x1561 ++#define AIU_MEM_I2S_END_PTR 0x1562 ++#define AIU_MEM_I2S_MASKS 0x1563 ++#define AIU_MEM_I2S_CONTROL 0x1564 ++#define AIU_MEM_IEC958_START_PTR 0x1565 ++#define AIU_MEM_IEC958_RD_PTR 0x1566 ++#define AIU_MEM_IEC958_END_PTR 0x1567 ++#define AIU_MEM_IEC958_MASKS 0x1568 ++#define AIU_MEM_IEC958_CONTROL 0x1569 ++#define AIU_MEM_AIFIFO2_START_PTR 0x156a ++#define AIU_MEM_AIFIFO2_CURR_PTR 0x156b ++#define AIU_MEM_AIFIFO2_END_PTR 0x156c ++#define AIU_MEM_AIFIFO2_BYTES_AVAIL 0x156d ++#define AIU_MEM_AIFIFO2_CONTROL 0x156e ++#define AIU_MEM_AIFIFO2_MAN_WP 0x156f ++#define AIU_MEM_AIFIFO2_MAN_RP 0x1570 ++#define AIU_MEM_AIFIFO2_LEVEL 0x1571 ++#define AIU_MEM_AIFIFO2_BUF_CNTL 0x1572 ++#define AIU_MEM_I2S_MAN_WP 0x1573 ++#define AIU_MEM_I2S_MAN_RP 0x1574 ++#define AIU_MEM_I2S_LEVEL 0x1575 ++#define AIU_MEM_I2S_BUF_CNTL 0x1576 ++#define AIU_MEM_I2S_BUF_WRAP_COUNT 0x1577 ++#define AIU_MEM_I2S_MEM_CTL 0x1578 ++#define AIU_MEM_IEC958_MEM_CTL 0x1579 ++#define AIU_MEM_IEC958_WRAP_COUNT 0x157a ++#define AIU_MEM_IEC958_IRQ_LEVEL 0x157b ++#define AIU_MEM_IEC958_MAN_WP 0x157c ++#define AIU_MEM_IEC958_MAN_RP 0x157d ++#define AIU_MEM_IEC958_LEVEL 0x157e ++#define AIU_MEM_IEC958_BUF_CNTL 0x157f ++#define AIU_AIFIFO_CTRL 0x1580 ++#define AIU_AIFIFO_STATUS 0x1581 ++#define AIU_AIFIFO_GBIT 0x1582 ++#define AIU_AIFIFO_CLB 0x1583 ++#define AIU_MEM_AIFIFO_START_PTR 0x1584 ++#define AIU_MEM_AIFIFO_CURR_PTR 0x1585 ++#define AIU_MEM_AIFIFO_END_PTR 0x1586 ++#define AIU_MEM_AIFIFO_BYTES_AVAIL 0x1587 ++#define AIU_MEM_AIFIFO_CONTROL 0x1588 ++#define AIU_MEM_AIFIFO_MAN_WP 0x1589 ++#define AIU_MEM_AIFIFO_MAN_RP 0x158a ++#define AIU_MEM_AIFIFO_LEVEL 0x158b ++#define AIU_MEM_AIFIFO_BUF_CNTL 0x158c ++#define AIU_MEM_AIFIFO_BUF_WRAP_COUNT 0x158d ++#define AIU_MEM_AIFIFO2_BUF_WRAP_COUNT 0x158e ++#define AIU_MEM_AIFIFO_MEM_CTL 0x158f ++#define AIFIFO_TIME_STAMP_CNTL 0x1590 ++#define AIFIFO_TIME_STAMP_SYNC_0 0x1591 ++#define AIFIFO_TIME_STAMP_SYNC_1 0x1592 ++#define AIFIFO_TIME_STAMP_0 0x1593 ++#define AIFIFO_TIME_STAMP_1 0x1594 ++#define AIFIFO_TIME_STAMP_2 0x1595 ++#define AIFIFO_TIME_STAMP_3 0x1596 ++#define AIFIFO_TIME_STAMP_LENGTH 0x1597 ++#define AIFIFO2_TIME_STAMP_CNTL 0x1598 ++#define AIFIFO2_TIME_STAMP_SYNC_0 0x1599 ++#define AIFIFO2_TIME_STAMP_SYNC_1 0x159a ++#define AIFIFO2_TIME_STAMP_0 0x159b ++#define AIFIFO2_TIME_STAMP_1 0x159c ++#define AIFIFO2_TIME_STAMP_2 0x159d ++#define AIFIFO2_TIME_STAMP_3 0x159e ++#define AIFIFO2_TIME_STAMP_LENGTH 0x159f ++#define IEC958_TIME_STAMP_CNTL 0x15a0 ++#define IEC958_TIME_STAMP_SYNC_0 0x15a1 ++#define IEC958_TIME_STAMP_SYNC_1 0x15a2 ++#define IEC958_TIME_STAMP_0 0x15a3 ++#define IEC958_TIME_STAMP_1 0x15a4 ++#define IEC958_TIME_STAMP_2 0x15a5 ++#define IEC958_TIME_STAMP_3 0x15a6 ++#define IEC958_TIME_STAMP_LENGTH 0x15a7 ++#define AIU_MEM_AIFIFO2_MEM_CTL 0x15a8 ++#define AIU_I2S_CBUS_DDR_CNTL 0x15a9 ++#define AIU_I2S_CBUS_DDR_WDATA 0x15aa ++#define AIU_I2S_CBUS_DDR_ADDR 0x15ab ++ ++int aml_audio_init(void); ++ ++#endif /* _SOUND_H_ */ +diff --git a/include/amlogic/spicc.h b/include/amlogic/spicc.h +new file mode 100644 +index 00000000000..282af845c5f +--- /dev/null ++++ b/include/amlogic/spicc.h +@@ -0,0 +1,44 @@ ++/* ++ * Amlogic Meson SPI communication controller(SPICC) ++ * ++ * Copyright (C) 2017 Amlogic Corporation ++ * ++ * Licensed under the GPL-2 or later. ++ * ++ */ ++ ++#ifndef __SPICC_H__ ++#define __SPICC_H__ ++ ++#define SPICC_DEFAULT_CLK_RATE 166666666 ++#define CS_GPIO_MAX 2 ++ ++/* ++ * @compatible: ++ * @reg: controller registers address. ++ * @mem_map: memory_mapped for read operations. ++ * @clk_rate: ++ * @clk_set_rate: ++ * @pinctrl_enable: ++ * @num_chipselect: ++ * @cs_gpios: ++ */ ++struct spicc_platdata { ++#ifndef CONFIG_OF_CONTROL ++ char *compatible; ++ int clk_rate; ++ int (*clk_set_rate)(int rate); ++ int (*clk_enable)(bool enable); ++ int (*pinctrl_enable)(bool enable); ++#endif ++ void __iomem *reg; ++ const char *cs_gpio_names[CS_GPIO_MAX]; ++ unsigned int clk_cs_delay; ++ unsigned int mo_delay; ++ unsigned int mi_delay; ++ unsigned int mi_capture_delay; ++ unsigned int tt_delay; ++ unsigned int ti_delay; ++}; ++ ++#endif /* __SPICC_H__ */ +\ No newline at end of file +diff --git a/include/amlogic/spifc.h b/include/amlogic/spifc.h +new file mode 100644 +index 00000000000..0eb759896a2 +--- /dev/null ++++ b/include/amlogic/spifc.h +@@ -0,0 +1,44 @@ ++/* ++ * Amlogic SPI flash controller(SPIFC) ++ * ++ * Copyright (C) 2018 Amlogic Corporation ++ * ++ * Licensed under the GPL-2 or later. ++ * ++ */ ++ ++#ifndef __SPIFC_H__ ++#define __SPIFC_H__ ++ ++/* ++ * @reg: controller registers base address. ++ * @mem_map: memory_mapped for read operations. ++ * @core: clk source, usually clk_81, 166M max. ++ * @speed: spi bus frequency, and you should know ++ * we use clk_81 as the clk source now, max ++ * speed is 166M. ++ * @io_num: max io number, SIO0 SIO1 SIO2 SIO3. ++ * @max_cs: the max slave device number, we support ++ * spi-nor, spi-nand now. ++ * @cs_gpios: gpio array, we use the cs pin as ++ * gpio, cause the spifc controller ++ * can not hold enough time sometimes. ++ */ ++ ++struct spifc_platdata { ++ ulong reg; ++ ulong mem_map; ++ u32 speed; ++ u32 mode; ++ u32 io_num; ++ u32 max_cs; ++}; ++ ++/* this is cs pin number, not slave device cs number */ ++/* #define SPIFC_MAX_CS 1 */ ++#define SPIFC_BUS_NUM 0 ++/* slave device cs number */ ++#define SPIFC_SNOR_CS 0 ++#define SPIFC_SNAND_CS 1 ++ ++#endif /* __SPIFC_H__ */ +\ No newline at end of file +diff --git a/include/amlogic/storage.h b/include/amlogic/storage.h +new file mode 100644 +index 00000000000..5bdb4cb00e0 +--- /dev/null ++++ b/include/amlogic/storage.h +@@ -0,0 +1,501 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Header file of storage interface module ++ * ++ * Copyright (C) 2018 Amlogic Corporation ++ * ++ * Licensed under the GPL-2 or later. ++ * ++ */ ++ ++#ifndef __STORAGE_H__ ++#define __STORAGE_H__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define RSV_UNVAIL 140 /* rsv unvail error */ ++ ++#define DISPROTECT_KEY BIT(0) ++#define DISPROTECT_SECURE BIT(1) ++#define DISPROTECT_FBBT BIT(2) ++#define DISPROTECT_HYNIX BIT(3) ++ ++#define PART_PROTECT_FLAG BIT(4) ++enum boot_type_e { ++ BOOT_EMMC = 1, ++ BOOT_SD = 1 << 1, ++ BOOT_NAND_NFTL = 1 << 2, ++ BOOT_NAND_MTD = 1 << 3, ++ BOOT_SNAND = 1 << 4,/* spi nand */ ++ BOOT_SNOR = 1 << 5,/* spi nor */ ++ BOOT_NONE = 0xFF ++}; ++ ++#define RSV_KEY "key" ++#define RSV_ENV "env" ++#define RSV_DTB "dtb" ++#define RSV_BBT "bbt" ++ ++#define DISCRETE_BOOTLOADER 1 ++#define COMPACT_BOOTLOADER 0 ++ ++struct nand_startup_parameter { ++ int page_size; ++ int block_size; ++ int layout_reserve_size; ++ int pages_per_block; ++ int setup_data; ++ /* */ ++ int page0_disable; ++}; ++ ++#define BL2E_STORAGE_PARAM_SIZE (0x80) ++#define BOOT_FIRST_BLOB_SIZE (254*1024) ++#define BOOT_FILLER_SIZE (4*1024) ++#define BOOT_RESERVED_SIZE (4*1024) ++#define BOOT_RANDOM_NONCE (16) ++#define BOOT_BL2E_SIZE (66672) //74864-8K ++#define BOOT_EBL2E_SIZE (BOOT_FILLER_SIZE + BOOT_RESERVED_SIZE + BOOT_BL2E_SIZE) ++#define BOOT_BL2X_SIZE (66672) ++#define MAX_BOOT_AREA_ENTRIES (8) ++/* bl2 core address base */ ++#define BL2_CORE_BASE_OFFSET_EMMC (0x200) ++/* boot area entry index */ ++#define BOOT_AREA_BB1ST (0) ++/* filler and reserved are considered part of the bl2E in storage view */ ++#define BOOT_AREA_BL2E (1) ++#define BOOT_AREA_BL2X (2) ++#define BOOT_AREA_DDRFIP (3) ++#define BOOT_AREA_DEVFIP (4) ++#define BOOT_AREA_INVALID (MAX_BOOT_AREA_ENTRIES) ++ ++typedef struct boot_area_entry { ++ /* name */ ++ char name[11]; ++ /* index */ ++ uint8_t idx; ++ uint64_t offset; ++ uint64_t size; ++} boot_area_entry_t; ++ ++struct boot_layout { ++ boot_area_entry_t *boot_entry; ++}; ++ ++struct emmc_startup_parameter { ++ //sd_emmc_setup_t setup; ++}; ++ ++struct spi_nand_startup_parameter { ++ uint32_t pagesize; ++ uint32_t pages_per_eraseblock; ++ uint32_t eraseblocks_per_lun; ++ uint32_t planes_per_lun; ++ uint32_t luns_per_target; ++ uint32_t ntargets; ++ int layout_reserve_size; ++}; ++ ++struct storage_boot_entry { ++ uint32_t offset; ++ uint32_t size; ++}; ++ ++union storage_independent_parameter { ++ struct nand_startup_parameter nsp; ++ struct emmc_startup_parameter esp; ++ struct spi_nand_startup_parameter snasp; ++}; ++ ++struct storage_startup_parameter { ++ uint8_t boot_device; ++ uint8_t boot_seq; ++ uint8_t boot_bakups; ++ uint8_t reserved; ++ struct storage_boot_entry boot_entry[MAX_BOOT_AREA_ENTRIES]; ++ union storage_independent_parameter sip; ++}; ++ ++struct storage_info_t { ++ u8 name[32]; ++ u8 id[8]; ++ u32 read_unit; ++ u32 write_unit; ++ u32 erase_unit; ++ u64 caps;/* total size */ ++ u8 mode;/* bootloader mode, compact or discrete */ ++}; ++ ++struct storage_t { ++ enum boot_type_e type; ++ struct storage_info_t info; ++ u32 init_flag; ++ struct list_head list; ++ int (*get_part_count)(void); ++ int (*list_part_name)(int idx, char *part_name); ++ /* when part_name is null, default to ops in whole chip */ ++ /* int (*block_is_bad)(const char *part_name, loff_t off); */ ++ u64 (*get_part_size)(const char *part_name); ++ int (*read)(const char *part_name, loff_t off, ++ size_t size, void *dest); ++ int (*write)(const char *part_name, loff_t off, ++ size_t size, void *source); ++ int (*erase)(const char *part_name, loff_t off, ++ size_t size, int scrub_flag); ++ ++#define BOOT_OPS_ALL 0xFF/* for cpy parameter operates all copies */ ++ u8 (*get_copies)(const char *part_name); ++ u64 (*get_copy_size)(const char *part_name); ++ int (*boot_read)(const char *part_name, ++ u8 cpy, size_t size, void *dest); ++ int (*boot_write)(const char *part_name, ++ u8 cpy, size_t size, void *source); ++ int (*boot_erase)(const char *part_name, u8 cpy); ++ ++ u32 (*get_rsv_size)(const char *rsv_name); ++ int (*read_rsv)(const char *rsv_name, size_t size, void *buf); ++ int (*write_rsv)(const char *rsv_name, size_t size, void *buf); ++ int (*erase_rsv)(const char *rsv_name); ++ int (*protect_rsv)(const char *rsv_name, ++ bool ops);/*true:on false:off*/ ++}; ++ ++struct device_node_t { ++ enum boot_type_e index; ++ char *type; ++ int (*pre)(void); ++ int (*probe)(u32 init_flag); ++}; ++ ++/** ++ * we use a valid device list to manage the storage devices, ++ * and every type of device can only exist ONE in this list. ++ * we will scan and add the valid storage device to the list ++ * in the init process, and of cause you can register the device ++ * by you own. ++ */ ++#define NAND_BOOT_NORMAL 0 ++#define NAND_BOOT_UPGRATE 1 ++#define NAND_BOOT_ERASE_PROTECT_CACHE 2 ++#define NAND_BOOT_ERASE_ALL 3 ++#define NAND_BOOT_SCRUB_ALL 4 ++#define NAND_SCAN_ID_INIT 5 ++/** ++ * @usage: init all the valid storage device ++ * ++ * @init_flag: it's only works for MLC/EMMC driver ++ * 0 NAND_BOOT_NORMAL:normal init, but can't operates the phy data area ++ * 1 NAND_BOOT_UPGRATE:same as 0, but operation on phy data area is allowed ++ * 2 NAND_BOOT_ERASE_PROTECT_CACHE:only erase rsv area ++ * 3 NAND_BOOT_ERASE_ALL:erase whole device ++ * 4 NAND_BOOT_SCRUB_ALL:erase whole device ++ * 5 NAND_SCAN_ID_INIT:only read nand id ++ * ++ * @return: init result ++ * 0 = failed ++ * other = device_index that device probe successfully ++ */ ++int store_init(u32 init_flag); ++ ++/** ++ * @usage: register a storage device to the valid list ++ * ++ * @param: the description pointer of your storage device ++ * ++ * @return: registration result ++ * 0 = success ++ * 1 = fail ++ */ ++int store_register(struct storage_t *store_dev); ++ ++/** ++ * @usage: unregister a storage device from the valid list ++ * ++ * @store_dev: the description pointer of your storage device ++ */ ++void store_unregister(struct storage_t *store_dev); ++ ++/** ++ * @usage: check the type of device is valid on this board ++ * ++ * @type: the device type that you want to check ++ * ++ * @return: is the device valid ++ * 0 = invalid ++ * 1 = valid ++ */ ++u8 store_device_valid(enum boot_type_e type); ++ ++/** ++ * @usage: set the 'type' device as current device, and you can operates it ++ * ++ * @type: the device type that you want to set ++ * ++ * @return: result of the operation ++ * 0 = success ++ * other = fail ++ */ ++int store_set_device(enum boot_type_e type); ++ ++/** ++ * @usage: get the type of current storage device ++ * ++ * @return: storage device type ++ */ ++enum boot_type_e store_get_type(void); ++ ++/** ++ * @usage: get information about the current device ++ * ++ * @info: the pointer for the information ++ * ++ * @return: result of the operation ++ * 0 = success ++ * other = fail ++ */ ++int store_get_device_info(struct storage_info_t *info); ++ ++/** ++ * @usage: read data from storage device ++ * ++ * @name: partition name, when it's null the target ++ * will regards as whole device. ++ * @off: offset to the 0 address of partition/device ++ * @size: the amount of bytes to read ++ * @buf: pointer of target buffer ++ * ++ * @return: result of the operation ++ * 0 = success ++ * other = fail ++ */ ++int store_read(const char *name, loff_t off, size_t size, void *buf); ++ ++/** ++ * @usage: write data to storage device ++ * ++ * @name: partition name, when it's null the target ++ * will regards as whole device. ++ * @off: offset to the 0 address of partition/device ++ * @size: the amount of bytes to write ++ * @buf: pointer of source buffer ++ * ++ * @return: result of the operation ++ * 0 = success ++ * other = fail ++ */ ++int store_write(const char *name, loff_t off, size_t size, void *buf); ++ ++/** ++ * @usage: erase the storage device ++ * ++ * @name: partition name, when it's null the target ++ * will regards as whole device. ++ * @off: offset to the 0 address of partition/device ++ * @size: the amount of bytes to erase ++ * @scrub: scrub flag(scrub operates will works only when the device support) ++ * 0 = no scrub, just erase ++ * 1 = use scrub operates instead of erase ++ * @return: result of the operation ++ * 0 = success ++ * other = fail ++ */ ++int store_erase(const char *name, loff_t off, size_t size, int scrub); ++ ++/** ++ * @usage: get the partition size or capacity of device ++ * ++ * @name: partition name, when it's null the target ++ * will regards as whole device. ++ * ++ * @return: the amount of bytes to the partition or device size ++ */ ++u64 store_part_size(const char *name); ++ ++/** ++ * @usage: get the copy number of [name] ++ * ++ * @name: only can be "bl2" or "tpl"/"fip" in discrete mode ++ * be "bootloader" in compact mode ++ * @return: the copy number of the "bootloader" or "tpl" ++ */ ++u8 store_boot_copy_num(const char *name); ++ ++/** ++ * @usage: get the 1st boot copy nubmer of current device. ++ * for eMMC: 0 -> user partition; 1 -> boot0; 2 -> boot1 ++ */ ++u8 store_boot_copy_start(void); ++ ++/** ++ * @usage: get the bootup index of [name] ++ * ++ * @name: do not care discrete mode or compact mode ++ * "bl2" "spl" could be used as the one romboot loaded ++ * "fip" "devfip" "tpl" or "bootloader" would be the main u-boot. ++ * @return: the copy number of the "bootloader" or "tpl" ++ */ ++u8 store_bootup_bootidx(const char *name); ++ ++/** ++ * @usage: restore the bootidx/bootdev etc. ++ */ ++void store_restore_bootidx(void); ++ ++/** ++ * @usage: get the copy size of [name] ++ * ++ * @name: name: only can be "bl2" or "tpl"/"fip" in discrete mode ++ * be "bootloader" in compact mode ++ * ++ * @return: the size of every copy ++ */ ++u64 store_boot_copy_size(const char *name); ++ ++/** ++ * @usage: read the [name] data from storage device ++ * ++ * @name: only can be "bl2" or "tpl"/"fip" in discrete mode ++ * be "bootloader" in compact mode ++ * @copy: which copy you want read ++ * @size: the amount of bytes to read ++ * @buf: pointer of the target buffer ++ * ++ * @return: result of the operation ++ * 0 = success ++ * other = fail ++ */ ++int store_boot_read(const char *name, u8 copy, size_t size, void *buf); ++ ++/** ++ * @usage: write the [name] data into storage device ++ * ++ * @name: only can be "bl2" or "tpl"/"fip" in discrete mode ++ * be "bootloader" in compact mode ++ * @copy: which copy you want write, ++ * it will write to all copies when copy = BOOT_OPS_ALL ++ * @size: the amount of bytes to write ++ * @buf: pointer of the source buffer ++ * ++ * @return: result of the operation ++ * 0 = success ++ * other = fail ++ */ ++int store_boot_write(const char *name, u8 copy, size_t size, void *buf); ++ ++/** ++ * @usage: erase the [name] data ++ * ++ * @name: only can be "bl2" or "tpl"/"fip" in discrete mode ++ * be "bootloader" in compact mode ++ * @copy: which copy you want erase, ++ * it will erase all copies when copy = BOOT_OPS_ALL ++ * ++ * @return: result of the operation ++ * 0 = success ++ * other = fail ++ */ ++int store_boot_erase(const char *name, u8 copy); ++ ++/** ++ * @usage: get the rsv info size ++ * ++ * @name: rsv info name, please refer to ++ * RSV_KEY "key" ++ * RSV_ENV "env" ++ * RSV_DTB "dtb" ++ * RSV_BBT "bbt" ++ * ++ * @return: the amount bytes of the rsv info ++ */ ++u32 store_rsv_size(const char *name); ++ ++/** ++ * @usage: read the rsv info from storage device ++ * ++ * @name: rsv info name, please refer to ++ * RSV_KEY "key" ++ * RSV_ENV "env" ++ * RSV_DTB "dtb" ++ * RSV_BBT "bbt" ++ * @size: the amount of bytes to read ++ * @buf: pointer of the target buffer ++ * ++ * @return: result of the operation ++ * 0 = success ++ * other = fail ++ */ ++int store_rsv_read(const char *name, size_t size, void *buf); ++ ++/** ++ * @usage: write the rsv info to the storage device ++ * ++ * @name: rsv info name, please refer to ++ * RSV_KEY "key" ++ * RSV_ENV "env" ++ * RSV_DTB "dtb" ++ * RSV_BBT "bbt" ++ * @size: the amount of bytes to write ++ * @buf: pointer of the source buffer ++ * ++ * @return: result of the operation ++ * 0 = success ++ * other = fail ++ */ ++int store_rsv_write(const char *name, size_t size, void *buf); ++ ++/** ++ * @usage: erase the rsv info ++ * ++ * @name: rsv info name, please refer to ++ * RSV_KEY "key" ++ * RSV_ENV "env" ++ * RSV_DTB "dtb" ++ * RSV_BBT "bbt" ++ * it will erase all reserve information ++ * when name is null ++ * ++ * @return: result of the operation ++ * 0 = success ++ * other = fail ++ */ ++int store_rsv_erase(const char *name); ++ ++/** ++ * @usage: turn on/off the protection of rsv info ++ * ++ * @name: rsv info name, please refer to ++ * RSV_KEY "key" ++ * RSV_ENV "env" ++ * RSV_DTB "dtb" ++ * RSV_BBT "bbt" ++ * it will operates all reserve information ++ * when name is null ++ * @ops: turn on/off the rsv info protection ++ * true = turn on the protection ++ * flase = turn off the protection ++ * ++ * @return: result of the operation ++ * 0 = success ++ * other = fail ++ */ ++int store_rsv_protect(const char *name, bool ops); ++ ++/** ++ * @usage: get bootloader mode for current storage ++ * ++ * @return: result of the operation ++ * 0 = COMPACT_BOOTLOADER ++ * 1 = DISCRETE_BOOTLOADER ++ */ ++int store_get_device_bootloader_mode(void); ++ ++int sheader_need(void); ++void sheader_load(void *addr); ++ ++#endif/* __STORAGE_H__ */ +diff --git a/include/amlogic/storagekey.h b/include/amlogic/storagekey.h +new file mode 100644 +index 00000000000..f258b82c95c +--- /dev/null ++++ b/include/amlogic/storagekey.h +@@ -0,0 +1,57 @@ ++#ifndef __STORAGEKEY_H__ ++#define __STORAGEKEY_H__ ++ ++ ++/* storage key interface */ ++/** ++ *1.amlkey_init: init storage key ++ * return ok 0, fail not 0 ++ */ ++extern int32_t amlkey_init(uint8_t *seed, uint32_t len); ++ ++/** ++ *2. amlkey_isexsit: query key, already programmed ? ++ * return: exsit 1, non 0 ++ */ ++extern int32_t amlkey_isexsit(const uint8_t * name); ++ ++/** ++ * 3. query if the key is secure ++ * return secure 1, non 0; ++ */ ++extern int32_t amlkey_issecure(const uint8_t * name); ++ ++/** ++ * 4. amlkey_size: actual bytes of key value ++ * return actual size. ++ */ ++extern ssize_t amlkey_size(const uint8_t *name); ++ ++/** ++ *5. amlkey_read: read non-secure key in bytes. ++ * return actual size read back; 0 means read failed! ++ */ ++extern ssize_t amlkey_read(const uint8_t *name, ++ uint8_t *buffer, uint32_t len); ++ ++/** ++ * 6. amlkey_write: write secure/non-secure key in bytes. ++ * return actual size write down. 0 means write failed! ++ */ ++extern ssize_t amlkey_write(const uint8_t *name, ++ uint8_t *buffer, uint32_t len, uint32_t secure); ++ ++/** ++ * 7. get the hash value of programmed secure key | 32bytes length, sha256 ++ * return success 0, fail -1 ++ */ ++extern int32_t amlkey_hash_4_secure(const uint8_t * name, uint8_t * hash); ++ ++/** ++ * 8. amlkey_del: del key by name ++ * return success 0, fail non-0. ++ */ ++extern int32_t amlkey_del(const uint8_t * name); ++ ++ ++#endif /* __STORAGEKEY_H__ */ +diff --git a/include/amlogic/store_wrapper.h b/include/amlogic/store_wrapper.h +new file mode 100644 +index 00000000000..0f3007de959 +--- /dev/null ++++ b/include/amlogic/store_wrapper.h +@@ -0,0 +1,56 @@ ++/* ++ * \file store_wrapper.h ++ * \brief wraaper for storage apis ++ * ++ * \version 1.0.0 ++ * \date 2019/5/30 ++ * \author Sam.Wu ++ * ++ * Copyright (c) 2019 Amlogic. All Rights Reserved. ++ * ++ */ ++#ifndef __STORE_WRAPPER_H__ ++#define __STORE_WRAPPER_H__ ++#include ++ ++//logic write/read, if not MTD, same as store_write ++int store_logic_write(const char *name, loff_t off, size_t size, void *buf); ++ ++int store_logic_read(const char *name, loff_t off, size_t size, void *buf); ++ ++u64 store_logic_cap(const char* partName); ++ ++#define AML_MAGIC_HDR_L (0x4c4d4140) //"@AML" ++#define AML_MAGIC_HDR_R (0x544f4f42) //"BOOT" ++ ++#define AML_MAGIC_CORE (0X54534242) //"BBST" ++#define AML_MAGIC_BL2E (0x45324c42) //"BL2E" ++#define AML_MAGIC_BL2X (0x58324c42) //"BL2X" ++#define AML_MAGIC_DDRF (0x46524444) //"DDRF" ++#define AML_MAGIC_DEVF (0x46564544) //"DEVF" ++typedef struct{ ++ unsigned int nMagic; //"BBST", "BL2E", "BL2X", "DDRF", "DEVF" ++ unsigned int nOffset; //offset from file head of file ++ unsigned int nPayLoadSize; //size of payload ++ unsigned int nReserved; //reserved for future ++}payload_info_item_t, *p_payload_info_item_t; ++ ++typedef struct{ ++ unsigned char szSHA2[32]; //sha256 of sizeof(payload_info_t) - sizeof(szSHA2) ++ unsigned int nMagicL; //"@AML" ++ unsigned int nMagicR; //"BOOT" ++ unsigned char byVersion; //version:0,1,2,.... ++ unsigned char byItemNum; //number of items ++ unsigned short nSize; //sizeof(this) = sizeof(hdr) + sizeof(item) * byItemNum ++ unsigned char szReserved1[4]; ++ char szTimeStamp[16];//"SC2-YYYYMMDDHHmm" e.g "SC2-202007082259" ++ ++}payload_info_hdr_t, *p_payload_info_hdr_t; ++ ++typedef struct{ ++ payload_info_hdr_t hdr; //header ++ payload_info_item_t arrItems[1]; //items ++}payload_info_t, *p_payload_info_t; ++ ++#endif//#ifndef __STORE_WRAPPER_H__ ++ +diff --git a/include/amlstorage/emmc_partitions.h b/include/amlstorage/emmc_partitions.h +new file mode 100644 +index 00000000000..5edc1f89c8f +--- /dev/null ++++ b/include/amlstorage/emmc_partitions.h +@@ -0,0 +1,271 @@ ++#ifndef _AML_MMC_H ++#define _AML_MMC_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include ++#include ++#include ++#include ++ ++#define AML_MMC_DBG ++ ++#define MAX_DEVICE_NUM 32 ++#define MAX_DEVICE_NAME_LEN 16 ++#define MAX_MMC_PART_NUM 32 ++#define MAX_MMC_PART_NAME_LEN 16 ++ ++#ifndef CONFIG_AML_MMC_INHERENT_PART ++#define PARTITION_RESERVED (8*SZ_1M) // 8MB ++#define MMC_BOOT_PARTITION_RESERVED (32*SZ_1M) // 32MB ++#define RESERVED_GPT_OFFSET (36*SZ_1M) // 36MB ++ ++#define MMC_BOOT_NAME "bootloader" ++#define MMC_BOOT_NAME0 "bootloader-boot0" ++#define MMC_BOOT_NAME1 "bootloader-boot1" ++#define MMC_BOOT_DEVICE_SIZE (0x4*SZ_1M) ++ ++#define MMC_RESERVED_NAME "reserved" ++#define MMC_RESERVED_SIZE (64*SZ_1M) ++#define MMC_BOTTOM_RSV_SIZE (0) ++#endif /* CONFIG_AML_MMC_INHERENT_PART */ ++ ++#define MMC_FREERTOS_NAME "rtos-0" ++#define MMC_NBG_NAME "NBG" ++ ++#define MMC_CACHE_NAME "cache" ++// #define MMC_CACHE_SIZE (512*SZ_1M) // this is not used and should be get from spl ++ ++#define MMC_ENV_NAME "env" ++#define MMC_ENV_SIZE (8*SZ_1M) ++ ++#define MMC_KEY_NAME "key" ++#define MMC_KEY_SIZE (256*1024) ++#define EMMCKEY_RESERVE_OFFSET (0x4000) ++#define MMC_RESERVED_OFFSET (36*SZ_1M) ++#define MMC_BLOCK_SIZE (512) ++// #define MMC_SECURE_NAME "secure" ++// #define MMC_SECURE_SIZE (0x1*SZ_1M) ++ ++#define MMC_DDR_PARAMETER_NAME "ddr-parameter" ++#define DDR_PARAMETER_OFFSET (SZ_1M * 8) ++#define DDR_PARAMETER_SIZE (4 * 512) ++ ++#define MMC_MPT_VERSION_1 "01.00.00" ++#define MMC_MPT_VERSION_2 "01.02.00" ++/* version in use, fixme when kenel driver is updated. */ ++#define MMC_MPT_VERSION MMC_MPT_VERSION_1 ++ ++#define MMC_PARTITIONS_MAGIC "MPT" // MMC Partition Table ++#define MMC_CARD_PARTITION_NAME "card" ++ ++/* virtual partitions*/ ++ ++#define MMC_MBR_NAME ("AML_MBR") ++/* offset&size of mbr will not be used */ ++#define MMC_MBR_OFFSET (0x0) ++#define MMC_MBR_SIZE (0x200) ++ ++/* ++* partition table ++* |<----partition_table---->|<----key---->| ++* ++*/ ++#define MMC_TABLE_NAME ("AML_TABLE") ++#define MMC_TABLE_OFFSET (0x0) ++#define MMC_TABLE_SIZE (16*1024) ++ ++/* ++* write 128KB data pattern ++* |<----pattern---->||<------DTB------>| ++*/ ++#define MMC_PATTERN_NAME "pattern" ++#define CALI_PATTERN_OFFSET (SZ_1M * 3) ++#define CALI_PATTERN_SIZE (256 * 512) ++#define CALI_BLOCK_SIZE (512) ++#define CALI_PATTERN (0x55aa55aa) ++ ++#define MMC_MAGIC_NAME "magic" ++#define MAGIC_OFFSET (SZ_1M * 6) ++#define MAGIC_SIZE (256 * 512) ++#define MAGIC_BLOCK_SIZE (512) ++#define MAGIC_PATTERN (0X00FF00FF) ++ ++#define MMC_RANDOM_NAME "random" ++#define RANDOM_OFFSET (SZ_1M * 7) ++#define RANDOM_SIZE (256 * 512) ++#define RANDOM_BLOCK_SIZE (512) ++#define RANDOM_PATTERN (0X52414E44) ++/* ++ * 2 copies dtb were stored in dtb area. ++ * each is 256K. ++ * timestamp&checksum are in the tail. ++ * |<--------------DTB Area-------------->| ++ * |<------DTB1------->|<------DTB2------>| ++ */ ++#define MMC_DTB_NAME "dtb" ++#define DTB_OFFSET (SZ_1M * 4) ++#define DTB_BLK_SIZE (512) ++#define DTB_BLK_CNT (512) ++#define DTB_SIZE (DTB_BLK_CNT * DTB_BLK_SIZE) ++#define DTB_COPIES (2) ++#define DTB_AREA_BLK_CNT (DTB_BLK_CNT * DTB_COPIES) ++#define EMMC_DTB_DEV (1) ++#define EMMC_FASTBOOT_CONTEXT_DEV (1) ++ ++#define MMC_FASTBOOT_CONTEXT_NAME "fastboot_context" ++#define FASTBOOT_CONTEXT_OFFSET (SZ_1M * 5) ++#define FASTBOOT_CONTEXT_SIZE (512) ++#define GPT_LBA_COUNT 34 ++#define GPT_TOTAL_SIZE (GPT_LBA_COUNT * 512) ++ ++struct virtual_partition { ++ char name[MAX_MMC_PART_NAME_LEN]; ++ uint64_t offset; ++ uint64_t size; ++}; ++ ++#define VIRTUAL_PARTITION_ELEMENT(na, of, sz) {.name = na, .offset = of, .size = sz,} ++ ++struct aml_pattern { ++ char name[MAX_MMC_PART_NAME_LEN]; ++ unsigned int pattern; ++}; ++#define AML_PATTERN_ELEMENT(na, pa) {.name = na, .pattern = pa,} ++ ++#ifdef AML_MMC_DBG ++#define aml_mmc_dbg(fmt, ...) printk( "%s: line:%d " fmt "\n", \ ++ __func__, __LINE__, ##__VA_ARGS__) ++ ++#define aml_mmc_msg(fmt, ...) printk( "%s: line:%d " fmt "\n", \ ++ __func__, __LINE__, ##__VA_ARGS__) ++#else ++#define aml_mmc_dbg(fmt, ...) ++#define aml_mmc_msg(fmt, ...) printk( fmt "\n", ##__VA_ARGS__) ++#endif ++ ++#define DOS_MBR 0 ++#define DOS_PBR 1 ++ ++#define DOS_PBR_FSTYPE_OFFSET 0x36 ++#define DOS_PBR32_FSTYPE_OFFSET 0x52 ++ ++#define DOS_PART_DISKSIG_OFFSET 0x1b8 ++#define DOS_PART_TBL_OFFSET 0x1be ++#define DOS_PART_MAGIC_OFFSET 0x1fe ++#define DOS_PBR_MEDIA_TYPE_OFFSET 0x15 ++ ++#define DOS_PARTITION_COUNT 32 ++ ++typedef struct dos_partition { ++ unsigned char boot_ind; /* 0x80 - active */ ++ unsigned char head; /* starting head */ ++ unsigned char sector; /* starting sector */ ++ unsigned char cyl; /* starting cylinder */ ++ unsigned char sys_ind; /* What partition type */ ++ unsigned char end_head; /* end head */ ++ unsigned char end_sector; /* end sector */ ++ unsigned char end_cyl; /* end cylinder */ ++ unsigned char start4[4]; /* starting sector counting from 0 */ ++ unsigned char size4[4]; /* nr of sectors in partition */ ++} dos_partition_t; ++ ++struct dos_mbr_or_ebr{ ++ unsigned char bootstart[446]; ++ struct dos_partition part_entry[4]; ++ unsigned char magic[2]; ++}; ++ ++struct mmc_partitions_fmt { ++ char magic[4]; ++ unsigned char version[12]; ++ int part_num; ++ int checksum; ++ struct partitions partitions[MAX_MMC_PART_NUM]; ++}; ++ ++struct mmc_partition_config{ ++ unsigned char version[12]; ++ int part_num; ++ struct partitions partitions[MAX_MMC_PART_NUM]; ++ unsigned option; ++ void * private_data; ++}; ++ ++/* ++struct _mmc_device{ ++ char name[MAX_DEVICE_NAME_LEN]; ++ uint64_t offset; ++ uint64_t size; ++ void * private_data; ++ struct list_head list; ++}; ++*/ ++ ++#define LOCK_MAJOR_VERSION 1 ++#define LOCK_MINOR_VERSION 0 ++ ++#define LOCK_DATA_SIZE 16 ++ ++typedef struct LockData { ++ uint8_t version_major; ++ uint8_t version_minor; ++ uint8_t unlock_ability; ++ ++ /* Padding to eight bytes. */ ++ uint8_t reserved1; ++ ++ /* 0: unlock 1: lock*/ ++ uint8_t lock_state; ++ ++ /* 0: unlock 1: lock*/ ++ uint8_t lock_critical_state; ++ ++ /* 0: enable bootloader version rollback 1: prevent bootloader version rollback*/ ++ uint8_t lock_bootloader; ++ uint8_t reserved2[1]; ++} LockData_t; ++ ++/*512Bytes*/ ++typedef struct FastbootContext { ++ /* locks */ ++ LockData_t lock; ++ uint8_t rsv[248]; ++ /* checksum, storage driver care */ ++ uint32_t crc32; ++} FastbootContext_t; ++ ++extern bool is_partition_checked; ++extern struct partitions emmc_partition_table[]; ++ ++extern int get_emmc_partition_arraysize(void); ++ ++/* ++ * get the partition number by name ++ * return value ++ * < 0 means no partition found ++ * >= 0 means valid partition ++ */ ++extern int get_partition_num_by_name(char const *name); ++ ++struct partitions* find_mmc_partition_by_name (char const *name); ++struct partitions *aml_get_partition_by_name(const char *name); ++int mmc_boot_size(char *name, uint64_t* size); ++struct virtual_partition *aml_get_virtual_partition_by_name(const char *name); ++bool aml_is_emmc_tsd (struct mmc *mmc); ++int mmc_device_init (struct mmc *mmc); ++ ++#define PARTITION_ELEMENT(na, sz, flags) {.name = na, .size = sz, .mask_flags = flags,} ++ ++#endif +diff --git a/include/amlstorage/emmc_storage.h b/include/amlstorage/emmc_storage.h +new file mode 100644 +index 00000000000..f2dc55fde77 +--- /dev/null ++++ b/include/amlstorage/emmc_storage.h +@@ -0,0 +1,76 @@ ++/*********************************************** ++*****Storage config of board, for ACS use.***** ++***********************************************/ ++ ++#ifndef __STORAGE_H ++#define __STORAGE_H ++ ++#include ++#include ++#ifndef __ASSEMBLY__ ++ ++//Partition table defines ++#define NAND_PART_SIZE_FULL -1 ++#define MAX_PART_NUM 32 ++#define MAX_PART_NAME_LEN 16 ++//#define SZ_1M 0x100000 ++ ++#define STORE_CODE 1 ++#define STORE_CACHE (1<<1) ++#define STORE_DATA (1<<2) ++ ++#define SPI_BOOT_FLAG 0 ++#define NAND_BOOT_FLAG 1 ++#define EMMC_BOOT_FLAG 2 ++#define CARD_BOOT_FLAG 3 ++#define SPI_NAND_FLAG 4 ++#define SPI_EMMC_FLAG 5 ++ ++#define CARD_TYPE_SHIFT 4 ++#define CARD_TYPE_MASK 0xf ++#define CARD_TYPE_UNKNOWN 0 /* unknown */ ++//#define CARD_TYPE_MMC 1 /* MMC card */ ++//#define CARD_TYPE_SD 2 /* SD card */ ++#define CARD_TYPE_SDIO 3 /* SDIO card */ ++#define CARD_TYPE_SD_COMBO 4 /* SD combo (IO+mem) card */ ++#define CARD_TYPE_NON_SDIO 5 /* NON sdio device (means SD/MMC card) */ ++ ++#define AML_GET_CARD_TYPE(val, port) ((val >> (port * CARD_TYPE_SHIFT)) & CARD_TYPE_MASK) ++#define AML_SET_CARD_TYPE(val, port, type) \ ++ (val |= ((type & CARD_TYPE_MASK) << (port * CARD_TYPE_SHIFT))) ++ ++/* storage device */ ++#define STORAGE_DEV_NOSET (0) ++#define STORAGE_DEV_EMMC (1) ++#define STORAGE_DEV_NAND (2) ++#define STORAGE_DEV_SPI (3) ++#define STORAGE_DEV_SDCARD (4) ++#define STORAGE_DEV_USB (5) ++ ++struct partitions { ++ char name[MAX_PART_NAME_LEN]; /* identifier string */ ++ uint64_t size; /* partition size */ ++ uint64_t offset; /* offset within the master space */ ++ unsigned mask_flags; /* master flags to mask out for this partition */ ++}; ++ ++struct config_nand { ++ unsigned enable_slc; ++ unsigned order_ce; ++ unsigned reserved[2]; ++}; ++ ++struct config_mmc { ++ unsigned type; ++ unsigned port; ++ unsigned reserved[2]; ++}; ++ ++struct store_config { ++ unsigned store_device_flag; // indicate storage devices on each board ++ struct config_nand nand_configs; // specital config for nand ++ struct config_mmc mmc_configs; // specital config for mmc ++}; ++ ++#endif ++#endif +diff --git a/include/amlstorage/partition_table.h b/include/amlstorage/partition_table.h +new file mode 100644 +index 00000000000..4e170f3748e +--- /dev/null ++++ b/include/amlstorage/partition_table.h +@@ -0,0 +1,72 @@ ++#ifndef _PARTITION_TABLE_H ++#define _PARTITION_TABLE_H ++// #ifdef CONFIG_STORE_COMPATIBLE ++#include ++#include ++// #endif ++//#include ++//#include ++ ++ ++#define STORE_DBG ++#ifdef STORE_DBG ++#define store_dbg(fmt, ...) printk( "%s: line:%d " fmt "\n", \ ++ __func__, __LINE__, ##__VA_ARGS__) ++ ++#define store_msg(fmt, ...) printk( "%s: line:%d " fmt "\n", \ ++ __func__, __LINE__, ##__VA_ARGS__) ++#else ++#define store_dbg(fmt, ...) ++#define store_msg(fmt, ...) printk( fmt "\n", ##__VA_ARGS__) ++#endif ++ ++//boot_flag ++//#define R_BOOT_DEVICE_FLAG READ_CBUS_REG(ASSIST_POR_CONFIG) ++ ++//#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 ++//#define POR_BOOT_VALUE ((((R_BOOT_DEVICE_FLAG>>9)&1)<<2)|((R_BOOT_DEVICE_FLAG>>6)&3)) ++//#else ++//#define POR_BOOT_VALUE (R_BOOT_DEVICE_FLAG & 7) ++//#endif ++ ++//#if 1 /*defined in poc.h*/ ++//#define POR_NAND_BOOT() ((POR_BOOT_VALUE == 7) || (POR_BOOT_VALUE == 6)) ++//#define POR_SPI_BOOT() ((POR_BOOT_VALUE == 5) || (POR_BOOT_VALUE == 4)) ++//#define POR_EMMC_BOOT() ((IS_MESON_M8M2_CPU | IS_MESON_M8BABY_CPU)?((POR_BOOT_VALUE == 3) || ((POR_BOOT_VALUE == 1))):(POR_BOOT_VALUE == 3)) ++//#define POR_CARD_BOOT() (POR_BOOT_VALUE == 0) ++//#endif ++ ++#define SPI_BOOT_FLAG 0 ++#define NAND_BOOT_FLAG 1 ++#define EMMC_BOOT_FLAG 2 ++#define CARD_BOOT_FLAG 3 ++#define SPI_NAND_FLAG 4 ++#define SPI_EMMC_FLAG 5 ++ ++#define _AML_DEVICE_BOOT_FLAG_DEFAULT (0XFFFFFFFF) ++ ++#define START_ADDR 0xd9000200 ++#define TABLE_MAGIC_NAME "part" ++#define STORE_MAGIC_NAME "stor" ++#define ACS_SET_LEN 128 ++ ++extern int info_disprotect; ++ ++extern int has_boot_slot; ++extern int has_system_slot; ++extern bool dynamic_partition; ++extern bool vendor_boot_partition; ++ ++extern int get_partition_from_dts(unsigned char * buffer); ++ ++extern int get_partitions_table(struct partitions **table); ++ ++#define AML_DTB_IMG_MAX_SZ ((256<<10) - 512) ++extern struct partitions *get_partitions(void); ++ ++extern int get_partition_count(void); ++extern void free_partitions(void); ++/* only nand&emmc for gxb and later soc */ ++ ++#endif// #ifndef _PARTITION_TABLE_H ++ +-- +2.43.2 + diff --git a/patch/u-boot/v2023.10/board_trhubv3l/0004-Copy-and-update-amlogic-2019-aml-partition-keyman-co.patch b/patch/u-boot/v2023.10/board_trhubv3l/0004-Copy-and-update-amlogic-2019-aml-partition-keyman-co.patch new file mode 100644 index 000000000..73f59449c --- /dev/null +++ b/patch/u-boot/v2023.10/board_trhubv3l/0004-Copy-and-update-amlogic-2019-aml-partition-keyman-co.patch @@ -0,0 +1,505 @@ +From aa7c8e63c6a81cf054af4392e7ae1fbf4e9bbf04 Mon Sep 17 00:00:00 2001 +From: Viacheslav Bocharov +Date: Tue, 3 Oct 2023 17:26:36 +0300 +Subject: [PATCH 4/8] Copy and update amlogic-2019 aml partition/keyman code to + mainline (fixes) + +--- + .../meson-axg-jethome-jethub-j100-u-boot.dtsi | 92 +++++++++++++++++ + cmd/Kconfig | 5 + + cmd/Makefile | 3 + + common/Makefile | 3 + + configs/jethub_j100_defconfig | 7 ++ + configs/jethub_j80_defconfig | 7 ++ + disk/Kconfig | 13 +++ + disk/Makefile | 1 + + drivers/Kconfig | 4 + + drivers/Makefile | 3 + + drivers/mmc/Makefile | 3 + + drivers/mmc/mmc.c | 99 ++++++++++++++++++- + include/mmc.h | 25 +++++ + include/part.h | 3 + + 14 files changed, 267 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/dts/meson-axg-jethome-jethub-j100-u-boot.dtsi b/arch/arm/dts/meson-axg-jethome-jethub-j100-u-boot.dtsi +index 3ecb233f8e2..e0e6b2259cc 100644 +--- a/arch/arm/dts/meson-axg-jethome-jethub-j100-u-boot.dtsi ++++ b/arch/arm/dts/meson-axg-jethome-jethub-j100-u-boot.dtsi +@@ -4,6 +4,98 @@ + * Author: Vyacheslav Bocharov + */ + ++/ { ++ partitions: partitions { ++ parts = <1>; ++ part-0 = <&rootfs>; ++ rootfs: rootfs { ++ pname = "rootfs"; ++ size = <0xffffffff 0xffffffff>; ++ mask = <4>; ++ }; ++ }; ++ ++ efusekey: efusekey { ++ keynum = <5>; ++ key0 = <&key_0>; ++ key1 = <&key_1>; ++ key2 = <&key_2>; ++ key3 = <&key_3>; ++ key4 = <&key_4>; ++ ++ key_0: key_0 { ++ keyname = "mac"; ++ offset = <0>; ++ size = <6>; ++ }; ++ key_1: key_1 { ++ keyname = "mac_bt"; ++ offset = <6>; ++ size = <6>; ++ }; ++ key_2: key_2 { ++ keyname = "mac_wifi"; ++ offset = <12>; ++ size = <6>; ++ }; ++ key_3: key_3 { ++ keyname = "usid"; ++ offset = <18>; ++ size = <32>; ++ }; ++ key_4: key_4 { ++ keyname = "serial"; ++ offset = <50>; ++ size = <32>; ++ }; ++ }; //End efusekey ++ ++ unifykey { ++ compatible = "amlogic, unifykey"; ++ status = "ok"; ++ unifykey-num = <6>; ++ unifykey-index-0 = <&keysn_0>; ++ unifykey-index-1 = <&keysn_1>; ++ unifykey-index-2 = <&keysn_2>; ++ unifykey-index-3 = <&keysn_3>; ++ unifykey-index-4 = <&keysn_4>; ++ unifykey-index-5 = <&keysn_5>; ++ ++ keysn_0: key_0 { ++ key-name = "usid"; ++ key-device = "normal"; ++ key-permit = "read"; ++ }; ++ keysn_1: key_1 { ++ key-name = "mac"; ++ key-device = "normal"; ++ key-permit = "read"; ++ }; ++ keysn_2: key_2 { ++ key-name = "mac_bt"; ++ key-device = "normal"; ++ key-permit = "read","write","del"; ++ key-type = "mac"; ++ }; ++ keysn_3: key_3 { ++ key-name = "mac_wifi"; ++ key-device = "normal"; ++ key-permit = "read","write","del"; ++ key-type = "mac"; ++ }; ++ keysn_4: key_4 { ++ key-name = "serial"; ++ key-device = "normal"; ++ key-permit = "read"; ++ }; ++ keysn_5:key_5 { ++ key-name = "deviceid"; ++ key-device = "normal"; ++ key-permit = "read","write","del"; ++ }; ++ }; //End unifykey ++}; ++ + &saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +diff --git a/cmd/Kconfig b/cmd/Kconfig +index 43ca10f69cc..71446cf0923 100644 +--- a/cmd/Kconfig ++++ b/cmd/Kconfig +@@ -2698,6 +2698,11 @@ config CMD_REISER + reiserls - list files + reiserload - load a file + ++config AML_STORAGE ++ bool "aml storage support" ++ help ++ storage cmd support ++ + config CMD_YAFFS2 + bool "yaffs2 - Access of YAFFS2 filesystem" + depends on YAFFS2 +diff --git a/cmd/Makefile b/cmd/Makefile +index 9bebf321c39..1f68971aaee 100644 +--- a/cmd/Makefile ++++ b/cmd/Makefile +@@ -214,6 +214,9 @@ obj-$(CONFIG_CMD_ETHSW) += ethsw.o + obj-$(CONFIG_CMD_AXI) += axi.o + obj-$(CONFIG_CMD_PVBLOCK) += pvblock.o + ++obj-$(CONFIG_AML_STORAGE) += storage.o ++obj-$(CONFIG_CMD_MMC) += aml_mmc.o ++ + # Power + obj-$(CONFIG_CMD_PMIC) += pmic.o + obj-$(CONFIG_CMD_REGULATOR) += regulator.o +diff --git a/common/Makefile b/common/Makefile +index f5c3d90f067..26d9aefeaaf 100644 +--- a/common/Makefile ++++ b/common/Makefile +@@ -11,6 +11,9 @@ obj-y += exports.o + obj-$(CONFIG_HUSH_PARSER) += cli_hush.o + obj-$(CONFIG_AUTOBOOT) += autoboot.o + ++obj-$(CONFIG_AML_STORAGE) += partitions.o ++obj-$(CONFIG_AML_STORAGE) += aml_dt.o ++ + # # boards + obj-y += board_f.o + obj-y += board_r.o +diff --git a/configs/jethub_j100_defconfig b/configs/jethub_j100_defconfig +index 549d5514f7a..26a22d96a6d 100644 +--- a/configs/jethub_j100_defconfig ++++ b/configs/jethub_j100_defconfig +@@ -68,3 +68,10 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e + CONFIG_USB_GADGET_PRODUCT_NUM=0xfada + CONFIG_USB_GADGET_DWC2_OTG=y + CONFIG_USB_GADGET_DOWNLOAD=y ++ ++CONFIG_AML_DRIVER=y ++CONFIG_UNIFY_KEY_MANAGE=y ++CONFIG_SECURE_STORAGE=y ++CONFIG_AML_STORAGE=y ++CONFIG_EFUSE=y ++CONFIG_AML_PARTITION=y +diff --git a/configs/jethub_j80_defconfig b/configs/jethub_j80_defconfig +index df9b8f3aedf..46bc96516e7 100644 +--- a/configs/jethub_j80_defconfig ++++ b/configs/jethub_j80_defconfig +@@ -72,3 +72,10 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e + CONFIG_USB_GADGET_PRODUCT_NUM=0xfada + CONFIG_USB_GADGET_DWC2_OTG=y + CONFIG_USB_GADGET_DOWNLOAD=y ++ ++CONFIG_AML_DRIVER=y ++CONFIG_UNIFY_KEY_MANAGE=y ++CONFIG_SECURE_STORAGE=y ++CONFIG_AML_STORAGE=y ++CONFIG_EFUSE=y ++CONFIG_AML_PARTITION=y +diff --git a/disk/Kconfig b/disk/Kconfig +index 85496958074..5c65ad5065c 100644 +--- a/disk/Kconfig ++++ b/disk/Kconfig +@@ -165,4 +165,17 @@ config SPL_PARTITION_TYPE_GUID + Activate the configuration of GUID type + for EFI partition + ++config AML_PARTITION ++ bool "Enable AML partition table" ++ depends on PARTITIONS ++ help ++ "AML_PARTITION_HELP" ++ ++config AML_GPT ++ bool "Enable AML GPT partition table" ++ depends on PARTITIONS ++ select RANDOM_UUID ++ help ++ "AML_GPT_HELP" ++ + endmenu +diff --git a/disk/Makefile b/disk/Makefile +index 45588cf66e4..23fc28bcbe4 100644 +--- a/disk/Makefile ++++ b/disk/Makefile +@@ -17,4 +17,5 @@ obj-$(CONFIG_$(SPL_TPL_)DOS_PARTITION) += part_dos.o + obj-$(CONFIG_$(SPL_TPL_)ISO_PARTITION) += part_iso.o + obj-$(CONFIG_$(SPL_TPL_)AMIGA_PARTITION) += part_amiga.o + obj-$(CONFIG_$(SPL_TPL_)EFI_PARTITION) += part_efi.o ++#obj-$(CONFIG_AML_PARTITION) += part_aml.o + endif +diff --git a/drivers/Kconfig b/drivers/Kconfig +index a25f6ae02fd..c074b7dce93 100644 +--- a/drivers/Kconfig ++++ b/drivers/Kconfig +@@ -156,6 +156,10 @@ source "drivers/watchdog/Kconfig" + + source "drivers/xen/Kconfig" + ++source "drivers/amlogic/Kconfig" ++ ++source "drivers/efuse/Kconfig" ++ + config PHYS_TO_BUS + bool "Custom physical to bus address mapping" + help +diff --git a/drivers/Makefile b/drivers/Makefile +index efc2a4afb24..91883a77af7 100644 +--- a/drivers/Makefile ++++ b/drivers/Makefile +@@ -43,6 +43,9 @@ obj-$(CONFIG_$(SPL_)VIDEO) += video/ + + obj-y += bus/ + ++obj-$(CONFIG_AML_DRIVER) += amlogic/ ++obj-$(CONFIG_EFUSE) += efuse/ ++ + ifndef CONFIG_TPL_BUILD + ifndef CONFIG_VPL_BUILD + ifdef CONFIG_SPL_BUILD +diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile +index 2c65c4765ab..2ee7af838ed 100644 +--- a/drivers/mmc/Makefile ++++ b/drivers/mmc/Makefile +@@ -4,7 +4,10 @@ + # Wolfgang Denk, DENX Software Engineering, wd@denx.de. + + obj-y += mmc.o ++obj-y += mmc_aml.o + obj-$(CONFIG_$(SPL_)DM_MMC) += mmc-uclass.o ++obj-$(CONFIG_CMD_MMC) += storage_emmc.o ++obj-$(CONFIG_MMC_MESON_GX) += aml_emmc_partition.o + + ifdef CONFIG_$(SPL_TPL_)DM_MMC + obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += mmc_bootdev.o +diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c +index 31cfda28858..9b275b82e14 100644 +--- a/drivers/mmc/mmc.c ++++ b/drivers/mmc/mmc.c +@@ -26,6 +26,24 @@ + #include + #include "mmc_private.h" + ++ ++// TODO amlogic ++#include ++#include ++#include ++#include ++ ++struct aml_pattern aml_pattern_table[] = { ++ AML_PATTERN_ELEMENT(MMC_PATTERN_NAME, CALI_PATTERN), ++ AML_PATTERN_ELEMENT(MMC_MAGIC_NAME, MAGIC_PATTERN), ++ AML_PATTERN_ELEMENT(MMC_RANDOM_NAME, RANDOM_PATTERN), ++}; ++ ++int mmc_pattern_check(struct mmc *mmc, struct aml_pattern *table); ++void mmc_write_cali_mattern(void *addr, struct aml_pattern *table); ++ ++// end TODO ++ + #define DEFAULT_CMD6_TIMEOUT_MS 500 + + static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage); +@@ -2391,6 +2409,12 @@ static int mmc_startup_v4(struct mmc *mmc) + } + #endif + ++ /* dev life time estimate type A/B */ ++ mmc->dev_lifetime_est_typ_a ++ = ext_csd[EXT_CSD_DEV_LIFETIME_EST_TYP_A]; ++ mmc->dev_lifetime_est_typ_b ++ = ext_csd[EXT_CSD_DEV_LIFETIME_EST_TYP_B]; ++ + /* + * Host needs to enable ERASE_GRP_DEF bit if device is + * partitioned. This bit will be lost every time after a reset +@@ -2984,7 +3008,7 @@ static int mmc_complete_init(struct mmc *mmc) + + int mmc_init(struct mmc *mmc) + { +- int err = 0; ++ int err = 0, i; + __maybe_unused ulong start; + #if CONFIG_IS_ENABLED(DM_MMC) + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev); +@@ -3003,6 +3027,18 @@ int mmc_init(struct mmc *mmc) + err = mmc_complete_init(mmc); + if (err) + pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start)); ++ info_disprotect |= DISPROTECT_KEY; ++ if (IS_MMC(mmc)) { ++ if (!is_partition_checked) { ++ if (mmc_device_init(mmc) == 0) { ++ is_partition_checked = true; ++ pr_info("eMMC/TSD partition table have been checked OK!\n"); ++ for (i = 0; i < ARRAY_SIZE(aml_pattern_table); i++) ++ mmc_pattern_check(mmc, &aml_pattern_table[i]); ++ } ++ } ++ } ++ info_disprotect &= ~DISPROTECT_KEY; + + return err; + } +@@ -3193,3 +3229,64 @@ __weak int mmc_get_env_dev(void) + return 0; + #endif + } ++ ++/// TODO: amlogic ++int mmc_pattern_check(struct mmc *mmc, struct aml_pattern *table) ++{ ++ void *addr = NULL; ++ u64 cnt = 0, n = 0, blk = 0; ++ u32 *buf = NULL; ++ u32 crc32_s = 0; ++ struct partitions *part = NULL; ++ struct virtual_partition *vpart = NULL; ++ ++ vpart = aml_get_virtual_partition_by_name(table->name); ++ ++ addr = (void *)malloc(vpart->size); ++ if (!addr) { ++ printf("%s malloc failed\n", table->name); ++ return 1; ++ } ++ part = aml_get_partition_by_name(MMC_RESERVED_NAME); ++ blk = (part->offset + vpart->offset) / mmc->read_bl_len; ++ cnt = vpart->size / mmc->read_bl_len; ++ n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr); ++ if (n != cnt) { ++ printf("read pattern failed\n"); ++ free(addr); ++ return 1; ++ } else { ++ buf = (u32 *)addr; ++ crc32_s = crc32(0, (u8 *)addr, (vpart->size - 4)); ++ if (crc32_s != buf[vpart->size/4 - 1]) { ++ printf("check %s failed,need to write\n", ++ table->name); ++ mmc_write_cali_mattern(addr, table); ++ n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr); ++ printf("several 0x%x pattern blocks write %s\n", ++ table->pattern, (n == cnt) ? "OK" : "ERROR"); ++ } ++ printf("crc32_s:0x%x == storage crc_pattern:0x%x!!!\n", ++ crc32_s, buf[vpart->size/4 - 1]); ++ } ++ free(addr); ++ return (n == cnt) ? 0 : 1; ++} ++ ++ ++void mmc_write_cali_mattern(void *addr, struct aml_pattern *table) ++{ ++ int i = 0; ++ unsigned int s = 10; ++ u32 *mattern = (u32 *)addr; ++ struct virtual_partition *vpart = ++ aml_get_virtual_partition_by_name(table->name); ++ for (i = 0;i < (vpart->size)/4 - 1;i++) { ++ if (!strcmp(table->name, "random")) ++ mattern[i] = rand_r(&s); ++ else ++ mattern[i] = table->pattern; ++ } ++ mattern[i] = crc32(0, (u8 *)addr, (vpart->size - 4)); ++ return; ++} +diff --git a/include/mmc.h b/include/mmc.h +index 1022db3ffa7..721758c3c7b 100644 +--- a/include/mmc.h ++++ b/include/mmc.h +@@ -109,6 +109,10 @@ struct bd_info; + #define MMC_CMD_SET_BLOCK_COUNT 23 + #define MMC_CMD_WRITE_SINGLE_BLOCK 24 + #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 ++#define MMC_CMD_SET_WRITE_PROTECT 28 ++#define MMC_CMD_CLR_WRITE_PROT 29 ++#define MMC_CMD_SEND_WRITE_PROT 30 ++#define MMC_CMD_SEND_WRITE_PROT_TYPE 31 + #define MMC_CMD_ERASE_GROUP_START 35 + #define MMC_CMD_ERASE_GROUP_END 36 + #define MMC_CMD_ERASE 38 +@@ -213,6 +217,7 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) + /* + * EXT_CSD fields + */ ++#define EXT_CSD_CLASS_6_CTRL 59 /*R/W/E_P*/ + #define EXT_CSD_ENH_START_ADDR 136 /* R/W */ + #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */ + #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ +@@ -236,6 +241,7 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) + #define EXT_CSD_HS_TIMING 185 /* R/W */ + #define EXT_CSD_REV 192 /* RO */ + #define EXT_CSD_CARD_TYPE 196 /* RO */ ++#define EXT_CSD_DRIVER_STRENGTH 197 /* RO */ + #define EXT_CSD_PART_SWITCH_TIME 199 /* RO */ + #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ + #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ +@@ -243,6 +249,9 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) + #define EXT_CSD_BOOT_MULT 226 /* RO */ + #define EXT_CSD_SEC_FEATURE 231 /* RO */ + #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */ ++#define EXT_CSD_DEV_LIFETIME_EST_TYP_A 268 /* RO */ ++#define EXT_CSD_DEV_LIFETIME_EST_TYP_B 269 /* RO */ ++ + #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ + + /* +@@ -344,6 +353,20 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) + #define ENHNCD_SUPPORT (0x2) + #define PART_ENH_ATTRIB (0x1f) + ++#define US_PWR_WP_DIS_BIT 1<<3 ++#define US_PERM_WP_DIS_BIT 1<<4 ++#define WP_CLEAR_TYPE 0 ++#define WP_POWER_ON_TYPE (1<<1) ++#define WP_TEMPORARY_TYPE 1 ++#define WP_PERMANENT_TYPE ((1<<0)|(1<<1)) ++#define WP_TYPE_MASK 3 ++#define WP_ENABLE_MASK 7 ++#define WP_TEMPORARY_EN_BIT 0 ++#define WP_POWER_ON_EN_BIT (1<<0) ++#define WP_PERM_EN_BIT (1<<2) ++#define WP_GRP_SIZE_MASK 31 ++ ++ + #define MMC_QUIRK_RETRY_SEND_CID BIT(0) + #define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1) + #define MMC_QUIRK_RETRY_APP_CMD BIT(2) +@@ -703,6 +726,8 @@ struct mmc { + #if CONFIG_IS_ENABLED(MMC_WRITE) + struct sd_ssr ssr; /* SD status register */ + #endif ++ uint dev_lifetime_est_typ_a; ++ uint dev_lifetime_est_typ_b; + u64 capacity; + u64 capacity_user; + u64 capacity_boot; +diff --git a/include/part.h b/include/part.h +index 8e451bbdff9..b61e22c863b 100644 +--- a/include/part.h ++++ b/include/part.h +@@ -30,12 +30,15 @@ struct block_drvr { + #define PART_TYPE_ISO 0x03 + #define PART_TYPE_AMIGA 0x04 + #define PART_TYPE_EFI 0x05 ++#define PART_TYPE_AML 0x06 + + /* maximum number of partition entries supported by search */ + #define DOS_ENTRY_NUMBERS 8 + #define ISO_ENTRY_NUMBERS 64 + #define MAC_ENTRY_NUMBERS 64 + #define AMIGA_ENTRY_NUMBERS 8 ++#define AML_ENTRY_NUMBERS 128 ++ + /* + * Type string for U-Boot bootable partitions + */ +-- +2.43.2 + diff --git a/patch/u-boot/v2023.10/board_trhubv3l/0005-Add-usid-serial-mac-read-from-emmc.patch b/patch/u-boot/v2023.10/board_trhubv3l/0005-Add-usid-serial-mac-read-from-emmc.patch new file mode 100644 index 000000000..a90e67933 --- /dev/null +++ b/patch/u-boot/v2023.10/board_trhubv3l/0005-Add-usid-serial-mac-read-from-emmc.patch @@ -0,0 +1,102 @@ +From 80d41294944231f135eb3b84dfc34658e0318b44 Mon Sep 17 00:00:00 2001 +From: Vyacheslav Bocharov +Date: Tue, 5 Jul 2022 19:06:25 +0300 +Subject: [PATCH 5/8] Add usid/serial/mac read from emmc + +--- + board/amlogic/jethub-j100/jethub-j100.c | 63 +++++++++++++++++++++++-- + 1 file changed, 60 insertions(+), 3 deletions(-) + +diff --git a/board/amlogic/jethub-j100/jethub-j100.c b/board/amlogic/jethub-j100/jethub-j100.c +index 6a2c4ad4c3c..41ef5db4932 100644 +--- a/board/amlogic/jethub-j100/jethub-j100.c ++++ b/board/amlogic/jethub-j100/jethub-j100.c +@@ -5,6 +5,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -20,8 +21,65 @@ int misc_init_r(void) + u8 mac_addr[ARP_HLEN]; + char serial[SM_SERIAL_SIZE]; + u32 sid; ++ int ret; + +- if (!meson_sm_get_serial(serial, SM_SERIAL_SIZE)) { ++ char _cmdbuf[96]; ++ char keyname[32]; ++ char keydata[256]; ++ int ver=0; ++ ++ memset (mac_addr,0, sizeof(mac_addr)); ++ sprintf(_cmdbuf, "store init"); ++ if(!run_command(_cmdbuf, 0)) ++ { ++ sprintf(_cmdbuf, "keyman init 0x1234"); ++ if(!run_command(_cmdbuf, 0)) ++ { ++ strcpy(keyname, "usid"); ++ memset (keydata, 0, sizeof(keydata)); ++ sprintf(_cmdbuf, "keyman read %s %p str", keyname, keydata); ++ ret = run_command(_cmdbuf, 0); ++ if (!ret) ++ { ++ // j100__04012201sw00016142005c ++ // 0123456789 ++ if (keydata[0] == 'j') ++ { ++ if (keydata[1] == '1') ++ { ++ sprintf(_cmdbuf, "%c%c",keydata[6],keydata[7]); ++ env_set("hwrev", _cmdbuf); ++ sprintf(_cmdbuf, "%c%c",keydata[8],keydata[9]); ++ env_set("perev", _cmdbuf); ++ } ++ } ++ } ++ // get serial ++ strcpy(keyname, "serial"); ++ memset (keydata, 0, sizeof(keydata)); ++ sprintf(_cmdbuf, "keyman read %s %p str", keyname, keydata); ++ ret = run_command(_cmdbuf, 0); ++ ++ // get mac ++ strcpy(keyname, "mac"); ++ memset (keydata, 0, sizeof(keydata)); ++ sprintf(_cmdbuf, "keyman read %s %#p str", keyname, keydata); ++ ret = run_command(_cmdbuf, 0); ++ if (keydata[2]==':') ++ { ++ keydata[17] = (char) 0x00; ++ sprintf(_cmdbuf,"env set ethaddr %s", keydata); ++ ret = run_command(_cmdbuf, 0); ++ mac_addr[0] = (char) 0x01; ++ } else ++ { ++ printf("keyman read mac failed\n"); ++ } ++ } ++ } ++ ++ if (mac_addr[0]==0) ++ if (!meson_sm_get_serial(serial, SM_SERIAL_SIZE)) { + sid = crc32(0, (unsigned char *)serial, SM_SERIAL_SIZE); + /* Ensure the NIC specific bytes of the mac are not all 0 */ + if ((sid & 0xffff) == 0) +@@ -34,9 +92,8 @@ int misc_init_r(void) + mac_addr[3] = (sid >> 16) & 0xff; + mac_addr[4] = (sid >> 8) & 0xff; + mac_addr[5] = (sid >> 0) & 0xff; +- + eth_env_set_enetaddr("ethaddr", mac_addr); +- } ++ } + + return 0; + } +-- +2.43.2 + diff --git a/patch/u-boot/v2023.10/board_trhubv3l/0006-HACK-force-disable-efi-options-for-JetHub-D1-H1.patch.disable b/patch/u-boot/v2023.10/board_trhubv3l/0006-HACK-force-disable-efi-options-for-JetHub-D1-H1.patch.disable new file mode 100644 index 000000000..29a220ff9 --- /dev/null +++ b/patch/u-boot/v2023.10/board_trhubv3l/0006-HACK-force-disable-efi-options-for-JetHub-D1-H1.patch.disable @@ -0,0 +1,67 @@ +From 59305d9189e17b1f135112ea0333eac9746e9739 Mon Sep 17 00:00:00 2001 +From: Vyacheslav Bocharov +Date: Thu, 1 Sep 2022 09:53:19 +0300 +Subject: [PATCH 6/8] HACK: force disable efi options for JetHub D1+/H1 + +--- + configs/jethub_j100_defconfig | 19 +++++++++++++++++++ + configs/jethub_j80_defconfig | 19 +++++++++++++++++++ + 2 files changed, 38 insertions(+) + +diff --git a/configs/jethub_j100_defconfig b/configs/jethub_j100_defconfig +index 26a22d96a6d..112445ffefb 100644 +--- a/configs/jethub_j100_defconfig ++++ b/configs/jethub_j100_defconfig +@@ -75,3 +75,22 @@ CONFIG_SECURE_STORAGE=y + CONFIG_AML_STORAGE=y + CONFIG_EFUSE=y + CONFIG_AML_PARTITION=y ++ ++CONFIG_BOOTMETH_EFILOADER=n ++CONFIG_CMD_BOOTEFI=n ++CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n ++CONFIG_EFI_PARTITION=n ++CONFIG_EFI_LOADER=n ++CONFIG_CMD_BOOTEFI_BOOTMGR=n ++CONFIG_EFI_SETUP_EARLY=n ++CONFIG_EFI_VARIABLE_FILE_STORE=n ++CONFIG_EFI_GET_TIME=n ++CONFIG_EFI_DEVICE_PATH_TO_TEXT=n ++CONFIG_EFI_DEVICE_PATH_UTIL=n ++CONFIG_EFI_DT_FIXUP=n ++CONFIG_EFI_LOADER_HII=n ++CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2=n ++CONFIG_EFI_UNICODE_CAPITALIZATION=n ++CONFIG_EFI_HAVE_RUNTIME_RESET=n ++CONFIG_EFI_RNG_PROTOCOL=n ++CONFIG_EFI_LOAD_FILE2_INITRD=n +diff --git a/configs/jethub_j80_defconfig b/configs/jethub_j80_defconfig +index 46bc96516e7..5d1344b0b5e 100644 +--- a/configs/jethub_j80_defconfig ++++ b/configs/jethub_j80_defconfig +@@ -79,3 +79,22 @@ CONFIG_SECURE_STORAGE=y + CONFIG_AML_STORAGE=y + CONFIG_EFUSE=y + CONFIG_AML_PARTITION=y ++ ++CONFIG_BOOTMETH_EFILOADER=n ++CONFIG_CMD_BOOTEFI=n ++CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n ++CONFIG_EFI_PARTITION=n ++CONFIG_EFI_LOADER=n ++CONFIG_CMD_BOOTEFI_BOOTMGR=n ++CONFIG_EFI_SETUP_EARLY=n ++CONFIG_EFI_VARIABLE_FILE_STORE=n ++CONFIG_EFI_GET_TIME=n ++CONFIG_EFI_DEVICE_PATH_TO_TEXT=n ++CONFIG_EFI_DEVICE_PATH_UTIL=n ++CONFIG_EFI_DT_FIXUP=n ++CONFIG_EFI_LOADER_HII=n ++CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2=n ++CONFIG_EFI_UNICODE_CAPITALIZATION=n ++CONFIG_EFI_HAVE_RUNTIME_RESET=n ++CONFIG_EFI_RNG_PROTOCOL=n ++CONFIG_EFI_LOAD_FILE2_INITRD=n +-- +2.43.2 + diff --git a/patch/u-boot/v2023.10/board_trhubv3l/0007-ARM-amlogic-revert-JetHub-D1-eth-mac-generation-with.patch b/patch/u-boot/v2023.10/board_trhubv3l/0007-ARM-amlogic-revert-JetHub-D1-eth-mac-generation-with.patch new file mode 100644 index 000000000..ecbb29d2e --- /dev/null +++ b/patch/u-boot/v2023.10/board_trhubv3l/0007-ARM-amlogic-revert-JetHub-D1-eth-mac-generation-with.patch @@ -0,0 +1,54 @@ +From 4c24d43140370f272a12b0695ffacb85863c51a7 Mon Sep 17 00:00:00 2001 +From: Viacheslav Bocharov +Date: Thu, 22 Dec 2022 15:10:29 +0300 +Subject: [PATCH 7/8] ARM: amlogic: revert JetHub D1 eth mac generation with + manufacturer OUI + +Partially revert add JetHub D1 eth mac generation with manufacturer OUI +commit 4f4f974a46244270c1c6723017711c0aa8250206 + +Signed-off-by: Viacheslav Bocharov +--- + board/amlogic/jethub-j100/jethub-j100.c | 19 +------------------ + 1 file changed, 1 insertion(+), 18 deletions(-) + +diff --git a/board/amlogic/jethub-j100/jethub-j100.c b/board/amlogic/jethub-j100/jethub-j100.c +index 41ef5db4932..0d1cb6b21dc 100644 +--- a/board/amlogic/jethub-j100/jethub-j100.c ++++ b/board/amlogic/jethub-j100/jethub-j100.c +@@ -19,8 +19,6 @@ + int misc_init_r(void) + { + u8 mac_addr[ARP_HLEN]; +- char serial[SM_SERIAL_SIZE]; +- u32 sid; + int ret; + + char _cmdbuf[96]; +@@ -78,22 +76,7 @@ int misc_init_r(void) + } + } + +- if (mac_addr[0]==0) +- if (!meson_sm_get_serial(serial, SM_SERIAL_SIZE)) { +- sid = crc32(0, (unsigned char *)serial, SM_SERIAL_SIZE); +- /* Ensure the NIC specific bytes of the mac are not all 0 */ +- if ((sid & 0xffff) == 0) +- sid |= 0x800000; +- +- /* OUI registered MAC address */ +- mac_addr[0] = 0x10; +- mac_addr[1] = 0x27; +- mac_addr[2] = 0xBE; +- mac_addr[3] = (sid >> 16) & 0xff; +- mac_addr[4] = (sid >> 8) & 0xff; +- mac_addr[5] = (sid >> 0) & 0xff; +- eth_env_set_enetaddr("ethaddr", mac_addr); +- } ++ meson_generate_serial_ethaddr(); + + return 0; + } +-- +2.43.2 + diff --git a/patch/u-boot/v2023.10/board_trhubv3l/0008-board-amlogic-jethub-j100-fix-common-config-header.patch b/patch/u-boot/v2023.10/board_trhubv3l/0008-board-amlogic-jethub-j100-fix-common-config-header.patch new file mode 100644 index 000000000..cca638d64 --- /dev/null +++ b/patch/u-boot/v2023.10/board_trhubv3l/0008-board-amlogic-jethub-j100-fix-common-config-header.patch @@ -0,0 +1,28 @@ +From f55573d59d5bbe04046bb1a4f7b61a64ae5f3f78 Mon Sep 17 00:00:00 2001 +From: Viacheslav Bocharov +Date: Mon, 26 Feb 2024 18:06:30 +0300 +Subject: [PATCH 8/8] board: amlogic: jethub j100: fix common config header + +Fix JetHub board sequence to read correct gpio for rescue button + +Signed-off-by: Viacheslav Bocharov +--- + include/configs/jethub.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/configs/jethub.h b/include/configs/jethub.h +index e22db4991de..2c44bfc853e 100644 +--- a/include/configs/jethub.h ++++ b/include/configs/jethub.h +@@ -11,7 +11,7 @@ + #if defined(CONFIG_MESON_AXG) + #define BOOTENV_DEV_RESCUE(devtypeu, devtypel, instance) \ + "bootcmd_rescue=" \ +- "if gpio input 10; then " \ ++ "if gpio input periphs-banks10; then " \ + "run bootcmd_mmc0; " \ + "run bootcmd_usb0;" \ + "fi;\0" +-- +2.43.2 + diff --git a/patch/u-boot/v2023.10/board_trhubv3l/0010-add-thirdreality-hubv3-linuxbox-support.patch b/patch/u-boot/v2023.10/board_trhubv3l/0010-add-thirdreality-hubv3-linuxbox-support.patch new file mode 100644 index 000000000..26858c5eb --- /dev/null +++ b/patch/u-boot/v2023.10/board_trhubv3l/0010-add-thirdreality-hubv3-linuxbox-support.patch @@ -0,0 +1,1658 @@ +From 5f4ad83874ede037fc03e5e37394f8e4a55ac8e8 Mon Sep 17 00:00:00 2001 +From: "guoping.liu" +Date: Thu, 15 Jan 2026 16:19:57 +0800 +Subject: [PATCH] add thirdreality-hubv3-linuxbox support + +--- + arch/arm/dts/Makefile | 2 + + .../dts/meson-axg-thirdreality-trhub-v3.dts | 338 ++++++++++++++++++ + .../dts/meson-axg-thirdreality-trhub-v3b.dts | 332 +++++++++++++++++ + board/amlogic/jethub-j100/jethub-j100.c | 9 +- + board/amlogic/trhub-v3/MAINTAINERS | 8 + + board/amlogic/trhub-v3/Makefile | 3 + + board/amlogic/trhub-v3/trhub-v3.c | 205 +++++++++++ + board/amlogic/trhub-v3b/MAINTAINERS | 8 + + board/amlogic/trhub-v3b/Makefile | 3 + + board/amlogic/trhub-v3b/trhub-v3b.c | 205 +++++++++++ + common/partitions.c | 22 +- + configs/trhub_v3_defconfig | 77 ++++ + configs/trhub_v3b_defconfig | 77 ++++ + drivers/amlogic/keymanage/key_manage.c | 4 +- + drivers/amlogic/keymanage/key_unify.c | 4 +- + drivers/amlogic/storagekey/storagekey.c | 6 +- + drivers/mmc/aml_emmc_partition.c | 5 +- + drivers/mmc/mmc.c | 12 +- + drivers/mmc/storage_emmc.c | 8 +- + include/configs/trhub.h | 35 ++ + 20 files changed, 1330 insertions(+), 33 deletions(-) + create mode 100644 arch/arm/dts/meson-axg-thirdreality-trhub-v3.dts + create mode 100644 arch/arm/dts/meson-axg-thirdreality-trhub-v3b.dts + create mode 100644 board/amlogic/trhub-v3/MAINTAINERS + create mode 100644 board/amlogic/trhub-v3/Makefile + create mode 100644 board/amlogic/trhub-v3/trhub-v3.c + create mode 100644 board/amlogic/trhub-v3b/MAINTAINERS + create mode 100644 board/amlogic/trhub-v3b/Makefile + create mode 100644 board/amlogic/trhub-v3b/trhub-v3b.c + create mode 100644 configs/trhub_v3_defconfig + create mode 100644 configs/trhub_v3b_defconfig + create mode 100644 include/configs/trhub.h + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 85fd5b1157b..c9cbd168b20 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -206,6 +206,8 @@ dtb-$(CONFIG_ARCH_MESON) += \ + meson-a1-ad401.dtb \ + meson-axg-s400.dtb \ + meson-axg-jethome-jethub-j100.dtb \ ++ meson-axg-thirdreality-trhub-v3.dtb \ ++ meson-axg-thirdreality-trhub-v3b.dtb \ + meson-gxbb-kii-pro.dtb \ + meson-gxbb-nanopi-k2.dtb \ + meson-gxbb-odroidc2.dtb \ +diff --git a/arch/arm/dts/meson-axg-thirdreality-trhub-v3.dts b/arch/arm/dts/meson-axg-thirdreality-trhub-v3.dts +new file mode 100644 +index 00000000000..624ad2ab886 +--- /dev/null ++++ b/arch/arm/dts/meson-axg-thirdreality-trhub-v3.dts +@@ -0,0 +1,338 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Vyacheslav Bocharov ++ * Copyright (c) 2020 JetHome ++ * Author: Aleksandr Kazantsev ++ * Author: Alexey Shevelkin ++ * Author: Vyacheslav Bocharov ++ */ ++ ++/dts-v1/; ++ ++#include "meson-axg.dtsi" ++#include ++#include ++ ++/ { ++ compatible = "thirdreality,trhub-v3", "amlogic,a113x", "amlogic,meson-axg"; ++ model = "ThirdReality TRHub-V3"; ++ aliases { ++ serial0 = &uart_AO; /* Console */ ++ serial1 = &uart_A; /* UART Bluetooth */ ++ serial3 = &uart_AO_B; /* ZigBee */ ++ //serial6 = &uart_B; /* Thread */ ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ /* 2048MB RAM */ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x80000000>; ++ }; ++ ++ reserved-memory { ++ linux,cma { ++ size = <0x0 0x400000>; ++ }; ++ }; ++ ++ emmc_pwrseq: emmc-pwrseq { ++ compatible = "mmc-pwrseq-emmc"; ++ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; ++ }; ++ ++ vcc_3v3: regulator-vcc_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ }; ++ ++ vcc_5v: regulator-vcc_5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC5V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ vddao_3v3: regulator-vddao_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDAO_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_5v>; ++ regulator-always-on; ++ }; ++ ++ vddio_ao18: regulator-vddio_ao18 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDIO_AO18"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ }; ++ ++ vddio_boot: regulator-vddio_boot { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDIO_BOOT"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ }; ++ ++ usb_pwr: regulator-usb_pwr { ++ compatible = "regulator-fixed"; ++ regulator-name = "USB_PWR"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_5v>; ++ regulator-always-on; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>; ++ clocks = <&wifi32k>; ++ clock-names = "ext_clock"; ++ }; ++ ++ wifi32k: wifi32k { ++ compatible = "pwm-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <32768>; ++ pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */ ++ }; ++ ++ thermal-zones { ++ cpu_thermal: cpu-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ thermal-sensors = <&scpi_sensors 0>; ++ trips { ++ cpu_passive: cpu-passive { ++ temperature = <70000>; /* millicelsius */ ++ hysteresis = <2000>; /* millicelsius */ ++ type = "passive"; ++ }; ++ ++ cpu_hot: cpu-hot { ++ temperature = <80000>; /* millicelsius */ ++ hysteresis = <2000>; /* millicelsius */ ++ type = "hot"; ++ }; ++ ++ cpu_critical: cpu-critical { ++ temperature = <100000>; /* millicelsius */ ++ hysteresis = <2000>; /* millicelsius */ ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ cpu_cooling_maps: cooling-maps { ++ map0 { ++ trip = <&cpu_passive>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ ++ map1 { ++ trip = <&cpu_hot>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ ++ onewire { ++ compatible = "w1-gpio"; ++ gpios = <&gpio GPIOA_14 GPIO_ACTIVE_HIGH>; ++ #gpio-cells = <1>; ++ }; ++}; ++ ++&efuse { ++ sn: sn@32 { ++ reg = <0x32 0x20>; ++ }; ++ ++ eth_mac: eth_mac@0 { ++ reg = <0x0 0x6>; ++ }; ++ ++ bt_mac: bt_mac@6 { ++ reg = <0x6 0x6>; ++ }; ++ ++ wifi_mac: wifi_mac@c { ++ reg = <0xc 0x6>; ++ }; ++ ++ bid: bid@12 { ++ reg = <0x12 0x20>; ++ }; ++}; ++ ++/* Internal I2C bus (on CPU module) */ ++&i2c1 { ++ status = "okay"; ++ pinctrl-0 = <&i2c1_z_pins>; ++ pinctrl-names = "default"; ++ ++ /* RTC */ ++ pcf8563: pcf8563@51 { ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ status = "okay"; ++ }; ++}; ++ ++/* Peripheral I2C bus (on motherboard) */ ++&i2c_AO { ++ status = "okay"; ++ pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&pwm_ab { ++ status = "okay"; ++ pinctrl-0 = <&pwm_a_x20_pins>; ++ pinctrl-names = "default"; ++}; ++ ++/* wifi module */ ++&sd_emmc_b { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pinctrl-0 = <&sdio_pins>; ++ pinctrl-1 = <&sdio_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <4>; ++ cap-sd-highspeed; ++ sd-uhs-sdr104; ++ max-frequency = <200000000>; ++ non-removable; ++ disable-wp; ++ ++ mmc-pwrseq = <&sdio_pwrseq>; ++ ++ vmmc-supply = <&vddao_3v3>; ++ vqmmc-supply = <&vddio_boot>; ++ ++ brcmf: wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ }; ++}; ++ ++/* emmc storage */ ++&sd_emmc_c { ++ status = "okay"; ++ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; ++ pinctrl-1 = <&emmc_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ max-frequency = <200000000>; ++ non-removable; ++ disable-wp; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ ++ mmc-pwrseq = <&emmc_pwrseq>; ++ ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vddio_boot>; ++}; ++ ++/* UART Bluetooth */ ++&uart_B { ++ status = "okay"; ++ pinctrl-0 = <&uart_b_z_pins>, <&uart_b_z_cts_rts_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ ++ bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ shutdown-gpios = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ ++/* UART Console */ ++&uart_AO { ++ status = "okay"; ++ pinctrl-0 = <&uart_ao_a_pins>; ++ pinctrl-names = "default"; ++}; ++ ++/* Zigbee */ ++&uart_AO_B { ++ status = "okay"; ++ pinctrl-0 = <&uart_ao_b_z_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&usb { ++ status = "okay"; ++ phy-supply = <&usb_pwr>; ++}; ++ ++&spicc1 { ++ status = "okay"; ++ pinctrl-0 = <&spi1_x_pins>, <&spi1_ss0_x_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&gpio { ++ gpio-line-names = ++ "", "", "", "", "", // 0 - 4 ++ "", "", "", "", "", // 5 - 9 ++ "", "", "", "", "", // 10 - 14 ++ "", "", "", "", "", // 15 - 19 ++ "", "", "", "", "", // 20 - 24 ++ "", "", "", "", "", // 25 - 29 ++ "", "", "", "", "", // 30 - 34 ++ "", "", "", "", "", // 35 - 39 ++ "", "", "", "", "", // 40 - 44 ++ "", "", "", "", "", // 45 - 49 ++ "", "", "", "", "", // 50 - 54 ++ "", "", "", "", "", // 55 - 59 ++ "", "", "", "", "", // 60 - 64 ++ "", "", "", "", "", // 65 - 69 ++ "", "", "", "", "", // 70 - 74 ++ "", "", "", "", "", // 75 - 79 ++ "", "", "", "", "", // 80 - 84 ++ "", ""; // 85-86 ++}; ++ ++&cpu0 { ++ #cooling-cells = <2>; ++}; ++ ++&cpu1 { ++ #cooling-cells = <2>; ++}; ++ ++&cpu2 { ++ #cooling-cells = <2>; ++}; ++ ++&cpu3 { ++ #cooling-cells = <2>; ++}; +diff --git a/arch/arm/dts/meson-axg-thirdreality-trhub-v3b.dts b/arch/arm/dts/meson-axg-thirdreality-trhub-v3b.dts +new file mode 100644 +index 00000000000..f683b585ef4 +--- /dev/null ++++ b/arch/arm/dts/meson-axg-thirdreality-trhub-v3b.dts +@@ -0,0 +1,332 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Vyacheslav Bocharov ++ * Copyright (c) 2020 JetHome ++ * Author: Aleksandr Kazantsev ++ * Author: Alexey Shevelkin ++ * Author: Vyacheslav Bocharov ++ */ ++ ++/dts-v1/; ++ ++#include "meson-axg.dtsi" ++#include ++#include ++ ++/ { ++ compatible = "thirdreality,trhub-v3b", "amlogic,a113x", "amlogic,meson-axg"; ++ model = "ThirdReality TRHub-V3b"; ++ aliases { ++ serial0 = &uart_AO; /* Console */ ++ serial1 = &uart_A; /* UART Bluetooth */ ++ serial3 = &uart_AO_B; /* ZigBee */ ++ //serial6 = &uart_B; /* Thread */ ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ /* 1024MB RAM */ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x40000000>; ++ }; ++ ++ reserved-memory { ++ linux,cma { ++ size = <0x0 0x400000>; ++ }; ++ }; ++ ++ emmc_pwrseq: emmc-pwrseq { ++ compatible = "mmc-pwrseq-emmc"; ++ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; ++ }; ++ ++ vcc_3v3: regulator-vcc_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ }; ++ ++ vcc_5v: regulator-vcc_5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC5V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ vddao_3v3: regulator-vddao_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDAO_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_5v>; ++ regulator-always-on; ++ }; ++ ++ vddio_ao18: regulator-vddio_ao18 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDIO_AO18"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ }; ++ ++ vddio_boot: regulator-vddio_boot { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDIO_BOOT"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ }; ++ ++ usb_pwr: regulator-usb_pwr { ++ compatible = "regulator-fixed"; ++ regulator-name = "USB_PWR"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_5v>; ++ regulator-always-on; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>; ++ clocks = <&wifi32k>; ++ clock-names = "ext_clock"; ++ }; ++ ++ wifi32k: wifi32k { ++ compatible = "pwm-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <32768>; ++ pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */ ++ }; ++ ++ thermal-zones { ++ cpu_thermal: cpu-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ thermal-sensors = <&scpi_sensors 0>; ++ trips { ++ cpu_passive: cpu-passive { ++ temperature = <70000>; /* millicelsius */ ++ hysteresis = <2000>; /* millicelsius */ ++ type = "passive"; ++ }; ++ ++ cpu_hot: cpu-hot { ++ temperature = <80000>; /* millicelsius */ ++ hysteresis = <2000>; /* millicelsius */ ++ type = "hot"; ++ }; ++ ++ cpu_critical: cpu-critical { ++ temperature = <100000>; /* millicelsius */ ++ hysteresis = <2000>; /* millicelsius */ ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ cpu_cooling_maps: cooling-maps { ++ map0 { ++ trip = <&cpu_passive>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ ++ map1 { ++ trip = <&cpu_hot>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++}; ++ ++&efuse { ++ sn: sn@32 { ++ reg = <0x32 0x20>; ++ }; ++ ++ eth_mac: eth_mac@0 { ++ reg = <0x0 0x6>; ++ }; ++ ++ bt_mac: bt_mac@6 { ++ reg = <0x6 0x6>; ++ }; ++ ++ wifi_mac: wifi_mac@c { ++ reg = <0xc 0x6>; ++ }; ++ ++ bid: bid@12 { ++ reg = <0x12 0x20>; ++ }; ++}; ++ ++/* Internal I2C bus (on CPU module) */ ++&i2c1 { ++ status = "okay"; ++ pinctrl-0 = <&i2c1_z_pins>; ++ pinctrl-names = "default"; ++ ++ /* RTC */ ++ pcf8563: pcf8563@51 { ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ status = "okay"; ++ }; ++}; ++ ++/* Peripheral I2C bus (on motherboard) */ ++&i2c_AO { ++ status = "okay"; ++ pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&pwm_ab { ++ status = "okay"; ++ pinctrl-0 = <&pwm_a_x20_pins>; ++ pinctrl-names = "default"; ++}; ++ ++/* wifi module */ ++&sd_emmc_b { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pinctrl-0 = <&sdio_pins>; ++ pinctrl-1 = <&sdio_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <4>; ++ cap-sd-highspeed; ++ sd-uhs-sdr104; ++ max-frequency = <200000000>; ++ non-removable; ++ disable-wp; ++ ++ mmc-pwrseq = <&sdio_pwrseq>; ++ ++ vmmc-supply = <&vddao_3v3>; ++ vqmmc-supply = <&vddio_boot>; ++ ++ brcmf: wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ }; ++}; ++ ++/* emmc storage */ ++&sd_emmc_c { ++ status = "okay"; ++ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; ++ pinctrl-1 = <&emmc_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ max-frequency = <200000000>; ++ non-removable; ++ disable-wp; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ ++ mmc-pwrseq = <&emmc_pwrseq>; ++ ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vddio_boot>; ++}; ++ ++/* UART Bluetooth */ ++&uart_B { ++ status = "okay"; ++ pinctrl-0 = <&uart_b_z_pins>, <&uart_b_z_cts_rts_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ ++ bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ shutdown-gpios = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ ++/* UART Console */ ++&uart_AO { ++ status = "okay"; ++ pinctrl-0 = <&uart_ao_a_pins>; ++ pinctrl-names = "default"; ++}; ++ ++/* UART Wireless module */ ++&uart_AO_B { ++ status = "okay"; ++ pinctrl-0 = <&uart_ao_b_z_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&usb { ++ status = "okay"; ++ phy-supply = <&usb_pwr>; ++}; ++ ++&spicc1 { ++ status = "okay"; ++ pinctrl-0 = <&spi1_x_pins>, <&spi1_ss0_x_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&gpio { ++ gpio-line-names = ++ "", "", "", "", "", // 0 - 4 ++ "", "", "", "", "", // 5 - 9 ++ "", "", "", "", "", // 10 - 14 ++ "", "", "", "", "", // 15 - 19 ++ "", "", "", "", "", // 20 - 24 ++ "", "", "", "", "", // 25 - 29 ++ "", "", "", "", "", // 30 - 34 ++ "", "", "", "", "", // 35 - 39 ++ "", "", "", "", "", // 40 - 44 ++ "", "", "", "", "", // 45 - 49 ++ "", "", "", "", "", // 50 - 54 ++ "", "", "", "", "", // 55 - 59 ++ "", "", "", "", "", // 60 - 64 ++ "", "", "", "", "", // 65 - 69 ++ "", "", "", "", "", // 70 - 74 ++ "", "", "", "", "", // 75 - 79 ++ "", "", "", "", "", // 80 - 84 ++ "", ""; // 85-86 ++}; ++ ++&cpu0 { ++ #cooling-cells = <2>; ++}; ++ ++&cpu1 { ++ #cooling-cells = <2>; ++}; ++ ++&cpu2 { ++ #cooling-cells = <2>; ++}; ++ ++&cpu3 { ++ #cooling-cells = <2>; ++}; +diff --git a/board/amlogic/jethub-j100/jethub-j100.c b/board/amlogic/jethub-j100/jethub-j100.c +index 0d1cb6b21dc..53833e38232 100644 +--- a/board/amlogic/jethub-j100/jethub-j100.c ++++ b/board/amlogic/jethub-j100/jethub-j100.c +@@ -69,10 +69,11 @@ int misc_init_r(void) + sprintf(_cmdbuf,"env set ethaddr %s", keydata); + ret = run_command(_cmdbuf, 0); + mac_addr[0] = (char) 0x01; +- } else +- { +- printf("keyman read mac failed\n"); +- } ++ } ++ //else ++ //{ ++ // printf("keyman read mac failed\n"); ++ //} + } + } + +diff --git a/board/amlogic/trhub-v3/MAINTAINERS b/board/amlogic/trhub-v3/MAINTAINERS +new file mode 100644 +index 00000000000..43f6a5fc86b +--- /dev/null ++++ b/board/amlogic/trhub-v3/MAINTAINERS +@@ -0,0 +1,8 @@ ++JetHome JetHub ++M: Vyacheslav Bocharov ++S: Maintained ++L: u-boot-amlogic@groups.io ++F: board/amlogic/jethub-j100/ ++F: configs/jethub_j100_defconfig ++F: doc/board/amlogic/jethub-j100.rst ++F: include/configs/jethub.h +diff --git a/board/amlogic/trhub-v3/Makefile b/board/amlogic/trhub-v3/Makefile +new file mode 100644 +index 00000000000..9c7a3b1961d +--- /dev/null ++++ b/board/amlogic/trhub-v3/Makefile +@@ -0,0 +1,3 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++ ++obj-y := trhub-v3.o +diff --git a/board/amlogic/trhub-v3/trhub-v3.c b/board/amlogic/trhub-v3/trhub-v3.c +new file mode 100644 +index 00000000000..7776a46d967 +--- /dev/null ++++ b/board/amlogic/trhub-v3/trhub-v3.c +@@ -0,0 +1,205 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2021 Vyacheslav Bocharov ++ * Author: Vyacheslav Bocharov ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define RGB_RED_GPIO 89 ++#define RGB_GREEN_GPIO 4 ++#define RGB_BLUE_GPIO 5 ++ ++ ++// GPIOZ_9 --> 9 ++#define ZIGBEE_RXD_GPIO 9 ++ ++// GPIOX_17 --> 64 ++#define THREAD_RXD_GPIO 64 ++ ++ ++ ++/* RGB LED åˆå§‹åŒ–函数 */ ++static int rgb_led_init(void) ++{ ++ int ret; ++ ++ /* åˆå§‹åŒ–红色 LED GPIO - 直接设置为高电平 */ ++ ret = gpio_request(RGB_RED_GPIO, "rgb_red"); ++ if (ret) { ++ printf("RGB LED: Failed to request red GPIO %d\n", RGB_RED_GPIO); ++ return ret; ++ } ++ gpio_direction_output(RGB_RED_GPIO, 1); ++ ++ /* åˆå§‹åŒ–绿色 LED GPIO - 直接设置为高电平 */ ++ ret = gpio_request(RGB_GREEN_GPIO, "rgb_green"); ++ if (ret) { ++ printf("RGB LED: Failed to request green GPIO %d\n", RGB_GREEN_GPIO); ++ goto err_green; ++ } ++ gpio_direction_output(RGB_GREEN_GPIO, 1); ++ ++ /* åˆå§‹åŒ–è“色 LED GPIO - 直接设置为高电平 */ ++ ret = gpio_request(RGB_BLUE_GPIO, "rgb_blue"); ++ if (ret) { ++ printf("RGB LED: Failed to request blue GPIO %d\n", RGB_BLUE_GPIO); ++ goto err_blue; ++ } ++ gpio_direction_output(RGB_BLUE_GPIO, 1); ++ ++ printf("RGB LED initialized successfully (all pins set to HIGH)\n"); ++ return 0; ++ ++err_blue: ++ gpio_free(RGB_GREEN_GPIO); ++err_green: ++ gpio_free(RGB_RED_GPIO); ++ return ret; ++} ++ ++/* GPIO 输入åˆå§‹åŒ–函数 */ ++static int gpio_input_init(void) ++{ ++ int ret; ++ ++ /* åˆå§‹åŒ– ZIGBEE_RXD_GPIO - è®¾ç½®ä¸ºè¾“å…¥æ¨¡å¼ */ ++ ret = gpio_request(ZIGBEE_RXD_GPIO, "zigbee_rxd"); ++ if (ret) { ++ printf("GPIO INPUT: Failed to request ZIGBEE_RXD GPIO %d\n", ZIGBEE_RXD_GPIO); ++ return ret; ++ } ++ gpio_direction_input(ZIGBEE_RXD_GPIO); ++ ++ /* åˆå§‹åŒ– THREAD_RXD_GPIO - è®¾ç½®ä¸ºè¾“å…¥æ¨¡å¼ */ ++ ret = gpio_request(THREAD_RXD_GPIO, "thread_rxd"); ++ if (ret) { ++ printf("GPIO INPUT: Failed to request THREAD_RXD GPIO %d\n", THREAD_RXD_GPIO); ++ goto err_thread; ++ } ++ gpio_direction_input(THREAD_RXD_GPIO); ++ ++ printf("GPIO inputs initialized successfully (ZIGBEE_RXD: %d, THREAD_RXD: %d)\n", ++ ZIGBEE_RXD_GPIO, THREAD_RXD_GPIO); ++ return 0; ++ ++err_thread: ++ gpio_free(ZIGBEE_RXD_GPIO); ++ return ret; ++} ++ ++ ++int misc_init_r(void) ++{ ++ u8 mac_addr[ARP_HLEN]; ++ char serial[SM_SERIAL_SIZE]; ++ u32 sid; ++ int ret; ++ ++ char _cmdbuf[96]; ++ char keyname[32]; ++ char keydata[256]; ++ int ver=0; ++ ++ /* åˆå§‹åŒ– RGB LED */ ++ ret = rgb_led_init(); ++ if (ret) { ++ printf("Warning: RGB LED initialization failed\n"); ++ } else { ++ /* RGB LED åˆå§‹åŒ–时已ç»è®¾ç½®ä¸ºç™½è‰²ï¼ˆæ‰€æœ‰å¼•è„šä¸ºé«˜ç”µå¹³ï¼‰ */ ++ printf("RGB LED initialized as WHITE (all pins HIGH)\n"); ++ } ++ ++ /* åˆå§‹åŒ– GPIO 输入引脚 */ ++ ret = gpio_input_init(); ++ if (ret) { ++ printf("Warning: GPIO input initialization failed\n"); ++ } else { ++ printf("GPIO inputs initialized successfully\n"); ++ } ++ ++ memset (mac_addr,0, sizeof(mac_addr)); ++ sprintf(_cmdbuf, "store init"); ++ if(!run_command(_cmdbuf, 0)) ++ { ++ sprintf(_cmdbuf, "keyman init 0x1234"); ++ if(!run_command(_cmdbuf, 0)) ++ { ++ strcpy(keyname, "usid"); ++ memset (keydata, 0, sizeof(keydata)); ++ sprintf(_cmdbuf, "keyman read %s %p str", keyname, keydata); ++ ret = run_command(_cmdbuf, 0); ++ if (!ret) ++ { ++#if 0 ++ // j100__04012201sw00016142005c ++ // 0123456789 ++ if (keydata[0] == 'j') ++ { ++ if (keydata[1] == '1') ++ { ++ sprintf(_cmdbuf, "%c%c",keydata[6],keydata[7]); ++ env_set("hwrev", _cmdbuf); ++ sprintf(_cmdbuf, "%c%c",keydata[8],keydata[9]); ++ env_set("perev", _cmdbuf); ++ } ++ } ++#endif ++ } ++ ++ // get serial ++ strcpy(keyname, "serial"); ++ memset (keydata, 0, sizeof(keydata)); ++ sprintf(_cmdbuf, "keyman read %s %p str", keyname, keydata); ++ ret = run_command(_cmdbuf, 0); ++ ++ // get mac ++ strcpy(keyname, "mac"); ++ memset (keydata, 0, sizeof(keydata)); ++ sprintf(_cmdbuf, "keyman read %s %#p str", keyname, keydata); ++ ret = run_command(_cmdbuf, 0); ++ if (keydata[2]==':') ++ { ++ keydata[17] = (char) 0x00; ++ sprintf(_cmdbuf,"env set ethaddr %s", keydata); ++ ret = run_command(_cmdbuf, 0); ++ mac_addr[0] = (char) 0x01; ++ } ++ //else ++ //{ ++ // printf("keyman read mac failed\n"); ++ //} ++ } ++ } ++ ++ if (mac_addr[0]==0) ++ if (!meson_sm_get_serial(serial, SM_SERIAL_SIZE)) { ++ sid = crc32(0, (unsigned char *)serial, SM_SERIAL_SIZE); ++ /* Ensure the NIC specific bytes of the mac are not all 0 */ ++ if ((sid & 0xffff) == 0) ++ sid |= 0x800000; ++ ++ /* OUI registered MAC address */ ++ mac_addr[0] = 0x10; ++ mac_addr[1] = 0x27; ++ mac_addr[2] = 0xBE; ++ mac_addr[3] = (sid >> 16) & 0xff; ++ mac_addr[4] = (sid >> 8) & 0xff; ++ mac_addr[5] = (sid >> 0) & 0xff; ++ eth_env_set_enetaddr("ethaddr", mac_addr); ++ } ++ ++ return 0; ++} +diff --git a/board/amlogic/trhub-v3b/MAINTAINERS b/board/amlogic/trhub-v3b/MAINTAINERS +new file mode 100644 +index 00000000000..43f6a5fc86b +--- /dev/null ++++ b/board/amlogic/trhub-v3b/MAINTAINERS +@@ -0,0 +1,8 @@ ++JetHome JetHub ++M: Vyacheslav Bocharov ++S: Maintained ++L: u-boot-amlogic@groups.io ++F: board/amlogic/jethub-j100/ ++F: configs/jethub_j100_defconfig ++F: doc/board/amlogic/jethub-j100.rst ++F: include/configs/jethub.h +diff --git a/board/amlogic/trhub-v3b/Makefile b/board/amlogic/trhub-v3b/Makefile +new file mode 100644 +index 00000000000..e33f617eb7d +--- /dev/null ++++ b/board/amlogic/trhub-v3b/Makefile +@@ -0,0 +1,3 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++ ++obj-y := trhub-v3b.o +diff --git a/board/amlogic/trhub-v3b/trhub-v3b.c b/board/amlogic/trhub-v3b/trhub-v3b.c +new file mode 100644 +index 00000000000..7776a46d967 +--- /dev/null ++++ b/board/amlogic/trhub-v3b/trhub-v3b.c +@@ -0,0 +1,205 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2021 Vyacheslav Bocharov ++ * Author: Vyacheslav Bocharov ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define RGB_RED_GPIO 89 ++#define RGB_GREEN_GPIO 4 ++#define RGB_BLUE_GPIO 5 ++ ++ ++// GPIOZ_9 --> 9 ++#define ZIGBEE_RXD_GPIO 9 ++ ++// GPIOX_17 --> 64 ++#define THREAD_RXD_GPIO 64 ++ ++ ++ ++/* RGB LED åˆå§‹åŒ–函数 */ ++static int rgb_led_init(void) ++{ ++ int ret; ++ ++ /* åˆå§‹åŒ–红色 LED GPIO - 直接设置为高电平 */ ++ ret = gpio_request(RGB_RED_GPIO, "rgb_red"); ++ if (ret) { ++ printf("RGB LED: Failed to request red GPIO %d\n", RGB_RED_GPIO); ++ return ret; ++ } ++ gpio_direction_output(RGB_RED_GPIO, 1); ++ ++ /* åˆå§‹åŒ–绿色 LED GPIO - 直接设置为高电平 */ ++ ret = gpio_request(RGB_GREEN_GPIO, "rgb_green"); ++ if (ret) { ++ printf("RGB LED: Failed to request green GPIO %d\n", RGB_GREEN_GPIO); ++ goto err_green; ++ } ++ gpio_direction_output(RGB_GREEN_GPIO, 1); ++ ++ /* åˆå§‹åŒ–è“色 LED GPIO - 直接设置为高电平 */ ++ ret = gpio_request(RGB_BLUE_GPIO, "rgb_blue"); ++ if (ret) { ++ printf("RGB LED: Failed to request blue GPIO %d\n", RGB_BLUE_GPIO); ++ goto err_blue; ++ } ++ gpio_direction_output(RGB_BLUE_GPIO, 1); ++ ++ printf("RGB LED initialized successfully (all pins set to HIGH)\n"); ++ return 0; ++ ++err_blue: ++ gpio_free(RGB_GREEN_GPIO); ++err_green: ++ gpio_free(RGB_RED_GPIO); ++ return ret; ++} ++ ++/* GPIO 输入åˆå§‹åŒ–函数 */ ++static int gpio_input_init(void) ++{ ++ int ret; ++ ++ /* åˆå§‹åŒ– ZIGBEE_RXD_GPIO - è®¾ç½®ä¸ºè¾“å…¥æ¨¡å¼ */ ++ ret = gpio_request(ZIGBEE_RXD_GPIO, "zigbee_rxd"); ++ if (ret) { ++ printf("GPIO INPUT: Failed to request ZIGBEE_RXD GPIO %d\n", ZIGBEE_RXD_GPIO); ++ return ret; ++ } ++ gpio_direction_input(ZIGBEE_RXD_GPIO); ++ ++ /* åˆå§‹åŒ– THREAD_RXD_GPIO - è®¾ç½®ä¸ºè¾“å…¥æ¨¡å¼ */ ++ ret = gpio_request(THREAD_RXD_GPIO, "thread_rxd"); ++ if (ret) { ++ printf("GPIO INPUT: Failed to request THREAD_RXD GPIO %d\n", THREAD_RXD_GPIO); ++ goto err_thread; ++ } ++ gpio_direction_input(THREAD_RXD_GPIO); ++ ++ printf("GPIO inputs initialized successfully (ZIGBEE_RXD: %d, THREAD_RXD: %d)\n", ++ ZIGBEE_RXD_GPIO, THREAD_RXD_GPIO); ++ return 0; ++ ++err_thread: ++ gpio_free(ZIGBEE_RXD_GPIO); ++ return ret; ++} ++ ++ ++int misc_init_r(void) ++{ ++ u8 mac_addr[ARP_HLEN]; ++ char serial[SM_SERIAL_SIZE]; ++ u32 sid; ++ int ret; ++ ++ char _cmdbuf[96]; ++ char keyname[32]; ++ char keydata[256]; ++ int ver=0; ++ ++ /* åˆå§‹åŒ– RGB LED */ ++ ret = rgb_led_init(); ++ if (ret) { ++ printf("Warning: RGB LED initialization failed\n"); ++ } else { ++ /* RGB LED åˆå§‹åŒ–时已ç»è®¾ç½®ä¸ºç™½è‰²ï¼ˆæ‰€æœ‰å¼•è„šä¸ºé«˜ç”µå¹³ï¼‰ */ ++ printf("RGB LED initialized as WHITE (all pins HIGH)\n"); ++ } ++ ++ /* åˆå§‹åŒ– GPIO 输入引脚 */ ++ ret = gpio_input_init(); ++ if (ret) { ++ printf("Warning: GPIO input initialization failed\n"); ++ } else { ++ printf("GPIO inputs initialized successfully\n"); ++ } ++ ++ memset (mac_addr,0, sizeof(mac_addr)); ++ sprintf(_cmdbuf, "store init"); ++ if(!run_command(_cmdbuf, 0)) ++ { ++ sprintf(_cmdbuf, "keyman init 0x1234"); ++ if(!run_command(_cmdbuf, 0)) ++ { ++ strcpy(keyname, "usid"); ++ memset (keydata, 0, sizeof(keydata)); ++ sprintf(_cmdbuf, "keyman read %s %p str", keyname, keydata); ++ ret = run_command(_cmdbuf, 0); ++ if (!ret) ++ { ++#if 0 ++ // j100__04012201sw00016142005c ++ // 0123456789 ++ if (keydata[0] == 'j') ++ { ++ if (keydata[1] == '1') ++ { ++ sprintf(_cmdbuf, "%c%c",keydata[6],keydata[7]); ++ env_set("hwrev", _cmdbuf); ++ sprintf(_cmdbuf, "%c%c",keydata[8],keydata[9]); ++ env_set("perev", _cmdbuf); ++ } ++ } ++#endif ++ } ++ ++ // get serial ++ strcpy(keyname, "serial"); ++ memset (keydata, 0, sizeof(keydata)); ++ sprintf(_cmdbuf, "keyman read %s %p str", keyname, keydata); ++ ret = run_command(_cmdbuf, 0); ++ ++ // get mac ++ strcpy(keyname, "mac"); ++ memset (keydata, 0, sizeof(keydata)); ++ sprintf(_cmdbuf, "keyman read %s %#p str", keyname, keydata); ++ ret = run_command(_cmdbuf, 0); ++ if (keydata[2]==':') ++ { ++ keydata[17] = (char) 0x00; ++ sprintf(_cmdbuf,"env set ethaddr %s", keydata); ++ ret = run_command(_cmdbuf, 0); ++ mac_addr[0] = (char) 0x01; ++ } ++ //else ++ //{ ++ // printf("keyman read mac failed\n"); ++ //} ++ } ++ } ++ ++ if (mac_addr[0]==0) ++ if (!meson_sm_get_serial(serial, SM_SERIAL_SIZE)) { ++ sid = crc32(0, (unsigned char *)serial, SM_SERIAL_SIZE); ++ /* Ensure the NIC specific bytes of the mac are not all 0 */ ++ if ((sid & 0xffff) == 0) ++ sid |= 0x800000; ++ ++ /* OUI registered MAC address */ ++ mac_addr[0] = 0x10; ++ mac_addr[1] = 0x27; ++ mac_addr[2] = 0xBE; ++ mac_addr[3] = (sid >> 16) & 0xff; ++ mac_addr[4] = (sid >> 8) & 0xff; ++ mac_addr[5] = (sid >> 0) & 0xff; ++ eth_env_set_enetaddr("ethaddr", mac_addr); ++ } ++ ++ return 0; ++} +diff --git a/common/partitions.c b/common/partitions.c +index 25ad5e447d8..35293599eaa 100644 +--- a/common/partitions.c ++++ b/common/partitions.c +@@ -69,7 +69,7 @@ int check_valid_dts(unsigned char *buffer) + flush_cache((unsigned long)sbuffer, AML_DTB_IMG_MAX_SZ); + ret = aml_sec_boot_check(AML_D_P_IMG_DECRYPT, (long unsigned)sbuffer, AML_DTB_IMG_MAX_SZ, 0); + if (ret) { +- printf("\n %s() %d: Decrypt dtb: Sig Check %d\n", __func__, __LINE__, ret); ++ //printf("\n %s() %d: Decrypt dtb: Sig Check %d\n", __func__, __LINE__, ret); + return -__LINE__; + } + memcpy(buffer, sbuffer, AML_DTB_IMG_MAX_SZ); +@@ -79,10 +79,10 @@ int check_valid_dts(unsigned char *buffer) + #else + dt_addr = (char *)buffer; + #endif +- pr_debug("start dts,buffer=%p,dt_addr=%p\n", buffer, dt_addr); ++ //pr_debug("start dts,buffer=%p,dt_addr=%p\n", buffer, dt_addr); + ret = fdt_check_header(dt_addr); +- if ( ret < 0 ) +- printf("%s: %s\n",__func__,fdt_strerror(ret)); ++ //if ( ret < 0 ) ++ // printf("%s: %s\n",__func__,fdt_strerror(ret)); + /* fixme, is it 0 when ok? */ + return ret; + } +@@ -104,10 +104,10 @@ int get_partition_from_dts(unsigned char *buffer) + goto _err; + + ret = check_valid_dts(buffer); +- printf("%s() %d: ret %d\n",__func__, __LINE__, ret); ++ //printf("%s() %d: ret %d\n",__func__, __LINE__, ret); + if ( ret < 0 ) + { +- printf("%s() %d: ret %d\n",__func__, __LINE__, ret); ++ //printf("%s() %d: ret %d\n",__func__, __LINE__, ret); + goto _err; + } + #ifdef CONFIG_MULTI_DTB +@@ -118,18 +118,18 @@ int get_partition_from_dts(unsigned char *buffer) + nodeoffset = fdt_path_offset(dt_addr, "/partitions"); + if (nodeoffset < 0) + { +- printf("%s: not find /partitions node %s.\n",__func__,fdt_strerror(nodeoffset)); ++ //printf("%s: not find /partitions node %s.\n",__func__,fdt_strerror(nodeoffset)); + ret = -1; + goto _err; + } + parts_num = (int *)fdt_getprop(dt_addr, nodeoffset, "parts", NULL); +- printf("parts: %d\n",be32_to_cpup((u32*)parts_num)); ++ //printf("parts: %d\n",be32_to_cpup((u32*)parts_num)); + + if (parts_num > 0) + { + part_table = (struct partitions *)malloc(sizeof(struct partitions)*(be32_to_cpup((u32*)parts_num))); + if (!part_table) { +- printk("%s part_table alloc _err\n",__func__); ++ //printk("%s part_table alloc _err\n",__func__); + //kfree(data); + return -1; + } +@@ -146,13 +146,13 @@ int get_partition_from_dts(unsigned char *buffer) + + phandle = fdt_getprop(dt_addr, nodeoffset, propname, NULL); + if (!phandle) { +- printf("don't find match part-%d\n",index); ++ //printf("don't find match part-%d\n",index); + goto _err; + } + if (phandle) { + poffset = fdt_node_offset_by_phandle(dt_addr, be32_to_cpup((u32*)phandle)); + if (!poffset) { +- printf("%s:%d,can't find device node\n",__func__,__LINE__); ++ //printf("%s:%d,can't find device node\n",__func__,__LINE__); + goto _err; + } + } +diff --git a/configs/trhub_v3_defconfig b/configs/trhub_v3_defconfig +new file mode 100644 +index 00000000000..bd78e5c7917 +--- /dev/null ++++ b/configs/trhub_v3_defconfig +@@ -0,0 +1,77 @@ ++CONFIG_ARM=y ++CONFIG_SYS_BOARD="trhub-v3" ++CONFIG_SYS_CONFIG_NAME="trhub" ++CONFIG_ARCH_MESON=y ++CONFIG_TEXT_BASE=0x01000000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 ++CONFIG_ENV_SIZE=0x2000 ++CONFIG_DM_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="meson-axg-thirdreality-trhub-v3" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DM_RESET=y ++CONFIG_MESON_AXG=y ++CONFIG_DEBUG_UART_BASE=0xff803000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_IDENT_STRING=" trhubv3" ++CONFIG_SYS_LOAD_ADDR=0x01000000 ++CONFIG_DEBUG_UART=y ++CONFIG_REMAKE_ELF=y ++CONFIG_OF_BOARD_SETUP=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_MISC_INIT_R=y ++CONFIG_SYS_MAXARGS=32 ++# CONFIG_CMD_BDI is not set ++# CONFIG_CMD_IMI is not set ++CONFIG_CMD_EEPROM=y ++CONFIG_CMD_ADC=y ++CONFIG_CMD_GPIO=y ++CONFIG_RANDOM_UUID=y ++CONFIG_CMD_I2C=y ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++CONFIG_CMD_RTC=y ++CONFIG_CMD_REGULATOR=y ++CONFIG_PARTITION_TYPE_GUID=y ++CONFIG_OF_CONTROL=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SARADC_MESON=y ++CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MESON=y ++CONFIG_MMC_MESON_GX=y ++CONFIG_MTD_UBI=y ++CONFIG_PHY_REALTEK=y ++CONFIG_ETH_DESIGNWARE_MESON8B=y ++CONFIG_MESON_GXL_USB_PHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCTRL_MESON_AXG=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_RTC=y ++CONFIG_RTC_PCF8563=y ++CONFIG_DEBUG_UART_ANNOUNCE=y ++CONFIG_DEBUG_UART_SKIP_INIT=y ++CONFIG_MESON_SERIAL=y ++CONFIG_USB=y ++CONFIG_DM_USB_GADGET=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_DWC2=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_DWC3_MESON_GXL=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e ++CONFIG_USB_GADGET_PRODUCT_NUM=0xfada ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++ ++CONFIG_AML_DRIVER=y ++CONFIG_UNIFY_KEY_MANAGE=y ++CONFIG_SECURE_STORAGE=y ++CONFIG_AML_STORAGE=y ++CONFIG_EFUSE=y ++CONFIG_AML_PARTITION=y +diff --git a/configs/trhub_v3b_defconfig b/configs/trhub_v3b_defconfig +new file mode 100644 +index 00000000000..8de72d0d500 +--- /dev/null ++++ b/configs/trhub_v3b_defconfig +@@ -0,0 +1,77 @@ ++CONFIG_ARM=y ++CONFIG_SYS_BOARD="trhub-v3b" ++CONFIG_SYS_CONFIG_NAME="trhub" ++CONFIG_ARCH_MESON=y ++CONFIG_TEXT_BASE=0x01000000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 ++CONFIG_ENV_SIZE=0x2000 ++CONFIG_DM_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="meson-axg-thirdreality-trhub-v3b" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DM_RESET=y ++CONFIG_MESON_AXG=y ++CONFIG_DEBUG_UART_BASE=0xff803000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_IDENT_STRING=" trhubv3b" ++CONFIG_SYS_LOAD_ADDR=0x01000000 ++CONFIG_DEBUG_UART=y ++CONFIG_REMAKE_ELF=y ++CONFIG_OF_BOARD_SETUP=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_MISC_INIT_R=y ++CONFIG_SYS_MAXARGS=32 ++# CONFIG_CMD_BDI is not set ++# CONFIG_CMD_IMI is not set ++CONFIG_CMD_EEPROM=y ++CONFIG_CMD_ADC=y ++CONFIG_CMD_GPIO=y ++CONFIG_RANDOM_UUID=y ++CONFIG_CMD_I2C=y ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++CONFIG_CMD_RTC=y ++CONFIG_CMD_REGULATOR=y ++CONFIG_PARTITION_TYPE_GUID=y ++CONFIG_OF_CONTROL=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SARADC_MESON=y ++CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MESON=y ++CONFIG_MMC_MESON_GX=y ++CONFIG_MTD_UBI=y ++CONFIG_PHY_REALTEK=y ++CONFIG_ETH_DESIGNWARE_MESON8B=y ++CONFIG_MESON_GXL_USB_PHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCTRL_MESON_AXG=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_RTC=y ++CONFIG_RTC_PCF8563=y ++CONFIG_DEBUG_UART_ANNOUNCE=y ++CONFIG_DEBUG_UART_SKIP_INIT=y ++CONFIG_MESON_SERIAL=y ++CONFIG_USB=y ++CONFIG_DM_USB_GADGET=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_DWC2=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_DWC3_MESON_GXL=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e ++CONFIG_USB_GADGET_PRODUCT_NUM=0xfada ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++ ++CONFIG_AML_DRIVER=y ++CONFIG_UNIFY_KEY_MANAGE=y ++CONFIG_SECURE_STORAGE=y ++CONFIG_AML_STORAGE=y ++CONFIG_EFUSE=y ++CONFIG_AML_PARTITION=y +diff --git a/drivers/amlogic/keymanage/key_manage.c b/drivers/amlogic/keymanage/key_manage.c +index f8e0700b0a1..434d7a4d564 100644 +--- a/drivers/amlogic/keymanage/key_manage.c ++++ b/drivers/amlogic/keymanage/key_manage.c +@@ -396,7 +396,7 @@ int key_manage_query_size(const char* keyname, ssize_t* keysize) + return __LINE__; + } + if (!exist) { +- KM_ERR ("key[%s] not programed yet\n", keyname) ; ++ //KM_ERR ("key[%s] not programed yet\n", keyname) ; + return __LINE__; + } + +@@ -455,7 +455,7 @@ int key_manage_query_secure(const char* keyname, int* isSecure) + return __LINE__; + } + if (!exist) { +- KM_ERR ("Key[%s] not programed yet\n", keyname) ; ++ //KM_ERR ("Key[%s] not programed yet\n", keyname) ; + return __LINE__; + } + +diff --git a/drivers/amlogic/keymanage/key_unify.c b/drivers/amlogic/keymanage/key_unify.c +index 069fff08dd2..fff6d174926 100644 +--- a/drivers/amlogic/keymanage/key_unify.c ++++ b/drivers/amlogic/keymanage/key_unify.c +@@ -331,7 +331,7 @@ int key_unify_read(const char *keyname, void* keydata, const unsigned bufLen) + + int ret = theDevOps->pKeyExist(keyname); + if (!ret) { +- KM_ERR("key[%s] not programed yet\n", keyname); ++ //KM_ERR("key[%s] not programed yet\n", keyname); + return __LINE__; + } + +@@ -402,7 +402,7 @@ int key_unify_query_secure(const char* keyname, int* isSecure) + + int ret = theDevOps->pKeyExist (keyname) ; + if (!ret) { +- KM_ERR("key[%s] not programed yet\n", keyname); ++ //KM_ERR("key[%s] not programed yet\n", keyname); + return __LINE__; + } + +diff --git a/drivers/amlogic/storagekey/storagekey.c b/drivers/amlogic/storagekey/storagekey.c +index 646ad3f0ded..bca29c0fc1b 100644 +--- a/drivers/amlogic/storagekey/storagekey.c ++++ b/drivers/amlogic/storagekey/storagekey.c +@@ -68,7 +68,7 @@ static int32_t _amlkey_init(uint8_t *seed, uint32_t len, int encrypt_type) + uint32_t buffer_size, actual_size; + + /* do nothing for now*/ +- printf("%s() enter!\n", __func__); ++ //printf("%s() enter!\n", __func__); + if (storagekey_info.buffer != NULL) { + printf("%s() %d: already init!\n", __func__, __LINE__); + goto _out; +@@ -87,8 +87,8 @@ static int32_t _amlkey_init(uint8_t *seed, uint32_t len, int encrypt_type) + encrypt_type = 0; + secure_storage_set_enctype(encrypt_type); + actual_size = store_rsv_size("key"); +- printf("%s %d actual_size: 0x%x\n", __func__, __LINE__, +- actual_size); ++ //printf("%s %d actual_size: 0x%x\n", __func__, __LINE__, ++ // actual_size); + + storagekey_info.size = min_t(uint32_t, actual_size, buffer_size); + ret = store_rsv_read("key", storagekey_info.size, storagekey_info.buffer); +diff --git a/drivers/mmc/aml_emmc_partition.c b/drivers/mmc/aml_emmc_partition.c +index 550042adb35..6cf56b1718b 100644 +--- a/drivers/mmc/aml_emmc_partition.c ++++ b/drivers/mmc/aml_emmc_partition.c +@@ -39,16 +39,19 @@ DECLARE_GLOBAL_DATA_PTR; + #define CONFIG_MPT_DEBUG (0) + #define GPT_PRIORITY (1) + ++#if (CONFIG_MPT_DEBUG) + #define apt_err(fmt, ...) printf( "%s()-%d: " fmt , \ + __func__, __LINE__, ##__VA_ARGS__) + + #define apt_wrn(fmt, ...) printf( "%s()-%d: " fmt , \ + __func__, __LINE__, ##__VA_ARGS__) +-#if (CONFIG_MPT_DEBUG) ++ + /* for detail debug info */ + #define apt_info(fmt, ...) printf( "%s()-%d: " fmt , \ + __func__, __LINE__, ##__VA_ARGS__) + #else ++#define apt_err(fmt, ...) ++#define apt_wrn(fmt, ...) + #define apt_info(fmt, ...) + #endif + +diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c +index 9b275b82e14..1d317c6c57d 100644 +--- a/drivers/mmc/mmc.c ++++ b/drivers/mmc/mmc.c +@@ -3259,15 +3259,15 @@ int mmc_pattern_check(struct mmc *mmc, struct aml_pattern *table) + buf = (u32 *)addr; + crc32_s = crc32(0, (u8 *)addr, (vpart->size - 4)); + if (crc32_s != buf[vpart->size/4 - 1]) { +- printf("check %s failed,need to write\n", +- table->name); ++ //printf("check %s failed,need to write\n", ++ // table->name); + mmc_write_cali_mattern(addr, table); + n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr); +- printf("several 0x%x pattern blocks write %s\n", +- table->pattern, (n == cnt) ? "OK" : "ERROR"); ++ //printf("several 0x%x pattern blocks write %s\n", ++ // table->pattern, (n == cnt) ? "OK" : "ERROR"); + } +- printf("crc32_s:0x%x == storage crc_pattern:0x%x!!!\n", +- crc32_s, buf[vpart->size/4 - 1]); ++ //printf("crc32_s:0x%x == storage crc_pattern:0x%x!!!\n", ++ // crc32_s, buf[vpart->size/4 - 1]); + } + free(addr); + return (n == cnt) ? 0 : 1; +diff --git a/drivers/mmc/storage_emmc.c b/drivers/mmc/storage_emmc.c +index d938066e49b..437c300fabf 100644 +--- a/drivers/mmc/storage_emmc.c ++++ b/drivers/mmc/storage_emmc.c +@@ -922,9 +922,9 @@ int emmc_pre(void) + } + config_storage_dev_func(storage_dev, mmc); + store_register(storage_dev); +- printf("emmc init success!\n"); ++ //printf("emmc init success!\n"); + } else +- printf("emmc init fail!\n"); ++ //printf("emmc init fail!\n"); + return ret; + } + +@@ -935,10 +935,10 @@ int emmc_probe(uint32_t init_flag) + + ret = mmc_storage_init(init_flag); /*flag 0*/ + if (ret) { +- printf("mmc init failed ret:%x\n", ret); ++ //printf("mmc init failed ret:%x\n", ret); + goto exit_error; + } +- printf("emmc probe success\n"); ++ //printf("emmc probe success\n"); + + exit_error: + return ret; +diff --git a/include/configs/trhub.h b/include/configs/trhub.h +new file mode 100644 +index 00000000000..7c488038894 +--- /dev/null ++++ b/include/configs/trhub.h +@@ -0,0 +1,35 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++ ++#ifndef _THIRDREALITY_HUB_CONFIG_H_ ++#define _THIRDREALITY_HUB_CONFIG_H_ ++ ++#if defined(CONFIG_MESON_AXG) ++#define BOOTENV_DEV_RESCUE(devtypeu, devtypel, instance) \ ++ "bootcmd_rescue=" \ ++ "if gpio input 10; then " \ ++ "run bootcmd_usb0;" \ ++ "fi;\0" ++#else ++#define BOOTENV_DEV_RESCUE(devtypeu, devtypel, instance) \ ++ "bootcmd_rescue=" \ ++ "if test \"${userbutton}\" = \"true\"; then " \ ++ "run bootcmd_mmc0; " \ ++ "fi;\0" ++#endif ++ ++#define BOOTENV_DEV_NAME_RESCUE(devtypeu, devtypel, instance) \ ++ "rescue " ++ ++#ifndef BOOT_TARGET_DEVICES ++#define BOOT_TARGET_DEVICES(func) \ ++ func(RESCUE, rescue, na) \ ++ func(MMC, mmc, 1) \ ++ func(MMC, mmc, 0) \ ++ BOOT_TARGET_DEVICES_USB(func) \ ++ func(PXE, pxe, na) \ ++ func(DHCP, dhcp, na) ++#endif ++ ++#include ++ ++#endif /* _THIRDREALITY_HUB_CONFIG_H_ */ +-- +2.39.5 + diff --git a/patch/u-boot/v2023.10/board_trhubv3l/0011-fixed-led-and-other-pin-ctrl.patch b/patch/u-boot/v2023.10/board_trhubv3l/0011-fixed-led-and-other-pin-ctrl.patch new file mode 100644 index 000000000..435203027 --- /dev/null +++ b/patch/u-boot/v2023.10/board_trhubv3l/0011-fixed-led-and-other-pin-ctrl.patch @@ -0,0 +1,119 @@ +From 67ce71f819b5a4a966bad3113416a2849b84f154 Mon Sep 17 00:00:00 2001 +From: "guoping.liu" +Date: Mon, 19 Jan 2026 15:04:14 +0800 +Subject: [PATCH] fixed led and other pin ctrl + +--- + board/amlogic/trhub-v3/trhub-v3.c | 42 ++++++++++++++++++++++------- + board/amlogic/trhub-v3b/trhub-v3b.c | 25 ++++++++++------- + drivers/amlogic/keymanage/km_dts.c | 2 +- + 3 files changed, 50 insertions(+), 19 deletions(-) + +diff --git a/board/amlogic/trhub-v3/trhub-v3.c b/board/amlogic/trhub-v3/trhub-v3.c +index 7776a46d967..e8bf6420490 100644 +--- a/board/amlogic/trhub-v3/trhub-v3.c ++++ b/board/amlogic/trhub-v3/trhub-v3.c +@@ -18,16 +18,40 @@ + + #include + +-#define RGB_RED_GPIO 89 +-#define RGB_GREEN_GPIO 4 +-#define RGB_BLUE_GPIO 5 +- +- +-// GPIOZ_9 --> 9 +-#define ZIGBEE_RXD_GPIO 9 ++/* ++ * GPIO Bank 顺åºåœ¨ä¸åŒ U-Boot 版本中å‘生了å˜åŒ–: ++ * ++ * v2022.10: aobus-banks(0-13), periphs-banks(14-99) ++ * v2023.10: periphs-banks(0-85), aobus-banks(86-99) ++ * ++ * 硬件连接: ++ * - RGB_RED: GPIOAO_3 ++ * - RGB_GREEN: GPIOZ_4 ++ * - RGB_BLUE: GPIOZ_5 ++ * - ZIGBEE_RXD: GPIOZ_9 ++ * - THREAD_RXD: GPIOX_17 ++ * ++ * 使用 UBOOT_GPIO_BANK_V2023 å®æ¥é€‰æ‹©ç‰ˆæœ¬: ++ * - ä¸å®šä¹‰(默认): 使用 v2022.10 çš„ GPIO ç¼–å· ++ * - 定义为 1: 使用 v2023.10 çš„ GPIO ç¼–å· ++ */ + +-// GPIOX_17 --> 64 +-#define THREAD_RXD_GPIO 64 ++#if 1 ++/* U-Boot v2023.10+: periphs-banks(0-85), aobus-banks(86-99) */ ++#define RGB_RED_GPIO 3 //GPIOAO_3 0 + 3 = 3 ++#define RGB_GREEN_GPIO 18 //GPIOZ_4 14 + 4 = 18 ++#define RGB_BLUE_GPIO 19 //GPIOZ_5 14 + 5 = 19 ++#define ZIGBEE_RXD_GPIO 23 //GPIOZ_9 14 + 9 = 23 ++#define THREAD_RXD_GPIO 78 //GPIOX_17 47 + 17 = 64 ++#else ++/* U-Boot v2022.10: aobus-banks(0-13), periphs-banks(14-99) */ ++#define RGB_RED_GPIO 89 //GPIOAO_3 86 + 3 = 89 ++#define RGB_GREEN_GPIO 4 //GPIOZ_4 14 + 4 = 18 ++#define RGB_BLUE_GPIO 5 //GPIOZ_5 14 + 5 = 19 ++#define ZIGBEE_RXD_GPIO 9 //GPIOZ_9 14 + 9 = 23 ++#define THREAD_RXD_GPIO 64 //GPIOX_17 47 + 17 = 64 ++ ++#endif + + + +diff --git a/board/amlogic/trhub-v3b/trhub-v3b.c b/board/amlogic/trhub-v3b/trhub-v3b.c +index 7776a46d967..005ede89c74 100644 +--- a/board/amlogic/trhub-v3b/trhub-v3b.c ++++ b/board/amlogic/trhub-v3b/trhub-v3b.c +@@ -18,17 +18,24 @@ + + #include + +-#define RGB_RED_GPIO 89 +-#define RGB_GREEN_GPIO 4 +-#define RGB_BLUE_GPIO 5 ++#if 1 ++/* U-Boot v2023.10+: periphs-banks(0-85), aobus-banks(86-99) */ ++#define RGB_RED_GPIO 3 //GPIOAO_3 0 + 3 = 3 ++#define RGB_GREEN_GPIO 18 //GPIOZ_4 14 + 4 = 18 ++#define RGB_BLUE_GPIO 19 //GPIOZ_5 14 + 5 = 19 ++#define ZIGBEE_RXD_GPIO 23 //GPIOZ_9 14 + 9 = 23 ++#define THREAD_RXD_GPIO 78 //GPIOX_17 47 + 17 = 64 ++#else ++/* U-Boot v2022.10: aobus-banks(0-13), periphs-banks(14-99) */ ++#define RGB_RED_GPIO 89 //GPIOAO_3 86 + 3 = 89 ++#define RGB_GREEN_GPIO 4 //GPIOZ_4 14 + 4 = 18 ++#define RGB_BLUE_GPIO 5 //GPIOZ_5 14 + 5 = 19 ++#define ZIGBEE_RXD_GPIO 9 //GPIOZ_9 14 + 9 = 23 ++#define THREAD_RXD_GPIO 64 //GPIOX_17 47 + 17 = 64 ++ ++#endif + + +-// GPIOZ_9 --> 9 +-#define ZIGBEE_RXD_GPIO 9 +- +-// GPIOX_17 --> 64 +-#define THREAD_RXD_GPIO 64 +- + + + /* RGB LED åˆå§‹åŒ–函数 */ +diff --git a/drivers/amlogic/keymanage/km_dts.c b/drivers/amlogic/keymanage/km_dts.c +index d2a2186147a..2db0d20a649 100644 +--- a/drivers/amlogic/keymanage/km_dts.c ++++ b/drivers/amlogic/keymanage/km_dts.c +@@ -291,7 +291,7 @@ int keymanage_dts_parse(const void* dt_addr) + + nodeoffset = fdt_path_offset(dt_addr, "/unifykey"); + if (nodeoffset < 0) { +- KM_ERR("dts: err(%s) in find /unifykey.\n",fdt_strerror(nodeoffset)); ++ //KM_ERR("dts: err(%s) in find /unifykey.\n",fdt_strerror(nodeoffset)); + return __LINE__; + } + +-- +2.39.5 + diff --git a/patch/u-boot/v2023.10/board_trhubv3l/0012-add-thirdreality-hubv3l-support.patch b/patch/u-boot/v2023.10/board_trhubv3l/0012-add-thirdreality-hubv3l-support.patch new file mode 100644 index 000000000..db8452301 --- /dev/null +++ b/patch/u-boot/v2023.10/board_trhubv3l/0012-add-thirdreality-hubv3l-support.patch @@ -0,0 +1,116 @@ +From: ThirdReality +Subject: [PATCH] board: amlogic: add ThirdReality HubV3L + +HubV3L (LinuxBox-Lite MB0.5) shares the HubV3 pinout and board code; only +RAM differs (2x DDR3, 2 ranks, 1GB). Add a v3l DTS that includes v3 and +overrides /memory, plus trhub_v3l_defconfig. +--- +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -208,6 +208,7 @@ + meson-axg-jethome-jethub-j100.dtb \ + meson-axg-thirdreality-trhub-v3.dtb \ + meson-axg-thirdreality-trhub-v3b.dtb \ ++ meson-axg-thirdreality-trhub-v3l.dtb \ + meson-gxbb-kii-pro.dtb \ + meson-gxbb-nanopi-k2.dtb \ + meson-gxbb-odroidc2.dtb \ +--- a/arch/arm/dts/meson-axg-thirdreality-trhub-v3l.dts ++++ b/arch/arm/dts/meson-axg-thirdreality-trhub-v3l.dts +@@ -0,0 +1,16 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * ThirdReality HubV3L (LinuxBox-Lite MB0.5): same pinout as HubV3, ++ * 2x DDR3 16bit 2 ranks = 1GB. ++ */ ++ ++#include "meson-axg-thirdreality-trhub-v3.dts" ++ ++/ { ++ compatible = "thirdreality,trhub-v3l", "amlogic,a113x", "amlogic,meson-axg"; ++ model = "ThirdReality TRHub-V3L"; ++ ++ memory@0 { ++ reg = <0x0 0x0 0x0 0x40000000>; ++ }; ++}; +--- a/configs/trhub_v3l_defconfig ++++ b/configs/trhub_v3l_defconfig +@@ -0,0 +1,77 @@ ++CONFIG_ARM=y ++CONFIG_SYS_BOARD="trhub-v3" ++CONFIG_SYS_CONFIG_NAME="trhub" ++CONFIG_ARCH_MESON=y ++CONFIG_TEXT_BASE=0x01000000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 ++CONFIG_ENV_SIZE=0x2000 ++CONFIG_DM_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="meson-axg-thirdreality-trhub-v3l" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DM_RESET=y ++CONFIG_MESON_AXG=y ++CONFIG_DEBUG_UART_BASE=0xff803000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_IDENT_STRING=" trhubv3l" ++CONFIG_SYS_LOAD_ADDR=0x01000000 ++CONFIG_DEBUG_UART=y ++CONFIG_REMAKE_ELF=y ++CONFIG_OF_BOARD_SETUP=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_MISC_INIT_R=y ++CONFIG_SYS_MAXARGS=32 ++# CONFIG_CMD_BDI is not set ++# CONFIG_CMD_IMI is not set ++CONFIG_CMD_EEPROM=y ++CONFIG_CMD_ADC=y ++CONFIG_CMD_GPIO=y ++CONFIG_RANDOM_UUID=y ++CONFIG_CMD_I2C=y ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++CONFIG_CMD_RTC=y ++CONFIG_CMD_REGULATOR=y ++CONFIG_PARTITION_TYPE_GUID=y ++CONFIG_OF_CONTROL=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SARADC_MESON=y ++CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MESON=y ++CONFIG_MMC_MESON_GX=y ++CONFIG_MTD_UBI=y ++CONFIG_PHY_REALTEK=y ++CONFIG_ETH_DESIGNWARE_MESON8B=y ++CONFIG_MESON_GXL_USB_PHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCTRL_MESON_AXG=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_RTC=y ++CONFIG_RTC_PCF8563=y ++CONFIG_DEBUG_UART_ANNOUNCE=y ++CONFIG_DEBUG_UART_SKIP_INIT=y ++CONFIG_MESON_SERIAL=y ++CONFIG_USB=y ++CONFIG_DM_USB_GADGET=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_DWC2=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_DWC3_MESON_GXL=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e ++CONFIG_USB_GADGET_PRODUCT_NUM=0xfada ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++ ++CONFIG_AML_DRIVER=y ++CONFIG_UNIFY_KEY_MANAGE=y ++CONFIG_SECURE_STORAGE=y ++CONFIG_AML_STORAGE=y ++CONFIG_EFUSE=y ++CONFIG_AML_PARTITION=y From b1448f482235dc9e8120627a47e1708afd7336b0 Mon Sep 17 00:00:00 2001 From: "guoping.liu" Date: Sat, 10 Oct 2026 17:22:46 +0800 Subject: [PATCH 5/9] fix(firstrun): Enable W155S1 WiFi/BT services on TRHub-V3L armbian-firstrun only enabled amlogicw1 and amlogicw1-bt for V3, V3B and V3A, so V3L booted with both services disabled and no wlan0. --- packages/bsp/common/usr/lib/armbian/armbian-firstrun | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/packages/bsp/common/usr/lib/armbian/armbian-firstrun b/packages/bsp/common/usr/lib/armbian/armbian-firstrun index 0b3d15436..fdcd86d43 100755 --- a/packages/bsp/common/usr/lib/armbian/armbian-firstrun +++ b/packages/bsp/common/usr/lib/armbian/armbian-firstrun @@ -118,7 +118,7 @@ case "$1" in # [[ "${LINUXFAMILY}" == meson64 ]] && set_fixed_mac # [[ "${BOARD}" == nanopi-r6* ]] && set_fixed_mac - if [[ $BOARD_NAME == "TRHub-V3" || $BOARD_NAME == "TRHub-V3B" || $BOARD_NAME == "TRHub-V3A" ]]; then + if [[ $BOARD_NAME == "TRHub-V3" || $BOARD_NAME == "TRHub-V3B" || $BOARD_NAME == "TRHub-V3A" || $BOARD_NAME == "TRHub-V3L" ]]; then systemctl enable NetworkManager systemctl enable wpa_supplicant From 0b4f2810ebc782a5effaf7088695e41799a78b0e Mon Sep 17 00:00:00 2001 From: "guoping.liu" Date: Sat, 10 Oct 2026 17:44:20 +0800 Subject: [PATCH 6/9] feat(burn): Move v3a/v3b off JetHub FIP and loaders, drop JetHub burn files - v3b = v3 hardware: FIP thirdreality-hubv3, bins/hubv3, dt-id axg_hubv3_v1 - v3a = v3l RAM (2x DDR3, 2 ranks, 1GB): FIP thirdreality-hubv3l, bins/hubv3l, dt-id axg_hubv3l_v1. Its u-boot DTS hardcoded 2GB via trhub_v3_defconfig; add trhub_v3a_defconfig + 1GB v3a DTS (0013) and make board_trhubv3a a copy of board_trhubv3l instead of a symlink to v3 - fix 1GB /memory in the v3a and v3l burn DTS - remove bins/j100 j80 j200 magicbox, JetHub DTS, non-axg dtsi/headers, convert.sh d1/d2/h1/cma and the jethubj* release cases; rewrite README - linuxbox board keeps jethub-j100 FIP (no SDK board for it) --- amlogic-tools.repo/README.md | 22 +- amlogic-tools.repo/bins/image.cfg | 17 - amlogic-tools.repo/bins/j100/DDR.USB | Bin 49152 -> 0 bytes amlogic-tools.repo/bins/j100/DDR_ENC.USB | Bin 49152 -> 0 bytes amlogic-tools.repo/bins/j100/UBOOT.USB | Bin 1123840 -> 0 bytes amlogic-tools.repo/bins/j100/UBOOT_ENC.USB | Bin 1123840 -> 0 bytes amlogic-tools.repo/bins/j100/platform.conf | 9 - amlogic-tools.repo/bins/j200/DDR.USB | Bin 1344368 -> 0 bytes amlogic-tools.repo/bins/j200/UBOOT.USB | Bin 1344368 -> 0 bytes amlogic-tools.repo/bins/j200/platform.conf | 8 - amlogic-tools.repo/bins/j80/DDR.USB | Bin 49152 -> 0 bytes amlogic-tools.repo/bins/j80/UBOOT.USB | Bin 802816 -> 0 bytes amlogic-tools.repo/bins/j80/platform.conf | 9 - amlogic-tools.repo/bins/magicbox/DDR.USB | Bin 49152 -> 0 bytes amlogic-tools.repo/bins/magicbox/DDR_ENC.USB | Bin 49152 -> 0 bytes amlogic-tools.repo/bins/magicbox/UBOOT.USB | Bin 1123840 -> 0 bytes .../bins/magicbox/UBOOT_ENC.USB | Bin 1123840 -> 0 bytes .../bins/magicbox/platform.conf | 9 - amlogic-tools.repo/bins/magicbox/u-boot.bin | Bin 1172992 -> 0 bytes .../bins/magicbox/u-boot.bin.encrypt | Bin 1173504 -> 0 bytes .../bins/magicbox/u-boot.bin.encrypt.sd.bin | Bin 1173504 -> 0 bytes .../bins/magicbox/u-boot.bin.sd.bin | Bin 1173504 -> 0 bytes amlogic-tools.repo/convert.sh | 20 +- .../dts/dt-bindings/clock/amlogic,g12a-clkc.h | 329 - .../dt-bindings/clock/amlogic,sm1-audio-clk.h | 95 - .../dts/dt-bindings/clock/gxbb-aoclkc.h | 74 - .../dts/dt-bindings/clock/gxbb-clkc.h | 151 - .../dts/dt-bindings/gpio/meson-g12a-gpio.h | 117 - .../dts/dt-bindings/gpio/meson-gxl-gpio.h | 125 - .../dts/dt-bindings/iio/adc/amlogic-saradc.h | 32 - .../dts/dt-bindings/input/meson_rc.h | 64 - .../dts/dt-bindings/phy/phy-amlogic-pcie.h | 19 - .../dts/dt-bindings/power/meson-gxbb-power.h | 13 - .../reset/amlogic,meson-gxbb-reset.h | 161 - .../dts/include/meson-g12-common.dtsi | 2957 - amlogic-tools.repo/dts/include/meson-gx.dtsi | 664 - amlogic-tools.repo/dts/include/meson-gxl.dtsi | 925 - amlogic-tools.repo/dts/include/meson-sm1.dtsi | 1286 - .../dts/include/mesong12_odroid_common.dtsi | 265 - .../dts/include/mesong12a-bifrost.dtsi | 129 - amlogic-tools.repo/dts/include/mesonsm1.dtsi | 2530 - .../dts/meson-axg-jethome-jethub-j100.dts | 354 - .../dts/meson-axg-thirdreality-trhub-v3a.dts | 6 +- .../dts/meson-axg-thirdreality-trhub-v3b.dts | 2 +- .../dts/meson-axg-thirdreality-trhub-v3l.dts | 4 +- .../meson-gxl-s905w-jethome-jethub-j80.dts | 310 - .../dts/meson-sm1-jethome-jethub-j200.dts | 1005 - config/boards/trhubv3a.conf | 4 +- config/sources/families/trhub.conf | 8 +- make-armbian-build-release.sh | 12 - ...jethome-0006-add-arm64-dts-trhub-v3a.patch | 2 +- patch/u-boot/v2023.10/board_trhubv3a | 1 - ...001-HACK-mmc-meson-gx-limit-to-24MHz.patch | 26 + ...change-clock-phase-value-on-axg-SoCs.patch | 54 + ...amlogic-2019-aml-partition-keyman-co.patch | 63704 ++++++++++++++++ ...amlogic-2019-aml-partition-keyman-co.patch | 505 + ...5-Add-usid-serial-mac-read-from-emmc.patch | 102 + ...efi-options-for-JetHub-D1-H1.patch.disable | 67 + ...rt-JetHub-D1-eth-mac-generation-with.patch | 54 + ...jethub-j100-fix-common-config-header.patch | 28 + ...-thirdreality-hubv3-linuxbox-support.patch | 1658 + .../0011-fixed-led-and-other-pin-ctrl.patch | 119 + ...0012-add-thirdreality-hubv3l-support.patch | 116 + ...0013-add-thirdreality-hubv3a-1gb-dts.patch | 117 + 64 files changed, 66584 insertions(+), 11704 deletions(-) delete mode 100644 amlogic-tools.repo/bins/image.cfg delete mode 100644 amlogic-tools.repo/bins/j100/DDR.USB delete mode 100644 amlogic-tools.repo/bins/j100/DDR_ENC.USB delete mode 100644 amlogic-tools.repo/bins/j100/UBOOT.USB delete mode 100644 amlogic-tools.repo/bins/j100/UBOOT_ENC.USB delete mode 100644 amlogic-tools.repo/bins/j100/platform.conf delete mode 100644 amlogic-tools.repo/bins/j200/DDR.USB delete mode 100644 amlogic-tools.repo/bins/j200/UBOOT.USB delete mode 100644 amlogic-tools.repo/bins/j200/platform.conf delete mode 100644 amlogic-tools.repo/bins/j80/DDR.USB delete mode 100644 amlogic-tools.repo/bins/j80/UBOOT.USB delete mode 100644 amlogic-tools.repo/bins/j80/platform.conf delete mode 100644 amlogic-tools.repo/bins/magicbox/DDR.USB delete mode 100644 amlogic-tools.repo/bins/magicbox/DDR_ENC.USB delete mode 100644 amlogic-tools.repo/bins/magicbox/UBOOT.USB delete mode 100644 amlogic-tools.repo/bins/magicbox/UBOOT_ENC.USB delete mode 100644 amlogic-tools.repo/bins/magicbox/platform.conf delete mode 100644 amlogic-tools.repo/bins/magicbox/u-boot.bin delete mode 100644 amlogic-tools.repo/bins/magicbox/u-boot.bin.encrypt delete mode 100644 amlogic-tools.repo/bins/magicbox/u-boot.bin.encrypt.sd.bin delete mode 100644 amlogic-tools.repo/bins/magicbox/u-boot.bin.sd.bin delete mode 100644 amlogic-tools.repo/dts/dt-bindings/clock/amlogic,g12a-clkc.h delete mode 100644 amlogic-tools.repo/dts/dt-bindings/clock/amlogic,sm1-audio-clk.h delete mode 100644 amlogic-tools.repo/dts/dt-bindings/clock/gxbb-aoclkc.h delete mode 100644 amlogic-tools.repo/dts/dt-bindings/clock/gxbb-clkc.h delete mode 100644 amlogic-tools.repo/dts/dt-bindings/gpio/meson-g12a-gpio.h delete mode 100644 amlogic-tools.repo/dts/dt-bindings/gpio/meson-gxl-gpio.h delete mode 100644 amlogic-tools.repo/dts/dt-bindings/iio/adc/amlogic-saradc.h delete mode 100644 amlogic-tools.repo/dts/dt-bindings/input/meson_rc.h delete mode 100644 amlogic-tools.repo/dts/dt-bindings/phy/phy-amlogic-pcie.h delete mode 100644 amlogic-tools.repo/dts/dt-bindings/power/meson-gxbb-power.h delete mode 100644 amlogic-tools.repo/dts/dt-bindings/reset/amlogic,meson-gxbb-reset.h delete mode 100644 amlogic-tools.repo/dts/include/meson-g12-common.dtsi delete mode 100644 amlogic-tools.repo/dts/include/meson-gx.dtsi delete mode 100644 amlogic-tools.repo/dts/include/meson-gxl.dtsi delete mode 100644 amlogic-tools.repo/dts/include/meson-sm1.dtsi delete mode 100644 amlogic-tools.repo/dts/include/mesong12_odroid_common.dtsi delete mode 100644 amlogic-tools.repo/dts/include/mesong12a-bifrost.dtsi delete mode 100644 amlogic-tools.repo/dts/include/mesonsm1.dtsi delete mode 100644 amlogic-tools.repo/dts/meson-axg-jethome-jethub-j100.dts delete mode 100644 amlogic-tools.repo/dts/meson-gxl-s905w-jethome-jethub-j80.dts delete mode 100644 amlogic-tools.repo/dts/meson-sm1-jethome-jethub-j200.dts delete mode 120000 patch/u-boot/v2023.10/board_trhubv3a create mode 100644 patch/u-boot/v2023.10/board_trhubv3a/0001-HACK-mmc-meson-gx-limit-to-24MHz.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3a/0002-mmc-meson-gx-change-clock-phase-value-on-axg-SoCs.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3a/0003-Copy-and-update-amlogic-2019-aml-partition-keyman-co.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3a/0004-Copy-and-update-amlogic-2019-aml-partition-keyman-co.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3a/0005-Add-usid-serial-mac-read-from-emmc.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3a/0006-HACK-force-disable-efi-options-for-JetHub-D1-H1.patch.disable create mode 100644 patch/u-boot/v2023.10/board_trhubv3a/0007-ARM-amlogic-revert-JetHub-D1-eth-mac-generation-with.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3a/0008-board-amlogic-jethub-j100-fix-common-config-header.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3a/0010-add-thirdreality-hubv3-linuxbox-support.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3a/0011-fixed-led-and-other-pin-ctrl.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3a/0012-add-thirdreality-hubv3l-support.patch create mode 100644 patch/u-boot/v2023.10/board_trhubv3a/0013-add-thirdreality-hubv3a-1gb-dts.patch diff --git a/amlogic-tools.repo/README.md b/amlogic-tools.repo/README.md index d694223f9..bf0758275 100644 --- a/amlogic-tools.repo/README.md +++ b/amlogic-tools.repo/README.md @@ -1,5 +1,21 @@ -# jethome-tools +# amlogic-tools -Разработка Ð¿Ñ€ÐµÐ¾Ð±Ñ€Ð°Ð·Ð¾Ð²Ð°Ð½Ð¸Ñ Ð¾Ð±Ñ€Ð°Ð·Ð¾Ð² SD -> USB Burning Tool +Convert an Armbian SD image of a ThirdReality HubV3 board into an Amlogic +USB Burning Tool image. -**Внимание** Репозиторий может быть перезапиÑан Ñ force push. +``` +./convert.sh [compress] +``` + +| Variant | Board | USB loaders | amlogic-dt-id | +|---|---|---|---| +| v3, v3b | HubV3 / HubV3B, DDR4 2GB | `bins/hubv3` | `axg_hubv3_v1` | +| v3l, v3a | HubV3L / HubV3A, DDR3 2 ranks 1GB | `bins/hubv3l` | `axg_hubv3l_v1` | + +`bins/*/DDR.USB` and `UBOOT.USB` are `u-boot.bin.usb.bl2` and +`u-boot.bin.usb.tpl` built from the Amlogic OpenLinux SDK 2025r1 boards +`axg_hubv3_v1` / `axg_hubv3l_v1`. Their `checkhw()` name must equal the +`amlogic-dt-id` in `dts/`, and it must have exactly three `_` fields because +`dtbtools/dtbTool.c` only parses `soc_platform_variant`. + +`tools/aml_image_v2_packer_new` is the Amlogic packer, identical to the SDK copy. diff --git a/amlogic-tools.repo/bins/image.cfg b/amlogic-tools.repo/bins/image.cfg deleted file mode 100644 index 8e6669cbe..000000000 --- a/amlogic-tools.repo/bins/image.cfg +++ /dev/null @@ -1,17 +0,0 @@ -[LIST_NORMAL] -file="DDR.USB" main_type="USB" sub_type="DDR" -file="UBOOT.USB" main_type="USB" sub_type="UBOOT" -file="_aml_dtb.PARTITION" main_type="dtb" sub_type="meson1" -file="platform.conf" main_type="conf" sub_type="platform" - -[LIST_VERIFY] -file="_aml_dtb.PARTITION" main_type="PARTITION" sub_type="_aml_dtb" -file="u-boot.bin" main_type="PARTITION" sub_type="bootloader" -file="part-1.img" main_type="PARTITION" sub_type="boothaos" -file="part-2.img" main_type="PARTITION" sub_type="overlay" -file="part-3.img" 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