From da2d6d7275d9a32564dd5906484f5a9e467c8bf7 Mon Sep 17 00:00:00 2001
From: jel221 <jlaurenceleigh@gmail.com>
Date: Thu, 15 Oct 2026 22:36:30 -0700
Subject: [PATCH] dispatch fix on single-packet inst

CONFIGS="-DVX_CFG_NUM_THREADS=16 -DVX_CFG_NUM_WARPS=16 -DVX_CFG_NUM_FPU_LANES=1" ./ci/blackbox.sh --driver=rtlsim --app=dogfood --args="-n1 -ttrig"
---
 hw/rtl/core/VX_lane_dispatch.sv | 5 ++++-
 hw/rtl/libs/VX_nz_iterator.sv   | 5 +++--
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/rtl/core/VX_lane_dispatch.sv b/hw/rtl/core/VX_lane_dispatch.sv
index b6ae6126a1..664df578b5 100644
--- a/hw/rtl/core/VX_lane_dispatch.sv
+++ b/hw/rtl/core/VX_lane_dispatch.sv
@@ -64,6 +64,7 @@ module VX_lane_dispatch import VX_gpu_pkg::*; #(
         assign dispatch_if[i].ready = dispatch_ready[i];
     end
 
+    wire [BLOCK_SIZE-1:0] block_valid;
     wire [BLOCK_SIZE-1:0] block_ready;
     wire [BLOCK_SIZE-1:0][NUM_LANES-1:0] block_tmask;
     wire [BLOCK_SIZE-1:0][2:0][NUM_LANES-1:0][`VX_CFG_XLEN-1:0] block_rsdata;
@@ -177,6 +178,7 @@ module VX_lane_dispatch import VX_gpu_pkg::*; #(
             assign block_pid[block_idx]   = start_p;
             assign block_sop[block_idx]   = is_first_p;
             assign block_eop[block_idx]   = is_last_p;
+            assign block_valid[block_idx] = valid_p;
             assign block_ready[block_idx] = ready_p;
             assign block_done[block_idx]  = (fire_p && is_last_p) || ~dispatch_valid[issue_idx];
         end else begin : g_full_simd
@@ -186,6 +188,7 @@ module VX_lane_dispatch import VX_gpu_pkg::*; #(
             assign block_pid[block_idx]   = 0;
             assign block_sop[block_idx]   = 1;
             assign block_eop[block_idx]   = 1;
+            assign block_valid[block_idx] = valid_p;
             assign block_ready[block_idx] = ready_p;
             assign block_done[block_idx]  = ready_p || ~valid_p;
         end
@@ -240,7 +243,7 @@ module VX_lane_dispatch import VX_gpu_pkg::*; #(
     always @(*) begin
         ready_in = 0;
         for (integer block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin
-            ready_in[issue_indices[block_idx]] = block_ready[block_idx] && block_eop[block_idx];
+            ready_in[issue_indices[block_idx]] = block_valid[block_idx] && block_ready[block_idx] && block_eop[block_idx];
         end
     end
     assign dispatch_ready = ready_in;
diff --git a/hw/rtl/libs/VX_nz_iterator.sv b/hw/rtl/libs/VX_nz_iterator.sv
index 5a364b7166..f0348a2c34 100644
--- a/hw/rtl/libs/VX_nz_iterator.sv
+++ b/hw/rtl/libs/VX_nz_iterator.sv
@@ -73,9 +73,10 @@ module VX_nz_iterator #(
         wire is_last_p = (start_p == end_p);
 
         wire enable = valid_in && (~valid_out || next);
+        wire eop_out = valid_out && eop;
 
         always @(posedge clk) begin
-            if (reset || (enable && (is_last_p || eop))) begin
+            if (reset || (enable && (is_last_p || eop_out))) begin
                 sent_mask_p <= '0;
                 is_first_p <= 1;
             end else if (enable) begin
@@ -90,7 +91,7 @@ module VX_nz_iterator #(
             .DEPTH  (OUT_REG)
         ) pipe_reg (
             .clk      (clk),
-            .reset    (reset || (enable && eop)),
+            .reset    (reset || (enable && eop_out)),
             .enable   (enable),
             .data_in  ({valid_in,  data_in[start_p], start_p, is_first_p, is_last_p}),
             .data_out ({valid_out, data_out,         pid,     sop,        eop})