benchmarked-silicon

A catalog of open chip blocks that are tested, documented, and eventually measured on real silicon.

Each block should include RTL, tests, a short datasheet, and notes on what has actually been verified. If a block gets taped out, we also publish bench results like max frequency, voltage behavior, bugs, and predicted vs actual performance.

The goal is to make open silicon IP more useful than just “here is some Verilog.” If a block is in the catalog, people should be able to see how it was tested, what worked, what failed, and who built it.

Example blocks

UART, FIFO, SPI, I2C, GPIO, PWM, timers, bus adapters, ring oscillators, SRAM controllers, and other small reusable blocks.

Basic structure

blocks/
  block_name/
    rtl/
    tb/
    docs/
    layout/
    measurements/
    README.md

Why

AI can write RTL quickly. It cannot fabricate a chip, probe it on a bench, or publish honest silicon measurements.

That is what this repo is for.