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contract: Register128 slab reading + classid-free register rails; bounded power sums end to end (D-LXC-29) - #1324
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…s (D-LXC-29) SlabReading::Register128 = 1: a 128-bit working register with no classid in its payload. Its semantic identity is the SPOG context it is resolved under; Facet96 is unchanged. - ValueTenant::Register0 / Register1 (16 B each) appended at row offsets [252,268) and [268,284); additive, stride unchanged, so no ENVELOPE_LAYOUT_VERSION bump (bumping it would make every existing Facet96 slab fail closed). Full carries them, as it carries every tenant. - register128::Register128 (16 raw LE bytes, words()/from_words) and RegisterLanes, the per-population binding. - ResolvedReading::bind_register128: grants the rails once, only for a Register128 slab whose value schema materialises them; otherwise ActivationDrift::NotRegister128 / RegisterRailAbsent. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X1YcYMRSFvfczXoP748wtB
Resolve the SPOG context once, bind both rails once, fold tile by tile through ndarray's bounded kernels, store each tile's registers per group in the value-slab rails, read back, widen and merge: equals the wide i32 path over a four-tile population, univariate and bivariate. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X1YcYMRSFvfczXoP748wtB
…ontract inventory Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X1YcYMRSFvfczXoP748wtB
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📝 WalkthroughWalkthroughThe change adds two register tenants to the Full value schema and introduces Register128 lane access and resolved-reading binding. An end-to-end test checks bounded tiled statistics stored in register rails against whole-population i32 results. Board records describe the contract, measurements, and open integration items. ChangesRegister128 Statistics
Priority: ⬇️ Low Estimated code review effort: 3 (Moderate) | ~25 minutes Change: Feature Merge Risk: 🟡 Moderate · up to The counter test can fail intermittently under parallel execution, and the JC build previously failed when its ndarray checkout lacked required APIs. Isolate the counter writes and confirm the dependency provides those APIs before merging. 🚥 Pre-merge checks | ✅ 5✅ Passed checks (5 passed)
✨ Finishing Touches📝 Generate docstrings
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…x duplicate) The entries index reported DUPLICATE ID D-LXC-29: the tenant-rails entry already owns it. The new entry now carries D-LXC-29-R, matching its STATUS_BOARD row. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X1YcYMRSFvfczXoP748wtB
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No fix can be made from inside this PR: the missing symbols live in the other repo. Locally, against the #339 branch, the test passes (2/2), as do contract clippy Next step: merge ndarray#339, then re-run this job.
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Review comments at @crates/jc/tests/register128_bounded_stats.rs:
- Around line 15-18: Update the ndarray dependency revision used by the jc test
workflow to one that exposes the bounded-kernel APIs and both widen_* functions
imported by the test, including BOUNDED_TILE_ROWS; then verify the jc cargo test
workflow compiles against that revision.
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.claude/board/LATEST_STATE.md.claude/board/STATUS_BOARD.md.claude/board/entries/2026-10-04-register128-bounded-power-sums.md.claude/board/entries/README.mdcrates/jc/tests/register128_bounded_stats.rscrates/lance-graph-contract/src/canonical_node.rscrates/lance-graph-contract/src/hotplug.rscrates/lance-graph-contract/src/lib.rscrates/lance-graph-contract/src/register128.rs
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RegisterLanes::set now calls tenant_counter::tenant_update for the rail's tenant after a successful copy, like every other tenant setter; a refused write is not counted. Test under tenant-counters pins the exact delta. (Codex review on #1324.) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X1YcYMRSFvfczXoP748wtB
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Inline comments:
Review comments at @crates/lance-graph-contract/src/register128.rs:
- Line 295: Update the register writes and reads in
hotplug::a_register_takes_its_concept_from_the_context_never_the_payload to use
Register1 instead of Register0, binding RegisterRails::Two and accessing lane 1
throughout. Keep the exact before + 2 assertion in the tenant-counter test
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crates/lance-graph-contract/src/register128.rs
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register_writes_are_counted_per_tenant pins an exact Register0 delta under tenant-counters, but the hotplug identity test also wrote rail 0, so the parallel harness could make the delta flaky. The identity test now binds both rails and writes rail 1; its assertions are unchanged. (CodeRabbit review on #1324.) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X1YcYMRSFvfczXoP748wtB
Board conflicts only: LATEST_STATE keeps both 2026-10-04 sections; the entries index is regenerated. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017PWtMb9jQ4gof5g4y2jzNt
What
This implements the D-LXC-29 operator ruling, alternative 2, with a live first consumer.
Contract
SlabReading::Register128 = 1. Its payload is 128 raw bits with no classid inside. Tags 2, 3, 0x80 and 0xFF still fail closed. Facet96 (tag 0) and its bytes are untouched.ValueTenant::Register0at row bytes[252,268)andValueTenant::Register1at[268,284), 16 bytes each.EpisodicBasin, and onlyValueSchema::Fullincludes them.BoardAggregatesreservation re-bases from ordinal 16 to 18.layout_versionbump:ENVELOPE_LAYOUT_VERSIONis not changed. Appending tenants preserves the layout (same precedent as earlier appends), and a bump would make every existing Facet96 slab fail closed.register128.rs:Register128([u8;16]), read as 4 little-endianu32words;RegisterRails::{One, Two};RegisterLanes:Copy, holds plain numbers only, withget/setper rail.ResolvedReading::bind_register128(rails), called once per population afterActivation::resolve_for_context. It returnsNotRegister128for a Facet96 or undeclared slab, andRegisterRailAbsentfor a schema without the rails.RegisterLanes::concept()), never from the payload.ndarray kernels (AdaWorldAPI/ndarray#339): bounded
u8folds (tile ≤ 65,536), widening to exactPowerSums/CrossPowerSums, and a tiledchecked_mergedriver.Register layouts
[n, Σx, Σx², reserved].[n, Σx, Σx², ·]and rail1 =[Σy, Σy², Σxy, ·], sonis stored once.jc end-to-end test (
crates/jc/tests/register128_bounded_stats.rs)NodeRowrails.The result equals the wide
i32path, univariate and bivariate. A Facet96 slab never binds.No #1323 logical API changed,
TurbovecResidueis not used, and no production crate gained a dependency (jc already has ndarray, and the contract as a dev-dependency).Proofs
register_rails_are_granted_only_to_a_register128_slaba_register_takes_its_concept_from_the_context_never_the_payloadfrom_tagtest, tags 2, 3, 0x80, 0xFFthe_rails_touch_no_other_tenant,writing_a_rail_leaves_every_other_byte_aloneregister_rails_carry_bounded_stats_that_widen_to_the_wide_pathThree Full-schema byte pins were re-pinned from 220 to 252, as intended.
Gates: contract clippy
--all-targets -D warningsis clean; contract tests 1391 + 7 + 12 pass; jc clippy--tests -D warningsis clean; fmt passes.CI note: the jc test needs AdaWorldAPI/ndarray#339 merged first.
Measured (AVX-512 host, release, ns/row)
The bounded path is 1.26–1.32× faster univariate and 1.58–1.71× faster bivariate, across tile sizes 4,096, 16,384 and 65,536 and over a population of 1.05M rows (16 tiles). The full table is in
.claude/board/entries/2026-10-04-register128-bounded-power-sums.md. AVX2 and NEON were not measured.OPEN
RegisterLanes::setonce per group (not per row). They do not write intoNodeRowin place.SlabDeclarationis stored in the metadata envelope, and which writer persists it.🤖 Generated with Claude Code
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