masking-ops: name G8 — the tree-depth column lzcnt(bswap(x)) >> 2; popcount is its tie-break - #317
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…opcount is its tie-break, not its substitute Filed, not built. Three docs, no code. The V3 facet's tail (bytes 8..16, tiers 2-5) is one aligned u64 at a compile-time offset -- a PEEK, so register ops on it are legitimate -- and within a basin HEEL/HIP are shared by construction, so the 6-tier LCP saturates and the information is in that tail. Two consequences: - Padding is useless once you can strip: eight u64 tails tile a zmm exactly, no tail descent. Same fact blackboard (18) found from the population side (the tail optimisation is inert on powers of two). - The op on a tree path is lzcnt, not popcount. Each tier byte is a 4-level 4-ary centroid tree (256 = 4^4), so depth-of-divergence is the metric and popcount is position-blind on it (leaf flip == root flip). popcount serves only the in-cell tie-break. The trap: LE byte order (root tier at the LOW byte) vs MSB-coarse nibble order inside a byte -- neither tzcnt nor lzcnt alone reads the path in one direction; one bswap reconciles them. G8 pre-registers a falsifier that fails a bswap-less implementation on a low-nibble/high-tier divergence. Gate before building: one named consumer call site that ranks by depth (FacetCascade tail ranking, or NiblePath::common_prefix_depth where this lzcnt IS the fold) -- the G5 count rule. - .claude/knowledge/masking-ops-state.md: OUTLOOK G8 (realizations per backend, falsifier, gate) - .claude/board/EPIPHANIES.md: the finding + named gap - .claude/blackboard.md: (19) loose end + the "no popcount variant" call Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01HScwwezRdMxFfTs3WLG19d
📝 WalkthroughWalkthroughThe change adds documentation for the deferred G8 tree-depth primitive. It records the ChangesG8 tree-depth masking
Priority: ⬇️ Low Estimated code review effort: 1 (Trivial) | ~5 minutes Change: Other Suggested reviewers: Merge Risk: 🟡 Moderate · up to The documented primitive could guide a future implementation toward incompatible ranking semantics or backend assumptions. Resolve these specification defects before merging. 🚥 Pre-merge checks | ✅ 5✅ Passed checks (5 passed)
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In @.claude/knowledge/masking-ops-state.md:
- Around line 235-237: Update the G8 realization list to include the nightly
backend from src/simd_nightly, keeping it consistent with the falsifier’s
six-realization requirement; only reduce the count if G8 explicitly excludes
nightly.
- Around line 223-225: Update the planned zmm realization description to require
both AVX-512CD and AVX-512BW for the vpshufb plus vplzcntq sequence, or specify
a byte-reversal alternative supported by the selected target; do not gate it on
AVX-512CD alone. Keep the existing G8-not-built scope unchanged.
- Around line 204-208: Update the V3 and G8 documentation to explicitly state
the coordinate system, operand width, and pair-versus-axis grouping used by the
carving. Align G8 with the V3 contract’s classid(4) | payload(12) layout and
RailSpec::v3_facet’s six sequential u8:u8 levels at offsets 4–16 with stride 2;
describe only the bytes actually used, and clarify how the six levels map to
pairs or axes when accessed as a u64.
- Around line 219-221: Clarify the G8 ranking unit at the depth_nibbles
calculation: either change it to two-bit 4-ary grouping and update the result
range, tie-break mask, and falsifier, or explicitly document the existing nibble
grouping as a coarsened 16-ary metric consistently across the referenced
planning documents.
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A sibling session measured the G8 formula against a fixture and found the
rationale contradicts it by 2x. Confirmed here.
The entry justified `lzcnt(bswap(a ^ b)) >> 2` with "each tier byte is a
4-level 4-ary centroid hierarchy (256 = 4^4)". A 4-ary tree is 2 bits per
level, so that justifies `>> 1` (depth 0..32), not `>> 2` (0..16). The
sentence was self-inconsistent on its own terms too: it said "4-level" and
"high nibble coarse" in the same breath, and a byte has 2 nibbles, not 4
levels.
Both readings are real and both are OGAR canon; they are different trees.
The nibble/16-ary one ("1 hex digit = 1 nibble = 1 level, FAN_OUT=16") is
the PATH reading and is what the shipped shift implements, and it matches
the named consumer (`NiblePath::common_prefix_depth` is in nibbles). The
4^4 one is the Morton-INTERLEAVED centroid space, where a nibble of
`FacetTier::morton()` is a 2bit x 2bit quad-tree level across both axes.
G8 reads the RAW tail, so it is the nibble tree. Ranking is identical
either way (both monotone in leading-equal-bits); the granularity bites
only where depth is consumed as a value, i.e. the `x & below(depth)`
tie-break the same paragraph proposes.
The pre-registered falsifier could not have caught this: both arms compare
the column op against `(a ^ b).swap_bytes().leading_zeros() >> 2`, the same
formula respelled, so they agree even when the shift is wrong. Adds a third
arm that builds the fixture independently, with the depth measured at all
16 positions:
depth = 4*(t-2) + 2*b + k // 0..15; 16 iff tails identical
for tier t in 2..5, byte-in-tier b (0 = lo, lower address), nibble-in-byte
k (0 = MSB). A first draft of that arm wrote `2*(t-2) + n`, correct only for
tier 2; running the model caught it, which is the arm's whole purpose.
Records one thing the measurement surfaced. `FacetTier` is `{ lo, hi }` with
`lo` at the lower address, so after the bswap a single lzcnt walks lo before
hi within every tier, alternating between the two chains every two nibbles.
But hi_chain and lo_chain are documented as ORTHOGONAL hierarchies, not
coarse and fine of one. So raw-tail depth is a mixed-axis metric: a valid
monotone tie-breaker, not a depth in either hierarchy. Whether that is what
the basin-local-similarity consumer wants is now part of the gate instead of
an assumption.
Docs only. Still named, not built.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01HScwwezRdMxFfTs3WLG19d
…ckend Five review findings on #317, each verified in the tree before fixing, plus two facts the verification turned up that change the gate. - "each tier byte" was wrong about the unit. `RailSpec::v3_facet` (src/hpc/clam_v3.rs) walks six sequential (u8:u8) levels at key offsets 4..16 with stride 2, so a tier is TWO bytes, one per axis. The u64 operand at 8..16 is 4 tiers x 2 bytes = 8 bytes = 16 nibbles. States the carving, operand width and pair-versus-axis grouping up front, as both reviewers asked. - vpshufb at zmm width needs AVX-512BW, not AVX-512CD. The entry gated the whole sequence on CD alone. Now names both bits and says a CD-without-BW target needs a different byte reversal. - "no padding and no tail descent" was a claim about the OPERAND stated as though it covered the population. Eight u64 tails tile a zmm, but a row count not divisible by eight still leaves a column remainder, as the slice-level U64x8 ops handle with pad_tail. No multiple-of-eight input contract is stated or intended; an implementation keeps a remainder path and tests non-multiple-of-eight lengths. - The falsifier said six realizations while the list named five. The sixth is the nightly core::simd arm (src/simd_nightly/), now named. - MD040: the depth fence had no language. Two findings from reading clam_v3.rs that the reviews did not reach, and that matter more than any of the above: - RailSpec carries TWO carvings and its doc records a measurement between them. The interleaved X:Y pair reading (v3_facet, 6 levels, stride 2) fits only 44.25% of paths on the medcare bake; the contiguous per-axis slab (RailSpec::slab, 12 levels, stride 1) fits 99.62% in twelve levels. That inverts G8's gate: on the slab carving a contiguous u64 IS one axis, the mixed-axis caveat evaporates, and a plain lzcnt(bswap) is exactly right; on the pair carving it is only a mixed-axis tiebreaker. So the consumer gate must name the CARVING as well as the call site, and the measured split says the slab is the likelier target. Do not build against the pair reading because it happens to be the zero-fallback default. - Levels grow by STACKING, not widening: a class needing more than six levels chains a second register, explicitly contemplated as the edge lane at 16..32, running depth 0..=12 over two registers. So a G8 column op over a stacked pair is two chained operands, never one wider one, which is also why no u128 variant is proposed. Docs only. Still named, not built. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01HScwwezRdMxFfTs3WLG19d
Filed, not built — three docs, no code
Names G8 in
masking-ops-state.md§ OUTLOOK: a tree-depth column op,lzcnt(bswap(a ^ b)) >> 2, for the V3 facet's tail. Records the finding inEPIPHANIES.mdand the loose end inblackboard.md(19).Why
The V3 facet's tail is one aligned
u64at a compile-time offset — a PEEK, not a gather — so register ops on it are legitimate under lance-graph's carrier doctrine (E-THREE-CARRIERS-THREE-FOLDS-1). Within a basin HEEL/HIP are shared by construction, so the 6-tier LCP saturates and the information is in that tail.State the carving before the op, because "tier" and "byte" are not the same unit. The facet is
classid(4) | payload(12), andRailSpec::v3_facet(src/hpc/clam_v3.rs) walks six sequential(u8:u8)levels at offsets4..16, stride 2. A tier is TWO bytes, one per axis. Theu64at8..16covers tiers 2–5, i.e. 4 tiers × 2 bytes = 8 bytes = 16 nibbles.no tail descentper 8-row group. Eightu64tails tile a zmm exactly, which removes the within-operand padding a narrower width would need. It says nothing about the population: a row count not divisible by 8 still leaves a remainder, as the slice-levelU64x8ops handle withpad_tail. No multiple-of-eight input contract is stated or intended.lzcnt, notpopcount. Depth-of-divergence is the metric; popcount is position-blind on it (a leaf flip counts the same as a root flip — "popcount also finds elephant : Wal"). Popcount serves only the in-cell tie-break.Which factorization of 256, stated because the canon carries two
Each tier byte is a 4-level 4-ary centroid tree (256 = 4⁴).Struck — that justifies>> 1, not the>> 2that ships. A 4-ary tree spends two bits per level.G8 commits to the 16-ary nibble reading ("1 hex digit = 1 nibble = 1 level,
FAN_OUT=16"), which is what the shift implements and what the named consumer uses, sinceNiblePath::common_prefix_depthis in nibbles. The4⁴reading is the Morton-interleaved centroid space, a different tree over a different operand. Ranking is identical either way (both monotone in leading-equal-bits); the granularity bites only where depth is consumed as a value, i.e. thex & below(depth)tie-break.The byte-order wrinkle, and the axis caveat
LE byte order puts the root tier at the low byte; nibble order inside a byte is MSB-coarse. One
bswapreconciles them.But
FacetTieris{ lo, hi }withloat the lower address, so a singlelzcntover the bswapped tail walkslobeforehiwithin every tier, alternating between two documented-orthogonal chains every two nibbles. Raw-tail depth is therefore a mixed-axis metric: a valid monotone tiebreaker, not a depth in either hierarchy.And
clam_v3.rsrecords which carving the real bake wants — it is not the pair reading.RailSpeccarries two, with a measurement between them: the interleavedX:Ypair reading fits "only 44.25 % of paths" on the medcare bake, while the contiguous per-axis slab (RailSpec::slab, 12 levels, stride 1) fits "99.62 % in twelve levels". On the slab a contiguousu64is one axis and the caveat evaporates. So the gate must name the carving, and the measured split says the slab is the likelier target.Levels grow by stacking, not widening: a class needing more than six chains a second register, with the edge lane at
16..32explicitly contemplated as that continuation, depth 0..=12 over two operands. Hence nou128variant.Falsifier
Three arms. The column op must equal the scalar
(a ^ b).swap_bytes().leading_zeros() >> 2on every row at all six realizations; a disable-run without thebswapmust fail on a fixture whose divergence sits in a low nibble of a high tier; and a third arm builds the fixture independently, because the first two compare the op against the same formula respelled and therefore cannot catch a wrong shift. Measured at all 16 positions:for tier
t∈ 2..5, byte-in-tierb(0 =lo), nibble-in-bytek(0 = MSB). A first draft of that arm wrote2*(t-2) + n, correct only for tier 2; running the model caught it, which is the arm's purpose.Realizations (named, not built) — six
vpshufb(byte reverse) needs AVX-512BW at zmm width andvplzcntqneeds AVX-512CD, so both feature bits, not CD alone. avx2 has no vector lzcnt (float-exponent trick or scalar peel — measure). NEONclzon 32-bit halves plus select. wasm and scalar flat. And the nightlycore::simdarm (src/simd_nightly/) — six, matching the falsifier's count.(The original listed five while the falsifier said six.)Gate
The G5 count rule: one named consumer call site that ranks by depth, and now the carving it uses. Candidates: lance-graph
FacetCascadetail ranking, orNiblePath::common_prefix_depth(ISS-NIBLEPATH-FOLD-IS-CARRIER-2-UNMASKED).No
popcountvariant —popcount_batch_u64already serves the tie-break. The gap islzcnt(+bswap).🤖 Generated with Claude Code
https://claude.ai/code/session_01HScwwezRdMxFfTs3WLG19d