WDL compiler does not render "SET" commands for bias channels, and fails silently without any warning

[weatherhead99]

It was mentioned to me by @tgreffe that it is possible in the UVEX wdl files to use commands to set bias lines as well as clock lines and that this was implemented at some point by @astronomerdave. Indeed this is supported by "recent" (post ~2018) Archon firmwares.

However, it seems in the upstream (i.e. current main) version of wdl, that these commands are not rendered, the state that comes out appears to be a nop.

There is no warning emitted from WDL about the lines in question, the resulting state simply does not contain the appropriate directives.

On a quick search I was not able to find the commit which implemented this functionality.

[weatherhead99]

updated information - it appears that it actually DOES render the command if you use a single channel (i.e. SET 7:1 to 14.0 or similar). But NOT if you use the wdl supported multi-channel notation (i.e. SET [7:1 7:2] to 14.0). Then nothing is emitted and there is no warning

[scizen9]

In the wset function in wdlParser.py, it looks like all you have to do is separate the slot:channel list items with a comma and it should work, no?

` if found("["):
consume("[")

while not found(","):
    if token.type == EOF:
        break
    # SLOT
    if found(NUMBER):
        setSlot.append(token.cargo)
    consume(NUMBER)
    consume(":")
    # CHANNEL
    if found(NUMBER):
        setChan.append(token.cargo)
    consume(NUMBER)

    # There can be a list of SLOT:CHAN, SLOT:CHAN within the [brackets]
    # so consume the comma and continue, if there is one,
    if found(","):
        consume(",")
    # otherwise get out of the loop if there is no list.
    else:
        break

if found("]"):
    consume("]")`

[weatherhead99]

hmmm, I will try this when I can....
if so, in that case my real complaint is more likely that this fails silently and generates a non-working configuration with no obvious way of telling that

[weatherhead99]

nope, confirmed sorry. See https://github.com/CaltechOpticalObservatories/wdlfiles/tree/deimos_debug2 (src/deimos/deimois.signals line 86). We did a #define VRD [ VRD_E, VRD_F]. If you use SET VRD TO 14.0; somewhere in a waveform it generates an empty state with no warning presently. However doing SET VRD_E TO 14.0 does work.

[scizen9]

OK, with example inputs I can start to debug this.

[scizen9]

Is there any rule that says you can't SET the same module twice? When I manually put in the waveform file:

SET VRD_F TO 17.0;
SET VRD_E TO 17.0;

it also produced the empty state. This was in the Waveform OutputTestSetup. However when I changed VRD_E in the signals file:

#define VRD_E 10 : 5

and then used

SET VRD TO 17.0;

It did NOT produce an empty state. This presumably used the define in the signals file:

#define VRD [VRD_E, VRD_F]

It produced these two state lines in the acf file:

STATE23\MOD9="1,6,17"
STATE23\MOD10="1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,5,17"

I don't know enough about these acf files to know if this is correct behaviour. It looks to me like the problem is setting the same module twice, not the list of module:channels.

[weatherhead99]

ah yes well spotted!

Indeed you can only issue one bias setting command per timing state I believe ...

in that case this should be raised as an error, somehow