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[Feature] PCI Express Link information granularity design concept #7

Description

@kernel-dev

Purpose: figure out best design principle for modeling this:

  • Encapsulation within a separate entity (i.e. PCIeLinkInfo); or
  • Separate fields
  • Or maybe a 3rd option?

For PCIe devices, the Link-related information is divided into 2 categories: negotiated and capable.

Note: the PCIe link data of interest to us is speed (generation) and width (the amount of PCIe lanes the device uses)

Meaning, if there are certain hardware limitations (i.e. motherboard doesn't support the capable PCIe speed) or the Active Power Management State is negotiating a potentially lower link speed if the system or device is supposed to be in “Low Power Consumption Mode”. This then becomes the negotiated PCIe link speed.

Windows

On Windows, this data can be obtained by using cfgmgr32 and the appropriate DEVNODE query, see: https://github.com/tpn/winsdk-10/blob/9b69fd26ac0c7d0b83d378dba01080e93349c2ed/Include/10.0.16299.0/shared/pciprop.h#L196

PIDs of interest: [9, 12]

MacOS

On MacOS, the IOKit library exposes properties for the IOPCIDevice instance:

  • IOPCIExpressLinkCapabilities (the capable); and
  • IOPCIExpressLinkStatus (the negotiated)

Both of these properties contain the encoding of both link speed and width.
The way to decode them is as follows:

speed = capability & 0xF
width = (capability >> 0x4) & 0x3F
IOPCIExpressLinkStatus IOPCIExpressLinkCapabilities

Decoding1

Linux

On Linux, the data is readily available via sysfs: you traverse up the device tree of the desired PCI device, and the data files are:

  • current_link_speed - negotiated
  • current_link_width - negotiated
  • max_link_speed - capable
  • max_link_width - capable

Footnotes

  1. This data was tested on a MacBookPro15,1 with an AMD Radeon Pro 550X (PCIe 3.0, x8) ↩

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