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Signed-off-by: Yuxian Qiu <142763828+yuxianq@users.noreply.github.com>
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@coderabbitai summary
Description
Refresh PrimTS from
yuxianq/flashinfer:trtllm-prims-ts-dev-20261012ataa709061230a58858375c513056e7733fa74294atoyuxianq/flashinfer:trtllm-prims-ts-dev-20261030atd1bed93d69d172fd8f9af96cf14f4f869ac488ef, an audited FlashInfer main commit. The new source branch points directly to that upstream commit, with zero downstream source commits.This PR contains the upstream refresh and the compatibility adaptations required by existing TRT-LLM consumers. The cache, prepared-launch validation, and paged-helper refactor in TRT-LLM #21337 / FlashInfer #8005 is deferred to a separate follow-up. The source cherry-pick
ec4814663c738291c7513f995fcefe4554a890cbis excluded.Downstream audit
All upstream merge commits below are ancestors of the selected main snapshot. Five downstream commits match the complete changed text and file/mode changes of their upstream counterparts, including tests, docs and external helpers. The three TMA commits were audited as a series; their combined selected source and separately added regression tests exactly match the merged fix. The existing
retain-until-verifiedrecord forae3851ab5was resolved using this comparison and inspection of the surviving physical-SM gate, real-Q prefix guard and descriptor correction.0e0761ef5ef10cb0762cc1b890a5c1a329bb49bf— SM103 block-sparse/Sage tuning388e7a311e9f79941134dcc298cbc942b5c607a19ac6f623e72e669b3735db4a880eae1c4176c402— SM107 testing and FP8/NVFP4 conversion2355145edf0c0b76548e0d080f82ac0b3e6fdab53109f31cd262cdeda79ed3979d84cccf4168012b— QToken sparse optimization69071c0e3747b760a9c159dbd2bb2c8e1416b6a96b00497398f491136be91fb0e60ac3f314da53ba+ae3851ab5f958ba22f154059df5b38321f6369d2+15209afee817320d4640018be99867990fbf96a6— ragged-Q correction and tail testsf57c58b898cc0f96ddea03066a3fd66ad201337a583810d32664bf3f461a6fb61714e0ec554ba846— compile cache and FP8/BF16 decode12199dba2ffdfe00c8e9b624df31c634eabee0f4aa709061230a58858375c513056e7733fa74294a— native two-source sparse MLAe67e925f6590a128d8f0cc2aee273990e58abda5The old canonical branch and historical promotion records are retained.
Consumer compatibility
scripts/vendor/manage.py._compile_cache.pyis byte-for-byte unchanged from the TRT-LLM base. The manual MLA compilation memo, original cached sparse-plan resolver, prepared-launch cache keys and output check remain in place.kv_cache_scalecontinue through upstream handling.functools.cachecompiler decorators.cuda_scalescompile mode and loads FP32 scale values on device. Graph tests update the same scale buffers and cover QK-only, V-only and combined overrides.The compatibility patch must still be regenerated: upstream changed the APIs, prepared-launch ABI, and scale representation against which the existing adaptations apply. Its changes preserve that behavior on the new baseline. The general cache decorator, expanded prepared cache keys, stricter validation, and paged-helper cleanup from #21337 are deferred.
FlashInfer
0.6.18, CuTe DSL4.8.0, public LLM/VisualGen configuration, FMHA selection gates, and unrelated vendors stay unchanged. Newly imported source capabilities are not automatically admitted by TRT-LLM adapters. The optional QToken metadata JIT generator remains unavailable in FlashInfer 0.6.18, as on the old snapshot; dependency migration is tracked separately by #20911, and DSL 4.9 compatibility by #21151.Test Coverage
The narrowed revision is validated on B200/SM100 with Python 3.12, PyTorch
2.14.0a0+b2c75dd062.nv26.09, FlashInfer0.6.18, and CuTe DSL4.8.0. Native binaries come from CIL0_MergeRequest_PR/67365at45260fcd233e69cb7c057fcb9fd900ab5a8aa247; its complete C++ tree, requirements and Git submodule pins match this PR's base. Tests import this worktree's Python implementation.Runtime validation of this revision is limited to these B200 component tests. Full-model, B300 and Rubin/SM107 qualification remain pending, along with normal CI and required approvals.
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