docs: bus manager design - #14
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Design for the single bus manager that replaces the FIFO queue and the per-component polls: lanes and their ordering rule, subscriptions merged into spans, coalesced writes, dirty spans instead of read-after-write, adaptive rates from measured latency, failure behaviour, a three-PR migration and the test list.
https://claude.ai/code/session_015YgEehU5GLftenbuhpKWMi