sycl: TernSYCL XMX path, decode attention and fusions for Bonsai 2 27B on Intel Arc (port of Torchit1/arc-b580) by bri-prism · Pull Request #356 · PrismML-Eng/llama.cpp

bri-prism · 2026-10-13T21:14:08Z

What

Ports Jesse Symons' SYCL work for Bonsai 2 27B on Intel Arc from Torchit1/llama.cpp arc-b580 (v0.10.1) onto prism. 39 of the 41 commits are his, cherry-picked with authorship kept; each one ends with the source commit it came from and, where only part of it was taken, which paths were left out. The last three commits are ours: two fix the merge, one sets Xe3 defaults.

Main pieces, all in ggml/src/ggml-sycl:

TernSYCL XMX path for PTQ1_0 and PQ2_0 weights (ptq1-t2.cpp), using the int2 x int8 DPAS kernels from libxsmm/TernSYCL, vendored under ternsycl/ with its BSD-3-Clause license and notice. Opt-in: GGML_SYCL_PTQ1_T2=all (or ffn).
Per-token rotate + quantize cache for the Hadamard input, with the residual add + RMS norm, SwiGLU and DeltaNet pre-norm folded into it, and same-input mat-vecs in one launch.
XMX decode attention straight from a q4_0 KV cache (fattn-dec.cpp), up to 256 query tokens. GGML_SYCL_FA_DEC_DPAS=1; default on for Xe3 only.
Blocked gated delta net, fused DeltaNet conv chain and gate block, fused gate/up, two-pass top-k, MKL flash-attention softmax per row, oneDNN int8 GEMM for large prompt batches.
test-backend-ops cases for the fusions (ARCLAB_*) and the Bonsai verify shapes.

Our three commits:

sycl: one in-place layout owner for PQ2_0/PTQ1_0 weights. The port's MMVQ reorder and the PQ2_0 XMX rewrite from sycl: XMX path for PQ2_0 and PTQ1_0 on 16-wide DPAS devices #294 both rewrite these weights in place and did not check each other. With GGML_SYCL_PTQ1_T2 unset a weight could get both layouts (27B PTQ1_0 perplexity 139615 on an Arc B390 while every op test passed). On 16-wide DPAS devices the XMX layout now owns these types.
sycl: drop PQ2_0/PTQ1_0 duplicates left by the arc-b580 merge. Both sides had added PQ2_0/PTQ1_0 support (sycl: add PTQ1_0 and PQ2_0 support with MMVQ vector dot kernel #235, sycl: XMX path for PQ2_0 and PTQ1_0 on 16-wide DPAS devices #294 here; the bundle commit there), so the merged tree did not compile. Deletions only.
sycl: Xe3 defaults to the MMVQ reorder for PQ2_0/PTQ1_0 and to XMX decode attention. On the B390 with GGML_SYCL_PTQ1_T2 unset, the reorder layout is +16% decode, +6% prompt and about 0.9 GB less memory than the XMX layout, at a higher but still small KLD (6.7e-4 vs 2.4e-4); the XMX decode attention adds 4-6% decode at 16K with KLD within run-to-run error and FLASH_ATTN_EXT head size 256 264/264. Verified on the commit with no env vars set: the reorder and DPAS kernels are the ones created, MUL_MAT 1445/1445, FLASH_ATTN_EXT head size 256 372/372, pp512 / tg128 / tg128 at 16K 353 / 15.8-16.1 / 14.8 t/s, and KLD vs prism identical to forcing the same env vars on the parent. GGML_SYCL_DISABLE_XMX=0 and GGML_SYCL_FA_DEC_DPAS=0 restore the old behaviour; other devices are unchanged.

Why

On an Arc B390 (Panther Lake, Xe3) this is 1.2x decode, 1.6x prompt and 2x decode at 16K context against current prism for Bonsai 2 27B, with the same memory use.

Defaults that change for SYCL users

Off by default: the TernSYCL path, and the XMX decode attention except on Xe3. On Xe3, PQ2_0/PTQ1_0 also default to the MMVQ reorder layout instead of the XMX layout from #294. On by default, as in the source branch: the fusions above, the oneDNN int8/s4 prompt GEMM for PQ2_0/PTQ1_0, and the legacy Level Zero adapter (SYCL_UR_USE_LEVEL_ZERO_V2=1 keeps V2). The B580 tile table only applies on a B580. Every new path has an off switch, listed in the source branch's doc.

Testing (Arc B390, Windows 11, driver 32.0.101.8860, oneAPI 2025.3.2)

Build: SYCL Release, JIT.
test-backend-ops: MUL_MAT 1445/1445 and all ARCLAB_* cases pass with GGML_SYCL_PTQ1_T2 unset and =all; FLASH_ATTN_EXT at head size 256 264/264 (head size 192 aborts in fattn-tile.cpp on prism too, separate issue).
KLD vs prism, 27B PTQ1_0, wikitext 16 x 512: GGML_SYCL_PTQ1_T2=all mean 0.000219, same top token 99.31%, PPL ratio 1.0004. GGML_SYCL_PTQ1_T2 unset: mean 0.000243, same top token 99.39%, PPL ratio 0.9997 (before the layout-owner fix this case was PPL 139615). Measured on the same commits before the rebase onto current prism; the rebase adds only prism's three newer commits (cuda: ptq1 sm86 rows1 #340, grammar: allow schema property order #347, cuda: keep quantized K/V type in the short-query MMA FA path #355) and a one-line format change.
llama-bench, 27B, -fa 1 -ctk q4_0 -ctv q4_0, GGML_SYCL_PTQ1_T2=all, mean of 2 alternated rounds (t/s):

	prism	this PR	source branch
pp512 PTQ1_0	304	496	492
tg128 PTQ1_0	12.2	14.7	14.6
tg128 @ 16K PTQ1_0	6.8	13.3	13.3
pp512 PQ2_0	307	497	494
tg128 PQ2_0	12.3	14.7	14.7

On this Xe3 part TernSYCL helps prompt (+37%) but costs about 9% decode against the source branch's own non-TernSYCL path, so a batch-size gate for it is a follow-up.

Not covered: Vulkan (not in this PR), Linux, Arc B-series discrete, Lunar Lake.

Credit

Jesse Symons (@Torchit1) for the port and the kernels around it. Evangelos Georganas, Alexander Heinecke and the libxsmm team for TernSYCL. The source branch started from Cary Palmer's bonsai-combo work (#221).

- SYCL: PTQ1_0 weights repacked to 2-bit at load and multiplied on XMX via the TernSYCL int8 x int2 DPAS kernels (vendored, BSD 3-Clause), activations quantized to int8 with round-to-nearest (GGML_SYCL_PTQ1_T2=ffn|all). - SYCL: decode attention for q4_0 KV serving 1-4 query tokens per launch; blocked gated delta-net; PTQ1_0 mat-vec kernels (single column, decode-once multi column, same-input merge, fused gate/up); narrow concat. - Vulkan: matching PTQ1_0 multi-column, decode attention, gated delta-net and coopmat work. - Speculative decoding: draft KV cache type (-ctkd/-ctvd) honoured by the MTP draft context, LLAMA_ARG_SPEC_DRAFT_UBATCH to shrink its compute buffer. - docs/bonsai-arc-b580.md: results at 128K on a B580, build and run instructions, switches, credits. Based on the bonsai-combo branch of professorpalmer/llama.cpp-ada-ternary (PrismML PR #221). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 753323e on Torchit1/llama.cpp arc-b580) Excluded from this port: .github docs ggml/src/ggml-vulkan Conflicts resolved against prism: fwht.cpp keeps prism's FWHT (#302) and adds this commit's signed variant beside it as ggml_sycl_op_fwht_signed; ggml_sycl_op_mul_mat_sycl takes fp16 for PQ2_0/PTQ1_0 as before (#278) plus this commit's large-batch rule; the T2 path runs before the PQ2_0 XMX path (#294), which still serves PQ2_0/PTQ1_0 when GGML_SYCL_PTQ1_T2 is unset.

PQ2_0 (2-bit codes 00=-1 01=0 10=+1, fp16 scale per 128) is the same size as the 2-bit XMX layout, so it is remapped in place. Code 3 (+2) has no 2-bit two's-complement form: the repack reports it and the matmul aborts with a message. test-backend-ops MUL_MAT type_a=pq2_0 with GGML_SYCL_PTQ1_T2=all: 84/84; ptq1 94/94. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 5056bde on Torchit1/llama.cpp arc-b580)

The T2 kernels use 16-lane int8 x int2 DPAS builtins that only Xe2 and newer drivers provide; on an Arc 140T (Xe-LPG+) GGML_SYCL_PTQ1_T2=all failed with 'No kernel named ... was found'. Now checked once against the device architecture. GGML_SYCL_PTQ1_T2_ANYGPU=1 skips the check. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 731c1a8 on Torchit1/llama.cpp arc-b580)

The 2D block I/O builtins took the surface base as 'long', which is 32 bits in SYCL device code on Windows (the device follows the host's LLP64 data model), so the weight loads would have used truncated addresses. 'long long' is 64 bits on both; identical code on Linux. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 2f0cf6e on Torchit1/llama.cpp arc-b580)

…default stays best) B580 pp1024 (ub 1024, all weights on XMX): 8x128/8x2 939 t/s (default), 8x128/16x1 949, others 480-857. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 244c4d4 on Torchit1/llama.cpp arc-b580)

… one-group kernel) The one-work-group top-k took ~550 us per MTP draft token on the B580 (248K-entry vocabulary). Now up to 256 groups per row with a pairwise local-memory merge, then one group merges the winners; ties keep the lower index. test-backend-ops TOP_K 325/325. 200K entries: k=1 241 -> 9.6 us, k=10 647 -> 71 us. Live settings: fresh +1-2%, rename/edit within noise (the speculative step is not purely GPU-bound). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit afe4c82 on Torchit1/llama.cpp arc-b580)

…_FA_DEC_DPAS) Q.K uses intel_sub_group_i8_i4_matrix_mad_k32 (IGC provides it on Xe2 though the public extension only lists i4_i4_k64): the raw 16-byte q4_0 block of a key XOR 0x88888888 is the B operand, one key per lane, against int8 Q with one RNE scale per row and block (q4_0 byte order absorbed by pairing dims l and l+16 in A). P.V computes O^T = V^T P^T on f16 DPAS so each lane dequantizes its own key's V block from 5 dword loads. Token chunks of 8 let one kernel serve 1..32 (or =N) query tokens, so n-gram verify batches stop falling back to oneDNN + a full-KV f16 conversion. Per layer (Bonsai 27B shape, real cache layout) old -> new, us: 16K 1 tok 266 -> 123, 4 tok 457 -> 244, 16 tok 2217 -> 776; 48K 1 tok 768 -> 433, 4 tok 1295 -> 671, 16 tok 6629 -> 1915. FLASH_ATTN_EXT decode cases incl. 12/16/17/32 tokens and the permuted layout: 57/57. GGML_SYCL_FA_DEC_DPAS_PROBE skips phases. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit e5a4d8a on Torchit1/llama.cpp arc-b580)

mkl_fa_online_softmax_chunk gave each query row to one work-item that walked the whole KV chunk twice, so neighbouring work-items read addresses chunk_size floats apart. Above the oneDNN KV cap this kernel was 72% of generation time (Bonsai 27B, 115K-token context: verify batches > 32 tokens and every new prompt). Now 256 work-items per row with coalesced reads and group reductions; same math. Bonsai 27B, live flags, 114.6K-token code context: new code 17.6 -> 44.0 t/s, edit 10.8 -> 27.5 t/s, identical output; short prompts unchanged. FLASH_ATTN_EXT with the MKL path forced (ONEDNN_MAX_KV=512): 82/84, the same two pre-existing prompt-batch failures as before. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit a122b2b on Torchit1/llama.cpp arc-b580)

Quantized mul_mat with 33+ columns fell through to dequantize-all-of-src0 + GEMM per call. For speculative-verify sized batches that is ruinous: Gemma 4 12B q4_0 with n-gram drafts of 33-64 tokens spent ~94% of GPU time in dequantize_row_q4_0_sycl_reorder. Default stays 4 x MMVQ_MAX_BATCH_SIZE (32); with 128, Gemma 4 12B + QAT assistant (ngram n-max 64): rename 79 -> 186 t/s, edit 57 -> 136. Bonsai 27B unchanged within noise. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit e8bd534 on Torchit1/llama.cpp arc-b580)

Reported from an Arc 140T and reproduced on a B580: FLASH_ATTN_EXT with quantized K/V in the permuted layout returned ERR ~1.2 for every KV length from 1024 up (ggml-org#27769). The failing test builds the cache view with a gap between tokens (2x the heads allocated, half viewed); the oneDNN SDPA and MKL dequant paths take the token stride from the head count. llama.cpp's own cache view is always packed, so real models were unaffected (Bonsai 27B perplexity at 4K: oneDNN 8.7273, MKL 8.7311, TILE 8.7330, and still 8.7273 with this guard). Interleaved K/V with a gap now falls back to TILE. FLASH_ATTN_EXT 4137/4137 (was 2 failing), plus a new q4_0 real-layout sweep (kv 1024..8192, nb 33/64/512) 29/29. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 226166a on Torchit1/llama.cpp arc-b580)

…ewhere GGML_SYCL_FA_DEC_DPAS uses the 16-lane int8 x int4 DPAS builtin that only Xe2 and newer provide; on Alchemist / Xe-LPG it would fail at the first launch (like the T2 path did before 9c25b48). Now checked once against the device architecture, sharing ggml_sycl_device_is_xe2() with the T2 gate; GGML_SYCL_FA_DEC_DPAS_ANYGPU=1 skips the check. B580 unchanged: 4-token verify at 48K 671 us (1295 without). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit d441076 on Torchit1/llama.cpp arc-b580)

…, head 256 x GQA 2 sliding) The s8 x s4 DPAS decode kernel takes the head size as a template parameter (K read block by block, P.V subgroups own D/16 dims) and serves two more shapes when GGML_SYCL_FA_DEC_DPAS is on: Gemma 4's global layers (512, 1 KV x 16 Q heads, token chunks of 2) and sliding layers (256, 2 per KV head, chunks of 8). Splits target ~256 work-groups in all (a single KV head used to leave the GPU idle); combine step templated on D. Global-layer attention at 48K, us: 1 token 1114 (f16 TILE) -> 236, 4 tokens 2011 -> 635. Gemma 4 12B QAT + assistant, q4_0 KV, 128K context: short 92 -> 100 t/s new code; at 48K new code 47 -> 65, edit 44 -> 57 (f16 KV was 55 / 47). Bonsai shape unchanged (4-token verify at 48K 638 us). FLASH_ATTN_EXT: Gemma global 20/20, sliding 10/10, Bonsai 36/36. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit c759ddb on Torchit1/llama.cpp arc-b580)

… GGML_SYCL_Q4_0_DPAS) Verify batches of 5..256 columns on q4_0 weights used MMVQ column chunks (weights re-read per 8 columns) or dequantize-everything + GEMM. The new kernel streams each weight row once for up to 64 columns (chunks of 64 beyond): one lane per weight row, B = the row's 16 q4_0 bytes XOR 0x88888888 through intel_sub_group_i8_i4_matrix_mad_k32, A = activations quantized once per call to int8 (per row and 32-block, elements l / l+16 paired). Xe2 only (ggml_sycl_device_is_xe2). GGML_SYCL_Q4_0_DPAS_MIN / _MAX (5 / 256). 15360x3840 q4_0: 8 columns 150 -> 81 us, 16 columns 292 -> 89 us. Gemma 4 12B QAT + assistant: rename 188 -> 275 t/s, edit 138 -> 168 (ngram n-max 96), new code unchanged, rename/edit outputs byte-identical. MUL_MAT q4_0 Gemma shapes 1..256 columns: 20/20. Also Gemma 4 q4_0 mat-mul perf cases. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 03594d5 on Torchit1/llama.cpp arc-b580)

…2_W8A8_MIN) Before the TernSYCL path went live, PTQ1_0 prompts ran on the W8A8 oneDNN GEMM (pp512 1013); GemmMT is better for verify-sized batches but slower on full prompt batches. New ggml_sycl_w8a8_mul_mat_t2 converts the repacked 2-bit layout to int8 (per-row scale, group ratios) and uses the same gemm_s8. The conversion is a fixed cost per call, so it only pays from ~1024 columns: Bonsai 27B pp1024 (ub 1024) 941 -> 1062, pp512 901 -> 818 (so MIN=1024 on the live config); 48.6K-token prompt read 67.7 -> 61.6 s (719 -> 789 t/s). PPL c4096 8.7273 -> 8.7359 (+0.1%, int8 rounding as the old W8A8 path). Off by default (0). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit a68382d on Torchit1/llama.cpp arc-b580)

…ve split count; PTQ1_0 T2 NSG knob fattn-dec (DPAS q4_0 path, D 256): single-token decode copies each 128-key K and V tile into SLM with overlapped 16-byte loads and reads lane = key from there; the split count now fills one wave of work-groups (Xe cores x work-groups per core / KV heads) instead of a fixed 64 per head. B580: 48K 1 token 433 -> 244 us, 4 tokens 640 -> 456 us; whole model plain decode +12% at 48K, +21% at 115K, same KLD and output. GGML_SYCL_FA_DEC_STAGE=0 and GGML_SYCL_FA_DEC_SPLITS=64 restore the old behaviour. ptq1-t2: GGML_SYCL_PTQ1_T2_NSG=4 (4 sub-groups for 2-8 row GEMV, +~1%, default off). Co-Authored-By: Claude <noreply@anthropic.com> (cherry picked from commit 9cfffcb on Torchit1/llama.cpp arc-b580)

…4_matrix_mad_k32 builtin The builtin is not in the public subgroup matrix extension list. On a Lunar Lake (Arc 140V) driver that does not provide it, loading the device image failed with "No device image found for external symbol _Z36intel_sub_group_i8_i4_matrix_mad_k32" and every model crashed at the first decode. xe2-dpas.hpp emits the dpas.s4.s8 instruction directly (as libxsmm/TernSYCL's xe2.hpp helpers), so the symbol is gone from libggml-sycl. Used by the q4_0 decode attention and the q4_0 small-batch GEMM. B580: FA 4167/4167, MUL_MAT q4_0 (GGML_SYCL_Q4_0_DPAS=1) 59/59; whole model output byte-identical to the builtin at short / 48K / 115K context, plain and MTP. Single-token attention kernel ~6% slower (48K 244 -> 259 us), whole model within 1-2%. Co-Authored-By: Claude <noreply@anthropic.com> (cherry picked from commit f31a4f6 on Torchit1/llama.cpp arc-b580)

… code split per kernel - ternsycl/: libxsmm/TernSYCL main (11484da) + the long long address fix of TernSYCL#3. Inline vISA only, so the undocumented builtins the old copy declared (intel_sub_group_i8_i2_matrix_mad_k32, __builtin_IB_* 2D block I/O) are gone; it also drops our three JIT workarounds. The per-32 activation scale variant (off by default) is removed. - ptq1-t2.cpp is compiled with -fp-model=precise: under icpx's default fast model the TernSYCL GemmMT returns NaN (upstream's own driver fails validation built that way). - fattn-dec: the f16 P.V DPAS also goes through inline vISA (xe2-dpas.hpp dpas_hf_r8). - CMake: -fsycl-device-code-split=per_kernel (GGML_SYCL_DEVICE_CODE_SPLIT_PER_KERNEL, default ON): the Xe2 XMX kernels are only JIT-compiled when launched, so GPUs without DPAS (Xe-LP, Gen9) don't compile them at all. - test-backend-ops: FA cases for 64-256 query tokens and ~115K history. B580: libggml-sycl has 0 matrix_mad / __builtin_IB references (was f16, i8_i2, 9 IB). FA 4167/4167, MUL_MAT q4_0 59/59, ptq1_0 T2 94/94. KLD (ub 1 / 4 / 512) identical to the previous build. Whole model output identical; MTP 48K 73.6 t/s, 115K 59.6 (was 69.6 / 57.2), plain unchanged. Startup unchanged (first request 4 s). Co-Authored-By: Claude <noreply@anthropic.com> (cherry picked from commit 2e8a0e6 on Torchit1/llama.cpp arc-b580)

Long n-gram verify batches now stay on the q4_0 DPAS kernel instead of oneDNN's path, which converts the whole KV cache to f16 each call. B580 per layer: 48K 64 tokens 28.8 -> 4.9 ms, 115K 256 tokens 253 -> 44 ms. KLD (ub 64-256) 0.012699 vs 0.012800, same top p 92.60 vs 92.89 %, equal within error. Whole model MTP: 48K 73.2 -> 76.1 t/s, 115K 60.3 -> 65.1. GGML_SYCL_FA_DEC_DPAS=32 restores the old cap. Co-Authored-By: Claude <noreply@anthropic.com> (cherry picked from commit 064461a on Torchit1/llama.cpp arc-b580)

MTP with 4 drafts verifies 5 tokens per step, which ran the 8-token DPAS kernel with 3 empty tokens (48 rows of Q.K / softmax for 30). A 5-token chunk (128-key tiles) cuts the kernel from 637 to 502 us per layer at 48K (215 -> 175 us at 16K); whole model MTP 48K 77.4 -> 78.1 t/s, 115K 65.7 -> 67.1, output identical. GGML_SYCL_FA_DEC_NQ5=0 turns it off (=2 SLM-staged and =3 256-key tiles were slower). test-backend-ops: 5/6-token real-layout cases. Co-Authored-By: Claude <noreply@anthropic.com> (cherry picked from commit 081d868 on Torchit1/llama.cpp arc-b580)

…MA_ARG_SPEC_NGRAM_FRESH - ggml_sycl_knob(name, def): the attention (DPAS cap, staging, 5-token chunks, split count, probe) and PTQ1_0 T2 (tile, sub-groups, GEMM off) switches are read through it. With GGML_SYCL_KNOBS_FILE set, the NAME=VALUE file is re-read at the start of a graph compute when it changes, so one server can A/B variants. Without it, each knob is read from the environment once, as before. - LLAMA_ARG_SPEC_NGRAM_FRESH=1: the n-gram drafter forgets earlier requests at the start of each one, so repeated benchmark prompts don't replay earlier answers as drafts. Co-Authored-By: Claude <noreply@anthropic.com> (cherry picked from commit 9db9408 on Torchit1/llama.cpp arc-b580) Excluded from this port: common

Back-to-back T2 mat-vecs on one tensor reuse its int8 activations (GGML_SYCL_PTQ1_T2_QCACHE), and the signed 1024-point FWHT that feeds them runs 128 lanes per block and writes Aq/SA itself (GGML_SYCL_PTQ1_T2_FWHTQ). B580 Bonsai 27B plain decode +3.6-4.9%, KLD unchanged. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 254dfb2 on Torchit1/llama.cpp arc-b580)

ADD + RMS_NORM + MUL(weight) [+ MUL(signs) + RESHAPE + Hadamard MUL_MAT] runs as one work-group per token (GGML_SYCL_PTQ1_T2_NORMQ). Outputs only used inside the chain are not written; across tokens, outputs must not partly overlap inputs. B580 Bonsai 27B plain decode +1.9-2.6%, KLD unchanged. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 4d50f84 on Torchit1/llama.cpp arc-b580)

Upstream fixed the GemmMT row-scale broadcast that returned NaN under icpx's default -fp-model=fast (libxsmm/TernSYCL#1). B580: MUL_MAT ptq1_0/pq2_0 178/178 with fast math, KLD unchanged, decode speed unchanged. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 546f94c on Torchit1/llama.cpp arc-b580)

…e non-weight cost) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 2dbd839 on Torchit1/llama.cpp arc-b580)

…, W8A8 threshold as a runtime knob; test shapes GGML_SYCL_HOST_TIMING=1 splits decode graphs into between / enqueue / wait host time plus per-op enqueue cost, without a tracer. test-backend-ops: Bonsai attn k/v and output-head mat-vec shapes, FA nh=1,2 at 48K. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit ec71714 on Torchit1/llama.cpp arc-b580)

…NV_CHAIN) CONCAT + conv-cache CPY + SSM_CONV + SILU + L2_NORM in one kernel per layer (one work-group per 128-channel head). Outputs are written at the CONCAT's position, so nodes in between must not touch them (checked); an output may sit exactly on the qkv input (same element per channel), and an L2 output on top of the old conv state falls back to its own L2_NORM kernel. Also GGML_SYCL_FAST_SET_TENSOR (opt-in pinned input uploads). B580 Bonsai 27B plain decode +1.3-1.8%, KLD ub1 unchanged. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit b56951e on Torchit1/llama.cpp arc-b580)

bf16 alpha + beta mat-vecs (2 x 48 rows, same input, up to 8 tokens) with the dt-bias add, softplus, ssm_a multiply and sigmoid in one kernel: 9 graph nodes / 7 launches per layer -> 1 (2 when an output aliases the input and goes through a scratch buffer). GGML_SYCL_DN_GATES_DEBUG=1 prints why a block is not fused. B580 Bonsai 27B plain decode +0.5-1.4%, KLD unchanged. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 38c6be5 on Torchit1/llama.cpp arc-b580)

q+k+v, GDN qkv+z and FFN gate+up (<= 8 tokens) share one quantization and one GEMV launch: TernSYCL's Gemv body now takes its work-group indices (run()), and a wrapper maps each group to its matrix through a single call site (three inlined copies spilled: 34.6 vs 46.3 t/s). Grouping and output staging as the PTQ1_0 merge. B580 Bonsai 27B plain decode +1.8-2.0%, KLD unchanged. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 31ae86e on Torchit1/llama.cpp arc-b580)

SWIGLU -> MUL(signs) -> RESHAPE -> Hadamard MUL_MAT: the rotate/quantize kernel computes silu(gate) * up on its load (GGML_SYCL_GLU_ROT). ADD + RMS_NORM + MUL whose rotation comes ~9 nodes later (DeltaNet layers): the rotation is computed with the norm when no node in between touches its output (GGML_SYCL_NORM_ROT_FAR). Same arithmetic, byte-identical outputs. B580 Bonsai 27B plain +0.3-0.8%, MTP rename +2%, edit +1.1%. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit cf4b155 on Torchit1/llama.cpp arc-b580)

…EMV_MAX knob arctune sweep on the B580: tile {8,128,2,4} is 7-11% faster per pass for 12-32 rows (n-gram verify batches), the default {8,128,8,2} from 48 rows up. GGML_SYCL_PTQ1_T2_TILE now forces one tile for all sizes; GGML_SYCL_PTQ1_T2_TILE_SMALL_MAX (default 32) picks the crossover. GGML_SYCL_PTQ1_T2_GEMV_MAX (default 8) makes the GEMV/GemmMT switch a knob; the sweep confirmed 8. Outputs and KLD identical; MTP rename/edit +0.5%, 48K copy +1.3%. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit a70fe64 on Torchit1/llama.cpp arc-b580)

…L_FA_DEC_PF) Phase probes (GGML_SYCL_FA_DEC_DPAS_PROBE) showed Q.K and P.V serialised behind the K / V loads. Each tile now prefetches its V rows before Q.K and the next tile's K rows before P.V (sycl_ext_oneapi_prefetch, L1). Per layer at 1 token: 48K 263 -> 226 us, 115K 554 -> 496 us. Whole model: plain 48K +2.7%, 115K +4.4%; MTP 48K +4.2%, 115K +7.5%; outputs identical. FA Bonsai cases 5/5. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit dc575f4 on Torchit1/llama.cpp arc-b580)

test-backend-ops ARCLAB_GLU_ROT / ADD_NORM_ROT / CONV_CHAIN / DN_GATES / T2_MULTI build the exact node pattern each fusion matches, at Bonsai 27B shapes and 1-16 tokens, 3 seeds each, and compare every fused output with the CPU backend: 75/75 pass, each fusion confirmed firing (GGML_SYCL_FUSION_LOG, GGML_SYCL_T2_MULTI_LOG). Found while writing them: the far norm->rotation fusion now requires the signs to be a weight (they are read early); the conv chain no longer refuses a later reader of the cache slot; the same-input merge repacks weights on first use, so it also merges on the first graph. Whole model unchanged (plain short / 48K / 115K md5s identical). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit bfb2d76 on Torchit1/llama.cpp arc-b580) Conflict resolved against prism: test-backend-ops keeps prism's fused SwiGLU/sign-flip FWHT cases and adds these.

… empty table) ARC-LAB: GGML_SYCL_PTQ1_T2_TUNED=1 (default 0) looks up a (N, K, rows, merged) row in t2_tuned_table() for every 1..8-row T2 GEMV (t2_dispatch and ggml_sycl_t2_mul_mat_multi) and launches TernSYCL's Gemv<SGM, NSG, LS, U> (TernSYCL, BSD 3-Clause) under a GRF mode and work-group order through GemvTuned (= gsw::Sweep of /lab/exp/gemv-sweep). Tiles are compiled from the T2_TUNED_KERNELS X-macro; t2_precompile warms them when the knob is on. Table and kernel list are empty until the B580 sweep results are in, so =1 changes nothing. =2 is a plumbing self-test: the default tiles through the tuned launcher (outputs must stay identical). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit a0d82ad on Torchit1/llama.cpp arc-b580)

…exact tiles) ARC-LAB: five rows from /lab/exp/gemv-sweep (JIT build, medians of 5 interleaved rounds), each with the same LS as the default tile, so the outputs are bit-identical: ffn_down n=5 0.775, gate+up n=5 0.896, output head n=5 0.882, q+k+v n=5 0.923, q+k+v n=1 0.974 (time vs the default tile). Tiles are TernSYCL's Gemv (BSD 3-Clause) under a different launch geometry and work-group order. Batch sizes 2-4 and other shapes keep the default tiles. Knob still defaults to 0. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 4bd894b on Torchit1/llama.cpp arc-b580)

…TUNED=0 turns them off) B580 A/B (sd2 head): MTP-only +2.9/+3.1%; live MTP + n-gram short +4.4%, 48K +3.1%, 115K flat; outputs identical. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 0729c9d on Torchit1/llama.cpp arc-b580)

…EL_ZERO_V2 is set Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 5336e12 on Torchit1/llama.cpp arc-b580)

…aft head (knobs, off) The draft head's Q6_K mat-vecs are ~60% of a draft step and read at ~70% of the B580's bandwidth (op timing, 2026-10-10). - GGML_SYCL_Q6K_GEMV=1: a single-column reordered Q6_K mat-vec with the original per-row arithmetic (same lane -> quant-int mapping, blocks in order, same vec_dot expression accumulated in the same order, same sub-group reduction) but U blocks' operands loaded before use, aligned 32-bit ql/qh loads, and GGML_SYCL_Q6K_SG sub-groups per work-group. Sweep knobs GGML_SYCL_Q6K_U (1/2/4, default 2) and GGML_SYCL_Q6K_SG (4/8/16, default 8). GGML_SYCL_Q6K_CHECK=1 reruns the original kernel per launch and counts rows that differ in any bit (stderr), the in-server identity check. - GGML_SYCL_Q6K_GLU=1: Q6_K joins the reorder gate+up+GLU fusion (1..8 columns), whose dot products are the reorder mat-vec's and whose epilogue is the SWIGLU kernel's silu(gate) * up. - test-backend-ops: Q6_K mat-vec and gate+up fusion cases at the head's shapes (eval: 1, 2, 6 tokens; perf: 1..5 tokens). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 6dd4481 on Torchit1/llama.cpp arc-b580)

…= key reads (GGML_SYCL_FA_DEC_B2D, default off) xe2dp::ld2d_t32_8x16 (lsc_load_block2d d32.8x16tn): one message gives each lane 8 dwords of its own key row, replacing the per-lane dword gathers in Q.K (5 messages per 16 keys instead of 40) and P.V (1 instead of 5). Same bytes and math, 89/89 FLASH_ATTN_EXT cases. Engages only on 64-byte aligned K/V surfaces (logged once). Slower on its own at 128K (register spills): 5 tokens 1069 -> 1220 us, 16 tokens 2945 -> 3610 us. Kernel launch now goes through a named lambda. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit fb75ee9 on Torchit1/llama.cpp arc-b580)

…ery tokens (GGML_SYCL_FA_DEC_GRF, default 256) The 3+ token launch is one wave of 2 work-groups x 16 subgroups per Xe core = 32 threads, which is what the 256-register mode allows, so it costs no occupancy and removes the spills. 1-2 tokens keep the default register file (their wave puts 4 work-groups on a core). GGML_SYCL_FA_DEC_GRF=0 = off. B580, us per layer at 128K (real cache layout) 5 / 8 / 12 / 16 tokens: 1073 / 1434 / 2920 / 2939 -> 1004 / 1240 / 2465 / 2445; 1 token unchanged. Whole model (arctune x3, MTP + n-gram, sd3 head): 48K 106.1 -> 108.2 t/s (+2.0%), 115K 86.8 -> 90.6 (+4.4%), output md5 identical (d09ea3 / 291b0b). FLASH_ATTN_EXT q4_0: 480/480. Perf cases: kv 16K/64K/128K x 1/5/8/12/16 tokens. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 1eb2307 on Torchit1/llama.cpp arc-b580) Also carries the FLASH_ATTN_EXT perf cases this commit widens, first added by 1fa26f1 (Jesse Symons), which is not picked separately.

The port's MMVQ reorder (opt_for_reorder, also called by the fused gate/up path) and the PQ2_0 XMX rewrite (#294) both change these weights in place, and neither checked the other's flag. With GGML_SYCL_PTQ1_T2 unset a weight could get both layouts, so 27B PTQ1_0 perplexity went to 139615 on the B390 while every op test passed. On 16-wide DPAS devices the XMX layout now owns PQ2_0/PTQ1_0 and the reorder skips them; the fused paths that need the reorder decline and fall back to the unfused XMX path. The XMX path also refuses a weight that is already reordered or T2-repacked.

Keep prism's dequantize, vec_dot and MMVQ dispatch; keep the port's reorder-aware convert/MMVQ cases. Prism (#235/#294) and the port both added PQ2_0/PTQ1_0 support, so the merged tree had duplicate dequant functions, switch cases and two MMVQ implementations with the same names and did not compile. Deletions only, found and built on the B390 (oneAPI 2025.3.2).

khosravipasha

🤖 Reviewing on behalf of the maintainers

Thanks for the port, careful integration fixes, and correctness/performance testing! Approved from this source-review pass, with a couple of follow-ups before merging:

The default FP16 GEMM change covers other quantized formats for batches over 32, and the legacy Level Zero adapter default affects SYCL users beyond Bonsai. Please confirm what validation covers those broader defaults; otherwise, consider leaving them opt-in until tested.
Ubuntu CI failed while fetching the test model from Hugging Face (HTTP 500), rather than demonstrating a code regression. Please rerun that job.

I have not independently validated the kernels on Intel hardware. Please merge this before the stacked #357.

khosravipasha · 2026-10-13T22:59:50Z

🤖 Reviewing on behalf of the maintainers

A few targeted testing suggestions to cover the remaining gaps:

At the current PR head, compare PQ2_0 and PTQ1_0 with TernSYCL unset and enabled, including a model-level quality check. The reported layout corruption despite passing operator tests makes that end-to-end check especially valuable.
Exercise the default FP16 GEMM change with a conventional quantized model and batches around the 32/33-token boundary, checking correctness against the existing path. Bonsai-only results do not cover that broader default.
Where hardware is available, test Linux and a non-B390 Intel device, including one without the required DPAS capabilities, to confirm clean fallback. Keep unvalidated device-specific paths opt-in if needed.
For the opt-in Q4 attention path, include short/partial query tiles, long context, and the mean-centering KV-cache workflow if supported, checking output correctness as well as speed.

These are focused validation suggestions, not a request for an exhaustive benchmark matrix.

khosravipasha · 2026-10-13T23:00:13Z

🤖 Reviewing on behalf of the maintainers

Please treat the testing suggestions above as a menu, not a required full matrix; use your judgment on the most useful subset given available hardware. I'd prioritize the current-head PQ2_0/PTQ1_0 model-level checks and coverage of the broader default FP16 GEMM change. Additional device coverage can follow, with the remaining limitations recorded.

…code attention Measured on an Arc B390 (Panther Lake) with GGML_SYCL_PTQ1_T2 unset: - PQ2_0/PTQ1_0 weights go to the MMVQ reorder layout instead of the XMX layout: decode +16%, prompt +6%, about 0.9 GB less memory; KLD vs prism 6.7e-4 (XMX 2.4e-4). GGML_SYCL_DISABLE_XMX=0 restores the XMX layout, =1 still forces the reorder on any device. - GGML_SYCL_FA_DEC_DPAS defaults to 1: decode at 16K context +4-6% with a q4_0 KV cache; FLASH_ATTN_EXT head size 256 264/264, KLD with and without it within run-to-run error. =0 turns it off. Other devices keep their previous defaults.

Torchit1 added 30 commits October 13, 2026 14:09

sycl: lab knob GGML_SYCL_T2_ZERO_WEIGHTS (zeroes T2 weights to profil…

1f16921

…e non-weight cost) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 2dbd839 on Torchit1/llama.cpp arc-b580)

Torchit1 and others added 11 commits October 13, 2026 14:09

sycl: default to the legacy Level Zero adapter unless SYCL_UR_USE_LEV…

174e85d

…EL_ZERO_V2 is set Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> (cherry picked from commit 5336e12 on Torchit1/llama.cpp arc-b580)

bri-prism marked this pull request as ready for review October 13, 2026 21:14

github-actions Bot added documentation Improvements or additions to documentation ggml testing SYCL labels Oct 13, 2026

bri-prism mentioned this pull request Oct 13, 2026

llama: GDN rollback by replay, one-graph MTP draft chain, K/V-only MTP prompt pass, sync trim (port of Torchit1/arc-b580) #357

Merged

bri-prism requested a review from khosravipasha October 13, 2026 22:52

khosravipasha approved these changes Oct 13, 2026

View reviewed changes

bri-prism merged commit 2972e00 into prism Oct 14, 2026
8 checks passed

This was referenced Oct 14, 2026

llama: GDN rollback by replay, one-graph MTP draft chain, K/V-only MTP prompt pass, sync trim (port of Torchit1/arc-b580) #358

Merged

docs: Ternary Bonsai 2 on Intel GPUs with the SYCL backend #359

Merged

This was referenced Oct 14, 2026

cuda: reserve the f16 K/V scratch for the short-query MMA route (#346) #350

Closed

tests: portable popcount in arclab_init_hadamard (MSVC build) #362

Merged

Navigation Menu

Repository navigation

sycl: TernSYCL XMX path, decode attention and fusions for Bonsai 2 27B on Intel Arc (port of Torchit1/arc-b580) - #356

sycl: TernSYCL XMX path, decode attention and fusions for Bonsai 2 27B on Intel Arc (port of Torchit1/arc-b580)#356
bri-prism merged 42 commits into
prismfrom
sycl/arc-b580-port

bri-prism commented Oct 13, 2026 •

edited

Loading

Uh oh!

khosravipasha left a comment

Uh oh!

khosravipasha commented Oct 13, 2026

Uh oh!

khosravipasha commented Oct 13, 2026

Uh oh!

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

3 participants

Conversation

bri-prism commented Oct 13, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

What

Why

Defaults that change for SYCL users

Testing (Arc B390, Windows 11, driver 32.0.101.8860, oneAPI 2025.3.2)

Credit

Uh oh!

khosravipasha left a comment

Choose a reason for hiding this comment

Uh oh!

khosravipasha commented Oct 13, 2026

Uh oh!

khosravipasha commented Oct 13, 2026

Uh oh!

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

3 participants

bri-prism commented Oct 13, 2026 •

edited

Loading