docs: align mov condition opcode names

[kurahin]

Renamed MOVZ/MOVN to MEQ/MNE in the ISA table so the documentation matches the actual opcode names used by the executor and mnemonic mapping.

[eigmax]

MNE is not the opcode name in MIPS, just an alias used inside Ziren.

[eigmax]

Thanks for the PR. Closing it, because the ISA table in docs/src/mips-vm/mips-isa.md lists MIPS32 architectural instructions, not executor opcodes.

Every row there is the official MIPS mnemonic with its encoding, for example ADDIU, ANDI, BGEZ and CLO, and many of them decode to differently named executor opcodes (ADDIU and ANDI become ADD and AND). MOVZ (SPECIAL, funct 001010) and MOVN (funct 001011) are the MIPS32r2 names that assemblers, objdump and the spec use. The executor's internal names are already documented on the same page, in the opcode enum (MEQ = 50, MNE = 51, MOVCOND). The decoder maps one to the other in crates/core/executor/src/instruction.rs (0b001010 → Opcode::MEQ, 0b001011 → Opcode::MNE). Renaming only these two rows would make them the only internal names in an architectural table, and readers matching disassembly would no longer find movz/movn.

If the aim is to make the correspondence visible, a change that keeps MOVZ/MOVN and adds the executor opcode in the description, for example rd = rs, if rt == 0 (executor: MEQ), would be welcome.