cpufeatures: add Speculation Barrier (SB) support for AArch64 - #1536
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As suggested in #1472, this instruction is needed by the `aarch64-dit` crate to properly implement Data-Independent Timing: https://support.arm.com/documentation/ddi0487/mb/-Part-B-The-AArch64-Application-Level-Architecture/-Chapter-B2-The-AArch64-Application-Level-Memory-Model/-B2-6-Memory-barriers/-B2-6-3-Speculation-Barrier The usage on Apple targets is covered here: https://developer.apple.com/documentation/xcode/writing-arm64-code-for-apple-platforms#Enable-DIT-for-constant-time-cryptographic-operations > "To ensure that subsequent instruction timing reflects the updated DIT > processor state, add a speculation barrier after turning on DIT. > Use the sb instruction to add a speculation barrier" This PR is effectively an extraction of the `cpufeatures`-related changes originally suggested in this patch from #1472: f31f41c
tarcieri
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Sep 10, 2026
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| @@ -89,6 +90,7 @@ pub mod hwcaps { | |||
| pub const SHA2: c_ulong = libc::HWCAP_SHA2; | |||
| pub const SHA3: c_ulong = libc::HWCAP_SHA3 | libc::HWCAP_SHA512; | |||
| pub const SM4: c_ulong = libc::HWCAP_SM3 | libc::HWCAP_SM4; | |||
| pub const SB: c_ulong = libc::HWCAP_SB; | |||
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Note: it's unclear to what extent either DIT or SB are helpful on non-Apple targets, as covered in #1472, but they've been added here (i.e. Linux) for completeness
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As suggested in #1472, this instruction is needed by the
aarch64-ditcrate to properly implement Data-Independent Timing:https://support.arm.com/documentation/ddi0487/mb/-Part-B-The-AArch64-Application-Level-Architecture/-Chapter-B2-The-AArch64-Application-Level-Memory-Model/-B2-6-Memory-barriers/-B2-6-3-Speculation-Barrier
The usage on Apple targets is covered here:
https://developer.apple.com/documentation/xcode/writing-arm64-code-for-apple-platforms#Enable-DIT-for-constant-time-cryptographic-operations
This PR is effectively an extraction of the
cpufeatures-related changes originally suggested in this patch from #1472:f31f41c