Multi Cycle Processor

This is the implementation of a multi cycle processor that uses an architecture that is similar to MIPS architecture and has a custom ISA that runs on it.

Name		Name	Last commit message	Last commit date
ALU.v		ALU.v
Controller .v		Controller .v
Datapath.v		Datapath.v
EE 446 Laboratory Work 5.pdf		EE 446 Laboratory Work 5.pdf
IDM.v		IDM.v
Laboratory Work 5.pdf		Laboratory Work 5.pdf
MCP.v		MCP.v
MCP_TB.v		MCP_TB.v
Mux2x1.v		Mux2x1.v
Mux4x1.v		Mux4x1.v
PC.v		PC.v
README.md		README.md
RF.v		RF.v
RegWithWE.v		RegWithWE.v
Shifter.v		Shifter.v
simpleReg.v		simpleReg.v

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