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10 changes: 4 additions & 6 deletions src/ext/b/zba.sv
Original file line number Diff line number Diff line change
Expand Up @@ -9,10 +9,8 @@

module zba(input [31:0] reg1
, input [31:0] reg2
, input [1:0] inst // two bit register, distinguish instruction
, input [2:0] inst // three bit register, distinguish instruction
/* verilator lint_off UNUSEDSIGNAL */
, input [2:0] funct3 //extra function inputs
, input [6:0] funct7
, output logic[31:0] out
);

Expand All @@ -22,15 +20,15 @@ always_comb

// sh1add behaviour

2'b00: out = (reg1 << 1) + reg2;
3'b010: out = (reg1 << 1) + reg2;

// sh2add behaviour

2'b01: out = (reg1 << 2) + reg2;
3'b100: out = (reg1 << 2) + reg2;

// sh3add

2'b10: out = (reg1 << 3) + reg2;
3'b110: out = (reg1 << 3) + reg2;

// other

Expand Down
8 changes: 7 additions & 1 deletion src/stages/execute_stage.sv
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ module execute_stage
logic zero_flag;

`ifdef UTOSS_RISCV_ENABLE_B_EXT
data_t zbb_result, zbkb_result;
data_t zba_result, zbb_result, zbkb_result;
logic zbb_zero_flag, zbkb_zero_flag;
`endif

Expand Down Expand Up @@ -73,6 +73,12 @@ module execute_stage
);

`ifdef UTOSS_RISCV_ENABLE_B_EXT
zba u_zba
( .reg1 (rs1)
, .reg2 (rs2)
, .inst (id_to_ex.funct3)
, .out (zba_result)
);
zbb u_zbb
( .a ( alu_input_a )
, .b ( alu_input_b )
Expand Down
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