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feat(image): fused DiT kernels, a 3x3 VAE convolution and faster large-row NAX matmuls, on mlx 0.32.3 - #89
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…s and a three-floor roofline
…probes at diffusion transformer shapes
…vs A aggregate and per-cell median CIs
… scalar loads and no-reuse bytes in side columns
… thermal curve for the cold rate
…ore calls per sample
…, f32 rows at M 1 and 2, and R1 and R2 calibration
…tches a known pattern
… single-threaded A/B runs, both off when unset
…s of pooled pairs, and raw samples reach disk before the summaries
…regate rebuilds the reports from it, and the median CI has CPU tests up to 5000 samples
… round beyond one weight and one output rounding
…ve guard, and KQ_NAX_BM128_ODD_M=0 keeps the parity rule
…, and KQ_SPLITK_F32=0 keeps the activation-dtype partials
…ount, not by output bits
…rors other than a declined route
…d size per GPU core
…h block in float, and KQ_VERIFY_MMA_HALF=1 keeps the half kernels
…8 and 256, at K below 2048, on three codecs below 4096 rows and up to 16384 rows
…batch row bound of the residual op
…mplate parameters of each codec kernel
…uantize then the stock matmul on m3 max with 40 gpu cores
…quantize then the stock matmul on m3 max with 40 gpu cores
…e m5 inside its measured k and n range, with a vjp on the quantized weight and a lever to force or disable it
…s k and n range, vjp, lever and log line
…ed matmul raises as on the kernel, the route decision is one tested function, and its tests check large calls on row slices
…and a shorter changelog entry
…ernel's name, and its tests check every row in blocks
…uffer completes, and the changelog names the measured chip
…herent buffers, and its kernels need two simdgroups
… as the ci paravirtual gpu miscompiles coherent bfloat vector accesses
… env builds, so it holds on gpus without nax
… they hold where mlx compile is off
…MLX_DISABLE_COMPILE holds for the tests after it
… nodes off too, as a gpu without nax builds them
…re that puts back the one found, so they hold under MLX_DISABLE_COMPILE
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