Skip to content

Latest commit

 

History

9 Commits

Folders and files

NameName
Last commit message
Last commit date
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

My Celox Project

A hardware simulation project using Celox and Veryl.

Prerequisites

Quick Start

# Install dependencies
pnpm install

# Run tests
pnpm test

Project Structure

├── Veryl.toml          # Veryl project configuration
├── vitest.config.ts    # Vitest config with Celox plugin
├── src/
│   ├── Adder.veryl     # 16-bit combinational adder
│   └── Counter.veryl   # 8-bit sequential counter
└── test/
    ├── adder.test.ts   # Event-based simulation tests
    └── counter.test.ts # Time-based simulation tests

Writing Tests

Event-based simulation (Simulator)

Use Simulator for combinational logic or when you want manual control over clock edges:

import { Simulator } from "@celox-sim/celox";

const sim = Simulator.fromProject<MyPorts>(".", "MyModule");
sim.dut.input = 42;
expect(sim.dut.output).toBe(expectedValue);
sim.dispose();

Time-based simulation (Simulation)

Use Simulation for sequential logic with automatic clock generation:

import { Simulation } from "@celox-sim/celox";

const sim = Simulation.fromProject<MyPorts>(".", "MyModule");
sim.addClock("clk", { period: 10 });

sim.dut.rst = 1;
sim.runUntil(20);
sim.dut.rst = 0;

sim.runUntil(100);
expect(sim.dut.output).toBe(expectedValue);
sim.dispose();

Next Steps

About

Starter template for Celox HDL simulator projects

Resources

Stars

0 stars

Watchers

0 watching

Forks

Releases

Packages

Contributors

Languages