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compress_icf_map_g() parses the level 3 match map greedily: from each position it takes the match there, a literal and the match after it, or two literals. Whether a position starts a match is close to random, so the branches of the C loop mispredict often. The compiled loop also reloads level_buf->icf_buf_next after each store. Move the parse loops to parse_icf_map_g(), dispatched like the other level 3 functions. parse_icf_map_g_base keeps the C loops, with the output pointer in a local. parse_icf_map_g_06, for x86 with AVX-512, first finds how far the parse moves from each position, 16 positions at a time. It then follows those advances in a loop that writes the codes and counts the histogram with conditional moves, so the only branches of the loop are its exits. The codes and the histogram do not change. Level 3 in-process A/B against master on GitHub runners, whole Silesia files: +11.9% on AMD EPYC 9V45 (Zen 5), +10.9% on Emerald Rapids, +7.5% on Granite Rapids, +3.9% on Ice Lake, +2.4% on EPYC 9V74 (Zen 4). The measured build had the same loop code, plus a dead store and a redundant xor in the setup. Signed-off-by: Parker Loflin <parker@cronstable.dev>
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compress_icf_map_g()parses the level 3 match map greedily: from each position it takes the match there, a literal and the match after it, or two literals. Whether a position starts a match is close to random, so the branches of the C loop mispredict often. This PR moves the parse into a dispatchedparse_icf_map_g()and addsparse_icf_map_g_06, which computes the advance from each position, 16 at a time, then follows the advances in a loop that writes the codes and counts the histogram with conditional moves. The loop's only branches are its exits.Which CPUs run it
x86 CPUs with AVX-512 run
parse_icf_map_g_06, at the_06dispatch level like the other level 3 kernels. Everything else, including aarch64, riscv64 andarch=noarch, runsparse_icf_map_g_base: the C loops, with the output pointer kept in a local. Only level 3 calls the parse.Output
The output does not change.
Results
Level 3 MB/s, master → this PR, in-process A/B on GitHub runners (harness; runs 1, 2, 3) on the Silesia files and on 256 slices of silesia.tar per size. Each cell is the median over all runs (two per runner) of the best of 11 rounds and, in parentheses, the median over runs of the change in median-round throughput. The benchmarked build has this PR's loop code with two extra setup instructions (a dead store and a redundant
xor).The Zen 3 runners (EPYC 7763, no AVX-512) run the C version and are within 1% of master at every size.
Testing
make checkpasses on x86-64, witharch=noarch, on aarch64 under qemu, and natively on Windows (mingw-w64) on a Ryzen 7 9800X3D, which dispatchesparse_icf_map_g_06. The igzip tests pass on riscv64 under qemu.parse_icf_map_g_06matchesparse_icf_map_g_base(return value, codes, histogram) on random match maps, as SysV code and as win64 code called through a thunk, with guard pages after the output and 64 bytes past the end of the map. The vector pass reads up to 16 entries past the end, whichhash_map.overflow[]makes room for.arch=noarch.parse_icf_map_g_06in level 3 deflate preserves xmm6-xmm15, the callee-saved general purpose registers, rsp and DF.