Eliminate redundant wires between submodule outputs and parent bus bits

[mkorbel1]

Description & Motivation

Improve generated SystemVerilog when multiple scalar submodule outputs feed a parent output bus through Logic.assignSubset. These connections can now map directly to destination bits, such as .result(observed[2]), instead of retaining intermediate wires and separate assignments.

The optimization applies to fully covered parent output buses, including connections through clearable full-width aliases. Existing safety checks for fanout, overlapping assignments, preserved names, constants, partial coverage, and net/array boundaries remain in place. Internal-bus concatenation behavior is unchanged.

Related Issue(s)

N/A

Testing

Added 157 synthetic regression cases covering producer topology, assignment order, alias depth, fanout, repeated source bits, preserved names, partial coverage, constants, mixed-width sources, 33/65-bit boundaries, and nested array consumers.

Tests check emitted port mappings, functional behavior, X/Z propagation, and repeat-synthesis stability with intervening netlist generation. Generated SystemVerilog is simulated with Icarus; unpacked-array integration uses Verilator for two-state simulation and ROHD for four-state checks.

• existing tests cover a lot

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No public API or functional behavior changes are intended. Generated SystemVerilog may contain fewer intermediate wires and assignments, so downstream checks that depend on exact generated text or internal signal names may need updates.

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

No user-facing documentation updates are required. This improves synthesis output without changing how designs are written.