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Keep the existing IRQ vectors and handlers, route device interrupts to the boot CPU and use the local APIC timer for scheduling. Leave the legacy PIC masked and remove its driver. Co-authored-by: Florian Kargl <f.kargl@posteo.de>
Adapt the INIT/SIPI sequence and real-mode entry from Florian Kargl's #287 (2546c25 and 8256d12). Keep the entry code in a naked C++ function, copy it to a reserved low page, and give each CPU its own TLS, stack, GDT and TSS. Secondary CPUs acknowledge initialization and remain parked with interrupts disabled until SMP scheduling is implemented. Co-authored-by: Florian Kargl <f.kargl@posteo.de>
Add compiler memory barriers to interrupt enable/disable and make the x86_64 IF query volatile.
Disable local interrupts across the sleep/unlock handoff, then yield and restore the previous interrupt state. Waking a thread no longer needs to wait for it to fall asleep. Use acquire/release accesses for thread state. Adapted from Florian Kargl's #287 (e6f3518). Co-authored-by: Florian Kargl <f.kargl@posteo.de>
Use thread_local for __cpu and let the compiler construct one scheduler per CPU. Initialize secondary CPU schedulers before reporting them online. Reserve room for the embedded thread stacks in boot TLS and omit TLS destructor registration. Build on Florian Kargl's CPU-local storage and earlier per-CPU scheduler in #287 (593c4ea and 20389d1). Co-authored-by: Florian Kargl <f.kargl@posteo.de>
Assign threads to a scheduler when they are enqueued and require local access to its thread list. Its cleanup thread can only run after the exiting thread has left its stack. Allow killing the current thread or a thread not yet enqueued. Cross-CPU wakeups still only change the thread state. Use the per-CPU cleanup approach from Florian Kargl's earlier CPU-local scheduler in #287 (20389d1). Co-authored-by: Florian Kargl <f.kargl@posteo.de>
Run local APIC setup on each CPU while keeping discovery and I/O APIC routing on the boot CPU. Secondary CPUs wait until boot allocations are finished, then enable their timer and enter their scheduler. Keep the existing heartbeat display on the boot CPU.
Use an NMI so CPUs also stop with interrupts disabled. Wait for their acknowledgements before setting KPANIC, which bypasses locks. Concurrent panics leave one CPU printing diagnostics.
Flush every active CPU and wait for acknowledgements before reusing mapped pages or page tables. Generation counters allow concurrent requests and coalesced IPIs without a shootdown lock. Adapt the unmap ordering from Florian Kargl's #287. Co-authored-by: Florian Kargl <f.kargl@posteo.de>
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Based on Florian Kargl's SMP work in #287 (@Woazboat), including ACPI/APIC, CPU-local storage, CPU startup, constructor support and several locking fixes.
One round-robin scheduler per CPU, including its own idle and cleanup threads.
__cpuusesthread_local, also for the scheduler object. New processes are distributed across CPUs; a thread stays on its CPU once enqueued.Replace PIC interrupt delivery with APIC, use local timers on each CPU, stop the other CPUs before printing panic diagnostics, and wait for TLB invalidation before reusing pages. Also fix the shared lock diagnostics, console buffers and ATA request/completion races. VFS operations use one mutex for now, with user buffers copied outside the lock so demand paging can read the executable without deadlocking.
make 1core,make 2core,make 4coreandmake 8corechange the QEMU CPU count while keeping the current architecture and build settings. The Raspberry Pi QEMU boards require four CPUs.Includes the constructor support from #336, needed for the CPU-local scheduler object. SMP scheduling is currently supported on x86_64.
This still needs a run on a full SWEB with more filesystem interactions before merging.