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[rtl] Switch to ratified bitmanip extensions #2459

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3 changes: 1 addition & 2 deletions README.md
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Expand Up @@ -47,8 +47,7 @@ Notes:
Amber indicates that some verification has been performed, but the configuration is still experimental.
Red indicates a configuration with minimal/no verification.
Users must make their own assessment of verification readiness for any tapeout.
* v.1.0.0 of the RISC-V Bit-Manipulation Extension is supported as well as the remaining sub-extensions of draft v.0.93 of the bitmanip spec.
The latter are *not ratified* and there may be changes before ratification.
* The ratified v.1.0.0 RISC-V Bit-Manipulation Extension (Zba, Zbb, Zbc, Zbs) is supported, as well as the ratified Zbkb and Zbkx sub-extensions of the RISC-V Scalar Cryptography Extension.
See [Standards Compliance](https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html) in the Ibex documentation for more information.

## Documentation
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20 changes: 8 additions & 12 deletions doc/01_overview/compliance.rst
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Expand Up @@ -8,7 +8,8 @@ It follows these specifications:
* `RISC-V Instruction Set Manual, Volume II: Privileged Architecture, document version 20211203 (December 4, 2021) <https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf>`_.
Ibex implements the Machine ISA version 1.12.
* `RISC-V External Debug Support, version 0.13.2 <https://content.riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf>`_
* `RISC-V Bit-Manipulation Extension, version 1.0.0 <https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf>`_ and `version 0.93 (draft from January 10, 2021) <https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.93.pdf>`_
* `RISC-V Bit-Manipulation Extension, version 1.0.0 <https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf>`_ (Zba, Zbb, Zbc, Zbs sub-extensions)
* `RISC-V Scalar Cryptography Extension, version 1.0.1 <https://github.com/riscv/riscv-crypto/releases/download/v1.0.1-scalar/riscv-crypto-spec-scalar-v1.0.1.pdf>`_ (Zbkb, Zbkx sub-extensions only)
* `PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp) version 1.0 <https://github.com/riscv/riscv-tee/blob/191b563b08b31cc2974d604a3b670d8666a2e093/Smepmp/Smepmp.pdf>`_

Many features in the RISC-V specification are optional, and Ibex can be parametrized to enable or disable some of them.
Expand All @@ -35,8 +36,12 @@ In addition, the following instruction set extensions are available.
- 2.0
- optional

* - **B**: Standard Extension for Bit-Manipulation Instructions
- 1.0.0 + 0.93 [#B_draft]_
* - **B**: Standard Extension for Bit-Manipulation Instructions (Zba, Zbb, Zbc, Zbs)
- 1.0.0
- optional
Comment on lines +39 to +41

@vogelpi vogelpi Aug 10, 2026

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Please note that B just comprises Zba, Zbb and Zbs. The collection comprising Zba, Zbb, Zbc and Zbs is called RISC-V bit manipulation extension v.1.0.0 (see https://www.ece.lsu.edu/ee4720/doc/riscv-bitmanip-1.0.0.pdf, it's the same doc you referenced above but this doesn't reference "B" anymore).

So, here we should probably say:

  • B + Zbc because that's what we use our ISA string
  • or then Zba, Zbb, Zbc, Zbs as above


* - **Zbkb, Zbkx**: Scalar Cryptography Bit-Manipulation Instructions
- 1.0.1
- optional

* - **Zicsr**: Control and Status Register Instructions
Expand Down Expand Up @@ -69,12 +74,3 @@ Ibex currently supports the following features according to the RISC-V Privilege
* All CSRs listed in :ref:`cs-registers`
* Performance counters as described in :ref:`performance-counters`
* Vectorized trap handling as described at :ref:`exceptions-interrupts`

.. rubric:: Footnotes

.. [#B_draft] Ibex fully implements the ratified version 1.0.0 of the RISC-V Bit-Manipulation Extension including the Zba, Zbb, Zbc and Zbs sub-extensions.
In addition, Ibex also supports the remaining Zbe, Zbf, Zbp, Zbr and Zbt sub-extensions as defined in draft version 0.93 of the RISC-V Bit-Manipulation Extension.
Note that the latter sub-extensions may change before being ratified as a standard by the RISC-V Foundation.
Ibex will be updated to match future versions of the specification.
Prior to ratification this may involve backwards incompatible changes.
Additionally, neither GCC or Clang have committed to maintaining support upstream for unratified versions of the specification.
2 changes: 1 addition & 1 deletion doc/02_user/configuration.rst
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Expand Up @@ -23,7 +23,7 @@ Here is an example of using the configuration tool to get the FuseSoC options re
./util/ibex_config.py opentitan fusesoc_opts

# The output of the tool
--RV32E=0 --RV32M=ibex_pkg::RV32MSingleCycle --RV32B=ibex_pkg::RV32BOTEarlGrey --RegFile=ibex_pkg::RegFileFF --BranchTargetALU=1 --WritebackStage=1 --ICache=1 --ICacheECC=1 --ICacheScramble=1 --BranchPredictor=0 --DbgTriggerEn=1 --SecureIbex=1 --PMPEnable=1 --PMPGranularity=0 --PMPNumRegions=16 --MHPMCounterNum=10 --MHPMCounterWidth=32
--RV32E=0 --RV32M=ibex_pkg::RV32MSingleCycle --RV32B=ibex_pkg::RV32BFull --RegFile=ibex_pkg::RegFileFF --BranchTargetALU=1 --WritebackStage=1 --ICache=1 --ICacheECC=1 --ICacheScramble=1 --BranchPredictor=0 --DbgTriggerEn=1 --SecureIbex=1 --PMPEnable=1 --PMPGranularity=0 --PMPNumRegions=16 --MHPMCounterNum=10 --MHPMCounterWidth=32

For further information about using the tool check the help provided on the command line.

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5 changes: 2 additions & 3 deletions doc/02_user/integration.rst
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Expand Up @@ -209,9 +209,8 @@ Parameters
+------------------------------+---------------------+----------------+-----------------------------------------------------------------------+
| ``RV32B`` | ibex_pkg::rv32b_e | RV32BNone | B(itmanipulation) extension select: |
| | | | "ibex_pkg::RV32BNone": No B-extension |
| | | | "ibex_pkg::RV32BBalanced": Sub-extensions Zba, Zbb, Zbs, Zbf and Zbt |
| | | | "ibex_pkg::RV32BOTEarlGrey": All sub-extensions except Zbe |
| | | | "ibex_pkg::RV32BFull": All sub-extensions |
| | | | "ibex_pkg::RV32BBalanced": Sub-extensions Zba, Zbb, Zbs |
| | | | "ibex_pkg::RV32BFull": Balanced plus Zbc, Zbkb, Zbkx |
+------------------------------+---------------------+----------------+-----------------------------------------------------------------------+
| ``RV32ZC`` | ibex_pkg::rv32zc_e | RV32ZcaZcbZcmp | Zc code-size saving extension select: |
| | | | "ibex_pkg::RV32Zca": The Zca extension |
Expand Down
57 changes: 20 additions & 37 deletions doc/03_reference/instruction_decode_execute.rst
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Expand Up @@ -65,43 +65,35 @@ Other blocks use the ALU for the following tasks:
* The LSU uses it to increment addresses when performing two accesses to handle an unaligned access

Bit-Manipulation Extension
Support for the `RISC-V Bit-Manipulation Extension version 1.0.0 <https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf>`_ and `draft version 0.93 from January 10, 2021 <https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.93.pdf>`_ is optional. [#B_draft]_
Support for the `RISC-V Bit-Manipulation Extension version 1.0.0 <https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf>`_, together with the Zbkb and Zbkx sub-extensions of the ratified Scalar Cryptography Extension, is optional.
It can be enabled via the enumerated parameter ``RV32B`` defined in :file:`rtl/ibex_pkg.sv`.
By default, this parameter is set to "ibex_pkg::RV32BNone" to disable the bit-manipulation extension.

There are three versions of the bit-manipulation extension available:
There are two versions of the bit-manipulation extension available:
The balanced version comprises a set of sub-extensions aiming for good benefits at a reasonable area overhead.
It can be selected by setting the ``RV32B`` parameter to "ibex_pkg::RV32BBalanced".
The OTEarlGrey version comprises all sub-extensions except for the Zbe.
This version can be selected by setting the ``RV32B`` parameter to "ibex_pkg::RV32BOTEarlGrey".
The full version comprises all sub-extensions and can be selected by setting the ``RV32B`` parameter to "ibex_pkg::RV32BFull".
The full version additionally comprises the Zbc, Zbkb and Zbkx sub-extensions and can be selected by setting the ``RV32B`` parameter to "ibex_pkg::RV32BFull".
The following table gives an overview of which sub-extensions are implemented in each version and of which instructions are implemented as multi-cycle instructions.
Multi-cycle instructions are completed in 2 cycles.
All remaining instructions complete in a single cycle.

+--------------------------------+---------+----------+------------+------+--------------------+
| Bit-Manipulation Sub-Extension | Spec. | Balanced | OTEarlGrey | Full | Multi-Cycle Instr. |
+================================+=========+==========+============+======+====================+
| Zba (Address generation) | v.1.0.0 | X | X | X | None |
+--------------------------------+---------+----------+------------+------+--------------------+
| Zbb (Base) | v.1.0.0 | X | X | X | rol, ror[i] |
+--------------------------------+---------+----------+------------+------+--------------------+
| Zbc (Carry-less multiply) | v.1.0.0 | | X | X | None |
+--------------------------------+---------+----------+------------+------+--------------------+
| Zbs (Single-bit) | v.1.0.0 | X | X | X | None |
+--------------------------------+---------+----------+------------+------+--------------------+
| Zbe (Bit compress/decompress) | v.0.93 | | | X | All |
+--------------------------------+---------+----------+------------+------+--------------------+
| Zbf (Bit-field place) | v.0.93 | X | X | X | All |
+--------------------------------+---------+----------+------------+------+--------------------+
| Zbp (Permutation) | v.0.93 | | X | X | None |
+--------------------------------+---------+----------+------------+------+--------------------+
| Zbr (CRC) | v.0.93 | | X | X | All |
+--------------------------------+---------+----------+------------+------+--------------------+
| Zbt (Ternary) | v.0.93 | X | X | X | All |
+--------------------------------+---------+----------+------------+------+--------------------+

The implementation of the Bit-Manipulation Extension comes with an area overhead of 2.7 kGE for the balanced version, 6.1 kGE for the OTEarlGrey version, and 7.5 kGE for the full version.
+------------------------------------+---------+----------+------+--------------------+
| Bit-Manipulation Sub-Extension | Spec. | Balanced | Full | Multi-Cycle Instr. |
+====================================+=========+==========+======+====================+
| Zba (Address generation) | v.1.0.0 | X | X | None |
+------------------------------------+---------+----------+------+--------------------+
| Zbb (Base) | v.1.0.0 | X | X | rol, ror[i] |
+------------------------------------+---------+----------+------+--------------------+
| Zbc (Carry-less multiply) | v.1.0.0 | | X | None |
+------------------------------------+---------+----------+------+--------------------+
| Zbs (Single-bit) | v.1.0.0 | X | X | None |
+------------------------------------+---------+----------+------+--------------------+
| Zbkb (Bit-manipulation for crypto) | v.1.0.0 | | X | None |
+------------------------------------+---------+----------+------+--------------------+
| Zbkx (Crossbar permutation) | v.1.0.0 | | X | None |
+------------------------------------+---------+----------+------+--------------------+

The implementation of the Bit-Manipulation Extension comes with an area overhead of 2.4 kGE for the balanced version and 5.9 kGE for the full version, relative to a configuration without any bit-manipulation support.
These numbers were obtained by synthesizing the design with Yosys and relaxed timing constraints.


Expand Down Expand Up @@ -169,12 +161,3 @@ Source File: :file:`rtl/ibex_load_store_unit.sv`

The Load-Store Unit (LSU) interfaces with main memory to perform load and store operations.
See :ref:`load-store-unit` for more details.

.. rubric:: Footnotes

.. [#B_draft] Ibex fully implements the ratified version 1.0.0 of the RISC-V Bit-Manipulation Extension including the Zba, Zbb, Zbc and Zbs sub-extensions.
In addition, Ibex also supports the remaining Zbe, Zbf, Zbp, Zbr and Zbt sub-extensions as defined in draft version 0.93 of the RISC-V Bit-Manipulation Extension.
Note that the latter sub-extensions may change before being ratified as a standard by the RISC-V Foundation.
Ibex will be updated to match future versions of the specification.
Prior to ratification this may involve backwards incompatible changes.
Additionally, neither GCC or Clang have committed to maintaining support upstream for unratified versions of the specification.
23 changes: 11 additions & 12 deletions dv/cosim/spike_cosim.cc
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Expand Up @@ -73,7 +73,8 @@ SpikeCosim::SpikeCosim(const std::string &isa_string, uint32_t start_pc,
processor->set_ibex_flags(secure_ibex, icache_en);
processor->set_debug_module_range(dm_start_addr, dm_end_addr);

initial_proc_setup(start_pc, start_mtvec, mhpm_counter_num);
bool rv32b_enabled = isa_string.find("Zb") != std::string::npos;
initial_proc_setup(start_pc, start_mtvec, mhpm_counter_num, rv32b_enabled);

if (log) {
processor->set_debug(true);
Expand Down Expand Up @@ -565,13 +566,21 @@ void SpikeCosim::set_cpuctrlsts_double_fault_seen() {
}

void SpikeCosim::initial_proc_setup(uint32_t start_pc, uint32_t start_mtvec,
uint32_t mhpm_counter_num) {
uint32_t mhpm_counter_num,
bool rv32b_enabled) {
processor->get_state()->pc = start_pc;
processor->get_state()->mtvec->write(start_mtvec);

processor->get_state()->csrmap[CSR_MARCHID] =
std::make_shared<const_csr_t>(processor.get(), CSR_MARCHID, IBEX_MARCHID);

uint32_t misa_val = processor->get_csr(CSR_MISA);
if (rv32b_enabled) {
misa_val |= 1 << 1;
}
processor->get_state()->csrmap[CSR_MISA] =
std::make_shared<const_csr_t>(processor.get(), CSR_MISA, misa_val);

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thommythomaso marked this conversation as resolved.
processor->set_mmu_capability(IMPL_MMU_SBARE);

for (int i = 0; i < processor->TM.count(); ++i) {
Expand Down Expand Up @@ -825,16 +834,6 @@ void SpikeCosim::fixup_csr(int csr_num, uint32_t csr_val) {
processor->set_csr(csr_num, new_val);
#else
processor->put_csr(csr_num, new_val);
#endif
break;
}
case CSR_MISA: {
// For Ibex, misa is hardwired
reg_t new_val = 0x40901104;
#ifdef OLD_SPIKE
processor->set_csr(csr_num, new_val);
#else
processor->put_csr(csr_num, new_val);
#endif
break;
}
Expand Down
2 changes: 1 addition & 1 deletion dv/cosim/spike_cosim.h
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Expand Up @@ -91,7 +91,7 @@ class SpikeCosim : public simif_t, public Cosim {
void handle_cpuctrl_exception_entry();

void initial_proc_setup(uint32_t start_pc, uint32_t start_mtvec,
uint32_t mhpm_counter_num);
uint32_t mhpm_counter_num, bool rv32b_enabled);

void early_interrupt_handle();

Expand Down
8 changes: 4 additions & 4 deletions dv/uvm/core_ibex/riscv_dv_extension/ml_testlist.yaml
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Expand Up @@ -80,7 +80,7 @@
+disable_compressed_instr=0
+randomize_csr=0
+enable_b_extension=1
+enable_bitmanip_groups=zbb,zb_tmp,zbt,zbs,zbp,zbf,zbe,zbc,zbr
+enable_bitmanip_groups=zbb,zbs,zbp,zbc
+boot_mode=u
+stream_name_0=riscv_load_store_rand_instr_stream
+stream_freq_0=4
Expand Down Expand Up @@ -175,7 +175,7 @@
+disable_compressed_instr=0
+randomize_csr=0
+enable_b_extension=1
+enable_bitmanip_groups=zbb,zb_tmp,zbt,zbs,zbp,zbf,zbe,zbc,zbr
+enable_bitmanip_groups=zbb,zbs,zbp,zbc
+boot_mode=u
+stream_name_0=riscv_load_store_rand_instr_stream
+stream_freq_0=4
Expand Down Expand Up @@ -264,7 +264,7 @@
+disable_compressed_instr=0
+randomize_csr=1
+enable_b_extension=1
+enable_bitmanip_groups=zbb,zb_tmp,zbt,zbs,zbp,zbf,zbe,zbc,zbr
+enable_bitmanip_groups=zbb,zbs,zbp,zbc
+boot_mode=u
+stream_name_0=riscv_load_store_rand_instr_stream
+stream_freq_0=4
Expand Down Expand Up @@ -349,7 +349,7 @@
+disable_compressed_instr=0
+randomize_csr=0
+enable_b_extension=1
+enable_bitmanip_groups=zbb,zb_tmp,zbt,zbs,zbp,zbf,zbe,zbc,zbr
+enable_bitmanip_groups=zbb,zbs,zbp,zbc
+boot_mode=u
+stream_name_0=riscv_load_store_rand_instr_stream
+stream_freq_0=4
Expand Down
27 changes: 3 additions & 24 deletions dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
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Expand Up @@ -1108,9 +1108,8 @@
PMPEnable: 1
timeout_s: 300

# Both an updated compiler and ISS are required to verify the bitmanip v.1.00
# and draft v.0.93 extensions. For now, disable the bitmanip tests.
# For details, refer to https://github.com/lowRISC/ibex/issues/1470
# Ibex implements only the ratified v1.00 Zba/Zbb/Zbc/Zbs extensions plus the
# ratified Zbkb/Zbkx crypto sub-extensions
- test: riscv_bitmanip_full_test
desc: >
Random instruction test with supported B extension instructions in full configuration
Expand All @@ -1121,28 +1120,10 @@
+enable_zbb_extension=1
+enable_zbc_extension=1
+enable_zbs_extension=1
+enable_b_extension=1
+enable_bitmanip_groups=zbe,zbf,zbp,zbr,zbt
rtl_test: core_ibex_base_test
rtl_params:
RV32B: "ibex_pkg::RV32BFull"

- test: riscv_bitmanip_otearlgrey_test
desc: >
Random instruction test with supported B extension instructions in OTEarlGrey configuration
iterations: 10
gen_test: riscv_rand_instr_test
gen_opts: >
+enable_zba_extension=1
+enable_zbb_extension=1
+enable_zbc_extension=1
+enable_zbs_extension=1
+enable_b_extension=1
+enable_bitmanip_groups=zbf,zbp,zbr,zbt
rtl_test: core_ibex_base_test
rtl_params:
RV32B: ["ibex_pkg::RV32BFull", "ibex_pkg::RV32BOTEarlGrey"]

- test: riscv_bitmanip_balanced_test
desc: >
Random instruction test with supported B extension instructions in balanced configuration
Expand All @@ -1152,8 +1133,6 @@
+enable_zba_extension=1
+enable_zbb_extension=1
+enable_zbs_extension=1
+enable_b_extension=1
+enable_bitmanip_groups=zbf,zbt
Comment thread
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rtl_test: core_ibex_base_test
rtl_params:
RV32B: ["ibex_pkg::RV32BFull", "ibex_pkg::RV32BOTEarlGrey", "ibex_pkg::RV32BBalanced"]
RV32B: ["ibex_pkg::RV32BFull", "ibex_pkg::RV32BBalanced"]
7 changes: 2 additions & 5 deletions dv/uvm/core_ibex/scripts/ibex_cmd.py
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Expand Up @@ -101,11 +101,8 @@ def get_isas_for_config(cfg: Config) -> Tuple[str, str]:

bitmanip_mapping = {
'ibex_pkg::RV32BNone': [],
'ibex_pkg::RV32BBalanced': ['Zba', 'Zbb', 'Zbs', 'XZbf', 'XZbt'],
'ibex_pkg::RV32BOTEarlGrey': ['Zba', 'Zbb', 'Zbc', 'Zbs',
'XZbf', 'XZbp', 'XZbr', 'XZbt'],
'ibex_pkg::RV32BFull': ['Zba', 'Zbb', 'Zbc', 'Zbs',
'XZbe', 'XZbf', 'XZbp', 'XZbr', 'XZbt']
'ibex_pkg::RV32BBalanced': ['Zba', 'Zbb', 'Zbs'],
'ibex_pkg::RV32BFull': ['Zba', 'Zbb', 'Zbc', 'Zbs', 'Zbkb', 'Zbkx']
}

bitmanip_isa = bitmanip_mapping.get(cfg.rv32b)
Expand Down
6 changes: 2 additions & 4 deletions dv/uvm/core_ibex/tests/core_ibex_base_test.sv
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Expand Up @@ -74,11 +74,9 @@ class core_ibex_base_test extends uvm_test;
RV32BNone:
;
RV32BBalanced:
isa = {isa, "_Zba_Zbb_Zbs_XZbf_XZbt"};
RV32BOTEarlGrey:
isa = {isa, "_Zba_Zbb_Zbc_Zbs_XZbf_XZbp_XZbr_XZbt"};
isa = {isa, "_Zba_Zbb_Zbs"};
RV32BFull:
isa = {isa, "_Zba_Zbb_Zbc_Zbs_XZbe_XZbf_XZbp_XZbr_XZbt"};
isa = {isa, "_Zba_Zbb_Zbc_Zbs_Zbkb_Zbkx"};
endcase

return isa;
Expand Down
10 changes: 3 additions & 7 deletions examples/simple_system/ibex_simple_system.cc
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Expand Up @@ -50,15 +50,11 @@ std::string SimpleSystem::GetIsaString() const {
break;

case 1: // RV32BBalanced
extensions += "_Zba_Zbb_Zbs_XZbf_XZbt";
extensions += "_Zba_Zbb_Zbs";
break;

case 2: // RV32BOTEarlGrey
extensions += "_Zba_Zbb_Zbc_Zbs_XZbf_XZbp_XZbr_XZbt";
break;

case 3: // RV32BFull
extensions += "_Zba_Zbb_Zbc_Zbs_XZbe_XZbf_XZbp_XZbr_XZbt";
case 2: // RV32BFull
extensions += "_Zba_Zbb_Zbc_Zbs_Zbkb_Zbkx";
break;
}

Expand Down
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