[sram_ctrl] Add support non-power-of-2 memory sizes - #30960
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This parameter got added in 6b1b90c and to support non-power-of-2 memory sizes in SRAM_CTRL, it needs to be forwarded through the racl variant of this module. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit extends the RTL and the DV of SRAM_CTRL to support non-power-of-2 memory sizes. The RTL changes are minimal, most of the changes have already been done as part of prim_ram_1p_scr, see commit 071e0be. Most of the DV changes are related to: 1. Specifying the memory size as number of bytes rather than by defining the number of address bits, 2. correcting the prediction for accesses to unimplemented addresses in in the range [MemDepth * 4 : 2 ** AddrWidth - 1), 3. not triggering accesses to unimplemented addresses for throughput tests as they have a different timing which is harder to predict, 4. extending the minimal a_valid length before retracting a request for the access_during_key_req sequence to avoid signaling delayed out-of-range-access errors. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This configurations is suitable for checking non-power-of-2 sized SRAM_CTRL configurations. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
Since we taped out Earlgrey-PROD and later signed of SRAM_CTRL at D3 in lowRISC#22654, this block experienced some changes which should be reflected in the version number. While some changes are transparent to software (switch to wider internal LFSR, support for RAM tiling), others are software visible but backwards compatible (parameterizable support for RACL, parameterizable support for correcting single-bit ECC errors, support for parameterizing the number of outstanding TLUL transactions, support for non-power-of-2 memory sizes incl. address and data scrambling). This justifies a minor version increase and we may need further changes before the next signoff. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
vogelpi
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andreaskurth,
hcallahan-lowrisc,
nasahlpa,
rswarbrick and
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hcallahan-lowrisc
August 7, 2026 14:43
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CHANGE AUTHORIZED: hw/ip/sram_ctrl/data/sram_ctrl.hjson Version increase to reflect implemented changes since the last tapeout and signoff. CHANGE AUTHORIZED: hw/ip/sram_ctrl/rtl/sram_ctrl.sv Minimal RTL change to pass through an SV parameter for the tlul_adapter_sram module. |
thommythomaso
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Aug 10, 2026
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Commit 071e0be already added support for non-power-of-2 memory sizes to the scrambling primitive (prim_ram_1p_scr) and commit 912cedf added the same feature to ROM_CTRL. This now enables it for SRAM_CTRL.
We'll need this for the CHERIoT Memory Subsystem HWIP for Gen2.