ToughC5 fixes: SPI DMA on AHB_DMA, internal I2C on the low power port, touch retries

[ainyan03]

Bring-up fixes and tuning for the M5Stack ToughC5 (ESP32-C5). Four commits:

• Report the last reading when Touch_CHSC6540 runs out of retries — while a finger is moving no two consecutive reads agree, so the retries ran out and the function reported "no touch": drags and flicks kept breaking up mid-gesture. Adopt the most recent reading, the way Touch_FT5x06 already does; a frame whose coordinate payload could not be read is dropped instead of turning into a touch at (0,0). The code path is shared by every board with this controller.
• Write the DMA descriptor address where AHB_DMA (C5/C61) expects it — this generation dropped the descriptor address bits from OUT_LINK and reads them from a separate OUT_LINK_ADDR_CHn register, so the old OR-into-START write was silently ignored and the first DMA transfer hung. Reuses the two-register path already needed on the P4 (AXI_DMA); the H4, whose AHB_DMA lays these registers out differently, keeps the old path.
• Drive the ToughC5 internal I2C devices on the low power port — the internal bus (SDA=G2 / SCL=G3) sits exactly on the C5's fixed LP_I2C pads; Port A is a level-shifted branch of the same bus, so moving the backlight / touch / post-detection bus there leaves the C5's single high power I2C controller entirely free, and on Arduino builds takes the internal devices off TwoWire. On an SDK without the low power support (pre-5.4 ESP-IDF) everything stays on the high power port.
• Raise the ToughC5 SPI write clock to 40MHz — the rate the same ILI9342 panel already runs at on the Core2 and Tough.

Verified on the actual board (display, backlight, touch, DMA transfers). The low power port commit pairs with m5stack/M5Unified#296 (In_I2C on the same port); the two should land together.

[Copilot]

Pull request overview

Bring-up fixes for the M5Stack ToughC5 (ESP32-C5), addressing touch stability during motion, ESP32-C5/C61 SPI DMA descriptor programming, internal I2C routing to the low-power controller, and increasing the ToughC5 SPI write clock.

Changes:

• Switch ToughC5 internal I2C (G2/G3) to the LP_I2C port when supported (ESP-IDF ≥ 5.4 + i2c_master driver), keeping HP I2C0 free for the external bus.
• Improve CHSC6540 touch behavior by dropping frames with incomplete coordinate payload reads and by returning the most recent reading when retries are exhausted (instead of reporting “no touch”).
• Update ESP32-C5/C61 SPI DMA setup to write the DMA descriptor address to the dedicated OUT_LINK_ADDR register (matching AHB_DMA behavior), and increase ToughC5 SPI write frequency to 40 MHz.

Reviewed changes

Copilot reviewed 4 out of 4 changed files in this pull request and generated no comments.

File	Description
src/M5GFX.cpp	Routes ToughC5 internal I2C to LP_I2C when available; bumps ToughC5 SPI write clock; uses selected I2C port for touch config.
src/lgfx/v1/touch/Touch_CHSC6540.cpp	Makes touch reads resilient to motion by avoiding “no touch” on retry exhaustion and dropping incomplete frames.
src/lgfx/v1/platforms/esp32/Bus_SPI.hpp	Extends DMA “second register” support to ESP32-C5/C61 for descriptor address programming.
src/lgfx/v1/platforms/esp32/Bus_SPI.cpp	Implements ESP32-C5/C61 AHB_DMA OUT_LINK_ADDR register writes for DMA descriptor address.

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