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Turn on the RRAM instruction cache and publish the real core clock #7

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Turn on the RRAM instruction cache and publish the real core clock #7

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bd449ef
Publish the core clock SystemInit selects, and scale micros() by it
andyshinn Sep 10, 2026
c8ba60b
Turn the RRAM instruction cache on in Reset_Handler
cvaldess Oct 15, 2026
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3 changes: 2 additions & 1 deletion cores/nRF5/delay.h
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Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,8 @@ static inline uint32_t micros( void ) __attribute__((always_inline));
static inline uint32_t micros( void )
{
// Use DWT cycle count if it is enabled, otherwise use rtos tick
return dwt_enabled() ? (DWT->CYCCNT / 64) : tick2us(xTaskGetTickCount());
return dwt_enabled() ? (DWT->CYCCNT / (SystemCoreClock / 1000000UL))
: tick2us(xTaskGetTickCount());
}

/**
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10 changes: 10 additions & 0 deletions cores/nRF5/startup_nrf54l15.S
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Expand Up @@ -347,6 +347,16 @@ LoopClearBss:

RunMain:
bl SystemInit

/* SystemCoreClock starts at its 64 MHz default, but SystemInit has set the
* PLL to 128 MHz. Correct it before global constructors can time anything. */
bl SystemCoreClockUpdate

/* The RRAM cache is off after reset. On before the global constructors, so all
* code runs cached, which is also what nrfx_coredep_delay_us() is costed for
* (3 cycles per loop iteration; about 8 from RRAM). */
bl nrf54_cache_enable

bl __libc_init_array
cpsie i
bl main
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7 changes: 7 additions & 0 deletions cores/nRF5/wiring.c
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Expand Up @@ -19,6 +19,7 @@

#include "Arduino.h"
#include "nrf.h"
#include "nrf_cache.h"
#include "nrf_nvic.h"
#include "sd_isr.h"

Expand All @@ -32,6 +33,12 @@ nrf_nvic_state_t nrf_nvic_state;
uint32_t bootloaderVersion = 0;
static uint32_t _reset_reason = 0;

// Called from Reset_Handler (startup_nrf54l15.S), before the global constructors
void nrf54_cache_enable( void )
{
nrf_cache_enable(NRF_ICACHE);
}

void init( void )
{
_reset_reason = NRF_RESET->RESETREAS;
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