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1. DSP48A1 DSP48A1 Public

   Behavioral Verilog implementation of the Xilinx DSP48A1 DSP slice, featuring an 18×18 multiplier, pre-adder/subtracter, configurable pipeline registers, and cascade I/O. Synthesized and constrained…

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2. SPI-Slave-with-Single-Port-RAM SPI-Slave-with-Single-Port-RAM Public

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3. Pipelined-32-bit-CPU Pipelined-32-bit-CPU Public

   Full 6-stage pipelined CPU implemented in VHDL with a custom ISA, hardware interrupt support, 2-bit dynamic branch predictor, forwarding unit, and hazard detection. Includes a Python assembler and …

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4. COMPASS-AI-travel-planner COMPASS-AI-travel-planner Public

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5. CNN-Accelerator CNN-Accelerator Public

   FPGA-based NxN CNN convolution accelerator for the IEEE SSCS Egypt Chapter 2026 Student Design Competition — fully pipelined Verilog datapath, multi-kernel support, ReLU, Python golden-model verifi…

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6. UVM-FIFO-Verification UVM-FIFO-Verification Public

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