Ndh/metro pre work

.github/filters.yml

@@ -30,5 +30,11 @@ cosmo_hp:
 cosmo_seq:
   - 'hdl/projects/cosmo_seq/**/*'
 
+# metro_seq depends on cosmo_seq's shared subsystems, so a change there has to
+# rebuild metro too.
+metro_seq:
+  - 'hdl/projects/metro_seq/**/*'
+  - 'hdl/projects/cosmo_seq/**/*'
+
 cosmo_ignition:
   - 'hdl/projects/cosmo_ignition/**/*'

.gitignore

@@ -51,4 +51,4 @@ vivado*.str
 **/*.svg.bkp
 
 # cobble local env
-BUILD.vars
+BUILD.vars

cos_soak_100.json

@@ -0,0 +1,53 @@
+{
+  "seed": 478,
+  "steps": [
+    {
+      "divisor": 2,
+      "freq_mhz": 100.0,
+      "ok": true,
+      "udp_timeouts_retried": 9,
+      "phases": {
+        "A_const_reads": {
+          "ok": true,
+          "values": [
+            "0x000001de"
+          ]
+        },
+        "B_scratch": {
+          "ok": true,
+          "patterns": 68,
+          "mismatches": []
+        },
+        "C_stress": {
+          "ok": true,
+          "write_burst": 1024,
+          "read_words": 1024,
+          "mismatches": []
+        },
+        "D_soak": {
+          "ok": true,
+          "ops": 14969449,
+          "mismatches": []
+        },
+        "E_throughput": {
+          "ok": true,
+          "wire_write_MBps": 1.228,
+          "wire_read_MBps": 1.003,
+          "single_read_us": 226.7,
+          "fmc_read_MBps": 11.41,
+          "fmc_read_ns_per_word": 351,
+          "fmc_read_fixed_ns_per_word": 309,
+          "fmc_write_MBps": 50.17,
+          "fmc_write_ns_per_word": 80,
+          "note": "fmc_* numbers are bus line rate (delta-timed block ops); wire_* include per-word network cost and are insensitive to the FMC clock"
+        }
+      },
+      "btr1": "0x0010ffff",
+      "clkdiv_verified": true,
+      "sp_ticks_before": 63172,
+      "sp_ticks_after": 3664254,
+      "sp_rebooted": false
+    }
+  ],
+  "restored_baseline_ok": true
+}

cos_soak_100_26p25.json

@@ -0,0 +1,53 @@
+{
+  "seed": 478,
+  "steps": [
+    {
+      "divisor": 2,
+      "freq_mhz": 100.0,
+      "ok": true,
+      "udp_timeouts_retried": 9,
+      "phases": {
+        "A_const_reads": {
+          "ok": true,
+          "values": [
+            "0x000001de"
+          ]
+        },
+        "B_scratch": {
+          "ok": true,
+          "patterns": 68,
+          "mismatches": []
+        },
+        "C_stress": {
+          "ok": true,
+          "write_burst": 1024,
+          "read_words": 1024,
+          "mismatches": []
+        },
+        "D_soak": {
+          "ok": true,
+          "ops": 14923578,
+          "mismatches": []
+        },
+        "E_throughput": {
+          "ok": true,
+          "wire_write_MBps": 1.224,
+          "wire_read_MBps": 0.997,
+          "single_read_us": 226.8,
+          "fmc_read_MBps": 11.39,
+          "fmc_read_ns_per_word": 351,
+          "fmc_read_fixed_ns_per_word": 309,
+          "fmc_write_MBps": 49.98,
+          "fmc_write_ns_per_word": 80,
+          "note": "fmc_* numbers are bus line rate (delta-timed block ops); wire_* include per-word network cost and are insensitive to the FMC clock"
+        }
+      },
+      "btr1": "0x0010ffff",
+      "clkdiv_verified": true,
+      "sp_ticks_before": 48439,
+      "sp_ticks_after": 3649492,
+      "sp_rebooted": false
+    }
+  ],
+  "restored_baseline_ok": true
+}

hdl/ip/vhd/espi/espi_target_top.vhd

@@ -20,6 +20,16 @@ use work.link_layer_pkg.all;
 use work.axil15x32_pkg.all;
 
 entity espi_target_top is
+    generic (
+        -- Whether this instance can ever forward SAFS flash writes and
+        -- erases. False strips the ability out of the build; true still
+        -- leaves it gated by the flash_write_enable control bit, which
+        -- resets to off. Refused writes and erases get an unsuccessful
+        -- completion.
+        FLASH_WRITES_ALLOWED : boolean := false;
+        -- Whether to keep the 4k entry post code buffer, see espi_regs.
+        POST_CODE_BUFFER_ENABLED : boolean := true
+    );
     port (
         clk   : in    std_logic;
         reset : in    std_logic;
@@ -43,6 +53,10 @@ entity espi_target_top is
         flash_rfifo_rdack : out std_logic;
         flash_rfifo_rempty: in std_logic;
         flash_fifo_clear : out std_logic;
+        -- Write payload FIFO, host to flash. Only ever written on an
+        -- instance built with FLASH_WRITES_ALLOWED; leave open otherwise.
+        flash_wfifo_data : out std_logic_vector(7 downto 0);
+        flash_wfifo_write : out std_logic;
         -- Interfaces to the UART block
         to_sp_uart_data : out std_logic_vector(7 downto 0);
         to_sp_uart_valid: out std_logic;
@@ -66,6 +80,8 @@ architecture rtl of espi_target_top is
     signal flash_np_free  : std_logic;
     signal flash_c_avail : std_logic;
     signal flash_channel_enable : boolean;
+    signal flash_write_enable : std_logic;
+    signal flash_writes_permitted : std_logic;
     signal dbg_chan : dbg_chan_t;
     signal spec_regs : spec_regs_t;
     signal response_done : boolean;
@@ -251,13 +267,17 @@ begin
    chip_sel_active <= not txn_csn;
     -- system (axi-lite) register block
    espi_sys_regs_inst: entity work.espi_regs
+    generic map(
+       POST_CODE_BUFFER_ENABLED => POST_CODE_BUFFER_ENABLED
+    )
     port map(
        clk => clk,
        reset => reset,
        axi_if => axi_if,
        stuff_fifo => stuff_fifo,
        stuff_wds => stuff_wds,
        dbg_chan => dbg_chan,
+       flash_write_enable => flash_write_enable,
        spec_regs_view => spec_regs,
        post_code => post_code,
        post_code_valid => post_code_valid,
@@ -286,6 +306,7 @@ begin
             data_to_host    => txn_resp,
             data_from_host  => txn_cmd,
             alert_needed    => alert_needed,
+            flash_writes_allowed => flash_writes_permitted,
             flash_req       => flash_req,
             flash_resp      => flash_resp,
             response_done   => response_done,
@@ -320,6 +341,11 @@ begin
             oob_enabled    => oob_enabled
         );
 
+    -- Both halves of the write permission have to agree; the generic keeps
+    -- the register bit from doing anything on an instance that must never
+    -- let the host write.
+    flash_writes_permitted <= '1' when FLASH_WRITES_ALLOWED and flash_write_enable = '1' else '0';
+
     -- flash access channel logic
    flash_channel_inst: entity work.flash_channel
     port map(
@@ -335,7 +361,9 @@ begin
        flash_cfifo_write => flash_cfifo_write,
        flash_rfifo_data => flash_rfifo_data,
        flash_rfifo_rdack => flash_rfifo_rdack,
-       flash_rfifo_rempty => flash_rfifo_rempty
+       flash_rfifo_rempty => flash_rfifo_rempty,
+       flash_wfifo_data => flash_wfifo_data,
+       flash_wfifo_write => flash_wfifo_write
    );
 
    -- uart channel logic