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Add Armv8.1-M targets for Cortex-M55 and Cortex-M85 based microcontrollers #162519
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0802593
Add Armv8.1-M targets.
jonathanpallant 1f797a7
Add new Armv8.1-M targets to `ignore_target_names`
jonathanpallant 35f53f8
Remove DSP column from Armv8.1-M platform page
jonathanpallant 2efae29
Correct target tier for Armv8.1-M targets
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28 changes: 28 additions & 0 deletions
28
compiler/rustc_target/src/spec/targets/thumbv81m_main_none_eabi.rs
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,28 @@ | ||
| // Targets the Cortex-M55/-M85 processors (Armv8.1-M Mainline architecture profile), | ||
| // without the Floating Point extension. | ||
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| use crate::spec::{Arch, CfgAbi, FloatAbi, Target, TargetMetadata, TargetOptions, base}; | ||
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| pub(crate) fn target() -> Target { | ||
| Target { | ||
| llvm_target: "thumbv8.1m.main-none-eabi".into(), | ||
| metadata: TargetMetadata { | ||
| description: Some("Bare ARMv8.1-M Mainline with DSP and LOB".into()), | ||
| tier: Some(3), | ||
| host_tools: Some(false), | ||
| std: Some(false), | ||
| }, | ||
| pointer_width: 32, | ||
| data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), | ||
| arch: Arch::Arm, | ||
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| options: TargetOptions { | ||
| cfg_abi: CfgAbi::Eabi, | ||
| llvm_floatabi: Some(FloatAbi::Soft), | ||
| // We assume you have the DSP and LOB extensions (which are technically optional). | ||
| features: "+dsp,+lob".into(), | ||
| max_atomic_width: Some(32), | ||
| ..base::arm_none::opts() | ||
| }, | ||
| } | ||
| } |
31 changes: 31 additions & 0 deletions
31
compiler/rustc_target/src/spec/targets/thumbv81m_main_none_eabihf.rs
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,31 @@ | ||
| // Targets the Cortex-M55/-M85 processors (Armv8.1-M Mainline architecture profile), | ||
| // with the Floating Point extension. | ||
| // | ||
| // It does not assume you have M-Profile Vector Extensions (aka Helium) | ||
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| use crate::spec::{Arch, CfgAbi, FloatAbi, Target, TargetMetadata, TargetOptions, base}; | ||
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| pub(crate) fn target() -> Target { | ||
| Target { | ||
| llvm_target: "thumbv8.1m.main-none-eabihf".into(), | ||
| metadata: TargetMetadata { | ||
| description: Some("Bare ARMv8.1-M Mainline, hardfloat, with DSP and LOB".into()), | ||
| tier: Some(3), | ||
| host_tools: Some(false), | ||
| std: Some(false), | ||
| }, | ||
| pointer_width: 32, | ||
| data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), | ||
| arch: Arch::Arm, | ||
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| options: TargetOptions { | ||
| cfg_abi: CfgAbi::EabiHf, | ||
| llvm_floatabi: Some(FloatAbi::Hard), | ||
| // The Cortex-M55 and Cortex-M85 both have FPv5-D16 double-precision FPUs | ||
| // We also assume you have the DSP and LOB extensions (which are technically optional). | ||
| features: "+dsp,+fp-armv8d16,+lob".into(), | ||
| max_atomic_width: Some(32), | ||
| ..base::arm_none::opts() | ||
| }, | ||
| } | ||
| } | ||
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111 changes: 111 additions & 0 deletions
111
src/doc/rustc/src/platform-support/thumbv8.1m.main-none-eabi.md
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| @@ -0,0 +1,111 @@ | ||
| # `thumbv8.1m.main-none-eabi` and `thumbv8.1m.main-none-eabihf` | ||
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| * **Tier: 3** | ||
| * **Library Support:** core and alloc (bare-metal, `#![no_std]`) | ||
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| Bare-metal target for CPUs in the Mainline [Armv8.1-M] architecture family, | ||
| supporting a subset of the [T32 ISA][t32-isa]. | ||
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| Processors in this family include the: | ||
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| * [Arm Cortex-M55][cortex-m55] | ||
| * [Arm Cortex-M85][cortex-m85] | ||
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| This target assumes your processor supports the *DSP* and *Low-Overhead Branch* extensions. | ||
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| See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all | ||
| `arm-none-eabi` targets, in particular the difference between the `eabi` and | ||
| `eabihf` ABI. | ||
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| [t32-isa]: https://developer.arm.com/Architectures/T32%20Instruction%20Set%20Architecture | ||
| [Armv8.1-M]: https://developer.arm.com/documentation/ddi0553/latest/ | ||
| [cortex-m55]: https://developer.arm.com/Processors/Cortex-M55 | ||
| [cortex-m85]: https://developer.arm.com/Processors/Cortex-M85 | ||
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| ## Target maintainers | ||
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| - [Rust Embedded Devices Working Group Arm Team](https://github.com/rust-embedded/wg?tab=readme-ov-file#the-arm-team) | ||
| - [arm-maintainers][arm_maintainers] ([rust@arm.com][arm_email]) | ||
| - Use `@rustbot ping arm-maintainers` to ping us | ||
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| [arm_maintainers]: https://github.com/rust-lang/team/blob/master/teams/arm-maintainers.toml | ||
| [arm_email]: mailto:rust@arm.com | ||
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| ## Target CPU and Target Feature options | ||
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| See [the bare-metal Arm | ||
| docs](arm-none-eabi.md#target-cpu-and-target-feature-options) for details on how | ||
| to use these flags. | ||
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| ### Table of supported CPUs for `thumbv8.1m.main-none-eabi` | ||
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| | CPU | FPU | MVE | Target CPU | Target Features | | ||
| | ----------- | --- | --------- | ------------- | --------------------- | | ||
| | Unspecified | No | No | None | None | | ||
| | Cortex-M55 | No | No | `cortex-m55` | `-fpregs,-mve` | | ||
| | Cortex-M55 | DP | No | `cortex-m55` | `-mve` | | ||
| | Cortex-M55 | No | Int | `cortex-m55` | `-fpregs,-mve.fp,+mve`| | ||
| | Cortex-M55 | DP | Int | `cortex-m55` | `-mve.fp` | | ||
| | Cortex-M55 | DP | Int+Float | `cortex-m55` | None | | ||
| | Cortex-M85 | No | No | `cortex-m85` | `-fpregs,-mve` | | ||
| | Cortex-M85 | DP | No | `cortex-m85` | `-mve` | | ||
| | Cortex-M85 | No | Int | `cortex-m85` | `-fpregs,-mve.fp,+mve`| | ||
| | Cortex-M85 | DP | Int | `cortex-m85` | `-mve.fp` | | ||
| | Cortex-M85 | DP | Int+Float | `cortex-m85` | None | | ||
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| ### Table of supported CPUs for `thumbv8.1m.main-none-eabihf` | ||
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| | CPU | FPU | MVE | Target CPU | Target Features | | ||
| | ----------- | --- | --------- | ------------- | --------------------- | | ||
| | Unspecified | DP | No | None | None | | ||
| | Cortex-M55 | DP | No | `cortex-m55` | `-mve` | | ||
| | Cortex-M55 | DP | Int | `cortex-m55` | `-mve.fp` | | ||
| | Cortex-M55 | DP | Int+Float | `cortex-m55` | None | | ||
| | Cortex-M85 | DP | No | `cortex-m85` | `-mve` | | ||
| | Cortex-M85 | DP | Int | `cortex-m85` | `-mve.fp` | | ||
| | Cortex-M85 | DP | Int+Float | `cortex-m85` | None | | ||
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| *Technically* you can use this hard-float ABI on a CPU which has no FPU but does | ||
| have Integer MVE, because MVE provides the same set of registers as the FPU | ||
| (including `s0` and `d0`). The particular set of flags that might enable this | ||
| unusual scenario are currently not recorded here. | ||
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| <div class="warning"> | ||
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| Never use the `-fpregs` *target-feature* with the `thumbv8.1m.main-none-eabihf` | ||
| target as it will cause compilation units to have different ABIs, which is | ||
| unsound. | ||
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| </div> | ||
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| ### M-Profile Vector Extensions | ||
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| The M-Profile Vector Extensions (also known as MVE, and marketed as "Helium") allow the processor to perform SIMD operations. MVE is available in either *integer-only* or *integer-and-float* variants. This target does not assume MVE support by default, but it can be added by specifying a *target-cpu*, or using certain *target-features* (noted below). | ||
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| ### Arm Cortex-M55 | ||
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| The target CPU is `cortex-m55`. | ||
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| * Has an optional double-precision FPU that also supports half-precision FP16 | ||
| values | ||
| * support is enabled by default with this *target-cpu* the 'eabihf' target | ||
| * disable support using the `-fpregs` *target-feature* (`eabi` only) | ||
| * Has optional support for M-Profile Vector Extensions | ||
| * The appropriate feature for the MVE is either `mve` (integer) or `mve.fp` | ||
| (float) | ||
| * `mve.fp` is enabled by default on this *target-cpu* | ||
| * disable using `-mve.fp` (disable float MVE) or `-mve` (disable all MVE) | ||
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| ### Arm Cortex-M85 | ||
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| The target CPU is `cortex-m85`. | ||
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| * Has an optional double-precision FPU that also supports half-precision FP16 | ||
| values | ||
| * support is enabled by default with this *target-cpu* or the 'eabihf' target | ||
| * disable support using the `-fpregs` *target-feature* (`eabi` only) | ||
| * Has optional support for M-Profile Vector Extensions | ||
| * The appropriate feature for the MVE is either `mve` (integer) or `mve.fp` | ||
| (float) | ||
| * `mve.fp` is enabled by default on this *target-cpu* | ||
| * disable using `-mve.fp` (disable float MVE) or `-mve` (disable all MVE) |
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