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plawk: array-element lines from one structural .stache template (template PR 4) - #4350

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@s243a s243a commented Oct 5, 2026

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Template PR 4 of docs/design/PLAN_TEMPLATE_REFACTOR.md (§2.3-A; decision 5: plawk is the first pattern_stache consumer on this line). It applies the owner's point directly: many literal cases that share a shape collapse into one structural case.

What

examples/plawk/codegen/llvm/templates/assoc_elem.ll.stache replaces 20 format/2 strings in plawk_native_codegen.pl with 3 structural cases:

{{match op}}
{{case elem_print(T, Key, Kind)}}  call void @wam_assoc_{{Kind}}_print(... %plawk_assoc_table_{{T}}, i64 {{Key}})
{{case elem_write(Res, T, Key, V, Fn, i64)}}  {{Res}} = call i64 @wam_assoc_i64_{{Fn}}(... i64 {{Key}}, i64 {{V}})
{{case elem_write(Res, T, Key, V, Fn, f64)}}  {{Res}} = call double @wam_assoc_f64_{{Fn}}(... i64 {{Key}}, double {{V}})
{{/match}}
  • elem_print serves the i64, f64 and str printers. The runtime names are uniform, so the kind is a value, not a case.

  • elem_write, one case per encoding, serves every element write:

    • 11 increments;
    • 2 f64 add-assigns;
    • 4 sets (arrays PR 2b);
    • the mixed-route writer.

    Only the LLVM type word differs between the two encodings. The plan's sketch had four cases; set joined the write family.

  • Prolog keeps every decision: the kind, the SSA names, and the op → runtime-function map (plawk_assoc_write_fn/3; the runtime spells i64 add inc). The template only spells the line.

  • A new encoding would need zero new cases for print and one for write.

  • examples/plawk/codegen/llvm/plawk_stache.pl provides plawk_render_stache(+Name, +Op, -Line):

    • Op must be ground;
    • templates are cached per process;
    • whitespace policy, which the SPEC leaves to the caller: one case per line in the file, surrounding newlines stripped, exactly one line required;
    • a load-time preflight renders every case against its expected line.

Verification

  • IR corpus: ir_corpus.pl dump + diff over all 2573 corpus programs (400 declines), feature line vs this branch: 0 changed. The corpus exercises every case, about 950 rendered lines:
    • prints: i64 337, f64 12, str 60;
    • writes: i64 inc 492, f64 add 27, i64 set 21, f64 set 7.
  • plawk sweep: 223/223, including the new tests/test_plawk_stache.pl (5). It covers the preflight, one print case for all kinds, the write cases, and the error cases (non-ground and unmatched ops).

Next

  • Arrays PR 3: element reads in conditions, arithmetic and END. It can write its element lines through this template from the start.

🤖 Generated with Claude Code

https://claude.ai/code/session_01QrQistdoYMNpVtecwims6g

…late PR 4)

The plawk .stache pilot -- the first pattern_stache consumer on this line
(PLAN_TEMPLATE_REFACTOR decision 5). templates/assoc_elem.ll.stache has three
structural cases replacing 20 format/2 strings in plawk_native_codegen.pl:

- elem_print(T, Key, Kind): the i64 / f64 / str element printers (the runtime
  names are uniform, @wam_assoc_<Kind>_print, so the kind is a value);
- elem_write(Res, T, Key, V, Fn, i64) and its f64 twin: every increment,
  add-assign and set (11 inc, 2 f64 add, 4 set) and the mixed-route writer;
  only the LLVM type word differs per encoding.

Prolog keeps every decision -- the kind, the SSA names, the op -> runtime
function map (plawk_assoc_write_fn/3; the runtime spells i64 add `inc`).
plawk_stache.pl renders a ground term to one IR line: templates cached per
process, surrounding newlines stripped and exactly one line required, and a
load-time preflight that renders every case against its expected line.

Verified: ir_corpus dump + diff over all 2573 corpus programs (400
declines): 0 changed. The corpus exercises every case (~950 lines).
tests/test_plawk_stache.pl (5).

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01QrQistdoYMNpVtecwims6g
@s243a
s243a marked this pull request as ready for review October 5, 2026 03:34
@s243a
s243a merged commit 22f1e25 into claude/plawk-llvm-wam-hybrid-p9ujut Oct 5, 2026
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