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1. verified-rv32i verified-rv32i Public

   An RV32I 5-Stage Pipelined Processor with coverage-driven and formal verification, written in SystemVerilog, verified with cocotb, riscv-formal, sby, and mcy

2. pinscribe pinscribe Public

   A programmable protocol emulator and bus sniffer for Jane Street Tiny Tapeout ASIC Competition

   Verilog

3. feeFIFOfum feeFIFOfum Public

   Source code for CppCon 2026 Lightning Talk titled "Fee, FIFO, Fum: When C++ Abstractions Lie about Hardware"

   C++

4. AXI-Stream-FIFO AXI-Stream-FIFO Public

   An Asynchronous AXI4-Stream FIFO in SystemVerilog with a cocotb testbench

   Python

5. RoundRobinUVM RoundRobinUVM Public

   A parameterized round robin arbiter, verified using pyuvm and UVM on EDA Playground

   SystemVerilog