A linux bus interface that lets you change screen brightness, compute captured webcam frames brightness and change screen temperature.
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May 14, 2024 - C
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bus-interface
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Aug 9, 2018 - Verilog
bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications
asic fsm interface architecture rtl verilog peripherals datapath soc testbench lfsr 32-bit 32bit bus-interface asic-design controlpath datapath-design lfsr-algorithm
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May 28, 2024 - Verilog
SystemVerilog model of the Intel 8088 microprocessor bus interfacing to memory and I/O — Moore and Mealy FSM memory/IO modules, SystemVerilog interfaces with modports, a bus-functional model driving encrypted 8088 IP, and a self-checking testbench. Intro to SystemVerilog course project.
fsm rtl microprocessor systemverilog computer-architecture testbench bus-interface questa hardware-design memory-mapped-io intel-8088
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May 26, 2026 - SystemVerilog
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