| Project | Found | Outcome |
|---|---|---|
| LiteDRAM | AXI write responses lost under BREADY backpressure | |
| LiteDRAM | DMA AXI byte addressing and WLAST | |
| LiteEth | ARP cache returning the wrong MAC address | |
| LitePCIe | MSI-X upper address and masked interrupts | |
| Highway | f64 → f32 demotion overflowing on finite values | |
| Z3 | FP subnormal rounded wrong by roundToIntegral |
|
| fast_float | from_chars overwriting output on invalid input |
|
| STP | Nested let scoping |
|
| GTKWave | vcd2lxt2 storing wrong settled values |
|
| tract | Signed division by a power of two rounding negatives | |
| BaseJump STL | bsg_mul_add_unsigned output width |
🫨
Founder of ChipLab
- Washington DC / Northern Virginia
- chiplab.donmakino.com/matrix
- https://orcid.org/0009-0003-9702-8164
- https://chiplab.donmakino.com
- in/nathan-chandrasekar
Highlights
- Pro
Pinned Loading
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verilator/verilator
verilator/verilator PublicVerilator open-source SystemVerilog simulator and lint system
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sonos/tract
sonos/tract PublicTiny, no-nonsense, self-contained, Tensorflow and ONNX inference
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