All workflows

Workflow runs

• CI

  completed successfully:
  CI#1933:Scheduled
  master

  Oct 19, 20263h 19m 32s
  More actions for workflow run 1933

• FPGA Gate

  failed:
  FPGA Gate#43:Manually runbytinebp
  master

  Oct 17, 202616h 58m 24s
  More actions for workflow run 43

• ci: regenerate perf baselines with the pinned toolchain

  completed successfully:
  CI#1932:Commit9dbb69cpushedbyjel221
  mufu

  Oct 16, 202645m 3s
  More actions for workflow run 1932

• fcvt: mark the overflow flag unused when no F2F format is enabled

  failed:
  CI#1931:Commitcd135b1pushedbyjel221
  mufu

  Oct 16, 20263h 53m 21s
  More actions for workflow run 1931

• ci: regenerate perf baselines

  completed successfully:
  CI#1930:Commit344039fpushedbyjel221
  mufu

  Oct 16, 20262h 22m 41s
  More actions for workflow run 1930

• zfhmin: half-precision load/store, move and conversion

  failed:
  CI#1929:Commit0ed20dcpushedbyjel221
  mufu

  Oct 16, 20263h 40m 52s
  More actions for workflow run 1929

• dispatch fix on single-packet inst

  completed successfully:
  CI#1928:Pull request#428openedbyjel221
  fix/lane-dispatch-stale-eop

  Oct 16, 20263h 59m 5s
  More actions for workflow run 1928

• mufu: rcpf, rsqrt, ex2, lg2, sin, cos, tanh

  failed:
  CI#1927:Commit35abdfapushedbyjel221
  mufu

  Oct 16, 20264h 2m 11s
  More actions for workflow run 1927

• dispatch fix on single-packet inst

  completed successfully:
  CI#1926:Commitda2d6d7pushedbyjel221
  fix/lane-dispatch-stale-eop

  Oct 16, 20263h 12m 3s
  More actions for workflow run 1926

• Change Vortex website URL in README

  completed successfully:
  CI#1925:Commit7b67f02pushedbyshin0403
  master

  Oct 15, 202645m 4s
  More actions for workflow run 1925

• FPGA Gate

  cancelled:
  FPGA Gate#42:Manually runbytinebp
  master

  Oct 15, 20261d 0h 0m 6s
  More actions for workflow run 42

• afu: optional single-ID in-order reads on the memory AXI ports

  failed:
  CI#1924:Commitd1e300epushedbyNikhilRout
  feature_mx

  Oct 14, 202615m 3s
  More actions for workflow run 1924

• Apptainer CI

  completed successfully:
  Apptainer CI#110:Scheduled
  master

  Oct 14, 202647m 44s
  More actions for workflow run 110

• ASIC Gate

  completed successfully:
  ASIC Gate#36:Scheduled
  master

  Oct 14, 202645m 39s
  More actions for workflow run 36

• FPGA Gate

  cancelled:
  FPGA Gate#41:Manually runbytinebp
  master

  Oct 13, 20261d 0h 0m 4s
  More actions for workflow run 41

• Rv64 fixes (#427)

  completed successfully:
  CI#1923:Commit942e381pushedbytinebp
  master

  Oct 13, 20264h 39m 5s
  More actions for workflow run 1923

• Rv64 fixes

  completed successfully:
  CI#1922:Pull request#427openedbytinebp
  rv64-fixes

  Oct 13, 20264h 40m 12s
  More actions for workflow run 1922

• ci: re-record the rtlsim perf-gate baselines for the DRAM model

  completed successfully:
  CI#1921:Commitc068ceapushedbytinebp
  rv64-fixes

  Oct 12, 20264h 40m 22s
  More actions for workflow run 1921

• CI

  completed successfully:
  CI#1920:Scheduled
  master

  Oct 12, 20263h 1m 55s
  More actions for workflow run 1920

• simx: model 1R1W LMEM banks

  failed:
  CI#1919:Commit0b75f20pushedbyjel221
  wgdxa2k

  Oct 9, 202610m 29s
  More actions for workflow run 1919

• FPGA Gate

  completed successfully:
  FPGA Gate#40:Manually runbytinebp
  master

  Oct 8, 20265h 46m 44s
  More actions for workflow run 40

• fpga fix

  failed:
  CI#1918:Commitf07c520pushedbyjel221
  wgdxa2k

  Oct 8, 202610m 15s
  More actions for workflow run 1918

• ASIC Gate

  completed successfully:
  ASIC Gate#35:Scheduled
  master

  Oct 8, 202638m 38s
  More actions for workflow run 35

• latest perf udpate

  failed:
  CI#1917:Commit906a96epushedbyjel221
  wgdxa2k

  Oct 8, 202623m 2s
  More actions for workflow run 1917

• cp: tag the low address bits in_global() leaves undecoded

  completed successfully:
  Apptainer CI#109:Commit7fe1936pushedbytinebp
  v3.0

  Oct 7, 20262h 1m 5s
  More actions for workflow run 109