██████╗ ███████╗██╗ ██╗ ██╔═══██╗██╔════╝██║ ██║ ██║ ██║███████╗███████║ ██║ ██║╚════██║██╔══██║ ╚██████╔╝███████║██║ ██║ ╚═════╝ ╚══════╝╚═╝ ╚═╝ OSH-LIBRARY
A growing collection of reusable Verilog hardware cores
OSH-Library is an open collection of parameterized, reusable HDL cores — built for learning, prototyping, and dropping into your own digital design projects. Right now the focus is on cryptographic cores, PRNGs, and small clock-domain-crossing (CDC) building blocks.
Whether you're just getting started with Verilog or you've been doing this for years, contributions are welcome!
Each core in this repo is self-contained — you can explore, simulate, and integrate them one at a time.
- A Verilog simulator (e.g., Icarus Verilog, Verilator, or similar)
- GTKWave or another waveform viewer (optional, for inspecting signals)
- Navigate to the core you're interested in.
- Compile the RTL source alongside its testbench.
- Run the simulation with your simulator of choice.
- Check the logs or waveform to confirm it behaves as expected.
Most cores already include a pre-run simulation log and waveform screenshot in their folder, so you can see expected output before running anything yourself.
- ChaCha20 — stream cipher, verified against RFC 8439 test vectors, includes a technical paper
- Trivium — stream cipher core
All cores here are checked with simulation-based testbenches. Formal verification hasn't been added yet — it's on our roadmap and something we're actively working on. Until then, treat these cores as simulation-verified, not formally proven.
Got a core to add, a bug to report, or an improvement in mind? Check out the Contribution Guidelines or start a Discussion — we'd love to hear from you.
For module requests, ideas, or collaboration, head over to the GitHub Discussions tab.
This project is licensed under the Apache License 2.0 — see LICENSE for details.