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angr
vex
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arm, arm64: return the architectural zero result for integer division by zero
Build
#138:
Pull request
#104
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DORA-B:fix/arm-a-profile-divzero
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x86: preserve ZF across BT-family instructions
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#88
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arm: check SMLAD overflow on final result
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#136:
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#87
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riscv64: do not trap on division by zero (RISC-V defines it)
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#135:
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#84
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x86: fix xadd reg,reg writeback order for the same-register case
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#134:
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#85
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[Review] x86: preserve ZF across BT-family instructions
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#133:
Pull request
#103
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10m 38s
DORA-B:review/pr88-x86-bt-zf-20260924
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[Review] arm: check SMLAD overflow on final result
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#132:
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[Review] x86: fix xadd reg,reg writeback order
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#131:
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DORA-B:review/pr85-x86-xadd-20260924
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[Review] riscv64: handle non-trapping division exceptions
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#130:
Pull request
#100
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11m 56s
DORA-B:review/pr84-riscv64-divzero-20260924
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mips32: Reject MIPS64-only encodings instead of asserting
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#129:
Pull request
#91
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5m 9s
feature/mips64-nodecode
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mips32: Reject MIPS64-only encodings instead of asserting
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feature/mips64-nodecode
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s390x: Sign-extend the BRCTH displacement from 32 bits
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#127:
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#93
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3m 20s
feature/s390x-brcth-displacement
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s390x: Use the 32-bit relative offset helper for BRCTH
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#126:
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feature/s390x-brcth-displacement
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arm: Account for Thumb instruction widths in IT lookback
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#125:
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#92
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3m 6s
feature/thumb-it-lookback-widths
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arm: Account for Thumb instruction widths in IT lookback
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feature/thumb-it-lookback-widths
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x86: decode 16-bit addressing modes correctly
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#123:
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#97
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1m 13s
feature/x86-addr16
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x86: decode 16-bit addressing modes correctly
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feature/x86-addr16
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Add AVX512 lifting support. (#99)
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#121:
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master
master
1m 10s
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riscv64: widen feq/flt results before assigning them to an Ity_I32 temp
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#120:
Pull request
#95
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2m 36s
fix/riscv-fcmp-i1-to-i32
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riscv64: widen feq/flt results to Ity_I32 before assigning them
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arm: Account for Thumb instruction widths in IT lookback
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#118:
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6m 13s
feature/thumb-it-lookback-widths
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arm: Account for Thumb instruction widths in IT lookback
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#117:
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x86: decode 16-bit addressing modes correctly
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feature/x86-addr16
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x86: decode 16-bit addressing modes correctly
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riscv64: widen feq/flt results before assigning them to an Ity_I32 temp
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#114:
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fix/riscv-fcmp-i1-to-i32
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