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1. uart-bram-write-read uart-bram-write-read Public

   UART-controlled 16-bit Block RAM (BRAM) read/write interface on FPGA.

   VHDL

2. uart-transceiver uart-transceiver Public

   A full-duplex parametric UART Transceiver (TX & RX) in VHDL implemented on Basys 3 FPGA

   VHDL

3. digital-stopwatch digital-stopwatch Public

   A 4-digit digital stopwatch (MM:SS) in VHDL on Basys 3 FPGA.

   VHDL

4. debounce-application debounce-application Public

   A parameterizable VHDL debounce filter featuring an FSM and 2-stage synchronizer. Includes Vivado simulation and Basys 3 FPGA hardware verification comparing debounced vs raw inputs.

   VHDL

5. adjustable-led-counter adjustable-led-counter Public

   Configurable frequency LED counter in VHDL with synchronous reset, verified via Vivado testbench and Basys 3 FPGA Board.

   Tcl

6. fpga-image-processing fpga-image-processing Public

   This repository contains the implementation of a real-time image processing system on FPGA. The design applies a Laplacian Edge Detection Filter** to an image stored in Block RAM and displays the r…

   VHDL