FPGA-Based Real-Time Image Processing System

This repository contains the implementation of EHB 436E Experiment 7, a real-time image processing system on FPGA. The design applies a Laplacian Edge Detection Filter to an image stored in Block RAM and displays the result via a VGA Interface (640x480 @ 60Hz).

System Overview

The system implements a complete hardware image processing pipeline. It reads RGB image data, processes it using a 3x3 convolution kernel in real-time, and outputs the detected edges.

• Resolution: 640x480 pixels
• Pixel Clock: 25 MHz
• Filter: Laplacian Kernel (Edge Detection)
• Verification: MATLAB-based co-simulation environment.

Architecture Highlights

The design is modular and fully pipelined:

1. VGA Driver: Generates accurate H-Sync and V-Sync timing signals for 640x480 resolution.
2. Memory Controller (Line Buffering):
   • Implements a smart Circular Buffer mechanism.
   • Uses internal line buffers to store previous rows (N-1, N-2).
   • Constructs a 3x3 sliding window on-the-fly from the streaming data, enabling single-pass convolution.
3. Convolution Unit:
   • Performs signed Multiply-Accumulate (MAC) operations for the Laplacian Kernel.
   • Includes saturation logic to clamp pixel values between 0-15 (4-bit color).
4. Parallel Processing: Red, Green, and Blue channels are processed by independent parallel pipelines for maximum throughput.

Project Structure

• src/: Verilog source codes (VGA driver, Controller, Conv Unit).
• scripts/: MATLAB scripts for data pre-processing and verification.
  • image_to_hex.m: Converts standard images (JPG/PNG) to FPGA-readable .txt hex files.
  • compare_fpga_vs_matlab.m: Compares FPGA simulation output against a software reference model.
• docs/: Detailed experiment report including timing analysis and resource utilization.
• image_proc.tcl: Script to recreate the Vivado project.

How to Run & Verify

This project includes a complete verification flow using MATLAB and Vivado:

1. Pre-Processing (MATLAB)

Run scripts/image_to_hex.m to convert your target image into hex files (red.txt, green.txt, etc.). These files initialize the Block RAM in the simulation.

2. Simulation (Vivado)

Run the behavioral simulation in Vivado. The testbench (top_tb.v) reads the input hex files, processes the frame through the FPGA logic, and writes the output frames to text files.

3. Verification (MATLAB)

Run scripts/compare_fpga_vs_matlab.m. This script:

• Reads the output text files generated by Vivado.
• Reconstructs the image.
• Compares the FPGA result pixel-by-pixel with a software-computed Laplacian result to verify bit-perfect accuracy.

Hardware Utilization

• BRAM: ~79% (Used for storing the 640x480 image).
• LUT: ~11% (Efficient logic usage due to constant coefficient optimization).
• Timing: Validated at 25 MHz with substantial positive slack.

Documentation

For detailed timing diagrams, state machine (FSM) descriptions, and verification results, please refer to the Project Report.

---

Developed for EHB 436E - Digital System Design Applications.