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Fix verilog_reader importing NOR and XNOR assignments as constant zero - #713
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vera-rubin wants to merge 3 commits into
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vera-rubin wants to merge 3 commits into
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lorina dispatches `assign y = ~( a | b );` and `assign y = ~( a ^ b );` to `on_nor` and `on_xnor`, but `verilog_reader` did not override them, so the inherited empty callbacks left the left-hand side undefined and the outputs were later created as constant 0. Add `on_nor` and `on_xnor` following `on_nand`. They negate `create_or` and `create_xor`, since not every network implements `create_nor` or `create_xnor` (e.g. `klut_network`, `mig_network`).
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## master #713 +/- ##
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- Coverage 84.10% 84.06% -0.04%
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Files 191 191
Lines 29579 29606 +27
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+ Hits 24876 24887 +11
- Misses 4703 4719 +16 ☔ View full report in Codecov by Harness. 🚀 New features to boost your workflow:
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Collaborator
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Thank you for the PR. Why don't we use create_nor and create_xnor? Probably we don't need the function description comment for this file. |
mig_network has no create_xnor and klut_network has neither, so fall back to create_not of create_or/create_xor when has_create_nor_v / has_create_xnor_v is false.
Author
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Thanks! Done: it now uses |
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verilog_readerinherits lorina's emptyon_norandon_xnorcallbacks, so parsed output assignments such asassign y = ~(a | b);andassign y = ~(a ^ b);become constant zero.This adds both callbacks with the same module and operand checks as
on_nand. They negatecreate_orandcreate_xorwithcreate_not, preserving operand complements without requiring direct NOR/XNOR methods from every network.Tested against base
1c9c3af6a423f650f654ccec340dae9b93995844in a GCC Debug build. The new MIG regression covers NOR, XNOR, a NAND control, and complemented operands. It fails four of five functional checks before the fix and passes afterward. The fullrun_testssuite passes before and after. The issue reproducer passes after the fix with assertions enabled and disabled.A separate four-expression fixture also checks AIG, XAG, XMG, k-LUT, MuxIG, crossed k-LUT, and buffered crossed k-LUT. Each imports the expected truth tables. Release builds and the other CI toolchains haven't been checked locally.
Fixes #712
ChipLab ref: CLAB-2026-353