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Fix verilog_reader importing NOR and XNOR assignments as constant zero - #713

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vera-rubin wants to merge 3 commits into
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vera-rubin:fix/verilog-reader-nor-xnor
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vera-rubin wants to merge 3 commits into
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vera-rubin:fix/verilog-reader-nor-xnor

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@vera-rubin

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verilog_reader inherits lorina's empty on_nor and on_xnor callbacks, so parsed output assignments such as assign y = ~(a | b); and assign y = ~(a ^ b); become constant zero.

This adds both callbacks with the same module and operand checks as on_nand. They negate create_or and create_xor with create_not, preserving operand complements without requiring direct NOR/XNOR methods from every network.

Tested against base 1c9c3af6a423f650f654ccec340dae9b93995844 in a GCC Debug build. The new MIG regression covers NOR, XNOR, a NAND control, and complemented operands. It fails four of five functional checks before the fix and passes afterward. The full run_tests suite passes before and after. The issue reproducer passes after the fix with assertions enabled and disabled.

A separate four-expression fixture also checks AIG, XAG, XMG, k-LUT, MuxIG, crossed k-LUT, and buffered crossed k-LUT. Each imports the expected truth tables. Release builds and the other CI toolchains haven't been checked locally.

Fixes #712

ChipLab ref: CLAB-2026-353

lorina dispatches `assign y = ~( a | b );` and `assign y = ~( a ^ b );`
to `on_nor` and `on_xnor`, but `verilog_reader` did not override them,
so the inherited empty callbacks left the left-hand side undefined and
the outputs were later created as constant 0.

Add `on_nor` and `on_xnor` following `on_nand`. They negate `create_or`
and `create_xor`, since not every network implements `create_nor` or
`create_xnor` (e.g. `klut_network`, `mig_network`).
@codecov

codecov Bot commented Oct 13, 2026 •

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Codecov Report

❌ Patch coverage is 66.66667% with 7 lines in your changes missing coverage. Please review.
✅ Project coverage is 84.06%. Comparing base (1c9c3af) to head (81bdbf5).

Files with missing lines Patch % Lines
include/mockturtle/io/verilog_reader.hpp 66.66% 7 Missing ⚠️
Additional details and impacted files
@@            Coverage Diff             @@
##           master     #713      +/-   ##
==========================================
- Coverage   84.10%   84.06%   -0.04%     
==========================================
  Files         191      191              
  Lines       29579    29606      +27     
==========================================
+ Hits        24876    24887      +11     
- Misses       4703     4719      +16     

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@myskyko

myskyko commented Oct 14, 2026

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Thank you for the PR. Why don't we use create_nor and create_xnor? Probably we don't need the function description comment for this file.

mig_network has no create_xnor and klut_network has neither, so fall back to create_not of create_or/create_xor when has_create_nor_v / has_create_xnor_v is false.
@vera-rubin

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Thanks! Done: it now uses create_nor/create_xnor when the network provides them and falls back for networks that don't (mig_network has no create_xnor, klut_network has neither). I also dropped the function comments.

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Verilog reader imports NOR and XNOR assignments as constant zero

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