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Multi-group CachePool with coherence-free write-through private L1 cache #24
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4c73e96
init
d1dcb95
[HW] init L1 private cache controller
1471b1a
[HW] init L1 private cache controller
e9c5785
[HW] init l1 ctrl and comitter overwrite
HHT1228 94e5c68
unknown reason conflict fix
HHT1228 b9e916a
private L1 defs and configs
HHT1228 8ae8f13
[HW] L1 instantiate, upstream wiring, and tile_id handling
HHT1228 b3f9d58
[HW] tile cache interco collapse, and adjustment at group-level
HHT1228 b19ab82
[HW] SRAM datawidth matching and noc wrapper adjustments
HHT1228 79c44e9
Private L1 bender and dep setup and portid_t matching, sim clear
HHT1228 41a4a29
[Periph] Clean up unused register.
DiyouS 2dbe169
[SW] Remove unused runtime functions
DiyouS 75080d8
[Lint] Fix some small linting issues and adjust L2 ICache size.
DiyouS 79d5281
[MISC] Clean up Makefile and change the test size for load-store test.
DiyouS c154ed1
[CFG] Add a 4x4 smaller configuration for faster testing
DiyouS 3dd812e
[CFG] tiny config setup
HHT1228 39dc1dc
[SW] simple kernels to test private L1 functions
HHT1228 a452ce8
[CFG][SW] init 4x4 mesh build; replacement/refill sw test
HHT1228 08db94b
[HW] init AMO support impl
HHT1228 44e36f8
[HW] shared D$ AMO support impl
HHT1228 77683f1
[SW] amo sanity test
HHT1228 cbe237a
[HW] hpdcache memIdWidth match with reqid_t
HHT1228 876a581
[SW] LRSC amo test
HHT1228 896e748
[HW] peripheral reg, port extension, and FSM for private L1 CMO
HHT1228 69ee3d1
[SW] private L1 CMO runtime, spin-lock and multi-spin-lock passed
HHT1228 7ae5cf6
[SW] MCS lock protection for non-coherence L1
HHT1228 67af6c8
[SW] fdotp reduction protection for private L1
HHT1228 ef0d64d
[HW] CMO periph reg parameterize (follow total core num)
HHT1228 8d42ee6
[SW] init FFT coherence protection
HHT1228 fd06fda
[SW] FFT data generation change from .pdcp_src to .data (DRAM)
HHT1228 6233342
MATMUL access misalignment fix
HHT1228 8f87b20
[SW] gemv protection and fix
HHT1228 3845add
[SW] fmamtul data alignment, def flag clean up for multiple kernels
HHT1228 3711453
[HW] private L1 byte-enable fix
HHT1228 546a399
Code clean-up and composed a note
HHT1228 9de023c
note adjust
HHT1228 34f053b
[SW HW] re-route private L1 CMOs from peripheral to snitch CSR
HHT1228 f1890c2
[HW Bender Makefile] Periph-related clean-up and remove bender local …
HHT1228 324fa10
[Bender] bender.lock local dep replaced
HHT1228 566dec5
[HW] HW code clean-up and cachepool_hpd_pkg created
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
|
|
@@ -32,7 +32,7 @@ packages: | |
| dependencies: | ||
| - common_cells | ||
| cluster_icache: | ||
| revision: ce0ed94a5b95f5c76b9fa51940303fcce53f56e5 | ||
| revision: 8e574182b1ed125ec1ed1ec7f1ffc9c2096250b3 | ||
| version: null | ||
| source: | ||
| Git: https://github.com/pulp-platform/cluster_icache.git | ||
|
|
@@ -42,8 +42,8 @@ packages: | |
| - scm | ||
| - tech_cells_generic | ||
| common_cells: | ||
| revision: 9ca8a7655f741e7dd5736669a20a301325194c28 | ||
| version: 1.39.0 | ||
| revision: 1281545696eb3fcba50ec5b4275993476a3c710e | ||
|
Collaborator
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. any reason of switching to a new version? |
||
| version: 1.40.0 | ||
| source: | ||
| Git: https://github.com/pulp-platform/common_cells.git | ||
| dependencies: | ||
|
|
@@ -63,7 +63,7 @@ packages: | |
| dependencies: | ||
| - axi | ||
| floo_noc: | ||
| revision: 97306733f33acbb646c7e403c03a674fc1404b44 | ||
| revision: 9a6972a5f9b8117506d1df8a6505ce1da2bc9084 | ||
| version: null | ||
| source: | ||
| Git: https://github.com/pulp-platform/FlooNoC.git | ||
|
|
@@ -96,6 +96,12 @@ packages: | |
| Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git | ||
| dependencies: | ||
| - common_cells | ||
| hpdcache: | ||
|
DiyouS marked this conversation as resolved.
|
||
| revision: 957e6f9b30dd5516b57cca3326f3f32e4357cf1b | ||
| version: null | ||
| source: | ||
| Git: https://github.com/HHT1228/cv-hpdcache.git | ||
| dependencies: [] | ||
| idma: | ||
| revision: 28a36e5e07705549e59fc33db96ab681bc1ca88e | ||
| version: 0.6.5 | ||
|
|
@@ -109,10 +115,10 @@ packages: | |
| - obi | ||
| - register_interface | ||
| insitu-cache: | ||
| revision: fa761ddebc946f9b46509d84945bf41ee1a9ec49 | ||
| revision: 129174e095db1f64136a02735ea9617dc2e29d6c | ||
| version: null | ||
| source: | ||
| Git: https://github.com/pulp-platform/Insitu-Cache.git | ||
| Git: https://github.com/HHT1228/Insitu-Cache.git | ||
| dependencies: | ||
| - axi | ||
| - common_cells | ||
|
|
@@ -150,10 +156,10 @@ packages: | |
| dependencies: | ||
| - tech_cells_generic | ||
| spatz: | ||
| revision: 944e9042379fbe1db69567655cffd7a2e260ff16 | ||
| revision: 6170425f91422aa1daa3b9d8e34cda41f2c05b32 | ||
| version: null | ||
| source: | ||
| Git: https://github.com/pulp-platform/spatz.git | ||
| Git: https://github.com/HHT1228/spatz.git | ||
| dependencies: | ||
| - axi | ||
| - axi_riscv_atomics | ||
|
|
@@ -165,8 +171,8 @@ packages: | |
| - riscv-dbg | ||
| - tech_cells_generic | ||
| tech_cells_generic: | ||
| revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf | ||
| version: 0.2.13 | ||
| revision: 3a3de73632a06826b1bd9c65a0a2e92b32016845 | ||
| version: 0.2.14 | ||
| source: | ||
| Git: https://github.com/pulp-platform/tech_cells_generic.git | ||
| dependencies: | ||
|
|
||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
|
|
@@ -16,8 +16,8 @@ CACHEPOOL_DIR := $(shell git rev-parse --show-toplevel 2>/dev/null || echo $$CAC | |
| SOFTWARE_DIR ?= ${CACHEPOOL_DIR}/software | ||
|
|
||
| # Host compilers (for DPI, simulators, tools) | ||
| CXX ?= /usr/pack/gcc-11.2.0-af/linux-x64/bin/g++ | ||
| CC ?= /usr/pack/gcc-11.2.0-af/linux-x64/bin/gcc | ||
| CXX := /usr/pack/gcc-11.2.0-af/linux-x64/bin/g++ | ||
| CC := /usr/pack/gcc-11.2.0-af/linux-x64/bin/gcc | ||
|
Collaborator
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Keep it |
||
| CXX_PATH ?= $(shell realpath -P $(CXX)) | ||
| CC_PATH ?= $(shell realpath -P $(CC)) | ||
| GCC_LIB ?= /usr/pack/gcc-11.2.0-af/linux-x64/lib64 | ||
|
|
@@ -147,7 +147,7 @@ $(BOOTROM_DIR)/bootdata.cc: $(SCRIPTS_DIR)/generate_bootdata.py $(HJSON_OUT) | |
| ${PYTHON} $< -c $(HJSON_OUT) -d $(BOOTROM_DIR) -t bootdata.cc.tpl -o $@ | ||
|
|
||
| $(BOOTROM_DIR)/bootrom.elf $(BOOTROM_DIR)/bootrom.dump $(BOOTROM_DIR)/bootrom.bin: \ | ||
| $(BOOTROM_DIR)/bootrom.S $(BOOTROM_DIR)/bootdata_bootrom.cc $(BOOTROM_DIR)/bootrom.ld Makefile | ||
| $(BOOTROM_DIR)/bootrom.S $(BOOTROM_DIR)/bootdata_bootrom.cc $(BOOTROM_DIR)/bootrom.ld | ||
| riscv -riscv64-gcc-9.5.0 riscv64-unknown-elf-gcc \ | ||
| -mabi=ilp32 -march=rv32imaf -static -nostartfiles \ | ||
| -T$(BOOTROM_DIR)/bootrom.ld \ | ||
|
|
@@ -195,7 +195,7 @@ VSIM_FLAGS := | |
| VSIM_BENDER = | ||
|
|
||
| .PHONY: dram-build | ||
| dram-build: $(DRAMSYS_PATH)/README.md dram-clean dram-config | ||
| dram-build: $(DRAMSYS_PATH)/README.md dram-config | ||
| cd $(DRAMSYS_PATH) && \ | ||
| if [ ! -d "build" ]; then \ | ||
| mkdir build && cd build; \ | ||
|
|
@@ -358,34 +358,29 @@ clean.data: | |
| clean.sw: | ||
| rm -rf ${SOFTWARE_DIR}/build | ||
|
|
||
| # Common CMake flags shared by sw and vsim targets. | ||
| # vsim appends -DSNITCH_SIMULATOR to point tests at the compiled binary. | ||
| SW_CMAKE_FLAGS = \ | ||
| -DENABLE_CACHEPOOL_TESTS=${ENABLE_CACHEPOOL_TESTS} \ | ||
| -DCACHEPOOL_DIR=$(CACHEPOOL_DIR) \ | ||
| -DRUNTIME_DIR=${SOFTWARE_DIR} \ | ||
| -DSPATZ_SW_DIR=$(SPATZ_SW_DIR) \ | ||
| -DLLVM_PATH=${LLVM_INSTALL_DIR} \ | ||
| -DGCC_PATH=${GCC_INSTALL_DIR} \ | ||
| -DPYTHON=${PYTHON} \ | ||
| -DBUILD_TESTS=ON | ||
|
|
||
| .PHONY: sw | ||
| sw: generate bootrom gen-data clean.sw | ||
| echo ${SOFTWARE_DIR} | ||
| sw: generate bootrom gen-data | ||
| mkdir -p ${SOFTWARE_DIR}/build | ||
| cd ${SOFTWARE_DIR}/build && ${CMAKE} \ | ||
| -DENABLE_CACHEPOOL_TESTS=${ENABLE_CACHEPOOL_TESTS} \ | ||
| -DCACHEPOOL_DIR=$(CACHEPOOL_DIR) \ | ||
| -DRUNTIME_DIR=${SOFTWARE_DIR} \ | ||
| -DSPATZ_SW_DIR=$(SPATZ_SW_DIR) \ | ||
| -DLLVM_PATH=${LLVM_INSTALL_DIR} \ | ||
| -DGCC_PATH=${GCC_INSTALL_DIR} \ | ||
| -DPYTHON=${PYTHON} \ | ||
| -DBUILD_TESTS=ON .. && $(MAKE) | ||
| cd ${SOFTWARE_DIR}/build && ${CMAKE} ${SW_CMAKE_FLAGS} .. && $(MAKE) | ||
|
|
||
| .PHONY: vsim | ||
| vsim: generate bootrom gen-data dpi ${SIMBIN_DIR}/cachepool_cluster.vsim | ||
| echo ${SOFTWARE_DIR} | ||
| mkdir -p ${SOFTWARE_DIR}/build | ||
| cd ${SOFTWARE_DIR}/build && ${CMAKE} \ | ||
| -DENABLE_CACHEPOOL_TESTS=${ENABLE_CACHEPOOL_TESTS} \ | ||
| -DCACHEPOOL_DIR=$(CACHEPOOL_DIR) \ | ||
| -DRUNTIME_DIR=${SOFTWARE_DIR} \ | ||
| -DSPATZ_SW_DIR=$(SPATZ_SW_DIR) \ | ||
| -DLLVM_PATH=${LLVM_INSTALL_DIR} \ | ||
| -DGCC_PATH=${GCC_INSTALL_DIR} \ | ||
| -DPYTHON=${PYTHON} \ | ||
| cd ${SOFTWARE_DIR}/build && ${CMAKE} ${SW_CMAKE_FLAGS} \ | ||
| -DSNITCH_SIMULATOR=${SIMBIN_DIR}/cachepool_cluster.vsim \ | ||
| -DBUILD_TESTS=ON .. && $(MAKE) | ||
| .. && $(MAKE) | ||
|
|
||
| .PHONY: clean | ||
| clean: clean.sw clean.vsim clean.data | ||
|
|
||
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