[zhen8838]

Why

• Supersedes fix(lowering,verify): bind each selected ring stage before an instruction uses it #276. Unbound ring views and stage selections reach CUDA operands without SSA names, and compilation entry points assemble different pass lists.

What

• Keep ring stages as a tuple of bound TensorViews and bind each selected stage once per consuming scope.
• Share default_pipeline across finalize, compile and scaffold. Resolve the core host-entry pass through Target.resolve, with CUDA supplying an @bind implementation.
• Make Module.entry the host starting point and carry analyzed shared-memory peaks into host launches.
• Link all CPU hosts on the call paths, with the root host first.

Contract

• Both InsertHostEntryPass.create(target, options) and ConvertHIRToTIR.create(target, options) support target-owned implementations.
• link_program removes entries; the loader binds the first linked host, and build requires a CPU host root.
• Full lowering requires memory-analysis metadata. ConvertHIRToTIR is a no-op for skeletons or modules without HIR; a CPU host root being lowered must launch exactly one HIR callee.

Risk

• fix(shard): canonicalize all-Broadcast layouts to plain layouts #278 tracks Broadcast layout normalization; the remaining layout-adaptation views are retained.
• refactor(parser,ir,analysis,codegen): finish the remaining work of twelve earlier issues #255 tracks SymbolRef/function references; indexed child entries remain excluded from synthesized hosts, and Launch type repair remains necessary.