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dispatch fix on single-packet inst #428

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dispatch fix on single-packet inst #428

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5 changes: 4 additions & 1 deletion hw/rtl/core/VX_lane_dispatch.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -64,6 +64,7 @@ module VX_lane_dispatch import VX_gpu_pkg::*; #(
assign dispatch_if[i].ready = dispatch_ready[i];
end

wire [BLOCK_SIZE-1:0] block_valid;
wire [BLOCK_SIZE-1:0] block_ready;
wire [BLOCK_SIZE-1:0][NUM_LANES-1:0] block_tmask;
wire [BLOCK_SIZE-1:0][2:0][NUM_LANES-1:0][`VX_CFG_XLEN-1:0] block_rsdata;
Expand Down Expand Up @@ -177,6 +178,7 @@ module VX_lane_dispatch import VX_gpu_pkg::*; #(
assign block_pid[block_idx] = start_p;
assign block_sop[block_idx] = is_first_p;
assign block_eop[block_idx] = is_last_p;
assign block_valid[block_idx] = valid_p;
assign block_ready[block_idx] = ready_p;
assign block_done[block_idx] = (fire_p && is_last_p) || ~dispatch_valid[issue_idx];
end else begin : g_full_simd
Expand All @@ -186,6 +188,7 @@ module VX_lane_dispatch import VX_gpu_pkg::*; #(
assign block_pid[block_idx] = 0;
assign block_sop[block_idx] = 1;
assign block_eop[block_idx] = 1;
assign block_valid[block_idx] = valid_p;
assign block_ready[block_idx] = ready_p;
assign block_done[block_idx] = ready_p || ~valid_p;
end
Expand Down Expand Up @@ -240,7 +243,7 @@ module VX_lane_dispatch import VX_gpu_pkg::*; #(
always @(*) begin
ready_in = 0;
for (integer block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin
ready_in[issue_indices[block_idx]] = block_ready[block_idx] && block_eop[block_idx];
ready_in[issue_indices[block_idx]] = block_valid[block_idx] && block_ready[block_idx] && block_eop[block_idx];
end
end
assign dispatch_ready = ready_in;
Expand Down
5 changes: 3 additions & 2 deletions hw/rtl/libs/VX_nz_iterator.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -73,9 +73,10 @@ module VX_nz_iterator #(
wire is_last_p = (start_p == end_p);

wire enable = valid_in && (~valid_out || next);
wire eop_out = valid_out && eop;

always @(posedge clk) begin
if (reset || (enable && (is_last_p || eop))) begin
if (reset || (enable && (is_last_p || eop_out))) begin
sent_mask_p <= '0;
is_first_p <= 1;
end else if (enable) begin
Expand All @@ -90,7 +91,7 @@ module VX_nz_iterator #(
.DEPTH (OUT_REG)
) pipe_reg (
.clk (clk),
.reset (reset || (enable && eop)),
.reset (reset || (enable && eop_out)),
.enable (enable),
.data_in ({valid_in, data_in[start_p], start_p, is_first_p, is_last_p}),
.data_out ({valid_out, data_out, pid, sop, eop})
Expand Down
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