Rv64 fixes

.gitignore

@@ -18,3 +18,7 @@ hw/syn/libs/asap7/verilog/
 hw/syn/libs/asap7/metadata/
 hw/syn/libs/asap7/.installed_*
 hw/syn/libs/asap7/install.sh
+
+# Built by third_party/Makefile
+third_party/ramulator_ext/*.o
+third_party/ramulator_ext/*.so

CHANGELOG.md

@@ -5,6 +5,25 @@ All notable changes to Vortex are documented here. The format is based on
 follows the version pins recorded in [VERSION](VERSION) (`VORTEX_VERSION`,
 `TOOLCHAIN_REV`, `GEM5_REV`).
 
+## [Unreleased]
+
+### Added
+
+- **Hardware profiles.** `profiles/<name>.json` names a machine (`tinygpu`, `rtx1080`, `v100`, `a100`, `h100`, `rtx5080`) that every flow
+  builds through `configure --profile=<name>` or `blackbox.sh --profile=<name>`; explicit `CONFIGS` win over the profile.
+  See [docs/simulation.md](docs/simulation.md#hardware-profiles).
+
+### Changed
+
+- **RV64 portability.** Device index math, DXA/OM addresses, pack-load strides, RTU scene/payload pointers and the ray log carry full
+  width on RV64 (`size_t`/`uintptr_t`, identical RV32 code); RTU slot reads into FP registers are NaN-boxed.
+- **Zero warnings restored.** Every C/C++ build (simulators, runtime, kernel library, tests, OpenCL/HIP/Vulkan apps) is `-Werror` and
+  Verilator warnings are fatal again, with the RTL and host code fixed to build clean.
+- **DRAM model redesign.** simx, rtlsim, opaesim and xrtsim model one independent Ramulator controller and device per memory bank
+  (JEDEC HBM2/HBM3/GDDR6 organization and nanosecond timing, 32 B bursts, permuted open-page bank interleave, per-channel
+  responses), configured from data-sheet values: `VX_CFG_PLATFORM_MEMORY_{TYPE,DATA_RATE,LATENCY,QUEUE_SIZE}`. The default machine
+  keeps its idle read latency (14/26 cycles open-row/conflict, was 13/27) and one-block-per-cycle peak.
+
 ## [3.0] — 2026-10-07
 
 The 3.0 release introduces a fixed-function graphics stack (rasterizer, texture units, and output mergers), tensor core structured sparsity (2:4), warpgroup-level matrix multiplication (WGMMA), global-to-local data transfer acceleration (DXA), a new hardware kernel scheduler (KMU) and Command Processor (CP) architecture, a new asynchronous runtime API (`vortex2.h`), asynchronous barriers with arrive/wait/event semantics, compressed instruction set (RVC) support, hardware atomics, an MMU/SV32 virtual memory stack, a Mesa/lavapipe Vulkan backend (`vortexpipe`), HIP via chipStar, gem5 integration, a SimX v3 TLM architecture with fixed-size handshake channels, productized Synopsys and Yosys ASIC synthesis flows, and a refreshed toolchain (LLVM 20, POCL 7.0). Build and configuration infrastructure was reworked: TOML-driven HW configuration ([VX_config.toml](VX_config.toml) + [VX_types.toml](VX_types.toml)) decoupling SimX/runtime from the RTL source tree, a `VX_CFG_` macro namespace that resolves toolchain preprocessor collisions, retirement of the global `toolchain_env.sh` to enable parallel multi-version Vortex worktrees on the same shell, consolidation of `kernel/`/`runtime/` under a shared `sw/` root, a single-source [VERSION](VERSION) file driving CI toolchain pinning, Perfetto trace export ([ci/perfetto.py](ci/perfetto.py)), and new top-level [AGENTS.md](AGENTS.md) + [CONTRIBUTING.md](CONTRIBUTING.md) for AI-agent and contributor workflows.

VX_config.toml

@@ -79,6 +79,17 @@ VX_CFG_PLATFORM_MEMORY_DATA_SIZE = 64
 VX_CFG_PLATFORM_MEMORY_INTERLEAVE = 1
 VX_CFG_PLATFORM_MEMORY_PEAK_BW = 460000 # 460 GB/s
 VX_CFG_PLATFORM_CLOCK_RATE = 400
+# DRAM the simulators model behind each memory bank (one channel per bank),
+# as a data sheet gives it: the JEDEC standard, its data rate (MT/s per pin),
+# the fixed read latency added for the PHY, controller and interconnect (core
+# cycles), and the requests a channel holds in flight (0 = unbounded).
+# Simulation-only: the RTL never reads them. The default clocks the DRAM with
+# the core: 14 cycles for an idle open-row read, 26 for a row conflict, one
+# 64 B block per cycle at peak; profiles set their own.
+VX_CFG_PLATFORM_MEMORY_TYPE = "HBM2"
+VX_CFG_PLATFORM_MEMORY_DATA_RATE = "expr: 2 * $VX_CFG_PLATFORM_CLOCK_RATE"
+VX_CFG_PLATFORM_MEMORY_LATENCY = 0
+VX_CFG_PLATFORM_MEMORY_QUEUE_SIZE = 0
 
 [alu]
 VX_CFG_NUM_ALU_LANES = "expr: $VX_CFG_SIMD_WIDTH"
@@ -456,6 +467,7 @@ VX_CFG_XLEN = [32, 64]
 VX_CFG_FLEN = [32, 64]
 VX_CFG_FPU_TYPE = ["DPI", "DSP", "FPNEW", "STD"]
 VX_CFG_TCU_TYPE = ["DPI", "DSP", "BHF", "TFR", "FPNEW"]
+VX_CFG_PLATFORM_MEMORY_TYPE = ["HBM2", "HBM3", "GDDR6"]
 
 [[param]]
 VX_CFG_DCACHE_NUM_REQS = "int"

VX_types.toml

@@ -442,6 +442,7 @@ VX_RT_STATUS                = 26      # per-lane VX_RT_STS_*; WAIT completes on
 # Every slot is written by the RTU and read by the shader; nothing else writes the
 # window. The payload pointer rides the arm doorbell (warp-uniform) and the
 # hitAttribute rides the CONTINUE, so both reach the RTU without a window write.
+# On RV64 the payload pointer's upper word follows in slot VX_RT_PAYLOAD_PTR_LO + 1.
 VX_RT_PAYLOAD_PTR_LO        = 27      # the tracing shader's payload; the callbacks read it
 VX_RT_HIT_ATTR_0            = 29      # user hitAttributeEXT (an IS shader returns it)
 

ci/baselines/perf/core.json

@@ -1,177 +1,177 @@
 {
   "core:raycast-nt16:rtlsim": {
     "32": {
-      "cycles": 568490,
+      "cycles": 563524,
       "instrs": 137486
     },
     "app": "raycast",
     "args": "",
-    "config_hash": "ee3a227211fa9942",
+    "config_hash": "396cee9df6025cdb",
     "configs": "-DVX_CFG_NUM_THREADS=16",
     "driver": "rtlsim"
   },
   "core:raycast-nt4:rtlsim": {
     "32": {
-      "cycles": 1495440,
+      "cycles": 1498642,
       "instrs": 259228
     },
     "app": "raycast",
     "args": "",
-    "config_hash": "c8b680eabeb18655",
+    "config_hash": "262f24032ef14b58",
     "configs": "-DVX_CFG_NUM_THREADS=4",
     "driver": "rtlsim"
   },
   "core:sgemm-mc-nt16:rtlsim": {
     "32": {
-      "cycles": 781696,
+      "cycles": 787850,
       "instrs": 623680
     },
     "app": "sgemm",
     "args": "-n128",
-    "config_hash": "58eb3cc06964207a",
+    "config_hash": "ad2b37492d761e8f",
     "configs": "-DVX_CFG_NUM_WARPS=8 -DVX_CFG_NUM_CORES=2 -DVX_CFG_NUM_THREADS=16 -DVX_CFG_L2_ENABLE",
     "driver": "rtlsim"
   },
   "core:sgemm-mc-nt4:rtlsim": {
     "32": {
-      "cycles": 2211340,
+      "cycles": 2239426,
       "instrs": 2494528
     },
     "app": "sgemm",
     "args": "-n128",
-    "config_hash": "aa6f26c7306417a8",
+    "config_hash": "606d011dc6f612d3",
     "configs": "-DVX_CFG_NUM_WARPS=8 -DVX_CFG_NUM_CORES=2 -DVX_CFG_NUM_THREADS=4 -DVX_CFG_L2_ENABLE",
     "driver": "rtlsim"
   },
   "core:sgemm-nt16:rtlsim": {
     "32": {
-      "cycles": 1823521,
+      "cycles": 1838654,
       "instrs": 623632
     },
     "app": "sgemm",
     "args": "-n128",
-    "config_hash": "b390d957eec8220f",
+    "config_hash": "9390754d3719fca3",
     "configs": "-DVX_CFG_NUM_THREADS=16",
     "driver": "rtlsim"
   },
   "core:sgemm-nt4:rtlsim": {
     "32": {
-      "cycles": 6055079,
+      "cycles": 5939731,
       "instrs": 2494480
     },
     "app": "sgemm",
     "args": "-n128",
-    "config_hash": "13d03df76d55105e",
+    "config_hash": "740fd84fa2938103",
     "configs": "-DVX_CFG_NUM_THREADS=4",
     "driver": "rtlsim"
   },
   "core:sgemmx-nt16:rtlsim": {
     "32": {
-      "cycles": 1297311,
+      "cycles": 1290130,
       "instrs": 266896
     },
     "app": "sgemmx",
     "args": "-n128",
-    "config_hash": "68638b6685801699",
+    "config_hash": "2e1c44e05f9ac34d",
     "configs": "-DVX_CFG_NUM_THREADS=16",
     "driver": "rtlsim"
   },
   "core:sgemmx-nt4:rtlsim": {
     "32": {
-      "cycles": 4210203,
+      "cycles": 4219466,
       "instrs": 1067536
     },
     "app": "sgemmx",
     "args": "-n128",
-    "config_hash": "837240be3049d62e",
+    "config_hash": "024adb49ed96bdd3",
     "configs": "-DVX_CFG_NUM_THREADS=4",
     "driver": "rtlsim"
   },
   "core:sgemv-nt16:rtlsim": {
     "32": {
-      "cycles": 633593,
-      "instrs": 79120
+      "cycles": 685107,
+      "instrs": 66800
     },
     "app": "sgemv",
     "args": "-m512 -n512",
-    "config_hash": "c6a3720118661bf7",
+    "config_hash": "a3d9df9695acbb95",
     "configs": "-DVX_CFG_NUM_THREADS=16",
     "driver": "rtlsim"
   },
   "core:sgemv-nt4:rtlsim": {
     "32": {
-      "cycles": 1060219,
-      "instrs": 316432
+      "cycles": 872926,
+      "instrs": 267152
     },
     "app": "sgemv",
     "args": "-m512 -n512",
-    "config_hash": "db6bb5af90ecc1a5",
+    "config_hash": "0e8990b25e64ad7f",
     "configs": "-DVX_CFG_NUM_THREADS=4",
     "driver": "rtlsim"
   },
   "core:softmax-nt16:rtlsim": {
     "32": {
-      "cycles": 1274656,
+      "cycles": 1272929,
       "instrs": 464089
     },
     "app": "softmax",
     "args": "-n64",
-    "config_hash": "1c0e7742deb14093",
+    "config_hash": "9e0c1c9767c760ea",
     "configs": "-DVX_CFG_NUM_THREADS=16",
     "driver": "rtlsim"
   },
   "core:softmax-nt4:rtlsim": {
     "32": {
-      "cycles": 4860631,
+      "cycles": 4860309,
       "instrs": 1789797
     },
     "app": "softmax",
     "args": "-n64",
-    "config_hash": "3797eecae3200315",
+    "config_hash": "eb5fed4bfce19d76",
     "configs": "-DVX_CFG_NUM_THREADS=4",
     "driver": "rtlsim"
   },
   "core:stencil3d-nt16:rtlsim": {
     "32": {
-      "cycles": 2388738,
+      "cycles": 2306960,
       "instrs": 892944
     },
     "app": "stencil3d",
     "args": "-n32",
-    "config_hash": "aa768c2a9c65b092",
+    "config_hash": "6925a5138be930ea",
     "configs": "-DVX_CFG_NUM_THREADS=16",
     "driver": "rtlsim"
   },
   "core:stencil3d-nt4:rtlsim": {
     "32": {
-      "cycles": 4177542,
+      "cycles": 4180969,
       "instrs": 1785872
     },
     "app": "stencil3d",
     "args": "-n32",
-    "config_hash": "5400d882a6c96ac1",
+    "config_hash": "b83a1e3735f79d39",
     "configs": "-DVX_CFG_NUM_THREADS=4",
     "driver": "rtlsim"
   },
   "core:vecadd-nt16:rtlsim": {
     "32": {
-      "cycles": 75714,
-      "instrs": 24592
+      "cycles": 100640,
+      "instrs": 29712
     },
     "app": "vecadd",
     "args": "-n16384",
-    "config_hash": "98b8bdc5e546ea62",
+    "config_hash": "ef0c2548e7c5bf86",
     "configs": "-DVX_CFG_NUM_THREADS=16",
     "driver": "rtlsim"
   },
   "core:vecadd-nt4:rtlsim": {
     "32": {
-      "cycles": 293078,
-      "instrs": 98320
+      "cycles": 367765,
+      "instrs": 118800
     },
     "app": "vecadd",
     "args": "-n16384",
-    "config_hash": "1510b8438164b252",
+    "config_hash": "ce1eb79984a98552",
     "configs": "-DVX_CFG_NUM_THREADS=4",
     "driver": "rtlsim"
   }